package/kernel/qca-ssdk/patches/102-qca-ssdk-support-selecting-PCS-channel-for-PORT3-on-.patch

   1 From 0116bb7359bd99c09bcad1b2051652cd1a04be3f Mon Sep 17 00:00:00 2001
   2 From: Mantas Pucka <mantas@8devices.com>
   3 Date: Mon, 12 Feb 2024 14:23:04 +0200
   4 Subject: [PATCH] qca-ssdk: support selecting PCS channel for PORT3 on IPQ6018
   5
   6 When QCA8072 is used in PSGMII mode with IPQ6018, PCS used for second
   7 PHY port would overlap with one used by SGMII+ port. SoC has register
   8 to select different PCS in such case.
   9
  10 Original code used PHY_ID for this decision, which also had other
  11 issues, but is no longer viable since we moved to upstream QCA807x
  12 driver.
  13
  14 Introduce DT property port3_pcs_channel to allow describing this in DT.
  15 Default value is <2>, and for some QCA8072 designs <4> would be needed.
  16
  17 Signed-off-by: Mantas Pucka <mantas@8devices.com>
  18 ---
  19  include/init/ssdk_dts.h            |  2 ++
  20  src/adpt/cppe/adpt_cppe_portctrl.c |  4 ++--
  21  src/adpt/hppe/adpt_hppe_uniphy.c   |  7 +------
  22  src/init/ssdk_dts.c                | 27 +++++++++++++++++++++++++++
  23  4 files changed, 32 insertions(+), 8 deletions(-)
  24
  25 --- a/include/init/ssdk_dts.h
  26 +++ b/include/init/ssdk_dts.h
  27 @@ -101,6 +101,7 @@ typedef struct
  28         a_uint32_t emu_chip_ver; /*only valid when is_emulation is true*/
  29         a_uint32_t clk_mode;
  30         a_uint32_t pcie_hw_base;
  31 +       a_uint32_t port3_pcs_channel;
  32  } ssdk_dt_cfg;
  33
  34  #define SSDK_MAX_NR_ETH 6
  35 @@ -162,6 +163,7 @@ a_uint32_t ssdk_device_id_get(a_uint32_t
  36  struct device_node *ssdk_dts_node_get(a_uint32_t dev_id);
  37  struct clk *ssdk_dts_essclk_get(a_uint32_t dev_id);
  38  struct clk *ssdk_dts_cmnclk_get(a_uint32_t dev_id);
  39 +a_uint32_t ssdk_dts_port3_pcs_channel_get(a_uint32_t dev_id);
  40
  41  int ssdk_switch_device_num_init(void);
  42  void ssdk_switch_device_num_exit(void);
  43 --- a/src/adpt/cppe/adpt_cppe_portctrl.c
  44 +++ b/src/adpt/cppe/adpt_cppe_portctrl.c
  45 @@ -33,6 +33,7 @@
  46  #include "hsl_phy.h"
  47  #include "hsl_port_prop.h"
  48  #include "hppe_init.h"
  49 +#include "ssdk_dts.h"
  50  #include "adpt.h"
  51  #include "adpt_hppe.h"
  52  #include "adpt_cppe_portctrl.h"
  53 @@ -60,8 +61,7 @@ _adpt_cppe_port_mux_mac_set(a_uint32_t d
  54                 case SSDK_PHYSICAL_PORT3:
  55                 case SSDK_PHYSICAL_PORT4:
  56                         if (mode0 == PORT_WRAPPER_PSGMII) {
  57 -                               if (hsl_port_phyid_get(dev_id,
  58 -                                       SSDK_PHYSICAL_PORT3) == MALIBU2PORT_PHY) {
  59 +                               if (ssdk_dts_port3_pcs_channel_get(dev_id) == 4) {
  60                                         cppe_port_mux_ctrl.bf.port3_pcs_sel =
  61                                                 CPPE_PORT3_PCS_SEL_PCS0_CHANNEL4;
  62                                         cppe_port_mux_ctrl.bf.port4_pcs_sel =
  63 --- a/src/adpt/hppe/adpt_hppe_uniphy.c
  64 +++ b/src/adpt/hppe/adpt_hppe_uniphy.c
  65 @@ -1122,9 +1122,6 @@ __adpt_hppe_uniphy_psgmii_mode_set(a_uin
  66  {
  67         a_uint32_t i;
  68         sw_error_t rv = SW_OK;
  69 -#if defined(CPPE)
  70 -       a_uint32_t phy_type = 0;
  71 -#endif
  72
  73         union uniphy_mode_ctrl_u uniphy_mode_ctrl;
  74
  75 @@ -1134,9 +1131,7 @@ __adpt_hppe_uniphy_psgmii_mode_set(a_uin
  76         SSDK_DEBUG("uniphy %d is psgmii mode\n", uniphy_index);
  77  #if defined(CPPE)
  78         if (adpt_ppe_type_get(dev_id) == CPPE_TYPE) {
  79 -               phy_type = hsl_port_phyid_get(dev_id,
  80 -                               SSDK_PHYSICAL_PORT3);
  81 -               if (phy_type == MALIBU2PORT_PHY) {
  82 +               if (ssdk_dts_port3_pcs_channel_get(dev_id) == 4) {
  83                         SSDK_INFO("cypress uniphy %d is qca8072 psgmii mode\n", uniphy_index);
  84                         rv = __adpt_cppe_uniphy_mode_set(dev_id, uniphy_index,
  85                                 PORT_WRAPPER_PSGMII);
  86 --- a/src/init/ssdk_dts.c
  87 +++ b/src/init/ssdk_dts.c
  88 @@ -272,6 +272,13 @@ struct clk *ssdk_dts_cmnclk_get(a_uint32
  89         return cfg->cmnblk_clk;
  90  }
  91
  92 +a_uint32_t ssdk_dts_port3_pcs_channel_get(a_uint32_t dev_id)
  93 +{
  94 +       ssdk_dt_cfg* cfg = ssdk_dt_global.ssdk_dt_switch_nodes[dev_id];
  95 +
  96 +       return cfg->port3_pcs_channel;
  97 +}
  98 +
  99  #ifndef BOARD_AR71XX
 100  #if defined(CONFIG_OF) && (LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0))
 101  static void ssdk_dt_parse_mac_mode(a_uint32_t dev_id,
 102 @@ -306,6 +313,25 @@ static void ssdk_dt_parse_mac_mode(a_uin
 103
 104         return;
 105  }
 106 +
 107 +static void ssdk_dt_parse_port3_pcs_channel(a_uint32_t dev_id,
 108 +               struct device_node *switch_node, ssdk_init_cfg *cfg)
 109 +{
 110 +       const __be32 *port3_pcs_channel;
 111 +       a_uint32_t len = 0;
 112 +
 113 +       port3_pcs_channel = of_get_property(switch_node, "port3_pcs_channel", &len);
 114 +       if (!port3_pcs_channel) {
 115 +               ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->port3_pcs_channel = 2;
 116 +       }
 117 +       else {
 118 +               ssdk_dt_global.ssdk_dt_switch_nodes[dev_id]->port3_pcs_channel =
 119 +                       be32_to_cpup(port3_pcs_channel);
 120 +       }
 121 +
 122 +       return;
 123 +}
 124 +
 125  #ifdef IN_UNIPHY
 126  static void ssdk_dt_parse_uniphy(a_uint32_t dev_id)
 127  {
 128 @@ -1292,6 +1318,7 @@ sw_error_t ssdk_dt_parse(ssdk_init_cfg *
 129         rv = ssdk_dt_parse_access_mode(switch_node, ssdk_dt_priv);
 130         SW_RTN_ON_ERROR(rv);
 131         ssdk_dt_parse_mac_mode(*dev_id, switch_node, cfg);
 132 +       ssdk_dt_parse_port3_pcs_channel(*dev_id, switch_node, cfg);
 133         ssdk_dt_parse_mdio(*dev_id, switch_node, cfg);
 134         ssdk_dt_parse_port_bmp(*dev_id, switch_node, cfg);
 135         ssdk_dt_parse_interrupt(*dev_id, switch_node);