target/linux/bmips/files/drivers/net/ethernet/broadcom/bcm6368-enetsw.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * BCM6368 Ethernet Switch Controller Driver
   4  *
   5  * Copyright (C) 2021 Álvaro Fernández Rojas <noltari@gmail.com>
   6  * Copyright (C) 2015 Jonas Gorski <jonas.gorski@gmail.com>
   7  * Copyright (C) 2008 Maxime Bizon <mbizon@freebox.fr>
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/delay.h>
  12 #include <linux/dma-mapping.h>
  13 #include <linux/err.h>
  14 #include <linux/ethtool.h>
  15 #include <linux/if_vlan.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/of_clk.h>
  18 #include <linux/of_net.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/pm_domain.h>
  21 #include <linux/pm_runtime.h>
  22 #include <linux/reset.h>
  23
  24 /* MTU */
  25 #define ENETSW_TAG_SIZE                 6
  26 #define ENETSW_MTU_OVERHEAD             (VLAN_ETH_HLEN + VLAN_HLEN + \
  27                                          ENETSW_TAG_SIZE)
  28 #define ENETSW_FRAG_SIZE(x)             (SKB_DATA_ALIGN(NET_SKB_PAD + x + \
  29                                          SKB_DATA_ALIGN(sizeof(struct skb_shared_info))))
  30
  31 /* default number of descriptor */
  32 #define ENETSW_DEF_RX_DESC              64
  33 #define ENETSW_DEF_TX_DESC              32
  34 #define ENETSW_DEF_CPY_BREAK            128
  35
  36 /* maximum burst len for dma (4 bytes unit) */
  37 #define ENETSW_DMA_MAXBURST             8
  38
  39 /* DMA channels */
  40 #define DMA_CHAN_WIDTH                  0x10
  41
  42 /* Controller Configuration Register */
  43 #define DMA_CFG_REG                     0x0
  44 #define DMA_CFG_EN_SHIFT                0
  45 #define DMA_CFG_EN_MASK                 (1 << DMA_CFG_EN_SHIFT)
  46 #define DMA_CFG_FLOWCH_MASK(x)          (1 << ((x >> 1) + 1))
  47
  48 /* Flow Control Descriptor Low Threshold register */
  49 #define DMA_FLOWCL_REG(x)               (0x4 + (x) * 6)
  50
  51 /* Flow Control Descriptor High Threshold register */
  52 #define DMA_FLOWCH_REG(x)               (0x8 + (x) * 6)
  53
  54 /* Flow Control Descriptor Buffer Alloca Threshold register */
  55 #define DMA_BUFALLOC_REG(x)             (0xc + (x) * 6)
  56 #define DMA_BUFALLOC_FORCE_SHIFT        31
  57 #define DMA_BUFALLOC_FORCE_MASK         (1 << DMA_BUFALLOC_FORCE_SHIFT)
  58
  59 /* Channel Configuration register */
  60 #define DMAC_CHANCFG_REG                0x0
  61 #define DMAC_CHANCFG_EN_SHIFT           0
  62 #define DMAC_CHANCFG_EN_MASK            (1 << DMAC_CHANCFG_EN_SHIFT)
  63 #define DMAC_CHANCFG_PKTHALT_SHIFT      1
  64 #define DMAC_CHANCFG_PKTHALT_MASK       (1 << DMAC_CHANCFG_PKTHALT_SHIFT)
  65 #define DMAC_CHANCFG_BUFHALT_SHIFT      2
  66 #define DMAC_CHANCFG_BUFHALT_MASK       (1 << DMAC_CHANCFG_BUFHALT_SHIFT)
  67 #define DMAC_CHANCFG_CHAINING_SHIFT     2
  68 #define DMAC_CHANCFG_CHAINING_MASK      (1 << DMAC_CHANCFG_CHAINING_SHIFT)
  69 #define DMAC_CHANCFG_WRAP_EN_SHIFT      3
  70 #define DMAC_CHANCFG_WRAP_EN_MASK       (1 << DMAC_CHANCFG_WRAP_EN_SHIFT)
  71 #define DMAC_CHANCFG_FLOWC_EN_SHIFT     4
  72 #define DMAC_CHANCFG_FLOWC_EN_MASK      (1 << DMAC_CHANCFG_FLOWC_EN_SHIFT)
  73
  74 /* Interrupt Control/Status register */
  75 #define DMAC_IR_REG                     0x4
  76 #define DMAC_IR_BUFDONE_MASK            (1 << 0)
  77 #define DMAC_IR_PKTDONE_MASK            (1 << 1)
  78 #define DMAC_IR_NOTOWNER_MASK           (1 << 2)
  79
  80 /* Interrupt Mask register */
  81 #define DMAC_IRMASK_REG                 0x8
  82
  83 /* Maximum Burst Length */
  84 #define DMAC_MAXBURST_REG               0xc
  85
  86 /* Ring Start Address register */
  87 #define DMAS_RSTART_REG                 0x0
  88
  89 /* State Ram Word 2 */
  90 #define DMAS_SRAM2_REG                  0x4
  91
  92 /* State Ram Word 3 */
  93 #define DMAS_SRAM3_REG                  0x8
  94
  95 /* State Ram Word 4 */
  96 #define DMAS_SRAM4_REG                  0xc
  97
  98 struct bcm6368_enetsw_desc {
  99         u32 len_stat;
 100         u32 address;
 101 };
 102
 103 /* control */
 104 #define DMADESC_LENGTH_SHIFT            16
 105 #define DMADESC_LENGTH_MASK             (0xfff << DMADESC_LENGTH_SHIFT)
 106 #define DMADESC_OWNER_MASK              (1 << 15)
 107 #define DMADESC_EOP_MASK                (1 << 14)
 108 #define DMADESC_SOP_MASK                (1 << 13)
 109 #define DMADESC_ESOP_MASK               (DMADESC_EOP_MASK | DMADESC_SOP_MASK)
 110 #define DMADESC_WRAP_MASK               (1 << 12)
 111 #define DMADESC_USB_NOZERO_MASK         (1 << 1)
 112 #define DMADESC_USB_ZERO_MASK           (1 << 0)
 113
 114 /* status */
 115 #define DMADESC_UNDER_MASK              (1 << 9)
 116 #define DMADESC_APPEND_CRC              (1 << 8)
 117 #define DMADESC_OVSIZE_MASK             (1 << 4)
 118 #define DMADESC_RXER_MASK               (1 << 2)
 119 #define DMADESC_CRC_MASK                (1 << 1)
 120 #define DMADESC_OV_MASK                 (1 << 0)
 121 #define DMADESC_ERR_MASK                (DMADESC_UNDER_MASK | \
 122                                          DMADESC_OVSIZE_MASK | \
 123                                          DMADESC_RXER_MASK | \
 124                                          DMADESC_CRC_MASK | \
 125                                          DMADESC_OV_MASK)
 126
 127 struct bcm6368_enetsw {
 128         void __iomem *dma_base;
 129         void __iomem *dma_chan;
 130         void __iomem *dma_sram;
 131
 132         struct device **pm;
 133         struct device_link **link_pm;
 134         int num_pms;
 135
 136         struct clk **clock;
 137         unsigned int num_clocks;
 138
 139         struct reset_control **reset;
 140         unsigned int num_resets;
 141
 142         int copybreak;
 143
 144         int irq_rx;
 145         int irq_tx;
 146
 147         /* hw view of rx & tx dma ring */
 148         dma_addr_t rx_desc_dma;
 149         dma_addr_t tx_desc_dma;
 150
 151         /* allocated size (in bytes) for rx & tx dma ring */
 152         unsigned int rx_desc_alloc_size;
 153         unsigned int tx_desc_alloc_size;
 154
 155         struct napi_struct napi;
 156
 157         /* dma channel id for rx */
 158         int rx_chan;
 159
 160         /* number of dma desc in rx ring */
 161         int rx_ring_size;
 162
 163         /* cpu view of rx dma ring */
 164         struct bcm6368_enetsw_desc *rx_desc_cpu;
 165
 166         /* current number of armed descriptor given to hardware for rx */
 167         int rx_desc_count;
 168
 169         /* next rx descriptor to fetch from hardware */
 170         int rx_curr_desc;
 171
 172         /* next dirty rx descriptor to refill */
 173         int rx_dirty_desc;
 174
 175         /* size of allocated rx buffer */
 176         unsigned int rx_buf_size;
 177
 178         /* size of allocated rx frag */
 179         unsigned int rx_frag_size;
 180
 181         /* list of buffer given to hw for rx */
 182         unsigned char **rx_buf;
 183
 184         /* used when rx buffer allocation failed, so we defer rx queue
 185          * refill */
 186         struct timer_list rx_timeout;
 187
 188         /* lock rx_timeout against rx normal operation */
 189         spinlock_t rx_lock;
 190
 191         /* dma channel id for tx */
 192         int tx_chan;
 193
 194         /* number of dma desc in tx ring */
 195         int tx_ring_size;
 196
 197         /* maximum dma burst size */
 198         int dma_maxburst;
 199
 200         /* cpu view of rx dma ring */
 201         struct bcm6368_enetsw_desc *tx_desc_cpu;
 202
 203         /* number of available descriptor for tx */
 204         int tx_desc_count;
 205
 206         /* next tx descriptor avaiable */
 207         int tx_curr_desc;
 208
 209         /* next dirty tx descriptor to reclaim */
 210         int tx_dirty_desc;
 211
 212         /* list of skb given to hw for tx */
 213         struct sk_buff **tx_skb;
 214
 215         /* lock used by tx reclaim and xmit */
 216         spinlock_t tx_lock;
 217
 218         /* network device reference */
 219         struct net_device *net_dev;
 220
 221         /* platform device reference */
 222         struct platform_device *pdev;
 223
 224         /* dma channel enable mask */
 225         u32 dma_chan_en_mask;
 226
 227         /* dma channel interrupt mask */
 228         u32 dma_chan_int_mask;
 229
 230         /* dma channel width */
 231         unsigned int dma_chan_width;
 232 };
 233
 234 static inline void dma_writel(struct bcm6368_enetsw *priv, u32 val, u32 off)
 235 {
 236         __raw_writel(val, priv->dma_base + off);
 237 }
 238
 239 static inline u32 dma_readl(struct bcm6368_enetsw *priv, u32 off, int chan)
 240 {
 241         return __raw_readl(priv->dma_chan + off + chan * priv->dma_chan_width);
 242 }
 243
 244 static inline void dmac_writel(struct bcm6368_enetsw *priv, u32 val,
 245                                     u32 off, int chan)
 246 {
 247         __raw_writel(val, priv->dma_chan + off + chan * priv->dma_chan_width);
 248 }
 249
 250 static inline void dmas_writel(struct bcm6368_enetsw *priv, u32 val,
 251                                     u32 off, int chan)
 252 {
 253         __raw_writel(val, priv->dma_sram + off + chan * priv->dma_chan_width);
 254 }
 255
 256 /*
 257  * refill rx queue
 258  */
 259 static int bcm6368_enetsw_refill_rx(struct net_device *dev, bool napi_mode)
 260 {
 261         struct bcm6368_enetsw *priv = netdev_priv(dev);
 262
 263         while (priv->rx_desc_count < priv->rx_ring_size) {
 264                 struct bcm6368_enetsw_desc *desc;
 265                 int desc_idx;
 266                 u32 len_stat;
 267
 268                 desc_idx = priv->rx_dirty_desc;
 269                 desc = &priv->rx_desc_cpu[desc_idx];
 270
 271                 if (!priv->rx_buf[desc_idx]) {
 272                         unsigned char *buf;
 273                         dma_addr_t p;
 274
 275                         if (likely(napi_mode))
 276                                 buf = napi_alloc_frag(priv->rx_frag_size);
 277                         else
 278                                 buf = netdev_alloc_frag(priv->rx_frag_size);
 279
 280                         if (unlikely(!buf))
 281                                 break;
 282
 283                         p = dma_map_single(&priv->pdev->dev, buf + NET_SKB_PAD,
 284                                            priv->rx_buf_size, DMA_FROM_DEVICE);
 285                         if (unlikely(dma_mapping_error(&priv->pdev->dev, p))) {
 286                                 skb_free_frag(buf);
 287                                 break;
 288                         }
 289
 290                         priv->rx_buf[desc_idx] = buf;
 291                         desc->address = p;
 292                 }
 293
 294                 len_stat = priv->rx_buf_size << DMADESC_LENGTH_SHIFT;
 295                 len_stat |= DMADESC_OWNER_MASK;
 296                 if (priv->rx_dirty_desc == priv->rx_ring_size - 1) {
 297                         len_stat |= DMADESC_WRAP_MASK;
 298                         priv->rx_dirty_desc = 0;
 299                 } else {
 300                         priv->rx_dirty_desc++;
 301                 }
 302                 wmb();
 303                 desc->len_stat = len_stat;
 304
 305                 priv->rx_desc_count++;
 306
 307                 /* tell dma engine we allocated one buffer */
 308                 dma_writel(priv, 1, DMA_BUFALLOC_REG(priv->rx_chan));
 309         }
 310
 311         /* If rx ring is still empty, set a timer to try allocating
 312          * again at a later time. */
 313         if (priv->rx_desc_count == 0 && netif_running(dev)) {
 314                 dev_warn(&priv->pdev->dev, "unable to refill rx ring\n");
 315                 priv->rx_timeout.expires = jiffies + HZ;
 316                 add_timer(&priv->rx_timeout);
 317         }
 318
 319         return 0;
 320 }
 321
 322 /*
 323  * timer callback to defer refill rx queue in case we're OOM
 324  */
 325 static void bcm6368_enetsw_refill_rx_timer(struct timer_list *t)
 326 {
 327         struct bcm6368_enetsw *priv = from_timer(priv, t, rx_timeout);
 328         struct net_device *dev = priv->net_dev;
 329
 330         spin_lock(&priv->rx_lock);
 331         bcm6368_enetsw_refill_rx(dev, false);
 332         spin_unlock(&priv->rx_lock);
 333 }
 334
 335 /*
 336  * extract packet from rx queue
 337  */
 338 static int bcm6368_enetsw_receive_queue(struct net_device *dev, int budget)
 339 {
 340         struct bcm6368_enetsw *priv = netdev_priv(dev);
 341         struct device *kdev = &priv->pdev->dev;
 342         struct list_head rx_list;
 343         struct sk_buff *skb;
 344         int processed = 0;
 345
 346         INIT_LIST_HEAD(&rx_list);
 347
 348         /* don't scan ring further than number of refilled
 349          * descriptor */
 350         if (budget > priv->rx_desc_count)
 351                 budget = priv->rx_desc_count;
 352
 353         do {
 354                 struct bcm6368_enetsw_desc *desc;
 355                 unsigned int frag_size;
 356                 unsigned char *buf;
 357                 int desc_idx;
 358                 u32 len_stat;
 359                 unsigned int len;
 360
 361                 desc_idx = priv->rx_curr_desc;
 362                 desc = &priv->rx_desc_cpu[desc_idx];
 363
 364                 /* make sure we actually read the descriptor status at
 365                  * each loop */
 366                 rmb();
 367
 368                 len_stat = desc->len_stat;
 369
 370                 /* break if dma ownership belongs to hw */
 371                 if (len_stat & DMADESC_OWNER_MASK)
 372                         break;
 373
 374                 processed++;
 375                 priv->rx_curr_desc++;
 376                 if (priv->rx_curr_desc == priv->rx_ring_size)
 377                         priv->rx_curr_desc = 0;
 378
 379                 /* if the packet does not have start of packet _and_
 380                  * end of packet flag set, then just recycle it */
 381                 if ((len_stat & DMADESC_ESOP_MASK) != DMADESC_ESOP_MASK) {
 382                         dev->stats.rx_dropped++;
 383                         continue;
 384                 }
 385
 386                 /* valid packet */
 387                 buf = priv->rx_buf[desc_idx];
 388                 len = (len_stat & DMADESC_LENGTH_MASK)
 389                       >> DMADESC_LENGTH_SHIFT;
 390                 /* don't include FCS */
 391                 len -= 4;
 392
 393                 if (len < priv->copybreak) {
 394                         unsigned int nfrag_size = ENETSW_FRAG_SIZE(len);
 395                         unsigned char *nbuf = napi_alloc_frag(nfrag_size);
 396
 397                         if (unlikely(!nbuf)) {
 398                                 /* forget packet, just rearm desc */
 399                                 dev->stats.rx_dropped++;
 400                                 continue;
 401                         }
 402
 403                         dma_sync_single_for_cpu(kdev, desc->address,
 404                                                 len, DMA_FROM_DEVICE);
 405                         memcpy(nbuf + NET_SKB_PAD, buf + NET_SKB_PAD, len);
 406                         dma_sync_single_for_device(kdev, desc->address,
 407                                                    len, DMA_FROM_DEVICE);
 408                         buf = nbuf;
 409                         frag_size = nfrag_size;
 410                 } else {
 411                         dma_unmap_single(kdev, desc->address,
 412                                          priv->rx_buf_size, DMA_FROM_DEVICE);
 413                         priv->rx_buf[desc_idx] = NULL;
 414                         frag_size = priv->rx_frag_size;
 415                 }
 416
 417                 skb = napi_build_skb(buf, frag_size);
 418                 if (unlikely(!skb)) {
 419                         skb_free_frag(buf);
 420                         dev->stats.rx_dropped++;
 421                         continue;
 422                 }
 423
 424                 skb_reserve(skb, NET_SKB_PAD);
 425                 skb_put(skb, len);
 426                 dev->stats.rx_packets++;
 427                 dev->stats.rx_bytes += len;
 428                 list_add_tail(&skb->list, &rx_list);
 429         } while (processed < budget);
 430
 431         list_for_each_entry(skb, &rx_list, list)
 432                 skb->protocol = eth_type_trans(skb, dev);
 433         netif_receive_skb_list(&rx_list);
 434         priv->rx_desc_count -= processed;
 435
 436         if (processed || !priv->rx_desc_count) {
 437                 bcm6368_enetsw_refill_rx(dev, true);
 438
 439                 /* kick rx dma */
 440                 dmac_writel(priv, priv->dma_chan_en_mask,
 441                             DMAC_CHANCFG_REG, priv->rx_chan);
 442         }
 443
 444         return processed;
 445 }
 446
 447 /*
 448  * try to or force reclaim of transmitted buffers
 449  */
 450 static int bcm6368_enetsw_tx_reclaim(struct net_device *dev, int force,
 451                                      int budget)
 452 {
 453         struct bcm6368_enetsw *priv = netdev_priv(dev);
 454         unsigned int bytes = 0;
 455         int released = 0;
 456
 457         while (priv->tx_desc_count < priv->tx_ring_size) {
 458                 struct bcm6368_enetsw_desc *desc;
 459                 struct sk_buff *skb;
 460
 461                 /* We run in a bh and fight against start_xmit, which
 462                  * is called with bh disabled */
 463                 spin_lock(&priv->tx_lock);
 464
 465                 desc = &priv->tx_desc_cpu[priv->tx_dirty_desc];
 466
 467                 if (!force && (desc->len_stat & DMADESC_OWNER_MASK)) {
 468                         spin_unlock(&priv->tx_lock);
 469                         break;
 470                 }
 471
 472                 /* ensure other field of the descriptor were not read
 473                  * before we checked ownership */
 474                 rmb();
 475
 476                 skb = priv->tx_skb[priv->tx_dirty_desc];
 477                 priv->tx_skb[priv->tx_dirty_desc] = NULL;
 478                 dma_unmap_single(&priv->pdev->dev, desc->address, skb->len,
 479                                  DMA_TO_DEVICE);
 480
 481                 priv->tx_dirty_desc++;
 482                 if (priv->tx_dirty_desc == priv->tx_ring_size)
 483                         priv->tx_dirty_desc = 0;
 484                 priv->tx_desc_count++;
 485
 486                 spin_unlock(&priv->tx_lock);
 487
 488                 if (desc->len_stat & DMADESC_UNDER_MASK)
 489                         dev->stats.tx_errors++;
 490
 491                 bytes += skb->len;
 492                 napi_consume_skb(skb, budget);
 493                 released++;
 494         }
 495
 496         netdev_completed_queue(dev, released, bytes);
 497
 498         if (netif_queue_stopped(dev) && released)
 499                 netif_wake_queue(dev);
 500
 501         return released;
 502 }
 503
 504 /*
 505  * poll func, called by network core
 506  */
 507 static int bcm6368_enetsw_poll(struct napi_struct *napi, int budget)
 508 {
 509         struct bcm6368_enetsw *priv = container_of(napi, struct bcm6368_enetsw, napi);
 510         struct net_device *dev = priv->net_dev;
 511         int rx_work_done;
 512
 513         /* ack interrupts */
 514         dmac_writel(priv, priv->dma_chan_int_mask,
 515                          DMAC_IR_REG, priv->rx_chan);
 516         dmac_writel(priv, priv->dma_chan_int_mask,
 517                          DMAC_IR_REG, priv->tx_chan);
 518
 519         /* reclaim sent skb */
 520         bcm6368_enetsw_tx_reclaim(dev, 0, budget);
 521
 522         spin_lock(&priv->rx_lock);
 523         rx_work_done = bcm6368_enetsw_receive_queue(dev, budget);
 524         spin_unlock(&priv->rx_lock);
 525
 526         if (rx_work_done >= budget) {
 527                 /* rx queue is not yet empty/clean */
 528                 return rx_work_done;
 529         }
 530
 531         /* no more packet in rx/tx queue, remove device from poll
 532          * queue */
 533         napi_complete_done(napi, rx_work_done);
 534
 535         /* restore rx/tx interrupt */
 536         dmac_writel(priv, priv->dma_chan_int_mask,
 537                          DMAC_IRMASK_REG, priv->rx_chan);
 538         dmac_writel(priv, priv->dma_chan_int_mask,
 539                          DMAC_IRMASK_REG, priv->tx_chan);
 540
 541         return rx_work_done;
 542 }
 543
 544 /*
 545  * rx/tx dma interrupt handler
 546  */
 547 static irqreturn_t bcm6368_enetsw_isr_dma(int irq, void *dev_id)
 548 {
 549         struct net_device *dev = dev_id;
 550         struct bcm6368_enetsw *priv = netdev_priv(dev);
 551
 552         /* mask rx/tx interrupts */
 553         dmac_writel(priv, 0, DMAC_IRMASK_REG, priv->rx_chan);
 554         dmac_writel(priv, 0, DMAC_IRMASK_REG, priv->tx_chan);
 555
 556         napi_schedule(&priv->napi);
 557
 558         return IRQ_HANDLED;
 559 }
 560
 561 /*
 562  * tx request callback
 563  */
 564 static netdev_tx_t
 565 bcm6368_enetsw_start_xmit(struct sk_buff *skb, struct net_device *dev)
 566 {
 567         struct bcm6368_enetsw *priv = netdev_priv(dev);
 568         struct bcm6368_enetsw_desc *desc;
 569         u32 len_stat;
 570         netdev_tx_t ret;
 571         dma_addr_t p;
 572
 573         /* lock against tx reclaim */
 574         spin_lock(&priv->tx_lock);
 575
 576         /* make sure the tx hw queue is not full, should not happen
 577          * since we stop queue before it's the case */
 578         if (unlikely(!priv->tx_desc_count)) {
 579                 netif_stop_queue(dev);
 580                 dev_err(&priv->pdev->dev, "xmit called with no tx desc "
 581                         "available?\n");
 582                 ret = NETDEV_TX_BUSY;
 583                 goto out_unlock;
 584         }
 585
 586         /* pad small packets */
 587         if (skb->len < (ETH_ZLEN + ETH_FCS_LEN)) {
 588                 int needed = (ETH_ZLEN + ETH_FCS_LEN) - skb->len;
 589                 char *data;
 590
 591                 if (unlikely(skb_tailroom(skb) < needed)) {
 592                         struct sk_buff *nskb;
 593
 594                         nskb = skb_copy_expand(skb, 0, needed, GFP_ATOMIC);
 595                         if (!nskb) {
 596                                 ret = NETDEV_TX_BUSY;
 597                                 goto out_unlock;
 598                         }
 599
 600                         dev_kfree_skb(skb);
 601                         skb = nskb;
 602                 }
 603                 data = skb_put_zero(skb, needed);
 604         }
 605
 606         /* fill descriptor */
 607         p = dma_map_single(&priv->pdev->dev, skb->data, skb->len,
 608                            DMA_TO_DEVICE);
 609         if (unlikely(dma_mapping_error(&priv->pdev->dev, p))) {
 610                 dev_kfree_skb(skb);
 611                 ret = NETDEV_TX_OK;
 612                 goto out_unlock;
 613         }
 614
 615         /* point to the next available desc */
 616         desc = &priv->tx_desc_cpu[priv->tx_curr_desc];
 617         priv->tx_skb[priv->tx_curr_desc] = skb;
 618         desc->address = p;
 619
 620         len_stat = (skb->len << DMADESC_LENGTH_SHIFT) & DMADESC_LENGTH_MASK;
 621         len_stat |= DMADESC_ESOP_MASK | DMADESC_APPEND_CRC |
 622                     DMADESC_OWNER_MASK;
 623
 624         priv->tx_curr_desc++;
 625         if (priv->tx_curr_desc == priv->tx_ring_size) {
 626                 priv->tx_curr_desc = 0;
 627                 len_stat |= DMADESC_WRAP_MASK;
 628         }
 629         priv->tx_desc_count--;
 630
 631         /* dma might be already polling, make sure we update desc
 632          * fields in correct order */
 633         wmb();
 634         desc->len_stat = len_stat;
 635         wmb();
 636
 637         netdev_sent_queue(dev, skb->len);
 638
 639         /* kick tx dma */
 640         dmac_writel(priv, priv->dma_chan_en_mask, DMAC_CHANCFG_REG,
 641                     priv->tx_chan);
 642
 643         /* stop queue if no more desc available */
 644         if (!priv->tx_desc_count)
 645                 netif_stop_queue(dev);
 646
 647         dev->stats.tx_bytes += skb->len;
 648         dev->stats.tx_packets++;
 649         ret = NETDEV_TX_OK;
 650
 651 out_unlock:
 652         spin_unlock(&priv->tx_lock);
 653         return ret;
 654 }
 655
 656 /*
 657  * disable dma in given channel
 658  */
 659 static void bcm6368_enetsw_disable_dma(struct bcm6368_enetsw *priv, int chan)
 660 {
 661         int limit = 1000;
 662
 663         dmac_writel(priv, 0, DMAC_CHANCFG_REG, chan);
 664
 665         do {
 666                 u32 val;
 667
 668                 val = dma_readl(priv, DMAC_CHANCFG_REG, chan);
 669                 if (!(val & DMAC_CHANCFG_EN_MASK))
 670                         break;
 671
 672                 udelay(1);
 673         } while (limit--);
 674 }
 675
 676 static int bcm6368_enetsw_open(struct net_device *dev)
 677 {
 678         struct bcm6368_enetsw *priv = netdev_priv(dev);
 679         struct device *kdev = &priv->pdev->dev;
 680         int i, ret;
 681         unsigned int size;
 682         void *p;
 683         u32 val;
 684
 685         /* mask all interrupts and request them */
 686         dmac_writel(priv, 0, DMAC_IRMASK_REG, priv->rx_chan);
 687         dmac_writel(priv, 0, DMAC_IRMASK_REG, priv->tx_chan);
 688
 689         ret = request_irq(priv->irq_rx, bcm6368_enetsw_isr_dma,
 690                           0, dev->name, dev);
 691         if (ret)
 692                 goto out_freeirq;
 693
 694         if (priv->irq_tx != -1) {
 695                 ret = request_irq(priv->irq_tx, bcm6368_enetsw_isr_dma,
 696                                   0, dev->name, dev);
 697                 if (ret)
 698                         goto out_freeirq_rx;
 699         }
 700
 701         /* allocate rx dma ring */
 702         size = priv->rx_ring_size * sizeof(struct bcm6368_enetsw_desc);
 703         p = dma_alloc_coherent(kdev, size, &priv->rx_desc_dma, GFP_KERNEL);
 704         if (!p) {
 705                 dev_err(kdev, "cannot allocate rx ring %u\n", size);
 706                 ret = -ENOMEM;
 707                 goto out_freeirq_tx;
 708         }
 709
 710         memset(p, 0, size);
 711         priv->rx_desc_alloc_size = size;
 712         priv->rx_desc_cpu = p;
 713
 714         /* allocate tx dma ring */
 715         size = priv->tx_ring_size * sizeof(struct bcm6368_enetsw_desc);
 716         p = dma_alloc_coherent(kdev, size, &priv->tx_desc_dma, GFP_KERNEL);
 717         if (!p) {
 718                 dev_err(kdev, "cannot allocate tx ring\n");
 719                 ret = -ENOMEM;
 720                 goto out_free_rx_ring;
 721         }
 722
 723         memset(p, 0, size);
 724         priv->tx_desc_alloc_size = size;
 725         priv->tx_desc_cpu = p;
 726
 727         priv->tx_skb = kzalloc(sizeof(struct sk_buff *) * priv->tx_ring_size,
 728                                GFP_KERNEL);
 729         if (!priv->tx_skb) {
 730                 dev_err(kdev, "cannot allocate tx skb queue\n");
 731                 ret = -ENOMEM;
 732                 goto out_free_tx_ring;
 733         }
 734
 735         priv->tx_desc_count = priv->tx_ring_size;
 736         priv->tx_dirty_desc = 0;
 737         priv->tx_curr_desc = 0;
 738         spin_lock_init(&priv->tx_lock);
 739
 740         /* init & fill rx ring with buffers */
 741         priv->rx_buf = kzalloc(sizeof(unsigned char *) * priv->rx_ring_size,
 742                                GFP_KERNEL);
 743         if (!priv->rx_buf) {
 744                 dev_err(kdev, "cannot allocate rx buffer queue\n");
 745                 ret = -ENOMEM;
 746                 goto out_free_tx_skb;
 747         }
 748
 749         priv->rx_desc_count = 0;
 750         priv->rx_dirty_desc = 0;
 751         priv->rx_curr_desc = 0;
 752
 753         /* initialize flow control buffer allocation */
 754         dma_writel(priv, DMA_BUFALLOC_FORCE_MASK | 0,
 755                    DMA_BUFALLOC_REG(priv->rx_chan));
 756
 757         if (bcm6368_enetsw_refill_rx(dev, false)) {
 758                 dev_err(kdev, "cannot allocate rx buffer queue\n");
 759                 ret = -ENOMEM;
 760                 goto out;
 761         }
 762
 763         /* write rx & tx ring addresses */
 764         dmas_writel(priv, priv->rx_desc_dma,
 765                     DMAS_RSTART_REG, priv->rx_chan);
 766         dmas_writel(priv, priv->tx_desc_dma,
 767                     DMAS_RSTART_REG, priv->tx_chan);
 768
 769         /* clear remaining state ram for rx & tx channel */
 770         dmas_writel(priv, 0, DMAS_SRAM2_REG, priv->rx_chan);
 771         dmas_writel(priv, 0, DMAS_SRAM2_REG, priv->tx_chan);
 772         dmas_writel(priv, 0, DMAS_SRAM3_REG, priv->rx_chan);
 773         dmas_writel(priv, 0, DMAS_SRAM3_REG, priv->tx_chan);
 774         dmas_writel(priv, 0, DMAS_SRAM4_REG, priv->rx_chan);
 775         dmas_writel(priv, 0, DMAS_SRAM4_REG, priv->tx_chan);
 776
 777         /* set dma maximum burst len */
 778         dmac_writel(priv, priv->dma_maxburst,
 779                     DMAC_MAXBURST_REG, priv->rx_chan);
 780         dmac_writel(priv, priv->dma_maxburst,
 781                     DMAC_MAXBURST_REG, priv->tx_chan);
 782
 783         /* set flow control low/high threshold to 1/3 / 2/3 */
 784         val = priv->rx_ring_size / 3;
 785         dma_writel(priv, val, DMA_FLOWCL_REG(priv->rx_chan));
 786         val = (priv->rx_ring_size * 2) / 3;
 787         dma_writel(priv, val, DMA_FLOWCH_REG(priv->rx_chan));
 788
 789         /* all set, enable mac and interrupts, start dma engine and
 790          * kick rx dma channel
 791          */
 792         wmb();
 793         dma_writel(priv, DMA_CFG_EN_MASK, DMA_CFG_REG);
 794         dmac_writel(priv, DMAC_CHANCFG_EN_MASK,
 795                     DMAC_CHANCFG_REG, priv->rx_chan);
 796
 797         /* watch "packet transferred" interrupt in rx and tx */
 798         dmac_writel(priv, DMAC_IR_PKTDONE_MASK,
 799                     DMAC_IR_REG, priv->rx_chan);
 800         dmac_writel(priv, DMAC_IR_PKTDONE_MASK,
 801                     DMAC_IR_REG, priv->tx_chan);
 802
 803         /* make sure we enable napi before rx interrupt  */
 804         napi_enable(&priv->napi);
 805
 806         dmac_writel(priv, DMAC_IR_PKTDONE_MASK,
 807                     DMAC_IRMASK_REG, priv->rx_chan);
 808         dmac_writel(priv, DMAC_IR_PKTDONE_MASK,
 809                     DMAC_IRMASK_REG, priv->tx_chan);
 810
 811         netif_carrier_on(dev);
 812         netif_start_queue(dev);
 813
 814         return 0;
 815
 816 out:
 817         for (i = 0; i < priv->rx_ring_size; i++) {
 818                 struct bcm6368_enetsw_desc *desc;
 819
 820                 if (!priv->rx_buf[i])
 821                         continue;
 822
 823                 desc = &priv->rx_desc_cpu[i];
 824                 dma_unmap_single(kdev, desc->address, priv->rx_buf_size,
 825                                  DMA_FROM_DEVICE);
 826                 skb_free_frag(priv->rx_buf[i]);
 827         }
 828         kfree(priv->rx_buf);
 829
 830 out_free_tx_skb:
 831         kfree(priv->tx_skb);
 832
 833 out_free_tx_ring:
 834         dma_free_coherent(kdev, priv->tx_desc_alloc_size,
 835                           priv->tx_desc_cpu, priv->tx_desc_dma);
 836
 837 out_free_rx_ring:
 838         dma_free_coherent(kdev, priv->rx_desc_alloc_size,
 839                           priv->rx_desc_cpu, priv->rx_desc_dma);
 840
 841 out_freeirq_tx:
 842         if (priv->irq_tx != -1)
 843                 free_irq(priv->irq_tx, dev);
 844
 845 out_freeirq_rx:
 846         free_irq(priv->irq_rx, dev);
 847
 848 out_freeirq:
 849         return ret;
 850 }
 851
 852 static int bcm6368_enetsw_stop(struct net_device *dev)
 853 {
 854         struct bcm6368_enetsw *priv = netdev_priv(dev);
 855         struct device *kdev = &priv->pdev->dev;
 856         int i;
 857
 858         netif_stop_queue(dev);
 859         napi_disable(&priv->napi);
 860         del_timer_sync(&priv->rx_timeout);
 861
 862         /* mask all interrupts */
 863         dmac_writel(priv, 0, DMAC_IRMASK_REG, priv->rx_chan);
 864         dmac_writel(priv, 0, DMAC_IRMASK_REG, priv->tx_chan);
 865
 866         /* disable dma & mac */
 867         bcm6368_enetsw_disable_dma(priv, priv->tx_chan);
 868         bcm6368_enetsw_disable_dma(priv, priv->rx_chan);
 869
 870         /* force reclaim of all tx buffers */
 871         bcm6368_enetsw_tx_reclaim(dev, 1, 0);
 872
 873         /* free the rx buffer ring */
 874         for (i = 0; i < priv->rx_ring_size; i++) {
 875                 struct bcm6368_enetsw_desc *desc;
 876
 877                 if (!priv->rx_buf[i])
 878                         continue;
 879
 880                 desc = &priv->rx_desc_cpu[i];
 881                 dma_unmap_single_attrs(kdev, desc->address, priv->rx_buf_size,
 882                                        DMA_FROM_DEVICE,
 883                                        DMA_ATTR_SKIP_CPU_SYNC);
 884                 skb_free_frag(priv->rx_buf[i]);
 885         }
 886
 887         /* free remaining allocated memory */
 888         kfree(priv->rx_buf);
 889         kfree(priv->tx_skb);
 890         dma_free_coherent(kdev, priv->rx_desc_alloc_size,
 891                           priv->rx_desc_cpu, priv->rx_desc_dma);
 892         dma_free_coherent(kdev, priv->tx_desc_alloc_size,
 893                           priv->tx_desc_cpu, priv->tx_desc_dma);
 894         if (priv->irq_tx != -1)
 895                 free_irq(priv->irq_tx, dev);
 896         free_irq(priv->irq_rx, dev);
 897
 898         netdev_reset_queue(dev);
 899
 900         return 0;
 901 }
 902
 903 static const struct net_device_ops bcm6368_enetsw_ops = {
 904         .ndo_open = bcm6368_enetsw_open,
 905         .ndo_stop = bcm6368_enetsw_stop,
 906         .ndo_start_xmit = bcm6368_enetsw_start_xmit,
 907 };
 908
 909 static int bcm6368_enetsw_probe(struct platform_device *pdev)
 910 {
 911         struct bcm6368_enetsw *priv;
 912         struct device *dev = &pdev->dev;
 913         struct device_node *node = dev->of_node;
 914         struct net_device *ndev;
 915         struct resource *res;
 916         unsigned i;
 917         int ret;
 918
 919         ndev = alloc_etherdev(sizeof(*priv));
 920         if (!ndev)
 921                 return -ENOMEM;
 922
 923         priv = netdev_priv(ndev);
 924
 925         priv->num_pms = of_count_phandle_with_args(node, "power-domains",
 926                                                    "#power-domain-cells");
 927         if (priv->num_pms > 1) {
 928                 priv->pm = devm_kcalloc(dev, priv->num_pms,
 929                                         sizeof(struct device *), GFP_KERNEL);
 930                 if (!priv->pm)
 931                         return -ENOMEM;
 932
 933                 priv->link_pm = devm_kcalloc(dev, priv->num_pms,
 934                                              sizeof(struct device_link *),
 935                                              GFP_KERNEL);
 936                 if (!priv->link_pm)
 937                         return -ENOMEM;
 938
 939                 for (i = 0; i < priv->num_pms; i++) {
 940                         priv->pm[i] = genpd_dev_pm_attach_by_id(dev, i);
 941                         if (IS_ERR(priv->pm[i])) {
 942                                 dev_err(dev, "error getting pm %d\n", i);
 943                                 return -EINVAL;
 944                         }
 945
 946                         priv->link_pm[i] = device_link_add(dev, priv->pm[i],
 947                                 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME |
 948                                 DL_FLAG_RPM_ACTIVE);
 949                 }
 950         }
 951
 952         pm_runtime_enable(dev);
 953         pm_runtime_no_callbacks(dev);
 954         ret = pm_runtime_get_sync(dev);
 955         if (ret < 0) {
 956                 pm_runtime_disable(dev);
 957                 dev_info(dev, "PM prober defer: ret=%d\n", ret);
 958                 return -EPROBE_DEFER;
 959         }
 960
 961         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma");
 962         priv->dma_base = devm_ioremap_resource(dev, res);
 963         if (IS_ERR(priv->dma_base))
 964                 return PTR_ERR(priv->dma_base);
 965
 966         res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
 967                                            "dma-channels");
 968         priv->dma_chan = devm_ioremap_resource(dev, res);
 969         if (IS_ERR(priv->dma_chan))
 970                 return PTR_ERR(priv->dma_chan);
 971
 972         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dma-sram");
 973         priv->dma_sram = devm_ioremap_resource(dev, res);
 974         if (IS_ERR(priv->dma_sram))
 975                 return PTR_ERR(priv->dma_sram);
 976
 977         priv->irq_rx = platform_get_irq_byname(pdev, "rx");
 978         if (!priv->irq_rx)
 979                 return -ENODEV;
 980
 981         priv->irq_tx = platform_get_irq_byname(pdev, "tx");
 982         if (!priv->irq_tx)
 983                 return -ENODEV;
 984         else if (priv->irq_tx < 0)
 985                 priv->irq_tx = -1;
 986
 987         if (device_property_read_u32(dev, "dma-rx", &priv->rx_chan))
 988                 return -ENODEV;
 989
 990         if (device_property_read_u32(dev, "dma-tx", &priv->tx_chan))
 991                 return -ENODEV;
 992
 993         priv->rx_ring_size = ENETSW_DEF_RX_DESC;
 994         priv->tx_ring_size = ENETSW_DEF_TX_DESC;
 995
 996         priv->dma_maxburst = ENETSW_DMA_MAXBURST;
 997
 998         priv->copybreak = ENETSW_DEF_CPY_BREAK;
 999
1000         priv->dma_chan_en_mask = DMAC_CHANCFG_EN_MASK;
1001         priv->dma_chan_int_mask = DMAC_IR_PKTDONE_MASK;
1002         priv->dma_chan_width = DMA_CHAN_WIDTH;
1003
1004         of_get_mac_address(node, ndev->dev_addr);
1005         if (is_valid_ether_addr(ndev->dev_addr)) {
1006                 dev_info(dev, "mtd mac %pM\n", ndev->dev_addr);
1007         } else {
1008                 random_ether_addr(ndev->dev_addr);
1009                 dev_info(dev, "random mac %pM\n", ndev->dev_addr);
1010         }
1011
1012         priv->rx_buf_size = ALIGN(ndev->mtu + ENETSW_MTU_OVERHEAD,
1013                                   priv->dma_maxburst * 4);
1014
1015         priv->rx_frag_size = ENETSW_FRAG_SIZE(priv->rx_buf_size);
1016
1017         priv->num_clocks = of_clk_get_parent_count(node);
1018         if (priv->num_clocks) {
1019                 priv->clock = devm_kcalloc(dev, priv->num_clocks,
1020                                            sizeof(struct clk *), GFP_KERNEL);
1021                 if (!priv->clock)
1022                         return -ENOMEM;
1023         }
1024         for (i = 0; i < priv->num_clocks; i++) {
1025                 priv->clock[i] = of_clk_get(node, i);
1026                 if (IS_ERR(priv->clock[i])) {
1027                         dev_err(dev, "error getting clock %d\n", i);
1028                         return -EINVAL;
1029                 }
1030
1031                 ret = clk_prepare_enable(priv->clock[i]);
1032                 if (ret) {
1033                         dev_err(dev, "error enabling clock %d\n", i);
1034                         return ret;
1035                 }
1036         }
1037
1038         priv->num_resets = of_count_phandle_with_args(node, "resets",
1039                                                       "#reset-cells");
1040         if (priv->num_resets) {
1041                 priv->reset = devm_kcalloc(dev, priv->num_resets,
1042                                            sizeof(struct reset_control *),
1043                                            GFP_KERNEL);
1044                 if (!priv->reset)
1045                         return -ENOMEM;
1046         }
1047         for (i = 0; i < priv->num_resets; i++) {
1048                 priv->reset[i] = devm_reset_control_get_by_index(dev, i);
1049                 if (IS_ERR(priv->reset[i])) {
1050                         dev_err(dev, "error getting reset %d\n", i);
1051                         return -EINVAL;
1052                 }
1053
1054                 ret = reset_control_reset(priv->reset[i]);
1055                 if (ret) {
1056                         dev_err(dev, "error performing reset %d\n", i);
1057                         return ret;
1058                 }
1059         }
1060
1061         spin_lock_init(&priv->rx_lock);
1062
1063         timer_setup(&priv->rx_timeout, bcm6368_enetsw_refill_rx_timer, 0);
1064
1065         /* register netdevice */
1066         ndev->netdev_ops = &bcm6368_enetsw_ops;
1067         ndev->min_mtu = ETH_ZLEN;
1068         ndev->mtu = ETH_DATA_LEN + ENETSW_TAG_SIZE;
1069         ndev->max_mtu = ETH_DATA_LEN + ENETSW_TAG_SIZE;
1070         netif_napi_add(ndev, &priv->napi, bcm6368_enetsw_poll, 16);
1071         SET_NETDEV_DEV(ndev, dev);
1072
1073         ret = register_netdev(ndev);
1074         if (ret)
1075                 goto out_disable_clk;
1076
1077         netif_carrier_off(ndev);
1078         platform_set_drvdata(pdev, ndev);
1079         priv->pdev = pdev;
1080         priv->net_dev = ndev;
1081
1082         return 0;
1083
1084 out_disable_clk:
1085         for (i = 0; i < priv->num_resets; i++)
1086                 reset_control_assert(priv->reset[i]);
1087
1088         for (i = 0; i < priv->num_clocks; i++)
1089                 clk_disable_unprepare(priv->clock[i]);
1090
1091         return ret;
1092 }
1093
1094 static int bcm6368_enetsw_remove(struct platform_device *pdev)
1095 {
1096         struct device *dev = &pdev->dev;
1097         struct net_device *ndev = platform_get_drvdata(pdev);
1098         struct bcm6368_enetsw *priv = netdev_priv(ndev);
1099         unsigned int i;
1100
1101         unregister_netdev(ndev);
1102
1103         pm_runtime_put_sync(dev);
1104         for (i = 0; priv->pm && i < priv->num_pms; i++) {
1105                 dev_pm_domain_detach(priv->pm[i], true);
1106                 device_link_del(priv->link_pm[i]);
1107         }
1108
1109         for (i = 0; i < priv->num_resets; i++)
1110                 reset_control_assert(priv->reset[i]);
1111
1112         for (i = 0; i < priv->num_clocks; i++)
1113                 clk_disable_unprepare(priv->clock[i]);
1114
1115         free_netdev(ndev);
1116
1117         return 0;
1118 }
1119
1120 static const struct of_device_id bcm6368_enetsw_of_match[] = {
1121         { .compatible = "brcm,bcm6318-enetsw", },
1122         { .compatible = "brcm,bcm6328-enetsw", },
1123         { .compatible = "brcm,bcm6362-enetsw", },
1124         { .compatible = "brcm,bcm6368-enetsw", },
1125         { .compatible = "brcm,bcm63268-enetsw", },
1126         { /* sentinel */ }
1127 };
1128 MODULE_DEVICE_TABLE(of, bcm6368_enetsw_of_match);
1129
1130 static struct platform_driver bcm6368_enetsw_driver = {
1131         .driver = {
1132                 .name = "bcm6368-enetsw",
1133                 .of_match_table = of_match_ptr(bcm6368_enetsw_of_match),
1134         },
1135         .probe  = bcm6368_enetsw_probe,
1136         .remove = bcm6368_enetsw_remove,
1137 };
1138 module_platform_driver(bcm6368_enetsw_driver);