include/arch/aarch64/el3_common_macros.S

   1 /*
   2  * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
   3  *
   4  * SPDX-License-Identifier: BSD-3-Clause
   5  */
   6
   7 #ifndef EL3_COMMON_MACROS_S
   8 #define EL3_COMMON_MACROS_S
   9
  10 #include <arch.h>
  11 #include <asm_macros.S>
  12
  13         /*
  14          * Helper macro to initialise EL3 registers we care about.
  15          */
  16         .macro el3_arch_init_common
  17         /* ---------------------------------------------------------------------
  18          * SCTLR_EL3 has already been initialised - read current value before
  19          * modifying.
  20          *
  21          * SCTLR_EL3.I: Enable the instruction cache.
  22          *
  23          * SCTLR_EL3.SA: Enable Stack Alignment check. A SP alignment fault
  24          *  exception is generated if a load or store instruction executed at
  25          *  EL3 uses the SP as the base address and the SP is not aligned to a
  26          *  16-byte boundary.
  27          *
  28          * SCTLR_EL3.A: Enable Alignment fault checking. All instructions that
  29          *  load or store one or more registers have an alignment check that the
  30          *  address being accessed is aligned to the size of the data element(s)
  31          *  being accessed.
  32          * ---------------------------------------------------------------------
  33          */
  34         mov     x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
  35         mrs     x0, sctlr_el3
  36         orr     x0, x0, x1
  37         msr     sctlr_el3, x0
  38         isb
  39
  40 #ifdef IMAGE_BL31
  41         /* ---------------------------------------------------------------------
  42          * Initialise the per-cpu cache pointer to the CPU.
  43          * This is done early to enable crash reporting to have access to crash
  44          * stack. Since crash reporting depends on cpu_data to report the
  45          * unhandled exception, not doing so can lead to recursive exceptions
  46          * due to a NULL TPIDR_EL3.
  47          * ---------------------------------------------------------------------
  48          */
  49         bl      init_cpu_data_ptr
  50 #endif /* IMAGE_BL31 */
  51
  52         /* ---------------------------------------------------------------------
  53          * Initialise SCR_EL3, setting all fields rather than relying on hw.
  54          * All fields are architecturally UNKNOWN on reset. The following fields
  55          * do not change during the TF lifetime. The remaining fields are set to
  56          * zero here but are updated ahead of transitioning to a lower EL in the
  57          * function cm_init_context_common().
  58          *
  59          * SCR_EL3.TWE: Set to zero so that execution of WFE instructions at
  60          *  EL2, EL1 and EL0 are not trapped to EL3.
  61          *
  62          * SCR_EL3.TWI: Set to zero so that execution of WFI instructions at
  63          *  EL2, EL1 and EL0 are not trapped to EL3.
  64          *
  65          * SCR_EL3.SIF: Set to one to disable instruction fetches from
  66          *  Non-secure memory.
  67          *
  68          * SCR_EL3.SMD: Set to zero to enable SMC calls at EL1 and above, from
  69          *  both Security states and both Execution states.
  70          *
  71          * SCR_EL3.EA: Set to one to route External Aborts and SError Interrupts
  72          *  to EL3 when executing at any EL.
  73          *
  74          * SCR_EL3.{API,APK}: For Armv8.3 pointer authentication feature,
  75          * disable traps to EL3 when accessing key registers or using pointer
  76          * authentication instructions from lower ELs.
  77          * ---------------------------------------------------------------------
  78          */
  79         mov_imm x0, ((SCR_RESET_VAL | SCR_EA_BIT | SCR_SIF_BIT) \
  80                         & ~(SCR_TWE_BIT | SCR_TWI_BIT | SCR_SMD_BIT))
  81 #if CTX_INCLUDE_PAUTH_REGS
  82         /*
  83          * If the pointer authentication registers are saved during world
  84          * switches, enable pointer authentication everywhere, as it is safe to
  85          * do so.
  86          */
  87         orr     x0, x0, #(SCR_API_BIT | SCR_APK_BIT)
  88 #endif
  89         msr     scr_el3, x0
  90
  91         /* ---------------------------------------------------------------------
  92          * Initialise MDCR_EL3, setting all fields rather than relying on hw.
  93          * Some fields are architecturally UNKNOWN on reset.
  94          *
  95          * MDCR_EL3.SDD: Set to one to disable AArch64 Secure self-hosted debug.
  96          *  Debug exceptions, other than Breakpoint Instruction exceptions, are
  97          *  disabled from all ELs in Secure state.
  98          *
  99          * MDCR_EL3.SPD32: Set to 0b10 to disable AArch32 Secure self-hosted
 100          *  privileged debug from S-EL1.
 101          *
 102          * MDCR_EL3.TDOSA: Set to zero so that EL2 and EL2 System register
 103          *  access to the powerdown debug registers do not trap to EL3.
 104          *
 105          * MDCR_EL3.TDA: Set to zero to allow EL0, EL1 and EL2 access to the
 106          *  debug registers, other than those registers that are controlled by
 107          *  MDCR_EL3.TDOSA.
 108          *
 109          * MDCR_EL3.TPM: Set to zero so that EL0, EL1, and EL2 System register
 110          *  accesses to all Performance Monitors registers do not trap to EL3.
 111          *
 112          * MDCR_EL3.SCCD: Set to one so that cycle counting by PMCCNTR_EL0 is
 113          *  prohibited in Secure state. This bit is RES0 in versions of the
 114          *  architecture earlier than ARMv8.5, setting it to 1 doesn't have any
 115          *  effect on them.
 116          *
 117          * MDCR_EL3.SPME: Set to zero so that event counting by the programmable
 118          *  counters PMEVCNTR<n>_EL0 is prohibited in Secure state. If ARMv8.2
 119          *  Debug is not implemented this bit does not have any effect on the
 120          *  counters unless there is support for the implementation defined
 121          *  authentication interface ExternalSecureNoninvasiveDebugEnabled().
 122          * ---------------------------------------------------------------------
 123          */
 124         mov_imm x0, ((MDCR_EL3_RESET_VAL | MDCR_SDD_BIT | \
 125                       MDCR_SPD32(MDCR_SPD32_DISABLE) | MDCR_SCCD_BIT) & \
 126                     ~(MDCR_SPME_BIT | MDCR_TDOSA_BIT | MDCR_TDA_BIT | \
 127                       MDCR_TPM_BIT))
 128
 129         msr     mdcr_el3, x0
 130
 131         /* ---------------------------------------------------------------------
 132          * Initialise PMCR_EL0 setting all fields rather than relying
 133          * on hw. Some fields are architecturally UNKNOWN on reset.
 134          *
 135          * PMCR_EL0.LP: Set to one so that event counter overflow, that
 136          *  is recorded in PMOVSCLR_EL0[0-30], occurs on the increment
 137          *  that changes PMEVCNTR<n>_EL0[63] from 1 to 0, when ARMv8.5-PMU
 138          *  is implemented. This bit is RES0 in versions of the architecture
 139          *  earlier than ARMv8.5, setting it to 1 doesn't have any effect
 140          *  on them.
 141          *
 142          * PMCR_EL0.LC: Set to one so that cycle counter overflow, that
 143          *  is recorded in PMOVSCLR_EL0[31], occurs on the increment
 144          *  that changes PMCCNTR_EL0[63] from 1 to 0.
 145          *
 146          * PMCR_EL0.DP: Set to one so that the cycle counter,
 147          *  PMCCNTR_EL0 does not count when event counting is prohibited.
 148          *
 149          * PMCR_EL0.X: Set to zero to disable export of events.
 150          *
 151          * PMCR_EL0.D: Set to zero so that, when enabled, PMCCNTR_EL0
 152          *  counts on every clock cycle.
 153          * ---------------------------------------------------------------------
 154          */
 155         mov_imm x0, ((PMCR_EL0_RESET_VAL | PMCR_EL0_LP_BIT | \
 156                       PMCR_EL0_LC_BIT | PMCR_EL0_DP_BIT) & \
 157                     ~(PMCR_EL0_X_BIT | PMCR_EL0_D_BIT))
 158         /* BRCM_PATCH: Do not overwrite the setting done by BRCM boot loaders
 159         msr     pmcr_el0, x0
 160         */
 161         /* ---------------------------------------------------------------------
 162          * Enable External Aborts and SError Interrupts now that the exception
 163          * vectors have been setup.
 164          * ---------------------------------------------------------------------
 165          */
 166         msr     daifclr, #DAIF_ABT_BIT
 167
 168         /* ---------------------------------------------------------------------
 169          * Initialise CPTR_EL3, setting all fields rather than relying on hw.
 170          * All fields are architecturally UNKNOWN on reset.
 171          *
 172          * CPTR_EL3.TCPAC: Set to zero so that any accesses to CPACR_EL1,
 173          *  CPTR_EL2, CPACR, or HCPTR do not trap to EL3.
 174          *
 175          * CPTR_EL3.TTA: Set to zero so that System register accesses to the
 176          *  trace registers do not trap to EL3.
 177          *
 178          * CPTR_EL3.TFP: Set to zero so that accesses to the V- or Z- registers
 179          *  by Advanced SIMD, floating-point or SVE instructions (if implemented)
 180          *  do not trap to EL3.
 181          */
 182         mov_imm x0, (CPTR_EL3_RESET_VAL & ~(TCPAC_BIT | TTA_BIT | TFP_BIT))
 183         msr     cptr_el3, x0
 184
 185         /*
 186          * If Data Independent Timing (DIT) functionality is implemented,
 187          * always enable DIT in EL3
 188          */
 189         mrs     x0, id_aa64pfr0_el1
 190         ubfx    x0, x0, #ID_AA64PFR0_DIT_SHIFT, #ID_AA64PFR0_DIT_LENGTH
 191         cmp     x0, #ID_AA64PFR0_DIT_SUPPORTED
 192         bne     1f
 193         mov     x0, #DIT_BIT
 194         msr     DIT, x0
 195 1:
 196         .endm
 197
 198 /* -----------------------------------------------------------------------------
 199  * This is the super set of actions that need to be performed during a cold boot
 200  * or a warm boot in EL3. This code is shared by BL1 and BL31.
 201  *
 202  * This macro will always perform reset handling, architectural initialisations
 203  * and stack setup. The rest of the actions are optional because they might not
 204  * be needed, depending on the context in which this macro is called. This is
 205  * why this macro is parameterised ; each parameter allows to enable/disable
 206  * some actions.
 207  *
 208  *  _init_sctlr:
 209  *      Whether the macro needs to initialise SCTLR_EL3, including configuring
 210  *      the endianness of data accesses.
 211  *
 212  *  _warm_boot_mailbox:
 213  *      Whether the macro needs to detect the type of boot (cold/warm). The
 214  *      detection is based on the platform entrypoint address : if it is zero
 215  *      then it is a cold boot, otherwise it is a warm boot. In the latter case,
 216  *      this macro jumps on the platform entrypoint address.
 217  *
 218  *  _secondary_cold_boot:
 219  *      Whether the macro needs to identify the CPU that is calling it: primary
 220  *      CPU or secondary CPU. The primary CPU will be allowed to carry on with
 221  *      the platform initialisations, while the secondaries will be put in a
 222  *      platform-specific state in the meantime.
 223  *
 224  *      If the caller knows this macro will only be called by the primary CPU
 225  *      then this parameter can be defined to 0 to skip this step.
 226  *
 227  * _init_memory:
 228  *      Whether the macro needs to initialise the memory.
 229  *
 230  * _init_c_runtime:
 231  *      Whether the macro needs to initialise the C runtime environment.
 232  *
 233  * _exception_vectors:
 234  *      Address of the exception vectors to program in the VBAR_EL3 register.
 235  * -----------------------------------------------------------------------------
 236  */
 237         .macro el3_entrypoint_common                                    \
 238                 _init_sctlr, _warm_boot_mailbox, _secondary_cold_boot,  \
 239                 _init_memory, _init_c_runtime, _exception_vectors
 240
 241         .if \_init_sctlr
 242                 /* -------------------------------------------------------------
 243                  * This is the initialisation of SCTLR_EL3 and so must ensure
 244                  * that all fields are explicitly set rather than relying on hw.
 245                  * Some fields reset to an IMPLEMENTATION DEFINED value and
 246                  * others are architecturally UNKNOWN on reset.
 247                  *
 248                  * SCTLR.EE: Set the CPU endianness before doing anything that
 249                  *  might involve memory reads or writes. Set to zero to select
 250                  *  Little Endian.
 251                  *
 252                  * SCTLR_EL3.WXN: For the EL3 translation regime, this field can
 253                  *  force all memory regions that are writeable to be treated as
 254                  *  XN (Execute-never). Set to zero so that this control has no
 255                  *  effect on memory access permissions.
 256                  *
 257                  * SCTLR_EL3.SA: Set to zero to disable Stack Alignment check.
 258                  *
 259                  * SCTLR_EL3.A: Set to zero to disable Alignment fault checking.
 260                  *
 261                  * SCTLR.DSSBS: Set to zero to disable speculation store bypass
 262                  *  safe behaviour upon exception entry to EL3.
 263                  * -------------------------------------------------------------
 264                  */
 265                 mov_imm x0, (SCTLR_RESET_VAL & ~(SCTLR_EE_BIT | SCTLR_WXN_BIT \
 266                                 | SCTLR_SA_BIT | SCTLR_A_BIT | SCTLR_DSSBS_BIT))
 267                 msr     sctlr_el3, x0
 268                 isb
 269         .endif /* _init_sctlr */
 270
 271         .if \_warm_boot_mailbox
 272                 /* -------------------------------------------------------------
 273                  * This code will be executed for both warm and cold resets.
 274                  * Now is the time to distinguish between the two.
 275                  * Query the platform entrypoint address and if it is not zero
 276                  * then it means it is a warm boot so jump to this address.
 277                  * -------------------------------------------------------------
 278                  */
 279                 bl      plat_get_my_entrypoint
 280                 cbz     x0, do_cold_boot
 281                 br      x0
 282
 283         do_cold_boot:
 284         .endif /* _warm_boot_mailbox */
 285
 286         /* ---------------------------------------------------------------------
 287          * Set the exception vectors.
 288          * ---------------------------------------------------------------------
 289          */
 290         adr     x0, \_exception_vectors
 291         msr     vbar_el3, x0
 292         isb
 293
 294         /* ---------------------------------------------------------------------
 295          * It is a cold boot.
 296          * Perform any processor specific actions upon reset e.g. cache, TLB
 297          * invalidations etc.
 298          * ---------------------------------------------------------------------
 299          */
 300         bl      reset_handler
 301
 302         el3_arch_init_common
 303
 304         .if \_secondary_cold_boot
 305                 /* -------------------------------------------------------------
 306                  * Check if this is a primary or secondary CPU cold boot.
 307                  * The primary CPU will set up the platform while the
 308                  * secondaries are placed in a platform-specific state until the
 309                  * primary CPU performs the necessary actions to bring them out
 310                  * of that state and allows entry into the OS.
 311                  * -------------------------------------------------------------
 312                  */
 313                 bl      plat_is_my_cpu_primary
 314                 cbnz    w0, do_primary_cold_boot
 315
 316                 /* This is a cold boot on a secondary CPU */
 317                 bl      plat_secondary_cold_boot_setup
 318                 /* plat_secondary_cold_boot_setup() is not supposed to return */
 319                 bl      el3_panic
 320
 321         do_primary_cold_boot:
 322         .endif /* _secondary_cold_boot */
 323
 324         /* ---------------------------------------------------------------------
 325          * Initialize memory now. Secondary CPU initialization won't get to this
 326          * point.
 327          * ---------------------------------------------------------------------
 328          */
 329
 330         .if \_init_memory
 331                 bl      platform_mem_init
 332         .endif /* _init_memory */
 333
 334         /* ---------------------------------------------------------------------
 335          * Init C runtime environment:
 336          *   - Zero-initialise the NOBITS sections. There are 2 of them:
 337          *       - the .bss section;
 338          *       - the coherent memory section (if any).
 339          *   - Relocate the data section from ROM to RAM, if required.
 340          * ---------------------------------------------------------------------
 341          */
 342         .if \_init_c_runtime
 343 #if defined(IMAGE_BL31) || (defined(IMAGE_BL2) && BL2_AT_EL3 && BL2_INV_DCACHE)
 344                 /* -------------------------------------------------------------
 345                  * Invalidate the RW memory used by the BL31 image. This
 346                  * includes the data and NOBITS sections. This is done to
 347                  * safeguard against possible corruption of this memory by
 348                  * dirty cache lines in a system cache as a result of use by
 349                  * an earlier boot loader stage.
 350                  * -------------------------------------------------------------
 351                  */
 352                 adrp    x0, __RW_START__
 353                 add     x0, x0, :lo12:__RW_START__
 354                 adrp    x1, __RW_END__
 355                 add     x1, x1, :lo12:__RW_END__
 356                 sub     x1, x1, x0
 357                 bl      inv_dcache_range
 358 #endif
 359                 adrp    x0, __BSS_START__
 360                 add     x0, x0, :lo12:__BSS_START__
 361
 362                 adrp    x1, __BSS_END__
 363                 add     x1, x1, :lo12:__BSS_END__
 364                 sub     x1, x1, x0
 365                 bl      zeromem
 366
 367 #if USE_COHERENT_MEM
 368                 adrp    x0, __COHERENT_RAM_START__
 369                 add     x0, x0, :lo12:__COHERENT_RAM_START__
 370                 adrp    x1, __COHERENT_RAM_END_UNALIGNED__
 371                 add     x1, x1, :lo12: __COHERENT_RAM_END_UNALIGNED__
 372                 sub     x1, x1, x0
 373                 bl      zeromem
 374 #endif
 375
 376 #if defined(IMAGE_BL1) || (defined(IMAGE_BL2) && BL2_AT_EL3 && BL2_IN_XIP_MEM)
 377                 adrp    x0, __DATA_RAM_START__
 378                 add     x0, x0, :lo12:__DATA_RAM_START__
 379                 adrp    x1, __DATA_ROM_START__
 380                 add     x1, x1, :lo12:__DATA_ROM_START__
 381                 adrp    x2, __DATA_RAM_END__
 382                 add     x2, x2, :lo12:__DATA_RAM_END__
 383                 sub     x2, x2, x0
 384                 bl      memcpy16
 385 #endif
 386         .endif /* _init_c_runtime */
 387
 388         /* ---------------------------------------------------------------------
 389          * Use SP_EL0 for the C runtime stack.
 390          * ---------------------------------------------------------------------
 391          */
 392         msr     spsel, #0
 393
 394         /* ---------------------------------------------------------------------
 395          * Allocate a stack whose memory will be marked as Normal-IS-WBWA when
 396          * the MMU is enabled. There is no risk of reading stale stack memory
 397          * after enabling the MMU as only the primary CPU is running at the
 398          * moment.
 399          * ---------------------------------------------------------------------
 400          */
 401         bl      plat_set_my_stack
 402
 403 #if STACK_PROTECTOR_ENABLED
 404         .if \_init_c_runtime
 405         bl      update_stack_protector_canary
 406         .endif /* _init_c_runtime */
 407 #endif
 408         .endm
 409
 410 #endif /* EL3_COMMON_MACROS_S */