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large target/linux cleanup
[openwrt/staging/mkresin.git] / openwrt / target / linux / brcm-2.6 / patches / 001-bcm947xx.patch
1 diff -urN linux.old/arch/mips/Kconfig linux.dev/arch/mips/Kconfig
2 --- linux.old/arch/mips/Kconfig 2005-12-19 01:36:54.000000000 +0100
3 +++ linux.dev/arch/mips/Kconfig 2005-12-28 16:37:32.810257250 +0100
4 @@ -244,6 +244,17 @@
5 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millenium and
6 Olivetti M700-10 workstations.
7
8 +config BCM947XX
9 + bool "Support for BCM947xx based boards"
10 + select DMA_NONCOHERENT
11 + select HW_HAS_PCI
12 + select IRQ_CPU
13 + select SYS_HAS_CPU_MIPS32_R1
14 + select SYS_SUPPORTS_32BIT_KERNEL
15 + select SYS_SUPPORTS_LITTLE_ENDIAN
16 + help
17 + Support for BCM947xx based boards
18 +
19 config LASAT
20 bool "Support for LASAT Networks platforms"
21 select DMA_NONCOHERENT
22 diff -urN linux.old/arch/mips/Makefile linux.dev/arch/mips/Makefile
23 --- linux.old/arch/mips/Makefile 2005-12-19 01:36:54.000000000 +0100
24 +++ linux.dev/arch/mips/Makefile 2005-12-28 16:37:32.814257500 +0100
25 @@ -689,6 +689,13 @@
26 load-$(CONFIG_SIBYTE_BIGSUR) := 0xffffffff80100000
27
28 #
29 +# Broadcom BCM47XX boards
30 +#
31 +core-$(CONFIG_BCM947XX) += arch/mips/bcm947xx/ arch/mips/bcm947xx/broadcom/
32 +cflags-$(CONFIG_BCM947XX) += -Iarch/mips/bcm947xx/include
33 +load-$(CONFIG_BCM947XX) := 0xffffffff80001000
34 +
35 +#
36 # SNI RM200 PCI
37 #
38 core-$(CONFIG_SNI_RM200_PCI) += arch/mips/sni/
39 diff -urN linux.old/arch/mips/bcm947xx/Makefile linux.dev/arch/mips/bcm947xx/Makefile
40 --- linux.old/arch/mips/bcm947xx/Makefile 1970-01-01 01:00:00.000000000 +0100
41 +++ linux.dev/arch/mips/bcm947xx/Makefile 2005-12-28 16:37:32.814257500 +0100
42 @@ -0,0 +1,6 @@
43 +#
44 +# Makefile for the BCM47xx specific kernel interface routines
45 +# under Linux.
46 +#
47 +
48 +obj-y := irq.o int-handler.o prom.o setup.o time.o pci.o
49 diff -urN linux.old/arch/mips/bcm947xx/broadcom/Makefile linux.dev/arch/mips/bcm947xx/broadcom/Makefile
50 --- linux.old/arch/mips/bcm947xx/broadcom/Makefile 1970-01-01 01:00:00.000000000 +0100
51 +++ linux.dev/arch/mips/bcm947xx/broadcom/Makefile 2005-12-28 16:37:32.814257500 +0100
52 @@ -0,0 +1,6 @@
53 +#
54 +# Makefile for the BCM47xx specific kernel interface routines
55 +# under Linux.
56 +#
57 +
58 +obj-y := sbutils.o linux_osl.o bcmsrom.o bcmutils.o sbmips.o sbpci.o sflash.o nvram.o cfe_env.o
59 diff -urN linux.old/arch/mips/bcm947xx/broadcom/bcmsrom.c linux.dev/arch/mips/bcm947xx/broadcom/bcmsrom.c
60 --- linux.old/arch/mips/bcm947xx/broadcom/bcmsrom.c 1970-01-01 01:00:00.000000000 +0100
61 +++ linux.dev/arch/mips/bcm947xx/broadcom/bcmsrom.c 2005-12-28 16:37:32.814257500 +0100
62 @@ -0,0 +1,481 @@
63 +/*
64 + * Misc useful routines to access NIC SROM/OTP .
65 + *
66 + * Copyright 2005, Broadcom Corporation
67 + * All Rights Reserved.
68 + *
69 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
70 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
71 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
72 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
73 + * $Id$
74 + */
75 +
76 +#include <typedefs.h>
77 +#include <osl.h>
78 +#include <bcmutils.h>
79 +#include <bcmsrom.h>
80 +#include <bcmdevs.h>
81 +#include <bcmendian.h>
82 +#include <pcicfg.h>
83 +#include <sbutils.h>
84 +
85 +#include <proto/ethernet.h> /* for sprom content groking */
86 +
87 +#define VARS_MAX 4096 /* should be reduced */
88 +
89 +#define WRITE_ENABLE_DELAY 500 /* 500 ms after write enable/disable toggle */
90 +#define WRITE_WORD_DELAY 20 /* 20 ms between each word write */
91 +
92 +static int initvars_srom_pci(void *sbh, void *curmap, char **vars, int *count);
93 +static int sprom_read_pci(uint16 *sprom, uint wordoff, uint16 *buf, uint nwords, bool check_crc);
94 +
95 +static int initvars_table(osl_t *osh, char *start, char *end, char **vars, uint *count);
96 +
97 +/*
98 + * Initialize local vars from the right source for this platform.
99 + * Return 0 on success, nonzero on error.
100 + */
101 +int
102 +srom_var_init(void *sbh, uint bustype, void *curmap, osl_t *osh, char **vars, int *count)
103 +{
104 + ASSERT(bustype == BUSTYPE(bustype));
105 + if (vars == NULL || count == NULL)
106 + return (0);
107 +
108 + switch (BUSTYPE(bustype)) {
109 +
110 + case PCI_BUS:
111 + ASSERT(curmap); /* can not be NULL */
112 + return initvars_srom_pci(sbh, curmap, vars, count);
113 +
114 + default:
115 + return 0;
116 + }
117 + return (-1);
118 +}
119 +
120 +/* support only 16-bit word read from srom */
121 +int
122 +srom_read(uint bustype, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf)
123 +{
124 + void *srom;
125 + uint off, nw;
126 +
127 + ASSERT(bustype == BUSTYPE(bustype));
128 +
129 + /* check input - 16-bit access only */
130 + if (byteoff & 1 || nbytes & 1 || (byteoff + nbytes) > (SPROM_SIZE * 2))
131 + return 1;
132 +
133 + off = byteoff / 2;
134 + nw = nbytes / 2;
135 +
136 + if (BUSTYPE(bustype) == PCI_BUS) {
137 + if (!curmap)
138 + return 1;
139 + srom = (uchar*)curmap + PCI_BAR0_SPROM_OFFSET;
140 + if (sprom_read_pci(srom, off, buf, nw, FALSE))
141 + return 1;
142 + } else {
143 + return 1;
144 + }
145 +
146 + return 0;
147 +}
148 +
149 +/* support only 16-bit word write into srom */
150 +int
151 +srom_write(uint bustype, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf)
152 +{
153 + uint16 *srom;
154 + uint i, off, nw, crc_range;
155 + uint16 image[SPROM_SIZE], *p;
156 + uint8 crc;
157 + volatile uint32 val32;
158 +
159 + ASSERT(bustype == BUSTYPE(bustype));
160 +
161 + /* check input - 16-bit access only */
162 + if (byteoff & 1 || nbytes & 1 || (byteoff + nbytes) > (SPROM_SIZE * 2))
163 + return 1;
164 +
165 + crc_range = (((BUSTYPE(bustype) == SDIO_BUS)) ? SPROM_SIZE : SPROM_CRC_RANGE) * 2;
166 +
167 + /* if changes made inside crc cover range */
168 + if (byteoff < crc_range) {
169 + nw = (((byteoff + nbytes) > crc_range) ? byteoff + nbytes : crc_range) / 2;
170 + /* read data including entire first 64 words from srom */
171 + if (srom_read(bustype, curmap, osh, 0, nw * 2, image))
172 + return 1;
173 + /* make changes */
174 + bcopy((void*)buf, (void*)&image[byteoff / 2], nbytes);
175 + /* calculate crc */
176 + htol16_buf(image, crc_range);
177 + crc = ~hndcrc8((uint8 *)image, crc_range - 1, CRC8_INIT_VALUE);
178 + ltoh16_buf(image, crc_range);
179 + image[(crc_range / 2) - 1] = (crc << 8) | (image[(crc_range / 2) - 1] & 0xff);
180 + p = image;
181 + off = 0;
182 + } else {
183 + p = buf;
184 + off = byteoff / 2;
185 + nw = nbytes / 2;
186 + }
187 +
188 + if (BUSTYPE(bustype) == PCI_BUS) {
189 + srom = (uint16*)((uchar*)curmap + PCI_BAR0_SPROM_OFFSET);
190 + /* enable writes to the SPROM */
191 + val32 = OSL_PCI_READ_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32));
192 + val32 |= SPROM_WRITEEN;
193 + OSL_PCI_WRITE_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32), val32);
194 + bcm_mdelay(WRITE_ENABLE_DELAY);
195 + /* write srom */
196 + for (i = 0; i < nw; i++) {
197 + W_REG(&srom[off + i], p[i]);
198 + bcm_mdelay(WRITE_WORD_DELAY);
199 + }
200 + /* disable writes to the SPROM */
201 + OSL_PCI_WRITE_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32), val32 & ~SPROM_WRITEEN);
202 + } else {
203 + return 1;
204 + }
205 +
206 + bcm_mdelay(WRITE_ENABLE_DELAY);
207 + return 0;
208 +}
209 +
210 +
211 +/*
212 + * Read in and validate sprom.
213 + * Return 0 on success, nonzero on error.
214 + */
215 +static int
216 +sprom_read_pci(uint16 *sprom, uint wordoff, uint16 *buf, uint nwords, bool check_crc)
217 +{
218 + int err = 0;
219 + uint i;
220 +
221 + /* read the sprom */
222 + for (i = 0; i < nwords; i++)
223 + buf[i] = R_REG(&sprom[wordoff + i]);
224 +
225 + if (check_crc) {
226 + /* fixup the endianness so crc8 will pass */
227 + htol16_buf(buf, nwords * 2);
228 + if (hndcrc8((uint8*)buf, nwords * 2, CRC8_INIT_VALUE) != CRC8_GOOD_VALUE)
229 + err = 1;
230 + /* now correct the endianness of the byte array */
231 + ltoh16_buf(buf, nwords * 2);
232 + }
233 +
234 + return err;
235 +}
236 +
237 +/*
238 +* Create variable table from memory.
239 +* Return 0 on success, nonzero on error.
240 +*/
241 +static int
242 +initvars_table(osl_t *osh, char *start, char *end, char **vars, uint *count)
243 +{
244 + int c = (int)(end - start);
245 +
246 + /* do it only when there is more than just the null string */
247 + if (c > 1) {
248 + char *vp = MALLOC(osh, c);
249 + ASSERT(vp);
250 + if (!vp)
251 + return BCME_NOMEM;
252 + bcopy(start, vp, c);
253 + *vars = vp;
254 + *count = c;
255 + }
256 + else {
257 + *vars = NULL;
258 + *count = 0;
259 + }
260 +
261 + return 0;
262 +}
263 +
264 +/*
265 + * Initialize nonvolatile variable table from sprom.
266 + * Return 0 on success, nonzero on error.
267 + */
268 +static int
269 +initvars_srom_pci(void *sbh, void *curmap, char **vars, int *count)
270 +{
271 + uint16 w, b[64];
272 + uint8 sromrev;
273 + struct ether_addr ea;
274 + char eabuf[32];
275 + uint32 w32;
276 + int woff, i;
277 + char *vp, *base;
278 + osl_t *osh = sb_osh(sbh);
279 + int err;
280 +
281 + /*
282 + * Apply CRC over SROM content regardless SROM is present or not,
283 + * and use variable <devpath>sromrev's existance in flash to decide
284 + * if we should return an error when CRC fails or read SROM variables
285 + * from flash.
286 + */
287 + sprom_read_pci((void*)((int8*)curmap + PCI_BAR0_SPROM_OFFSET), 0, b, sizeof(b)/sizeof(b[0]), TRUE);
288 +
289 + /* top word of sprom contains version and crc8 */
290 + sromrev = b[63] & 0xff;
291 + /* bcm4401 sroms misprogrammed */
292 + if (sromrev == 0x10)
293 + sromrev = 1;
294 +
295 + /* srom version check */
296 + if (sromrev > 3)
297 + return (-2);
298 +
299 + ASSERT(vars);
300 + ASSERT(count);
301 +
302 + base = vp = MALLOC(osh, VARS_MAX);
303 + ASSERT(vp);
304 + if (!vp)
305 + return -2;
306 +
307 + vp += sprintf(vp, "sromrev=%d", sromrev);
308 + vp++;
309 +
310 + if (sromrev >= 3) {
311 + /* New section takes over the 3th hardware function space */
312 +
313 + /* Words 22+23 are 11a (mid) ofdm power offsets */
314 + w32 = ((uint32)b[23] << 16) | b[22];
315 + vp += sprintf(vp, "ofdmapo=%d", w32);
316 + vp++;
317 +
318 + /* Words 24+25 are 11a (low) ofdm power offsets */
319 + w32 = ((uint32)b[25] << 16) | b[24];
320 + vp += sprintf(vp, "ofdmalpo=%d", w32);
321 + vp++;
322 +
323 + /* Words 26+27 are 11a (high) ofdm power offsets */
324 + w32 = ((uint32)b[27] << 16) | b[26];
325 + vp += sprintf(vp, "ofdmahpo=%d", w32);
326 + vp++;
327 +
328 + /*GPIO LED Powersave duty cycle (oncount >> 24) (offcount >> 8)*/
329 + w32 = ((uint32)b[43] << 24) | ((uint32)b[42] << 8);
330 + vp += sprintf(vp, "gpiotimerval=%d", w32);
331 +
332 + /*GPIO LED Powersave duty cycle (oncount >> 24) (offcount >> 8)*/
333 + w32 = ((uint32)((unsigned char)(b[21] >> 8) & 0xFF) << 24) | /* oncount*/
334 + ((uint32)((unsigned char)(b[21] & 0xFF)) << 8); /* offcount */
335 + vp += sprintf(vp, "gpiotimerval=%d", w32);
336 +
337 + vp++;
338 + }
339 +
340 + if (sromrev >= 2) {
341 + /* New section takes over the 4th hardware function space */
342 +
343 + /* Word 29 is max power 11a high/low */
344 + w = b[29];
345 + vp += sprintf(vp, "pa1himaxpwr=%d", w & 0xff);
346 + vp++;
347 + vp += sprintf(vp, "pa1lomaxpwr=%d", (w >> 8) & 0xff);
348 + vp++;
349 +
350 + /* Words 30-32 set the 11alow pa settings,
351 + * 33-35 are the 11ahigh ones.
352 + */
353 + for (i = 0; i < 3; i++) {
354 + vp += sprintf(vp, "pa1lob%d=%d", i, b[30 + i]);
355 + vp++;
356 + vp += sprintf(vp, "pa1hib%d=%d", i, b[33 + i]);
357 + vp++;
358 + }
359 + w = b[59];
360 + if (w == 0)
361 + vp += sprintf(vp, "ccode=");
362 + else
363 + vp += sprintf(vp, "ccode=%c%c", (w >> 8), (w & 0xff));
364 + vp++;
365 +
366 + }
367 +
368 + /* parameter section of sprom starts at byte offset 72 */
369 + woff = 72/2;
370 +
371 + /* first 6 bytes are il0macaddr */
372 + ea.octet[0] = (b[woff] >> 8) & 0xff;
373 + ea.octet[1] = b[woff] & 0xff;
374 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
375 + ea.octet[3] = b[woff+1] & 0xff;
376 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
377 + ea.octet[5] = b[woff+2] & 0xff;
378 + woff += ETHER_ADDR_LEN/2 ;
379 + bcm_ether_ntoa((uchar*)&ea, eabuf);
380 + vp += sprintf(vp, "il0macaddr=%s", eabuf);
381 + vp++;
382 +
383 + /* next 6 bytes are et0macaddr */
384 + ea.octet[0] = (b[woff] >> 8) & 0xff;
385 + ea.octet[1] = b[woff] & 0xff;
386 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
387 + ea.octet[3] = b[woff+1] & 0xff;
388 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
389 + ea.octet[5] = b[woff+2] & 0xff;
390 + woff += ETHER_ADDR_LEN/2 ;
391 + bcm_ether_ntoa((uchar*)&ea, eabuf);
392 + vp += sprintf(vp, "et0macaddr=%s", eabuf);
393 + vp++;
394 +
395 + /* next 6 bytes are et1macaddr */
396 + ea.octet[0] = (b[woff] >> 8) & 0xff;
397 + ea.octet[1] = b[woff] & 0xff;
398 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
399 + ea.octet[3] = b[woff+1] & 0xff;
400 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
401 + ea.octet[5] = b[woff+2] & 0xff;
402 + woff += ETHER_ADDR_LEN/2 ;
403 + bcm_ether_ntoa((uchar*)&ea, eabuf);
404 + vp += sprintf(vp, "et1macaddr=%s", eabuf);
405 + vp++;
406 +
407 + /*
408 + * Enet phy settings one or two singles or a dual
409 + * Bits 4-0 : MII address for enet0 (0x1f for not there)
410 + * Bits 9-5 : MII address for enet1 (0x1f for not there)
411 + * Bit 14 : Mdio for enet0
412 + * Bit 15 : Mdio for enet1
413 + */
414 + w = b[woff];
415 + vp += sprintf(vp, "et0phyaddr=%d", (w & 0x1f));
416 + vp++;
417 + vp += sprintf(vp, "et1phyaddr=%d", ((w >> 5) & 0x1f));
418 + vp++;
419 + vp += sprintf(vp, "et0mdcport=%d", ((w >> 14) & 0x1));
420 + vp++;
421 + vp += sprintf(vp, "et1mdcport=%d", ((w >> 15) & 0x1));
422 + vp++;
423 +
424 + /* Word 46 has board rev, antennas 0/1 & Country code/control */
425 + w = b[46];
426 + vp += sprintf(vp, "boardrev=%d", w & 0xff);
427 + vp++;
428 +
429 + if (sromrev > 1)
430 + vp += sprintf(vp, "cctl=%d", (w >> 8) & 0xf);
431 + else
432 + vp += sprintf(vp, "cc=%d", (w >> 8) & 0xf);
433 + vp++;
434 +
435 + vp += sprintf(vp, "aa0=%d", (w >> 12) & 0x3);
436 + vp++;
437 +
438 + vp += sprintf(vp, "aa1=%d", (w >> 14) & 0x3);
439 + vp++;
440 +
441 + /* Words 47-49 set the (wl) pa settings */
442 + woff = 47;
443 +
444 + for (i = 0; i < 3; i++) {
445 + vp += sprintf(vp, "pa0b%d=%d", i, b[woff+i]);
446 + vp++;
447 + vp += sprintf(vp, "pa1b%d=%d", i, b[woff+i+6]);
448 + vp++;
449 + }
450 +
451 + /*
452 + * Words 50-51 set the customer-configured wl led behavior.
453 + * 8 bits/gpio pin. High bit: activehi=0, activelo=1;
454 + * LED behavior values defined in wlioctl.h .
455 + */
456 + w = b[50];
457 + if ((w != 0) && (w != 0xffff)) {
458 + /* gpio0 */
459 + vp += sprintf(vp, "wl0gpio0=%d", (w & 0xff));
460 + vp++;
461 +
462 + /* gpio1 */
463 + vp += sprintf(vp, "wl0gpio1=%d", (w >> 8) & 0xff);
464 + vp++;
465 + }
466 + w = b[51];
467 + if ((w != 0) && (w != 0xffff)) {
468 + /* gpio2 */
469 + vp += sprintf(vp, "wl0gpio2=%d", w & 0xff);
470 + vp++;
471 +
472 + /* gpio3 */
473 + vp += sprintf(vp, "wl0gpio3=%d", (w >> 8) & 0xff);
474 + vp++;
475 + }
476 +
477 + /* Word 52 is max power 0/1 */
478 + w = b[52];
479 + vp += sprintf(vp, "pa0maxpwr=%d", w & 0xff);
480 + vp++;
481 + vp += sprintf(vp, "pa1maxpwr=%d", (w >> 8) & 0xff);
482 + vp++;
483 +
484 + /* Word 56 is idle tssi target 0/1 */
485 + w = b[56];
486 + vp += sprintf(vp, "pa0itssit=%d", w & 0xff);
487 + vp++;
488 + vp += sprintf(vp, "pa1itssit=%d", (w >> 8) & 0xff);
489 + vp++;
490 +
491 + /* Word 57 is boardflags, if not programmed make it zero */
492 + w32 = (uint32)b[57];
493 + if (w32 == 0xffff) w32 = 0;
494 + if (sromrev > 1) {
495 + /* Word 28 is the high bits of boardflags */
496 + w32 |= (uint32)b[28] << 16;
497 + }
498 + vp += sprintf(vp, "boardflags=%d", w32);
499 + vp++;
500 +
501 + /* Word 58 is antenna gain 0/1 */
502 + w = b[58];
503 + vp += sprintf(vp, "ag0=%d", w & 0xff);
504 + vp++;
505 +
506 + vp += sprintf(vp, "ag1=%d", (w >> 8) & 0xff);
507 + vp++;
508 +
509 + if (sromrev == 1) {
510 + /* set the oem string */
511 + vp += sprintf(vp, "oem=%02x%02x%02x%02x%02x%02x%02x%02x",
512 + ((b[59] >> 8) & 0xff), (b[59] & 0xff),
513 + ((b[60] >> 8) & 0xff), (b[60] & 0xff),
514 + ((b[61] >> 8) & 0xff), (b[61] & 0xff),
515 + ((b[62] >> 8) & 0xff), (b[62] & 0xff));
516 + vp++;
517 + } else if (sromrev == 2) {
518 + /* Word 60 OFDM tx power offset from CCK level */
519 + /* OFDM Power Offset - opo */
520 + vp += sprintf(vp, "opo=%d", b[60] & 0xff);
521 + vp++;
522 + } else {
523 + /* Word 60: cck power offsets */
524 + vp += sprintf(vp, "cckpo=%d", b[60]);
525 + vp++;
526 +
527 + /* Words 61+62: 11g ofdm power offsets */
528 + w32 = ((uint32)b[62] << 16) | b[61];
529 + vp += sprintf(vp, "ofdmgpo=%d", w32);
530 + vp++;
531 + }
532 +
533 + /* final nullbyte terminator */
534 + *vp++ = '\0';
535 +
536 + ASSERT((vp - base) <= VARS_MAX);
537 +
538 + err = initvars_table(osh, base, vp, vars, count);
539 +
540 + MFREE(osh, base, VARS_MAX);
541 + return err;
542 +}
543 +
544 diff -urN linux.old/arch/mips/bcm947xx/broadcom/bcmutils.c linux.dev/arch/mips/bcm947xx/broadcom/bcmutils.c
545 --- linux.old/arch/mips/bcm947xx/broadcom/bcmutils.c 1970-01-01 01:00:00.000000000 +0100
546 +++ linux.dev/arch/mips/bcm947xx/broadcom/bcmutils.c 2005-12-28 16:37:32.814257500 +0100
547 @@ -0,0 +1,356 @@
548 +/*
549 + * Misc useful OS-independent routines.
550 + *
551 + * Copyright 2005, Broadcom Corporation
552 + * All Rights Reserved.
553 + *
554 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
555 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
556 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
557 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
558 + * $Id$
559 + */
560 +
561 +#include <typedefs.h>
562 +#include <osl.h>
563 +#include <sbutils.h>
564 +#include <bcmnvram.h>
565 +#include <bcmutils.h>
566 +#include <bcmendian.h>
567 +#include <bcmdevs.h>
568 +
569 +unsigned char bcm_ctype[] = {
570 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 0-7 */
571 + _BCM_C,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C,_BCM_C, /* 8-15 */
572 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 16-23 */
573 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 24-31 */
574 + _BCM_S|_BCM_SP,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 32-39 */
575 + _BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 40-47 */
576 + _BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D, /* 48-55 */
577 + _BCM_D,_BCM_D,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 56-63 */
578 + _BCM_P,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U, /* 64-71 */
579 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 72-79 */
580 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 80-87 */
581 + _BCM_U,_BCM_U,_BCM_U,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 88-95 */
582 + _BCM_P,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L, /* 96-103 */
583 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 104-111 */
584 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 112-119 */
585 + _BCM_L,_BCM_L,_BCM_L,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_C, /* 120-127 */
586 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 128-143 */
587 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 144-159 */
588 + _BCM_S|_BCM_SP,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 160-175 */
589 + _BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 176-191 */
590 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 192-207 */
591 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_P,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_L, /* 208-223 */
592 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 224-239 */
593 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_P,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L /* 240-255 */
594 +};
595 +
596 +uchar
597 +bcm_toupper(uchar c)
598 +{
599 + if (bcm_islower(c))
600 + c -= 'a'-'A';
601 + return (c);
602 +}
603 +
604 +ulong
605 +bcm_strtoul(char *cp, char **endp, uint base)
606 +{
607 + ulong result, value;
608 + bool minus;
609 +
610 + minus = FALSE;
611 +
612 + while (bcm_isspace(*cp))
613 + cp++;
614 +
615 + if (cp[0] == '+')
616 + cp++;
617 + else if (cp[0] == '-') {
618 + minus = TRUE;
619 + cp++;
620 + }
621 +
622 + if (base == 0) {
623 + if (cp[0] == '0') {
624 + if ((cp[1] == 'x') || (cp[1] == 'X')) {
625 + base = 16;
626 + cp = &cp[2];
627 + } else {
628 + base = 8;
629 + cp = &cp[1];
630 + }
631 + } else
632 + base = 10;
633 + } else if (base == 16 && (cp[0] == '0') && ((cp[1] == 'x') || (cp[1] == 'X'))) {
634 + cp = &cp[2];
635 + }
636 +
637 + result = 0;
638 +
639 + while (bcm_isxdigit(*cp) &&
640 + (value = bcm_isdigit(*cp) ? *cp-'0' : bcm_toupper(*cp)-'A'+10) < base) {
641 + result = result*base + value;
642 + cp++;
643 + }
644 +
645 + if (minus)
646 + result = (ulong)(result * -1);
647 +
648 + if (endp)
649 + *endp = (char *)cp;
650 +
651 + return (result);
652 +}
653 +
654 +uint
655 +bcm_atoi(char *s)
656 +{
657 + uint n;
658 +
659 + n = 0;
660 +
661 + while (bcm_isdigit(*s))
662 + n = (n * 10) + *s++ - '0';
663 + return (n);
664 +}
665 +
666 +/* return pointer to location of substring 'needle' in 'haystack' */
667 +char*
668 +bcmstrstr(char *haystack, char *needle)
669 +{
670 + int len, nlen;
671 + int i;
672 +
673 + if ((haystack == NULL) || (needle == NULL))
674 + return (haystack);
675 +
676 + nlen = strlen(needle);
677 + len = strlen(haystack) - nlen + 1;
678 +
679 + for (i = 0; i < len; i++)
680 + if (bcmp(needle, &haystack[i], nlen) == 0)
681 + return (&haystack[i]);
682 + return (NULL);
683 +}
684 +
685 +char*
686 +bcmstrcat(char *dest, const char *src)
687 +{
688 + strcpy(&dest[strlen(dest)], src);
689 + return (dest);
690 +}
691 +
692 +
693 +char*
694 +bcm_ether_ntoa(char *ea, char *buf)
695 +{
696 + sprintf(buf,"%02x:%02x:%02x:%02x:%02x:%02x",
697 + (uchar)ea[0]&0xff, (uchar)ea[1]&0xff, (uchar)ea[2]&0xff,
698 + (uchar)ea[3]&0xff, (uchar)ea[4]&0xff, (uchar)ea[5]&0xff);
699 + return (buf);
700 +}
701 +
702 +/* parse a xx:xx:xx:xx:xx:xx format ethernet address */
703 +int
704 +bcm_ether_atoe(char *p, char *ea)
705 +{
706 + int i = 0;
707 +
708 + for (;;) {
709 + ea[i++] = (char) bcm_strtoul(p, &p, 16);
710 + if (!*p++ || i == 6)
711 + break;
712 + }
713 +
714 + return (i == 6);
715 +}
716 +
717 +void
718 +bcm_mdelay(uint ms)
719 +{
720 + uint i;
721 +
722 + for (i = 0; i < ms; i++) {
723 + OSL_DELAY(1000);
724 + }
725 +}
726 +
727 +/*
728 + * Search the name=value vars for a specific one and return its value.
729 + * Returns NULL if not found.
730 + */
731 +char*
732 +getvar(char *vars, char *name)
733 +{
734 + char *s;
735 + int len;
736 +
737 + len = strlen(name);
738 +
739 + /* first look in vars[] */
740 + for (s = vars; s && *s; ) {
741 + if ((bcmp(s, name, len) == 0) && (s[len] == '='))
742 + return (&s[len+1]);
743 +
744 + while (*s++)
745 + ;
746 + }
747 +
748 + /* then query nvram */
749 + return (BCMINIT(nvram_get)(name));
750 +}
751 +
752 +/*
753 + * Search the vars for a specific one and return its value as
754 + * an integer. Returns 0 if not found.
755 + */
756 +int
757 +getintvar(char *vars, char *name)
758 +{
759 + char *val;
760 +
761 + if ((val = getvar(vars, name)) == NULL)
762 + return (0);
763 +
764 + return (bcm_strtoul(val, NULL, 0));
765 +}
766 +
767 +
768 +/* Search for token in comma separated token-string */
769 +static int
770 +findmatch(char *string, char *name)
771 +{
772 + uint len;
773 + char *c;
774 +
775 + len = strlen(name);
776 + while ((c = strchr(string, ',')) != NULL) {
777 + if (len == (uint)(c - string) && !strncmp(string, name, len))
778 + return 1;
779 + string = c + 1;
780 + }
781 +
782 + return (!strcmp(string, name));
783 +}
784 +
785 +/* Return gpio pin number assigned to the named pin */
786 +/*
787 +* Variable should be in format:
788 +*
789 +* gpio<N>=pin_name,pin_name
790 +*
791 +* This format allows multiple features to share the gpio with mutual
792 +* understanding.
793 +*
794 +* 'def_pin' is returned if a specific gpio is not defined for the requested functionality
795 +* and if def_pin is not used by others.
796 +*/
797 +uint
798 +getgpiopin(char *vars, char *pin_name, uint def_pin)
799 +{
800 + char name[] = "gpioXXXX";
801 + char *val;
802 + uint pin;
803 +
804 + /* Go thru all possibilities till a match in pin name */
805 + for (pin = 0; pin < GPIO_NUMPINS; pin ++) {
806 + sprintf(name, "gpio%d", pin);
807 + val = getvar(vars, name);
808 + if (val && findmatch(val, pin_name))
809 + return pin;
810 + }
811 +
812 + if (def_pin != GPIO_PIN_NOTDEFINED) {
813 + /* make sure the default pin is not used by someone else */
814 + sprintf(name, "gpio%d", def_pin);
815 + if (getvar(vars, name)) {
816 + def_pin = GPIO_PIN_NOTDEFINED;
817 + }
818 + }
819 +
820 + return def_pin;
821 +}
822 +
823 +
824 +/*******************************************************************************
825 + * crc8
826 + *
827 + * Computes a crc8 over the input data using the polynomial:
828 + *
829 + * x^8 + x^7 +x^6 + x^4 + x^2 + 1
830 + *
831 + * The caller provides the initial value (either CRC8_INIT_VALUE
832 + * or the previous returned value) to allow for processing of
833 + * discontiguous blocks of data. When generating the CRC the
834 + * caller is responsible for complementing the final return value
835 + * and inserting it into the byte stream. When checking, a final
836 + * return value of CRC8_GOOD_VALUE indicates a valid CRC.
837 + *
838 + * Reference: Dallas Semiconductor Application Note 27
839 + * Williams, Ross N., "A Painless Guide to CRC Error Detection Algorithms",
840 + * ver 3, Aug 1993, ross@guest.adelaide.edu.au, Rocksoft Pty Ltd.,
841 + * ftp://ftp.rocksoft.com/clients/rocksoft/papers/crc_v3.txt
842 + *
843 + ******************************************************************************/
844 +
845 +static uint8 crc8_table[256] = {
846 + 0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B,
847 + 0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21,
848 + 0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF,
849 + 0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5,
850 + 0x7F, 0x88, 0xC6, 0x31, 0x5A, 0xAD, 0xE3, 0x14,
851 + 0x35, 0xC2, 0x8C, 0x7B, 0x10, 0xE7, 0xA9, 0x5E,
852 + 0xEB, 0x1C, 0x52, 0xA5, 0xCE, 0x39, 0x77, 0x80,
853 + 0xA1, 0x56, 0x18, 0xEF, 0x84, 0x73, 0x3D, 0xCA,
854 + 0xFE, 0x09, 0x47, 0xB0, 0xDB, 0x2C, 0x62, 0x95,
855 + 0xB4, 0x43, 0x0D, 0xFA, 0x91, 0x66, 0x28, 0xDF,
856 + 0x6A, 0x9D, 0xD3, 0x24, 0x4F, 0xB8, 0xF6, 0x01,
857 + 0x20, 0xD7, 0x99, 0x6E, 0x05, 0xF2, 0xBC, 0x4B,
858 + 0x81, 0x76, 0x38, 0xCF, 0xA4, 0x53, 0x1D, 0xEA,
859 + 0xCB, 0x3C, 0x72, 0x85, 0xEE, 0x19, 0x57, 0xA0,
860 + 0x15, 0xE2, 0xAC, 0x5B, 0x30, 0xC7, 0x89, 0x7E,
861 + 0x5F, 0xA8, 0xE6, 0x11, 0x7A, 0x8D, 0xC3, 0x34,
862 + 0xAB, 0x5C, 0x12, 0xE5, 0x8E, 0x79, 0x37, 0xC0,
863 + 0xE1, 0x16, 0x58, 0xAF, 0xC4, 0x33, 0x7D, 0x8A,
864 + 0x3F, 0xC8, 0x86, 0x71, 0x1A, 0xED, 0xA3, 0x54,
865 + 0x75, 0x82, 0xCC, 0x3B, 0x50, 0xA7, 0xE9, 0x1E,
866 + 0xD4, 0x23, 0x6D, 0x9A, 0xF1, 0x06, 0x48, 0xBF,
867 + 0x9E, 0x69, 0x27, 0xD0, 0xBB, 0x4C, 0x02, 0xF5,
868 + 0x40, 0xB7, 0xF9, 0x0E, 0x65, 0x92, 0xDC, 0x2B,
869 + 0x0A, 0xFD, 0xB3, 0x44, 0x2F, 0xD8, 0x96, 0x61,
870 + 0x55, 0xA2, 0xEC, 0x1B, 0x70, 0x87, 0xC9, 0x3E,
871 + 0x1F, 0xE8, 0xA6, 0x51, 0x3A, 0xCD, 0x83, 0x74,
872 + 0xC1, 0x36, 0x78, 0x8F, 0xE4, 0x13, 0x5D, 0xAA,
873 + 0x8B, 0x7C, 0x32, 0xC5, 0xAE, 0x59, 0x17, 0xE0,
874 + 0x2A, 0xDD, 0x93, 0x64, 0x0F, 0xF8, 0xB6, 0x41,
875 + 0x60, 0x97, 0xD9, 0x2E, 0x45, 0xB2, 0xFC, 0x0B,
876 + 0xBE, 0x49, 0x07, 0xF0, 0x9B, 0x6C, 0x22, 0xD5,
877 + 0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F
878 +};
879 +
880 +#define CRC_INNER_LOOP(n, c, x) \
881 + (c) = ((c) >> 8) ^ crc##n##_table[((c) ^ (x)) & 0xff]
882 +
883 +uint8
884 +hndcrc8(
885 + uint8 *pdata, /* pointer to array of data to process */
886 + uint nbytes, /* number of input data bytes to process */
887 + uint8 crc /* either CRC8_INIT_VALUE or previous return value */
888 +)
889 +{
890 + /* hard code the crc loop instead of using CRC_INNER_LOOP macro
891 + * to avoid the undefined and unnecessary (uint8 >> 8) operation. */
892 + while (nbytes-- > 0)
893 + crc = crc8_table[(crc ^ *pdata++) & 0xff];
894 +
895 + return crc;
896 +}
897 +
898 +#ifdef notdef
899 +#define CLEN 1499
900 +#define CBUFSIZ (CLEN+4)
901 +#define CNBUFS 5
902 +
903 +#endif
904 diff -urN linux.old/arch/mips/bcm947xx/broadcom/cfe_env.c linux.dev/arch/mips/bcm947xx/broadcom/cfe_env.c
905 --- linux.old/arch/mips/bcm947xx/broadcom/cfe_env.c 1970-01-01 01:00:00.000000000 +0100
906 +++ linux.dev/arch/mips/bcm947xx/broadcom/cfe_env.c 2005-12-28 16:37:32.818257750 +0100
907 @@ -0,0 +1,234 @@
908 +/*
909 + * NVRAM variable manipulation (Linux kernel half)
910 + *
911 + * Copyright 2001-2003, Broadcom Corporation
912 + * All Rights Reserved.
913 + *
914 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
915 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
916 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
917 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
918 + *
919 + * $Id$
920 + */
921 +
922 +#include <linux/config.h>
923 +#include <linux/init.h>
924 +#include <linux/module.h>
925 +#include <linux/kernel.h>
926 +#include <linux/string.h>
927 +#include <asm/io.h>
928 +#include <asm/uaccess.h>
929 +
930 +#include <typedefs.h>
931 +#include <osl.h>
932 +#include <bcmendian.h>
933 +#include <bcmutils.h>
934 +
935 +#define NVRAM_SIZE (0x1ff0)
936 +static char _nvdata[NVRAM_SIZE] __initdata;
937 +static char _valuestr[256] __initdata;
938 +
939 +/*
940 + * TLV types. These codes are used in the "type-length-value"
941 + * encoding of the items stored in the NVRAM device (flash or EEPROM)
942 + *
943 + * The layout of the flash/nvram is as follows:
944 + *
945 + * <type> <length> <data ...> <type> <length> <data ...> <type_end>
946 + *
947 + * The type code of "ENV_TLV_TYPE_END" marks the end of the list.
948 + * The "length" field marks the length of the data section, not
949 + * including the type and length fields.
950 + *
951 + * Environment variables are stored as follows:
952 + *
953 + * <type_env> <length> <flags> <name> = <value>
954 + *
955 + * If bit 0 (low bit) is set, the length is an 8-bit value.
956 + * If bit 0 (low bit) is clear, the length is a 16-bit value
957 + *
958 + * Bit 7 set indicates "user" TLVs. In this case, bit 0 still
959 + * indicates the size of the length field.
960 + *
961 + * Flags are from the constants below:
962 + *
963 + */
964 +#define ENV_LENGTH_16BITS 0x00 /* for low bit */
965 +#define ENV_LENGTH_8BITS 0x01
966 +
967 +#define ENV_TYPE_USER 0x80
968 +
969 +#define ENV_CODE_SYS(n,l) (((n)<<1)|(l))
970 +#define ENV_CODE_USER(n,l) ((((n)<<1)|(l)) | ENV_TYPE_USER)
971 +
972 +/*
973 + * The actual TLV types we support
974 + */
975 +
976 +#define ENV_TLV_TYPE_END 0x00
977 +#define ENV_TLV_TYPE_ENV ENV_CODE_SYS(0,ENV_LENGTH_8BITS)
978 +
979 +/*
980 + * Environment variable flags
981 + */
982 +
983 +#define ENV_FLG_NORMAL 0x00 /* normal read/write */
984 +#define ENV_FLG_BUILTIN 0x01 /* builtin - not stored in flash */
985 +#define ENV_FLG_READONLY 0x02 /* read-only - cannot be changed */
986 +
987 +#define ENV_FLG_MASK 0xFF /* mask of attributes we keep */
988 +#define ENV_FLG_ADMIN 0x100 /* lets us internally override permissions */
989 +
990 +
991 +/* *********************************************************************
992 + * _nvram_read(buffer,offset,length)
993 + *
994 + * Read data from the NVRAM device
995 + *
996 + * Input parameters:
997 + * buffer - destination buffer
998 + * offset - offset of data to read
999 + * length - number of bytes to read
1000 + *
1001 + * Return value:
1002 + * number of bytes read, or <0 if error occured
1003 + ********************************************************************* */
1004 +static int
1005 +_nvram_read(unsigned char *nv_buf, unsigned char *buffer, int offset, int length)
1006 +{
1007 + int i;
1008 + if (offset > NVRAM_SIZE)
1009 + return -1;
1010 +
1011 + for ( i = 0; i < length; i++) {
1012 + buffer[i] = ((volatile unsigned char*)nv_buf)[offset + i];
1013 + }
1014 + return length;
1015 +}
1016 +
1017 +
1018 +static char*
1019 +_strnchr(const char *dest,int c,size_t cnt)
1020 +{
1021 + while (*dest && (cnt > 0)) {
1022 + if (*dest == c) return (char *) dest;
1023 + dest++;
1024 + cnt--;
1025 + }
1026 + return NULL;
1027 +}
1028 +
1029 +
1030 +
1031 +/*
1032 + * Core support API: Externally visible.
1033 + */
1034 +
1035 +/*
1036 + * Get the value of an NVRAM variable
1037 + * @param name name of variable to get
1038 + * @return value of variable or NULL if undefined
1039 + */
1040 +
1041 +char*
1042 +cfe_env_get(unsigned char *nv_buf, char* name)
1043 +{
1044 + int size;
1045 + unsigned char *buffer;
1046 + unsigned char *ptr;
1047 + unsigned char *envval;
1048 + unsigned int reclen;
1049 + unsigned int rectype;
1050 + int offset;
1051 + int flg;
1052 +
1053 + size = NVRAM_SIZE;
1054 + buffer = &_nvdata[0];
1055 +
1056 + ptr = buffer;
1057 + offset = 0;
1058 +
1059 + /* Read the record type and length */
1060 + if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
1061 + goto error;
1062 + }
1063 +
1064 + while ((*ptr != ENV_TLV_TYPE_END) && (size > 1)) {
1065 +
1066 + /* Adjust pointer for TLV type */
1067 + rectype = *(ptr);
1068 + offset++;
1069 + size--;
1070 +
1071 + /*
1072 + * Read the length. It can be either 1 or 2 bytes
1073 + * depending on the code
1074 + */
1075 + if (rectype & ENV_LENGTH_8BITS) {
1076 + /* Read the record type and length - 8 bits */
1077 + if (_nvram_read(nv_buf, ptr,offset,1) != 1) {
1078 + goto error;
1079 + }
1080 + reclen = *(ptr);
1081 + size--;
1082 + offset++;
1083 + }
1084 + else {
1085 + /* Read the record type and length - 16 bits, MSB first */
1086 + if (_nvram_read(nv_buf, ptr,offset,2) != 2) {
1087 + goto error;
1088 + }
1089 + reclen = (((unsigned int) *(ptr)) << 8) + (unsigned int) *(ptr+1);
1090 + size -= 2;
1091 + offset += 2;
1092 + }
1093 +
1094 + if (reclen > size)
1095 + break; /* should not happen, bad NVRAM */
1096 +
1097 + switch (rectype) {
1098 + case ENV_TLV_TYPE_ENV:
1099 + /* Read the TLV data */
1100 + if (_nvram_read(nv_buf, ptr,offset,reclen) != reclen)
1101 + goto error;
1102 + flg = *ptr++;
1103 + envval = (unsigned char *) _strnchr(ptr,'=',(reclen-1));
1104 + if (envval) {
1105 + *envval++ = '\0';
1106 + memcpy(_valuestr,envval,(reclen-1)-(envval-ptr));
1107 + _valuestr[(reclen-1)-(envval-ptr)] = '\0';
1108 +#if 0
1109 + printk(KERN_INFO "NVRAM:%s=%s\n", ptr, _valuestr);
1110 +#endif
1111 + if(!strcmp(ptr, name)){
1112 + return _valuestr;
1113 + }
1114 + if((strlen(ptr) > 1) && !strcmp(&ptr[1], name))
1115 + return _valuestr;
1116 + }
1117 + break;
1118 +
1119 + default:
1120 + /* Unknown TLV type, skip it. */
1121 + break;
1122 + }
1123 +
1124 + /*
1125 + * Advance to next TLV
1126 + */
1127 +
1128 + size -= (int)reclen;
1129 + offset += reclen;
1130 +
1131 + /* Read the next record type */
1132 + ptr = buffer;
1133 + if (_nvram_read(nv_buf, ptr,offset,1) != 1)
1134 + goto error;
1135 + }
1136 +
1137 +error:
1138 + return NULL;
1139 +
1140 +}
1141 +
1142 diff -urN linux.old/arch/mips/bcm947xx/broadcom/linux_osl.c linux.dev/arch/mips/bcm947xx/broadcom/linux_osl.c
1143 --- linux.old/arch/mips/bcm947xx/broadcom/linux_osl.c 1970-01-01 01:00:00.000000000 +0100
1144 +++ linux.dev/arch/mips/bcm947xx/broadcom/linux_osl.c 2005-12-28 16:37:32.834258750 +0100
1145 @@ -0,0 +1,102 @@
1146 +/*
1147 + * Linux OS Independent Layer
1148 + *
1149 + * Copyright 2005, Broadcom Corporation
1150 + * All Rights Reserved.
1151 + *
1152 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1153 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1154 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1155 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1156 + *
1157 + * $Id$
1158 + */
1159 +
1160 +#define LINUX_OSL
1161 +
1162 +#include <typedefs.h>
1163 +#include <bcmendian.h>
1164 +#include <linux/module.h>
1165 +#include <linuxver.h>
1166 +#include <osl.h>
1167 +#include <bcmutils.h>
1168 +#include <linux/delay.h>
1169 +#ifdef mips
1170 +#include <asm/paccess.h>
1171 +#endif
1172 +#include <pcicfg.h>
1173 +
1174 +#define PCI_CFG_RETRY 10
1175 +
1176 +#define OS_HANDLE_MAGIC 0x1234abcd
1177 +#define BCM_MEM_FILENAME_LEN 24
1178 +
1179 +typedef struct bcm_mem_link {
1180 + struct bcm_mem_link *prev;
1181 + struct bcm_mem_link *next;
1182 + uint size;
1183 + int line;
1184 + char file[BCM_MEM_FILENAME_LEN];
1185 +} bcm_mem_link_t;
1186 +
1187 +struct os_handle {
1188 + uint magic;
1189 + void *pdev;
1190 + uint malloced;
1191 + uint failed;
1192 + bcm_mem_link_t *dbgmem_list;
1193 +};
1194 +
1195 +uint32
1196 +osl_pci_read_config(osl_t *osh, uint offset, uint size)
1197 +{
1198 + uint val;
1199 + uint retry=PCI_CFG_RETRY;
1200 +
1201 + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
1202 +
1203 + /* only 4byte access supported */
1204 + ASSERT(size == 4);
1205 +
1206 + do {
1207 + pci_read_config_dword(osh->pdev, offset, &val);
1208 + if (val != 0xffffffff)
1209 + break;
1210 + } while (retry--);
1211 +
1212 +
1213 + return (val);
1214 +}
1215 +
1216 +void
1217 +osl_pci_write_config(osl_t *osh, uint offset, uint size, uint val)
1218 +{
1219 + uint retry=PCI_CFG_RETRY;
1220 +
1221 + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
1222 +
1223 + /* only 4byte access supported */
1224 + ASSERT(size == 4);
1225 +
1226 + do {
1227 + pci_write_config_dword(osh->pdev, offset, val);
1228 + if (offset!=PCI_BAR0_WIN)
1229 + break;
1230 + if (osl_pci_read_config(osh,offset,size) == val)
1231 + break;
1232 + } while (retry--);
1233 +
1234 +}
1235 +
1236 +void
1237 +osl_delay(uint usec)
1238 +{
1239 + uint d;
1240 +
1241 + while (usec > 0) {
1242 + d = MIN(usec, 1000);
1243 + udelay(d);
1244 + usec -= d;
1245 + }
1246 +}
1247 +
1248 diff -urN linux.old/arch/mips/bcm947xx/broadcom/nvram.c linux.dev/arch/mips/bcm947xx/broadcom/nvram.c
1249 --- linux.old/arch/mips/bcm947xx/broadcom/nvram.c 1970-01-01 01:00:00.000000000 +0100
1250 +++ linux.dev/arch/mips/bcm947xx/broadcom/nvram.c 2005-12-28 19:30:54.804469750 +0100
1251 @@ -0,0 +1,192 @@
1252 +/*
1253 + * NVRAM variable manipulation (Linux kernel half)
1254 + *
1255 + * Copyright 2005, Broadcom Corporation
1256 + * All Rights Reserved.
1257 + *
1258 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1259 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1260 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1261 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1262 + *
1263 + * $Id$
1264 + */
1265 +
1266 +#include <linux/config.h>
1267 +#include <linux/init.h>
1268 +#include <linux/module.h>
1269 +#include <linux/kernel.h>
1270 +#include <linux/string.h>
1271 +#include <linux/interrupt.h>
1272 +#include <linux/spinlock.h>
1273 +#include <linux/slab.h>
1274 +#include <asm/bootinfo.h>
1275 +#include <asm/addrspace.h>
1276 +#include <asm/io.h>
1277 +#include <asm/uaccess.h>
1278 +
1279 +#include <typedefs.h>
1280 +#include <bcmendian.h>
1281 +#include <bcmnvram.h>
1282 +#include <bcmutils.h>
1283 +#include <sbconfig.h>
1284 +#include <sbchipc.h>
1285 +#include <sbutils.h>
1286 +#include <sbmips.h>
1287 +#include <sflash.h>
1288 +
1289 +/* In BSS to minimize text size and page aligned so it can be mmap()-ed */
1290 +static char nvram_buf[NVRAM_SPACE] __attribute__((aligned(PAGE_SIZE)));
1291 +
1292 +/* Global SB handle */
1293 +extern void *sbh;
1294 +extern spinlock_t bcm947xx_sbh_lock;
1295 +static int cfe_env;
1296 +
1297 +extern char *cfe_env_get(char *nv_buf, const char *name);
1298 +
1299 +
1300 +/* Convenience */
1301 +#define sbh_lock bcm947xx_sbh_lock
1302 +#define KB * 1024
1303 +#define MB * 1024 * 1024
1304 +
1305 +/* Probe for NVRAM header */
1306 +static void __init
1307 +early_nvram_init(void)
1308 +{
1309 + struct nvram_header *header;
1310 + chipcregs_t *cc;
1311 + struct sflash *info = NULL;
1312 + int i;
1313 + uint32 base, off, lim;
1314 + u32 *src, *dst;
1315 +
1316 + cfe_env = 0;
1317 + if ((cc = sb_setcore(sbh, SB_CC, 0)) != NULL) {
1318 + base = KSEG1ADDR(SB_FLASH2);
1319 + switch (readl(&cc->capabilities) & CAP_FLASH_MASK) {
1320 + case PFLASH:
1321 + lim = SB_FLASH2_SZ;
1322 + break;
1323 +
1324 + case SFLASH_ST:
1325 + case SFLASH_AT:
1326 + if ((info = sflash_init(cc)) == NULL)
1327 + return;
1328 + lim = info->size;
1329 + break;
1330 +
1331 + case FLASH_NONE:
1332 + default:
1333 + return;
1334 + }
1335 + } else {
1336 + /* extif assumed, Stop at 4 MB */
1337 + base = KSEG1ADDR(SB_FLASH1);
1338 + lim = SB_FLASH1_SZ;
1339 + }
1340 +
1341 + /* XXX: hack for supporting the CFE environment stuff on WGT634U */
1342 + src = (u32 *) KSEG1ADDR(base + 8 * 1024 * 1024 - 0x2000);
1343 + dst = (u32 *) nvram_buf;
1344 + if ((lim == 0x02000000) && ((*src & 0xff00ff) == 0x000001)) {
1345 + printk("early_nvram_init: WGT634U NVRAM found.\n");
1346 +
1347 + for (i = 0; i < 0x1ff0; i++) {
1348 + if (*src == 0xFFFFFFFF)
1349 + break;
1350 + *dst++ = *src++;
1351 + }
1352 + cfe_env = 1;
1353 + return;
1354 + }
1355 +
1356 + off = FLASH_MIN;
1357 + while (off <= lim) {
1358 + /* Windowed flash access */
1359 + header = (struct nvram_header *) KSEG1ADDR(base + off - NVRAM_SPACE);
1360 + if (header->magic == NVRAM_MAGIC)
1361 + goto found;
1362 + off <<= 1;
1363 + }
1364 +
1365 + /* Try embedded NVRAM at 4 KB and 1 KB as last resorts */
1366 + header = (struct nvram_header *) KSEG1ADDR(base + 4 KB);
1367 + if (header->magic == NVRAM_MAGIC)
1368 + goto found;
1369 +
1370 + header = (struct nvram_header *) KSEG1ADDR(base + 1 KB);
1371 + if (header->magic == NVRAM_MAGIC)
1372 + goto found;
1373 +
1374 + return;
1375 +
1376 +found:
1377 + src = (u32 *) header;
1378 + dst = (u32 *) nvram_buf;
1379 + for (i = 0; i < sizeof(struct nvram_header); i += 4)
1380 + *dst++ = *src++;
1381 + for (; i < header->len && i < NVRAM_SPACE; i += 4)
1382 + *dst++ = ltoh32(*src++);
1383 +}
1384 +
1385 +/* Early (before mm or mtd) read-only access to NVRAM */
1386 +char * __init early_nvram_get(const char *name)
1387 +{
1388 + char *var, *value, *end, *eq;
1389 +
1390 + if (!name)
1391 + return NULL;
1392 +
1393 + /* Too early? */
1394 + if (sbh == NULL)
1395 + return NULL;
1396 +
1397 + if (!nvram_buf[0])
1398 + early_nvram_init();
1399 +
1400 + if (cfe_env)
1401 + return cfe_env_get(nvram_buf, name);
1402 +
1403 + /* Look for name=value and return value */
1404 + var = &nvram_buf[sizeof(struct nvram_header)];
1405 + end = nvram_buf + sizeof(nvram_buf) - 2;
1406 + end[0] = end[1] = '\0';
1407 + for (; *var; var = value + strlen(value) + 1) {
1408 + if (!(eq = strchr(var, '=')))
1409 + break;
1410 + value = eq + 1;
1411 + if ((eq - var) == strlen(name) && strncmp(var, name, (eq - var)) == 0)
1412 + return value;
1413 + }
1414 +
1415 + return NULL;
1416 +}
1417 +
1418 +char *nvram_get(const char *name)
1419 +{
1420 + char *var, *value, *end, *eq;
1421 +
1422 + if (!name)
1423 + return NULL;
1424 +
1425 + if (!nvram_buf[0])
1426 + return NULL;
1427 +
1428 + /* Look for name=value and return value */
1429 + var = &nvram_buf[sizeof(struct nvram_header)];
1430 + end = nvram_buf + sizeof(nvram_buf) - 2;
1431 + end[0] = end[1] = '\0';
1432 + for (; *var; var = value + strlen(value) + 1) {
1433 + if (!(eq = strchr(var, '=')))
1434 + break;
1435 + value = eq + 1;
1436 + if ((eq - var) == strlen(name) && strncmp(var, name, (eq - var)) == 0)
1437 + return value;
1438 + }
1439 +
1440 + return NULL;
1441 +}
1442 +
1443 +EXPORT_SYMBOL(nvram_get);
1444 diff -urN linux.old/arch/mips/bcm947xx/broadcom/sbmips.c linux.dev/arch/mips/bcm947xx/broadcom/sbmips.c
1445 --- linux.old/arch/mips/bcm947xx/broadcom/sbmips.c 1970-01-01 01:00:00.000000000 +0100
1446 +++ linux.dev/arch/mips/bcm947xx/broadcom/sbmips.c 2005-12-28 19:19:50.570957750 +0100
1447 @@ -0,0 +1,1038 @@
1448 +/*
1449 + * BCM47XX Sonics SiliconBackplane MIPS core routines
1450 + *
1451 + * Copyright 2005, Broadcom Corporation
1452 + * All Rights Reserved.
1453 + *
1454 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1455 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1456 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1457 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1458 + *
1459 + * $Id$
1460 + */
1461 +
1462 +#include <typedefs.h>
1463 +#include <osl.h>
1464 +#include <sbutils.h>
1465 +#include <bcmdevs.h>
1466 +#include <bcmnvram.h>
1467 +#include <bcmutils.h>
1468 +#include <hndmips.h>
1469 +#include <sbconfig.h>
1470 +#include <sbextif.h>
1471 +#include <sbchipc.h>
1472 +#include <sbmemc.h>
1473 +#include <mipsinc.h>
1474 +#include <sbutils.h>
1475 +
1476 +/*
1477 + * Returns TRUE if an external UART exists at the given base
1478 + * register.
1479 + */
1480 +static bool
1481 +BCMINITFN(serial_exists)(uint8 *regs)
1482 +{
1483 + uint8 save_mcr, status1;
1484 +
1485 + save_mcr = R_REG(&regs[UART_MCR]);
1486 + W_REG(&regs[UART_MCR], UART_MCR_LOOP | 0x0a);
1487 + status1 = R_REG(&regs[UART_MSR]) & 0xf0;
1488 + W_REG(&regs[UART_MCR], save_mcr);
1489 +
1490 + return (status1 == 0x90);
1491 +}
1492 +
1493 +/*
1494 + * Initializes UART access. The callback function will be called once
1495 + * per found UART.
1496 + */
1497 +void
1498 +BCMINITFN(sb_serial_init)(sb_t *sbh, void (*add)(void *regs, uint irq, uint baud_base, uint reg_shift))
1499 +{
1500 + void *regs;
1501 + ulong base;
1502 + uint irq;
1503 + int i, n;
1504 +
1505 + if ((regs = sb_setcore(sbh, SB_EXTIF, 0))) {
1506 + extifregs_t *eir = (extifregs_t *) regs;
1507 + sbconfig_t *sb;
1508 +
1509 + /* Determine external UART register base */
1510 + sb = (sbconfig_t *)((ulong) eir + SBCONFIGOFF);
1511 + base = EXTIF_CFGIF_BASE(sb_base(R_REG(&sb->sbadmatch1)));
1512 +
1513 + /* Determine IRQ */
1514 + irq = sb_irq(sbh);
1515 +
1516 + /* Disable GPIO interrupt initially */
1517 + W_REG(&eir->gpiointpolarity, 0);
1518 + W_REG(&eir->gpiointmask, 0);
1519 +
1520 + /* Search for external UARTs */
1521 + n = 2;
1522 + for (i = 0; i < 2; i++) {
1523 + regs = (void *) REG_MAP(base + (i * 8), 8);
1524 + if (BCMINIT(serial_exists)(regs)) {
1525 + /* Set GPIO 1 to be the external UART IRQ */
1526 + W_REG(&eir->gpiointmask, 2);
1527 + if (add)
1528 + add(regs, irq, 13500000, 0);
1529 + }
1530 + }
1531 +
1532 + /* Add internal UART if enabled */
1533 + if (R_REG(&eir->corecontrol) & CC_UE)
1534 + if (add)
1535 + add((void *) &eir->uartdata, irq, sb_clock(sbh), 2);
1536 + } else if ((regs = sb_setcore(sbh, SB_CC, 0))) {
1537 + chipcregs_t *cc = (chipcregs_t *) regs;
1538 + uint32 rev, cap, pll, baud_base, div;
1539 +
1540 + /* Determine core revision and capabilities */
1541 + rev = sb_corerev(sbh);
1542 + cap = R_REG(&cc->capabilities);
1543 + pll = cap & CAP_PLL_MASK;
1544 +
1545 + /* Determine IRQ */
1546 + irq = sb_irq(sbh);
1547 +
1548 + if (pll == PLL_TYPE1) {
1549 + /* PLL clock */
1550 + baud_base = sb_clock_rate(pll,
1551 + R_REG(&cc->clockcontrol_n),
1552 + R_REG(&cc->clockcontrol_m2));
1553 + div = 1;
1554 + } else {
1555 + if (rev >= 11) {
1556 + /* Fixed ALP clock */
1557 + baud_base = 20000000;
1558 + div = 1;
1559 + /* Set the override bit so we don't divide it */
1560 + W_REG(&cc->corecontrol, CC_UARTCLKO);
1561 + } else if (rev >= 3) {
1562 + /* Internal backplane clock */
1563 + baud_base = sb_clock(sbh);
1564 + div = 2; /* Minimum divisor */
1565 + W_REG(&cc->clkdiv,
1566 + ((R_REG(&cc->clkdiv) & ~CLKD_UART) | div));
1567 + } else {
1568 + /* Fixed internal backplane clock */
1569 + baud_base = 88000000;
1570 + div = 48;
1571 + }
1572 +
1573 + /* Clock source depends on strapping if UartClkOverride is unset */
1574 + if ((rev > 0) &&
1575 + ((R_REG(&cc->corecontrol) & CC_UARTCLKO) == 0)) {
1576 + if ((cap & CAP_UCLKSEL) == CAP_UINTCLK) {
1577 + /* Internal divided backplane clock */
1578 + baud_base /= div;
1579 + } else {
1580 + /* Assume external clock of 1.8432 MHz */
1581 + baud_base = 1843200;
1582 + }
1583 + }
1584 + }
1585 +
1586 + /* Add internal UARTs */
1587 + n = cap & CAP_UARTS_MASK;
1588 + for (i = 0; i < n; i++) {
1589 + /* Register offset changed after revision 0 */
1590 + if (rev)
1591 + regs = (void *)((ulong) &cc->uart0data + (i * 256));
1592 + else
1593 + regs = (void *)((ulong) &cc->uart0data + (i * 8));
1594 +
1595 + if (add)
1596 + add(regs, irq, baud_base, 0);
1597 + }
1598 + }
1599 +}
1600 +
1601 +/*
1602 + * Initialize jtag master and return handle for
1603 + * jtag_rwreg. Returns NULL on failure.
1604 + */
1605 +void *
1606 +sb_jtagm_init(sb_t *sbh, uint clkd, bool exttap)
1607 +{
1608 + void *regs;
1609 +
1610 + if ((regs = sb_setcore(sbh, SB_CC, 0)) != NULL) {
1611 + chipcregs_t *cc = (chipcregs_t *) regs;
1612 + uint32 tmp;
1613 +
1614 + /*
1615 + * Determine jtagm availability from
1616 + * core revision and capabilities.
1617 + */
1618 + tmp = sb_corerev(sbh);
1619 + /*
1620 + * Corerev 10 has jtagm, but the only chip
1621 + * with it does not have a mips, and
1622 + * the layout of the jtagcmd register is
1623 + * different. We'll only accept >= 11.
1624 + */
1625 + if (tmp < 11)
1626 + return (NULL);
1627 +
1628 + tmp = R_REG(&cc->capabilities);
1629 + if ((tmp & CAP_JTAGP) == 0)
1630 + return (NULL);
1631 +
1632 + /* Set clock divider if requested */
1633 + if (clkd != 0) {
1634 + tmp = R_REG(&cc->clkdiv);
1635 + tmp = (tmp & ~CLKD_JTAG) |
1636 + ((clkd << CLKD_JTAG_SHIFT) & CLKD_JTAG);
1637 + W_REG(&cc->clkdiv, tmp);
1638 + }
1639 +
1640 + /* Enable jtagm */
1641 + tmp = JCTRL_EN | (exttap ? JCTRL_EXT_EN : 0);
1642 + W_REG(&cc->jtagctrl, tmp);
1643 + }
1644 +
1645 + return (regs);
1646 +}
1647 +
1648 +void
1649 +sb_jtagm_disable(void *h)
1650 +{
1651 + chipcregs_t *cc = (chipcregs_t *)h;
1652 +
1653 + W_REG(&cc->jtagctrl, R_REG(&cc->jtagctrl) & ~JCTRL_EN);
1654 +}
1655 +
1656 +/*
1657 + * Read/write a jtag register. Assumes a target with
1658 + * 8 bit IR and 32 bit DR.
1659 + */
1660 +#define IRWIDTH 8
1661 +#define DRWIDTH 32
1662 +uint32
1663 +jtag_rwreg(void *h, uint32 ir, uint32 dr)
1664 +{
1665 + chipcregs_t *cc = (chipcregs_t *) h;
1666 + uint32 tmp;
1667 +
1668 + W_REG(&cc->jtagir, ir);
1669 + W_REG(&cc->jtagdr, dr);
1670 + tmp = JCMD_START | JCMD_ACC_IRDR |
1671 + ((IRWIDTH - 1) << JCMD_IRW_SHIFT) |
1672 + (DRWIDTH - 1);
1673 + W_REG(&cc->jtagcmd, tmp);
1674 + while (((tmp = R_REG(&cc->jtagcmd)) & JCMD_BUSY) == JCMD_BUSY) {
1675 + /* OSL_DELAY(1); */
1676 + }
1677 +
1678 + tmp = R_REG(&cc->jtagdr);
1679 + return (tmp);
1680 +}
1681 +
1682 +/* Returns the SB interrupt flag of the current core. */
1683 +uint32
1684 +sb_flag(sb_t *sbh)
1685 +{
1686 + void *regs;
1687 + sbconfig_t *sb;
1688 +
1689 + regs = sb_coreregs(sbh);
1690 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
1691 +
1692 + return (R_REG(&sb->sbtpsflag) & SBTPS_NUM0_MASK);
1693 +}
1694 +
1695 +static const uint32 sbips_int_mask[] = {
1696 + 0,
1697 + SBIPS_INT1_MASK,
1698 + SBIPS_INT2_MASK,
1699 + SBIPS_INT3_MASK,
1700 + SBIPS_INT4_MASK
1701 +};
1702 +
1703 +static const uint32 sbips_int_shift[] = {
1704 + 0,
1705 + 0,
1706 + SBIPS_INT2_SHIFT,
1707 + SBIPS_INT3_SHIFT,
1708 + SBIPS_INT4_SHIFT
1709 +};
1710 +
1711 +/*
1712 + * Returns the MIPS IRQ assignment of the current core. If unassigned,
1713 + * 0 is returned.
1714 + */
1715 +uint
1716 +sb_irq(sb_t *sbh)
1717 +{
1718 + uint idx;
1719 + void *regs;
1720 + sbconfig_t *sb;
1721 + uint32 flag, sbipsflag;
1722 + uint irq = 0;
1723 +
1724 + flag = sb_flag(sbh);
1725 +
1726 + idx = sb_coreidx(sbh);
1727 +
1728 + if ((regs = sb_setcore(sbh, SB_MIPS, 0)) ||
1729 + (regs = sb_setcore(sbh, SB_MIPS33, 0))) {
1730 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
1731 +
1732 + /* sbipsflag specifies which core is routed to interrupts 1 to 4 */
1733 + sbipsflag = R_REG(&sb->sbipsflag);
1734 + for (irq = 1; irq <= 4; irq++) {
1735 + if (((sbipsflag & sbips_int_mask[irq]) >> sbips_int_shift[irq]) == flag)
1736 + break;
1737 + }
1738 + if (irq == 5)
1739 + irq = 0;
1740 + }
1741 +
1742 + sb_setcoreidx(sbh, idx);
1743 +
1744 + return irq;
1745 +}
1746 +
1747 +/* Clears the specified MIPS IRQ. */
1748 +static void
1749 +BCMINITFN(sb_clearirq)(sb_t *sbh, uint irq)
1750 +{
1751 + void *regs;
1752 + sbconfig_t *sb;
1753 +
1754 + if (!(regs = sb_setcore(sbh, SB_MIPS, 0)) &&
1755 + !(regs = sb_setcore(sbh, SB_MIPS33, 0)))
1756 + ASSERT(regs);
1757 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
1758 +
1759 + if (irq == 0)
1760 + W_REG(&sb->sbintvec, 0);
1761 + else
1762 + OR_REG(&sb->sbipsflag, sbips_int_mask[irq]);
1763 +}
1764 +
1765 +/*
1766 + * Assigns the specified MIPS IRQ to the specified core. Shared MIPS
1767 + * IRQ 0 may be assigned more than once.
1768 + */
1769 +static void
1770 +BCMINITFN(sb_setirq)(sb_t *sbh, uint irq, uint coreid, uint coreunit)
1771 +{
1772 + void *regs;
1773 + sbconfig_t *sb;
1774 + uint32 flag;
1775 +
1776 + regs = sb_setcore(sbh, coreid, coreunit);
1777 + ASSERT(regs);
1778 + flag = sb_flag(sbh);
1779 +
1780 + if (!(regs = sb_setcore(sbh, SB_MIPS, 0)) &&
1781 + !(regs = sb_setcore(sbh, SB_MIPS33, 0)))
1782 + ASSERT(regs);
1783 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
1784 +
1785 + if (irq == 0)
1786 + OR_REG(&sb->sbintvec, 1 << flag);
1787 + else {
1788 + flag <<= sbips_int_shift[irq];
1789 + ASSERT(!(flag & ~sbips_int_mask[irq]));
1790 + flag |= R_REG(&sb->sbipsflag) & ~sbips_int_mask[irq];
1791 + W_REG(&sb->sbipsflag, flag);
1792 + }
1793 +}
1794 +
1795 +/*
1796 + * Initializes clocks and interrupts. SB and NVRAM access must be
1797 + * initialized prior to calling.
1798 + */
1799 +void
1800 +BCMINITFN(sb_mips_init)(sb_t *sbh)
1801 +{
1802 + ulong hz, ns, tmp;
1803 + extifregs_t *eir;
1804 + chipcregs_t *cc;
1805 + char *value;
1806 + uint irq;
1807 +
1808 + /* Figure out current SB clock speed */
1809 + if ((hz = sb_clock(sbh)) == 0)
1810 + hz = 100000000;
1811 + ns = 1000000000 / hz;
1812 +
1813 + /* Setup external interface timing */
1814 + if ((eir = sb_setcore(sbh, SB_EXTIF, 0))) {
1815 + /* Initialize extif so we can get to the LEDs and external UART */
1816 + W_REG(&eir->prog_config, CF_EN);
1817 +
1818 + /* Set timing for the flash */
1819 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
1820 + tmp = tmp | (CEIL(40, ns) << FW_W1_SHIFT); /* W1 = 40nS */
1821 + tmp = tmp | CEIL(120, ns); /* W0 = 120nS */
1822 + W_REG(&eir->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
1823 +
1824 + /* Set programmable interface timing for external uart */
1825 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
1826 + tmp = tmp | (CEIL(20, ns) << FW_W2_SHIFT); /* W2 = 20nS */
1827 + tmp = tmp | (CEIL(100, ns) << FW_W1_SHIFT); /* W1 = 100nS */
1828 + tmp = tmp | CEIL(120, ns); /* W0 = 120nS */
1829 + W_REG(&eir->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
1830 + } else if ((cc = sb_setcore(sbh, SB_CC, 0))) {
1831 + /* Set timing for the flash */
1832 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
1833 + tmp |= CEIL(10, ns) << FW_W1_SHIFT; /* W1 = 10nS */
1834 + tmp |= CEIL(120, ns); /* W0 = 120nS */
1835 +
1836 + // Added by Chen-I for 5365
1837 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID)
1838 + {
1839 + W_REG(&cc->flash_waitcount, tmp);
1840 + W_REG(&cc->pcmcia_memwait, tmp);
1841 + }
1842 + else
1843 + {
1844 + if (sb_corerev(sbh) < 9)
1845 + W_REG(&cc->flash_waitcount, tmp);
1846 +
1847 + if ((sb_corerev(sbh) < 9) ||
1848 + ((BCMINIT(sb_chip)(sbh) == BCM5350_DEVICE_ID) && BCMINIT(sb_chiprev)(sbh) == 0)) {
1849 + W_REG(&cc->pcmcia_memwait, tmp);
1850 + }
1851 + }
1852 + }
1853 +
1854 + /* Chip specific initialization */
1855 + switch (BCMINIT(sb_chip)(sbh)) {
1856 + case BCM4710_DEVICE_ID:
1857 + /* Clear interrupt map */
1858 + for (irq = 0; irq <= 4; irq++)
1859 + BCMINIT(sb_clearirq)(sbh, irq);
1860 + BCMINIT(sb_setirq)(sbh, 0, SB_CODEC, 0);
1861 + BCMINIT(sb_setirq)(sbh, 0, SB_EXTIF, 0);
1862 + BCMINIT(sb_setirq)(sbh, 2, SB_ENET, 1);
1863 + BCMINIT(sb_setirq)(sbh, 3, SB_ILINE20, 0);
1864 + BCMINIT(sb_setirq)(sbh, 4, SB_PCI, 0);
1865 + ASSERT(eir);
1866 + value = BCMINIT(early_nvram_get)("et0phyaddr");
1867 + if (value && !strcmp(value, "31")) {
1868 + /* Enable internal UART */
1869 + W_REG(&eir->corecontrol, CC_UE);
1870 + /* Give USB its own interrupt */
1871 + BCMINIT(sb_setirq)(sbh, 1, SB_USB, 0);
1872 + } else {
1873 + /* Disable internal UART */
1874 + W_REG(&eir->corecontrol, 0);
1875 + /* Give Ethernet its own interrupt */
1876 + BCMINIT(sb_setirq)(sbh, 1, SB_ENET, 0);
1877 + BCMINIT(sb_setirq)(sbh, 0, SB_USB, 0);
1878 + }
1879 + break;
1880 + case BCM5350_DEVICE_ID:
1881 + /* Clear interrupt map */
1882 + for (irq = 0; irq <= 4; irq++)
1883 + BCMINIT(sb_clearirq)(sbh, irq);
1884 + BCMINIT(sb_setirq)(sbh, 0, SB_CC, 0);
1885 + BCMINIT(sb_setirq)(sbh, 1, SB_D11, 0);
1886 + BCMINIT(sb_setirq)(sbh, 2, SB_ENET, 0);
1887 + BCMINIT(sb_setirq)(sbh, 3, SB_PCI, 0);
1888 + BCMINIT(sb_setirq)(sbh, 4, SB_USB, 0);
1889 + break;
1890 + }
1891 +}
1892 +
1893 +uint32
1894 +BCMINITFN(sb_mips_clock)(sb_t *sbh)
1895 +{
1896 + extifregs_t *eir;
1897 + chipcregs_t *cc;
1898 + uint32 n, m;
1899 + uint idx;
1900 + uint32 pll_type, rate = 0;
1901 +
1902 + /* get index of the current core */
1903 + idx = sb_coreidx(sbh);
1904 + pll_type = PLL_TYPE1;
1905 +
1906 + /* switch to extif or chipc core */
1907 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
1908 + n = R_REG(&eir->clockcontrol_n);
1909 + m = R_REG(&eir->clockcontrol_sb);
1910 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
1911 + pll_type = R_REG(&cc->capabilities) & CAP_PLL_MASK;
1912 + n = R_REG(&cc->clockcontrol_n);
1913 + if ((pll_type == PLL_TYPE2) ||
1914 + (pll_type == PLL_TYPE4) ||
1915 + (pll_type == PLL_TYPE6) ||
1916 + (pll_type == PLL_TYPE7))
1917 + m = R_REG(&cc->clockcontrol_mips);
1918 + else if (pll_type == PLL_TYPE5) {
1919 + rate = 200000000;
1920 + goto out;
1921 + }
1922 + else if (pll_type == PLL_TYPE3) {
1923 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID) { /* 5365 is also type3 */
1924 + rate = 200000000;
1925 + goto out;
1926 + } else
1927 + m = R_REG(&cc->clockcontrol_m2); /* 5350 uses m2 to control mips */
1928 + } else
1929 + m = R_REG(&cc->clockcontrol_sb);
1930 + } else
1931 + goto out;
1932 +
1933 + // Added by Chen-I for 5365
1934 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID)
1935 + rate = 100000000;
1936 + else
1937 + /* calculate rate */
1938 + rate = sb_clock_rate(pll_type, n, m);
1939 +
1940 + if (pll_type == PLL_TYPE6)
1941 + rate = SB2MIPS_T6(rate);
1942 +
1943 +out:
1944 + /* switch back to previous core */
1945 + sb_setcoreidx(sbh, idx);
1946 +
1947 + return rate;
1948 +}
1949 +
1950 +#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4)
1951 +
1952 +static void
1953 +BCMINITFN(handler)(void)
1954 +{
1955 + /* Step 11 */
1956 + __asm__ (
1957 + ".set\tmips32\n\t"
1958 + "ssnop\n\t"
1959 + "ssnop\n\t"
1960 + /* Disable interrupts */
1961 + /* MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) & ~(ALLINTS | STO_IE)); */
1962 + "mfc0 $15, $12\n\t"
1963 + /* Just a Hack to not to use reg 'at' which was causing problems on 4704 A2 */
1964 + "li $14, -31746\n\t"
1965 + "and $15, $15, $14\n\t"
1966 + "mtc0 $15, $12\n\t"
1967 + "eret\n\t"
1968 + "nop\n\t"
1969 + "nop\n\t"
1970 + ".set\tmips0"
1971 + );
1972 +}
1973 +
1974 +/* The following MUST come right after handler() */
1975 +static void
1976 +BCMINITFN(afterhandler)(void)
1977 +{
1978 +}
1979 +
1980 +/*
1981 + * Set the MIPS, backplane and PCI clocks as closely as possible.
1982 + */
1983 +bool
1984 +BCMINITFN(sb_mips_setclock)(sb_t *sbh, uint32 mipsclock, uint32 sbclock, uint32 pciclock)
1985 +{
1986 + extifregs_t *eir = NULL;
1987 + chipcregs_t *cc = NULL;
1988 + mipsregs_t *mipsr = NULL;
1989 + volatile uint32 *clockcontrol_n, *clockcontrol_sb, *clockcontrol_pci, *clockcontrol_m2;
1990 + uint32 orig_n, orig_sb, orig_pci, orig_m2, orig_mips, orig_ratio_parm, orig_ratio_cfg;
1991 + uint32 pll_type, sync_mode;
1992 + uint ic_size, ic_lsize;
1993 + uint idx, i;
1994 + typedef struct {
1995 + uint32 mipsclock;
1996 + uint16 n;
1997 + uint32 sb;
1998 + uint32 pci33;
1999 + uint32 pci25;
2000 + } n3m_table_t;
2001 + static n3m_table_t BCMINITDATA(type1_table)[] = {
2002 + { 96000000, 0x0303, 0x04020011, 0x11030011, 0x11050011 }, /* 96.000 32.000 24.000 */
2003 + { 100000000, 0x0009, 0x04020011, 0x11030011, 0x11050011 }, /* 100.000 33.333 25.000 */
2004 + { 104000000, 0x0802, 0x04020011, 0x11050009, 0x11090009 }, /* 104.000 31.200 24.960 */
2005 + { 108000000, 0x0403, 0x04020011, 0x11050009, 0x02000802 }, /* 108.000 32.400 24.923 */
2006 + { 112000000, 0x0205, 0x04020011, 0x11030021, 0x02000403 }, /* 112.000 32.000 24.889 */
2007 + { 115200000, 0x0303, 0x04020009, 0x11030011, 0x11050011 }, /* 115.200 32.000 24.000 */
2008 + { 120000000, 0x0011, 0x04020011, 0x11050011, 0x11090011 }, /* 120.000 30.000 24.000 */
2009 + { 124800000, 0x0802, 0x04020009, 0x11050009, 0x11090009 }, /* 124.800 31.200 24.960 */
2010 + { 128000000, 0x0305, 0x04020011, 0x11050011, 0x02000305 }, /* 128.000 32.000 24.000 */
2011 + { 132000000, 0x0603, 0x04020011, 0x11050011, 0x02000305 }, /* 132.000 33.000 24.750 */
2012 + { 136000000, 0x0c02, 0x04020011, 0x11090009, 0x02000603 }, /* 136.000 32.640 24.727 */
2013 + { 140000000, 0x0021, 0x04020011, 0x11050021, 0x02000c02 }, /* 140.000 30.000 24.706 */
2014 + { 144000000, 0x0405, 0x04020011, 0x01020202, 0x11090021 }, /* 144.000 30.857 24.686 */
2015 + { 150857142, 0x0605, 0x04020021, 0x02000305, 0x02000605 }, /* 150.857 33.000 24.000 */
2016 + { 152000000, 0x0e02, 0x04020011, 0x11050021, 0x02000e02 }, /* 152.000 32.571 24.000 */
2017 + { 156000000, 0x0802, 0x04020005, 0x11050009, 0x11090009 }, /* 156.000 31.200 24.960 */
2018 + { 160000000, 0x0309, 0x04020011, 0x11090011, 0x02000309 }, /* 160.000 32.000 24.000 */
2019 + { 163200000, 0x0c02, 0x04020009, 0x11090009, 0x02000603 }, /* 163.200 32.640 24.727 */
2020 + { 168000000, 0x0205, 0x04020005, 0x11030021, 0x02000403 }, /* 168.000 32.000 24.889 */
2021 + { 176000000, 0x0602, 0x04020003, 0x11050005, 0x02000602 }, /* 176.000 33.000 24.000 */
2022 + };
2023 + typedef struct {
2024 + uint32 mipsclock;
2025 + uint16 n;
2026 + uint32 m2; /* that is the clockcontrol_m2 */
2027 + } type3_table_t;
2028 + static type3_table_t type3_table[] = { /* for 5350, mips clock is always double sb clock */
2029 + { 150000000, 0x311, 0x4020005 },
2030 + { 200000000, 0x311, 0x4020003 },
2031 + };
2032 + typedef struct {
2033 + uint32 mipsclock;
2034 + uint32 sbclock;
2035 + uint16 n;
2036 + uint32 sb;
2037 + uint32 pci33;
2038 + uint32 m2;
2039 + uint32 m3;
2040 + uint32 ratio_cfg;
2041 + uint32 ratio_parm;
2042 + } n4m_table_t;
2043 +
2044 + static n4m_table_t BCMINITDATA(type2_table)[] = {
2045 + { 180000000, 80000000, 0x0403, 0x01010000, 0x01020300, 0x01020600, 0x05000100, 8, 0x012a00a9 },
2046 + { 180000000, 90000000, 0x0403, 0x01000100, 0x01020300, 0x01000100, 0x05000100, 11, 0x0aaa0555 },
2047 + { 200000000, 100000000, 0x0303, 0x02010000, 0x02040001, 0x02010000, 0x06000001, 11, 0x0aaa0555 },
2048 + { 211200000, 105600000, 0x0902, 0x01000200, 0x01030400, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
2049 + { 220800000, 110400000, 0x1500, 0x01000200, 0x01030400, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
2050 + { 230400000, 115200000, 0x0604, 0x01000200, 0x01020600, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
2051 + { 234000000, 104000000, 0x0b01, 0x01010000, 0x01010700, 0x01020600, 0x05000100, 8, 0x012a00a9 },
2052 + { 240000000, 120000000, 0x0803, 0x01000200, 0x01020600, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
2053 + { 252000000, 126000000, 0x0504, 0x01000100, 0x01020500, 0x01000100, 0x05000100, 11, 0x0aaa0555 },
2054 + { 264000000, 132000000, 0x0903, 0x01000200, 0x01020700, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
2055 + { 270000000, 120000000, 0x0703, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 8, 0x012a00a9 },
2056 + { 276000000, 122666666, 0x1500, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 8, 0x012a00a9 },
2057 + { 280000000, 140000000, 0x0503, 0x01000000, 0x01010600, 0x01000000, 0x05000000, 11, 0x0aaa0555 },
2058 + { 288000000, 128000000, 0x0604, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 8, 0x012a00a9 },
2059 + { 288000000, 144000000, 0x0404, 0x01000000, 0x01010600, 0x01000000, 0x05000000, 11, 0x0aaa0555 },
2060 + { 300000000, 133333333, 0x0803, 0x01010000, 0x01020600, 0x01020600, 0x05000100, 8, 0x012a00a9 },
2061 + { 300000000, 150000000, 0x0803, 0x01000100, 0x01020600, 0x01000100, 0x05000100, 11, 0x0aaa0555 }
2062 + };
2063 +
2064 + static n4m_table_t BCMINITDATA(type4_table)[] = {
2065 + { 192000000, 96000000, 0x0702, 0x04000011, 0x11030011, 0x04000011, 0x04000003, 11, 0x0aaa0555 },
2066 + { 198000000, 99000000, 0x0603, 0x11020005, 0x11030011, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2067 + { 200000000, 100000000, 0x0009, 0x04020011, 0x11030011, 0x04020011, 0x04020003, 11, 0x0aaa0555 },
2068 + { 204000000, 102000000, 0x0c02, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2069 + { 208000000, 104000000, 0x0802, 0x11030002, 0x11090005, 0x11030002, 0x04000003, 11, 0x0aaa0555 },
2070 + { 210000000, 105000000, 0x0209, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2071 + { 216000000, 108000000, 0x0111, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2072 + { 224000000, 112000000, 0x0205, 0x11030002, 0x02002103, 0x11030002, 0x04000003, 11, 0x0aaa0555 },
2073 + { 228000000, 101333333, 0x0e02, 0x11030003, 0x11210005, 0x01030305, 0x04000005, 8, 0x012a00a9 },
2074 + { 228000000, 114000000, 0x0e02, 0x11020005, 0x11210005, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2075 + { 240000000, 102857143, 0x0109, 0x04000021, 0x01050203, 0x11030021, 0x04000003, 13, 0x254a14a9 },
2076 + { 240000000, 120000000, 0x0109, 0x11030002, 0x01050203, 0x11030002, 0x04000003, 11, 0x0aaa0555 },
2077 + { 252000000, 100800000, 0x0203, 0x04000009, 0x11050005, 0x02000209, 0x04000002, 9, 0x02520129 },
2078 + { 252000000, 126000000, 0x0203, 0x04000005, 0x11050005, 0x04000005, 0x04000002, 11, 0x0aaa0555 },
2079 + { 264000000, 132000000, 0x0602, 0x04000005, 0x11050005, 0x04000005, 0x04000002, 11, 0x0aaa0555 },
2080 + { 272000000, 116571428, 0x0c02, 0x04000021, 0x02000909, 0x02000221, 0x04000003, 13, 0x254a14a9 },
2081 + { 280000000, 120000000, 0x0209, 0x04000021, 0x01030303, 0x02000221, 0x04000003, 13, 0x254a14a9 },
2082 + { 288000000, 123428571, 0x0111, 0x04000021, 0x01030303, 0x02000221, 0x04000003, 13, 0x254a14a9 },
2083 + { 300000000, 120000000, 0x0009, 0x04000009, 0x01030203, 0x02000902, 0x04000002, 9, 0x02520129 },
2084 + { 300000000, 150000000, 0x0009, 0x04000005, 0x01030203, 0x04000005, 0x04000002, 11, 0x0aaa0555 }
2085 + };
2086 +
2087 + static n4m_table_t BCMINITDATA(type7_table)[] = {
2088 + { 183333333, 91666666, 0x0605, 0x04000011, 0x11030011, 0x04000011, 0x04000003, 11, 0x0aaa0555 },
2089 + { 187500000, 93750000, 0x0a03, 0x04000011, 0x11030011, 0x04000011, 0x04000003, 11, 0x0aaa0555 },
2090 + { 196875000, 98437500, 0x1003, 0x11020005, 0x11050011, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2091 + { 200000000, 100000000, 0x0311, 0x04000011, 0x11030011, 0x04000009, 0x04000003, 11, 0x0aaa0555 },
2092 + { 200000000, 100000000, 0x0311, 0x04020011, 0x11030011, 0x04020011, 0x04020003, 11, 0x0aaa0555 },
2093 + { 206250000, 103125000, 0x1103, 0x11020005, 0x11050011, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2094 + { 212500000, 106250000, 0x0c05, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2095 + { 215625000, 107812500, 0x1203, 0x11090009, 0x11050005, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2096 + { 216666666, 108333333, 0x0805, 0x11020003, 0x11030011, 0x11020003, 0x04000003, 11, 0x0aaa0555 },
2097 + { 225000000, 112500000, 0x0d03, 0x11020003, 0x11030011, 0x11020003, 0x04000003, 11, 0x0aaa0555 },
2098 + { 233333333, 116666666, 0x0905, 0x11020003, 0x11030011, 0x11020003, 0x04000003, 11, 0x0aaa0555 },
2099 + { 237500000, 118750000, 0x0e05, 0x11020005, 0x11210005, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
2100 + { 240000000, 120000000, 0x0b11, 0x11020009, 0x11210009, 0x11020009, 0x04000009, 11, 0x0aaa0555 },
2101 + { 250000000, 125000000, 0x0f03, 0x11020003, 0x11210003, 0x11020003, 0x04000003, 11, 0x0aaa0555 }
2102 + };
2103 +
2104 + ulong start, end, dst;
2105 + bool ret = FALSE;
2106 +
2107 + /* get index of the current core */
2108 + idx = sb_coreidx(sbh);
2109 + clockcontrol_m2 = NULL;
2110 +
2111 + /* switch to extif or chipc core */
2112 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
2113 + pll_type = PLL_TYPE1;
2114 + clockcontrol_n = &eir->clockcontrol_n;
2115 + clockcontrol_sb = &eir->clockcontrol_sb;
2116 + clockcontrol_pci = &eir->clockcontrol_pci;
2117 + clockcontrol_m2 = &cc->clockcontrol_m2;
2118 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
2119 + pll_type = R_REG(&cc->capabilities) & CAP_PLL_MASK;
2120 + if (pll_type == PLL_TYPE6) {
2121 + clockcontrol_n = NULL;
2122 + clockcontrol_sb = NULL;
2123 + clockcontrol_pci = NULL;
2124 + } else {
2125 + clockcontrol_n = &cc->clockcontrol_n;
2126 + clockcontrol_sb = &cc->clockcontrol_sb;
2127 + clockcontrol_pci = &cc->clockcontrol_pci;
2128 + clockcontrol_m2 = &cc->clockcontrol_m2;
2129 + }
2130 + } else
2131 + goto done;
2132 +
2133 + if (pll_type == PLL_TYPE6) {
2134 + /* Silence compilers */
2135 + orig_n = orig_sb = orig_pci = 0;
2136 + } else {
2137 + /* Store the current clock register values */
2138 + orig_n = R_REG(clockcontrol_n);
2139 + orig_sb = R_REG(clockcontrol_sb);
2140 + orig_pci = R_REG(clockcontrol_pci);
2141 + }
2142 +
2143 + if (pll_type == PLL_TYPE1) {
2144 + /* Keep the current PCI clock if not specified */
2145 + if (pciclock == 0) {
2146 + pciclock = sb_clock_rate(pll_type, R_REG(clockcontrol_n), R_REG(clockcontrol_pci));
2147 + pciclock = (pciclock <= 25000000) ? 25000000 : 33000000;
2148 + }
2149 +
2150 + /* Search for the closest MIPS clock less than or equal to a preferred value */
2151 + for (i = 0; i < ARRAYSIZE(BCMINIT(type1_table)); i++) {
2152 + ASSERT(BCMINIT(type1_table)[i].mipsclock ==
2153 + sb_clock_rate(pll_type, BCMINIT(type1_table)[i].n, BCMINIT(type1_table)[i].sb));
2154 + if (BCMINIT(type1_table)[i].mipsclock > mipsclock)
2155 + break;
2156 + }
2157 + if (i == 0) {
2158 + ret = FALSE;
2159 + goto done;
2160 + } else {
2161 + ret = TRUE;
2162 + i--;
2163 + }
2164 + ASSERT(BCMINIT(type1_table)[i].mipsclock <= mipsclock);
2165 +
2166 + /* No PLL change */
2167 + if ((orig_n == BCMINIT(type1_table)[i].n) &&
2168 + (orig_sb == BCMINIT(type1_table)[i].sb) &&
2169 + (orig_pci == BCMINIT(type1_table)[i].pci33))
2170 + goto done;
2171 +
2172 + /* Set the PLL controls */
2173 + W_REG(clockcontrol_n, BCMINIT(type1_table)[i].n);
2174 + W_REG(clockcontrol_sb, BCMINIT(type1_table)[i].sb);
2175 + if (pciclock == 25000000)
2176 + W_REG(clockcontrol_pci, BCMINIT(type1_table)[i].pci25);
2177 + else
2178 + W_REG(clockcontrol_pci, BCMINIT(type1_table)[i].pci33);
2179 +
2180 + /* Reset */
2181 + sb_watchdog(sbh, 1);
2182 +
2183 + while (1);
2184 + } else if ((pll_type == PLL_TYPE3) &&
2185 + (BCMINIT(sb_chip)(sbh) != BCM5365_DEVICE_ID)) {
2186 + /* 5350 */
2187 + /* Search for the closest MIPS clock less than or equal to a preferred value */
2188 +
2189 + for (i = 0; i < ARRAYSIZE(type3_table); i++) {
2190 + if (type3_table[i].mipsclock > mipsclock)
2191 + break;
2192 + }
2193 + if (i == 0) {
2194 + ret = FALSE;
2195 + goto done;
2196 + } else {
2197 + ret = TRUE;
2198 + i--;
2199 + }
2200 + ASSERT(type3_table[i].mipsclock <= mipsclock);
2201 +
2202 + /* No PLL change */
2203 + orig_m2 = R_REG(&cc->clockcontrol_m2);
2204 + if ((orig_n == type3_table[i].n) &&
2205 + (orig_m2 == type3_table[i].m2)) {
2206 + goto done;
2207 + }
2208 +
2209 + /* Set the PLL controls */
2210 + W_REG(clockcontrol_n, type3_table[i].n);
2211 + W_REG(clockcontrol_m2, type3_table[i].m2);
2212 +
2213 + /* Reset */
2214 + sb_watchdog(sbh, 1);
2215 + while (1);
2216 + } else if ((pll_type == PLL_TYPE2) ||
2217 + (pll_type == PLL_TYPE4) ||
2218 + (pll_type == PLL_TYPE6) ||
2219 + (pll_type == PLL_TYPE7)) {
2220 + n4m_table_t *table = NULL, *te;
2221 + uint tabsz = 0;
2222 +
2223 + ASSERT(cc);
2224 +
2225 + orig_mips = R_REG(&cc->clockcontrol_mips);
2226 +
2227 + if (pll_type == PLL_TYPE6) {
2228 + uint32 new_mips = 0;
2229 +
2230 + ret = TRUE;
2231 + if (mipsclock <= SB2MIPS_T6(CC_T6_M1))
2232 + new_mips = CC_T6_MMASK;
2233 +
2234 + if (orig_mips == new_mips)
2235 + goto done;
2236 +
2237 + W_REG(&cc->clockcontrol_mips, new_mips);
2238 + goto end_fill;
2239 + }
2240 +
2241 + if (pll_type == PLL_TYPE2) {
2242 + table = BCMINIT(type2_table);
2243 + tabsz = ARRAYSIZE(BCMINIT(type2_table));
2244 + } else if (pll_type == PLL_TYPE4) {
2245 + table = BCMINIT(type4_table);
2246 + tabsz = ARRAYSIZE(BCMINIT(type4_table));
2247 + } else if (pll_type == PLL_TYPE7) {
2248 + table = BCMINIT(type7_table);
2249 + tabsz = ARRAYSIZE(BCMINIT(type7_table));
2250 + } else
2251 + ASSERT("No table for plltype" == NULL);
2252 +
2253 + /* Store the current clock register values */
2254 + orig_m2 = R_REG(&cc->clockcontrol_m2);
2255 + orig_ratio_parm = 0;
2256 + orig_ratio_cfg = 0;
2257 +
2258 + /* Look up current ratio */
2259 + for (i = 0; i < tabsz; i++) {
2260 + if ((orig_n == table[i].n) &&
2261 + (orig_sb == table[i].sb) &&
2262 + (orig_pci == table[i].pci33) &&
2263 + (orig_m2 == table[i].m2) &&
2264 + (orig_mips == table[i].m3)) {
2265 + orig_ratio_parm = table[i].ratio_parm;
2266 + orig_ratio_cfg = table[i].ratio_cfg;
2267 + break;
2268 + }
2269 + }
2270 +
2271 + /* Search for the closest MIPS clock greater or equal to a preferred value */
2272 + for (i = 0; i < tabsz; i++) {
2273 + ASSERT(table[i].mipsclock ==
2274 + sb_clock_rate(pll_type, table[i].n, table[i].m3));
2275 + if ((mipsclock <= table[i].mipsclock) &&
2276 + ((sbclock == 0) || (sbclock <= table[i].sbclock)))
2277 + break;
2278 + }
2279 + if (i == tabsz) {
2280 + ret = FALSE;
2281 + goto done;
2282 + } else {
2283 + te = &table[i];
2284 + ret = TRUE;
2285 + }
2286 +
2287 + /* No PLL change */
2288 + if ((orig_n == te->n) &&
2289 + (orig_sb == te->sb) &&
2290 + (orig_pci == te->pci33) &&
2291 + (orig_m2 == te->m2) &&
2292 + (orig_mips == te->m3))
2293 + goto done;
2294 +
2295 + /* Set the PLL controls */
2296 + W_REG(clockcontrol_n, te->n);
2297 + W_REG(clockcontrol_sb, te->sb);
2298 + W_REG(clockcontrol_pci, te->pci33);
2299 + W_REG(&cc->clockcontrol_m2, te->m2);
2300 + W_REG(&cc->clockcontrol_mips, te->m3);
2301 +
2302 + /* Set the chipcontrol bit to change mipsref to the backplane divider if needed */
2303 + if ((pll_type == PLL_TYPE7) &&
2304 + (te->sb != te->m2) &&
2305 + (sb_clock_rate(pll_type, te->n, te->m2) == 120000000))
2306 + W_REG(&cc->chipcontrol, R_REG(&cc->chipcontrol) | 0x100);
2307 +
2308 + /* No ratio change */
2309 + if (orig_ratio_parm == te->ratio_parm)
2310 + goto end_fill;
2311 +
2312 + icache_probe(MFC0(C0_CONFIG, 1), &ic_size, &ic_lsize);
2313 +
2314 + /* Preload the code into the cache */
2315 + start = ((ulong) &&start_fill) & ~(ic_lsize - 1);
2316 + end = ((ulong) &&end_fill + (ic_lsize - 1)) & ~(ic_lsize - 1);
2317 + while (start < end) {
2318 + cache_op(start, Fill_I);
2319 + start += ic_lsize;
2320 + }
2321 +
2322 + /* Copy the handler */
2323 + start = (ulong) &BCMINIT(handler);
2324 + end = (ulong) &BCMINIT(afterhandler);
2325 + dst = KSEG1ADDR(0x180);
2326 + for (i = 0; i < (end - start); i += 4)
2327 + *((ulong *)(dst + i)) = *((ulong *)(start + i));
2328 +
2329 + /* Preload handler into the cache one line at a time */
2330 + for (i = 0; i < (end - start); i += 4)
2331 + cache_op(dst + i, Fill_I);
2332 +
2333 + /* Clear BEV bit */
2334 + MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) & ~ST0_BEV);
2335 +
2336 + /* Enable interrupts */
2337 + MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) | (ALLINTS | ST0_IE));
2338 +
2339 + /* Enable MIPS timer interrupt */
2340 + if (!(mipsr = sb_setcore(sbh, SB_MIPS, 0)) &&
2341 + !(mipsr = sb_setcore(sbh, SB_MIPS33, 0)))
2342 + ASSERT(mipsr);
2343 + W_REG(&mipsr->intmask, 1);
2344 +
2345 + start_fill:
2346 + /* step 1, set clock ratios */
2347 + MTC0(C0_BROADCOM, 3, te->ratio_parm);
2348 + MTC0(C0_BROADCOM, 1, te->ratio_cfg);
2349 +
2350 + /* step 2: program timer intr */
2351 + W_REG(&mipsr->timer, 100);
2352 + (void) R_REG(&mipsr->timer);
2353 +
2354 + /* step 3, switch to async */
2355 + sync_mode = MFC0(C0_BROADCOM, 4);
2356 + MTC0(C0_BROADCOM, 4, 1 << 22);
2357 +
2358 + /* step 4, set cfg active */
2359 + MTC0(C0_BROADCOM, 2, 0x9);
2360 +
2361 +
2362 + /* steps 5 & 6 */
2363 + __asm__ __volatile__ (
2364 + ".set\tmips3\n\t"
2365 + "wait\n\t"
2366 + ".set\tmips0"
2367 + );
2368 +
2369 + /* step 7, clear cfg_active */
2370 + MTC0(C0_BROADCOM, 2, 0);
2371 +
2372 + /* Additional Step: set back to orig sync mode */
2373 + MTC0(C0_BROADCOM, 4, sync_mode);
2374 +
2375 + /* step 8, fake soft reset */
2376 + MTC0(C0_BROADCOM, 5, MFC0(C0_BROADCOM, 5) | 4);
2377 +
2378 + end_fill:
2379 + /* step 9 set watchdog timer */
2380 + sb_watchdog(sbh, 20);
2381 + (void) R_REG(&cc->chipid);
2382 +
2383 + /* step 11 */
2384 + __asm__ __volatile__ (
2385 + ".set\tmips3\n\t"
2386 + "sync\n\t"
2387 + "wait\n\t"
2388 + ".set\tmips0"
2389 + );
2390 + while (1);
2391 + }
2392 +
2393 +done:
2394 + /* switch back to previous core */
2395 + sb_setcoreidx(sbh, idx);
2396 +
2397 + return ret;
2398 +}
2399 +
2400 +/*
2401 + * This also must be run from the cache on 47xx
2402 + * so there are no mips core BIU ops in progress
2403 + * when the PFC is enabled.
2404 + */
2405 +
2406 +static void
2407 +BCMINITFN(_enable_pfc)(uint32 mode)
2408 +{
2409 + /* write range */
2410 + *(volatile uint32 *)PFC_CR1 = 0xffff0000;
2411 +
2412 + /* enable */
2413 + *(volatile uint32 *)PFC_CR0 = mode;
2414 +}
2415 +
2416 +void
2417 +BCMINITFN(enable_pfc)(uint32 mode)
2418 +{
2419 + ulong start, end;
2420 + int i;
2421 +
2422 + /* If auto then choose the correct mode for this
2423 + platform, currently we only ever select one mode */
2424 + if (mode == PFC_AUTO)
2425 + mode = PFC_INST;
2426 +
2427 + /* enable prefetch cache if available */
2428 + if (MFC0(C0_BROADCOM, 0) & BRCM_PFC_AVAIL) {
2429 + start = (ulong) &BCMINIT(_enable_pfc);
2430 + end = (ulong) &BCMINIT(enable_pfc);
2431 +
2432 + /* Preload handler into the cache one line at a time */
2433 + for (i = 0; i < (end - start); i += 4)
2434 + cache_op(start + i, Fill_I);
2435 +
2436 + BCMINIT(_enable_pfc)(mode);
2437 + }
2438 +}
2439 +
2440 +/* returns the ncdl value to be programmed into sdram_ncdl for calibration */
2441 +uint32
2442 +BCMINITFN(sb_memc_get_ncdl)(sb_t *sbh)
2443 +{
2444 + sbmemcregs_t *memc;
2445 + uint32 ret = 0;
2446 + uint32 config, rd, wr, misc, dqsg, cd, sm, sd;
2447 + uint idx, rev;
2448 +
2449 + idx = sb_coreidx(sbh);
2450 +
2451 + memc = (sbmemcregs_t *)sb_setcore(sbh, SB_MEMC, 0);
2452 + if (memc == 0)
2453 + goto out;
2454 +
2455 + rev = sb_corerev(sbh);
2456 +
2457 + config = R_REG(&memc->config);
2458 + wr = R_REG(&memc->wrncdlcor);
2459 + rd = R_REG(&memc->rdncdlcor);
2460 + misc = R_REG(&memc->miscdlyctl);
2461 + dqsg = R_REG(&memc->dqsgatencdl);
2462 +
2463 + rd &= MEMC_RDNCDLCOR_RD_MASK;
2464 + wr &= MEMC_WRNCDLCOR_WR_MASK;
2465 + dqsg &= MEMC_DQSGATENCDL_G_MASK;
2466 +
2467 + if (config & MEMC_CONFIG_DDR) {
2468 + ret = (wr << 16) | (rd << 8) | dqsg;
2469 + } else {
2470 + if (rev > 0)
2471 + cd = rd;
2472 + else
2473 + cd = (rd == MEMC_CD_THRESHOLD) ? rd : (wr + MEMC_CD_THRESHOLD);
2474 + sm = (misc & MEMC_MISC_SM_MASK) >> MEMC_MISC_SM_SHIFT;
2475 + sd = (misc & MEMC_MISC_SD_MASK) >> MEMC_MISC_SD_SHIFT;
2476 + ret = (sm << 16) | (sd << 8) | cd;
2477 + }
2478 +
2479 +out:
2480 + /* switch back to previous core */
2481 + sb_setcoreidx(sbh, idx);
2482 +
2483 + return ret;
2484 +}
2485 +
2486 diff -urN linux.old/arch/mips/bcm947xx/broadcom/sbpci.c linux.dev/arch/mips/bcm947xx/broadcom/sbpci.c
2487 --- linux.old/arch/mips/bcm947xx/broadcom/sbpci.c 1970-01-01 01:00:00.000000000 +0100
2488 +++ linux.dev/arch/mips/bcm947xx/broadcom/sbpci.c 2005-12-28 16:37:32.854260000 +0100
2489 @@ -0,0 +1,533 @@
2490 +/*
2491 + * Low-Level PCI and SB support for BCM47xx
2492 + *
2493 + * Copyright 2005, Broadcom Corporation
2494 + * All Rights Reserved.
2495 + *
2496 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2497 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2498 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2499 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2500 + *
2501 + * $Id$
2502 + */
2503 +
2504 +#include <typedefs.h>
2505 +#include <pcicfg.h>
2506 +#include <bcmdevs.h>
2507 +#include <sbconfig.h>
2508 +#include <osl.h>
2509 +#include <sbutils.h>
2510 +#include <sbpci.h>
2511 +#include <bcmendian.h>
2512 +#include <bcmutils.h>
2513 +#include <bcmnvram.h>
2514 +#include <hndmips.h>
2515 +
2516 +/* Can free sbpci_init() memory after boot */
2517 +#ifndef linux
2518 +#define __init
2519 +#endif
2520 +
2521 +/* Emulated configuration space */
2522 +static pci_config_regs sb_config_regs[SB_MAXCORES];
2523 +
2524 +/* Banned cores */
2525 +static uint16 pci_ban[32] = { 0 };
2526 +static uint pci_banned = 0;
2527 +
2528 +/* CardBus mode */
2529 +static bool cardbus = FALSE;
2530 +
2531 +/* Disable PCI host core */
2532 +static bool pci_disabled = FALSE;
2533 +
2534 +/*
2535 + * Functions for accessing external PCI configuration space
2536 + */
2537 +
2538 +/* Assume one-hot slot wiring */
2539 +#define PCI_SLOT_MAX 16
2540 +
2541 +static uint32
2542 +config_cmd(sb_t *sbh, uint bus, uint dev, uint func, uint off)
2543 +{
2544 + uint coreidx;
2545 + sbpciregs_t *regs;
2546 + uint32 addr = 0;
2547 +
2548 + /* CardBusMode supports only one device */
2549 + if (cardbus && dev > 1)
2550 + return 0;
2551 +
2552 + coreidx = sb_coreidx(sbh);
2553 + regs = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0);
2554 +
2555 + /* Type 0 transaction */
2556 + if (bus == 1) {
2557 + /* Skip unwired slots */
2558 + if (dev < PCI_SLOT_MAX) {
2559 + /* Slide the PCI window to the appropriate slot */
2560 + W_REG(&regs->sbtopci1, SBTOPCI_CFG0 | ((1 << (dev + 16)) & SBTOPCI1_MASK));
2561 + addr = SB_PCI_CFG | ((1 << (dev + 16)) & ~SBTOPCI1_MASK) |
2562 + (func << 8) | (off & ~3);
2563 + }
2564 + }
2565 +
2566 + /* Type 1 transaction */
2567 + else {
2568 + W_REG(&regs->sbtopci1, SBTOPCI_CFG1);
2569 + addr = SB_PCI_CFG | (bus << 16) | (dev << 11) | (func << 8) | (off & ~3);
2570 + }
2571 +
2572 + sb_setcoreidx(sbh, coreidx);
2573 +
2574 + return addr;
2575 +}
2576 +
2577 +static int
2578 +extpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
2579 +{
2580 + uint32 addr, *reg = NULL, val;
2581 + int ret = 0;
2582 +
2583 + if (pci_disabled ||
2584 + !(addr = config_cmd(sbh, bus, dev, func, off)) ||
2585 + !(reg = (uint32 *) REG_MAP(addr, len)) ||
2586 + BUSPROBE(val, reg))
2587 + val = 0xffffffff;
2588 +
2589 + val >>= 8 * (off & 3);
2590 + if (len == 4)
2591 + *((uint32 *) buf) = val;
2592 + else if (len == 2)
2593 + *((uint16 *) buf) = (uint16) val;
2594 + else if (len == 1)
2595 + *((uint8 *) buf) = (uint8) val;
2596 + else
2597 + ret = -1;
2598 +
2599 + if (reg)
2600 + REG_UNMAP(reg);
2601 +
2602 + return ret;
2603 +}
2604 +
2605 +static int
2606 +extpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
2607 +{
2608 + uint32 addr, *reg = NULL, val;
2609 + int ret = 0;
2610 +
2611 + if (pci_disabled ||
2612 + !(addr = config_cmd(sbh, bus, dev, func, off)) ||
2613 + !(reg = (uint32 *) REG_MAP(addr, len)) ||
2614 + BUSPROBE(val, reg))
2615 + goto done;
2616 +
2617 + if (len == 4)
2618 + val = *((uint32 *) buf);
2619 + else if (len == 2) {
2620 + val &= ~(0xffff << (8 * (off & 3)));
2621 + val |= *((uint16 *) buf) << (8 * (off & 3));
2622 + } else if (len == 1) {
2623 + val &= ~(0xff << (8 * (off & 3)));
2624 + val |= *((uint8 *) buf) << (8 * (off & 3));
2625 + } else
2626 + ret = -1;
2627 +
2628 + W_REG(reg, val);
2629 +
2630 + done:
2631 + if (reg)
2632 + REG_UNMAP(reg);
2633 +
2634 + return ret;
2635 +}
2636 +
2637 +/*
2638 + * Functions for accessing translated SB configuration space
2639 + */
2640 +
2641 +static int
2642 +sb_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
2643 +{
2644 + pci_config_regs *cfg;
2645 +
2646 + if (dev >= SB_MAXCORES || (off + len) > sizeof(pci_config_regs))
2647 + return -1;
2648 + cfg = &sb_config_regs[dev];
2649 +
2650 + ASSERT(ISALIGNED(off, len));
2651 + ASSERT(ISALIGNED((uintptr)buf, len));
2652 +
2653 + if (len == 4)
2654 + *((uint32 *) buf) = ltoh32(*((uint32 *)((ulong) cfg + off)));
2655 + else if (len == 2)
2656 + *((uint16 *) buf) = ltoh16(*((uint16 *)((ulong) cfg + off)));
2657 + else if (len == 1)
2658 + *((uint8 *) buf) = *((uint8 *)((ulong) cfg + off));
2659 + else
2660 + return -1;
2661 +
2662 + return 0;
2663 +}
2664 +
2665 +static int
2666 +sb_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
2667 +{
2668 + uint coreidx, n;
2669 + void *regs;
2670 + sbconfig_t *sb;
2671 + pci_config_regs *cfg;
2672 +
2673 + if (dev >= SB_MAXCORES || (off + len) > sizeof(pci_config_regs))
2674 + return -1;
2675 + cfg = &sb_config_regs[dev];
2676 +
2677 + ASSERT(ISALIGNED(off, len));
2678 + ASSERT(ISALIGNED((uintptr)buf, len));
2679 +
2680 + /* Emulate BAR sizing */
2681 + if (off >= OFFSETOF(pci_config_regs, base[0]) && off <= OFFSETOF(pci_config_regs, base[3]) &&
2682 + len == 4 && *((uint32 *) buf) == ~0) {
2683 + coreidx = sb_coreidx(sbh);
2684 + if ((regs = sb_setcoreidx(sbh, dev))) {
2685 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
2686 + /* Highest numbered address match register */
2687 + n = (R_REG(&sb->sbidlow) & SBIDL_AR_MASK) >> SBIDL_AR_SHIFT;
2688 + if (off == OFFSETOF(pci_config_regs, base[0]))
2689 + cfg->base[0] = ~(sb_size(R_REG(&sb->sbadmatch0)) - 1);
2690 +#if 0
2691 + else if (off == OFFSETOF(pci_config_regs, base[1]) && n >= 1)
2692 + cfg->base[1] = ~(sb_size(R_REG(&sb->sbadmatch1)) - 1);
2693 + else if (off == OFFSETOF(pci_config_regs, base[2]) && n >= 2)
2694 + cfg->base[2] = ~(sb_size(R_REG(&sb->sbadmatch2)) - 1);
2695 + else if (off == OFFSETOF(pci_config_regs, base[3]) && n >= 3)
2696 + cfg->base[3] = ~(sb_size(R_REG(&sb->sbadmatch3)) - 1);
2697 +#endif
2698 + }
2699 + sb_setcoreidx(sbh, coreidx);
2700 + return 0;
2701 + }
2702 +
2703 + if (len == 4)
2704 + *((uint32 *)((ulong) cfg + off)) = htol32(*((uint32 *) buf));
2705 + else if (len == 2)
2706 + *((uint16 *)((ulong) cfg + off)) = htol16(*((uint16 *) buf));
2707 + else if (len == 1)
2708 + *((uint8 *)((ulong) cfg + off)) = *((uint8 *) buf);
2709 + else
2710 + return -1;
2711 +
2712 + return 0;
2713 +}
2714 +
2715 +int
2716 +sbpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
2717 +{
2718 + if (bus == 0)
2719 + return sb_read_config(sbh, bus, dev, func, off, buf, len);
2720 + else
2721 + return extpci_read_config(sbh, bus, dev, func, off, buf, len);
2722 +}
2723 +
2724 +int
2725 +sbpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
2726 +{
2727 + if (bus == 0)
2728 + return sb_write_config(sbh, bus, dev, func, off, buf, len);
2729 + else
2730 + return extpci_write_config(sbh, bus, dev, func, off, buf, len);
2731 +}
2732 +
2733 +void
2734 +sbpci_ban(uint16 core)
2735 +{
2736 + if (pci_banned < ARRAYSIZE(pci_ban))
2737 + pci_ban[pci_banned++] = core;
2738 +}
2739 +
2740 +static int
2741 +sbpci_init_pci(sb_t *sbh)
2742 +{
2743 + uint chip, chiprev, chippkg, host;
2744 + uint32 boardflags;
2745 + sbpciregs_t *pci;
2746 + sbconfig_t *sb;
2747 + uint32 val;
2748 +
2749 + chip = sb_chip(sbh);
2750 + chiprev = sb_chiprev(sbh);
2751 + chippkg = sb_chippkg(sbh);
2752 +
2753 + if (!(pci = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0))) {
2754 + printf("PCI: no core\n");
2755 + pci_disabled = TRUE;
2756 + return -1;
2757 + }
2758 + sb_core_reset(sbh, 0);
2759 +
2760 + boardflags = (uint32) getintvar(NULL, "boardflags");
2761 +
2762 + if ((chip == BCM4310_DEVICE_ID) && (chiprev == 0))
2763 + pci_disabled = TRUE;
2764 +
2765 + /*
2766 + * The 200-pin BCM4712 package does not bond out PCI. Even when
2767 + * PCI is bonded out, some boards may leave the pins
2768 + * floating.
2769 + */
2770 + if (((chip == BCM4712_DEVICE_ID) &&
2771 + ((chippkg == BCM4712SMALL_PKG_ID) ||
2772 + (chippkg == BCM4712MID_PKG_ID))) ||
2773 + (boardflags & BFL_NOPCI))
2774 + pci_disabled = TRUE;
2775 +
2776 + /*
2777 + * If the PCI core should not be touched (disabled, not bonded
2778 + * out, or pins floating), do not even attempt to access core
2779 + * registers. Otherwise, try to determine if it is in host
2780 + * mode.
2781 + */
2782 + if (pci_disabled)
2783 + host = 0;
2784 + else
2785 + host = !BUSPROBE(val, &pci->control);
2786 +
2787 + if (!host) {
2788 + /* Disable PCI interrupts in client mode */
2789 + sb = (sbconfig_t *)((ulong) pci + SBCONFIGOFF);
2790 + W_REG(&sb->sbintvec, 0);
2791 +
2792 + /* Disable the PCI bridge in client mode */
2793 + sbpci_ban(SB_PCI);
2794 + printf("PCI: Disabled\n");
2795 + } else {
2796 + /* Reset the external PCI bus and enable the clock */
2797 + W_REG(&pci->control, 0x5); /* enable the tristate drivers */
2798 + W_REG(&pci->control, 0xd); /* enable the PCI clock */
2799 + OSL_DELAY(150); /* delay > 100 us */
2800 + W_REG(&pci->control, 0xf); /* deassert PCI reset */
2801 + W_REG(&pci->arbcontrol, PCI_INT_ARB); /* use internal arbiter */
2802 + OSL_DELAY(1); /* delay 1 us */
2803 +
2804 + /* Enable CardBusMode */
2805 + cardbus = nvram_match("cardbus", "1");
2806 + if (cardbus) {
2807 + printf("PCI: Enabling CardBus\n");
2808 + /* GPIO 1 resets the CardBus device on bcm94710ap */
2809 + sb_gpioout(sbh, 1, 1, GPIO_DRV_PRIORITY);
2810 + sb_gpioouten(sbh, 1, 1, GPIO_DRV_PRIORITY);
2811 + W_REG(&pci->sprom[0], R_REG(&pci->sprom[0]) | 0x400);
2812 + }
2813 +
2814 + /* 64 MB I/O access window */
2815 + W_REG(&pci->sbtopci0, SBTOPCI_IO);
2816 + /* 64 MB configuration access window */
2817 + W_REG(&pci->sbtopci1, SBTOPCI_CFG0);
2818 + /* 1 GB memory access window */
2819 + W_REG(&pci->sbtopci2, SBTOPCI_MEM | SB_PCI_DMA);
2820 +
2821 + /* Enable PCI bridge BAR0 prefetch and burst */
2822 + val = 6;
2823 + sbpci_write_config(sbh, 1, 0, 0, PCI_CFG_CMD, &val, sizeof(val));
2824 +
2825 + /* Enable PCI interrupts */
2826 + W_REG(&pci->intmask, PCI_INTA);
2827 + }
2828 +
2829 + return 0;
2830 +}
2831 +
2832 +static int
2833 +sbpci_init_cores(sb_t *sbh)
2834 +{
2835 + uint chip, chiprev, chippkg, coreidx, i;
2836 + sbconfig_t *sb;
2837 + pci_config_regs *cfg;
2838 + void *regs;
2839 + char varname[8];
2840 + uint wlidx = 0;
2841 + uint16 vendor, core;
2842 + uint8 class, subclass, progif;
2843 + uint32 val;
2844 + uint32 sbips_int_mask[] = { 0, SBIPS_INT1_MASK, SBIPS_INT2_MASK, SBIPS_INT3_MASK, SBIPS_INT4_MASK };
2845 + uint32 sbips_int_shift[] = { 0, 0, SBIPS_INT2_SHIFT, SBIPS_INT3_SHIFT, SBIPS_INT4_SHIFT };
2846 +
2847 + chip = sb_chip(sbh);
2848 + chiprev = sb_chiprev(sbh);
2849 + chippkg = sb_chippkg(sbh);
2850 + coreidx = sb_coreidx(sbh);
2851 +
2852 + /* Scan the SB bus */
2853 + bzero(sb_config_regs, sizeof(sb_config_regs));
2854 + for (cfg = sb_config_regs; cfg < &sb_config_regs[SB_MAXCORES]; cfg++) {
2855 + cfg->vendor = 0xffff;
2856 + if (!(regs = sb_setcoreidx(sbh, cfg - sb_config_regs)))
2857 + continue;
2858 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
2859 +
2860 + /* Read ID register and parse vendor and core */
2861 + val = R_REG(&sb->sbidhigh);
2862 + vendor = (val & SBIDH_VC_MASK) >> SBIDH_VC_SHIFT;
2863 + core = (val & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT;
2864 + progif = 0;
2865 +
2866 + /* Check if this core is banned */
2867 + for (i = 0; i < pci_banned; i++)
2868 + if (core == pci_ban[i])
2869 + break;
2870 + if (i < pci_banned)
2871 + continue;
2872 +
2873 + /* Known vendor translations */
2874 + switch (vendor) {
2875 + case SB_VEND_BCM:
2876 + vendor = VENDOR_BROADCOM;
2877 + break;
2878 + }
2879 +
2880 + /* Determine class based on known core codes */
2881 + switch (core) {
2882 + case SB_ILINE20:
2883 + class = PCI_CLASS_NET;
2884 + subclass = PCI_NET_ETHER;
2885 + core = BCM47XX_ILINE_ID;
2886 + break;
2887 + case SB_ILINE100:
2888 + class = PCI_CLASS_NET;
2889 + subclass = PCI_NET_ETHER;
2890 + core = BCM4610_ILINE_ID;
2891 + break;
2892 + case SB_ENET:
2893 + class = PCI_CLASS_NET;
2894 + subclass = PCI_NET_ETHER;
2895 + core = BCM47XX_ENET_ID;
2896 + break;
2897 + case SB_SDRAM:
2898 + case SB_MEMC:
2899 + class = PCI_CLASS_MEMORY;
2900 + subclass = PCI_MEMORY_RAM;
2901 + break;
2902 + case SB_PCI:
2903 +#if 0
2904 + class = PCI_CLASS_BRIDGE;
2905 + subclass = PCI_BRIDGE_PCI;
2906 + break;
2907 +#endif
2908 + case SB_MIPS:
2909 + case SB_MIPS33:
2910 + class = PCI_CLASS_CPU;
2911 + subclass = PCI_CPU_MIPS;
2912 + break;
2913 + case SB_CODEC:
2914 + class = PCI_CLASS_COMM;
2915 + subclass = PCI_COMM_MODEM;
2916 + core = BCM47XX_V90_ID;
2917 + break;
2918 + case SB_USB:
2919 + class = PCI_CLASS_SERIAL;
2920 + subclass = PCI_SERIAL_USB;
2921 + progif = 0x10; /* OHCI */
2922 + core = BCM47XX_USB_ID;
2923 + break;
2924 + case SB_USB11H:
2925 + class = PCI_CLASS_SERIAL;
2926 + subclass = PCI_SERIAL_USB;
2927 + progif = 0x10; /* OHCI */
2928 + core = BCM47XX_USBH_ID;
2929 + break;
2930 + case SB_USB11D:
2931 + class = PCI_CLASS_SERIAL;
2932 + subclass = PCI_SERIAL_USB;
2933 + core = BCM47XX_USBD_ID;
2934 + break;
2935 + case SB_IPSEC:
2936 + class = PCI_CLASS_CRYPT;
2937 + subclass = PCI_CRYPT_NETWORK;
2938 + core = BCM47XX_IPSEC_ID;
2939 + break;
2940 + case SB_ROBO:
2941 + class = PCI_CLASS_NET;
2942 + subclass = PCI_NET_OTHER;
2943 + core = BCM47XX_ROBO_ID;
2944 + break;
2945 + case SB_EXTIF:
2946 + case SB_CC:
2947 + class = PCI_CLASS_MEMORY;
2948 + subclass = PCI_MEMORY_FLASH;
2949 + break;
2950 + case SB_D11:
2951 + class = PCI_CLASS_NET;
2952 + subclass = PCI_NET_OTHER;
2953 + /* Let an nvram variable override this */
2954 + sprintf(varname, "wl%did", wlidx);
2955 + wlidx++;
2956 + if ((core = getintvar(NULL, varname)) == 0) {
2957 + if (chip == BCM4712_DEVICE_ID) {
2958 + if (chippkg == BCM4712SMALL_PKG_ID)
2959 + core = BCM4306_D11G_ID;
2960 + else
2961 + core = BCM4306_D11DUAL_ID;
2962 + } else {
2963 + /* 4310 */
2964 + core = BCM4310_D11B_ID;
2965 + }
2966 + }
2967 + break;
2968 +
2969 + default:
2970 + class = subclass = progif = 0xff;
2971 + break;
2972 + }
2973 +
2974 + /* Supported translations */
2975 + cfg->vendor = htol16(vendor);
2976 + cfg->device = htol16(core);
2977 + cfg->rev_id = chiprev;
2978 + cfg->prog_if = progif;
2979 + cfg->sub_class = subclass;
2980 + cfg->base_class = class;
2981 + cfg->base[0] = htol32(sb_base(R_REG(&sb->sbadmatch0)));
2982 + cfg->base[1] = 0;//htol32(sb_base(R_REG(&sb->sbadmatch1)));
2983 + cfg->base[2] = 0;//htol32(sb_base(R_REG(&sb->sbadmatch2)));
2984 + cfg->base[3] = 0;//htol32(sb_base(R_REG(&sb->sbadmatch3)));
2985 + cfg->base[4] = 0;
2986 + cfg->base[5] = 0;
2987 + if (class == PCI_CLASS_BRIDGE && subclass == PCI_BRIDGE_PCI)
2988 + cfg->header_type = PCI_HEADER_BRIDGE;
2989 + else
2990 + cfg->header_type = PCI_HEADER_NORMAL;
2991 + /* Save core interrupt flag */
2992 + cfg->int_pin = R_REG(&sb->sbtpsflag) & SBTPS_NUM0_MASK;
2993 + /* Default to MIPS shared interrupt 0 */
2994 + cfg->int_line = 0;
2995 + /* MIPS sbipsflag maps core interrupt flags to interrupts 1 through 4 */
2996 + if ((regs = sb_setcore(sbh, SB_MIPS, 0)) ||
2997 + (regs = sb_setcore(sbh, SB_MIPS33, 0))) {
2998 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
2999 + val = R_REG(&sb->sbipsflag);
3000 + for (cfg->int_line = 1; cfg->int_line <= 4; cfg->int_line++) {
3001 + if (((val & sbips_int_mask[cfg->int_line]) >> sbips_int_shift[cfg->int_line]) == cfg->int_pin)
3002 + break;
3003 + }
3004 + if (cfg->int_line > 4)
3005 + cfg->int_line = 0;
3006 + }
3007 + /* Emulated core */
3008 + *((uint32 *) &cfg->sprom_control) = 0xffffffff;
3009 + }
3010 +
3011 + sb_setcoreidx(sbh, coreidx);
3012 + return 0;
3013 +}
3014 +
3015 +int __init
3016 +sbpci_init(sb_t *sbh)
3017 +{
3018 + sbpci_init_pci(sbh);
3019 + sbpci_init_cores(sbh);
3020 + return 0;
3021 +}
3022 +
3023 diff -urN linux.old/arch/mips/bcm947xx/broadcom/sbutils.c linux.dev/arch/mips/bcm947xx/broadcom/sbutils.c
3024 --- linux.old/arch/mips/bcm947xx/broadcom/sbutils.c 1970-01-01 01:00:00.000000000 +0100
3025 +++ linux.dev/arch/mips/bcm947xx/broadcom/sbutils.c 2005-12-28 16:37:32.858260250 +0100
3026 @@ -0,0 +1,2370 @@
3027 +/*
3028 + * Misc utility routines for accessing chip-specific features
3029 + * of the SiliconBackplane-based Broadcom chips.
3030 + *
3031 + * Copyright 2005, Broadcom Corporation
3032 + * All Rights Reserved.
3033 + *
3034 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
3035 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
3036 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
3037 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
3038 + * $Id$
3039 + */
3040 +
3041 +#include <typedefs.h>
3042 +#include <osl.h>
3043 +#include <sbutils.h>
3044 +#include <bcmutils.h>
3045 +#include <bcmdevs.h>
3046 +#include <sbconfig.h>
3047 +#include <sbchipc.h>
3048 +#include <sbpci.h>
3049 +#include <pcicfg.h>
3050 +#include <sbextif.h>
3051 +#include <bcmsrom.h>
3052 +
3053 +/* debug/trace */
3054 +#define SB_ERROR(args)
3055 +
3056 +
3057 +typedef uint32 (*sb_intrsoff_t)(void *intr_arg);
3058 +typedef void (*sb_intrsrestore_t)(void *intr_arg, uint32 arg);
3059 +typedef bool (*sb_intrsenabled_t)(void *intr_arg);
3060 +
3061 +/* misc sb info needed by some of the routines */
3062 +typedef struct sb_info {
3063 +
3064 + struct sb_pub sb; /* back plane public state(must be first field of sb_info */
3065 +
3066 + void *osh; /* osl os handle */
3067 + void *sdh; /* bcmsdh handle */
3068 +
3069 + void *curmap; /* current regs va */
3070 + void *regs[SB_MAXCORES]; /* other regs va */
3071 +
3072 + uint curidx; /* current core index */
3073 + uint dev_coreid; /* the core provides driver functions */
3074 +
3075 + uint gpioidx; /* gpio control core index */
3076 + uint gpioid; /* gpio control coretype */
3077 +
3078 + uint numcores; /* # discovered cores */
3079 + uint coreid[SB_MAXCORES]; /* id of each core */
3080 +
3081 + void *intr_arg; /* interrupt callback function arg */
3082 + sb_intrsoff_t intrsoff_fn; /* function turns chip interrupts off */
3083 + sb_intrsrestore_t intrsrestore_fn; /* function restore chip interrupts */
3084 + sb_intrsenabled_t intrsenabled_fn; /* function to check if chip interrupts are enabled */
3085 +
3086 +} sb_info_t;
3087 +
3088 +/* local prototypes */
3089 +static sb_info_t * BCMINIT(sb_doattach)(sb_info_t *si, uint devid, osl_t *osh, void *regs,
3090 + uint bustype, void *sdh, char **vars, int *varsz);
3091 +static void BCMINIT(sb_scan)(sb_info_t *si);
3092 +static uint sb_corereg(sb_info_t *si, uint coreidx, uint regoff, uint mask, uint val);
3093 +static uint _sb_coreidx(sb_info_t *si);
3094 +static uint sb_findcoreidx(sb_info_t *si, uint coreid, uint coreunit);
3095 +static uint BCMINIT(sb_pcidev2chip)(uint pcidev);
3096 +static uint BCMINIT(sb_chip2numcores)(uint chip);
3097 +static int sb_pci_fixcfg(sb_info_t *si);
3098 +
3099 +/* delay needed between the mdio control/ mdiodata register data access */
3100 +#define PR28829_DELAY() OSL_DELAY(10)
3101 +
3102 +
3103 +/* global variable to indicate reservation/release of gpio's*/
3104 +static uint32 sb_gpioreservation = 0;
3105 +
3106 +#define SB_INFO(sbh) (sb_info_t*)sbh
3107 +#define SET_SBREG(sbh, r, mask, val) W_SBREG((sbh), (r), ((R_SBREG((sbh), (r)) & ~(mask)) | (val)))
3108 +#define GOODCOREADDR(x) (((x) >= SB_ENUM_BASE) && ((x) <= SB_ENUM_LIM) && ISALIGNED((x), SB_CORE_SIZE))
3109 +#define GOODREGS(regs) ((regs) && ISALIGNED((uintptr)(regs), SB_CORE_SIZE))
3110 +#define REGS2SB(va) (sbconfig_t*) ((int8*)(va) + SBCONFIGOFF)
3111 +#define GOODIDX(idx) (((uint)idx) < SB_MAXCORES)
3112 +#define BADIDX (SB_MAXCORES+1)
3113 +#define NOREV -1
3114 +
3115 +#define PCI(si) ((BUSTYPE(si->sb.bustype) == PCI_BUS) && (si->sb.buscoretype == SB_PCI))
3116 +
3117 +/* sonicsrev */
3118 +#define SONICS_2_2 (SBIDL_RV_2_2 >> SBIDL_RV_SHIFT)
3119 +#define SONICS_2_3 (SBIDL_RV_2_3 >> SBIDL_RV_SHIFT)
3120 +
3121 +#define R_SBREG(sbh, sbr) sb_read_sbreg((sbh), (sbr))
3122 +#define W_SBREG(sbh, sbr, v) sb_write_sbreg((sbh), (sbr), (v))
3123 +#define AND_SBREG(sbh, sbr, v) W_SBREG((sbh), (sbr), (R_SBREG((sbh), (sbr)) & (v)))
3124 +#define OR_SBREG(sbh, sbr, v) W_SBREG((sbh), (sbr), (R_SBREG((sbh), (sbr)) | (v)))
3125 +
3126 +/*
3127 + * Macros to disable/restore function core(D11, ENET, ILINE20, etc) interrupts before/
3128 + * after core switching to avoid invalid register accesss inside ISR.
3129 + */
3130 +#define INTR_OFF(si, intr_val) \
3131 + if ((si)->intrsoff_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
3132 + intr_val = (*(si)->intrsoff_fn)((si)->intr_arg); }
3133 +#define INTR_RESTORE(si, intr_val) \
3134 + if ((si)->intrsrestore_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
3135 + (*(si)->intrsrestore_fn)((si)->intr_arg, intr_val); }
3136 +
3137 +/* dynamic clock control defines */
3138 +#define LPOMINFREQ 25000 /* low power oscillator min */
3139 +#define LPOMAXFREQ 43000 /* low power oscillator max */
3140 +#define XTALMINFREQ 19800000 /* 20 MHz - 1% */
3141 +#define XTALMAXFREQ 20200000 /* 20 MHz + 1% */
3142 +#define PCIMINFREQ 25000000 /* 25 MHz */
3143 +#define PCIMAXFREQ 34000000 /* 33 MHz + fudge */
3144 +
3145 +#define ILP_DIV_5MHZ 0 /* ILP = 5 MHz */
3146 +#define ILP_DIV_1MHZ 4 /* ILP = 1 MHz */
3147 +
3148 +#define MIN_DUMPBUFLEN 32 /* debug */
3149 +
3150 +/* GPIO Based LED powersave defines */
3151 +#define DEFAULT_GPIO_ONTIME 10
3152 +#define DEFAULT_GPIO_OFFTIME 90
3153 +
3154 +#define DEFAULT_GPIOTIMERVAL ((DEFAULT_GPIO_ONTIME << GPIO_ONTIME_SHIFT) | DEFAULT_GPIO_OFFTIME)
3155 +
3156 +static uint32
3157 +sb_read_sbreg(sb_info_t *si, volatile uint32 *sbr)
3158 +{
3159 + uint32 val = R_REG(sbr);
3160 +
3161 + return (val);
3162 +}
3163 +
3164 +static void
3165 +sb_write_sbreg(sb_info_t *si, volatile uint32 *sbr, uint32 v)
3166 +{
3167 + W_REG(sbr, v);
3168 +}
3169 +
3170 +/* Using sb_kattach depends on SB_BUS support, either implicit */
3171 +/* no limiting BCMBUSTYPE value) or explicit (value is SB_BUS). */
3172 +#if !defined(BCMBUSTYPE) || (BCMBUSTYPE == SB_BUS)
3173 +
3174 +/* global kernel resource */
3175 +static sb_info_t ksi;
3176 +
3177 +/* generic kernel variant of sb_attach() */
3178 +sb_t *
3179 +BCMINITFN(sb_kattach)()
3180 +{
3181 + uint32 *regs;
3182 +
3183 + if (ksi.curmap == NULL) {
3184 + uint32 cid;
3185 +
3186 + regs = (uint32 *)REG_MAP(SB_ENUM_BASE, SB_CORE_SIZE);
3187 + cid = R_REG((uint32 *)regs);
3188 + if (((cid & CID_ID_MASK) == BCM4712_DEVICE_ID) &&
3189 + ((cid & CID_PKG_MASK) != BCM4712LARGE_PKG_ID) &&
3190 + ((cid & CID_REV_MASK) <= (3 << CID_REV_SHIFT))) {
3191 + uint32 *scc, val;
3192 +
3193 + scc = (uint32 *)((uchar*)regs + OFFSETOF(chipcregs_t, slow_clk_ctl));
3194 + val = R_REG(scc);
3195 + SB_ERROR((" initial scc = 0x%x\n", val));
3196 + val |= SCC_SS_XTAL;
3197 + W_REG(scc, val);
3198 + }
3199 +
3200 + if (BCMINIT(sb_doattach)(&ksi, BCM4710_DEVICE_ID, NULL, (void*)regs,
3201 + SB_BUS, NULL, NULL, NULL) == NULL) {
3202 + return NULL;
3203 + }
3204 + }
3205 +
3206 + return (sb_t *)&ksi;
3207 +}
3208 +#endif
3209 +
3210 +static sb_info_t *
3211 +BCMINITFN(sb_doattach)(sb_info_t *si, uint devid, osl_t *osh, void *regs,
3212 + uint bustype, void *sdh, char **vars, int *varsz)
3213 +{
3214 + uint origidx;
3215 + chipcregs_t *cc;
3216 + sbconfig_t *sb;
3217 + uint32 w;
3218 +
3219 + ASSERT(GOODREGS(regs));
3220 +
3221 + bzero((uchar*)si, sizeof (sb_info_t));
3222 +
3223 + si->sb.buscoreidx = si->gpioidx = BADIDX;
3224 +
3225 + si->osh = osh;
3226 + si->curmap = regs;
3227 + si->sdh = sdh;
3228 +
3229 + /* check to see if we are a sb core mimic'ing a pci core */
3230 + if (bustype == PCI_BUS) {
3231 + if (OSL_PCI_READ_CONFIG(osh, PCI_SPROM_CONTROL, sizeof (uint32)) == 0xffffffff)
3232 + bustype = SB_BUS;
3233 + else
3234 + bustype = PCI_BUS;
3235 + }
3236 +
3237 + si->sb.bustype = bustype;
3238 + if (si->sb.bustype != BUSTYPE(si->sb.bustype)) {
3239 + SB_ERROR(("sb_doattach: bus type %d does not match configured bus type %d\n",
3240 + si->sb.bustype, BUSTYPE(si->sb.bustype)));
3241 + return NULL;
3242 + }
3243 +
3244 + /* kludge to enable the clock on the 4306 which lacks a slowclock */
3245 + if (BUSTYPE(si->sb.bustype) == PCI_BUS)
3246 + sb_clkctl_xtal(&si->sb, XTAL|PLL, ON);
3247 +
3248 + if (BUSTYPE(si->sb.bustype) == PCI_BUS) {
3249 + w = OSL_PCI_READ_CONFIG(osh, PCI_BAR0_WIN, sizeof (uint32));
3250 + if (!GOODCOREADDR(w))
3251 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_BAR0_WIN, sizeof (uint32), SB_ENUM_BASE);
3252 + }
3253 +
3254 + /* initialize current core index value */
3255 + si->curidx = _sb_coreidx(si);
3256 +
3257 + if (si->curidx == BADIDX) {
3258 + SB_ERROR(("sb_doattach: bad core index\n"));
3259 + return NULL;
3260 + }
3261 +
3262 + /* get sonics backplane revision */
3263 + sb = REGS2SB(si->curmap);
3264 + si->sb.sonicsrev = (R_SBREG(si, &(sb)->sbidlow) & SBIDL_RV_MASK) >> SBIDL_RV_SHIFT;
3265 +
3266 + /* keep and reuse the initial register mapping */
3267 + origidx = si->curidx;
3268 + if (BUSTYPE(si->sb.bustype) == SB_BUS)
3269 + si->regs[origidx] = regs;
3270 +
3271 + /* is core-0 a chipcommon core? */
3272 + si->numcores = 1;
3273 + cc = (chipcregs_t*) sb_setcoreidx(&si->sb, 0);
3274 + if (sb_coreid(&si->sb) != SB_CC)
3275 + cc = NULL;
3276 +
3277 + /* determine chip id and rev */
3278 + if (cc) {
3279 + /* chip common core found! */
3280 + si->sb.chip = R_REG(&cc->chipid) & CID_ID_MASK;
3281 + si->sb.chiprev = (R_REG(&cc->chipid) & CID_REV_MASK) >> CID_REV_SHIFT;
3282 + si->sb.chippkg = (R_REG(&cc->chipid) & CID_PKG_MASK) >> CID_PKG_SHIFT;
3283 + } else {
3284 + /* no chip common core -- must convert device id to chip id */
3285 + if ((si->sb.chip = BCMINIT(sb_pcidev2chip)(devid)) == 0) {
3286 + SB_ERROR(("sb_doattach: unrecognized device id 0x%04x\n", devid));
3287 + sb_setcoreidx(&si->sb, origidx);
3288 + return NULL;
3289 + }
3290 + }
3291 +
3292 + /* get chipcommon rev */
3293 + si->sb.ccrev = cc ? (int)sb_corerev(&si->sb) : NOREV;
3294 +
3295 + /* determine numcores */
3296 + if (cc && ((si->sb.ccrev == 4) || (si->sb.ccrev >= 6)))
3297 + si->numcores = (R_REG(&cc->chipid) & CID_CC_MASK) >> CID_CC_SHIFT;
3298 + else
3299 + si->numcores = BCMINIT(sb_chip2numcores)(si->sb.chip);
3300 +
3301 + /* return to original core */
3302 + sb_setcoreidx(&si->sb, origidx);
3303 +
3304 + /* sanity checks */
3305 + ASSERT(si->sb.chip);
3306 +
3307 + /* scan for cores */
3308 + BCMINIT(sb_scan)(si);
3309 +
3310 + /* fixup necessary chip/core configurations */
3311 + if (BUSTYPE(si->sb.bustype) == PCI_BUS) {
3312 + if (sb_pci_fixcfg(si)) {
3313 + SB_ERROR(("sb_doattach: sb_pci_fixcfg failed\n"));
3314 + return NULL;
3315 + }
3316 + }
3317 +
3318 + /* srom_var_init() depends on sb_scan() info */
3319 + if (srom_var_init(si, si->sb.bustype, si->curmap, osh, vars, varsz)) {
3320 + SB_ERROR(("sb_doattach: srom_var_init failed: bad srom\n"));
3321 + return (NULL);
3322 + }
3323 +
3324 + if (cc == NULL) {
3325 + /*
3326 + * The chip revision number is hardwired into all
3327 + * of the pci function config rev fields and is
3328 + * independent from the individual core revision numbers.
3329 + * For example, the "A0" silicon of each chip is chip rev 0.
3330 + */
3331 + if (BUSTYPE(si->sb.bustype) == PCI_BUS) {
3332 + w = OSL_PCI_READ_CONFIG(osh, PCI_CFG_REV, sizeof (uint32));
3333 + si->sb.chiprev = w & 0xff;
3334 + } else
3335 + si->sb.chiprev = 0;
3336 + }
3337 +
3338 + /* gpio control core is required */
3339 + if (!GOODIDX(si->gpioidx)) {
3340 + SB_ERROR(("sb_doattach: gpio control core not found\n"));
3341 + return NULL;
3342 + }
3343 +
3344 + /* get boardtype and boardrev */
3345 + switch (BUSTYPE(si->sb.bustype)) {
3346 + case PCI_BUS:
3347 + /* do a pci config read to get subsystem id and subvendor id */
3348 + w = OSL_PCI_READ_CONFIG(osh, PCI_CFG_SVID, sizeof (uint32));
3349 + si->sb.boardvendor = w & 0xffff;
3350 + si->sb.boardtype = (w >> 16) & 0xffff;
3351 + break;
3352 +
3353 + case SB_BUS:
3354 + case JTAG_BUS:
3355 + si->sb.boardvendor = VENDOR_BROADCOM;
3356 + if ((si->sb.boardtype = getintvar(NULL, "boardtype")) == 0)
3357 + si->sb.boardtype = 0xffff;
3358 + break;
3359 + }
3360 +
3361 + if (si->sb.boardtype == 0) {
3362 + SB_ERROR(("sb_doattach: unknown board type\n"));
3363 + ASSERT(si->sb.boardtype);
3364 + }
3365 +
3366 + /* setup the GPIO based LED powersave register */
3367 + if (si->sb.ccrev >= 16) {
3368 + w = getintvar(*vars, "gpiotimerval");
3369 + if (!w)
3370 + w = DEFAULT_GPIOTIMERVAL;
3371 + sb_corereg(si, 0, OFFSETOF(chipcregs_t, gpiotimerval), ~0, w);
3372 + }
3373 +
3374 +
3375 + return (si);
3376 +}
3377 +
3378 +uint
3379 +sb_coreid(sb_t *sbh)
3380 +{
3381 + sb_info_t *si;
3382 + sbconfig_t *sb;
3383 +
3384 + si = SB_INFO(sbh);
3385 + sb = REGS2SB(si->curmap);
3386 +
3387 + return ((R_SBREG(si, &(sb)->sbidhigh) & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT);
3388 +}
3389 +
3390 +uint
3391 +sb_coreidx(sb_t *sbh)
3392 +{
3393 + sb_info_t *si;
3394 +
3395 + si = SB_INFO(sbh);
3396 + return (si->curidx);
3397 +}
3398 +
3399 +/* return current index of core */
3400 +static uint
3401 +_sb_coreidx(sb_info_t *si)
3402 +{
3403 + sbconfig_t *sb;
3404 + uint32 sbaddr = 0;
3405 +
3406 + ASSERT(si);
3407 +
3408 + switch (BUSTYPE(si->sb.bustype)) {
3409 + case SB_BUS:
3410 + sb = REGS2SB(si->curmap);
3411 + sbaddr = sb_base(R_SBREG(si, &sb->sbadmatch0));
3412 + break;
3413 +
3414 + case PCI_BUS:
3415 + sbaddr = OSL_PCI_READ_CONFIG(si->osh, PCI_BAR0_WIN, sizeof (uint32));
3416 + break;
3417 +
3418 +#ifdef BCMJTAG
3419 + case JTAG_BUS:
3420 + sbaddr = (uint32)si->curmap;
3421 + break;
3422 +#endif /* BCMJTAG */
3423 +
3424 + default:
3425 + ASSERT(0);
3426 + }
3427 +
3428 + if (!GOODCOREADDR(sbaddr))
3429 + return BADIDX;
3430 +
3431 + return ((sbaddr - SB_ENUM_BASE) / SB_CORE_SIZE);
3432 +}
3433 +
3434 +uint
3435 +sb_corevendor(sb_t *sbh)
3436 +{
3437 + sb_info_t *si;
3438 + sbconfig_t *sb;
3439 +
3440 + si = SB_INFO(sbh);
3441 + sb = REGS2SB(si->curmap);
3442 +
3443 + return ((R_SBREG(si, &(sb)->sbidhigh) & SBIDH_VC_MASK) >> SBIDH_VC_SHIFT);
3444 +}
3445 +
3446 +uint
3447 +sb_corerev(sb_t *sbh)
3448 +{
3449 + sb_info_t *si;
3450 + sbconfig_t *sb;
3451 + uint sbidh;
3452 +
3453 + si = SB_INFO(sbh);
3454 + sb = REGS2SB(si->curmap);
3455 + sbidh = R_SBREG(si, &(sb)->sbidhigh);
3456 +
3457 + return (SBCOREREV(sbidh));
3458 +}
3459 +
3460 +void *
3461 +sb_osh(sb_t *sbh)
3462 +{
3463 + sb_info_t *si;
3464 +
3465 + si = SB_INFO(sbh);
3466 + return si->osh;
3467 +}
3468 +
3469 +#define SBTML_ALLOW (SBTML_PE | SBTML_FGC | SBTML_FL_MASK)
3470 +
3471 +/* set/clear sbtmstatelow core-specific flags */
3472 +uint32
3473 +sb_coreflags(sb_t *sbh, uint32 mask, uint32 val)
3474 +{
3475 + sb_info_t *si;
3476 + sbconfig_t *sb;
3477 + uint32 w;
3478 +
3479 + si = SB_INFO(sbh);
3480 + sb = REGS2SB(si->curmap);
3481 +
3482 + ASSERT((val & ~mask) == 0);
3483 + ASSERT((mask & ~SBTML_ALLOW) == 0);
3484 +
3485 + /* mask and set */
3486 + if (mask || val) {
3487 + w = (R_SBREG(si, &sb->sbtmstatelow) & ~mask) | val;
3488 + W_SBREG(si, &sb->sbtmstatelow, w);
3489 + }
3490 +
3491 + /* return the new value */
3492 + return (R_SBREG(si, &sb->sbtmstatelow) & SBTML_ALLOW);
3493 +}
3494 +
3495 +/* set/clear sbtmstatehigh core-specific flags */
3496 +uint32
3497 +sb_coreflagshi(sb_t *sbh, uint32 mask, uint32 val)
3498 +{
3499 + sb_info_t *si;
3500 + sbconfig_t *sb;
3501 + uint32 w;
3502 +
3503 + si = SB_INFO(sbh);
3504 + sb = REGS2SB(si->curmap);
3505 +
3506 + ASSERT((val & ~mask) == 0);
3507 + ASSERT((mask & ~SBTMH_FL_MASK) == 0);
3508 +
3509 + /* mask and set */
3510 + if (mask || val) {
3511 + w = (R_SBREG(si, &sb->sbtmstatehigh) & ~mask) | val;
3512 + W_SBREG(si, &sb->sbtmstatehigh, w);
3513 + }
3514 +
3515 + /* return the new value */
3516 + return (R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_FL_MASK);
3517 +}
3518 +
3519 +/* caller needs to take care of core-specific bist hazards */
3520 +int
3521 +sb_corebist(sb_t *sbh, uint coreid, uint coreunit)
3522 +{
3523 + uint32 sblo;
3524 + uint coreidx;
3525 + sb_info_t *si;
3526 + int result = 0;
3527 +
3528 + si = SB_INFO(sbh);
3529 +
3530 + coreidx = sb_findcoreidx(si, coreid, coreunit);
3531 + if (!GOODIDX(coreidx))
3532 + result = BCME_ERROR;
3533 + else {
3534 + sblo = sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatelow), 0, 0);
3535 + sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatelow), ~0, (sblo | SBTML_FGC | SBTML_BE));
3536 +
3537 + SPINWAIT(((sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatehigh), 0, 0) & SBTMH_BISTD) == 0), 100000);
3538 +
3539 + if (sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatehigh), 0, 0) & SBTMH_BISTF)
3540 + result = BCME_ERROR;
3541 +
3542 + sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatelow), ~0, sblo);
3543 + }
3544 +
3545 + return result;
3546 +}
3547 +
3548 +bool
3549 +sb_iscoreup(sb_t *sbh)
3550 +{
3551 + sb_info_t *si;
3552 + sbconfig_t *sb;
3553 +
3554 + si = SB_INFO(sbh);
3555 + sb = REGS2SB(si->curmap);
3556 +
3557 + return ((R_SBREG(si, &(sb)->sbtmstatelow) & (SBTML_RESET | SBTML_REJ_MASK | SBTML_CLK)) == SBTML_CLK);
3558 +}
3559 +
3560 +/*
3561 + * Switch to 'coreidx', issue a single arbitrary 32bit register mask&set operation,
3562 + * switch back to the original core, and return the new value.
3563 + */
3564 +static uint
3565 +sb_corereg(sb_info_t *si, uint coreidx, uint regoff, uint mask, uint val)
3566 +{
3567 + uint origidx;
3568 + uint32 *r;
3569 + uint w;
3570 + uint intr_val = 0;
3571 +
3572 + ASSERT(GOODIDX(coreidx));
3573 + ASSERT(regoff < SB_CORE_SIZE);
3574 + ASSERT((val & ~mask) == 0);
3575 +
3576 + INTR_OFF(si, intr_val);
3577 +
3578 + /* save current core index */
3579 + origidx = sb_coreidx(&si->sb);
3580 +
3581 + /* switch core */
3582 + r = (uint32*) ((uchar*) sb_setcoreidx(&si->sb, coreidx) + regoff);
3583 +
3584 + /* mask and set */
3585 + if (mask || val) {
3586 + if (regoff >= SBCONFIGOFF) {
3587 + w = (R_SBREG(si, r) & ~mask) | val;
3588 + W_SBREG(si, r, w);
3589 + } else {
3590 + w = (R_REG(r) & ~mask) | val;
3591 + W_REG(r, w);
3592 + }
3593 + }
3594 +
3595 + /* readback */
3596 + if (regoff >= SBCONFIGOFF)
3597 + w = R_SBREG(si, r);
3598 + else
3599 + w = R_REG(r);
3600 +
3601 + /* restore core index */
3602 + if (origidx != coreidx)
3603 + sb_setcoreidx(&si->sb, origidx);
3604 +
3605 + INTR_RESTORE(si, intr_val);
3606 + return (w);
3607 +}
3608 +
3609 +#define DWORD_ALIGN(x) (x & ~(0x03))
3610 +#define BYTE_POS(x) (x & 0x3)
3611 +#define WORD_POS(x) (x & 0x1)
3612 +
3613 +#define BYTE_SHIFT(x) (8 * BYTE_POS(x))
3614 +#define WORD_SHIFT(x) (16 * WORD_POS(x))
3615 +
3616 +#define BYTE_VAL(a, x) ((a >> BYTE_SHIFT(x)) & 0xFF)
3617 +#define WORD_VAL(a, x) ((a >> WORD_SHIFT(x)) & 0xFFFF)
3618 +
3619 +#define read_pci_cfg_byte(a) \
3620 + (BYTE_VAL(OSL_PCI_READ_CONFIG(si->osh, DWORD_ALIGN(a), 4), a) & 0xff)
3621 +
3622 +#define read_pci_cfg_write(a) \
3623 + (WORD_VAL(OSL_PCI_READ_CONFIG(si->osh, DWORD_ALIGN(a), 4), a) & 0xffff)
3624 +
3625 +
3626 +/* scan the sb enumerated space to identify all cores */
3627 +static void
3628 +BCMINITFN(sb_scan)(sb_info_t *si)
3629 +{
3630 + uint origidx;
3631 + uint i;
3632 + bool pci;
3633 + uint pciidx;
3634 + uint pcirev;
3635 +
3636 +
3637 +
3638 + /* numcores should already be set */
3639 + ASSERT((si->numcores > 0) && (si->numcores <= SB_MAXCORES));
3640 +
3641 + /* save current core index */
3642 + origidx = sb_coreidx(&si->sb);
3643 +
3644 + si->sb.buscorerev = NOREV;
3645 + si->sb.buscoreidx = BADIDX;
3646 +
3647 + si->gpioidx = BADIDX;
3648 +
3649 + pci = FALSE;
3650 + pcirev = NOREV;
3651 + pciidx = BADIDX;
3652 +
3653 + for (i = 0; i < si->numcores; i++) {
3654 + sb_setcoreidx(&si->sb, i);
3655 + si->coreid[i] = sb_coreid(&si->sb);
3656 +
3657 + if (si->coreid[i] == SB_PCI) {
3658 + pciidx = i;
3659 + pcirev = sb_corerev(&si->sb);
3660 + pci = TRUE;
3661 + }
3662 + }
3663 + if (pci) {
3664 + si->sb.buscoretype = SB_PCI;
3665 + si->sb.buscorerev = pcirev;
3666 + si->sb.buscoreidx = pciidx;
3667 + }
3668 +
3669 + /*
3670 + * Find the gpio "controlling core" type and index.
3671 + * Precedence:
3672 + * - if there's a chip common core - use that
3673 + * - else if there's a pci core (rev >= 2) - use that
3674 + * - else there had better be an extif core (4710 only)
3675 + */
3676 + if (GOODIDX(sb_findcoreidx(si, SB_CC, 0))) {
3677 + si->gpioidx = sb_findcoreidx(si, SB_CC, 0);
3678 + si->gpioid = SB_CC;
3679 + } else if (PCI(si) && (si->sb.buscorerev >= 2)) {
3680 + si->gpioidx = si->sb.buscoreidx;
3681 + si->gpioid = SB_PCI;
3682 + } else if (sb_findcoreidx(si, SB_EXTIF, 0)) {
3683 + si->gpioidx = sb_findcoreidx(si, SB_EXTIF, 0);
3684 + si->gpioid = SB_EXTIF;
3685 + } else
3686 + ASSERT(si->gpioidx != BADIDX);
3687 +
3688 + /* return to original core index */
3689 + sb_setcoreidx(&si->sb, origidx);
3690 +}
3691 +
3692 +/* may be called with core in reset */
3693 +void
3694 +sb_detach(sb_t *sbh)
3695 +{
3696 + sb_info_t *si;
3697 + uint idx;
3698 +
3699 + si = SB_INFO(sbh);
3700 +
3701 + if (si == NULL)
3702 + return;
3703 +
3704 + if (BUSTYPE(si->sb.bustype) == SB_BUS)
3705 + for (idx = 0; idx < SB_MAXCORES; idx++)
3706 + if (si->regs[idx]) {
3707 + REG_UNMAP(si->regs[idx]);
3708 + si->regs[idx] = NULL;
3709 + }
3710 +
3711 + if (si != &ksi)
3712 + MFREE(si->osh, si, sizeof (sb_info_t));
3713 +}
3714 +
3715 +/* use pci dev id to determine chip id for chips not having a chipcommon core */
3716 +static uint
3717 +BCMINITFN(sb_pcidev2chip)(uint pcidev)
3718 +{
3719 + if ((pcidev >= BCM4710_DEVICE_ID) && (pcidev <= BCM47XX_USB_ID))
3720 + return (BCM4710_DEVICE_ID);
3721 + if ((pcidev >= BCM4402_DEVICE_ID) && (pcidev <= BCM4402_V90_ID))
3722 + return (BCM4402_DEVICE_ID);
3723 + if (pcidev == BCM4401_ENET_ID)
3724 + return (BCM4402_DEVICE_ID);
3725 + if ((pcidev >= BCM4307_V90_ID) && (pcidev <= BCM4307_D11B_ID))
3726 + return (BCM4307_DEVICE_ID);
3727 + if (pcidev == BCM4301_DEVICE_ID)
3728 + return (BCM4301_DEVICE_ID);
3729 +
3730 + return (0);
3731 +}
3732 +
3733 +/* convert chip number to number of i/o cores */
3734 +static uint
3735 +BCMINITFN(sb_chip2numcores)(uint chip)
3736 +{
3737 + if (chip == BCM4710_DEVICE_ID)
3738 + return (9);
3739 + if (chip == BCM4402_DEVICE_ID)
3740 + return (3);
3741 + if ((chip == BCM4301_DEVICE_ID) || (chip == BCM4307_DEVICE_ID))
3742 + return (5);
3743 + if (chip == BCM4306_DEVICE_ID) /* < 4306c0 */
3744 + return (6);
3745 + if (chip == BCM4704_DEVICE_ID)
3746 + return (9);
3747 + if (chip == BCM5365_DEVICE_ID)
3748 + return (7);
3749 +
3750 + SB_ERROR(("sb_chip2numcores: unsupported chip 0x%x\n", chip));
3751 + ASSERT(0);
3752 + return (1);
3753 +}
3754 +
3755 +/* return index of coreid or BADIDX if not found */
3756 +static uint
3757 +sb_findcoreidx( sb_info_t *si, uint coreid, uint coreunit)
3758 +{
3759 + uint found;
3760 + uint i;
3761 +
3762 + found = 0;
3763 +
3764 + for (i = 0; i < si->numcores; i++)
3765 + if (si->coreid[i] == coreid) {
3766 + if (found == coreunit)
3767 + return (i);
3768 + found++;
3769 + }
3770 +
3771 + return (BADIDX);
3772 +}
3773 +
3774 +/*
3775 + * this function changes logical "focus" to the indiciated core,
3776 + * must be called with interrupt off.
3777 + * Moreover, callers should keep interrupts off during switching out of and back to d11 core
3778 + */
3779 +void*
3780 +sb_setcoreidx(sb_t *sbh, uint coreidx)
3781 +{
3782 + sb_info_t *si;
3783 + uint32 sbaddr;
3784 +
3785 + si = SB_INFO(sbh);
3786 +
3787 + if (coreidx >= si->numcores)
3788 + return (NULL);
3789 +
3790 + /*
3791 + * If the user has provided an interrupt mask enabled function,
3792 + * then assert interrupts are disabled before switching the core.
3793 + */
3794 + ASSERT((si->intrsenabled_fn == NULL) || !(*(si)->intrsenabled_fn)((si)->intr_arg));
3795 +
3796 + sbaddr = SB_ENUM_BASE + (coreidx * SB_CORE_SIZE);
3797 +
3798 + switch (BUSTYPE(si->sb.bustype)) {
3799 + case SB_BUS:
3800 + /* map new one */
3801 + if (!si->regs[coreidx]) {
3802 + si->regs[coreidx] = (void*)REG_MAP(sbaddr, SB_CORE_SIZE);
3803 + ASSERT(GOODREGS(si->regs[coreidx]));
3804 + }
3805 + si->curmap = si->regs[coreidx];
3806 + break;
3807 +
3808 + case PCI_BUS:
3809 + /* point bar0 window */
3810 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_BAR0_WIN, 4, sbaddr);
3811 + break;
3812 +
3813 +#ifdef BCMJTAG
3814 + case JTAG_BUS:
3815 + /* map new one */
3816 + if (!si->regs[coreidx]) {
3817 + si->regs[coreidx] = (void *)sbaddr;
3818 + ASSERT(GOODREGS(si->regs[coreidx]));
3819 + }
3820 + si->curmap = si->regs[coreidx];
3821 + break;
3822 +#endif /* BCMJTAG */
3823 + }
3824 +
3825 + si->curidx = coreidx;
3826 +
3827 + return (si->curmap);
3828 +}
3829 +
3830 +/*
3831 + * this function changes logical "focus" to the indiciated core,
3832 + * must be called with interrupt off.
3833 + * Moreover, callers should keep interrupts off during switching out of and back to d11 core
3834 + */
3835 +void*
3836 +sb_setcore(sb_t *sbh, uint coreid, uint coreunit)
3837 +{
3838 + sb_info_t *si;
3839 + uint idx;
3840 +
3841 + si = SB_INFO(sbh);
3842 + idx = sb_findcoreidx(si, coreid, coreunit);
3843 + if (!GOODIDX(idx))
3844 + return (NULL);
3845 +
3846 + return (sb_setcoreidx(sbh, idx));
3847 +}
3848 +
3849 +/* return chip number */
3850 +uint
3851 +BCMINITFN(sb_chip)(sb_t *sbh)
3852 +{
3853 + sb_info_t *si;
3854 +
3855 + si = SB_INFO(sbh);
3856 + return (si->sb.chip);
3857 +}
3858 +
3859 +/* return chip revision number */
3860 +uint
3861 +BCMINITFN(sb_chiprev)(sb_t *sbh)
3862 +{
3863 + sb_info_t *si;
3864 +
3865 + si = SB_INFO(sbh);
3866 + return (si->sb.chiprev);
3867 +}
3868 +
3869 +/* return chip common revision number */
3870 +uint
3871 +BCMINITFN(sb_chipcrev)(sb_t *sbh)
3872 +{
3873 + sb_info_t *si;
3874 +
3875 + si = SB_INFO(sbh);
3876 + return (si->sb.ccrev);
3877 +}
3878 +
3879 +/* return chip package option */
3880 +uint
3881 +BCMINITFN(sb_chippkg)(sb_t *sbh)
3882 +{
3883 + sb_info_t *si;
3884 +
3885 + si = SB_INFO(sbh);
3886 + return (si->sb.chippkg);
3887 +}
3888 +
3889 +/* return PCI core rev. */
3890 +uint
3891 +BCMINITFN(sb_pcirev)(sb_t *sbh)
3892 +{
3893 + sb_info_t *si;
3894 +
3895 + si = SB_INFO(sbh);
3896 + return (si->sb.buscorerev);
3897 +}
3898 +
3899 +bool
3900 +BCMINITFN(sb_war16165)(sb_t *sbh)
3901 +{
3902 + sb_info_t *si;
3903 +
3904 + si = SB_INFO(sbh);
3905 +
3906 + return (PCI(si) && (si->sb.buscorerev <= 10));
3907 +}
3908 +
3909 +/* return board vendor id */
3910 +uint
3911 +BCMINITFN(sb_boardvendor)(sb_t *sbh)
3912 +{
3913 + sb_info_t *si;
3914 +
3915 + si = SB_INFO(sbh);
3916 + return (si->sb.boardvendor);
3917 +}
3918 +
3919 +/* return boardtype */
3920 +uint
3921 +BCMINITFN(sb_boardtype)(sb_t *sbh)
3922 +{
3923 + sb_info_t *si;
3924 + char *var;
3925 +
3926 + si = SB_INFO(sbh);
3927 +
3928 + if (BUSTYPE(si->sb.bustype) == SB_BUS && si->sb.boardtype == 0xffff) {
3929 + /* boardtype format is a hex string */
3930 + si->sb.boardtype = getintvar(NULL, "boardtype");
3931 +
3932 + /* backward compatibility for older boardtype string format */
3933 + if ((si->sb.boardtype == 0) && (var = getvar(NULL, "boardtype"))) {
3934 + if (!strcmp(var, "bcm94710dev"))
3935 + si->sb.boardtype = BCM94710D_BOARD;
3936 + else if (!strcmp(var, "bcm94710ap"))
3937 + si->sb.boardtype = BCM94710AP_BOARD;
3938 + else if (!strcmp(var, "bu4710"))
3939 + si->sb.boardtype = BU4710_BOARD;
3940 + else if (!strcmp(var, "bcm94702mn"))
3941 + si->sb.boardtype = BCM94702MN_BOARD;
3942 + else if (!strcmp(var, "bcm94710r1"))
3943 + si->sb.boardtype = BCM94710R1_BOARD;
3944 + else if (!strcmp(var, "bcm94710r4"))
3945 + si->sb.boardtype = BCM94710R4_BOARD;
3946 + else if (!strcmp(var, "bcm94702cpci"))
3947 + si->sb.boardtype = BCM94702CPCI_BOARD;
3948 + else if (!strcmp(var, "bcm95380_rr"))
3949 + si->sb.boardtype = BCM95380RR_BOARD;
3950 + }
3951 + }
3952 +
3953 + return (si->sb.boardtype);
3954 +}
3955 +
3956 +/* return bus type of sbh device */
3957 +uint
3958 +sb_bus(sb_t *sbh)
3959 +{
3960 + sb_info_t *si;
3961 +
3962 + si = SB_INFO(sbh);
3963 + return (si->sb.bustype);
3964 +}
3965 +
3966 +/* return bus core type */
3967 +uint
3968 +sb_buscoretype(sb_t *sbh)
3969 +{
3970 + sb_info_t *si;
3971 +
3972 + si = SB_INFO(sbh);
3973 +
3974 + return (si->sb.buscoretype);
3975 +}
3976 +
3977 +/* return bus core revision */
3978 +uint
3979 +sb_buscorerev(sb_t *sbh)
3980 +{
3981 + sb_info_t *si;
3982 + si = SB_INFO(sbh);
3983 +
3984 + return (si->sb.buscorerev);
3985 +}
3986 +
3987 +/* return list of found cores */
3988 +uint
3989 +sb_corelist(sb_t *sbh, uint coreid[])
3990 +{
3991 + sb_info_t *si;
3992 +
3993 + si = SB_INFO(sbh);
3994 +
3995 + bcopy((uchar*)si->coreid, (uchar*)coreid, (si->numcores * sizeof (uint)));
3996 + return (si->numcores);
3997 +}
3998 +
3999 +/* return current register mapping */
4000 +void *
4001 +sb_coreregs(sb_t *sbh)
4002 +{
4003 + sb_info_t *si;
4004 +
4005 + si = SB_INFO(sbh);
4006 + ASSERT(GOODREGS(si->curmap));
4007 +
4008 + return (si->curmap);
4009 +}
4010 +
4011 +
4012 +/* do buffered registers update */
4013 +void
4014 +sb_commit(sb_t *sbh)
4015 +{
4016 + sb_info_t *si;
4017 + uint origidx;
4018 + uint intr_val = 0;
4019 +
4020 + si = SB_INFO(sbh);
4021 +
4022 + origidx = si->curidx;
4023 + ASSERT(GOODIDX(origidx));
4024 +
4025 + INTR_OFF(si, intr_val);
4026 +
4027 + /* switch over to chipcommon core if there is one, else use pci */
4028 + if (si->sb.ccrev != NOREV) {
4029 + chipcregs_t *ccregs = (chipcregs_t *)sb_setcore(sbh, SB_CC, 0);
4030 +
4031 + /* do the buffer registers update */
4032 + W_REG(&ccregs->broadcastaddress, SB_COMMIT);
4033 + W_REG(&ccregs->broadcastdata, 0x0);
4034 + } else if (PCI(si)) {
4035 + sbpciregs_t *pciregs = (sbpciregs_t *)sb_setcore(sbh, SB_PCI, 0);
4036 +
4037 + /* do the buffer registers update */
4038 + W_REG(&pciregs->bcastaddr, SB_COMMIT);
4039 + W_REG(&pciregs->bcastdata, 0x0);
4040 + } else
4041 + ASSERT(0);
4042 +
4043 + /* restore core index */
4044 + sb_setcoreidx(sbh, origidx);
4045 + INTR_RESTORE(si, intr_val);
4046 +}
4047 +
4048 +/* reset and re-enable a core */
4049 +void
4050 +sb_core_reset(sb_t *sbh, uint32 bits)
4051 +{
4052 + sb_info_t *si;
4053 + sbconfig_t *sb;
4054 + volatile uint32 dummy;
4055 +
4056 + si = SB_INFO(sbh);
4057 + ASSERT(GOODREGS(si->curmap));
4058 + sb = REGS2SB(si->curmap);
4059 +
4060 + /*
4061 + * Must do the disable sequence first to work for arbitrary current core state.
4062 + */
4063 + sb_core_disable(sbh, bits);
4064 +
4065 + /*
4066 + * Now do the initialization sequence.
4067 + */
4068 +
4069 + /* set reset while enabling the clock and forcing them on throughout the core */
4070 + W_SBREG(si, &sb->sbtmstatelow, (SBTML_FGC | SBTML_CLK | SBTML_RESET | bits));
4071 + dummy = R_SBREG(si, &sb->sbtmstatelow);
4072 + OSL_DELAY(1);
4073 +
4074 + if (R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_SERR) {
4075 + W_SBREG(si, &sb->sbtmstatehigh, 0);
4076 + }
4077 + if ((dummy = R_SBREG(si, &sb->sbimstate)) & (SBIM_IBE | SBIM_TO)) {
4078 + AND_SBREG(si, &sb->sbimstate, ~(SBIM_IBE | SBIM_TO));
4079 + }
4080 +
4081 + /* clear reset and allow it to propagate throughout the core */
4082 + W_SBREG(si, &sb->sbtmstatelow, (SBTML_FGC | SBTML_CLK | bits));
4083 + dummy = R_SBREG(si, &sb->sbtmstatelow);
4084 + OSL_DELAY(1);
4085 +
4086 + /* leave clock enabled */
4087 + W_SBREG(si, &sb->sbtmstatelow, (SBTML_CLK | bits));
4088 + dummy = R_SBREG(si, &sb->sbtmstatelow);
4089 + OSL_DELAY(1);
4090 +}
4091 +
4092 +void
4093 +sb_core_tofixup(sb_t *sbh)
4094 +{
4095 + sb_info_t *si;
4096 + sbconfig_t *sb;
4097 +
4098 + si = SB_INFO(sbh);
4099 +
4100 + if ( (BUSTYPE(si->sb.bustype) != PCI_BUS) || (PCI(si) && (si->sb.buscorerev >= 5)) )
4101 + return;
4102 +
4103 + ASSERT(GOODREGS(si->curmap));
4104 + sb = REGS2SB(si->curmap);
4105 +
4106 + if (BUSTYPE(si->sb.bustype) == SB_BUS) {
4107 + SET_SBREG(si, &sb->sbimconfiglow,
4108 + SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
4109 + (0x5 << SBIMCL_RTO_SHIFT) | 0x3);
4110 + } else {
4111 + if (sb_coreid(sbh) == SB_PCI) {
4112 + SET_SBREG(si, &sb->sbimconfiglow,
4113 + SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
4114 + (0x3 << SBIMCL_RTO_SHIFT) | 0x2);
4115 + } else {
4116 + SET_SBREG(si, &sb->sbimconfiglow, (SBIMCL_RTO_MASK | SBIMCL_STO_MASK), 0);
4117 + }
4118 + }
4119 +
4120 + sb_commit(sbh);
4121 +}
4122 +
4123 +/*
4124 + * Set the initiator timeout for the "master core".
4125 + * The master core is defined to be the core in control
4126 + * of the chip and so it issues accesses to non-memory
4127 + * locations (Because of dma *any* core can access memeory).
4128 + *
4129 + * The routine uses the bus to decide who is the master:
4130 + * SB_BUS => mips
4131 + * JTAG_BUS => chipc
4132 + * PCI_BUS => pci
4133 + *
4134 + * This routine exists so callers can disable initiator
4135 + * timeouts so accesses to very slow devices like otp
4136 + * won't cause an abort. The routine allows arbitrary
4137 + * settings of the service and request timeouts, though.
4138 + *
4139 + * Returns the timeout state before changing it or -1
4140 + * on error.
4141 + */
4142 +
4143 +#define TO_MASK (SBIMCL_RTO_MASK | SBIMCL_STO_MASK)
4144 +
4145 +uint32
4146 +sb_set_initiator_to(sb_t *sbh, uint32 to)
4147 +{
4148 + sb_info_t *si;
4149 + uint origidx, idx;
4150 + uint intr_val = 0;
4151 + uint32 tmp, ret = 0xffffffff;
4152 + sbconfig_t *sb;
4153 +
4154 + si = SB_INFO(sbh);
4155 +
4156 + if ((to & ~TO_MASK) != 0)
4157 + return ret;
4158 +
4159 + /* Figure out the master core */
4160 + idx = BADIDX;
4161 + switch (BUSTYPE(si->sb.bustype)) {
4162 + case PCI_BUS:
4163 + idx = si->sb.buscoreidx;
4164 + break;
4165 + case JTAG_BUS:
4166 + idx = SB_CC_IDX;
4167 + break;
4168 + case SB_BUS:
4169 + if ((idx = sb_findcoreidx(si, SB_MIPS33, 0)) == BADIDX)
4170 + idx = sb_findcoreidx(si, SB_MIPS, 0);
4171 + break;
4172 + default:
4173 + ASSERT(0);
4174 + }
4175 + if (idx == BADIDX)
4176 + return ret;
4177 +
4178 + INTR_OFF(si, intr_val);
4179 + origidx = sb_coreidx(sbh);
4180 +
4181 + sb = REGS2SB(sb_setcoreidx(sbh, idx));
4182 +
4183 + tmp = R_SBREG(si, &sb->sbimconfiglow);
4184 + ret = tmp & TO_MASK;
4185 + W_SBREG(si, &sb->sbimconfiglow, (tmp & ~TO_MASK) | to);
4186 +
4187 + sb_commit(sbh);
4188 + sb_setcoreidx(sbh, origidx);
4189 + INTR_RESTORE(si, intr_val);
4190 + return ret;
4191 +}
4192 +
4193 +void
4194 +sb_core_disable(sb_t *sbh, uint32 bits)
4195 +{
4196 + sb_info_t *si;
4197 + volatile uint32 dummy;
4198 + uint32 rej;
4199 + sbconfig_t *sb;
4200 +
4201 + si = SB_INFO(sbh);
4202 +
4203 + ASSERT(GOODREGS(si->curmap));
4204 + sb = REGS2SB(si->curmap);
4205 +
4206 + /* if core is already in reset, just return */
4207 + if (R_SBREG(si, &sb->sbtmstatelow) & SBTML_RESET)
4208 + return;
4209 +
4210 + /* reject value changed between sonics 2.2 and 2.3 */
4211 + if (si->sb.sonicsrev == SONICS_2_2)
4212 + rej = (1 << SBTML_REJ_SHIFT);
4213 + else
4214 + rej = (2 << SBTML_REJ_SHIFT);
4215 +
4216 + /* if clocks are not enabled, put into reset and return */
4217 + if ((R_SBREG(si, &sb->sbtmstatelow) & SBTML_CLK) == 0)
4218 + goto disable;
4219 +
4220 + /* set target reject and spin until busy is clear (preserve core-specific bits) */
4221 + OR_SBREG(si, &sb->sbtmstatelow, rej);
4222 + dummy = R_SBREG(si, &sb->sbtmstatelow);
4223 + OSL_DELAY(1);
4224 + SPINWAIT((R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_BUSY), 100000);
4225 +
4226 + if (R_SBREG(si, &sb->sbidlow) & SBIDL_INIT) {
4227 + OR_SBREG(si, &sb->sbimstate, SBIM_RJ);
4228 + dummy = R_SBREG(si, &sb->sbimstate);
4229 + OSL_DELAY(1);
4230 + SPINWAIT((R_SBREG(si, &sb->sbimstate) & SBIM_BY), 100000);
4231 + }
4232 +
4233 + /* set reset and reject while enabling the clocks */
4234 + W_SBREG(si, &sb->sbtmstatelow, (bits | SBTML_FGC | SBTML_CLK | rej | SBTML_RESET));
4235 + dummy = R_SBREG(si, &sb->sbtmstatelow);
4236 + OSL_DELAY(10);
4237 +
4238 + /* don't forget to clear the initiator reject bit */
4239 + if (R_SBREG(si, &sb->sbidlow) & SBIDL_INIT)
4240 + AND_SBREG(si, &sb->sbimstate, ~SBIM_RJ);
4241 +
4242 +disable:
4243 + /* leave reset and reject asserted */
4244 + W_SBREG(si, &sb->sbtmstatelow, (bits | rej | SBTML_RESET));
4245 + OSL_DELAY(1);
4246 +}
4247 +
4248 +/* set chip watchdog reset timer to fire in 'ticks' backplane cycles */
4249 +void
4250 +sb_watchdog(sb_t *sbh, uint ticks)
4251 +{
4252 + sb_info_t *si = SB_INFO(sbh);
4253 +
4254 + /* instant NMI */
4255 + switch (si->gpioid) {
4256 + case SB_CC:
4257 + sb_corereg(si, 0, OFFSETOF(chipcregs_t, watchdog), ~0, ticks);
4258 + break;
4259 + case SB_EXTIF:
4260 + sb_corereg(si, si->gpioidx, OFFSETOF(extifregs_t, watchdog), ~0, ticks);
4261 + break;
4262 + }
4263 +}
4264 +
4265 +
4266 +/*
4267 + * Configure the pci core for pci client (NIC) action
4268 + * coremask is the bitvec of cores by index to be enabled.
4269 + */
4270 +void
4271 +sb_pci_setup(sb_t *sbh, uint coremask)
4272 +{
4273 + sb_info_t *si;
4274 + sbconfig_t *sb;
4275 + sbpciregs_t *pciregs;
4276 + uint32 sbflag;
4277 + uint32 w;
4278 + uint idx;
4279 +
4280 + si = SB_INFO(sbh);
4281 +
4282 + /* if not pci bus, we're done */
4283 + if (BUSTYPE(si->sb.bustype) != PCI_BUS)
4284 + return;
4285 +
4286 + ASSERT(PCI(si));
4287 + ASSERT(si->sb.buscoreidx != BADIDX);
4288 +
4289 + /* get current core index */
4290 + idx = si->curidx;
4291 +
4292 + /* we interrupt on this backplane flag number */
4293 + ASSERT(GOODREGS(si->curmap));
4294 + sb = REGS2SB(si->curmap);
4295 + sbflag = R_SBREG(si, &sb->sbtpsflag) & SBTPS_NUM0_MASK;
4296 +
4297 + /* switch over to pci core */
4298 + pciregs = (sbpciregs_t*) sb_setcoreidx(sbh, si->sb.buscoreidx);
4299 + sb = REGS2SB(pciregs);
4300 +
4301 + /*
4302 + * Enable sb->pci interrupts. Assume
4303 + * PCI rev 2.3 support was added in pci core rev 6 and things changed..
4304 + */
4305 + if ((PCI(si) && ((si->sb.buscorerev) >= 6))) {
4306 + /* pci config write to set this core bit in PCIIntMask */
4307 + w = OSL_PCI_READ_CONFIG(si->osh, PCI_INT_MASK, sizeof(uint32));
4308 + w |= (coremask << PCI_SBIM_SHIFT);
4309 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_INT_MASK, sizeof(uint32), w);
4310 + } else {
4311 + /* set sbintvec bit for our flag number */
4312 + OR_SBREG(si, &sb->sbintvec, (1 << sbflag));
4313 + }
4314 +
4315 + if (PCI(si)) {
4316 + OR_REG(&pciregs->sbtopci2, (SBTOPCI_PREF|SBTOPCI_BURST));
4317 + if (si->sb.buscorerev >= 11)
4318 + OR_REG(&pciregs->sbtopci2, SBTOPCI_RC_READMULTI);
4319 + if (si->sb.buscorerev < 5) {
4320 + SET_SBREG(si, &sb->sbimconfiglow, SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
4321 + (0x3 << SBIMCL_RTO_SHIFT) | 0x2);
4322 + sb_commit(sbh);
4323 + }
4324 + }
4325 +
4326 + /* switch back to previous core */
4327 + sb_setcoreidx(sbh, idx);
4328 +}
4329 +
4330 +uint32
4331 +sb_base(uint32 admatch)
4332 +{
4333 + uint32 base;
4334 + uint type;
4335 +
4336 + type = admatch & SBAM_TYPE_MASK;
4337 + ASSERT(type < 3);
4338 +
4339 + base = 0;
4340 +
4341 + if (type == 0) {
4342 + base = admatch & SBAM_BASE0_MASK;
4343 + } else if (type == 1) {
4344 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
4345 + base = admatch & SBAM_BASE1_MASK;
4346 + } else if (type == 2) {
4347 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
4348 + base = admatch & SBAM_BASE2_MASK;
4349 + }
4350 +
4351 + return (base);
4352 +}
4353 +
4354 +uint32
4355 +sb_size(uint32 admatch)
4356 +{
4357 + uint32 size;
4358 + uint type;
4359 +
4360 + type = admatch & SBAM_TYPE_MASK;
4361 + ASSERT(type < 3);
4362 +
4363 + size = 0;
4364 +
4365 + if (type == 0) {
4366 + size = 1 << (((admatch & SBAM_ADINT0_MASK) >> SBAM_ADINT0_SHIFT) + 1);
4367 + } else if (type == 1) {
4368 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
4369 + size = 1 << (((admatch & SBAM_ADINT1_MASK) >> SBAM_ADINT1_SHIFT) + 1);
4370 + } else if (type == 2) {
4371 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
4372 + size = 1 << (((admatch & SBAM_ADINT2_MASK) >> SBAM_ADINT2_SHIFT) + 1);
4373 + }
4374 +
4375 + return (size);
4376 +}
4377 +
4378 +/* return the core-type instantiation # of the current core */
4379 +uint
4380 +sb_coreunit(sb_t *sbh)
4381 +{
4382 + sb_info_t *si;
4383 + uint idx;
4384 + uint coreid;
4385 + uint coreunit;
4386 + uint i;
4387 +
4388 + si = SB_INFO(sbh);
4389 + coreunit = 0;
4390 +
4391 + idx = si->curidx;
4392 +
4393 + ASSERT(GOODREGS(si->curmap));
4394 + coreid = sb_coreid(sbh);
4395 +
4396 + /* count the cores of our type */
4397 + for (i = 0; i < idx; i++)
4398 + if (si->coreid[i] == coreid)
4399 + coreunit++;
4400 +
4401 + return (coreunit);
4402 +}
4403 +
4404 +static INLINE uint32
4405 +factor6(uint32 x)
4406 +{
4407 + switch (x) {
4408 + case CC_F6_2: return 2;
4409 + case CC_F6_3: return 3;
4410 + case CC_F6_4: return 4;
4411 + case CC_F6_5: return 5;
4412 + case CC_F6_6: return 6;
4413 + case CC_F6_7: return 7;
4414 + default: return 0;
4415 + }
4416 +}
4417 +
4418 +/* calculate the speed the SB would run at given a set of clockcontrol values */
4419 +uint32
4420 +sb_clock_rate(uint32 pll_type, uint32 n, uint32 m)
4421 +{
4422 + uint32 n1, n2, clock, m1, m2, m3, mc;
4423 +
4424 + n1 = n & CN_N1_MASK;
4425 + n2 = (n & CN_N2_MASK) >> CN_N2_SHIFT;
4426 +
4427 + if (pll_type == PLL_TYPE6) {
4428 + if (m & CC_T6_MMASK)
4429 + return CC_T6_M1;
4430 + else
4431 + return CC_T6_M0;
4432 + } else if ((pll_type == PLL_TYPE1) ||
4433 + (pll_type == PLL_TYPE3) ||
4434 + (pll_type == PLL_TYPE4) ||
4435 + (pll_type == PLL_TYPE7)) {
4436 + n1 = factor6(n1);
4437 + n2 += CC_F5_BIAS;
4438 + } else if (pll_type == PLL_TYPE2) {
4439 + n1 += CC_T2_BIAS;
4440 + n2 += CC_T2_BIAS;
4441 + ASSERT((n1 >= 2) && (n1 <= 7));
4442 + ASSERT((n2 >= 5) && (n2 <= 23));
4443 + } else if (pll_type == PLL_TYPE5) {
4444 + return (100000000);
4445 + } else
4446 + ASSERT(0);
4447 + /* PLL types 3 and 7 use BASE2 (25Mhz) */
4448 + if ((pll_type == PLL_TYPE3) ||
4449 + (pll_type == PLL_TYPE7)) {
4450 + clock = CC_CLOCK_BASE2 * n1 * n2;
4451 + }
4452 + else
4453 + clock = CC_CLOCK_BASE1 * n1 * n2;
4454 +
4455 + if (clock == 0)
4456 + return 0;
4457 +
4458 + m1 = m & CC_M1_MASK;
4459 + m2 = (m & CC_M2_MASK) >> CC_M2_SHIFT;
4460 + m3 = (m & CC_M3_MASK) >> CC_M3_SHIFT;
4461 + mc = (m & CC_MC_MASK) >> CC_MC_SHIFT;
4462 +
4463 + if ((pll_type == PLL_TYPE1) ||
4464 + (pll_type == PLL_TYPE3) ||
4465 + (pll_type == PLL_TYPE4) ||
4466 + (pll_type == PLL_TYPE7)) {
4467 + m1 = factor6(m1);
4468 + if ((pll_type == PLL_TYPE1) || (pll_type == PLL_TYPE3))
4469 + m2 += CC_F5_BIAS;
4470 + else
4471 + m2 = factor6(m2);
4472 + m3 = factor6(m3);
4473 +
4474 + switch (mc) {
4475 + case CC_MC_BYPASS: return (clock);
4476 + case CC_MC_M1: return (clock / m1);
4477 + case CC_MC_M1M2: return (clock / (m1 * m2));
4478 + case CC_MC_M1M2M3: return (clock / (m1 * m2 * m3));
4479 + case CC_MC_M1M3: return (clock / (m1 * m3));
4480 + default: return (0);
4481 + }
4482 + } else {
4483 + ASSERT(pll_type == PLL_TYPE2);
4484 +
4485 + m1 += CC_T2_BIAS;
4486 + m2 += CC_T2M2_BIAS;
4487 + m3 += CC_T2_BIAS;
4488 + ASSERT((m1 >= 2) && (m1 <= 7));
4489 + ASSERT((m2 >= 3) && (m2 <= 10));
4490 + ASSERT((m3 >= 2) && (m3 <= 7));
4491 +
4492 + if ((mc & CC_T2MC_M1BYP) == 0)
4493 + clock /= m1;
4494 + if ((mc & CC_T2MC_M2BYP) == 0)
4495 + clock /= m2;
4496 + if ((mc & CC_T2MC_M3BYP) == 0)
4497 + clock /= m3;
4498 +
4499 + return(clock);
4500 + }
4501 +}
4502 +
4503 +/* returns the current speed the SB is running at */
4504 +uint32
4505 +sb_clock(sb_t *sbh)
4506 +{
4507 + sb_info_t *si;
4508 + extifregs_t *eir;
4509 + chipcregs_t *cc;
4510 + uint32 n, m;
4511 + uint idx;
4512 + uint32 pll_type, rate;
4513 + uint intr_val = 0;
4514 +
4515 + si = SB_INFO(sbh);
4516 + idx = si->curidx;
4517 + pll_type = PLL_TYPE1;
4518 +
4519 + INTR_OFF(si, intr_val);
4520 +
4521 + /* switch to extif or chipc core */
4522 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
4523 + n = R_REG(&eir->clockcontrol_n);
4524 + m = R_REG(&eir->clockcontrol_sb);
4525 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
4526 + pll_type = R_REG(&cc->capabilities) & CAP_PLL_MASK;
4527 + n = R_REG(&cc->clockcontrol_n);
4528 + if (pll_type == PLL_TYPE6)
4529 + m = R_REG(&cc->clockcontrol_mips);
4530 + else if (pll_type == PLL_TYPE3)
4531 + {
4532 + // Added by Chen-I for 5365
4533 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID)
4534 + m = R_REG(&cc->clockcontrol_sb);
4535 + else
4536 + m = R_REG(&cc->clockcontrol_m2);
4537 + }
4538 + else
4539 + m = R_REG(&cc->clockcontrol_sb);
4540 + } else {
4541 + INTR_RESTORE(si, intr_val);
4542 + return 0;
4543 + }
4544 +
4545 + // Added by Chen-I for 5365
4546 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID)
4547 + {
4548 + rate = 100000000;
4549 + }
4550 + else
4551 + {
4552 + /* calculate rate */
4553 + rate = sb_clock_rate(pll_type, n, m);
4554 + if (pll_type == PLL_TYPE3)
4555 + rate = rate / 2;
4556 + }
4557 +
4558 + /* switch back to previous core */
4559 + sb_setcoreidx(sbh, idx);
4560 +
4561 + INTR_RESTORE(si, intr_val);
4562 +
4563 + return rate;
4564 +}
4565 +
4566 +/* change logical "focus" to the gpio core for optimized access */
4567 +void*
4568 +sb_gpiosetcore(sb_t *sbh)
4569 +{
4570 + sb_info_t *si;
4571 +
4572 + si = SB_INFO(sbh);
4573 +
4574 + return (sb_setcoreidx(sbh, si->gpioidx));
4575 +}
4576 +
4577 +/* mask&set gpiocontrol bits */
4578 +uint32
4579 +sb_gpiocontrol(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
4580 +{
4581 + sb_info_t *si;
4582 + uint regoff;
4583 +
4584 + si = SB_INFO(sbh);
4585 + regoff = 0;
4586 +
4587 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
4588 +
4589 + /* gpios could be shared on router platforms */
4590 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
4591 + mask = priority ? (sb_gpioreservation & mask) :
4592 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
4593 + val &= mask;
4594 + }
4595 +
4596 + switch (si->gpioid) {
4597 + case SB_CC:
4598 + regoff = OFFSETOF(chipcregs_t, gpiocontrol);
4599 + break;
4600 +
4601 + case SB_PCI:
4602 + regoff = OFFSETOF(sbpciregs_t, gpiocontrol);
4603 + break;
4604 +
4605 + case SB_EXTIF:
4606 + return (0);
4607 + }
4608 +
4609 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
4610 +}
4611 +
4612 +/* mask&set gpio output enable bits */
4613 +uint32
4614 +sb_gpioouten(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
4615 +{
4616 + sb_info_t *si;
4617 + uint regoff;
4618 +
4619 + si = SB_INFO(sbh);
4620 + regoff = 0;
4621 +
4622 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
4623 +
4624 + /* gpios could be shared on router platforms */
4625 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
4626 + mask = priority ? (sb_gpioreservation & mask) :
4627 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
4628 + val &= mask;
4629 + }
4630 +
4631 + switch (si->gpioid) {
4632 + case SB_CC:
4633 + regoff = OFFSETOF(chipcregs_t, gpioouten);
4634 + break;
4635 +
4636 + case SB_PCI:
4637 + regoff = OFFSETOF(sbpciregs_t, gpioouten);
4638 + break;
4639 +
4640 + case SB_EXTIF:
4641 + regoff = OFFSETOF(extifregs_t, gpio[0].outen);
4642 + break;
4643 + }
4644 +
4645 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
4646 +}
4647 +
4648 +/* mask&set gpio output bits */
4649 +uint32
4650 +sb_gpioout(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
4651 +{
4652 + sb_info_t *si;
4653 + uint regoff;
4654 +
4655 + si = SB_INFO(sbh);
4656 + regoff = 0;
4657 +
4658 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
4659 +
4660 + /* gpios could be shared on router platforms */
4661 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
4662 + mask = priority ? (sb_gpioreservation & mask) :
4663 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
4664 + val &= mask;
4665 + }
4666 +
4667 + switch (si->gpioid) {
4668 + case SB_CC:
4669 + regoff = OFFSETOF(chipcregs_t, gpioout);
4670 + break;
4671 +
4672 + case SB_PCI:
4673 + regoff = OFFSETOF(sbpciregs_t, gpioout);
4674 + break;
4675 +
4676 + case SB_EXTIF:
4677 + regoff = OFFSETOF(extifregs_t, gpio[0].out);
4678 + break;
4679 + }
4680 +
4681 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
4682 +}
4683 +
4684 +/* reserve one gpio */
4685 +uint32
4686 +sb_gpioreserve(sb_t *sbh, uint32 gpio_bitmask, uint8 priority)
4687 +{
4688 + sb_info_t *si;
4689 +
4690 + si = SB_INFO(sbh);
4691 +
4692 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
4693 +
4694 + /* only cores on SB_BUS share GPIO's and only applcation users need to reserve/release GPIO */
4695 + if ( (BUSTYPE(si->sb.bustype) != SB_BUS) || (!priority)) {
4696 + ASSERT((BUSTYPE(si->sb.bustype) == SB_BUS) && (priority));
4697 + return -1;
4698 + }
4699 + /* make sure only one bit is set */
4700 + if ((!gpio_bitmask) || ((gpio_bitmask) & (gpio_bitmask - 1))) {
4701 + ASSERT((gpio_bitmask) && !((gpio_bitmask) & (gpio_bitmask - 1)));
4702 + return -1;
4703 + }
4704 +
4705 + /* already reserved */
4706 + if (sb_gpioreservation & gpio_bitmask)
4707 + return -1;
4708 + /* set reservation */
4709 + sb_gpioreservation |= gpio_bitmask;
4710 +
4711 + return sb_gpioreservation;
4712 +}
4713 +
4714 +/* release one gpio */
4715 +/*
4716 + * releasing the gpio doesn't change the current value on the GPIO last write value
4717 + * persists till some one overwrites it
4718 +*/
4719 +
4720 +uint32
4721 +sb_gpiorelease(sb_t *sbh, uint32 gpio_bitmask, uint8 priority)
4722 +{
4723 + sb_info_t *si;
4724 +
4725 + si = SB_INFO(sbh);
4726 +
4727 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
4728 +
4729 + /* only cores on SB_BUS share GPIO's and only applcation users need to reserve/release GPIO */
4730 + if ( (BUSTYPE(si->sb.bustype) != SB_BUS) || (!priority)) {
4731 + ASSERT((BUSTYPE(si->sb.bustype) == SB_BUS) && (priority));
4732 + return -1;
4733 + }
4734 + /* make sure only one bit is set */
4735 + if ((!gpio_bitmask) || ((gpio_bitmask) & (gpio_bitmask - 1))) {
4736 + ASSERT((gpio_bitmask) && !((gpio_bitmask) & (gpio_bitmask - 1)));
4737 + return -1;
4738 + }
4739 +
4740 + /* already released */
4741 + if (!(sb_gpioreservation & gpio_bitmask))
4742 + return -1;
4743 +
4744 + /* clear reservation */
4745 + sb_gpioreservation &= ~gpio_bitmask;
4746 +
4747 + return sb_gpioreservation;
4748 +}
4749 +
4750 +/* return the current gpioin register value */
4751 +uint32
4752 +sb_gpioin(sb_t *sbh)
4753 +{
4754 + sb_info_t *si;
4755 + uint regoff;
4756 +
4757 + si = SB_INFO(sbh);
4758 + regoff = 0;
4759 +
4760 + switch (si->gpioid) {
4761 + case SB_CC:
4762 + regoff = OFFSETOF(chipcregs_t, gpioin);
4763 + break;
4764 +
4765 + case SB_PCI:
4766 + regoff = OFFSETOF(sbpciregs_t, gpioin);
4767 + break;
4768 +
4769 + case SB_EXTIF:
4770 + regoff = OFFSETOF(extifregs_t, gpioin);
4771 + break;
4772 + }
4773 +
4774 + return (sb_corereg(si, si->gpioidx, regoff, 0, 0));
4775 +}
4776 +
4777 +/* mask&set gpio interrupt polarity bits */
4778 +uint32
4779 +sb_gpiointpolarity(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
4780 +{
4781 + sb_info_t *si;
4782 + uint regoff;
4783 +
4784 + si = SB_INFO(sbh);
4785 + regoff = 0;
4786 +
4787 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
4788 +
4789 + /* gpios could be shared on router platforms */
4790 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
4791 + mask = priority ? (sb_gpioreservation & mask) :
4792 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
4793 + val &= mask;
4794 + }
4795 +
4796 + switch (si->gpioid) {
4797 + case SB_CC:
4798 + regoff = OFFSETOF(chipcregs_t, gpiointpolarity);
4799 + break;
4800 +
4801 + case SB_PCI:
4802 + /* pci gpio implementation does not support interrupt polarity */
4803 + ASSERT(0);
4804 + break;
4805 +
4806 + case SB_EXTIF:
4807 + regoff = OFFSETOF(extifregs_t, gpiointpolarity);
4808 + break;
4809 + }
4810 +
4811 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
4812 +}
4813 +
4814 +/* mask&set gpio interrupt mask bits */
4815 +uint32
4816 +sb_gpiointmask(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
4817 +{
4818 + sb_info_t *si;
4819 + uint regoff;
4820 +
4821 + si = SB_INFO(sbh);
4822 + regoff = 0;
4823 +
4824 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
4825 +
4826 + /* gpios could be shared on router platforms */
4827 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
4828 + mask = priority ? (sb_gpioreservation & mask) :
4829 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
4830 + val &= mask;
4831 + }
4832 +
4833 + switch (si->gpioid) {
4834 + case SB_CC:
4835 + regoff = OFFSETOF(chipcregs_t, gpiointmask);
4836 + break;
4837 +
4838 + case SB_PCI:
4839 + /* pci gpio implementation does not support interrupt mask */
4840 + ASSERT(0);
4841 + break;
4842 +
4843 + case SB_EXTIF:
4844 + regoff = OFFSETOF(extifregs_t, gpiointmask);
4845 + break;
4846 + }
4847 +
4848 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
4849 +}
4850 +
4851 +/* assign the gpio to an led */
4852 +uint32
4853 +sb_gpioled(sb_t *sbh, uint32 mask, uint32 val)
4854 +{
4855 + sb_info_t *si;
4856 +
4857 + si = SB_INFO(sbh);
4858 + if (si->sb.ccrev < 16)
4859 + return -1;
4860 +
4861 + /* gpio led powersave reg */
4862 + return(sb_corereg(si, 0, OFFSETOF(chipcregs_t, gpiotimeroutmask), mask, val));
4863 +}
4864 +
4865 +/* mask&set gpio timer val */
4866 +uint32
4867 +sb_gpiotimerval(sb_t *sbh, uint32 mask, uint32 gpiotimerval)
4868 +{
4869 + sb_info_t *si;
4870 + si = SB_INFO(sbh);
4871 +
4872 + if (si->sb.ccrev < 16)
4873 + return -1;
4874 +
4875 + return(sb_corereg(si, 0, OFFSETOF(chipcregs_t, gpiotimerval), mask, gpiotimerval));
4876 +}
4877 +
4878 +
4879 +/* return the slow clock source - LPO, XTAL, or PCI */
4880 +static uint
4881 +sb_slowclk_src(sb_info_t *si)
4882 +{
4883 + chipcregs_t *cc;
4884 +
4885 +
4886 + ASSERT(sb_coreid(&si->sb) == SB_CC);
4887 +
4888 + if (si->sb.ccrev < 6) {
4889 + if ((BUSTYPE(si->sb.bustype) == PCI_BUS)
4890 + && (OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32)) & PCI_CFG_GPIO_SCS))
4891 + return (SCC_SS_PCI);
4892 + else
4893 + return (SCC_SS_XTAL);
4894 + } else if (si->sb.ccrev < 10) {
4895 + cc = (chipcregs_t*) sb_setcoreidx(&si->sb, si->curidx);
4896 + return (R_REG(&cc->slow_clk_ctl) & SCC_SS_MASK);
4897 + } else /* Insta-clock */
4898 + return (SCC_SS_XTAL);
4899 +}
4900 +
4901 +/* return the ILP (slowclock) min or max frequency */
4902 +static uint
4903 +sb_slowclk_freq(sb_info_t *si, bool max)
4904 +{
4905 + chipcregs_t *cc;
4906 + uint32 slowclk;
4907 + uint div;
4908 +
4909 +
4910 + ASSERT(sb_coreid(&si->sb) == SB_CC);
4911 +
4912 + cc = (chipcregs_t*) sb_setcoreidx(&si->sb, si->curidx);
4913 +
4914 + /* shouldn't be here unless we've established the chip has dynamic clk control */
4915 + ASSERT(R_REG(&cc->capabilities) & CAP_PWR_CTL);
4916 +
4917 + slowclk = sb_slowclk_src(si);
4918 + if (si->sb.ccrev < 6) {
4919 + if (slowclk == SCC_SS_PCI)
4920 + return (max? (PCIMAXFREQ/64) : (PCIMINFREQ/64));
4921 + else
4922 + return (max? (XTALMAXFREQ/32) : (XTALMINFREQ/32));
4923 + } else if (si->sb.ccrev < 10) {
4924 + div = 4 * (((R_REG(&cc->slow_clk_ctl) & SCC_CD_MASK) >> SCC_CD_SHIFT) + 1);
4925 + if (slowclk == SCC_SS_LPO)
4926 + return (max? LPOMAXFREQ : LPOMINFREQ);
4927 + else if (slowclk == SCC_SS_XTAL)
4928 + return (max? (XTALMAXFREQ/div) : (XTALMINFREQ/div));
4929 + else if (slowclk == SCC_SS_PCI)
4930 + return (max? (PCIMAXFREQ/div) : (PCIMINFREQ/div));
4931 + else
4932 + ASSERT(0);
4933 + } else {
4934 + /* Chipc rev 10 is InstaClock */
4935 + div = R_REG(&cc->system_clk_ctl) >> SYCC_CD_SHIFT;
4936 + div = 4 * (div + 1);
4937 + return (max ? XTALMAXFREQ : (XTALMINFREQ/div));
4938 + }
4939 + return (0);
4940 +}
4941 +
4942 +static void
4943 +sb_clkctl_setdelay(sb_info_t *si, void *chipcregs)
4944 +{
4945 + chipcregs_t * cc;
4946 + uint slowmaxfreq, pll_delay, slowclk;
4947 + uint pll_on_delay, fref_sel_delay;
4948 +
4949 + pll_delay = PLL_DELAY;
4950 +
4951 + /* If the slow clock is not sourced by the xtal then add the xtal_on_delay
4952 + * since the xtal will also be powered down by dynamic clk control logic.
4953 + */
4954 + slowclk = sb_slowclk_src(si);
4955 + if (slowclk != SCC_SS_XTAL)
4956 + pll_delay += XTAL_ON_DELAY;
4957 +
4958 + /* Starting with 4318 it is ILP that is used for the delays */
4959 + slowmaxfreq = sb_slowclk_freq(si, (si->sb.ccrev >= 10) ? FALSE : TRUE);
4960 +
4961 + pll_on_delay = ((slowmaxfreq * pll_delay) + 999999) / 1000000;
4962 + fref_sel_delay = ((slowmaxfreq * FREF_DELAY) + 999999) / 1000000;
4963 +
4964 + cc = (chipcregs_t *)chipcregs;
4965 + W_REG(&cc->pll_on_delay, pll_on_delay);
4966 + W_REG(&cc->fref_sel_delay, fref_sel_delay);
4967 +}
4968 +
4969 +int
4970 +sb_pwrctl_slowclk(void *sbh, bool set, uint *div)
4971 +{
4972 + sb_info_t *si;
4973 + uint origidx;
4974 + chipcregs_t *cc;
4975 + uint intr_val = 0;
4976 + uint err = 0;
4977 +
4978 + si = SB_INFO(sbh);
4979 +
4980 + /* chipcommon cores prior to rev6 don't support slowclkcontrol */
4981 + if (si->sb.ccrev < 6)
4982 + return 1;
4983 +
4984 + /* chipcommon cores rev10 are a whole new ball game */
4985 + if (si->sb.ccrev >= 10)
4986 + return 1;
4987 +
4988 + if (set && ((*div % 4) || (*div < 4)))
4989 + return 2;
4990 +
4991 + INTR_OFF(si, intr_val);
4992 + origidx = si->curidx;
4993 + cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0);
4994 + ASSERT(cc != NULL);
4995 +
4996 + if (!(R_REG(&cc->capabilities) & CAP_PWR_CTL)) {
4997 + err = 3;
4998 + goto done;
4999 + }
5000 +
5001 + if (set) {
5002 + SET_REG(&cc->slow_clk_ctl, SCC_CD_MASK, ((*div / 4 - 1) << SCC_CD_SHIFT));
5003 + sb_clkctl_setdelay(sbh, (void *)cc);
5004 + } else
5005 + *div = 4 * (((R_REG(&cc->slow_clk_ctl) & SCC_CD_MASK) >> SCC_CD_SHIFT) + 1);
5006 +
5007 +done:
5008 + sb_setcoreidx(sbh, origidx);
5009 + INTR_RESTORE(si, intr_val);
5010 + return err;
5011 +}
5012 +
5013 +/* initialize power control delay registers */
5014 +void sb_clkctl_init(sb_t *sbh)
5015 +{
5016 + sb_info_t *si;
5017 + uint origidx;
5018 + chipcregs_t *cc;
5019 +
5020 + si = SB_INFO(sbh);
5021 +
5022 + origidx = si->curidx;
5023 +
5024 + if ((cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0)) == NULL)
5025 + return;
5026 +
5027 + if (!(R_REG(&cc->capabilities) & CAP_PWR_CTL))
5028 + goto done;
5029 +
5030 + /* set all Instaclk chip ILP to 1 MHz */
5031 + if (si->sb.ccrev >= 10)
5032 + SET_REG(&cc->system_clk_ctl, SYCC_CD_MASK, (ILP_DIV_1MHZ << SYCC_CD_SHIFT));
5033 +
5034 + sb_clkctl_setdelay(si, (void *)cc);
5035 +
5036 +done:
5037 + sb_setcoreidx(sbh, origidx);
5038 +}
5039 +void sb_pwrctl_init(sb_t *sbh)
5040 +{
5041 +sb_clkctl_init(sbh);
5042 +}
5043 +/* return the value suitable for writing to the dot11 core FAST_PWRUP_DELAY register */
5044 +uint16
5045 +sb_clkctl_fast_pwrup_delay(sb_t *sbh)
5046 +{
5047 + sb_info_t *si;
5048 + uint origidx;
5049 + chipcregs_t *cc;
5050 + uint slowminfreq;
5051 + uint16 fpdelay;
5052 + uint intr_val = 0;
5053 +
5054 + si = SB_INFO(sbh);
5055 + fpdelay = 0;
5056 + origidx = si->curidx;
5057 +
5058 + INTR_OFF(si, intr_val);
5059 +
5060 + if ((cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0)) == NULL)
5061 + goto done;
5062 +
5063 + if (!(R_REG(&cc->capabilities) & CAP_PWR_CTL))
5064 + goto done;
5065 +
5066 + slowminfreq = sb_slowclk_freq(si, FALSE);
5067 + fpdelay = (((R_REG(&cc->pll_on_delay) + 2) * 1000000) + (slowminfreq - 1)) / slowminfreq;
5068 +
5069 +done:
5070 + sb_setcoreidx(sbh, origidx);
5071 + INTR_RESTORE(si, intr_val);
5072 + return (fpdelay);
5073 +}
5074 +uint16 sb_pwrctl_fast_pwrup_delay(sb_t *sbh)
5075 +{
5076 +return sb_clkctl_fast_pwrup_delay(sbh);
5077 +}
5078 +/* turn primary xtal and/or pll off/on */
5079 +int
5080 +sb_clkctl_xtal(sb_t *sbh, uint what, bool on)
5081 +{
5082 + sb_info_t *si;
5083 + uint32 in, out, outen;
5084 +
5085 + si = SB_INFO(sbh);
5086 +
5087 + switch (BUSTYPE(si->sb.bustype)) {
5088 + case PCI_BUS:
5089 +
5090 + in = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_IN, sizeof (uint32));
5091 + out = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32));
5092 + outen = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUTEN, sizeof (uint32));
5093 +
5094 + /*
5095 + * Avoid glitching the clock if GPRS is already using it.
5096 + * We can't actually read the state of the PLLPD so we infer it
5097 + * by the value of XTAL_PU which *is* readable via gpioin.
5098 + */
5099 + if (on && (in & PCI_CFG_GPIO_XTAL))
5100 + return (0);
5101 +
5102 + if (what & XTAL)
5103 + outen |= PCI_CFG_GPIO_XTAL;
5104 + if (what & PLL)
5105 + outen |= PCI_CFG_GPIO_PLL;
5106 +
5107 + if (on) {
5108 + /* turn primary xtal on */
5109 + if (what & XTAL) {
5110 + out |= PCI_CFG_GPIO_XTAL;
5111 + if (what & PLL)
5112 + out |= PCI_CFG_GPIO_PLL;
5113 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32), out);
5114 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUTEN, sizeof (uint32), outen);
5115 + OSL_DELAY(XTAL_ON_DELAY);
5116 + }
5117 +
5118 + /* turn pll on */
5119 + if (what & PLL) {
5120 + out &= ~PCI_CFG_GPIO_PLL;
5121 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32), out);
5122 + OSL_DELAY(2000);
5123 + }
5124 + } else {
5125 + if (what & XTAL)
5126 + out &= ~PCI_CFG_GPIO_XTAL;
5127 + if (what & PLL)
5128 + out |= PCI_CFG_GPIO_PLL;
5129 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32), out);
5130 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUTEN, sizeof (uint32), outen);
5131 + }
5132 +
5133 + default:
5134 + return (-1);
5135 + }
5136 +
5137 + return (0);
5138 +}
5139 +
5140 +int sb_pwrctl_xtal(sb_t *sbh, uint what, bool on)
5141 +{
5142 +return sb_clkctl_xtal(sbh,what,on);
5143 +}
5144 +
5145 +/* set dynamic clk control mode (forceslow, forcefast, dynamic) */
5146 +/* returns true if ignore pll off is set and false if it is not */
5147 +bool
5148 +sb_clkctl_clk(sb_t *sbh, uint mode)
5149 +{
5150 + sb_info_t *si;
5151 + uint origidx;
5152 + chipcregs_t *cc;
5153 + uint32 scc;
5154 + bool forcefastclk=FALSE;
5155 + uint intr_val = 0;
5156 +
5157 + si = SB_INFO(sbh);
5158 +
5159 + /* chipcommon cores prior to rev6 don't support dynamic clock control */
5160 + if (si->sb.ccrev < 6)
5161 + return (FALSE);
5162 +
5163 + /* chipcommon cores rev10 are a whole new ball game */
5164 + if (si->sb.ccrev >= 10)
5165 + return (FALSE);
5166 +
5167 + INTR_OFF(si, intr_val);
5168 +
5169 + origidx = si->curidx;
5170 +
5171 + cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0);
5172 + ASSERT(cc != NULL);
5173 +
5174 + if (!(R_REG(&cc->capabilities) & CAP_PWR_CTL))
5175 + goto done;
5176 +
5177 + switch (mode) {
5178 + case CLK_FAST: /* force fast (pll) clock */
5179 + /* don't forget to force xtal back on before we clear SCC_DYN_XTAL.. */
5180 + sb_clkctl_xtal(&si->sb, XTAL, ON);
5181 +
5182 + SET_REG(&cc->slow_clk_ctl, (SCC_XC | SCC_FS | SCC_IP), SCC_IP);
5183 + break;
5184 +
5185 + case CLK_DYNAMIC: /* enable dynamic clock control */
5186 + scc = R_REG(&cc->slow_clk_ctl);
5187 + scc &= ~(SCC_FS | SCC_IP | SCC_XC);
5188 + if ((scc & SCC_SS_MASK) != SCC_SS_XTAL)
5189 + scc |= SCC_XC;
5190 + W_REG(&cc->slow_clk_ctl, scc);
5191 +
5192 + /* for dynamic control, we have to release our xtal_pu "force on" */
5193 + if (scc & SCC_XC)
5194 + sb_clkctl_xtal(&si->sb, XTAL, OFF);
5195 + break;
5196 +
5197 + default:
5198 + ASSERT(0);
5199 + }
5200 +
5201 + /* Is the h/w forcing the use of the fast clk */
5202 + forcefastclk = (bool)((R_REG(&cc->slow_clk_ctl) & SCC_IP) == SCC_IP);
5203 +
5204 +done:
5205 + sb_setcoreidx(sbh, origidx);
5206 + INTR_RESTORE(si, intr_val);
5207 + return (forcefastclk);
5208 +}
5209 +
5210 +bool sb_pwrctl_clk(sb_t *sbh, uint mode)
5211 +{
5212 +return sb_clkctl_clk(sbh, mode);
5213 +}
5214 +/* register driver interrupt disabling and restoring callback functions */
5215 +void
5216 +sb_register_intr_callback(sb_t *sbh, void *intrsoff_fn, void *intrsrestore_fn, void *intrsenabled_fn, void *intr_arg)
5217 +{
5218 + sb_info_t *si;
5219 +
5220 + si = SB_INFO(sbh);
5221 + si->intr_arg = intr_arg;
5222 + si->intrsoff_fn = (sb_intrsoff_t)intrsoff_fn;
5223 + si->intrsrestore_fn = (sb_intrsrestore_t)intrsrestore_fn;
5224 + si->intrsenabled_fn = (sb_intrsenabled_t)intrsenabled_fn;
5225 + /* save current core id. when this function called, the current core
5226 + * must be the core which provides driver functions(il, et, wl, etc.)
5227 + */
5228 + si->dev_coreid = si->coreid[si->curidx];
5229 +}
5230 +
5231 +
5232 +void
5233 +sb_corepciid(sb_t *sbh, uint16 *pcivendor, uint16 *pcidevice,
5234 + uint8 *pciclass, uint8 *pcisubclass, uint8 *pciprogif)
5235 +{
5236 + uint vendor, core, unit;
5237 + uint chip, chippkg;
5238 + char varname[8];
5239 + uint8 class, subclass, progif;
5240 +
5241 + vendor = sb_corevendor(sbh);
5242 + core = sb_coreid(sbh);
5243 + unit = sb_coreunit(sbh);
5244 +
5245 + chip = BCMINIT(sb_chip)(sbh);
5246 + chippkg = BCMINIT(sb_chippkg)(sbh);
5247 +
5248 + progif = 0;
5249 +
5250 + /* Known vendor translations */
5251 + switch (vendor) {
5252 + case SB_VEND_BCM:
5253 + vendor = VENDOR_BROADCOM;
5254 + break;
5255 + }
5256 +
5257 + /* Determine class based on known core codes */
5258 + switch (core) {
5259 + case SB_ILINE20:
5260 + class = PCI_CLASS_NET;
5261 + subclass = PCI_NET_ETHER;
5262 + core = BCM47XX_ILINE_ID;
5263 + break;
5264 + case SB_ENET:
5265 + class = PCI_CLASS_NET;
5266 + subclass = PCI_NET_ETHER;
5267 + core = BCM47XX_ENET_ID;
5268 + break;
5269 + case SB_SDRAM:
5270 + case SB_MEMC:
5271 + class = PCI_CLASS_MEMORY;
5272 + subclass = PCI_MEMORY_RAM;
5273 + break;
5274 + case SB_PCI:
5275 + class = PCI_CLASS_BRIDGE;
5276 + subclass = PCI_BRIDGE_PCI;
5277 + break;
5278 + case SB_MIPS:
5279 + case SB_MIPS33:
5280 + class = PCI_CLASS_CPU;
5281 + subclass = PCI_CPU_MIPS;
5282 + break;
5283 + case SB_CODEC:
5284 + class = PCI_CLASS_COMM;
5285 + subclass = PCI_COMM_MODEM;
5286 + core = BCM47XX_V90_ID;
5287 + break;
5288 + case SB_USB:
5289 + class = PCI_CLASS_SERIAL;
5290 + subclass = PCI_SERIAL_USB;
5291 + progif = 0x10; /* OHCI */
5292 + core = BCM47XX_USB_ID;
5293 + break;
5294 + case SB_USB11H:
5295 + class = PCI_CLASS_SERIAL;
5296 + subclass = PCI_SERIAL_USB;
5297 + progif = 0x10; /* OHCI */
5298 + core = BCM47XX_USBH_ID;
5299 + break;
5300 + case SB_USB11D:
5301 + class = PCI_CLASS_SERIAL;
5302 + subclass = PCI_SERIAL_USB;
5303 + core = BCM47XX_USBD_ID;
5304 + break;
5305 + case SB_IPSEC:
5306 + class = PCI_CLASS_CRYPT;
5307 + subclass = PCI_CRYPT_NETWORK;
5308 + core = BCM47XX_IPSEC_ID;
5309 + break;
5310 + case SB_ROBO:
5311 + class = PCI_CLASS_NET;
5312 + subclass = PCI_NET_OTHER;
5313 + core = BCM47XX_ROBO_ID;
5314 + break;
5315 + case SB_EXTIF:
5316 + case SB_CC:
5317 + class = PCI_CLASS_MEMORY;
5318 + subclass = PCI_MEMORY_FLASH;
5319 + break;
5320 + case SB_D11:
5321 + class = PCI_CLASS_NET;
5322 + subclass = PCI_NET_OTHER;
5323 + /* Let an nvram variable override this */
5324 + sprintf(varname, "wl%did", unit);
5325 + if ((core = getintvar(NULL, varname)) == 0) {
5326 + if (chip == BCM4712_DEVICE_ID) {
5327 + if (chippkg == BCM4712SMALL_PKG_ID)
5328 + core = BCM4306_D11G_ID;
5329 + else
5330 + core = BCM4306_D11DUAL_ID;
5331 + }
5332 + }
5333 + break;
5334 +
5335 + default:
5336 + class = subclass = progif = 0xff;
5337 + break;
5338 + }
5339 +
5340 + *pcivendor = (uint16)vendor;
5341 + *pcidevice = (uint16)core;
5342 + *pciclass = class;
5343 + *pcisubclass = subclass;
5344 + *pciprogif = progif;
5345 +}
5346 +
5347 +/* Fix chip's configuration. The current core may be changed upon return */
5348 +static int
5349 +sb_pci_fixcfg(sb_info_t *si)
5350 +{
5351 + uint origidx, pciidx;
5352 + sbpciregs_t *pciregs;
5353 + uint16 val16, *reg16;
5354 +
5355 + ASSERT(BUSTYPE(si->sb.bustype) == PCI_BUS);
5356 +
5357 + /* Fix PCI(e) SROM shadow area */
5358 + /* save the current index */
5359 + origidx = sb_coreidx(&si->sb);
5360 +
5361 + if (si->sb.buscoretype == SB_PCI) {
5362 + pciregs = (sbpciregs_t *)sb_setcore(&si->sb, SB_PCI, 0);
5363 + ASSERT(pciregs);
5364 + reg16 = &pciregs->sprom[SRSH_PI_OFFSET];
5365 + }
5366 + else {
5367 + ASSERT(0);
5368 + return -1;
5369 + }
5370 + pciidx = sb_coreidx(&si->sb);
5371 + val16 = R_REG(reg16);
5372 + if (((val16 & SRSH_PI_MASK) >> SRSH_PI_SHIFT) != (uint16)pciidx) {
5373 + val16 = (uint16)(pciidx << SRSH_PI_SHIFT) | (val16 & ~SRSH_PI_MASK);
5374 + W_REG(reg16, val16);
5375 + }
5376 +
5377 + /* restore the original index */
5378 + sb_setcoreidx(&si->sb, origidx);
5379 +
5380 + return 0;
5381 +}
5382 +
5383 +EXPORT_SYMBOL(sb_boardtype);
5384 +EXPORT_SYMBOL(sb_boardvendor);
5385 +EXPORT_SYMBOL(sb_gpiocontrol);
5386 +EXPORT_SYMBOL(sb_gpioin);
5387 +EXPORT_SYMBOL(sb_gpiointmask);
5388 +EXPORT_SYMBOL(sb_gpiointpolarity);
5389 +EXPORT_SYMBOL(sb_gpioled);
5390 +EXPORT_SYMBOL(sb_gpioout);
5391 +EXPORT_SYMBOL(sb_gpioouten);
5392 +EXPORT_SYMBOL(sb_gpiorelease);
5393 +EXPORT_SYMBOL(sb_gpioreserve);
5394 +EXPORT_SYMBOL(sb_gpiosetcore);
5395 +EXPORT_SYMBOL(sb_gpiotimerval);
5396 +EXPORT_SYMBOL(sb_watchdog);
5397 diff -urN linux.old/arch/mips/bcm947xx/broadcom/sflash.c linux.dev/arch/mips/bcm947xx/broadcom/sflash.c
5398 --- linux.old/arch/mips/bcm947xx/broadcom/sflash.c 1970-01-01 01:00:00.000000000 +0100
5399 +++ linux.dev/arch/mips/bcm947xx/broadcom/sflash.c 2005-12-28 16:37:32.870261000 +0100
5400 @@ -0,0 +1,418 @@
5401 +/*
5402 + * Broadcom SiliconBackplane chipcommon serial flash interface
5403 + *
5404 + * Copyright 2005, Broadcom Corporation
5405 + * All Rights Reserved.
5406 + *
5407 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
5408 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
5409 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
5410 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
5411 + *
5412 + * $Id$
5413 + */
5414 +
5415 +#include <osl.h>
5416 +#include <typedefs.h>
5417 +#include <sbconfig.h>
5418 +#include <sbchipc.h>
5419 +#include <mipsinc.h>
5420 +#include <bcmutils.h>
5421 +#include <bcmdevs.h>
5422 +#include <sflash.h>
5423 +
5424 +/* Private global state */
5425 +static struct sflash sflash;
5426 +
5427 +/* Issue a serial flash command */
5428 +static INLINE void
5429 +sflash_cmd(chipcregs_t *cc, uint opcode)
5430 +{
5431 + W_REG(&cc->flashcontrol, SFLASH_START | opcode);
5432 + while (R_REG(&cc->flashcontrol) & SFLASH_BUSY);
5433 +}
5434 +
5435 +/* Initialize serial flash access */
5436 +struct sflash *
5437 +sflash_init(chipcregs_t *cc)
5438 +{
5439 + uint32 id, id2;
5440 +
5441 + bzero(&sflash, sizeof(sflash));
5442 +
5443 + sflash.type = R_REG(&cc->capabilities) & CAP_FLASH_MASK;
5444 +
5445 + switch (sflash.type) {
5446 + case SFLASH_ST:
5447 + /* Probe for ST chips */
5448 + sflash_cmd(cc, SFLASH_ST_DP);
5449 + sflash_cmd(cc, SFLASH_ST_RES);
5450 + id = R_REG(&cc->flashdata);
5451 + switch (id) {
5452 + case 0x11:
5453 + /* ST M25P20 2 Mbit Serial Flash */
5454 + sflash.blocksize = 64 * 1024;
5455 + sflash.numblocks = 4;
5456 + break;
5457 + case 0x12:
5458 + /* ST M25P40 4 Mbit Serial Flash */
5459 + sflash.blocksize = 64 * 1024;
5460 + sflash.numblocks = 8;
5461 + break;
5462 + case 0x13:
5463 + /* ST M25P80 8 Mbit Serial Flash */
5464 + sflash.blocksize = 64 * 1024;
5465 + sflash.numblocks = 16;
5466 + break;
5467 + case 0x14:
5468 + /* ST M25P16 16 Mbit Serial Flash */
5469 + sflash.blocksize = 64 * 1024;
5470 + sflash.numblocks = 32;
5471 + break;
5472 + case 0x15:
5473 + /* ST M25P32 32 Mbit Serial Flash */
5474 + sflash.blocksize = 64 * 1024;
5475 + sflash.numblocks = 64;
5476 + break;
5477 + case 0xbf:
5478 + W_REG(&cc->flashaddress, 1);
5479 + sflash_cmd(cc, SFLASH_ST_RES);
5480 + id2 = R_REG(&cc->flashdata);
5481 + if (id2 == 0x44) {
5482 + /* SST M25VF80 4 Mbit Serial Flash */
5483 + sflash.blocksize = 64 * 1024;
5484 + sflash.numblocks = 8;
5485 + }
5486 + break;
5487 + }
5488 + break;
5489 +
5490 + case SFLASH_AT:
5491 + /* Probe for Atmel chips */
5492 + sflash_cmd(cc, SFLASH_AT_STATUS);
5493 + id = R_REG(&cc->flashdata) & 0x3c;
5494 + switch (id) {
5495 + case 0xc:
5496 + /* Atmel AT45DB011 1Mbit Serial Flash */
5497 + sflash.blocksize = 256;
5498 + sflash.numblocks = 512;
5499 + break;
5500 + case 0x14:
5501 + /* Atmel AT45DB021 2Mbit Serial Flash */
5502 + sflash.blocksize = 256;
5503 + sflash.numblocks = 1024;
5504 + break;
5505 + case 0x1c:
5506 + /* Atmel AT45DB041 4Mbit Serial Flash */
5507 + sflash.blocksize = 256;
5508 + sflash.numblocks = 2048;
5509 + break;
5510 + case 0x24:
5511 + /* Atmel AT45DB081 8Mbit Serial Flash */
5512 + sflash.blocksize = 256;
5513 + sflash.numblocks = 4096;
5514 + break;
5515 + case 0x2c:
5516 + /* Atmel AT45DB161 16Mbit Serial Flash */
5517 + sflash.blocksize = 512;
5518 + sflash.numblocks = 4096;
5519 + break;
5520 + case 0x34:
5521 + /* Atmel AT45DB321 32Mbit Serial Flash */
5522 + sflash.blocksize = 512;
5523 + sflash.numblocks = 8192;
5524 + break;
5525 + case 0x3c:
5526 + /* Atmel AT45DB642 64Mbit Serial Flash */
5527 + sflash.blocksize = 1024;
5528 + sflash.numblocks = 8192;
5529 + break;
5530 + }
5531 + break;
5532 + }
5533 +
5534 + sflash.size = sflash.blocksize * sflash.numblocks;
5535 + return sflash.size ? &sflash : NULL;
5536 +}
5537 +
5538 +/* Read len bytes starting at offset into buf. Returns number of bytes read. */
5539 +int
5540 +sflash_read(chipcregs_t *cc, uint offset, uint len, uchar *buf)
5541 +{
5542 + int cnt;
5543 + uint32 *from, *to;
5544 +
5545 + if (!len)
5546 + return 0;
5547 +
5548 + if ((offset + len) > sflash.size)
5549 + return -22;
5550 +
5551 + if ((len >= 4) && (offset & 3))
5552 + cnt = 4 - (offset & 3);
5553 + else if ((len >= 4) && ((uint32)buf & 3))
5554 + cnt = 4 - ((uint32)buf & 3);
5555 + else
5556 + cnt = len;
5557 +
5558 + from = (uint32 *)KSEG1ADDR(SB_FLASH2 + offset);
5559 + to = (uint32 *)buf;
5560 +
5561 + if (cnt < 4) {
5562 + bcopy(from, to, cnt);
5563 + return cnt;
5564 + }
5565 +
5566 + while (cnt >= 4) {
5567 + *to++ = *from++;
5568 + cnt -= 4;
5569 + }
5570 +
5571 + return (len - cnt);
5572 +}
5573 +
5574 +/* Poll for command completion. Returns zero when complete. */
5575 +int
5576 +sflash_poll(chipcregs_t *cc, uint offset)
5577 +{
5578 + if (offset >= sflash.size)
5579 + return -22;
5580 +
5581 + switch (sflash.type) {
5582 + case SFLASH_ST:
5583 + /* Check for ST Write In Progress bit */
5584 + sflash_cmd(cc, SFLASH_ST_RDSR);
5585 + return R_REG(&cc->flashdata) & SFLASH_ST_WIP;
5586 + case SFLASH_AT:
5587 + /* Check for Atmel Ready bit */
5588 + sflash_cmd(cc, SFLASH_AT_STATUS);
5589 + return !(R_REG(&cc->flashdata) & SFLASH_AT_READY);
5590 + }
5591 +
5592 + return 0;
5593 +}
5594 +
5595 +/* Write len bytes starting at offset into buf. Returns number of bytes
5596 + * written. Caller should poll for completion.
5597 + */
5598 +int
5599 +sflash_write(chipcregs_t *cc, uint offset, uint len, const uchar *buf)
5600 +{
5601 + struct sflash *sfl;
5602 + int ret = 0;
5603 + bool is4712b0;
5604 + uint32 page, byte, mask;
5605 +
5606 + if (!len)
5607 + return 0;
5608 +
5609 + if ((offset + len) > sflash.size)
5610 + return -22;
5611 +
5612 + sfl = &sflash;
5613 + switch (sfl->type) {
5614 + case SFLASH_ST:
5615 + mask = R_REG(&cc->chipid);
5616 + is4712b0 = (((mask & CID_ID_MASK) == BCM4712_DEVICE_ID) &&
5617 + ((mask & CID_REV_MASK) == (3 << CID_REV_SHIFT)));
5618 + /* Enable writes */
5619 + sflash_cmd(cc, SFLASH_ST_WREN);
5620 + if (is4712b0) {
5621 + mask = 1 << 14;
5622 + W_REG(&cc->flashaddress, offset);
5623 + W_REG(&cc->flashdata, *buf++);
5624 + /* Set chip select */
5625 + OR_REG(&cc->gpioout, mask);
5626 + /* Issue a page program with the first byte */
5627 + sflash_cmd(cc, SFLASH_ST_PP);
5628 + ret = 1;
5629 + offset++;
5630 + len--;
5631 + while (len > 0) {
5632 + if ((offset & 255) == 0) {
5633 + /* Page boundary, drop cs and return */
5634 + AND_REG(&cc->gpioout, ~mask);
5635 + if (!sflash_poll(cc, offset)) {
5636 + /* Flash rejected command */
5637 + return -11;
5638 + }
5639 + return ret;
5640 + } else {
5641 + /* Write single byte */
5642 + sflash_cmd(cc, *buf++);
5643 + }
5644 + ret++;
5645 + offset++;
5646 + len--;
5647 + }
5648 + /* All done, drop cs if needed */
5649 + if ((offset & 255) != 1) {
5650 + /* Drop cs */
5651 + AND_REG(&cc->gpioout, ~mask);
5652 + if (!sflash_poll(cc, offset)) {
5653 + /* Flash rejected command */
5654 + return -12;
5655 + }
5656 + }
5657 + } else {
5658 + ret = 1;
5659 + W_REG(&cc->flashaddress, offset);
5660 + W_REG(&cc->flashdata, *buf);
5661 + /* Page program */
5662 + sflash_cmd(cc, SFLASH_ST_PP);
5663 + }
5664 + break;
5665 + case SFLASH_AT:
5666 + mask = sfl->blocksize - 1;
5667 + page = (offset & ~mask) << 1;
5668 + byte = offset & mask;
5669 + /* Read main memory page into buffer 1 */
5670 + if (byte || len < sfl->blocksize) {
5671 + W_REG(&cc->flashaddress, page);
5672 + sflash_cmd(cc, SFLASH_AT_BUF1_LOAD);
5673 + /* 250 us for AT45DB321B */
5674 + SPINWAIT(sflash_poll(cc, offset), 1000);
5675 + ASSERT(!sflash_poll(cc, offset));
5676 + }
5677 + /* Write into buffer 1 */
5678 + for (ret = 0; ret < len && byte < sfl->blocksize; ret++) {
5679 + W_REG(&cc->flashaddress, byte++);
5680 + W_REG(&cc->flashdata, *buf++);
5681 + sflash_cmd(cc, SFLASH_AT_BUF1_WRITE);
5682 + }
5683 + /* Write buffer 1 into main memory page */
5684 + W_REG(&cc->flashaddress, page);
5685 + sflash_cmd(cc, SFLASH_AT_BUF1_PROGRAM);
5686 + break;
5687 + }
5688 +
5689 + return ret;
5690 +}
5691 +
5692 +/* Erase a region. Returns number of bytes scheduled for erasure.
5693 + * Caller should poll for completion.
5694 + */
5695 +int
5696 +sflash_erase(chipcregs_t *cc, uint offset)
5697 +{
5698 + struct sflash *sfl;
5699 +
5700 + if (offset >= sflash.size)
5701 + return -22;
5702 +
5703 + sfl = &sflash;
5704 + switch (sfl->type) {
5705 + case SFLASH_ST:
5706 + sflash_cmd(cc, SFLASH_ST_WREN);
5707 + W_REG(&cc->flashaddress, offset);
5708 + sflash_cmd(cc, SFLASH_ST_SE);
5709 + return sfl->blocksize;
5710 + case SFLASH_AT:
5711 + W_REG(&cc->flashaddress, offset << 1);
5712 + sflash_cmd(cc, SFLASH_AT_PAGE_ERASE);
5713 + return sfl->blocksize;
5714 + }
5715 +
5716 + return 0;
5717 +}
5718 +
5719 +/*
5720 + * writes the appropriate range of flash, a NULL buf simply erases
5721 + * the region of flash
5722 + */
5723 +int
5724 +sflash_commit(chipcregs_t *cc, uint offset, uint len, const uchar *buf)
5725 +{
5726 + struct sflash *sfl;
5727 + uchar *block = NULL, *cur_ptr, *blk_ptr;
5728 + uint blocksize = 0, mask, cur_offset, cur_length, cur_retlen, remainder;
5729 + uint blk_offset, blk_len, copied;
5730 + int bytes, ret = 0;
5731 +
5732 + /* Check address range */
5733 + if (len <= 0)
5734 + return 0;
5735 +
5736 + sfl = &sflash;
5737 + if ((offset + len) > sfl->size)
5738 + return -1;
5739 +
5740 + blocksize = sfl->blocksize;
5741 + mask = blocksize - 1;
5742 +
5743 + /* Allocate a block of mem */
5744 + if (!(block = MALLOC(NULL, blocksize)))
5745 + return -1;
5746 +
5747 + while (len) {
5748 + /* Align offset */
5749 + cur_offset = offset & ~mask;
5750 + cur_length = blocksize;
5751 + cur_ptr = block;
5752 +
5753 + remainder = blocksize - (offset & mask);
5754 + if (len < remainder)
5755 + cur_retlen = len;
5756 + else
5757 + cur_retlen = remainder;
5758 +
5759 + /* buf == NULL means erase only */
5760 + if (buf) {
5761 + /* Copy existing data into holding block if necessary */
5762 + if ((offset & mask) || (len < blocksize)) {
5763 + blk_offset = cur_offset;
5764 + blk_len = cur_length;
5765 + blk_ptr = cur_ptr;
5766 +
5767 + /* Copy entire block */
5768 + while(blk_len) {
5769 + copied = sflash_read(cc, blk_offset, blk_len, blk_ptr);
5770 + blk_offset += copied;
5771 + blk_len -= copied;
5772 + blk_ptr += copied;
5773 + }
5774 + }
5775 +
5776 + /* Copy input data into holding block */
5777 + memcpy(cur_ptr + (offset & mask), buf, cur_retlen);
5778 + }
5779 +
5780 + /* Erase block */
5781 + if ((ret = sflash_erase(cc, (uint) cur_offset)) < 0)
5782 + goto done;
5783 + while (sflash_poll(cc, (uint) cur_offset));
5784 +
5785 + /* buf == NULL means erase only */
5786 + if (!buf) {
5787 + offset += cur_retlen;
5788 + len -= cur_retlen;
5789 + continue;
5790 + }
5791 +
5792 + /* Write holding block */
5793 + while (cur_length > 0) {
5794 + if ((bytes = sflash_write(cc,
5795 + (uint) cur_offset,
5796 + (uint) cur_length,
5797 + (uchar *) cur_ptr)) < 0) {
5798 + ret = bytes;
5799 + goto done;
5800 + }
5801 + while (sflash_poll(cc, (uint) cur_offset));
5802 + cur_offset += bytes;
5803 + cur_length -= bytes;
5804 + cur_ptr += bytes;
5805 + }
5806 +
5807 + offset += cur_retlen;
5808 + len -= cur_retlen;
5809 + buf += cur_retlen;
5810 + }
5811 +
5812 + ret = len;
5813 +done:
5814 + if (block)
5815 + MFREE(NULL, block, blocksize);
5816 + return ret;
5817 +}
5818 +
5819 diff -urN linux.old/arch/mips/bcm947xx/include/bcmdevs.h linux.dev/arch/mips/bcm947xx/include/bcmdevs.h
5820 --- linux.old/arch/mips/bcm947xx/include/bcmdevs.h 1970-01-01 01:00:00.000000000 +0100
5821 +++ linux.dev/arch/mips/bcm947xx/include/bcmdevs.h 2005-12-28 16:37:32.874261250 +0100
5822 @@ -0,0 +1,391 @@
5823 +/*
5824 + * Broadcom device-specific manifest constants.
5825 + *
5826 + * Copyright 2005, Broadcom Corporation
5827 + * All Rights Reserved.
5828 + *
5829 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
5830 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
5831 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
5832 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
5833 + * $Id$
5834 + */
5835 +
5836 +#ifndef _BCMDEVS_H
5837 +#define _BCMDEVS_H
5838 +
5839 +
5840 +/* Known PCI vendor Id's */
5841 +#define VENDOR_EPIGRAM 0xfeda
5842 +#define VENDOR_BROADCOM 0x14e4
5843 +#define VENDOR_3COM 0x10b7
5844 +#define VENDOR_NETGEAR 0x1385
5845 +#define VENDOR_DIAMOND 0x1092
5846 +#define VENDOR_DELL 0x1028
5847 +#define VENDOR_HP 0x0e11
5848 +#define VENDOR_APPLE 0x106b
5849 +
5850 +/* PCI Device Id's */
5851 +#define BCM4210_DEVICE_ID 0x1072 /* never used */
5852 +#define BCM4211_DEVICE_ID 0x4211
5853 +#define BCM4230_DEVICE_ID 0x1086 /* never used */
5854 +#define BCM4231_DEVICE_ID 0x4231
5855 +
5856 +#define BCM4410_DEVICE_ID 0x4410 /* bcm44xx family pci iline */
5857 +#define BCM4430_DEVICE_ID 0x4430 /* bcm44xx family cardbus iline */
5858 +#define BCM4412_DEVICE_ID 0x4412 /* bcm44xx family pci enet */
5859 +#define BCM4432_DEVICE_ID 0x4432 /* bcm44xx family cardbus enet */
5860 +
5861 +#define BCM3352_DEVICE_ID 0x3352 /* bcm3352 device id */
5862 +#define BCM3360_DEVICE_ID 0x3360 /* bcm3360 device id */
5863 +
5864 +#define EPI41210_DEVICE_ID 0xa0fa /* bcm4210 */
5865 +#define EPI41230_DEVICE_ID 0xa10e /* bcm4230 */
5866 +
5867 +#define BCM47XX_ILINE_ID 0x4711 /* 47xx iline20 */
5868 +#define BCM47XX_V90_ID 0x4712 /* 47xx v90 codec */
5869 +#define BCM47XX_ENET_ID 0x4713 /* 47xx enet */
5870 +#define BCM47XX_EXT_ID 0x4714 /* 47xx external i/f */
5871 +#define BCM47XX_USB_ID 0x4715 /* 47xx usb */
5872 +#define BCM47XX_USBH_ID 0x4716 /* 47xx usb host */
5873 +#define BCM47XX_USBD_ID 0x4717 /* 47xx usb device */
5874 +#define BCM47XX_IPSEC_ID 0x4718 /* 47xx ipsec */
5875 +#define BCM47XX_ROBO_ID 0x4719 /* 47xx/53xx roboswitch core */
5876 +#define BCM47XX_USB20H_ID 0x471a /* 47xx usb 2.0 host */
5877 +#define BCM47XX_USB20D_ID 0x471b /* 47xx usb 2.0 device */
5878 +
5879 +#define BCM4710_DEVICE_ID 0x4710 /* 4710 primary function 0 */
5880 +
5881 +#define BCM4610_DEVICE_ID 0x4610 /* 4610 primary function 0 */
5882 +#define BCM4610_ILINE_ID 0x4611 /* 4610 iline100 */
5883 +#define BCM4610_V90_ID 0x4612 /* 4610 v90 codec */
5884 +#define BCM4610_ENET_ID 0x4613 /* 4610 enet */
5885 +#define BCM4610_EXT_ID 0x4614 /* 4610 external i/f */
5886 +#define BCM4610_USB_ID 0x4615 /* 4610 usb */
5887 +
5888 +#define BCM4402_DEVICE_ID 0x4402 /* 4402 primary function 0 */
5889 +#define BCM4402_ENET_ID 0x4402 /* 4402 enet */
5890 +#define BCM4402_V90_ID 0x4403 /* 4402 v90 codec */
5891 +#define BCM4401_ENET_ID 0x170c /* 4401b0 production enet cards */
5892 +
5893 +#define BCM4301_DEVICE_ID 0x4301 /* 4301 primary function 0 */
5894 +#define BCM4301_D11B_ID 0x4301 /* 4301 802.11b */
5895 +
5896 +#define BCM4307_DEVICE_ID 0x4307 /* 4307 primary function 0 */
5897 +#define BCM4307_V90_ID 0x4305 /* 4307 v90 codec */
5898 +#define BCM4307_ENET_ID 0x4306 /* 4307 enet */
5899 +#define BCM4307_D11B_ID 0x4307 /* 4307 802.11b */
5900 +
5901 +#define BCM4306_DEVICE_ID 0x4306 /* 4306 chipcommon chipid */
5902 +#define BCM4306_D11G_ID 0x4320 /* 4306 802.11g */
5903 +#define BCM4306_D11G_ID2 0x4325
5904 +#define BCM4306_D11A_ID 0x4321 /* 4306 802.11a */
5905 +#define BCM4306_UART_ID 0x4322 /* 4306 uart */
5906 +#define BCM4306_V90_ID 0x4323 /* 4306 v90 codec */
5907 +#define BCM4306_D11DUAL_ID 0x4324 /* 4306 dual A+B */
5908 +
5909 +#define BCM4309_PKG_ID 1 /* 4309 package id */
5910 +
5911 +#define BCM4303_D11B_ID 0x4303 /* 4303 802.11b */
5912 +#define BCM4303_PKG_ID 2 /* 4303 package id */
5913 +
5914 +#define BCM4310_DEVICE_ID 0x4310 /* 4310 chipcommon chipid */
5915 +#define BCM4310_D11B_ID 0x4311 /* 4310 802.11b */
5916 +#define BCM4310_UART_ID 0x4312 /* 4310 uart */
5917 +#define BCM4310_ENET_ID 0x4313 /* 4310 enet */
5918 +#define BCM4310_USB_ID 0x4315 /* 4310 usb */
5919 +
5920 +#define BCMGPRS_UART_ID 0x4333 /* Uart id used by 4306/gprs card */
5921 +#define BCMGPRS2_UART_ID 0x4344 /* Uart id used by 4306/gprs card */
5922 +
5923 +
5924 +#define BCM4704_DEVICE_ID 0x4704 /* 4704 chipcommon chipid */
5925 +#define BCM4704_ENET_ID 0x4706 /* 4704 enet (Use 47XX_ENET_ID instead!) */
5926 +
5927 +#define BCM4317_DEVICE_ID 0x4317 /* 4317 chip common chipid */
5928 +
5929 +#define BCM4318_DEVICE_ID 0x4318 /* 4318 chip common chipid */
5930 +#define BCM4318_D11G_ID 0x4318 /* 4318 801.11b/g id */
5931 +#define BCM4318_D11DUAL_ID 0x4319 /* 4318 801.11a/b/g id */
5932 +#define BCM4318_JTAGM_ID 0x4331 /* 4318 jtagm device id */
5933 +
5934 +#define FPGA_JTAGM_ID 0x4330 /* ??? */
5935 +
5936 +/* Address map */
5937 +#define BCM4710_SDRAM 0x00000000 /* Physical SDRAM */
5938 +#define BCM4710_PCI_MEM 0x08000000 /* Host Mode PCI memory access space (64 MB) */
5939 +#define BCM4710_PCI_CFG 0x0c000000 /* Host Mode PCI configuration space (64 MB) */
5940 +#define BCM4710_PCI_DMA 0x40000000 /* Client Mode PCI memory access space (1 GB) */
5941 +#define BCM4710_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
5942 +#define BCM4710_ENUM 0x18000000 /* Beginning of core enumeration space */
5943 +
5944 +/* Core register space */
5945 +#define BCM4710_REG_SDRAM 0x18000000 /* SDRAM core registers */
5946 +#define BCM4710_REG_ILINE20 0x18001000 /* InsideLine20 core registers */
5947 +#define BCM4710_REG_EMAC0 0x18002000 /* Ethernet MAC 0 core registers */
5948 +#define BCM4710_REG_CODEC 0x18003000 /* Codec core registers */
5949 +#define BCM4710_REG_USB 0x18004000 /* USB core registers */
5950 +#define BCM4710_REG_PCI 0x18005000 /* PCI core registers */
5951 +#define BCM4710_REG_MIPS 0x18006000 /* MIPS core registers */
5952 +#define BCM4710_REG_EXTIF 0x18007000 /* External Interface core registers */
5953 +#define BCM4710_REG_EMAC1 0x18008000 /* Ethernet MAC 1 core registers */
5954 +
5955 +#define BCM4710_EXTIF 0x1f000000 /* External Interface base address */
5956 +#define BCM4710_PCMCIA_MEM 0x1f000000 /* External Interface PCMCIA memory access */
5957 +#define BCM4710_PCMCIA_IO 0x1f100000 /* PCMCIA I/O access */
5958 +#define BCM4710_PCMCIA_CONF 0x1f200000 /* PCMCIA configuration */
5959 +#define BCM4710_PROG 0x1f800000 /* Programable interface */
5960 +#define BCM4710_FLASH 0x1fc00000 /* Flash */
5961 +
5962 +#define BCM4710_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
5963 +
5964 +#define BCM4710_UART (BCM4710_REG_EXTIF + 0x00000300)
5965 +
5966 +#define BCM4710_EUART (BCM4710_EXTIF + 0x00800000)
5967 +#define BCM4710_LED (BCM4710_EXTIF + 0x00900000)
5968 +
5969 +#define BCM4712_DEVICE_ID 0x4712 /* 4712 chipcommon chipid */
5970 +#define BCM4712_MIPS_ID 0x4720 /* 4712 base devid */
5971 +#define BCM4712LARGE_PKG_ID 0 /* 340pin 4712 package id */
5972 +#define BCM4712SMALL_PKG_ID 1 /* 200pin 4712 package id */
5973 +#define BCM4712MID_PKG_ID 2 /* 225pin 4712 package id */
5974 +
5975 +#define SDIOH_FPGA_ID 0x4380 /* sdio host fpga */
5976 +
5977 +#define BCM5365_DEVICE_ID 0x5365 /* 5365 chipcommon chipid */
5978 +#define BCM5350_DEVICE_ID 0x5350 /* bcm5350 chipcommon chipid */
5979 +#define BCM5352_DEVICE_ID 0x5352 /* bcm5352 chipcommon chipid */
5980 +
5981 +#define BCM4320_DEVICE_ID 0x4320 /* bcm4320 chipcommon chipid */
5982 +
5983 +/* PCMCIA vendor Id's */
5984 +
5985 +#define VENDOR_BROADCOM_PCMCIA 0x02d0
5986 +
5987 +/* SDIO vendor Id's */
5988 +#define VENDOR_BROADCOM_SDIO 0x00BF
5989 +
5990 +
5991 +/* boardflags */
5992 +#define BFL_BTCOEXIST 0x0001 /* This board implements Bluetooth coexistance */
5993 +#define BFL_PACTRL 0x0002 /* This board has gpio 9 controlling the PA */
5994 +#define BFL_AIRLINEMODE 0x0004 /* This board implements gpio13 radio disable indication */
5995 +#define BFL_ENETROBO 0x0010 /* This board has robo switch or core */
5996 +#define BFL_CCKHIPWR 0x0040 /* Can do high-power CCK transmission */
5997 +#define BFL_ENETADM 0x0080 /* This board has ADMtek switch */
5998 +#define BFL_ENETVLAN 0x0100 /* This board has vlan capability */
5999 +#define BFL_AFTERBURNER 0x0200 /* This board supports Afterburner mode */
6000 +#define BFL_NOPCI 0x0400 /* This board leaves PCI floating */
6001 +#define BFL_FEM 0x0800 /* This board supports the Front End Module */
6002 +#define BFL_EXTLNA 0x1000 /* This board has an external LNA */
6003 +#define BFL_HGPA 0x2000 /* This board has a high gain PA */
6004 +#define BFL_BTCMOD 0x4000 /* This board' BTCOEXIST is in the alternate gpios */
6005 +#define BFL_ALTIQ 0x8000 /* Alternate I/Q settings */
6006 +
6007 +/* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */
6008 +#define BOARD_GPIO_HWRAD_B 0x010 /* bit 4 is HWRAD input on 4301 */
6009 +#define BOARD_GPIO_BTCMOD_IN 0x010 /* bit 4 is the alternate BT Coexistance Input */
6010 +#define BOARD_GPIO_BTCMOD_OUT 0x020 /* bit 5 is the alternate BT Coexistance Out */
6011 +#define BOARD_GPIO_BTC_IN 0x080 /* bit 7 is BT Coexistance Input */
6012 +#define BOARD_GPIO_BTC_OUT 0x100 /* bit 8 is BT Coexistance Out */
6013 +#define BOARD_GPIO_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */
6014 +#define PCI_CFG_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */
6015 +#define PCI_CFG_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */
6016 +#define PCI_CFG_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */
6017 +#define PCI_CFG_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */
6018 +
6019 +/* Bus types */
6020 +#define SB_BUS 0 /* Silicon Backplane */
6021 +#define PCI_BUS 1 /* PCI target */
6022 +#define PCMCIA_BUS 2 /* PCMCIA target */
6023 +#define SDIO_BUS 3 /* SDIO target */
6024 +#define JTAG_BUS 4 /* JTAG */
6025 +
6026 +/* Allows optimization for single-bus support */
6027 +#ifdef BCMBUSTYPE
6028 +#define BUSTYPE(bus) (BCMBUSTYPE)
6029 +#else
6030 +#define BUSTYPE(bus) (bus)
6031 +#endif
6032 +
6033 +/* power control defines */
6034 +#define PLL_DELAY 150 /* us pll on delay */
6035 +#define FREF_DELAY 200 /* us fref change delay */
6036 +#define MIN_SLOW_CLK 32 /* us Slow clock period */
6037 +#define XTAL_ON_DELAY 1000 /* us crystal power-on delay */
6038 +
6039 +/* Reference Board Types */
6040 +
6041 +#define BU4710_BOARD 0x0400
6042 +#define VSIM4710_BOARD 0x0401
6043 +#define QT4710_BOARD 0x0402
6044 +
6045 +#define BU4610_BOARD 0x0403
6046 +#define VSIM4610_BOARD 0x0404
6047 +
6048 +#define BU4307_BOARD 0x0405
6049 +#define BCM94301CB_BOARD 0x0406
6050 +#define BCM94301PC_BOARD 0x0406 /* Pcmcia 5v card */
6051 +#define BCM94301MP_BOARD 0x0407
6052 +#define BCM94307MP_BOARD 0x0408
6053 +#define BCMAP4307_BOARD 0x0409
6054 +
6055 +#define BU4309_BOARD 0x040a
6056 +#define BCM94309CB_BOARD 0x040b
6057 +#define BCM94309MP_BOARD 0x040c
6058 +#define BCM4309AP_BOARD 0x040d
6059 +
6060 +#define BCM94302MP_BOARD 0x040e
6061 +
6062 +#define VSIM4310_BOARD 0x040f
6063 +#define BU4711_BOARD 0x0410
6064 +#define BCM94310U_BOARD 0x0411
6065 +#define BCM94310AP_BOARD 0x0412
6066 +#define BCM94310MP_BOARD 0x0414
6067 +
6068 +#define BU4306_BOARD 0x0416
6069 +#define BCM94306CB_BOARD 0x0417
6070 +#define BCM94306MP_BOARD 0x0418
6071 +
6072 +#define BCM94710D_BOARD 0x041a
6073 +#define BCM94710R1_BOARD 0x041b
6074 +#define BCM94710R4_BOARD 0x041c
6075 +#define BCM94710AP_BOARD 0x041d
6076 +
6077 +
6078 +#define BU2050_BOARD 0x041f
6079 +
6080 +
6081 +#define BCM94309G_BOARD 0x0421
6082 +
6083 +#define BCM94301PC3_BOARD 0x0422 /* Pcmcia 3.3v card */
6084 +
6085 +#define BU4704_BOARD 0x0423
6086 +#define BU4702_BOARD 0x0424
6087 +
6088 +#define BCM94306PC_BOARD 0x0425 /* pcmcia 3.3v 4306 card */
6089 +
6090 +#define BU4317_BOARD 0x0426
6091 +
6092 +
6093 +#define BCM94702MN_BOARD 0x0428
6094 +
6095 +/* BCM4702 1U CompactPCI Board */
6096 +#define BCM94702CPCI_BOARD 0x0429
6097 +
6098 +/* BCM4702 with BCM95380 VLAN Router */
6099 +#define BCM95380RR_BOARD 0x042a
6100 +
6101 +/* cb4306 with SiGe PA */
6102 +#define BCM94306CBSG_BOARD 0x042b
6103 +
6104 +/* mp4301 with 2050 radio */
6105 +#define BCM94301MPL_BOARD 0x042c
6106 +
6107 +/* cb4306 with SiGe PA */
6108 +#define PCSG94306_BOARD 0x042d
6109 +
6110 +/* bu4704 with sdram */
6111 +#define BU4704SD_BOARD 0x042e
6112 +
6113 +/* Dual 11a/11g Router */
6114 +#define BCM94704AGR_BOARD 0x042f
6115 +
6116 +/* 11a-only minipci */
6117 +#define BCM94308MP_BOARD 0x0430
6118 +
6119 +
6120 +
6121 +/* BCM94317 boards */
6122 +#define BCM94317CB_BOARD 0x0440
6123 +#define BCM94317MP_BOARD 0x0441
6124 +#define BCM94317PCMCIA_BOARD 0x0442
6125 +#define BCM94317SDIO_BOARD 0x0443
6126 +
6127 +#define BU4712_BOARD 0x0444
6128 +#define BU4712SD_BOARD 0x045d
6129 +#define BU4712L_BOARD 0x045f
6130 +
6131 +/* BCM4712 boards */
6132 +#define BCM94712AP_BOARD 0x0445
6133 +#define BCM94712P_BOARD 0x0446
6134 +
6135 +/* BCM4318 boards */
6136 +#define BU4318_BOARD 0x0447
6137 +#define CB4318_BOARD 0x0448
6138 +#define MPG4318_BOARD 0x0449
6139 +#define MP4318_BOARD 0x044a
6140 +#define SD4318_BOARD 0x044b
6141 +
6142 +/* BCM63XX boards */
6143 +#define BCM96338_BOARD 0x6338
6144 +#define BCM96345_BOARD 0x6345
6145 +#define BCM96348_BOARD 0x6348
6146 +
6147 +/* Another mp4306 with SiGe */
6148 +#define BCM94306P_BOARD 0x044c
6149 +
6150 +/* CF-like 4317 modules */
6151 +#define BCM94317CF_BOARD 0x044d
6152 +
6153 +/* mp4303 */
6154 +#define BCM94303MP_BOARD 0x044e
6155 +
6156 +/* mpsgh4306 */
6157 +#define BCM94306MPSGH_BOARD 0x044f
6158 +
6159 +/* BRCM 4306 w/ Front End Modules */
6160 +#define BCM94306MPM 0x0450
6161 +#define BCM94306MPL 0x0453
6162 +
6163 +/* 4712agr */
6164 +#define BCM94712AGR_BOARD 0x0451
6165 +
6166 +/* The real CF 4317 board */
6167 +#define CFI4317_BOARD 0x0452
6168 +
6169 +/* pcmcia 4303 */
6170 +#define PC4303_BOARD 0x0454
6171 +
6172 +/* 5350K */
6173 +#define BCM95350K_BOARD 0x0455
6174 +
6175 +/* 5350R */
6176 +#define BCM95350R_BOARD 0x0456
6177 +
6178 +/* 4306mplna */
6179 +#define BCM94306MPLNA_BOARD 0x0457
6180 +
6181 +/* 4320 boards */
6182 +#define BU4320_BOARD 0x0458
6183 +#define BU4320S_BOARD 0x0459
6184 +#define BCM94320PH_BOARD 0x045a
6185 +
6186 +/* 4306mph */
6187 +#define BCM94306MPH_BOARD 0x045b
6188 +
6189 +/* 4306pciv */
6190 +#define BCM94306PCIV_BOARD 0x045c
6191 +
6192 +#define BU4712SD_BOARD 0x045d
6193 +
6194 +#define BCM94320PFLSH_BOARD 0x045e
6195 +
6196 +#define BU4712L_BOARD 0x045f
6197 +#define BCM94712LGR_BOARD 0x0460
6198 +#define BCM94320R_BOARD 0x0461
6199 +
6200 +#define BU5352_BOARD 0x0462
6201 +
6202 +#define BCM94318MPGH_BOARD 0x0463
6203 +
6204 +
6205 +#define BCM95352GR_BOARD 0x0467
6206 +
6207 +/* bcm95351agr */
6208 +#define BCM95351AGR_BOARD 0x0470
6209 +
6210 +/* # of GPIO pins */
6211 +#define GPIO_NUMPINS 16
6212 +
6213 +#endif /* _BCMDEVS_H */
6214 diff -urN linux.old/arch/mips/bcm947xx/include/bcmendian.h linux.dev/arch/mips/bcm947xx/include/bcmendian.h
6215 --- linux.old/arch/mips/bcm947xx/include/bcmendian.h 1970-01-01 01:00:00.000000000 +0100
6216 +++ linux.dev/arch/mips/bcm947xx/include/bcmendian.h 2005-12-28 16:37:32.874261250 +0100
6217 @@ -0,0 +1,152 @@
6218 +/*
6219 + * local version of endian.h - byte order defines
6220 + *
6221 + * Copyright 2005, Broadcom Corporation
6222 + * All Rights Reserved.
6223 + *
6224 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6225 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6226 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6227 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6228 + *
6229 + * $Id$
6230 +*/
6231 +
6232 +#ifndef _BCMENDIAN_H_
6233 +#define _BCMENDIAN_H_
6234 +
6235 +#include <typedefs.h>
6236 +
6237 +/* Byte swap a 16 bit value */
6238 +#define BCMSWAP16(val) \
6239 + ((uint16)( \
6240 + (((uint16)(val) & (uint16)0x00ffU) << 8) | \
6241 + (((uint16)(val) & (uint16)0xff00U) >> 8) ))
6242 +
6243 +/* Byte swap a 32 bit value */
6244 +#define BCMSWAP32(val) \
6245 + ((uint32)( \
6246 + (((uint32)(val) & (uint32)0x000000ffUL) << 24) | \
6247 + (((uint32)(val) & (uint32)0x0000ff00UL) << 8) | \
6248 + (((uint32)(val) & (uint32)0x00ff0000UL) >> 8) | \
6249 + (((uint32)(val) & (uint32)0xff000000UL) >> 24) ))
6250 +
6251 +/* 2 Byte swap a 32 bit value */
6252 +#define BCMSWAP32BY16(val) \
6253 + ((uint32)( \
6254 + (((uint32)(val) & (uint32)0x0000ffffUL) << 16) | \
6255 + (((uint32)(val) & (uint32)0xffff0000UL) >> 16) ))
6256 +
6257 +
6258 +static INLINE uint16
6259 +bcmswap16(uint16 val)
6260 +{
6261 + return BCMSWAP16(val);
6262 +}
6263 +
6264 +static INLINE uint32
6265 +bcmswap32(uint32 val)
6266 +{
6267 + return BCMSWAP32(val);
6268 +}
6269 +
6270 +static INLINE uint32
6271 +bcmswap32by16(uint32 val)
6272 +{
6273 + return BCMSWAP32BY16(val);
6274 +}
6275 +
6276 +/* buf - start of buffer of shorts to swap */
6277 +/* len - byte length of buffer */
6278 +static INLINE void
6279 +bcmswap16_buf(uint16 *buf, uint len)
6280 +{
6281 + len = len/2;
6282 +
6283 + while(len--){
6284 + *buf = bcmswap16(*buf);
6285 + buf++;
6286 + }
6287 +}
6288 +
6289 +#ifndef hton16
6290 +#ifndef IL_BIGENDIAN
6291 +#define HTON16(i) BCMSWAP16(i)
6292 +#define hton16(i) bcmswap16(i)
6293 +#define hton32(i) bcmswap32(i)
6294 +#define ntoh16(i) bcmswap16(i)
6295 +#define ntoh32(i) bcmswap32(i)
6296 +#define ltoh16(i) (i)
6297 +#define ltoh32(i) (i)
6298 +#define htol16(i) (i)
6299 +#define htol32(i) (i)
6300 +#else
6301 +#define HTON16(i) (i)
6302 +#define hton16(i) (i)
6303 +#define hton32(i) (i)
6304 +#define ntoh16(i) (i)
6305 +#define ntoh32(i) (i)
6306 +#define ltoh16(i) bcmswap16(i)
6307 +#define ltoh32(i) bcmswap32(i)
6308 +#define htol16(i) bcmswap16(i)
6309 +#define htol32(i) bcmswap32(i)
6310 +#endif
6311 +#endif
6312 +
6313 +#ifndef IL_BIGENDIAN
6314 +#define ltoh16_buf(buf, i)
6315 +#define htol16_buf(buf, i)
6316 +#else
6317 +#define ltoh16_buf(buf, i) bcmswap16_buf((uint16*)buf, i)
6318 +#define htol16_buf(buf, i) bcmswap16_buf((uint16*)buf, i)
6319 +#endif
6320 +
6321 +/*
6322 +* load 16-bit value from unaligned little endian byte array.
6323 +*/
6324 +static INLINE uint16
6325 +ltoh16_ua(uint8 *bytes)
6326 +{
6327 + return (bytes[1]<<8)+bytes[0];
6328 +}
6329 +
6330 +/*
6331 +* load 32-bit value from unaligned little endian byte array.
6332 +*/
6333 +static INLINE uint32
6334 +ltoh32_ua(uint8 *bytes)
6335 +{
6336 + return (bytes[3]<<24)+(bytes[2]<<16)+(bytes[1]<<8)+bytes[0];
6337 +}
6338 +
6339 +/*
6340 +* load 16-bit value from unaligned big(network) endian byte array.
6341 +*/
6342 +static INLINE uint16
6343 +ntoh16_ua(uint8 *bytes)
6344 +{
6345 + return (bytes[0]<<8)+bytes[1];
6346 +}
6347 +
6348 +/*
6349 +* load 32-bit value from unaligned big(network) endian byte array.
6350 +*/
6351 +static INLINE uint32
6352 +ntoh32_ua(uint8 *bytes)
6353 +{
6354 + return (bytes[0]<<24)+(bytes[1]<<16)+(bytes[2]<<8)+bytes[3];
6355 +}
6356 +
6357 +#define ltoh_ua(ptr) ( \
6358 + sizeof(*(ptr)) == sizeof(uint8) ? *(uint8 *)ptr : \
6359 + sizeof(*(ptr)) == sizeof(uint16) ? (((uint8 *)ptr)[1]<<8)+((uint8 *)ptr)[0] : \
6360 + (((uint8 *)ptr)[3]<<24)+(((uint8 *)ptr)[2]<<16)+(((uint8 *)ptr)[1]<<8)+((uint8 *)ptr)[0] \
6361 +)
6362 +
6363 +#define ntoh_ua(ptr) ( \
6364 + sizeof(*(ptr)) == sizeof(uint8) ? *(uint8 *)ptr : \
6365 + sizeof(*(ptr)) == sizeof(uint16) ? (((uint8 *)ptr)[0]<<8)+((uint8 *)ptr)[1] : \
6366 + (((uint8 *)ptr)[0]<<24)+(((uint8 *)ptr)[1]<<16)+(((uint8 *)ptr)[2]<<8)+((uint8 *)ptr)[3] \
6367 +)
6368 +
6369 +#endif /* _BCMENDIAN_H_ */
6370 diff -urN linux.old/arch/mips/bcm947xx/include/bcmnvram.h linux.dev/arch/mips/bcm947xx/include/bcmnvram.h
6371 --- linux.old/arch/mips/bcm947xx/include/bcmnvram.h 1970-01-01 01:00:00.000000000 +0100
6372 +++ linux.dev/arch/mips/bcm947xx/include/bcmnvram.h 2005-12-28 19:28:28.399320000 +0100
6373 @@ -0,0 +1,95 @@
6374 +/*
6375 + * NVRAM variable manipulation
6376 + *
6377 + * Copyright 2005, Broadcom Corporation
6378 + * All Rights Reserved.
6379 + *
6380 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6381 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6382 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6383 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6384 + *
6385 + * $Id$
6386 + */
6387 +
6388 +#ifndef _bcmnvram_h_
6389 +#define _bcmnvram_h_
6390 +
6391 +#ifndef _LANGUAGE_ASSEMBLY
6392 +
6393 +#include <typedefs.h>
6394 +
6395 +struct nvram_header {
6396 + uint32 magic;
6397 + uint32 len;
6398 + uint32 crc_ver_init; /* 0:7 crc, 8:15 ver, 16:31 sdram_init */
6399 + uint32 config_refresh; /* 0:15 sdram_config, 16:31 sdram_refresh */
6400 + uint32 config_ncdl; /* ncdl values for memc */
6401 +};
6402 +
6403 +struct nvram_tuple {
6404 + char *name;
6405 + char *value;
6406 + struct nvram_tuple *next;
6407 +};
6408 +
6409 +/*
6410 + * Get the value of an NVRAM variable. The pointer returned may be
6411 + * invalid after a set.
6412 + * @param name name of variable to get
6413 + * @return value of variable or NULL if undefined
6414 + */
6415 +extern char * __init early_nvram_get(const char *name);
6416 +
6417 +/*
6418 + * Get the value of an NVRAM variable. The pointer returned may be
6419 + * invalid after a set.
6420 + * @param name name of variable to get
6421 + * @return value of variable or NULL if undefined
6422 + */
6423 +extern char *nvram_get(const char *name);
6424 +
6425 +/*
6426 + * Get the value of an NVRAM variable.
6427 + * @param name name of variable to get
6428 + * @return value of variable or NUL if undefined
6429 + */
6430 +#define nvram_safe_get(name) (BCMINIT(early_nvram_get)(name) ? : "")
6431 +
6432 +/*
6433 + * Match an NVRAM variable.
6434 + * @param name name of variable to match
6435 + * @param match value to compare against value of variable
6436 + * @return TRUE if variable is defined and its value is string equal
6437 + * to match or FALSE otherwise
6438 + */
6439 +static inline int
6440 +nvram_match(char *name, char *match) {
6441 + const char *value = BCMINIT(early_nvram_get)(name);
6442 + return (value && !strcmp(value, match));
6443 +}
6444 +
6445 +/*
6446 + * Inversely match an NVRAM variable.
6447 + * @param name name of variable to match
6448 + * @param match value to compare against value of variable
6449 + * @return TRUE if variable is defined and its value is not string
6450 + * equal to invmatch or FALSE otherwise
6451 + */
6452 +static inline int
6453 +nvram_invmatch(char *name, char *invmatch) {
6454 + const char *value = BCMINIT(early_nvram_get)(name);
6455 + return (value && strcmp(value, invmatch));
6456 +}
6457 +
6458 +#endif /* _LANGUAGE_ASSEMBLY */
6459 +
6460 +#define NVRAM_MAGIC 0x48534C46 /* 'FLSH' */
6461 +#define NVRAM_VERSION 1
6462 +#define NVRAM_HEADER_SIZE 20
6463 +#define NVRAM_SPACE 0x8000
6464 +
6465 +#define NVRAM_MAX_VALUE_LEN 255
6466 +#define NVRAM_MAX_PARAM_LEN 64
6467 +
6468 +#endif /* _bcmnvram_h_ */
6469 diff -urN linux.old/arch/mips/bcm947xx/include/bcmsrom.h linux.dev/arch/mips/bcm947xx/include/bcmsrom.h
6470 --- linux.old/arch/mips/bcm947xx/include/bcmsrom.h 1970-01-01 01:00:00.000000000 +0100
6471 +++ linux.dev/arch/mips/bcm947xx/include/bcmsrom.h 2005-12-28 16:37:32.874261250 +0100
6472 @@ -0,0 +1,23 @@
6473 +/*
6474 + * Misc useful routines to access NIC local SROM/OTP .
6475 + *
6476 + * Copyright 2005, Broadcom Corporation
6477 + * All Rights Reserved.
6478 + *
6479 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6480 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6481 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6482 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6483 + *
6484 + * $Id$
6485 + */
6486 +
6487 +#ifndef _bcmsrom_h_
6488 +#define _bcmsrom_h_
6489 +
6490 +extern int srom_var_init(void *sbh, uint bus, void *curmap, osl_t *osh, char **vars, int *count);
6491 +
6492 +extern int srom_read(uint bus, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf);
6493 +extern int srom_write(uint bus, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf);
6494 +
6495 +#endif /* _bcmsrom_h_ */
6496 diff -urN linux.old/arch/mips/bcm947xx/include/bcmutils.h linux.dev/arch/mips/bcm947xx/include/bcmutils.h
6497 --- linux.old/arch/mips/bcm947xx/include/bcmutils.h 1970-01-01 01:00:00.000000000 +0100
6498 +++ linux.dev/arch/mips/bcm947xx/include/bcmutils.h 2005-12-28 16:37:32.874261250 +0100
6499 @@ -0,0 +1,308 @@
6500 +/*
6501 + * Misc useful os-independent macros and functions.
6502 + *
6503 + * Copyright 2005, Broadcom Corporation
6504 + * All Rights Reserved.
6505 + *
6506 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6507 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6508 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6509 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6510 + * $Id$
6511 + */
6512 +
6513 +#ifndef _bcmutils_h_
6514 +#define _bcmutils_h_
6515 +
6516 +/*** driver-only section ***/
6517 +#include <osl.h>
6518 +
6519 +#define _BCM_U 0x01 /* upper */
6520 +#define _BCM_L 0x02 /* lower */
6521 +#define _BCM_D 0x04 /* digit */
6522 +#define _BCM_C 0x08 /* cntrl */
6523 +#define _BCM_P 0x10 /* punct */
6524 +#define _BCM_S 0x20 /* white space (space/lf/tab) */
6525 +#define _BCM_X 0x40 /* hex digit */
6526 +#define _BCM_SP 0x80 /* hard space (0x20) */
6527 +
6528 +#define GPIO_PIN_NOTDEFINED 0x20
6529 +
6530 +extern unsigned char bcm_ctype[];
6531 +#define bcm_ismask(x) (bcm_ctype[(int)(unsigned char)(x)])
6532 +
6533 +#define bcm_isalnum(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L|_BCM_D)) != 0)
6534 +#define bcm_isalpha(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L)) != 0)
6535 +#define bcm_iscntrl(c) ((bcm_ismask(c)&(_BCM_C)) != 0)
6536 +#define bcm_isdigit(c) ((bcm_ismask(c)&(_BCM_D)) != 0)
6537 +#define bcm_isgraph(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D)) != 0)
6538 +#define bcm_islower(c) ((bcm_ismask(c)&(_BCM_L)) != 0)
6539 +#define bcm_isprint(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D|_BCM_SP)) != 0)
6540 +#define bcm_ispunct(c) ((bcm_ismask(c)&(_BCM_P)) != 0)
6541 +#define bcm_isspace(c) ((bcm_ismask(c)&(_BCM_S)) != 0)
6542 +#define bcm_isupper(c) ((bcm_ismask(c)&(_BCM_U)) != 0)
6543 +#define bcm_isxdigit(c) ((bcm_ismask(c)&(_BCM_D|_BCM_X)) != 0)
6544 +
6545 +/*
6546 + * Spin at most 'us' microseconds while 'exp' is true.
6547 + * Caller should explicitly test 'exp' when this completes
6548 + * and take appropriate error action if 'exp' is still true.
6549 + */
6550 +#define SPINWAIT(exp, us) { \
6551 + uint countdown = (us) + 9; \
6552 + while ((exp) && (countdown >= 10)) {\
6553 + OSL_DELAY(10); \
6554 + countdown -= 10; \
6555 + } \
6556 +}
6557 +
6558 +/* generic osl packet queue */
6559 +struct pktq {
6560 + void *head; /* first packet to dequeue */
6561 + void *tail; /* last packet to dequeue */
6562 + uint len; /* number of queued packets */
6563 + uint maxlen; /* maximum number of queued packets */
6564 + bool priority; /* enqueue by packet priority */
6565 + uint8 prio_map[MAXPRIO+1]; /* user priority to packet enqueue policy map */
6566 +};
6567 +#define DEFAULT_QLEN 128
6568 +
6569 +#define pktq_len(q) ((q)->len)
6570 +#define pktq_avail(q) ((q)->maxlen - (q)->len)
6571 +#define pktq_head(q) ((q)->head)
6572 +#define pktq_full(q) ((q)->len >= (q)->maxlen)
6573 +#define _pktq_pri(q, pri) ((q)->prio_map[pri])
6574 +#define pktq_tailpri(q) ((q)->tail ? _pktq_pri(q, PKTPRIO((q)->tail)) : _pktq_pri(q, 0))
6575 +
6576 +/* externs */
6577 +/* packet */
6578 +extern uint pktcopy(osl_t *osh, void *p, uint offset, int len, uchar *buf);
6579 +extern uint pkttotlen(osl_t *osh, void *);
6580 +extern void pktq_init(struct pktq *q, uint maxlen, const uint8 prio_map[]);
6581 +extern void pktenq(struct pktq *q, void *p, bool lifo);
6582 +extern void *pktdeq(struct pktq *q);
6583 +extern void *pktdeqtail(struct pktq *q);
6584 +/* string */
6585 +extern uint bcm_atoi(char *s);
6586 +extern uchar bcm_toupper(uchar c);
6587 +extern ulong bcm_strtoul(char *cp, char **endp, uint base);
6588 +extern char *bcmstrstr(char *haystack, char *needle);
6589 +extern char *bcmstrcat(char *dest, const char *src);
6590 +extern ulong wchar2ascii(char *abuf, ushort *wbuf, ushort wbuflen, ulong abuflen);
6591 +/* ethernet address */
6592 +extern char *bcm_ether_ntoa(char *ea, char *buf);
6593 +extern int bcm_ether_atoe(char *p, char *ea);
6594 +/* delay */
6595 +extern void bcm_mdelay(uint ms);
6596 +/* variable access */
6597 +extern char *getvar(char *vars, char *name);
6598 +extern int getintvar(char *vars, char *name);
6599 +extern uint getgpiopin(char *vars, char *pin_name, uint def_pin);
6600 +#define bcmlog(fmt, a1, a2)
6601 +#define bcmdumplog(buf, size) *buf = '\0'
6602 +#define bcmdumplogent(buf, idx) -1
6603 +
6604 +/*** driver/apps-shared section ***/
6605 +
6606 +#define BCME_STRLEN 64
6607 +#define VALID_BCMERROR(e) ((e <= 0) && (e >= BCME_LAST))
6608 +
6609 +
6610 +/*
6611 + * error codes could be added but the defined ones shouldn't be changed/deleted
6612 + * these error codes are exposed to the user code
6613 + * when ever a new error code is added to this list
6614 + * please update errorstring table with the related error string and
6615 + * update osl files with os specific errorcode map
6616 +*/
6617 +
6618 +#define BCME_ERROR -1 /* Error generic */
6619 +#define BCME_BADARG -2 /* Bad Argument */
6620 +#define BCME_BADOPTION -3 /* Bad option */
6621 +#define BCME_NOTUP -4 /* Not up */
6622 +#define BCME_NOTDOWN -5 /* Not down */
6623 +#define BCME_NOTAP -6 /* Not AP */
6624 +#define BCME_NOTSTA -7 /* Not STA */
6625 +#define BCME_BADKEYIDX -8 /* BAD Key Index */
6626 +#define BCME_RADIOOFF -9 /* Radio Off */
6627 +#define BCME_NOTBANDLOCKED -10 /* Not bandlocked */
6628 +#define BCME_NOCLK -11 /* No Clock*/
6629 +#define BCME_BADRATESET -12 /* BAD RateSet*/
6630 +#define BCME_BADBAND -13 /* BAD Band */
6631 +#define BCME_BUFTOOSHORT -14 /* Buffer too short */
6632 +#define BCME_BUFTOOLONG -15 /* Buffer too Long */
6633 +#define BCME_BUSY -16 /* Busy*/
6634 +#define BCME_NOTASSOCIATED -17 /* Not associated*/
6635 +#define BCME_BADSSIDLEN -18 /* BAD SSID Len */
6636 +#define BCME_OUTOFRANGECHAN -19 /* Out of Range Channel*/
6637 +#define BCME_BADCHAN -20 /* BAD Channel */
6638 +#define BCME_BADADDR -21 /* BAD Address*/
6639 +#define BCME_NORESOURCE -22 /* No resources*/
6640 +#define BCME_UNSUPPORTED -23 /* Unsupported*/
6641 +#define BCME_BADLEN -24 /* Bad Length*/
6642 +#define BCME_NOTREADY -25 /* Not ready Yet*/
6643 +#define BCME_EPERM -26 /* Not Permitted */
6644 +#define BCME_NOMEM -27 /* No Memory */
6645 +#define BCME_ASSOCIATED -28 /* Associated */
6646 +#define BCME_RANGE -29 /* Range Error*/
6647 +#define BCME_NOTFOUND -30 /* Not found */
6648 +#define BCME_LAST BCME_NOTFOUND
6649 +
6650 +#ifndef ABS
6651 +#define ABS(a) (((a)<0)?-(a):(a))
6652 +#endif
6653 +
6654 +#ifndef MIN
6655 +#define MIN(a, b) (((a)<(b))?(a):(b))
6656 +#endif
6657 +
6658 +#ifndef MAX
6659 +#define MAX(a, b) (((a)>(b))?(a):(b))
6660 +#endif
6661 +
6662 +#define CEIL(x, y) (((x) + ((y)-1)) / (y))
6663 +#define ROUNDUP(x, y) ((((x)+((y)-1))/(y))*(y))
6664 +#define ISALIGNED(a, x) (((a) & ((x)-1)) == 0)
6665 +#define ISPOWEROF2(x) ((((x)-1)&(x))==0)
6666 +#define VALID_MASK(mask) !((mask) & ((mask) + 1))
6667 +#define OFFSETOF(type, member) ((uint)(uintptr)&((type *)0)->member)
6668 +#define ARRAYSIZE(a) (sizeof(a)/sizeof(a[0]))
6669 +
6670 +/* bit map related macros */
6671 +#ifndef setbit
6672 +#define NBBY 8 /* 8 bits per byte */
6673 +#define setbit(a,i) (((uint8 *)a)[(i)/NBBY] |= 1<<((i)%NBBY))
6674 +#define clrbit(a,i) (((uint8 *)a)[(i)/NBBY] &= ~(1<<((i)%NBBY)))
6675 +#define isset(a,i) (((uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY)))
6676 +#define isclr(a,i) ((((uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY))) == 0)
6677 +#endif
6678 +
6679 +#define NBITS(type) (sizeof(type) * 8)
6680 +#define NBITVAL(bits) (1 << (bits))
6681 +#define MAXBITVAL(bits) ((1 << (bits)) - 1)
6682 +
6683 +/* crc defines */
6684 +#define CRC8_INIT_VALUE 0xff /* Initial CRC8 checksum value */
6685 +#define CRC8_GOOD_VALUE 0x9f /* Good final CRC8 checksum value */
6686 +#define CRC16_INIT_VALUE 0xffff /* Initial CRC16 checksum value */
6687 +#define CRC16_GOOD_VALUE 0xf0b8 /* Good final CRC16 checksum value */
6688 +#define CRC32_INIT_VALUE 0xffffffff /* Initial CRC32 checksum value */
6689 +#define CRC32_GOOD_VALUE 0xdebb20e3 /* Good final CRC32 checksum value */
6690 +
6691 +/* bcm_format_flags() bit description structure */
6692 +typedef struct bcm_bit_desc {
6693 + uint32 bit;
6694 + char* name;
6695 +} bcm_bit_desc_t;
6696 +
6697 +/* tag_ID/length/value_buffer tuple */
6698 +typedef struct bcm_tlv {
6699 + uint8 id;
6700 + uint8 len;
6701 + uint8 data[1];
6702 +} bcm_tlv_t;
6703 +
6704 +/* Check that bcm_tlv_t fits into the given buflen */
6705 +#define bcm_valid_tlv(elt, buflen) ((buflen) >= 2 && (int)(buflen) >= (int)(2 + (elt)->len))
6706 +
6707 +/* buffer length for ethernet address from bcm_ether_ntoa() */
6708 +#define ETHER_ADDR_STR_LEN 18
6709 +
6710 +/* unaligned load and store macros */
6711 +#ifdef IL_BIGENDIAN
6712 +static INLINE uint32
6713 +load32_ua(uint8 *a)
6714 +{
6715 + return ((a[0] << 24) | (a[1] << 16) | (a[2] << 8) | a[3]);
6716 +}
6717 +
6718 +static INLINE void
6719 +store32_ua(uint8 *a, uint32 v)
6720 +{
6721 + a[0] = (v >> 24) & 0xff;
6722 + a[1] = (v >> 16) & 0xff;
6723 + a[2] = (v >> 8) & 0xff;
6724 + a[3] = v & 0xff;
6725 +}
6726 +
6727 +static INLINE uint16
6728 +load16_ua(uint8 *a)
6729 +{
6730 + return ((a[0] << 8) | a[1]);
6731 +}
6732 +
6733 +static INLINE void
6734 +store16_ua(uint8 *a, uint16 v)
6735 +{
6736 + a[0] = (v >> 8) & 0xff;
6737 + a[1] = v & 0xff;
6738 +}
6739 +
6740 +#else
6741 +
6742 +static INLINE uint32
6743 +load32_ua(uint8 *a)
6744 +{
6745 + return ((a[3] << 24) | (a[2] << 16) | (a[1] << 8) | a[0]);
6746 +}
6747 +
6748 +static INLINE void
6749 +store32_ua(uint8 *a, uint32 v)
6750 +{
6751 + a[3] = (v >> 24) & 0xff;
6752 + a[2] = (v >> 16) & 0xff;
6753 + a[1] = (v >> 8) & 0xff;
6754 + a[0] = v & 0xff;
6755 +}
6756 +
6757 +static INLINE uint16
6758 +load16_ua(uint8 *a)
6759 +{
6760 + return ((a[1] << 8) | a[0]);
6761 +}
6762 +
6763 +static INLINE void
6764 +store16_ua(uint8 *a, uint16 v)
6765 +{
6766 + a[1] = (v >> 8) & 0xff;
6767 + a[0] = v & 0xff;
6768 +}
6769 +
6770 +#endif
6771 +
6772 +/* externs */
6773 +/* crc */
6774 +extern uint8 hndcrc8(uint8 *p, uint nbytes, uint8 crc);
6775 +/* format/print */
6776 +/* IE parsing */
6777 +extern bcm_tlv_t *bcm_next_tlv(bcm_tlv_t *elt, int *buflen);
6778 +extern bcm_tlv_t *bcm_parse_tlvs(void *buf, int buflen, uint key);
6779 +extern bcm_tlv_t *bcm_parse_ordered_tlvs(void *buf, int buflen, uint key);
6780 +
6781 +/* bcmerror*/
6782 +extern const char *bcmerrorstr(int bcmerror);
6783 +
6784 +/* multi-bool data type: set of bools, mbool is true if any is set */
6785 +typedef uint32 mbool;
6786 +#define mboolset(mb, bit) (mb |= bit) /* set one bool */
6787 +#define mboolclr(mb, bit) (mb &= ~bit) /* clear one bool */
6788 +#define mboolisset(mb, bit) ((mb & bit) != 0) /* TRUE if one bool is set */
6789 +#define mboolmaskset(mb, mask, val) ((mb) = (((mb) & ~(mask)) | (val)))
6790 +
6791 +/* power conversion */
6792 +extern uint16 bcm_qdbm_to_mw(uint8 qdbm);
6793 +extern uint8 bcm_mw_to_qdbm(uint16 mw);
6794 +
6795 +/* generic datastruct to help dump routines */
6796 +struct fielddesc {
6797 + char *nameandfmt;
6798 + uint32 offset;
6799 + uint32 len;
6800 +};
6801 +
6802 +typedef uint32 (*readreg_rtn)(void *arg0, void *arg1, uint32 offset);
6803 +extern uint bcmdumpfields(readreg_rtn func_ptr, void *arg0, void *arg1, struct fielddesc *str, char *buf, uint32 bufsize);
6804 +
6805 +extern uint bcm_mkiovar(char *name, char *data, uint datalen, char *buf, uint len);
6806 +
6807 +#endif /* _bcmutils_h_ */
6808 diff -urN linux.old/arch/mips/bcm947xx/include/bitfuncs.h linux.dev/arch/mips/bcm947xx/include/bitfuncs.h
6809 --- linux.old/arch/mips/bcm947xx/include/bitfuncs.h 1970-01-01 01:00:00.000000000 +0100
6810 +++ linux.dev/arch/mips/bcm947xx/include/bitfuncs.h 2005-12-28 16:37:32.874261250 +0100
6811 @@ -0,0 +1,85 @@
6812 +/*
6813 + * bit manipulation utility functions
6814 + *
6815 + * Copyright 2005, Broadcom Corporation
6816 + * All Rights Reserved.
6817 + *
6818 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6819 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6820 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6821 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6822 + * $Id$
6823 + */
6824 +
6825 +#ifndef _BITFUNCS_H
6826 +#define _BITFUNCS_H
6827 +
6828 +#include <typedefs.h>
6829 +
6830 +/* local prototypes */
6831 +static INLINE uint32 find_msbit(uint32 x);
6832 +
6833 +
6834 +/*
6835 + * find_msbit: returns index of most significant set bit in x, with index
6836 + * range defined as 0-31. NOTE: returns zero if input is zero.
6837 + */
6838 +
6839 +#if defined(USE_PENTIUM_BSR) && defined(__GNUC__)
6840 +
6841 +/*
6842 + * Implementation for Pentium processors and gcc. Note that this
6843 + * instruction is actually very slow on some processors (e.g., family 5,
6844 + * model 2, stepping 12, "Pentium 75 - 200"), so we use the generic
6845 + * implementation instead.
6846 + */
6847 +static INLINE uint32 find_msbit(uint32 x)
6848 +{
6849 + uint msbit;
6850 + __asm__("bsrl %1,%0"
6851 + :"=r" (msbit)
6852 + :"r" (x));
6853 + return msbit;
6854 +}
6855 +
6856 +#else
6857 +
6858 +/*
6859 + * Generic Implementation
6860 + */
6861 +
6862 +#define DB_POW_MASK16 0xffff0000
6863 +#define DB_POW_MASK8 0x0000ff00
6864 +#define DB_POW_MASK4 0x000000f0
6865 +#define DB_POW_MASK2 0x0000000c
6866 +#define DB_POW_MASK1 0x00000002
6867 +
6868 +static INLINE uint32 find_msbit(uint32 x)
6869 +{
6870 + uint32 temp_x = x;
6871 + uint msbit = 0;
6872 + if (temp_x & DB_POW_MASK16) {
6873 + temp_x >>= 16;
6874 + msbit = 16;
6875 + }
6876 + if (temp_x & DB_POW_MASK8) {
6877 + temp_x >>= 8;
6878 + msbit += 8;
6879 + }
6880 + if (temp_x & DB_POW_MASK4) {
6881 + temp_x >>= 4;
6882 + msbit += 4;
6883 + }
6884 + if (temp_x & DB_POW_MASK2) {
6885 + temp_x >>= 2;
6886 + msbit += 2;
6887 + }
6888 + if (temp_x & DB_POW_MASK1) {
6889 + msbit += 1;
6890 + }
6891 + return(msbit);
6892 +}
6893 +
6894 +#endif
6895 +
6896 +#endif /* _BITFUNCS_H */
6897 diff -urN linux.old/arch/mips/bcm947xx/include/flash.h linux.dev/arch/mips/bcm947xx/include/flash.h
6898 --- linux.old/arch/mips/bcm947xx/include/flash.h 1970-01-01 01:00:00.000000000 +0100
6899 +++ linux.dev/arch/mips/bcm947xx/include/flash.h 2005-12-28 16:37:32.874261250 +0100
6900 @@ -0,0 +1,188 @@
6901 +/*
6902 + * flash.h: Common definitions for flash access.
6903 + *
6904 + * Copyright 2005, Broadcom Corporation
6905 + * All Rights Reserved.
6906 + *
6907 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6908 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6909 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6910 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6911 + *
6912 + * $Id$
6913 + */
6914 +
6915 +/* Types of flashes we know about */
6916 +typedef enum _flash_type {OLD, BSC, SCS, AMD, SST, SFLASH} flash_type_t;
6917 +
6918 +/* Commands to write/erase the flases */
6919 +typedef struct _flash_cmds{
6920 + flash_type_t type;
6921 + bool need_unlock;
6922 + uint16 pre_erase;
6923 + uint16 erase_block;
6924 + uint16 erase_chip;
6925 + uint16 write_word;
6926 + uint16 write_buf;
6927 + uint16 clear_csr;
6928 + uint16 read_csr;
6929 + uint16 read_id;
6930 + uint16 confirm;
6931 + uint16 read_array;
6932 +} flash_cmds_t;
6933 +
6934 +#define UNLOCK_CMD_WORDS 2
6935 +
6936 +typedef struct _unlock_cmd {
6937 + uint addr[UNLOCK_CMD_WORDS];
6938 + uint16 cmd[UNLOCK_CMD_WORDS];
6939 +} unlock_cmd_t;
6940 +
6941 +/* Flash descriptors */
6942 +typedef struct _flash_desc {
6943 + uint16 mfgid; /* Manufacturer Id */
6944 + uint16 devid; /* Device Id */
6945 + uint size; /* Total size in bytes */
6946 + uint width; /* Device width in bytes */
6947 + flash_type_t type; /* Device type old, S, J */
6948 + uint bsize; /* Block size */
6949 + uint nb; /* Number of blocks */
6950 + uint ff; /* First full block */
6951 + uint lf; /* Last full block */
6952 + uint nsub; /* Number of subblocks */
6953 + uint *subblocks; /* Offsets for subblocks */
6954 + char *desc; /* Description */
6955 +} flash_desc_t;
6956 +
6957 +
6958 +#ifdef DECLARE_FLASHES
6959 +flash_cmds_t sflash_cmd_t =
6960 + { SFLASH, 0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
6961 +
6962 +flash_cmds_t flash_cmds[] = {
6963 +/* type needu preera eraseb erasech write wbuf clcsr rdcsr rdid confrm read */
6964 + { BSC, 0, 0x00, 0x20, 0x00, 0x40, 0x00, 0x50, 0x70, 0x90, 0xd0, 0xff },
6965 + { SCS, 0, 0x00, 0x20, 0x00, 0x40, 0xe8, 0x50, 0x70, 0x90, 0xd0, 0xff },
6966 + { AMD, 1, 0x80, 0x30, 0x10, 0xa0, 0x00, 0x00, 0x00, 0x90, 0x00, 0xf0 },
6967 + { SST, 1, 0x80, 0x50, 0x10, 0xa0, 0x00, 0x00, 0x00, 0x90, 0x00, 0xf0 },
6968 + { 0 }
6969 +};
6970 +
6971 +unlock_cmd_t unlock_cmd_amd = {
6972 +#ifdef MIPSEB
6973 +/* addr: */ { 0x0aa8, 0x0556},
6974 +#else
6975 +/* addr: */ { 0x0aaa, 0x0554},
6976 +#endif
6977 +/* data: */ { 0xaa, 0x55}
6978 +};
6979 +
6980 +unlock_cmd_t unlock_cmd_sst = {
6981 +#ifdef MIPSEB
6982 +/* addr: */ { 0xaaa8, 0x5556},
6983 +#else
6984 +/* addr: */ { 0xaaaa, 0x5554},
6985 +#endif
6986 +/* data: */ { 0xaa, 0x55}
6987 +};
6988 +
6989 +#define AMD_CMD 0xaaa
6990 +#define SST_CMD 0xaaaa
6991 +
6992 +/* intel unlock block cmds */
6993 +#define INTEL_UNLOCK1 0x60
6994 +#define INTEL_UNLOCK2 0xD0
6995 +
6996 +/* Just eight blocks of 8KB byte each */
6997 +
6998 +uint blk8x8k[] = { 0x00000000,
6999 + 0x00002000,
7000 + 0x00004000,
7001 + 0x00006000,
7002 + 0x00008000,
7003 + 0x0000a000,
7004 + 0x0000c000,
7005 + 0x0000e000,
7006 + 0x00010000
7007 +};
7008 +
7009 +/* Funky AMD arrangement for 29xx800's */
7010 +uint amd800[] = { 0x00000000, /* 16KB */
7011 + 0x00004000, /* 32KB */
7012 + 0x0000c000, /* 8KB */
7013 + 0x0000e000, /* 8KB */
7014 + 0x00010000, /* 8KB */
7015 + 0x00012000, /* 8KB */
7016 + 0x00014000, /* 32KB */
7017 + 0x0001c000, /* 16KB */
7018 + 0x00020000
7019 +};
7020 +
7021 +/* AMD arrangement for 29xx160's */
7022 +uint amd4112[] = { 0x00000000, /* 32KB */
7023 + 0x00008000, /* 8KB */
7024 + 0x0000a000, /* 8KB */
7025 + 0x0000c000, /* 16KB */
7026 + 0x00010000
7027 +};
7028 +uint amd2114[] = { 0x00000000, /* 16KB */
7029 + 0x00004000, /* 8KB */
7030 + 0x00006000, /* 8KB */
7031 + 0x00008000, /* 32KB */
7032 + 0x00010000
7033 +};
7034 +
7035 +
7036 +flash_desc_t sflash_desc =
7037 + { 0, 0, 0, 0, SFLASH, 0, 0, 0, 0, 0, NULL, "SFLASH" };
7038 +
7039 +flash_desc_t flashes[] = {
7040 + { 0x00b0, 0x00d0, 0x0200000, 2, SCS, 0x10000, 32, 0, 31, 0, NULL, "Intel 28F160S3/5 1Mx16" },
7041 + { 0x00b0, 0x00d4, 0x0400000, 2, SCS, 0x10000, 64, 0, 63, 0, NULL, "Intel 28F320S3/5 2Mx16" },
7042 + { 0x0089, 0x8890, 0x0200000, 2, BSC, 0x10000, 32, 0, 30, 8, blk8x8k, "Intel 28F160B3 1Mx16 TopB" },
7043 + { 0x0089, 0x8891, 0x0200000, 2, BSC, 0x10000, 32, 1, 31, 8, blk8x8k, "Intel 28F160B3 1Mx16 BotB" },
7044 + { 0x0089, 0x8896, 0x0400000, 2, BSC, 0x10000, 64, 0, 62, 8, blk8x8k, "Intel 28F320B3 2Mx16 TopB" },
7045 + { 0x0089, 0x8897, 0x0400000, 2, BSC, 0x10000, 64, 1, 63, 8, blk8x8k, "Intel 28F320B3 2Mx16 BotB" },
7046 + { 0x0089, 0x8898, 0x0800000, 2, BSC, 0x10000, 128, 0, 126, 8, blk8x8k, "Intel 28F640B3 4Mx16 TopB" },
7047 + { 0x0089, 0x8899, 0x0800000, 2, BSC, 0x10000, 128, 1, 127, 8, blk8x8k, "Intel 28F640B3 4Mx16 BotB" },
7048 + { 0x0089, 0x88C2, 0x0200000, 2, BSC, 0x10000, 32, 0, 30, 8, blk8x8k, "Intel 28F160C3 1Mx16 TopB" },
7049 + { 0x0089, 0x88C3, 0x0200000, 2, BSC, 0x10000, 32, 1, 31, 8, blk8x8k, "Intel 28F160C3 1Mx16 BotB" },
7050 + { 0x0089, 0x88C4, 0x0400000, 2, BSC, 0x10000, 64, 0, 62, 8, blk8x8k, "Intel 28F320C3 2Mx16 TopB" },
7051 + { 0x0089, 0x88C5, 0x0400000, 2, BSC, 0x10000, 64, 1, 63, 8, blk8x8k, "Intel 28F320C3 2Mx16 BotB" },
7052 + { 0x0089, 0x88CC, 0x0800000, 2, BSC, 0x10000, 128, 0, 126, 8, blk8x8k, "Intel 28F640C3 4Mx16 TopB" },
7053 + { 0x0089, 0x88CD, 0x0800000, 2, BSC, 0x10000, 128, 1, 127, 8, blk8x8k, "Intel 28F640C3 4Mx16 BotB" },
7054 + { 0x0089, 0x0014, 0x0400000, 2, SCS, 0x20000, 32, 0, 31, 0, NULL, "Intel 28F320J5 2Mx16" },
7055 + { 0x0089, 0x0015, 0x0800000, 2, SCS, 0x20000, 64, 0, 63, 0, NULL, "Intel 28F640J5 4Mx16" },
7056 + { 0x0089, 0x0016, 0x0400000, 2, SCS, 0x20000, 32, 0, 31, 0, NULL, "Intel 28F320J3 2Mx16" },
7057 + { 0x0089, 0x0017, 0x0800000, 2, SCS, 0x20000, 64, 0, 63, 0, NULL, "Intel 28F640J3 4Mx16" },
7058 + { 0x0089, 0x0018, 0x1000000, 2, SCS, 0x20000, 128, 0, 127, 0, NULL, "Intel 28F128J3 8Mx16" },
7059 + { 0x00b0, 0x00e3, 0x0400000, 2, BSC, 0x10000, 64, 1, 63, 8, blk8x8k, "Sharp 28F320BJE 2Mx16 BotB" },
7060 + { 0x0001, 0x224a, 0x0100000, 2, AMD, 0x10000, 16, 0, 13, 8, amd800, "AMD 29DL800BT 512Kx16 TopB" },
7061 + { 0x0001, 0x22cb, 0x0100000, 2, AMD, 0x10000, 16, 2, 15, 8, amd800, "AMD 29DL800BB 512Kx16 BotB" },
7062 + { 0x0001, 0x22c4, 0x0200000, 2, AMD, 0x10000, 32, 0, 30, 4, amd2114, "AMD 29lv160DT 1Mx16 TopB" },
7063 + { 0x0001, 0x2249, 0x0200000, 2, AMD, 0x10000, 32, 1, 31, 4, amd4112, "AMD 29lv160DB 1Mx16 BotB" },
7064 + { 0x0001, 0x22f6, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 8, blk8x8k, "AMD 29lv320DT 2Mx16 TopB" },
7065 + { 0x0001, 0x22f9, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 8, blk8x8k, "AMD 29lv320DB 2Mx16 BotB" },
7066 + { 0x0001, 0x227e, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 8, blk8x8k, "AMD 29lv320MT 2Mx16 TopB" },
7067 + { 0x0001, 0x2200, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 8, blk8x8k, "AMD 29lv320MB 2Mx16 BotB" },
7068 + { 0x0020, 0x22CA, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "ST 29w320DT 2Mx16 TopB" },
7069 + { 0x0020, 0x22CB, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "ST 29w320DB 2Mx16 BotB" },
7070 + { 0x00C2, 0x00A7, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "MX29LV320T 2Mx16 TopB" },
7071 + { 0x00C2, 0x00A8, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "MX29LV320B 2Mx16 BotB" },
7072 + { 0x0004, 0x22F6, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "MBM29LV320TE 2Mx16 TopB" },
7073 + { 0x0004, 0x22F9, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "MBM29LV320BE 2Mx16 BotB" },
7074 + { 0x0098, 0x009A, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "TC58FVT321 2Mx16 TopB" },
7075 + { 0x0098, 0x009C, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "TC58FVB321 2Mx16 BotB" },
7076 + { 0x00C2, 0x22A7, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "MX29LV320T 2Mx16 TopB" },
7077 + { 0x00C2, 0x22A8, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "MX29LV320B 2Mx16 BotB" },
7078 + { 0x00BF, 0x2783, 0x0400000, 2, SST, 0x10000, 64, 0, 63, 0, NULL, "SST39VF320 2Mx16" },
7079 + { 0, 0, 0, 0, OLD, 0, 0, 0, 0, 0, NULL, NULL },
7080 +};
7081 +
7082 +#else
7083 +
7084 +extern flash_cmds_t flash_cmds[];
7085 +extern unlock_cmd_t unlock_cmd;
7086 +extern flash_desc_t flashes[];
7087 +
7088 +#endif
7089 diff -urN linux.old/arch/mips/bcm947xx/include/flashutl.h linux.dev/arch/mips/bcm947xx/include/flashutl.h
7090 --- linux.old/arch/mips/bcm947xx/include/flashutl.h 1970-01-01 01:00:00.000000000 +0100
7091 +++ linux.dev/arch/mips/bcm947xx/include/flashutl.h 2005-12-28 16:37:32.878261500 +0100
7092 @@ -0,0 +1,27 @@
7093 +/*
7094 + * BCM47XX FLASH driver interface
7095 + *
7096 + * Copyright 2005, Broadcom Corporation
7097 + * All Rights Reserved.
7098 + *
7099 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7100 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7101 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7102 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7103 + * $Id$
7104 + */
7105 +
7106 +#ifndef _flashutl_h_
7107 +#define _flashutl_h_
7108 +
7109 +
7110 +#ifndef _LANGUAGE_ASSEMBLY
7111 +
7112 +int sysFlashInit(char *flash_str);
7113 +int sysFlashRead(uint off, uchar *dst, uint bytes);
7114 +int sysFlashWrite(uint off, uchar *src, uint bytes);
7115 +void nvWrite(unsigned short *data, unsigned int len);
7116 +
7117 +#endif /* _LANGUAGE_ASSEMBLY */
7118 +
7119 +#endif /* _flashutl_h_ */
7120 diff -urN linux.old/arch/mips/bcm947xx/include/hndmips.h linux.dev/arch/mips/bcm947xx/include/hndmips.h
7121 --- linux.old/arch/mips/bcm947xx/include/hndmips.h 1970-01-01 01:00:00.000000000 +0100
7122 +++ linux.dev/arch/mips/bcm947xx/include/hndmips.h 2005-12-28 16:37:32.878261500 +0100
7123 @@ -0,0 +1,16 @@
7124 +/*
7125 + * Alternate include file for HND sbmips.h since CFE also ships with
7126 + * a sbmips.h.
7127 + *
7128 + * Copyright 2005, Broadcom Corporation
7129 + * All Rights Reserved.
7130 + *
7131 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7132 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7133 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7134 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7135 + *
7136 + * $Id$
7137 + */
7138 +
7139 +#include "sbmips.h"
7140 diff -urN linux.old/arch/mips/bcm947xx/include/linux_osl.h linux.dev/arch/mips/bcm947xx/include/linux_osl.h
7141 --- linux.old/arch/mips/bcm947xx/include/linux_osl.h 1970-01-01 01:00:00.000000000 +0100
7142 +++ linux.dev/arch/mips/bcm947xx/include/linux_osl.h 2005-12-28 16:37:32.878261500 +0100
7143 @@ -0,0 +1,331 @@
7144 +/*
7145 + * Linux OS Independent Layer
7146 + *
7147 + * Copyright 2005, Broadcom Corporation
7148 + * All Rights Reserved.
7149 + *
7150 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7151 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7152 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7153 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7154 + *
7155 + * $Id$
7156 + */
7157 +
7158 +#ifndef _linux_osl_h_
7159 +#define _linux_osl_h_
7160 +
7161 +#include <typedefs.h>
7162 +
7163 +/* use current 2.4.x calling conventions */
7164 +#include <linuxver.h>
7165 +
7166 +/* assert and panic */
7167 +#ifdef __GNUC__
7168 +#define GCC_VERSION (__GNUC__ * 10000 + __GNUC_MINOR__ * 100 + __GNUC_PATCHLEVEL__)
7169 +#if GCC_VERSION > 30100
7170 +#define ASSERT(exp) do {} while (0)
7171 +#else
7172 +/* ASSERT could causes segmentation fault on GCC3.1, use empty instead*/
7173 +#define ASSERT(exp)
7174 +#endif
7175 +#endif
7176 +
7177 +/* microsecond delay */
7178 +#define OSL_DELAY(usec) osl_delay(usec)
7179 +extern void osl_delay(uint usec);
7180 +
7181 +/* PCI configuration space access macros */
7182 +#define OSL_PCI_READ_CONFIG(osh, offset, size) \
7183 + osl_pci_read_config((osh), (offset), (size))
7184 +#define OSL_PCI_WRITE_CONFIG(osh, offset, size, val) \
7185 + osl_pci_write_config((osh), (offset), (size), (val))
7186 +extern uint32 osl_pci_read_config(osl_t *osh, uint size, uint offset);
7187 +extern void osl_pci_write_config(osl_t *osh, uint offset, uint size, uint val);
7188 +
7189 +/* PCI device bus # and slot # */
7190 +#define OSL_PCI_BUS(osh) osl_pci_bus(osh)
7191 +#define OSL_PCI_SLOT(osh) osl_pci_slot(osh)
7192 +extern uint osl_pci_bus(osl_t *osh);
7193 +extern uint osl_pci_slot(osl_t *osh);
7194 +
7195 +/* OSL initialization */
7196 +extern osl_t *osl_attach(void *pdev);
7197 +extern void osl_detach(osl_t *osh);
7198 +
7199 +/* host/bus architecture-specific byte swap */
7200 +#define BUS_SWAP32(v) (v)
7201 +
7202 +/* general purpose memory allocation */
7203 +
7204 +#define MALLOC(osh, size) kmalloc(size, GFP_ATOMIC)
7205 +#define MFREE(osh, addr, size) kfree(addr);
7206 +
7207 +#define MALLOC_FAILED(osh) osl_malloc_failed((osh))
7208 +
7209 +extern void *osl_malloc(osl_t *osh, uint size);
7210 +extern void osl_mfree(osl_t *osh, void *addr, uint size);
7211 +extern uint osl_malloced(osl_t *osh);
7212 +extern uint osl_malloc_failed(osl_t *osh);
7213 +
7214 +/* allocate/free shared (dma-able) consistent memory */
7215 +#define DMA_CONSISTENT_ALIGN PAGE_SIZE
7216 +#define DMA_ALLOC_CONSISTENT(osh, size, pap) \
7217 + osl_dma_alloc_consistent((osh), (size), (pap))
7218 +#define DMA_FREE_CONSISTENT(osh, va, size, pa) \
7219 + osl_dma_free_consistent((osh), (void*)(va), (size), (pa))
7220 +extern void *osl_dma_alloc_consistent(osl_t *osh, uint size, ulong *pap);
7221 +extern void osl_dma_free_consistent(osl_t *osh, void *va, uint size, ulong pa);
7222 +
7223 +/* map/unmap direction */
7224 +#define DMA_TX 1
7225 +#define DMA_RX 2
7226 +
7227 +/* register access macros */
7228 +#if defined(BCMJTAG)
7229 +#include <bcmjtag.h>
7230 +#define R_REG(r) bcmjtag_read(NULL, (uint32)(r), sizeof (*(r)))
7231 +#define W_REG(r, v) bcmjtag_write(NULL, (uint32)(r), (uint32)(v), sizeof (*(r)))
7232 +#endif
7233 +
7234 +/*
7235 + * BINOSL selects the slightly slower function-call-based binary compatible osl.
7236 + * Macros expand to calls to functions defined in linux_osl.c .
7237 + */
7238 +#ifndef BINOSL
7239 +
7240 +/* string library, kernel mode */
7241 +#define printf(fmt, args...) printk(fmt, ## args)
7242 +#include <linux/kernel.h>
7243 +#include <linux/string.h>
7244 +
7245 +/* register access macros */
7246 +#if !defined(BCMJTAG)
7247 +#ifndef IL_BIGENDIAN
7248 +#define R_REG(r) ( \
7249 + sizeof(*(r)) == sizeof(uint8) ? readb((volatile uint8*)(r)) : \
7250 + sizeof(*(r)) == sizeof(uint16) ? readw((volatile uint16*)(r)) : \
7251 + readl((volatile uint32*)(r)) \
7252 +)
7253 +#define W_REG(r, v) do { \
7254 + switch (sizeof(*(r))) { \
7255 + case sizeof(uint8): writeb((uint8)(v), (volatile uint8*)(r)); break; \
7256 + case sizeof(uint16): writew((uint16)(v), (volatile uint16*)(r)); break; \
7257 + case sizeof(uint32): writel((uint32)(v), (volatile uint32*)(r)); break; \
7258 + } \
7259 +} while (0)
7260 +#else /* IL_BIGENDIAN */
7261 +#define R_REG(r) ({ \
7262 + __typeof(*(r)) __osl_v; \
7263 + switch (sizeof(*(r))) { \
7264 + case sizeof(uint8): __osl_v = readb((volatile uint8*)((uint32)r^3)); break; \
7265 + case sizeof(uint16): __osl_v = readw((volatile uint16*)((uint32)r^2)); break; \
7266 + case sizeof(uint32): __osl_v = readl((volatile uint32*)(r)); break; \
7267 + } \
7268 + __osl_v; \
7269 +})
7270 +#define W_REG(r, v) do { \
7271 + switch (sizeof(*(r))) { \
7272 + case sizeof(uint8): writeb((uint8)(v), (volatile uint8*)((uint32)r^3)); break; \
7273 + case sizeof(uint16): writew((uint16)(v), (volatile uint16*)((uint32)r^2)); break; \
7274 + case sizeof(uint32): writel((uint32)(v), (volatile uint32*)(r)); break; \
7275 + } \
7276 +} while (0)
7277 +#endif
7278 +#endif
7279 +
7280 +#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
7281 +#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
7282 +
7283 +/* bcopy, bcmp, and bzero */
7284 +#define bcopy(src, dst, len) memcpy((dst), (src), (len))
7285 +#define bcmp(b1, b2, len) memcmp((b1), (b2), (len))
7286 +#define bzero(b, len) memset((b), '\0', (len))
7287 +
7288 +/* uncached virtual address */
7289 +#ifdef mips
7290 +#define OSL_UNCACHED(va) KSEG1ADDR((va))
7291 +#include <asm/addrspace.h>
7292 +#else
7293 +#define OSL_UNCACHED(va) (va)
7294 +#endif
7295 +
7296 +/* get processor cycle count */
7297 +#if defined(mips)
7298 +#define OSL_GETCYCLES(x) ((x) = read_c0_count() * 2)
7299 +#elif defined(__i386__)
7300 +#define OSL_GETCYCLES(x) rdtscl((x))
7301 +#else
7302 +#define OSL_GETCYCLES(x) ((x) = 0)
7303 +#endif
7304 +
7305 +/* dereference an address that may cause a bus exception */
7306 +#ifdef mips
7307 +#if defined(MODULE) && (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,17))
7308 +#define BUSPROBE(val, addr) panic("get_dbe() will not fixup a bus exception when compiled into a module")
7309 +#else
7310 +#define BUSPROBE(val, addr) get_dbe((val), (addr))
7311 +#include <asm/paccess.h>
7312 +#endif
7313 +#else
7314 +#define BUSPROBE(val, addr) ({ (val) = R_REG((addr)); 0; })
7315 +#endif
7316 +
7317 +/* map/unmap physical to virtual I/O */
7318 +#define REG_MAP(pa, size) ioremap_nocache((unsigned long)(pa), (unsigned long)(size))
7319 +#define REG_UNMAP(va) iounmap((void *)(va))
7320 +
7321 +/* shared (dma-able) memory access macros */
7322 +#define R_SM(r) *(r)
7323 +#define W_SM(r, v) (*(r) = (v))
7324 +#define BZERO_SM(r, len) memset((r), '\0', (len))
7325 +
7326 +/* packet primitives */
7327 +#define PKTGET(osh, len, send) osl_pktget((osh), (len), (send))
7328 +#define PKTFREE(osh, skb, send) osl_pktfree((skb))
7329 +#define PKTDATA(osh, skb) (((struct sk_buff*)(skb))->data)
7330 +#define PKTLEN(osh, skb) (((struct sk_buff*)(skb))->len)
7331 +#define PKTHEADROOM(osh, skb) (PKTDATA(osh,skb)-(((struct sk_buff*)(skb))->head))
7332 +#define PKTTAILROOM(osh, skb) ((((struct sk_buff*)(skb))->end)-(((struct sk_buff*)(skb))->tail))
7333 +#define PKTNEXT(osh, skb) (((struct sk_buff*)(skb))->next)
7334 +#define PKTSETNEXT(skb, x) (((struct sk_buff*)(skb))->next = (struct sk_buff*)(x))
7335 +#define PKTSETLEN(osh, skb, len) __skb_trim((struct sk_buff*)(skb), (len))
7336 +#define PKTPUSH(osh, skb, bytes) skb_push((struct sk_buff*)(skb), (bytes))
7337 +#define PKTPULL(osh, skb, bytes) skb_pull((struct sk_buff*)(skb), (bytes))
7338 +#define PKTDUP(osh, skb) skb_clone((struct sk_buff*)(skb), GFP_ATOMIC)
7339 +#define PKTCOOKIE(skb) ((void*)((struct sk_buff*)(skb))->csum)
7340 +#define PKTSETCOOKIE(skb, x) (((struct sk_buff*)(skb))->csum = (uint)(x))
7341 +#define PKTLINK(skb) (((struct sk_buff*)(skb))->prev)
7342 +#define PKTSETLINK(skb, x) (((struct sk_buff*)(skb))->prev = (struct sk_buff*)(x))
7343 +#define PKTPRIO(skb) (((struct sk_buff*)(skb))->priority)
7344 +#define PKTSETPRIO(skb, x) (((struct sk_buff*)(skb))->priority = (x))
7345 +extern void *osl_pktget(osl_t *osh, uint len, bool send);
7346 +extern void osl_pktfree(void *skb);
7347 +
7348 +#else /* BINOSL */
7349 +
7350 +/* string library */
7351 +#ifndef LINUX_OSL
7352 +#undef printf
7353 +#define printf(fmt, args...) osl_printf((fmt), ## args)
7354 +#undef sprintf
7355 +#define sprintf(buf, fmt, args...) osl_sprintf((buf), (fmt), ## args)
7356 +#undef strcmp
7357 +#define strcmp(s1, s2) osl_strcmp((s1), (s2))
7358 +#undef strncmp
7359 +#define strncmp(s1, s2, n) osl_strncmp((s1), (s2), (n))
7360 +#undef strlen
7361 +#define strlen(s) osl_strlen((s))
7362 +#undef strcpy
7363 +#define strcpy(d, s) osl_strcpy((d), (s))
7364 +#undef strncpy
7365 +#define strncpy(d, s, n) osl_strncpy((d), (s), (n))
7366 +#endif
7367 +extern int osl_printf(const char *format, ...);
7368 +extern int osl_sprintf(char *buf, const char *format, ...);
7369 +extern int osl_strcmp(const char *s1, const char *s2);
7370 +extern int osl_strncmp(const char *s1, const char *s2, uint n);
7371 +extern int osl_strlen(const char *s);
7372 +extern char* osl_strcpy(char *d, const char *s);
7373 +extern char* osl_strncpy(char *d, const char *s, uint n);
7374 +
7375 +/* register access macros */
7376 +#if !defined(BCMJTAG)
7377 +#define R_REG(r) ( \
7378 + sizeof(*(r)) == sizeof(uint8) ? osl_readb((volatile uint8*)(r)) : \
7379 + sizeof(*(r)) == sizeof(uint16) ? osl_readw((volatile uint16*)(r)) : \
7380 + osl_readl((volatile uint32*)(r)) \
7381 +)
7382 +#define W_REG(r, v) do { \
7383 + switch (sizeof(*(r))) { \
7384 + case sizeof(uint8): osl_writeb((uint8)(v), (volatile uint8*)(r)); break; \
7385 + case sizeof(uint16): osl_writew((uint16)(v), (volatile uint16*)(r)); break; \
7386 + case sizeof(uint32): osl_writel((uint32)(v), (volatile uint32*)(r)); break; \
7387 + } \
7388 +} while (0)
7389 +#endif
7390 +
7391 +#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
7392 +#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
7393 +extern uint8 osl_readb(volatile uint8 *r);
7394 +extern uint16 osl_readw(volatile uint16 *r);
7395 +extern uint32 osl_readl(volatile uint32 *r);
7396 +extern void osl_writeb(uint8 v, volatile uint8 *r);
7397 +extern void osl_writew(uint16 v, volatile uint16 *r);
7398 +extern void osl_writel(uint32 v, volatile uint32 *r);
7399 +
7400 +/* bcopy, bcmp, and bzero */
7401 +extern void bcopy(const void *src, void *dst, int len);
7402 +extern int bcmp(const void *b1, const void *b2, int len);
7403 +extern void bzero(void *b, int len);
7404 +
7405 +/* uncached virtual address */
7406 +#define OSL_UNCACHED(va) osl_uncached((va))
7407 +extern void *osl_uncached(void *va);
7408 +
7409 +/* get processor cycle count */
7410 +#define OSL_GETCYCLES(x) ((x) = osl_getcycles())
7411 +extern uint osl_getcycles(void);
7412 +
7413 +/* dereference an address that may target abort */
7414 +#define BUSPROBE(val, addr) osl_busprobe(&(val), (addr))
7415 +extern int osl_busprobe(uint32 *val, uint32 addr);
7416 +
7417 +/* map/unmap physical to virtual */
7418 +#define REG_MAP(pa, size) osl_reg_map((pa), (size))
7419 +#define REG_UNMAP(va) osl_reg_unmap((va))
7420 +extern void *osl_reg_map(uint32 pa, uint size);
7421 +extern void osl_reg_unmap(void *va);
7422 +
7423 +/* shared (dma-able) memory access macros */
7424 +#define R_SM(r) *(r)
7425 +#define W_SM(r, v) (*(r) = (v))
7426 +#define BZERO_SM(r, len) bzero((r), (len))
7427 +
7428 +/* packet primitives */
7429 +#define PKTGET(osh, len, send) osl_pktget((osh), (len), (send))
7430 +#define PKTFREE(osh, skb, send) osl_pktfree((skb))
7431 +#define PKTDATA(osh, skb) osl_pktdata((osh), (skb))
7432 +#define PKTLEN(osh, skb) osl_pktlen((osh), (skb))
7433 +#define PKTHEADROOM(osh, skb) osl_pktheadroom((osh), (skb))
7434 +#define PKTTAILROOM(osh, skb) osl_pkttailroom((osh), (skb))
7435 +#define PKTNEXT(osh, skb) osl_pktnext((osh), (skb))
7436 +#define PKTSETNEXT(skb, x) osl_pktsetnext((skb), (x))
7437 +#define PKTSETLEN(osh, skb, len) osl_pktsetlen((osh), (skb), (len))
7438 +#define PKTPUSH(osh, skb, bytes) osl_pktpush((osh), (skb), (bytes))
7439 +#define PKTPULL(osh, skb, bytes) osl_pktpull((osh), (skb), (bytes))
7440 +#define PKTDUP(osh, skb) osl_pktdup((osh), (skb))
7441 +#define PKTCOOKIE(skb) osl_pktcookie((skb))
7442 +#define PKTSETCOOKIE(skb, x) osl_pktsetcookie((skb), (x))
7443 +#define PKTLINK(skb) osl_pktlink((skb))
7444 +#define PKTSETLINK(skb, x) osl_pktsetlink((skb), (x))
7445 +#define PKTPRIO(skb) osl_pktprio((skb))
7446 +#define PKTSETPRIO(skb, x) osl_pktsetprio((skb), (x))
7447 +extern void *osl_pktget(osl_t *osh, uint len, bool send);
7448 +extern void osl_pktfree(void *skb);
7449 +extern uchar *osl_pktdata(osl_t *osh, void *skb);
7450 +extern uint osl_pktlen(osl_t *osh, void *skb);
7451 +extern uint osl_pktheadroom(osl_t *osh, void *skb);
7452 +extern uint osl_pkttailroom(osl_t *osh, void *skb);
7453 +extern void *osl_pktnext(osl_t *osh, void *skb);
7454 +extern void osl_pktsetnext(void *skb, void *x);
7455 +extern void osl_pktsetlen(osl_t *osh, void *skb, uint len);
7456 +extern uchar *osl_pktpush(osl_t *osh, void *skb, int bytes);
7457 +extern uchar *osl_pktpull(osl_t *osh, void *skb, int bytes);
7458 +extern void *osl_pktdup(osl_t *osh, void *skb);
7459 +extern void *osl_pktcookie(void *skb);
7460 +extern void osl_pktsetcookie(void *skb, void *x);
7461 +extern void *osl_pktlink(void *skb);
7462 +extern void osl_pktsetlink(void *skb, void *x);
7463 +extern uint osl_pktprio(void *skb);
7464 +extern void osl_pktsetprio(void *skb, uint x);
7465 +
7466 +#endif /* BINOSL */
7467 +
7468 +#define OSL_ERROR(bcmerror) osl_error(bcmerror)
7469 +extern int osl_error(int bcmerror);
7470 +
7471 +/* the largest reasonable packet buffer driver uses for ethernet MTU in bytes */
7472 +#define PKTBUFSZ 2048
7473 +
7474 +#endif /* _linux_osl_h_ */
7475 diff -urN linux.old/arch/mips/bcm947xx/include/linuxver.h linux.dev/arch/mips/bcm947xx/include/linuxver.h
7476 --- linux.old/arch/mips/bcm947xx/include/linuxver.h 1970-01-01 01:00:00.000000000 +0100
7477 +++ linux.dev/arch/mips/bcm947xx/include/linuxver.h 2005-12-28 16:37:32.878261500 +0100
7478 @@ -0,0 +1,389 @@
7479 +/*
7480 + * Linux-specific abstractions to gain some independence from linux kernel versions.
7481 + * Pave over some 2.2 versus 2.4 versus 2.6 kernel differences.
7482 + *
7483 + * Copyright 2005, Broadcom Corporation
7484 + * All Rights Reserved.
7485 + *
7486 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7487 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7488 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7489 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7490 + *
7491 + * $Id$
7492 + */
7493 +
7494 +#ifndef _linuxver_h_
7495 +#define _linuxver_h_
7496 +
7497 +#include <linux/config.h>
7498 +#include <linux/version.h>
7499 +
7500 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,0))
7501 +/* __NO_VERSION__ must be defined for all linkables except one in 2.2 */
7502 +#ifdef __UNDEF_NO_VERSION__
7503 +#undef __NO_VERSION__
7504 +#else
7505 +#define __NO_VERSION__
7506 +#endif
7507 +#endif
7508 +
7509 +#if defined(MODULE) && defined(MODVERSIONS)
7510 +#include <linux/modversions.h>
7511 +#endif
7512 +
7513 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0)
7514 +#include <linux/moduleparam.h>
7515 +#endif
7516 +
7517 +
7518 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
7519 +#define module_param(_name_, _type_, _perm_) MODULE_PARM(_name_, "i")
7520 +#define module_param_string(_name_, _string_, _size_, _perm_) MODULE_PARM(_string_, "c" __MODULE_STRING(_size_))
7521 +#endif
7522 +
7523 +/* linux/malloc.h is deprecated, use linux/slab.h instead. */
7524 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,9))
7525 +#include <linux/malloc.h>
7526 +#else
7527 +#include <linux/slab.h>
7528 +#endif
7529 +
7530 +#include <linux/types.h>
7531 +#include <linux/init.h>
7532 +#include <linux/mm.h>
7533 +#include <linux/string.h>
7534 +#include <linux/pci.h>
7535 +#include <linux/interrupt.h>
7536 +#include <linux/netdevice.h>
7537 +#include <asm/io.h>
7538 +
7539 +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,41))
7540 +#include <linux/workqueue.h>
7541 +#else
7542 +#include <linux/tqueue.h>
7543 +#ifndef work_struct
7544 +#define work_struct tq_struct
7545 +#endif
7546 +#ifndef INIT_WORK
7547 +#define INIT_WORK(_work, _func, _data) INIT_TQUEUE((_work), (_func), (_data))
7548 +#endif
7549 +#ifndef schedule_work
7550 +#define schedule_work(_work) schedule_task((_work))
7551 +#endif
7552 +#ifndef flush_scheduled_work
7553 +#define flush_scheduled_work() flush_scheduled_tasks()
7554 +#endif
7555 +#endif
7556 +
7557 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0))
7558 +/* Some distributions have their own 2.6.x compatibility layers */
7559 +#ifndef IRQ_NONE
7560 +typedef void irqreturn_t;
7561 +#define IRQ_NONE
7562 +#define IRQ_HANDLED
7563 +#define IRQ_RETVAL(x)
7564 +#endif
7565 +#else
7566 +typedef irqreturn_t (*FN_ISR) (int irq, void *dev_id, struct pt_regs *ptregs);
7567 +#endif
7568 +
7569 +#ifndef __exit
7570 +#define __exit
7571 +#endif
7572 +#ifndef __devexit
7573 +#define __devexit
7574 +#endif
7575 +#ifndef __devinit
7576 +#define __devinit __init
7577 +#endif
7578 +#ifndef __devinitdata
7579 +#define __devinitdata
7580 +#endif
7581 +#ifndef __devexit_p
7582 +#define __devexit_p(x) x
7583 +#endif
7584 +
7585 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,0))
7586 +
7587 +#define pci_get_drvdata(dev) (dev)->sysdata
7588 +#define pci_set_drvdata(dev, value) (dev)->sysdata=(value)
7589 +
7590 +/*
7591 + * New-style (2.4.x) PCI/hot-pluggable PCI/CardBus registration
7592 + */
7593 +
7594 +struct pci_device_id {
7595 + unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
7596 + unsigned int subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */
7597 + unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */
7598 + unsigned long driver_data; /* Data private to the driver */
7599 +};
7600 +
7601 +struct pci_driver {
7602 + struct list_head node;
7603 + char *name;
7604 + const struct pci_device_id *id_table; /* NULL if wants all devices */
7605 + int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
7606 + void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
7607 + void (*suspend)(struct pci_dev *dev); /* Device suspended */
7608 + void (*resume)(struct pci_dev *dev); /* Device woken up */
7609 +};
7610 +
7611 +#define MODULE_DEVICE_TABLE(type, name)
7612 +#define PCI_ANY_ID (~0)
7613 +
7614 +/* compatpci.c */
7615 +#define pci_module_init pci_register_driver
7616 +extern int pci_register_driver(struct pci_driver *drv);
7617 +extern void pci_unregister_driver(struct pci_driver *drv);
7618 +
7619 +#endif /* PCI registration */
7620 +
7621 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,2,18))
7622 +#ifdef MODULE
7623 +#define module_init(x) int init_module(void) { return x(); }
7624 +#define module_exit(x) void cleanup_module(void) { x(); }
7625 +#else
7626 +#define module_init(x) __initcall(x);
7627 +#define module_exit(x) __exitcall(x);
7628 +#endif
7629 +#endif
7630 +
7631 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,48))
7632 +#define list_for_each(pos, head) \
7633 + for (pos = (head)->next; pos != (head); pos = pos->next)
7634 +#endif
7635 +
7636 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,13))
7637 +#define pci_resource_start(dev, bar) ((dev)->base_address[(bar)])
7638 +#elif (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,44))
7639 +#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
7640 +#endif
7641 +
7642 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,23))
7643 +#define pci_enable_device(dev) do { } while (0)
7644 +#endif
7645 +
7646 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,14))
7647 +#define net_device device
7648 +#endif
7649 +
7650 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,42))
7651 +
7652 +/*
7653 + * DMA mapping
7654 + *
7655 + * See linux/Documentation/DMA-mapping.txt
7656 + */
7657 +
7658 +#ifndef PCI_DMA_TODEVICE
7659 +#define PCI_DMA_TODEVICE 1
7660 +#define PCI_DMA_FROMDEVICE 2
7661 +#endif
7662 +
7663 +typedef u32 dma_addr_t;
7664 +
7665 +/* Pure 2^n version of get_order */
7666 +static inline int get_order(unsigned long size)
7667 +{
7668 + int order;
7669 +
7670 + size = (size-1) >> (PAGE_SHIFT-1);
7671 + order = -1;
7672 + do {
7673 + size >>= 1;
7674 + order++;
7675 + } while (size);
7676 + return order;
7677 +}
7678 +
7679 +static inline void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size,
7680 + dma_addr_t *dma_handle)
7681 +{
7682 + void *ret;
7683 + int gfp = GFP_ATOMIC | GFP_DMA;
7684 +
7685 + ret = (void *)__get_free_pages(gfp, get_order(size));
7686 +
7687 + if (ret != NULL) {
7688 + memset(ret, 0, size);
7689 + *dma_handle = virt_to_bus(ret);
7690 + }
7691 + return ret;
7692 +}
7693 +static inline void pci_free_consistent(struct pci_dev *hwdev, size_t size,
7694 + void *vaddr, dma_addr_t dma_handle)
7695 +{
7696 + free_pages((unsigned long)vaddr, get_order(size));
7697 +}
7698 +#ifdef ILSIM
7699 +extern uint pci_map_single(void *dev, void *va, uint size, int direction);
7700 +extern void pci_unmap_single(void *dev, uint pa, uint size, int direction);
7701 +#else
7702 +#define pci_map_single(cookie, address, size, dir) virt_to_bus(address)
7703 +#define pci_unmap_single(cookie, address, size, dir)
7704 +#endif
7705 +
7706 +#endif /* DMA mapping */
7707 +
7708 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,43))
7709 +
7710 +#define dev_kfree_skb_any(a) dev_kfree_skb(a)
7711 +#define netif_down(dev) do { (dev)->start = 0; } while(0)
7712 +
7713 +/* pcmcia-cs provides its own netdevice compatibility layer */
7714 +#ifndef _COMPAT_NETDEVICE_H
7715 +
7716 +/*
7717 + * SoftNet
7718 + *
7719 + * For pre-softnet kernels we need to tell the upper layer not to
7720 + * re-enter start_xmit() while we are in there. However softnet
7721 + * guarantees not to enter while we are in there so there is no need
7722 + * to do the netif_stop_queue() dance unless the transmit queue really
7723 + * gets stuck. This should also improve performance according to tests
7724 + * done by Aman Singla.
7725 + */
7726 +
7727 +#define dev_kfree_skb_irq(a) dev_kfree_skb(a)
7728 +#define netif_wake_queue(dev) do { clear_bit(0, &(dev)->tbusy); mark_bh(NET_BH); } while(0)
7729 +#define netif_stop_queue(dev) set_bit(0, &(dev)->tbusy)
7730 +
7731 +static inline void netif_start_queue(struct net_device *dev)
7732 +{
7733 + dev->tbusy = 0;
7734 + dev->interrupt = 0;
7735 + dev->start = 1;
7736 +}
7737 +
7738 +#define netif_queue_stopped(dev) (dev)->tbusy
7739 +#define netif_running(dev) (dev)->start
7740 +
7741 +#endif /* _COMPAT_NETDEVICE_H */
7742 +
7743 +#define netif_device_attach(dev) netif_start_queue(dev)
7744 +#define netif_device_detach(dev) netif_stop_queue(dev)
7745 +
7746 +/* 2.4.x renamed bottom halves to tasklets */
7747 +#define tasklet_struct tq_struct
7748 +static inline void tasklet_schedule(struct tasklet_struct *tasklet)
7749 +{
7750 + queue_task(tasklet, &tq_immediate);
7751 + mark_bh(IMMEDIATE_BH);
7752 +}
7753 +
7754 +static inline void tasklet_init(struct tasklet_struct *tasklet,
7755 + void (*func)(unsigned long),
7756 + unsigned long data)
7757 +{
7758 + tasklet->next = NULL;
7759 + tasklet->sync = 0;
7760 + tasklet->routine = (void (*)(void *))func;
7761 + tasklet->data = (void *)data;
7762 +}
7763 +#define tasklet_kill(tasklet) {do{} while(0);}
7764 +
7765 +/* 2.4.x introduced del_timer_sync() */
7766 +#define del_timer_sync(timer) del_timer(timer)
7767 +
7768 +#else
7769 +
7770 +#define netif_down(dev)
7771 +
7772 +#endif /* SoftNet */
7773 +
7774 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,3))
7775 +
7776 +/*
7777 + * Emit code to initialise a tq_struct's routine and data pointers
7778 + */
7779 +#define PREPARE_TQUEUE(_tq, _routine, _data) \
7780 + do { \
7781 + (_tq)->routine = _routine; \
7782 + (_tq)->data = _data; \
7783 + } while (0)
7784 +
7785 +/*
7786 + * Emit code to initialise all of a tq_struct
7787 + */
7788 +#define INIT_TQUEUE(_tq, _routine, _data) \
7789 + do { \
7790 + INIT_LIST_HEAD(&(_tq)->list); \
7791 + (_tq)->sync = 0; \
7792 + PREPARE_TQUEUE((_tq), (_routine), (_data)); \
7793 + } while (0)
7794 +
7795 +#endif
7796 +
7797 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,6))
7798 +
7799 +/* Power management related routines */
7800 +
7801 +static inline int
7802 +pci_save_state(struct pci_dev *dev, u32 *buffer)
7803 +{
7804 + int i;
7805 + if (buffer) {
7806 + for (i = 0; i < 16; i++)
7807 + pci_read_config_dword(dev, i * 4,&buffer[i]);
7808 + }
7809 + return 0;
7810 +}
7811 +
7812 +static inline int
7813 +pci_restore_state(struct pci_dev *dev, u32 *buffer)
7814 +{
7815 + int i;
7816 +
7817 + if (buffer) {
7818 + for (i = 0; i < 16; i++)
7819 + pci_write_config_dword(dev,i * 4, buffer[i]);
7820 + }
7821 + /*
7822 + * otherwise, write the context information we know from bootup.
7823 + * This works around a problem where warm-booting from Windows
7824 + * combined with a D3(hot)->D0 transition causes PCI config
7825 + * header data to be forgotten.
7826 + */
7827 + else {
7828 + for (i = 0; i < 6; i ++)
7829 + pci_write_config_dword(dev,
7830 + PCI_BASE_ADDRESS_0 + (i * 4),
7831 + pci_resource_start(dev, i));
7832 + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
7833 + }
7834 + return 0;
7835 +}
7836 +
7837 +#endif /* PCI power management */
7838 +
7839 +/* Old cp0 access macros deprecated in 2.4.19 */
7840 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,19))
7841 +#define read_c0_count() read_32bit_cp0_register(CP0_COUNT)
7842 +#endif
7843 +
7844 +/* Module refcount handled internally in 2.6.x */
7845 +#ifndef SET_MODULE_OWNER
7846 +#define SET_MODULE_OWNER(dev) do {} while (0)
7847 +#define OLD_MOD_INC_USE_COUNT MOD_INC_USE_COUNT
7848 +#define OLD_MOD_DEC_USE_COUNT MOD_DEC_USE_COUNT
7849 +#else
7850 +#define OLD_MOD_INC_USE_COUNT do {} while (0)
7851 +#define OLD_MOD_DEC_USE_COUNT do {} while (0)
7852 +#endif
7853 +
7854 +#ifndef SET_NETDEV_DEV
7855 +#define SET_NETDEV_DEV(net, pdev) do {} while (0)
7856 +#endif
7857 +
7858 +#ifndef HAVE_FREE_NETDEV
7859 +#define free_netdev(dev) kfree(dev)
7860 +#endif
7861 +
7862 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0))
7863 +/* struct packet_type redefined in 2.6.x */
7864 +#define af_packet_priv data
7865 +#endif
7866 +
7867 +#endif /* _linuxver_h_ */
7868 diff -urN linux.old/arch/mips/bcm947xx/include/mipsinc.h linux.dev/arch/mips/bcm947xx/include/mipsinc.h
7869 --- linux.old/arch/mips/bcm947xx/include/mipsinc.h 1970-01-01 01:00:00.000000000 +0100
7870 +++ linux.dev/arch/mips/bcm947xx/include/mipsinc.h 2005-12-28 16:37:32.878261500 +0100
7871 @@ -0,0 +1,552 @@
7872 +/*
7873 + * HND Run Time Environment for standalone MIPS programs.
7874 + *
7875 + * Copyright 2005, Broadcom Corporation
7876 + * All Rights Reserved.
7877 + *
7878 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7879 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7880 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7881 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7882 + *
7883 + * $Id$
7884 + */
7885 +
7886 +#ifndef _MISPINC_H
7887 +#define _MISPINC_H
7888 +
7889 +
7890 +/* MIPS defines */
7891 +
7892 +#ifdef _LANGUAGE_ASSEMBLY
7893 +
7894 +/*
7895 + * Symbolic register names for 32 bit ABI
7896 + */
7897 +#define zero $0 /* wired zero */
7898 +#define AT $1 /* assembler temp - uppercase because of ".set at" */
7899 +#define v0 $2 /* return value */
7900 +#define v1 $3
7901 +#define a0 $4 /* argument registers */
7902 +#define a1 $5
7903 +#define a2 $6
7904 +#define a3 $7
7905 +#define t0 $8 /* caller saved */
7906 +#define t1 $9
7907 +#define t2 $10
7908 +#define t3 $11
7909 +#define t4 $12
7910 +#define t5 $13
7911 +#define t6 $14
7912 +#define t7 $15
7913 +#define s0 $16 /* callee saved */
7914 +#define s1 $17
7915 +#define s2 $18
7916 +#define s3 $19
7917 +#define s4 $20
7918 +#define s5 $21
7919 +#define s6 $22
7920 +#define s7 $23
7921 +#define t8 $24 /* caller saved */
7922 +#define t9 $25
7923 +#define jp $25 /* PIC jump register */
7924 +#define k0 $26 /* kernel scratch */
7925 +#define k1 $27
7926 +#define gp $28 /* global pointer */
7927 +#define sp $29 /* stack pointer */
7928 +#define fp $30 /* frame pointer */
7929 +#define s8 $30 /* same like fp! */
7930 +#define ra $31 /* return address */
7931 +
7932 +
7933 +/*
7934 + * CP0 Registers
7935 + */
7936 +
7937 +#define C0_INX $0
7938 +#define C0_RAND $1
7939 +#define C0_TLBLO0 $2
7940 +#define C0_TLBLO C0_TLBLO0
7941 +#define C0_TLBLO1 $3
7942 +#define C0_CTEXT $4
7943 +#define C0_PGMASK $5
7944 +#define C0_WIRED $6
7945 +#define C0_BADVADDR $8
7946 +#define C0_COUNT $9
7947 +#define C0_TLBHI $10
7948 +#define C0_COMPARE $11
7949 +#define C0_SR $12
7950 +#define C0_STATUS C0_SR
7951 +#define C0_CAUSE $13
7952 +#define C0_EPC $14
7953 +#define C0_PRID $15
7954 +#define C0_CONFIG $16
7955 +#define C0_LLADDR $17
7956 +#define C0_WATCHLO $18
7957 +#define C0_WATCHHI $19
7958 +#define C0_XCTEXT $20
7959 +#define C0_DIAGNOSTIC $22
7960 +#define C0_BROADCOM C0_DIAGNOSTIC
7961 +#define C0_PERFORMANCE $25
7962 +#define C0_ECC $26
7963 +#define C0_CACHEERR $27
7964 +#define C0_TAGLO $28
7965 +#define C0_TAGHI $29
7966 +#define C0_ERREPC $30
7967 +#define C0_DESAVE $31
7968 +
7969 +/*
7970 + * LEAF - declare leaf routine
7971 + */
7972 +#define LEAF(symbol) \
7973 + .globl symbol; \
7974 + .align 2; \
7975 + .type symbol,@function; \
7976 + .ent symbol,0; \
7977 +symbol: .frame sp,0,ra
7978 +
7979 +/*
7980 + * END - mark end of function
7981 + */
7982 +#define END(function) \
7983 + .end function; \
7984 + .size function,.-function
7985 +
7986 +#define _ULCAST_
7987 +
7988 +#else
7989 +
7990 +/*
7991 + * The following macros are especially useful for __asm__
7992 + * inline assembler.
7993 + */
7994 +#ifndef __STR
7995 +#define __STR(x) #x
7996 +#endif
7997 +#ifndef STR
7998 +#define STR(x) __STR(x)
7999 +#endif
8000 +
8001 +#define _ULCAST_ (unsigned long)
8002 +
8003 +
8004 +/*
8005 + * CP0 Registers
8006 + */
8007 +
8008 +#define C0_INX 0 /* CP0: TLB Index */
8009 +#define C0_RAND 1 /* CP0: TLB Random */
8010 +#define C0_TLBLO0 2 /* CP0: TLB EntryLo0 */
8011 +#define C0_TLBLO C0_TLBLO0 /* CP0: TLB EntryLo0 */
8012 +#define C0_TLBLO1 3 /* CP0: TLB EntryLo1 */
8013 +#define C0_CTEXT 4 /* CP0: Context */
8014 +#define C0_PGMASK 5 /* CP0: TLB PageMask */
8015 +#define C0_WIRED 6 /* CP0: TLB Wired */
8016 +#define C0_BADVADDR 8 /* CP0: Bad Virtual Address */
8017 +#define C0_COUNT 9 /* CP0: Count */
8018 +#define C0_TLBHI 10 /* CP0: TLB EntryHi */
8019 +#define C0_COMPARE 11 /* CP0: Compare */
8020 +#define C0_SR 12 /* CP0: Processor Status */
8021 +#define C0_STATUS C0_SR /* CP0: Processor Status */
8022 +#define C0_CAUSE 13 /* CP0: Exception Cause */
8023 +#define C0_EPC 14 /* CP0: Exception PC */
8024 +#define C0_PRID 15 /* CP0: Processor Revision Indentifier */
8025 +#define C0_CONFIG 16 /* CP0: Config */
8026 +#define C0_LLADDR 17 /* CP0: LLAddr */
8027 +#define C0_WATCHLO 18 /* CP0: WatchpointLo */
8028 +#define C0_WATCHHI 19 /* CP0: WatchpointHi */
8029 +#define C0_XCTEXT 20 /* CP0: XContext */
8030 +#define C0_DIAGNOSTIC 22 /* CP0: Diagnostic */
8031 +#define C0_BROADCOM C0_DIAGNOSTIC /* CP0: Broadcom Register */
8032 +#define C0_PERFORMANCE 25 /* CP0: Performance Counter/Control Registers */
8033 +#define C0_ECC 26 /* CP0: ECC */
8034 +#define C0_CACHEERR 27 /* CP0: CacheErr */
8035 +#define C0_TAGLO 28 /* CP0: TagLo */
8036 +#define C0_TAGHI 29 /* CP0: TagHi */
8037 +#define C0_ERREPC 30 /* CP0: ErrorEPC */
8038 +#define C0_DESAVE 31 /* CP0: DebugSave */
8039 +
8040 +#endif /* _LANGUAGE_ASSEMBLY */
8041 +
8042 +/*
8043 + * Memory segments (32bit kernel mode addresses)
8044 + */
8045 +#undef KUSEG
8046 +#undef KSEG0
8047 +#undef KSEG1
8048 +#undef KSEG2
8049 +#undef KSEG3
8050 +#define KUSEG 0x00000000
8051 +#define KSEG0 0x80000000
8052 +#define KSEG1 0xa0000000
8053 +#define KSEG2 0xc0000000
8054 +#define KSEG3 0xe0000000
8055 +#define PHYSADDR_MASK 0x1fffffff
8056 +
8057 +/*
8058 + * Map an address to a certain kernel segment
8059 + */
8060 +#undef PHYSADDR
8061 +#undef KSEG0ADDR
8062 +#undef KSEG1ADDR
8063 +#undef KSEG2ADDR
8064 +#undef KSEG3ADDR
8065 +
8066 +#define PHYSADDR(a) (_ULCAST_(a) & PHYSADDR_MASK)
8067 +#define KSEG0ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG0)
8068 +#define KSEG1ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG1)
8069 +#define KSEG2ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG2)
8070 +#define KSEG3ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG3)
8071 +
8072 +
8073 +#ifndef Index_Invalidate_I
8074 +/*
8075 + * Cache Operations
8076 + */
8077 +#define Index_Invalidate_I 0x00
8078 +#define Index_Writeback_Inv_D 0x01
8079 +#define Index_Invalidate_SI 0x02
8080 +#define Index_Writeback_Inv_SD 0x03
8081 +#define Index_Load_Tag_I 0x04
8082 +#define Index_Load_Tag_D 0x05
8083 +#define Index_Load_Tag_SI 0x06
8084 +#define Index_Load_Tag_SD 0x07
8085 +#define Index_Store_Tag_I 0x08
8086 +#define Index_Store_Tag_D 0x09
8087 +#define Index_Store_Tag_SI 0x0A
8088 +#define Index_Store_Tag_SD 0x0B
8089 +#define Create_Dirty_Excl_D 0x0d
8090 +#define Create_Dirty_Excl_SD 0x0f
8091 +#define Hit_Invalidate_I 0x10
8092 +#define Hit_Invalidate_D 0x11
8093 +#define Hit_Invalidate_SI 0x12
8094 +#define Hit_Invalidate_SD 0x13
8095 +#define Fill_I 0x14
8096 +#define Hit_Writeback_Inv_D 0x15
8097 + /* 0x16 is unused */
8098 +#define Hit_Writeback_Inv_SD 0x17
8099 +#define R5K_Page_Invalidate_S 0x17
8100 +#define Hit_Writeback_I 0x18
8101 +#define Hit_Writeback_D 0x19
8102 + /* 0x1a is unused */
8103 +#define Hit_Writeback_SD 0x1b
8104 + /* 0x1c is unused */
8105 + /* 0x1e is unused */
8106 +#define Hit_Set_Virtual_SI 0x1e
8107 +#define Hit_Set_Virtual_SD 0x1f
8108 +#endif
8109 +
8110 +
8111 +/*
8112 + * R4x00 interrupt enable / cause bits
8113 + */
8114 +#define IE_SW0 (_ULCAST_(1) << 8)
8115 +#define IE_SW1 (_ULCAST_(1) << 9)
8116 +#define IE_IRQ0 (_ULCAST_(1) << 10)
8117 +#define IE_IRQ1 (_ULCAST_(1) << 11)
8118 +#define IE_IRQ2 (_ULCAST_(1) << 12)
8119 +#define IE_IRQ3 (_ULCAST_(1) << 13)
8120 +#define IE_IRQ4 (_ULCAST_(1) << 14)
8121 +#define IE_IRQ5 (_ULCAST_(1) << 15)
8122 +
8123 +#ifndef ST0_UM
8124 +/*
8125 + * Bitfields in the mips32 cp0 status register
8126 + */
8127 +#define ST0_IE 0x00000001
8128 +#define ST0_EXL 0x00000002
8129 +#define ST0_ERL 0x00000004
8130 +#define ST0_UM 0x00000010
8131 +#define ST0_SWINT0 0x00000100
8132 +#define ST0_SWINT1 0x00000200
8133 +#define ST0_HWINT0 0x00000400
8134 +#define ST0_HWINT1 0x00000800
8135 +#define ST0_HWINT2 0x00001000
8136 +#define ST0_HWINT3 0x00002000
8137 +#define ST0_HWINT4 0x00004000
8138 +#define ST0_HWINT5 0x00008000
8139 +#define ST0_IM 0x0000ff00
8140 +#define ST0_NMI 0x00080000
8141 +#define ST0_SR 0x00100000
8142 +#define ST0_TS 0x00200000
8143 +#define ST0_BEV 0x00400000
8144 +#define ST0_RE 0x02000000
8145 +#define ST0_RP 0x08000000
8146 +#define ST0_CU 0xf0000000
8147 +#define ST0_CU0 0x10000000
8148 +#define ST0_CU1 0x20000000
8149 +#define ST0_CU2 0x40000000
8150 +#define ST0_CU3 0x80000000
8151 +#endif
8152 +
8153 +
8154 +/*
8155 + * Bitfields in the mips32 cp0 cause register
8156 + */
8157 +#define C_EXC 0x0000007c
8158 +#define C_EXC_SHIFT 2
8159 +#define C_INT 0x0000ff00
8160 +#define C_INT_SHIFT 8
8161 +#define C_SW0 (_ULCAST_(1) << 8)
8162 +#define C_SW1 (_ULCAST_(1) << 9)
8163 +#define C_IRQ0 (_ULCAST_(1) << 10)
8164 +#define C_IRQ1 (_ULCAST_(1) << 11)
8165 +#define C_IRQ2 (_ULCAST_(1) << 12)
8166 +#define C_IRQ3 (_ULCAST_(1) << 13)
8167 +#define C_IRQ4 (_ULCAST_(1) << 14)
8168 +#define C_IRQ5 (_ULCAST_(1) << 15)
8169 +#define C_WP 0x00400000
8170 +#define C_IV 0x00800000
8171 +#define C_CE 0x30000000
8172 +#define C_CE_SHIFT 28
8173 +#define C_BD 0x80000000
8174 +
8175 +/* Values in C_EXC */
8176 +#define EXC_INT 0
8177 +#define EXC_TLBM 1
8178 +#define EXC_TLBL 2
8179 +#define EXC_TLBS 3
8180 +#define EXC_AEL 4
8181 +#define EXC_AES 5
8182 +#define EXC_IBE 6
8183 +#define EXC_DBE 7
8184 +#define EXC_SYS 8
8185 +#define EXC_BPT 9
8186 +#define EXC_RI 10
8187 +#define EXC_CU 11
8188 +#define EXC_OV 12
8189 +#define EXC_TR 13
8190 +#define EXC_WATCH 23
8191 +#define EXC_MCHK 24
8192 +
8193 +
8194 +/*
8195 + * Bits in the cp0 config register.
8196 + */
8197 +#define CONF_CM_CACHABLE_NO_WA 0
8198 +#define CONF_CM_CACHABLE_WA 1
8199 +#define CONF_CM_UNCACHED 2
8200 +#define CONF_CM_CACHABLE_NONCOHERENT 3
8201 +#define CONF_CM_CACHABLE_CE 4
8202 +#define CONF_CM_CACHABLE_COW 5
8203 +#define CONF_CM_CACHABLE_CUW 6
8204 +#define CONF_CM_CACHABLE_ACCELERATED 7
8205 +#define CONF_CM_CMASK 7
8206 +#define CONF_CU (_ULCAST_(1) << 3)
8207 +#define CONF_DB (_ULCAST_(1) << 4)
8208 +#define CONF_IB (_ULCAST_(1) << 5)
8209 +#define CONF_SE (_ULCAST_(1) << 12)
8210 +#define CONF_SC (_ULCAST_(1) << 17)
8211 +#define CONF_AC (_ULCAST_(1) << 23)
8212 +#define CONF_HALT (_ULCAST_(1) << 25)
8213 +
8214 +
8215 +/*
8216 + * Bits in the cp0 config register select 1.
8217 + */
8218 +#define CONF1_FP 0x00000001 /* FPU present */
8219 +#define CONF1_EP 0x00000002 /* EJTAG present */
8220 +#define CONF1_CA 0x00000004 /* mips16 implemented */
8221 +#define CONF1_WR 0x00000008 /* Watch registers present */
8222 +#define CONF1_PC 0x00000010 /* Performance counters present */
8223 +#define CONF1_DA_SHIFT 7 /* D$ associativity */
8224 +#define CONF1_DA_MASK 0x00000380
8225 +#define CONF1_DA_BASE 1
8226 +#define CONF1_DL_SHIFT 10 /* D$ line size */
8227 +#define CONF1_DL_MASK 0x00001c00
8228 +#define CONF1_DL_BASE 2
8229 +#define CONF1_DS_SHIFT 13 /* D$ sets/way */
8230 +#define CONF1_DS_MASK 0x0000e000
8231 +#define CONF1_DS_BASE 64
8232 +#define CONF1_IA_SHIFT 16 /* I$ associativity */
8233 +#define CONF1_IA_MASK 0x00070000
8234 +#define CONF1_IA_BASE 1
8235 +#define CONF1_IL_SHIFT 19 /* I$ line size */
8236 +#define CONF1_IL_MASK 0x00380000
8237 +#define CONF1_IL_BASE 2
8238 +#define CONF1_IS_SHIFT 22 /* Instruction cache sets/way */
8239 +#define CONF1_IS_MASK 0x01c00000
8240 +#define CONF1_IS_BASE 64
8241 +#define CONF1_MS_MASK 0x7e000000 /* Number of tlb entries */
8242 +#define CONF1_MS_SHIFT 25
8243 +
8244 +/* PRID register */
8245 +#define PRID_COPT_MASK 0xff000000
8246 +#define PRID_COMP_MASK 0x00ff0000
8247 +#define PRID_IMP_MASK 0x0000ff00
8248 +#define PRID_REV_MASK 0x000000ff
8249 +
8250 +#define PRID_COMP_LEGACY 0x000000
8251 +#define PRID_COMP_MIPS 0x010000
8252 +#define PRID_COMP_BROADCOM 0x020000
8253 +#define PRID_COMP_ALCHEMY 0x030000
8254 +#define PRID_COMP_SIBYTE 0x040000
8255 +#define PRID_IMP_BCM4710 0x4000
8256 +#define PRID_IMP_BCM3302 0x9000
8257 +#define PRID_IMP_BCM3303 0x9100
8258 +
8259 +#define PRID_IMP_UNKNOWN 0xff00
8260 +
8261 +#define BCM330X(id) \
8262 + (((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3302)) \
8263 + || ((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3303)))
8264 +
8265 +/* Bits in C0_BROADCOM */
8266 +#define BRCM_PFC_AVAIL 0x20000000 /* PFC is available */
8267 +#define BRCM_DC_ENABLE 0x40000000 /* Enable Data $ */
8268 +#define BRCM_IC_ENABLE 0x80000000 /* Enable Instruction $ */
8269 +#define BRCM_PFC_ENABLE 0x00400000 /* Obsolete? Enable PFC (at least on 4310) */
8270 +
8271 +/* PreFetch Cache aka Read Ahead Cache */
8272 +
8273 +#define PFC_CR0 0xff400000 /* control reg 0 */
8274 +#define PFC_CR1 0xff400004 /* control reg 1 */
8275 +
8276 +/* PFC operations */
8277 +#define PFC_I 0x00000001 /* Enable PFC use for instructions */
8278 +#define PFC_D 0x00000002 /* Enable PFC use for data */
8279 +#define PFC_PFI 0x00000004 /* Enable seq. prefetch for instructions */
8280 +#define PFC_PFD 0x00000008 /* Enable seq. prefetch for data */
8281 +#define PFC_CINV 0x00000010 /* Enable selective (i/d) cacheop flushing */
8282 +#define PFC_NCH 0x00000020 /* Disable flushing based on cacheops */
8283 +#define PFC_DPF 0x00000040 /* Enable directional prefetching */
8284 +#define PFC_FLUSH 0x00000100 /* Flush the PFC */
8285 +#define PFC_BRR 0x40000000 /* Bus error indication */
8286 +#define PFC_PWR 0x80000000 /* Disable power saving (clock gating) */
8287 +
8288 +/* Handy defaults */
8289 +#define PFC_DISABLED 0
8290 +#define PFC_AUTO 0xffffffff /* auto select the default mode */
8291 +#define PFC_INST (PFC_I | PFC_PFI | PFC_CINV)
8292 +#define PFC_INST_NOPF (PFC_I | PFC_CINV)
8293 +#define PFC_DATA (PFC_D | PFC_PFD | PFC_CINV)
8294 +#define PFC_DATA_NOPF (PFC_D | PFC_CINV)
8295 +#define PFC_I_AND_D (PFC_INST | PFC_DATA)
8296 +#define PFC_I_AND_D_NOPF (PFC_INST_NOPF | PFC_DATA_NOPF)
8297 +
8298 +
8299 +/*
8300 + * These are the UART port assignments, expressed as offsets from the base
8301 + * register. These assignments should hold for any serial port based on
8302 + * a 8250, 16450, or 16550(A).
8303 + */
8304 +
8305 +#define UART_RX 0 /* In: Receive buffer (DLAB=0) */
8306 +#define UART_TX 0 /* Out: Transmit buffer (DLAB=0) */
8307 +#define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */
8308 +#define UART_DLM 1 /* Out: Divisor Latch High (DLAB=1) */
8309 +#define UART_LCR 3 /* Out: Line Control Register */
8310 +#define UART_MCR 4 /* Out: Modem Control Register */
8311 +#define UART_LSR 5 /* In: Line Status Register */
8312 +#define UART_MSR 6 /* In: Modem Status Register */
8313 +#define UART_SCR 7 /* I/O: Scratch Register */
8314 +#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
8315 +#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
8316 +#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
8317 +#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
8318 +#define UART_LSR_RXRDY 0x01 /* Receiver ready */
8319 +
8320 +
8321 +#ifndef _LANGUAGE_ASSEMBLY
8322 +
8323 +/*
8324 + * Macros to access the system control coprocessor
8325 + */
8326 +
8327 +#define MFC0(source, sel) \
8328 +({ \
8329 + int __res; \
8330 + __asm__ __volatile__( \
8331 + ".set\tnoreorder\n\t" \
8332 + ".set\tnoat\n\t" \
8333 + ".word\t"STR(0x40010000 | ((source)<<11) | (sel))"\n\t" \
8334 + "move\t%0,$1\n\t" \
8335 + ".set\tat\n\t" \
8336 + ".set\treorder" \
8337 + :"=r" (__res) \
8338 + : \
8339 + :"$1"); \
8340 + __res; \
8341 +})
8342 +
8343 +#define MTC0(source, sel, value) \
8344 +do { \
8345 + __asm__ __volatile__( \
8346 + ".set\tnoreorder\n\t" \
8347 + ".set\tnoat\n\t" \
8348 + "move\t$1,%z0\n\t" \
8349 + ".word\t"STR(0x40810000 | ((source)<<11) | (sel))"\n\t" \
8350 + ".set\tat\n\t" \
8351 + ".set\treorder" \
8352 + : \
8353 + :"jr" (value) \
8354 + :"$1"); \
8355 +} while (0)
8356 +
8357 +#define get_c0_count() \
8358 +({ \
8359 + int __res; \
8360 + __asm__ __volatile__( \
8361 + ".set\tnoreorder\n\t" \
8362 + ".set\tnoat\n\t" \
8363 + "mfc0\t%0,$9\n\t" \
8364 + ".set\tat\n\t" \
8365 + ".set\treorder" \
8366 + :"=r" (__res)); \
8367 + __res; \
8368 +})
8369 +
8370 +static INLINE void icache_probe(uint32 config1, uint *size, uint *lsize)
8371 +{
8372 + uint lsz, sets, ways;
8373 +
8374 + /* Instruction Cache Size = Associativity * Line Size * Sets Per Way */
8375 + if ((lsz = ((config1 & CONF1_IL_MASK) >> CONF1_IL_SHIFT)))
8376 + lsz = CONF1_IL_BASE << lsz;
8377 + sets = CONF1_IS_BASE << ((config1 & CONF1_IS_MASK) >> CONF1_IS_SHIFT);
8378 + ways = CONF1_IA_BASE + ((config1 & CONF1_IA_MASK) >> CONF1_IA_SHIFT);
8379 + *size = lsz * sets * ways;
8380 + *lsize = lsz;
8381 +}
8382 +
8383 +static INLINE void dcache_probe(uint32 config1, uint *size, uint *lsize)
8384 +{
8385 + uint lsz, sets, ways;
8386 +
8387 + /* Data Cache Size = Associativity * Line Size * Sets Per Way */
8388 + if ((lsz = ((config1 & CONF1_DL_MASK) >> CONF1_DL_SHIFT)))
8389 + lsz = CONF1_DL_BASE << lsz;
8390 + sets = CONF1_DS_BASE << ((config1 & CONF1_DS_MASK) >> CONF1_DS_SHIFT);
8391 + ways = CONF1_DA_BASE + ((config1 & CONF1_DA_MASK) >> CONF1_DA_SHIFT);
8392 + *size = lsz * sets * ways;
8393 + *lsize = lsz;
8394 +}
8395 +
8396 +#define cache_op(base, op) \
8397 + __asm__ __volatile__(" \
8398 + .set noreorder; \
8399 + .set mips3; \
8400 + cache %1, (%0); \
8401 + .set mips0; \
8402 + .set reorder" \
8403 + : \
8404 + : "r" (base), \
8405 + "i" (op));
8406 +
8407 +#define cache_unroll4(base, delta, op) \
8408 + __asm__ __volatile__(" \
8409 + .set noreorder; \
8410 + .set mips3; \
8411 + cache %1,0(%0); \
8412 + cache %1,delta(%0); \
8413 + cache %1,(2 * delta)(%0); \
8414 + cache %1,(3 * delta)(%0); \
8415 + .set mips0; \
8416 + .set reorder" \
8417 + : \
8418 + : "r" (base), \
8419 + "i" (op));
8420 +
8421 +#endif /* !_LANGUAGE_ASSEMBLY */
8422 +
8423 +#endif /* _MISPINC_H */
8424 diff -urN linux.old/arch/mips/bcm947xx/include/osl.h linux.dev/arch/mips/bcm947xx/include/osl.h
8425 --- linux.old/arch/mips/bcm947xx/include/osl.h 1970-01-01 01:00:00.000000000 +0100
8426 +++ linux.dev/arch/mips/bcm947xx/include/osl.h 2005-12-28 16:37:32.878261500 +0100
8427 @@ -0,0 +1,42 @@
8428 +/*
8429 + * OS Abstraction Layer
8430 + *
8431 + * Copyright 2005, Broadcom Corporation
8432 + * All Rights Reserved.
8433 + *
8434 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8435 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8436 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8437 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8438 + * $Id$
8439 + */
8440 +
8441 +#ifndef _osl_h_
8442 +#define _osl_h_
8443 +
8444 +/* osl handle type forward declaration */
8445 +typedef struct os_handle osl_t;
8446 +
8447 +#if defined(linux)
8448 +#include <linux_osl.h>
8449 +#elif defined(NDIS)
8450 +#include <ndis_osl.h>
8451 +#elif defined(_CFE_)
8452 +#include <cfe_osl.h>
8453 +#elif defined(_HNDRTE_)
8454 +#include <hndrte_osl.h>
8455 +#elif defined(_MINOSL_)
8456 +#include <min_osl.h>
8457 +#elif PMON
8458 +#include <pmon_osl.h>
8459 +#elif defined(MACOSX)
8460 +#include <macosx_osl.h>
8461 +#else
8462 +#error "Unsupported OSL requested"
8463 +#endif
8464 +
8465 +/* handy */
8466 +#define SET_REG(r, mask, val) W_REG((r), ((R_REG(r) & ~(mask)) | (val)))
8467 +#define MAXPRIO 7 /* 0-7 */
8468 +
8469 +#endif /* _osl_h_ */
8470 diff -urN linux.old/arch/mips/bcm947xx/include/pcicfg.h linux.dev/arch/mips/bcm947xx/include/pcicfg.h
8471 --- linux.old/arch/mips/bcm947xx/include/pcicfg.h 1970-01-01 01:00:00.000000000 +0100
8472 +++ linux.dev/arch/mips/bcm947xx/include/pcicfg.h 2005-12-28 16:37:32.882261750 +0100
8473 @@ -0,0 +1,398 @@
8474 +/*
8475 + * pcicfg.h: PCI configuration constants and structures.
8476 + *
8477 + * Copyright 2005, Broadcom Corporation
8478 + * All Rights Reserved.
8479 + *
8480 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8481 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8482 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8483 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8484 + *
8485 + * $Id$
8486 + */
8487 +
8488 +#ifndef _h_pci_
8489 +#define _h_pci_
8490 +
8491 +/* The following inside ifndef's so we don't collide with NTDDK.H */
8492 +#ifndef PCI_MAX_BUS
8493 +#define PCI_MAX_BUS 0x100
8494 +#endif
8495 +#ifndef PCI_MAX_DEVICES
8496 +#define PCI_MAX_DEVICES 0x20
8497 +#endif
8498 +#ifndef PCI_MAX_FUNCTION
8499 +#define PCI_MAX_FUNCTION 0x8
8500 +#endif
8501 +
8502 +#ifndef PCI_INVALID_VENDORID
8503 +#define PCI_INVALID_VENDORID 0xffff
8504 +#endif
8505 +#ifndef PCI_INVALID_DEVICEID
8506 +#define PCI_INVALID_DEVICEID 0xffff
8507 +#endif
8508 +
8509 +
8510 +/* Convert between bus-slot-function-register and config addresses */
8511 +
8512 +#define PCICFG_BUS_SHIFT 16 /* Bus shift */
8513 +#define PCICFG_SLOT_SHIFT 11 /* Slot shift */
8514 +#define PCICFG_FUN_SHIFT 8 /* Function shift */
8515 +#define PCICFG_OFF_SHIFT 0 /* Register shift */
8516 +
8517 +#define PCICFG_BUS_MASK 0xff /* Bus mask */
8518 +#define PCICFG_SLOT_MASK 0x1f /* Slot mask */
8519 +#define PCICFG_FUN_MASK 7 /* Function mask */
8520 +#define PCICFG_OFF_MASK 0xff /* Bus mask */
8521 +
8522 +#define PCI_CONFIG_ADDR(b, s, f, o) \
8523 + ((((b) & PCICFG_BUS_MASK) << PCICFG_BUS_SHIFT) \
8524 + | (((s) & PCICFG_SLOT_MASK) << PCICFG_SLOT_SHIFT) \
8525 + | (((f) & PCICFG_FUN_MASK) << PCICFG_FUN_SHIFT) \
8526 + | (((o) & PCICFG_OFF_MASK) << PCICFG_OFF_SHIFT))
8527 +
8528 +#define PCI_CONFIG_BUS(a) (((a) >> PCICFG_BUS_SHIFT) & PCICFG_BUS_MASK)
8529 +#define PCI_CONFIG_SLOT(a) (((a) >> PCICFG_SLOT_SHIFT) & PCICFG_SLOT_MASK)
8530 +#define PCI_CONFIG_FUN(a) (((a) >> PCICFG_FUN_SHIFT) & PCICFG_FUN_MASK)
8531 +#define PCI_CONFIG_OFF(a) (((a) >> PCICFG_OFF_SHIFT) & PCICFG_OFF_MASK)
8532 +
8533 +/* The actual config space */
8534 +
8535 +#define PCI_BAR_MAX 6
8536 +
8537 +#define PCI_ROM_BAR 8
8538 +
8539 +#define PCR_RSVDA_MAX 2
8540 +
8541 +/* pci config status reg has a bit to indicate that capability ptr is present*/
8542 +
8543 +#define PCI_CAPPTR_PRESENT 0x0010
8544 +
8545 +typedef struct _pci_config_regs {
8546 + unsigned short vendor;
8547 + unsigned short device;
8548 + unsigned short command;
8549 + unsigned short status;
8550 + unsigned char rev_id;
8551 + unsigned char prog_if;
8552 + unsigned char sub_class;
8553 + unsigned char base_class;
8554 + unsigned char cache_line_size;
8555 + unsigned char latency_timer;
8556 + unsigned char header_type;
8557 + unsigned char bist;
8558 + unsigned long base[PCI_BAR_MAX];
8559 + unsigned long cardbus_cis;
8560 + unsigned short subsys_vendor;
8561 + unsigned short subsys_id;
8562 + unsigned long baserom;
8563 + unsigned long rsvd_a[PCR_RSVDA_MAX];
8564 + unsigned char int_line;
8565 + unsigned char int_pin;
8566 + unsigned char min_gnt;
8567 + unsigned char max_lat;
8568 + unsigned char dev_dep[192];
8569 +} pci_config_regs;
8570 +
8571 +#define SZPCR (sizeof (pci_config_regs))
8572 +#define MINSZPCR 64 /* offsetof (dev_dep[0] */
8573 +
8574 +/* A structure for the config registers is nice, but in most
8575 + * systems the config space is not memory mapped, so we need
8576 + * filed offsetts. :-(
8577 + */
8578 +#define PCI_CFG_VID 0
8579 +#define PCI_CFG_DID 2
8580 +#define PCI_CFG_CMD 4
8581 +#define PCI_CFG_STAT 6
8582 +#define PCI_CFG_REV 8
8583 +#define PCI_CFG_PROGIF 9
8584 +#define PCI_CFG_SUBCL 0xa
8585 +#define PCI_CFG_BASECL 0xb
8586 +#define PCI_CFG_CLSZ 0xc
8587 +#define PCI_CFG_LATTIM 0xd
8588 +#define PCI_CFG_HDR 0xe
8589 +#define PCI_CFG_BIST 0xf
8590 +#define PCI_CFG_BAR0 0x10
8591 +#define PCI_CFG_BAR1 0x14
8592 +#define PCI_CFG_BAR2 0x18
8593 +#define PCI_CFG_BAR3 0x1c
8594 +#define PCI_CFG_BAR4 0x20
8595 +#define PCI_CFG_BAR5 0x24
8596 +#define PCI_CFG_CIS 0x28
8597 +#define PCI_CFG_SVID 0x2c
8598 +#define PCI_CFG_SSID 0x2e
8599 +#define PCI_CFG_ROMBAR 0x30
8600 +#define PCI_CFG_CAPPTR 0x34
8601 +#define PCI_CFG_INT 0x3c
8602 +#define PCI_CFG_PIN 0x3d
8603 +#define PCI_CFG_MINGNT 0x3e
8604 +#define PCI_CFG_MAXLAT 0x3f
8605 +
8606 +/* Classes and subclasses */
8607 +
8608 +typedef enum {
8609 + PCI_CLASS_OLD = 0,
8610 + PCI_CLASS_DASDI,
8611 + PCI_CLASS_NET,
8612 + PCI_CLASS_DISPLAY,
8613 + PCI_CLASS_MMEDIA,
8614 + PCI_CLASS_MEMORY,
8615 + PCI_CLASS_BRIDGE,
8616 + PCI_CLASS_COMM,
8617 + PCI_CLASS_BASE,
8618 + PCI_CLASS_INPUT,
8619 + PCI_CLASS_DOCK,
8620 + PCI_CLASS_CPU,
8621 + PCI_CLASS_SERIAL,
8622 + PCI_CLASS_INTELLIGENT = 0xe,
8623 + PCI_CLASS_SATELLITE,
8624 + PCI_CLASS_CRYPT,
8625 + PCI_CLASS_DSP,
8626 + PCI_CLASS_MAX
8627 +} pci_classes;
8628 +
8629 +typedef enum {
8630 + PCI_DASDI_SCSI,
8631 + PCI_DASDI_IDE,
8632 + PCI_DASDI_FLOPPY,
8633 + PCI_DASDI_IPI,
8634 + PCI_DASDI_RAID,
8635 + PCI_DASDI_OTHER = 0x80
8636 +} pci_dasdi_subclasses;
8637 +
8638 +typedef enum {
8639 + PCI_NET_ETHER,
8640 + PCI_NET_TOKEN,
8641 + PCI_NET_FDDI,
8642 + PCI_NET_ATM,
8643 + PCI_NET_OTHER = 0x80
8644 +} pci_net_subclasses;
8645 +
8646 +typedef enum {
8647 + PCI_DISPLAY_VGA,
8648 + PCI_DISPLAY_XGA,
8649 + PCI_DISPLAY_3D,
8650 + PCI_DISPLAY_OTHER = 0x80
8651 +} pci_display_subclasses;
8652 +
8653 +typedef enum {
8654 + PCI_MMEDIA_VIDEO,
8655 + PCI_MMEDIA_AUDIO,
8656 + PCI_MMEDIA_PHONE,
8657 + PCI_MEDIA_OTHER = 0x80
8658 +} pci_mmedia_subclasses;
8659 +
8660 +typedef enum {
8661 + PCI_MEMORY_RAM,
8662 + PCI_MEMORY_FLASH,
8663 + PCI_MEMORY_OTHER = 0x80
8664 +} pci_memory_subclasses;
8665 +
8666 +typedef enum {
8667 + PCI_BRIDGE_HOST,
8668 + PCI_BRIDGE_ISA,
8669 + PCI_BRIDGE_EISA,
8670 + PCI_BRIDGE_MC,
8671 + PCI_BRIDGE_PCI,
8672 + PCI_BRIDGE_PCMCIA,
8673 + PCI_BRIDGE_NUBUS,
8674 + PCI_BRIDGE_CARDBUS,
8675 + PCI_BRIDGE_RACEWAY,
8676 + PCI_BRIDGE_OTHER = 0x80
8677 +} pci_bridge_subclasses;
8678 +
8679 +typedef enum {
8680 + PCI_COMM_UART,
8681 + PCI_COMM_PARALLEL,
8682 + PCI_COMM_MULTIUART,
8683 + PCI_COMM_MODEM,
8684 + PCI_COMM_OTHER = 0x80
8685 +} pci_comm_subclasses;
8686 +
8687 +typedef enum {
8688 + PCI_BASE_PIC,
8689 + PCI_BASE_DMA,
8690 + PCI_BASE_TIMER,
8691 + PCI_BASE_RTC,
8692 + PCI_BASE_PCI_HOTPLUG,
8693 + PCI_BASE_OTHER = 0x80
8694 +} pci_base_subclasses;
8695 +
8696 +typedef enum {
8697 + PCI_INPUT_KBD,
8698 + PCI_INPUT_PEN,
8699 + PCI_INPUT_MOUSE,
8700 + PCI_INPUT_SCANNER,
8701 + PCI_INPUT_GAMEPORT,
8702 + PCI_INPUT_OTHER = 0x80
8703 +} pci_input_subclasses;
8704 +
8705 +typedef enum {
8706 + PCI_DOCK_GENERIC,
8707 + PCI_DOCK_OTHER = 0x80
8708 +} pci_dock_subclasses;
8709 +
8710 +typedef enum {
8711 + PCI_CPU_386,
8712 + PCI_CPU_486,
8713 + PCI_CPU_PENTIUM,
8714 + PCI_CPU_ALPHA = 0x10,
8715 + PCI_CPU_POWERPC = 0x20,
8716 + PCI_CPU_MIPS = 0x30,
8717 + PCI_CPU_COPROC = 0x40,
8718 + PCI_CPU_OTHER = 0x80
8719 +} pci_cpu_subclasses;
8720 +
8721 +typedef enum {
8722 + PCI_SERIAL_IEEE1394,
8723 + PCI_SERIAL_ACCESS,
8724 + PCI_SERIAL_SSA,
8725 + PCI_SERIAL_USB,
8726 + PCI_SERIAL_FIBER,
8727 + PCI_SERIAL_SMBUS,
8728 + PCI_SERIAL_OTHER = 0x80
8729 +} pci_serial_subclasses;
8730 +
8731 +typedef enum {
8732 + PCI_INTELLIGENT_I2O,
8733 +} pci_intelligent_subclasses;
8734 +
8735 +typedef enum {
8736 + PCI_SATELLITE_TV,
8737 + PCI_SATELLITE_AUDIO,
8738 + PCI_SATELLITE_VOICE,
8739 + PCI_SATELLITE_DATA,
8740 + PCI_SATELLITE_OTHER = 0x80
8741 +} pci_satellite_subclasses;
8742 +
8743 +typedef enum {
8744 + PCI_CRYPT_NETWORK,
8745 + PCI_CRYPT_ENTERTAINMENT,
8746 + PCI_CRYPT_OTHER = 0x80
8747 +} pci_crypt_subclasses;
8748 +
8749 +typedef enum {
8750 + PCI_DSP_DPIO,
8751 + PCI_DSP_OTHER = 0x80
8752 +} pci_dsp_subclasses;
8753 +
8754 +/* Header types */
8755 +typedef enum {
8756 + PCI_HEADER_NORMAL,
8757 + PCI_HEADER_BRIDGE,
8758 + PCI_HEADER_CARDBUS
8759 +} pci_header_types;
8760 +
8761 +
8762 +/* Overlay for a PCI-to-PCI bridge */
8763 +
8764 +#define PPB_RSVDA_MAX 2
8765 +#define PPB_RSVDD_MAX 8
8766 +
8767 +typedef struct _ppb_config_regs {
8768 + unsigned short vendor;
8769 + unsigned short device;
8770 + unsigned short command;
8771 + unsigned short status;
8772 + unsigned char rev_id;
8773 + unsigned char prog_if;
8774 + unsigned char sub_class;
8775 + unsigned char base_class;
8776 + unsigned char cache_line_size;
8777 + unsigned char latency_timer;
8778 + unsigned char header_type;
8779 + unsigned char bist;
8780 + unsigned long rsvd_a[PPB_RSVDA_MAX];
8781 + unsigned char prim_bus;
8782 + unsigned char sec_bus;
8783 + unsigned char sub_bus;
8784 + unsigned char sec_lat;
8785 + unsigned char io_base;
8786 + unsigned char io_lim;
8787 + unsigned short sec_status;
8788 + unsigned short mem_base;
8789 + unsigned short mem_lim;
8790 + unsigned short pf_mem_base;
8791 + unsigned short pf_mem_lim;
8792 + unsigned long pf_mem_base_hi;
8793 + unsigned long pf_mem_lim_hi;
8794 + unsigned short io_base_hi;
8795 + unsigned short io_lim_hi;
8796 + unsigned short subsys_vendor;
8797 + unsigned short subsys_id;
8798 + unsigned long rsvd_b;
8799 + unsigned char rsvd_c;
8800 + unsigned char int_pin;
8801 + unsigned short bridge_ctrl;
8802 + unsigned char chip_ctrl;
8803 + unsigned char diag_ctrl;
8804 + unsigned short arb_ctrl;
8805 + unsigned long rsvd_d[PPB_RSVDD_MAX];
8806 + unsigned char dev_dep[192];
8807 +} ppb_config_regs;
8808 +
8809 +
8810 +/* PCI CAPABILITY DEFINES */
8811 +#define PCI_CAP_POWERMGMTCAP_ID 0x01
8812 +#define PCI_CAP_MSICAP_ID 0x05
8813 +
8814 +/* Data structure to define the Message Signalled Interrupt facility
8815 + * Valid for PCI and PCIE configurations */
8816 +typedef struct _pciconfig_cap_msi {
8817 + unsigned char capID;
8818 + unsigned char nextptr;
8819 + unsigned short msgctrl;
8820 + unsigned int msgaddr;
8821 +} pciconfig_cap_msi;
8822 +
8823 +/* Data structure to define the Power managment facility
8824 + * Valid for PCI and PCIE configurations */
8825 +typedef struct _pciconfig_cap_pwrmgmt {
8826 + unsigned char capID;
8827 + unsigned char nextptr;
8828 + unsigned short pme_cap;
8829 + unsigned short pme_sts_ctrl;
8830 + unsigned char pme_bridge_ext;
8831 + unsigned char data;
8832 +} pciconfig_cap_pwrmgmt;
8833 +
8834 +/* Everything below is BRCM HND proprietary */
8835 +
8836 +#define PCI_BAR0_WIN 0x80 /* backplane addres space accessed by BAR0 */
8837 +#define PCI_BAR1_WIN 0x84 /* backplane addres space accessed by BAR1 */
8838 +#define PCI_SPROM_CONTROL 0x88 /* sprom property control */
8839 +#define PCI_BAR1_CONTROL 0x8c /* BAR1 region burst control */
8840 +#define PCI_INT_STATUS 0x90 /* PCI and other cores interrupts */
8841 +#define PCI_INT_MASK 0x94 /* mask of PCI and other cores interrupts */
8842 +#define PCI_TO_SB_MB 0x98 /* signal backplane interrupts */
8843 +#define PCI_BACKPLANE_ADDR 0xA0 /* address an arbitrary location on the system backplane */
8844 +#define PCI_BACKPLANE_DATA 0xA4 /* data at the location specified by above address register */
8845 +#define PCI_GPIO_IN 0xb0 /* pci config space gpio input (>=rev3) */
8846 +#define PCI_GPIO_OUT 0xb4 /* pci config space gpio output (>=rev3) */
8847 +#define PCI_GPIO_OUTEN 0xb8 /* pci config space gpio output enable (>=rev3) */
8848 +
8849 +#define PCI_BAR0_SPROM_OFFSET (4 * 1024) /* bar0 + 4K accesses external sprom */
8850 +#define PCI_BAR0_PCIREGS_OFFSET (6 * 1024) /* bar0 + 6K accesses pci core registers */
8851 +
8852 +/* PCI_INT_STATUS */
8853 +#define PCI_SBIM_STATUS_SERR 0x4 /* backplane SBErr interrupt status */
8854 +
8855 +/* PCI_INT_MASK */
8856 +#define PCI_SBIM_SHIFT 8 /* backplane core interrupt mask bits offset */
8857 +#define PCI_SBIM_MASK 0xff00 /* backplane core interrupt mask */
8858 +#define PCI_SBIM_MASK_SERR 0x4 /* backplane SBErr interrupt mask */
8859 +
8860 +/* PCI_SPROM_CONTROL */
8861 +#define SPROM_BLANK 0x04 /* indicating a blank sprom */
8862 +#define SPROM_WRITEEN 0x10 /* sprom write enable */
8863 +#define SPROM_BOOTROM_WE 0x20 /* external bootrom write enable */
8864 +
8865 +#define SPROM_SIZE 256 /* sprom size in 16-bit */
8866 +#define SPROM_CRC_RANGE 64 /* crc cover range in 16-bit */
8867 +
8868 +/* PCI_CFG_CMD_STAT */
8869 +#define PCI_CFG_CMD_STAT_TA 0x08000000 /* target abort status */
8870 +
8871 +#endif
8872 diff -urN linux.old/arch/mips/bcm947xx/include/proto/ethernet.h linux.dev/arch/mips/bcm947xx/include/proto/ethernet.h
8873 --- linux.old/arch/mips/bcm947xx/include/proto/ethernet.h 1970-01-01 01:00:00.000000000 +0100
8874 +++ linux.dev/arch/mips/bcm947xx/include/proto/ethernet.h 2005-12-28 16:37:32.882261750 +0100
8875 @@ -0,0 +1,145 @@
8876 +/*******************************************************************************
8877 + * $Id$
8878 + * Copyright 2001-2003, Broadcom Corporation
8879 + * All Rights Reserved.
8880 + *
8881 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8882 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8883 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8884 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8885 + * From FreeBSD 2.2.7: Fundamental constants relating to ethernet.
8886 + ******************************************************************************/
8887 +
8888 +#ifndef _NET_ETHERNET_H_ /* use native BSD ethernet.h when available */
8889 +#define _NET_ETHERNET_H_
8890 +
8891 +#ifndef _TYPEDEFS_H_
8892 +#include "typedefs.h"
8893 +#endif
8894 +
8895 +#if defined(__GNUC__)
8896 +#define PACKED __attribute__((packed))
8897 +#else
8898 +#define PACKED
8899 +#endif
8900 +
8901 +/*
8902 + * The number of bytes in an ethernet (MAC) address.
8903 + */
8904 +#define ETHER_ADDR_LEN 6
8905 +
8906 +/*
8907 + * The number of bytes in the type field.
8908 + */
8909 +#define ETHER_TYPE_LEN 2
8910 +
8911 +/*
8912 + * The number of bytes in the trailing CRC field.
8913 + */
8914 +#define ETHER_CRC_LEN 4
8915 +
8916 +/*
8917 + * The length of the combined header.
8918 + */
8919 +#define ETHER_HDR_LEN (ETHER_ADDR_LEN*2+ETHER_TYPE_LEN)
8920 +
8921 +/*
8922 + * The minimum packet length.
8923 + */
8924 +#define ETHER_MIN_LEN 64
8925 +
8926 +/*
8927 + * The minimum packet user data length.
8928 + */
8929 +#define ETHER_MIN_DATA 46
8930 +
8931 +/*
8932 + * The maximum packet length.
8933 + */
8934 +#define ETHER_MAX_LEN 1518
8935 +
8936 +/*
8937 + * The maximum packet user data length.
8938 + */
8939 +#define ETHER_MAX_DATA 1500
8940 +
8941 +/*
8942 + * Used to uniquely identify a 802.1q VLAN-tagged header.
8943 + */
8944 +#define VLAN_TAG 0x8100
8945 +
8946 +/*
8947 + * Located after dest & src address in ether header.
8948 + */
8949 +#define VLAN_FIELDS_OFFSET (ETHER_ADDR_LEN * 2)
8950 +
8951 +/*
8952 + * 4 bytes of vlan field info.
8953 + */
8954 +#define VLAN_FIELDS_SIZE 4
8955 +
8956 +/* location of pri bits in 16-bit vlan fields */
8957 +#define VLAN_PRI_SHIFT 13
8958 +
8959 +/* 3 bits of priority */
8960 +#define VLAN_PRI_MASK 7
8961 +
8962 +/* 802.1X ethertype */
8963 +#define ETHER_TYPE_802_1X 0x888e
8964 +
8965 +/*
8966 + * A macro to validate a length with
8967 + */
8968 +#define ETHER_IS_VALID_LEN(foo) \
8969 + ((foo) >= ETHER_MIN_LEN && (foo) <= ETHER_MAX_LEN)
8970 +
8971 +
8972 +#ifndef __INCif_etherh /* Quick and ugly hack for VxWorks */
8973 +/*
8974 + * Structure of a 10Mb/s Ethernet header.
8975 + */
8976 +struct ether_header {
8977 + uint8 ether_dhost[ETHER_ADDR_LEN];
8978 + uint8 ether_shost[ETHER_ADDR_LEN];
8979 + uint16 ether_type;
8980 +} PACKED ;
8981 +
8982 +/*
8983 + * Structure of a 48-bit Ethernet address.
8984 + */
8985 +struct ether_addr {
8986 + uint8 octet[ETHER_ADDR_LEN];
8987 +} PACKED ;
8988 +#endif
8989 +
8990 +/*
8991 + * Takes a pointer, returns true if a 48-bit multicast address
8992 + * (including broadcast, since it is all ones)
8993 + */
8994 +#define ETHER_ISMULTI(ea) (((uint8 *)(ea))[0] & 1)
8995 +
8996 +/*
8997 + * Takes a pointer, returns true if a 48-bit broadcast (all ones)
8998 + */
8999 +#define ETHER_ISBCAST(ea) ((((uint8 *)(ea))[0] & \
9000 + ((uint8 *)(ea))[1] & \
9001 + ((uint8 *)(ea))[2] & \
9002 + ((uint8 *)(ea))[3] & \
9003 + ((uint8 *)(ea))[4] & \
9004 + ((uint8 *)(ea))[5]) == 0xff)
9005 +
9006 +static const struct ether_addr ether_bcast = {{255, 255, 255, 255, 255, 255}};
9007 +
9008 +/*
9009 + * Takes a pointer, returns true if a 48-bit null address (all zeros)
9010 + */
9011 +#define ETHER_ISNULLADDR(ea) ((((uint8 *)(ea))[0] | \
9012 + ((uint8 *)(ea))[1] | \
9013 + ((uint8 *)(ea))[2] | \
9014 + ((uint8 *)(ea))[3] | \
9015 + ((uint8 *)(ea))[4] | \
9016 + ((uint8 *)(ea))[5]) == 0)
9017 +
9018 +#undef PACKED
9019 +
9020 +#endif /* _NET_ETHERNET_H_ */
9021 diff -urN linux.old/arch/mips/bcm947xx/include/s5.h linux.dev/arch/mips/bcm947xx/include/s5.h
9022 --- linux.old/arch/mips/bcm947xx/include/s5.h 1970-01-01 01:00:00.000000000 +0100
9023 +++ linux.dev/arch/mips/bcm947xx/include/s5.h 2005-12-28 16:37:32.882261750 +0100
9024 @@ -0,0 +1,103 @@
9025 +#ifndef _S5_H_
9026 +#define _S5_H_
9027 +/*
9028 + * Copyright 2003, Broadcom Corporation
9029 + * All Rights Reserved.
9030 + *
9031 + * Broadcom Sentry5 (S5) BCM5365, 53xx, BCM58xx SOC Internal Core
9032 + * and MIPS3301 (R4K) System Address Space
9033 + *
9034 + * This program is free software; you can redistribute it and/or
9035 + * modify it under the terms of the GNU General Public License as
9036 + * published by the Free Software Foundation, located in the file
9037 + * LICENSE.
9038 + *
9039 + * $Id: s5.h,v 1.3 2003/06/10 18:54:51 jfd Exp $
9040 + *
9041 + */
9042 +
9043 +/* BCM5365 Address map */
9044 +#define KSEG1ADDR(x) ( (x) | 0xa0000000)
9045 +#define BCM5365_SDRAM 0x00000000 /* 0-128MB Physical SDRAM */
9046 +#define BCM5365_PCI_MEM 0x08000000 /* Host Mode PCI mem space (64MB) */
9047 +#define BCM5365_PCI_CFG 0x0c000000 /* Host Mode PCI cfg space (64MB) */
9048 +#define BCM5365_PCI_DMA 0x40000000 /* Client Mode PCI mem space (1GB)*/
9049 +#define BCM5365_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
9050 +#define BCM5365_ENUM 0x18000000 /* Beginning of core enum space */
9051 +
9052 +/* BCM5365 Core register space */
9053 +#define BCM5365_REG_CHIPC 0x18000000 /* Chipcommon registers */
9054 +#define BCM5365_REG_EMAC0 0x18001000 /* Ethernet MAC0 core registers */
9055 +#define BCM5365_REG_IPSEC 0x18002000 /* BCM582x CryptoCore registers */
9056 +#define BCM5365_REG_USB 0x18003000 /* USB core registers */
9057 +#define BCM5365_REG_PCI 0x18004000 /* PCI core registers */
9058 +#define BCM5365_REG_MIPS33 0x18005000 /* MIPS core registers */
9059 +#define BCM5365_REG_MEMC 0x18006000 /* MEMC core registers */
9060 +#define BCM5365_REG_UARTS (BCM5365_REG_CHIPC + 0x300) /* UART regs */
9061 +#define BCM5365_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
9062 +
9063 +/* COM Ports 1/2 */
9064 +#define BCM5365_UART (BCM5365_REG_UARTS)
9065 +#define BCM5365_UART_COM2 (BCM5365_REG_UARTS + 0x00000100)
9066 +
9067 +/* Registers common to MIPS33 Core used in 5365 */
9068 +#define MIPS33_FLASH_REGION 0x1fc00000 /* Boot FLASH Region */
9069 +#define MIPS33_EXTIF_REGION 0x1a000000 /* Chipcommon EXTIF region*/
9070 +#define BCM5365_EXTIF 0x1b000000 /* MISC_CS */
9071 +#define MIPS33_FLASH_REGION_AUX 0x1c000000 /* FLASH Region 2*/
9072 +
9073 +/* Internal Core Sonics Backplane Devices */
9074 +#define INTERNAL_UART_COM1 BCM5365_UART
9075 +#define INTERNAL_UART_COM2 BCM5365_UART_COM2
9076 +#define SB_REG_CHIPC BCM5365_REG_CHIPC
9077 +#define SB_REG_ENET0 BCM5365_REG_EMAC0
9078 +#define SB_REG_IPSEC BCM5365_REG_IPSEC
9079 +#define SB_REG_USB BCM5365_REG_USB
9080 +#define SB_REG_PCI BCM5365_REG_PCI
9081 +#define SB_REG_MIPS BCM5365_REG_MIPS33
9082 +#define SB_REG_MEMC BCM5365_REG_MEMC
9083 +#define SB_REG_MEMC_OFF 0x6000
9084 +#define SB_EXTIF_SPACE MIPS33_EXTIF_REGION
9085 +#define SB_FLASH_SPACE MIPS33_FLASH_REGION
9086 +
9087 +/*
9088 + * XXX
9089 + * 5365-specific backplane interrupt flag numbers. This should be done
9090 + * dynamically instead.
9091 + */
9092 +#define SBFLAG_PCI 0
9093 +#define SBFLAG_ENET0 1
9094 +#define SBFLAG_ILINE20 2
9095 +#define SBFLAG_CODEC 3
9096 +#define SBFLAG_USB 4
9097 +#define SBFLAG_EXTIF 5
9098 +#define SBFLAG_ENET1 6
9099 +
9100 +/* BCM95365 Local Bus devices */
9101 +#define BCM95365K_RESET_ADDR BCM5365_EXTIF
9102 +#define BCM95365K_BOARDID_ADDR (BCM5365_EXTIF | 0x4000)
9103 +#define BCM95365K_DOC_ADDR (BCM5365_EXTIF | 0x6000)
9104 +#define BCM95365K_LED_ADDR (BCM5365_EXTIF | 0xc000)
9105 +#define BCM95365K_TOD_REG_BASE (BCM95365K_NVRAM_ADDR | 0x1ff0)
9106 +#define BCM95365K_NVRAM_ADDR (BCM5365_EXTIF | 0xe000)
9107 +#define BCM95365K_NVRAM_SIZE 0x1ff0 /* 8K NVRAM : DS1743/STM48txx*/
9108 +
9109 +/* Write to DLR2416 VFD Display character RAM */
9110 +#define LED_REG(x) \
9111 + (*(volatile unsigned char *) (KSEG1ADDR(BCM95365K_LED_ADDR) + (x)))
9112 +
9113 +#ifdef CONFIG_VSIM
9114 +#define BCM5365_TRACE(trval) do { *((int *)0xa0002ff8) = (trval); \
9115 + } while (0)
9116 +#else
9117 +#define BCM5365_TRACE(trval) do { *((unsigned char *)\
9118 + KSEG1ADDR(BCM5365K_LED_ADDR)) = (trval); \
9119 + *((int *)0xa0002ff8) = (trval); } while (0)
9120 +#endif
9121 +
9122 +/* BCM9536R Local Bus devices */
9123 +#define BCM95365R_DOC_ADDR BCM5365_EXTIF
9124 +
9125 +
9126 +
9127 +#endif /*!_S5_H_ */
9128 diff -urN linux.old/arch/mips/bcm947xx/include/sbchipc.h linux.dev/arch/mips/bcm947xx/include/sbchipc.h
9129 --- linux.old/arch/mips/bcm947xx/include/sbchipc.h 1970-01-01 01:00:00.000000000 +0100
9130 +++ linux.dev/arch/mips/bcm947xx/include/sbchipc.h 2005-12-28 16:37:32.882261750 +0100
9131 @@ -0,0 +1,440 @@
9132 +/*
9133 + * SiliconBackplane Chipcommon core hardware definitions.
9134 + *
9135 + * The chipcommon core provides chip identification, SB control,
9136 + * jtag, 0/1/2 uarts, clock frequency control, a watchdog interrupt timer,
9137 + * gpio interface, extbus, and support for serial and parallel flashes.
9138 + *
9139 + * $Id$
9140 + * Copyright 2005, Broadcom Corporation
9141 + * All Rights Reserved.
9142 + *
9143 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
9144 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9145 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
9146 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
9147 + *
9148 + */
9149 +
9150 +#ifndef _SBCHIPC_H
9151 +#define _SBCHIPC_H
9152 +
9153 +
9154 +#ifndef _LANGUAGE_ASSEMBLY
9155 +
9156 +/* cpp contortions to concatenate w/arg prescan */
9157 +#ifndef PAD
9158 +#define _PADLINE(line) pad ## line
9159 +#define _XSTR(line) _PADLINE(line)
9160 +#define PAD _XSTR(__LINE__)
9161 +#endif /* PAD */
9162 +
9163 +typedef volatile struct {
9164 + uint32 chipid; /* 0x0 */
9165 + uint32 capabilities;
9166 + uint32 corecontrol; /* corerev >= 1 */
9167 + uint32 bist;
9168 +
9169 + /* OTP */
9170 + uint32 otpstatus; /* 0x10, corerev >= 10 */
9171 + uint32 otpcontrol;
9172 + uint32 otpprog;
9173 + uint32 PAD;
9174 +
9175 + /* Interrupt control */
9176 + uint32 intstatus; /* 0x20 */
9177 + uint32 intmask;
9178 + uint32 chipcontrol; /* 0x28, rev >= 11 */
9179 + uint32 chipstatus; /* 0x2c, rev >= 11 */
9180 +
9181 + /* Jtag Master */
9182 + uint32 jtagcmd; /* 0x30, rev >= 10 */
9183 + uint32 jtagir;
9184 + uint32 jtagdr;
9185 + uint32 jtagctrl;
9186 +
9187 + /* serial flash interface registers */
9188 + uint32 flashcontrol; /* 0x40 */
9189 + uint32 flashaddress;
9190 + uint32 flashdata;
9191 + uint32 PAD[1];
9192 +
9193 + /* Silicon backplane configuration broadcast control */
9194 + uint32 broadcastaddress; /* 0x50 */
9195 + uint32 broadcastdata;
9196 + uint32 PAD[2];
9197 +
9198 + /* gpio - cleared only by power-on-reset */
9199 + uint32 gpioin; /* 0x60 */
9200 + uint32 gpioout;
9201 + uint32 gpioouten;
9202 + uint32 gpiocontrol;
9203 + uint32 gpiointpolarity;
9204 + uint32 gpiointmask;
9205 + uint32 PAD[2];
9206 +
9207 + /* Watchdog timer */
9208 + uint32 watchdog; /* 0x80 */
9209 + uint32 PAD[1];
9210 +
9211 + /*GPIO based LED powersave registers corerev >= 16*/
9212 + uint32 gpiotimerval; /*0x88 */
9213 + uint32 gpiotimeroutmask;
9214 +
9215 + /* clock control */
9216 + uint32 clockcontrol_n; /* 0x90 */
9217 + uint32 clockcontrol_sb; /* aka m0 */
9218 + uint32 clockcontrol_pci; /* aka m1 */
9219 + uint32 clockcontrol_m2; /* mii/uart/mipsref */
9220 + uint32 clockcontrol_mips; /* aka m3 */
9221 + uint32 clkdiv; /* corerev >= 3 */
9222 + uint32 PAD[2];
9223 +
9224 + /* pll delay registers (corerev >= 4) */
9225 + uint32 pll_on_delay; /* 0xb0 */
9226 + uint32 fref_sel_delay;
9227 + uint32 slow_clk_ctl; /* 5 < corerev < 10 */
9228 + uint32 PAD[1];
9229 +
9230 + /* Instaclock registers (corerev >= 10) */
9231 + uint32 system_clk_ctl; /* 0xc0 */
9232 + uint32 clkstatestretch;
9233 + uint32 PAD[14];
9234 +
9235 + /* ExtBus control registers (corerev >= 3) */
9236 + uint32 pcmcia_config; /* 0x100 */
9237 + uint32 pcmcia_memwait;
9238 + uint32 pcmcia_attrwait;
9239 + uint32 pcmcia_iowait;
9240 + uint32 ide_config;
9241 + uint32 ide_memwait;
9242 + uint32 ide_attrwait;
9243 + uint32 ide_iowait;
9244 + uint32 prog_config;
9245 + uint32 prog_waitcount;
9246 + uint32 flash_config;
9247 + uint32 flash_waitcount;
9248 + uint32 PAD[116];
9249 +
9250 + /* uarts */
9251 + uint8 uart0data; /* 0x300 */
9252 + uint8 uart0imr;
9253 + uint8 uart0fcr;
9254 + uint8 uart0lcr;
9255 + uint8 uart0mcr;
9256 + uint8 uart0lsr;
9257 + uint8 uart0msr;
9258 + uint8 uart0scratch;
9259 + uint8 PAD[248]; /* corerev >= 1 */
9260 +
9261 + uint8 uart1data; /* 0x400 */
9262 + uint8 uart1imr;
9263 + uint8 uart1fcr;
9264 + uint8 uart1lcr;
9265 + uint8 uart1mcr;
9266 + uint8 uart1lsr;
9267 + uint8 uart1msr;
9268 + uint8 uart1scratch;
9269 +} chipcregs_t;
9270 +
9271 +#endif /* _LANGUAGE_ASSEMBLY */
9272 +
9273 +#define CC_CHIPID 0
9274 +#define CC_CAPABILITIES 4
9275 +#define CC_JTAGCMD 0x30
9276 +#define CC_JTAGIR 0x34
9277 +#define CC_JTAGDR 0x38
9278 +#define CC_JTAGCTRL 0x3c
9279 +#define CC_WATCHDOG 0x80
9280 +#define CC_CLKC_N 0x90
9281 +#define CC_CLKC_M0 0x94
9282 +#define CC_CLKC_M1 0x98
9283 +#define CC_CLKC_M2 0x9c
9284 +#define CC_CLKC_M3 0xa0
9285 +#define CC_CLKDIV 0xa4
9286 +#define CC_SYS_CLK_CTL 0xc0
9287 +#define CC_OTP 0x800
9288 +
9289 +/* chipid */
9290 +#define CID_ID_MASK 0x0000ffff /* Chip Id mask */
9291 +#define CID_REV_MASK 0x000f0000 /* Chip Revision mask */
9292 +#define CID_REV_SHIFT 16 /* Chip Revision shift */
9293 +#define CID_PKG_MASK 0x00f00000 /* Package Option mask */
9294 +#define CID_PKG_SHIFT 20 /* Package Option shift */
9295 +#define CID_CC_MASK 0x0f000000 /* CoreCount (corerev >= 4) */
9296 +#define CID_CC_SHIFT 24
9297 +
9298 +/* capabilities */
9299 +#define CAP_UARTS_MASK 0x00000003 /* Number of uarts */
9300 +#define CAP_MIPSEB 0x00000004 /* MIPS is in big-endian mode */
9301 +#define CAP_UCLKSEL 0x00000018 /* UARTs clock select */
9302 +#define CAP_UINTCLK 0x00000008 /* UARTs are driven by internal divided clock */
9303 +#define CAP_UARTGPIO 0x00000020 /* UARTs own Gpio's 15:12 */
9304 +#define CAP_EXTBUS 0x00000040 /* External bus present */
9305 +#define CAP_FLASH_MASK 0x00000700 /* Type of flash */
9306 +#define CAP_PLL_MASK 0x00038000 /* Type of PLL */
9307 +#define CAP_PWR_CTL 0x00040000 /* Power control */
9308 +#define CAP_OTPSIZE 0x00380000 /* OTP Size (0 = none) */
9309 +#define CAP_OTPSIZE_SHIFT 19 /* OTP Size shift */
9310 +#define CAP_OTPSIZE_BASE 5 /* OTP Size base */
9311 +#define CAP_JTAGP 0x00400000 /* JTAG Master Present */
9312 +#define CAP_ROM 0x00800000 /* Internal boot rom active */
9313 +
9314 +/* PLL type */
9315 +#define PLL_NONE 0x00000000
9316 +#define PLL_TYPE1 0x00010000 /* 48Mhz base, 3 dividers */
9317 +#define PLL_TYPE2 0x00020000 /* 48Mhz, 4 dividers */
9318 +#define PLL_TYPE3 0x00030000 /* 25Mhz, 2 dividers */
9319 +#define PLL_TYPE4 0x00008000 /* 48Mhz, 4 dividers */
9320 +#define PLL_TYPE5 0x00018000 /* 25Mhz, 4 dividers */
9321 +#define PLL_TYPE6 0x00028000 /* 100/200 or 120/240 only */
9322 +#define PLL_TYPE7 0x00038000 /* 25Mhz, 4 dividers */
9323 +
9324 +/* corecontrol */
9325 +#define CC_UARTCLKO 0x00000001 /* Drive UART with internal clock */
9326 +#define CC_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
9327 +
9328 +/* Fields in the otpstatus register */
9329 +#define OTPS_PROGFAIL 0x80000000
9330 +#define OTPS_PROTECT 0x00000007
9331 +#define OTPS_HW_PROTECT 0x00000001
9332 +#define OTPS_SW_PROTECT 0x00000002
9333 +#define OTPS_CID_PROTECT 0x00000004
9334 +
9335 +/* Fields in the otpcontrol register */
9336 +#define OTPC_RECWAIT 0xff000000
9337 +#define OTPC_PROGWAIT 0x00ffff00
9338 +#define OTPC_PRW_SHIFT 8
9339 +#define OTPC_MAXFAIL 0x00000038
9340 +#define OTPC_VSEL 0x00000006
9341 +#define OTPC_SELVL 0x00000001
9342 +
9343 +/* Fields in otpprog */
9344 +#define OTPP_COL_MASK 0x000000ff
9345 +#define OTPP_ROW_MASK 0x0000ff00
9346 +#define OTPP_ROW_SHIFT 8
9347 +#define OTPP_READERR 0x10000000
9348 +#define OTPP_VALUE 0x20000000
9349 +#define OTPP_VALUE_SHIFT 29
9350 +#define OTPP_READ 0x40000000
9351 +#define OTPP_START 0x80000000
9352 +#define OTPP_BUSY 0x80000000
9353 +
9354 +/* jtagcmd */
9355 +#define JCMD_START 0x80000000
9356 +#define JCMD_BUSY 0x80000000
9357 +#define JCMD_PAUSE 0x40000000
9358 +#define JCMD0_ACC_MASK 0x0000f000
9359 +#define JCMD0_ACC_IRDR 0x00000000
9360 +#define JCMD0_ACC_DR 0x00001000
9361 +#define JCMD0_ACC_IR 0x00002000
9362 +#define JCMD0_ACC_RESET 0x00003000
9363 +#define JCMD0_ACC_IRPDR 0x00004000
9364 +#define JCMD0_ACC_PDR 0x00005000
9365 +#define JCMD0_IRW_MASK 0x00000f00
9366 +#define JCMD_ACC_MASK 0x000f0000 /* Changes for corerev 11 */
9367 +#define JCMD_ACC_IRDR 0x00000000
9368 +#define JCMD_ACC_DR 0x00010000
9369 +#define JCMD_ACC_IR 0x00020000
9370 +#define JCMD_ACC_RESET 0x00030000
9371 +#define JCMD_ACC_IRPDR 0x00040000
9372 +#define JCMD_ACC_PDR 0x00050000
9373 +#define JCMD_IRW_MASK 0x00001f00
9374 +#define JCMD_IRW_SHIFT 8
9375 +#define JCMD_DRW_MASK 0x0000003f
9376 +
9377 +/* jtagctrl */
9378 +#define JCTRL_FORCE_CLK 4 /* Force clock */
9379 +#define JCTRL_EXT_EN 2 /* Enable external targets */
9380 +#define JCTRL_EN 1 /* Enable Jtag master */
9381 +
9382 +/* Fields in clkdiv */
9383 +#define CLKD_SFLASH 0x0f000000
9384 +#define CLKD_SFLASH_SHIFT 24
9385 +#define CLKD_OTP 0x000f0000
9386 +#define CLKD_OTP_SHIFT 16
9387 +#define CLKD_JTAG 0x00000f00
9388 +#define CLKD_JTAG_SHIFT 8
9389 +#define CLKD_UART 0x000000ff
9390 +
9391 +/* intstatus/intmask */
9392 +#define CI_GPIO 0x00000001 /* gpio intr */
9393 +#define CI_EI 0x00000002 /* ro: ext intr pin (corerev >= 3) */
9394 +#define CI_WDRESET 0x80000000 /* watchdog reset occurred */
9395 +
9396 +/* slow_clk_ctl */
9397 +#define SCC_SS_MASK 0x00000007 /* slow clock source mask */
9398 +#define SCC_SS_LPO 0x00000000 /* source of slow clock is LPO */
9399 +#define SCC_SS_XTAL 0x00000001 /* source of slow clock is crystal */
9400 +#define SCC_SS_PCI 0x00000002 /* source of slow clock is PCI */
9401 +#define SCC_LF 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */
9402 +#define SCC_LP 0x00000400 /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled */
9403 +#define SCC_FS 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock, 0: power logic control */
9404 +#define SCC_IP 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors PLL clock disable requests from core */
9405 +#define SCC_XC 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't disable crystal when appropriate */
9406 +#define SCC_XP 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */
9407 +#define SCC_CD_MASK 0xffff0000 /* ClockDivider (SlowClk = 1/(4+divisor)) */
9408 +#define SCC_CD_SHIFT 16
9409 +
9410 +/* system_clk_ctl */
9411 +#define SYCC_IE 0x00000001 /* ILPen: Enable Idle Low Power */
9412 +#define SYCC_AE 0x00000002 /* ALPen: Enable Active Low Power */
9413 +#define SYCC_FP 0x00000004 /* ForcePLLOn */
9414 +#define SYCC_AR 0x00000008 /* Force ALP (or HT if ALPen is not set */
9415 +#define SYCC_HR 0x00000010 /* Force HT */
9416 +#define SYCC_CD_MASK 0xffff0000 /* ClkDiv (ILP = 1/(4+divisor)) */
9417 +#define SYCC_CD_SHIFT 16
9418 +
9419 +/* gpiotimerval*/
9420 +#define GPIO_ONTIME_SHIFT 16
9421 +
9422 +/* clockcontrol_n */
9423 +#define CN_N1_MASK 0x3f /* n1 control */
9424 +#define CN_N2_MASK 0x3f00 /* n2 control */
9425 +#define CN_N2_SHIFT 8
9426 +#define CN_PLLC_MASK 0xf0000 /* pll control */
9427 +#define CN_PLLC_SHIFT 16
9428 +
9429 +/* clockcontrol_sb/pci/uart */
9430 +#define CC_M1_MASK 0x3f /* m1 control */
9431 +#define CC_M2_MASK 0x3f00 /* m2 control */
9432 +#define CC_M2_SHIFT 8
9433 +#define CC_M3_MASK 0x3f0000 /* m3 control */
9434 +#define CC_M3_SHIFT 16
9435 +#define CC_MC_MASK 0x1f000000 /* mux control */
9436 +#define CC_MC_SHIFT 24
9437 +
9438 +/* N3M Clock control magic field values */
9439 +#define CC_F6_2 0x02 /* A factor of 2 in */
9440 +#define CC_F6_3 0x03 /* 6-bit fields like */
9441 +#define CC_F6_4 0x05 /* N1, M1 or M3 */
9442 +#define CC_F6_5 0x09
9443 +#define CC_F6_6 0x11
9444 +#define CC_F6_7 0x21
9445 +
9446 +#define CC_F5_BIAS 5 /* 5-bit fields get this added */
9447 +
9448 +#define CC_MC_BYPASS 0x08
9449 +#define CC_MC_M1 0x04
9450 +#define CC_MC_M1M2 0x02
9451 +#define CC_MC_M1M2M3 0x01
9452 +#define CC_MC_M1M3 0x11
9453 +
9454 +/* Type 2 Clock control magic field values */
9455 +#define CC_T2_BIAS 2 /* n1, n2, m1 & m3 bias */
9456 +#define CC_T2M2_BIAS 3 /* m2 bias */
9457 +
9458 +#define CC_T2MC_M1BYP 1
9459 +#define CC_T2MC_M2BYP 2
9460 +#define CC_T2MC_M3BYP 4
9461 +
9462 +/* Type 6 Clock control magic field values */
9463 +#define CC_T6_MMASK 1 /* bits of interest in m */
9464 +#define CC_T6_M0 120000000 /* sb clock for m = 0 */
9465 +#define CC_T6_M1 100000000 /* sb clock for m = 1 */
9466 +#define SB2MIPS_T6(sb) (2 * (sb))
9467 +
9468 +/* Common clock base */
9469 +#define CC_CLOCK_BASE1 24000000 /* Half the clock freq */
9470 +#define CC_CLOCK_BASE2 12500000 /* Alternate crystal on some PLL's */
9471 +
9472 +/* Clock control values for 200Mhz in 5350 */
9473 +#define CLKC_5350_N 0x0311
9474 +#define CLKC_5350_M 0x04020009
9475 +
9476 +/* Flash types in the chipcommon capabilities register */
9477 +#define FLASH_NONE 0x000 /* No flash */
9478 +#define SFLASH_ST 0x100 /* ST serial flash */
9479 +#define SFLASH_AT 0x200 /* Atmel serial flash */
9480 +#define PFLASH 0x700 /* Parallel flash */
9481 +
9482 +/* Bits in the config registers */
9483 +#define CC_CFG_EN 0x0001 /* Enable */
9484 +#define CC_CFG_EM_MASK 0x000e /* Extif Mode */
9485 +#define CC_CFG_EM_ASYNC 0x0002 /* Async/Parallel flash */
9486 +#define CC_CFG_EM_SYNC 0x0004 /* Synchronous */
9487 +#define CC_CFG_EM_PCMCIA 0x0008 /* PCMCIA */
9488 +#define CC_CFG_EM_IDE 0x000a /* IDE */
9489 +#define CC_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */
9490 +#define CC_CFG_CD_MASK 0x0060 /* Sync: Clock divisor */
9491 +#define CC_CFG_CE 0x0080 /* Sync: Clock enable */
9492 +#define CC_CFG_SB 0x0100 /* Sync: Size/Bytestrobe */
9493 +
9494 +/* Start/busy bit in flashcontrol */
9495 +#define SFLASH_START 0x80000000
9496 +#define SFLASH_BUSY SFLASH_START
9497 +
9498 +/* flashcontrol opcodes for ST flashes */
9499 +#define SFLASH_ST_WREN 0x0006 /* Write Enable */
9500 +#define SFLASH_ST_WRDIS 0x0004 /* Write Disable */
9501 +#define SFLASH_ST_RDSR 0x0105 /* Read Status Register */
9502 +#define SFLASH_ST_WRSR 0x0101 /* Write Status Register */
9503 +#define SFLASH_ST_READ 0x0303 /* Read Data Bytes */
9504 +#define SFLASH_ST_PP 0x0302 /* Page Program */
9505 +#define SFLASH_ST_SE 0x02d8 /* Sector Erase */
9506 +#define SFLASH_ST_BE 0x00c7 /* Bulk Erase */
9507 +#define SFLASH_ST_DP 0x00b9 /* Deep Power-down */
9508 +#define SFLASH_ST_RES 0x03ab /* Read Electronic Signature */
9509 +
9510 +/* Status register bits for ST flashes */
9511 +#define SFLASH_ST_WIP 0x01 /* Write In Progress */
9512 +#define SFLASH_ST_WEL 0x02 /* Write Enable Latch */
9513 +#define SFLASH_ST_BP_MASK 0x1c /* Block Protect */
9514 +#define SFLASH_ST_BP_SHIFT 2
9515 +#define SFLASH_ST_SRWD 0x80 /* Status Register Write Disable */
9516 +
9517 +/* flashcontrol opcodes for Atmel flashes */
9518 +#define SFLASH_AT_READ 0x07e8
9519 +#define SFLASH_AT_PAGE_READ 0x07d2
9520 +#define SFLASH_AT_BUF1_READ
9521 +#define SFLASH_AT_BUF2_READ
9522 +#define SFLASH_AT_STATUS 0x01d7
9523 +#define SFLASH_AT_BUF1_WRITE 0x0384
9524 +#define SFLASH_AT_BUF2_WRITE 0x0387
9525 +#define SFLASH_AT_BUF1_ERASE_PROGRAM 0x0283
9526 +#define SFLASH_AT_BUF2_ERASE_PROGRAM 0x0286
9527 +#define SFLASH_AT_BUF1_PROGRAM 0x0288
9528 +#define SFLASH_AT_BUF2_PROGRAM 0x0289
9529 +#define SFLASH_AT_PAGE_ERASE 0x0281
9530 +#define SFLASH_AT_BLOCK_ERASE 0x0250
9531 +#define SFLASH_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382
9532 +#define SFLASH_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385
9533 +#define SFLASH_AT_BUF1_LOAD 0x0253
9534 +#define SFLASH_AT_BUF2_LOAD 0x0255
9535 +#define SFLASH_AT_BUF1_COMPARE 0x0260
9536 +#define SFLASH_AT_BUF2_COMPARE 0x0261
9537 +#define SFLASH_AT_BUF1_REPROGRAM 0x0258
9538 +#define SFLASH_AT_BUF2_REPROGRAM 0x0259
9539 +
9540 +/* Status register bits for Atmel flashes */
9541 +#define SFLASH_AT_READY 0x80
9542 +#define SFLASH_AT_MISMATCH 0x40
9543 +#define SFLASH_AT_ID_MASK 0x38
9544 +#define SFLASH_AT_ID_SHIFT 3
9545 +
9546 +/* OTP regions */
9547 +#define OTP_HW_REGION OTPS_HW_PROTECT
9548 +#define OTP_SW_REGION OTPS_SW_PROTECT
9549 +#define OTP_CID_REGION OTPS_CID_PROTECT
9550 +
9551 +/* OTP regions (Byte offsets from otp size) */
9552 +#define OTP_SWLIM_OFF (-8)
9553 +#define OTP_CIDBASE_OFF 0
9554 +#define OTP_CIDLIM_OFF 8
9555 +
9556 +/* Predefined OTP words (Word offset from otp size) */
9557 +#define OTP_BOUNDARY_OFF (-4)
9558 +#define OTP_HWSIGN_OFF (-3)
9559 +#define OTP_SWSIGN_OFF (-2)
9560 +#define OTP_CIDSIGN_OFF (-1)
9561 +
9562 +#define OTP_CID_OFF 0
9563 +#define OTP_PKG_OFF 1
9564 +#define OTP_FID_OFF 2
9565 +#define OTP_RSV_OFF 3
9566 +#define OTP_LIM_OFF 4
9567 +
9568 +#define OTP_SIGNATURE 0x578a
9569 +#define OTP_MAGIC 0x4e56
9570 +
9571 +#endif /* _SBCHIPC_H */
9572 diff -urN linux.old/arch/mips/bcm947xx/include/sbconfig.h linux.dev/arch/mips/bcm947xx/include/sbconfig.h
9573 --- linux.old/arch/mips/bcm947xx/include/sbconfig.h 1970-01-01 01:00:00.000000000 +0100
9574 +++ linux.dev/arch/mips/bcm947xx/include/sbconfig.h 2005-12-28 16:37:32.898262750 +0100
9575 @@ -0,0 +1,342 @@
9576 +/*
9577 + * Broadcom SiliconBackplane hardware register definitions.
9578 + *
9579 + * Copyright 2005, Broadcom Corporation
9580 + * All Rights Reserved.
9581 + *
9582 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
9583 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9584 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
9585 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
9586 + * $Id$
9587 + */
9588 +
9589 +#ifndef _SBCONFIG_H
9590 +#define _SBCONFIG_H
9591 +
9592 +/* cpp contortions to concatenate w/arg prescan */
9593 +#ifndef PAD
9594 +#define _PADLINE(line) pad ## line
9595 +#define _XSTR(line) _PADLINE(line)
9596 +#define PAD _XSTR(__LINE__)
9597 +#endif
9598 +
9599 +/*
9600 + * SiliconBackplane Address Map.
9601 + * All regions may not exist on all chips.
9602 + */
9603 +#define SB_SDRAM_BASE 0x00000000 /* Physical SDRAM */
9604 +#define SB_PCI_MEM 0x08000000 /* Host Mode sb2pcitranslation0 (64 MB) */
9605 +#define SB_PCI_CFG 0x0c000000 /* Host Mode sb2pcitranslation1 (64 MB) */
9606 +#define SB_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
9607 +#define SB_ENUM_BASE 0x18000000 /* Enumeration space base */
9608 +#define SB_ENUM_LIM 0x18010000 /* Enumeration space limit */
9609 +
9610 +#define SB_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */
9611 +#define SB_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */
9612 +
9613 +#define SB_EXTIF_BASE 0x1f000000 /* External Interface region base address */
9614 +#define SB_FLASH1 0x1fc00000 /* Flash Region 1 */
9615 +#define SB_FLASH1_SZ 0x00400000 /* Size of Flash Region 1 */
9616 +
9617 +#define SB_PCI_DMA 0x40000000 /* Client Mode sb2pcitranslation2 (1 GB) */
9618 +#define SB_PCI_DMA_SZ 0x40000000 /* Client Mode sb2pcitranslation2 size in bytes */
9619 +#define SB_PCIE_DMA_L32 0x00000000 /* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), low 32 bits */
9620 +#define SB_PCIE_DMA_H32 0x80000000 /* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), high 32 bits */
9621 +#define SB_EUART (SB_EXTIF_BASE + 0x00800000)
9622 +#define SB_LED (SB_EXTIF_BASE + 0x00900000)
9623 +
9624 +
9625 +/* enumeration space related defs */
9626 +#define SB_CORE_SIZE 0x1000 /* each core gets 4Kbytes for registers */
9627 +#define SB_MAXCORES ((SB_ENUM_LIM - SB_ENUM_BASE)/SB_CORE_SIZE)
9628 +#define SBCONFIGOFF 0xf00 /* core sbconfig regs are top 256bytes of regs */
9629 +#define SBCONFIGSIZE 256 /* sizeof (sbconfig_t) */
9630 +
9631 +/* mips address */
9632 +#define SB_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
9633 +
9634 +/*
9635 + * Sonics Configuration Space Registers.
9636 + */
9637 +#define SBIPSFLAG 0x08
9638 +#define SBTPSFLAG 0x18
9639 +#define SBTMERRLOGA 0x48 /* sonics >= 2.3 */
9640 +#define SBTMERRLOG 0x50 /* sonics >= 2.3 */
9641 +#define SBADMATCH3 0x60
9642 +#define SBADMATCH2 0x68
9643 +#define SBADMATCH1 0x70
9644 +#define SBIMSTATE 0x90
9645 +#define SBINTVEC 0x94
9646 +#define SBTMSTATELOW 0x98
9647 +#define SBTMSTATEHIGH 0x9c
9648 +#define SBBWA0 0xa0
9649 +#define SBIMCONFIGLOW 0xa8
9650 +#define SBIMCONFIGHIGH 0xac
9651 +#define SBADMATCH0 0xb0
9652 +#define SBTMCONFIGLOW 0xb8
9653 +#define SBTMCONFIGHIGH 0xbc
9654 +#define SBBCONFIG 0xc0
9655 +#define SBBSTATE 0xc8
9656 +#define SBACTCNFG 0xd8
9657 +#define SBFLAGST 0xe8
9658 +#define SBIDLOW 0xf8
9659 +#define SBIDHIGH 0xfc
9660 +
9661 +#ifndef _LANGUAGE_ASSEMBLY
9662 +
9663 +typedef volatile struct _sbconfig {
9664 + uint32 PAD[2];
9665 + uint32 sbipsflag; /* initiator port ocp slave flag */
9666 + uint32 PAD[3];
9667 + uint32 sbtpsflag; /* target port ocp slave flag */
9668 + uint32 PAD[11];
9669 + uint32 sbtmerrloga; /* (sonics >= 2.3) */
9670 + uint32 PAD;
9671 + uint32 sbtmerrlog; /* (sonics >= 2.3) */
9672 + uint32 PAD[3];
9673 + uint32 sbadmatch3; /* address match3 */
9674 + uint32 PAD;
9675 + uint32 sbadmatch2; /* address match2 */
9676 + uint32 PAD;
9677 + uint32 sbadmatch1; /* address match1 */
9678 + uint32 PAD[7];
9679 + uint32 sbimstate; /* initiator agent state */
9680 + uint32 sbintvec; /* interrupt mask */
9681 + uint32 sbtmstatelow; /* target state */
9682 + uint32 sbtmstatehigh; /* target state */
9683 + uint32 sbbwa0; /* bandwidth allocation table0 */
9684 + uint32 PAD;
9685 + uint32 sbimconfiglow; /* initiator configuration */
9686 + uint32 sbimconfighigh; /* initiator configuration */
9687 + uint32 sbadmatch0; /* address match0 */
9688 + uint32 PAD;
9689 + uint32 sbtmconfiglow; /* target configuration */
9690 + uint32 sbtmconfighigh; /* target configuration */
9691 + uint32 sbbconfig; /* broadcast configuration */
9692 + uint32 PAD;
9693 + uint32 sbbstate; /* broadcast state */
9694 + uint32 PAD[3];
9695 + uint32 sbactcnfg; /* activate configuration */
9696 + uint32 PAD[3];
9697 + uint32 sbflagst; /* current sbflags */
9698 + uint32 PAD[3];
9699 + uint32 sbidlow; /* identification */
9700 + uint32 sbidhigh; /* identification */
9701 +} sbconfig_t;
9702 +
9703 +#endif /* _LANGUAGE_ASSEMBLY */
9704 +
9705 +/* sbipsflag */
9706 +#define SBIPS_INT1_MASK 0x3f /* which sbflags get routed to mips interrupt 1 */
9707 +#define SBIPS_INT1_SHIFT 0
9708 +#define SBIPS_INT2_MASK 0x3f00 /* which sbflags get routed to mips interrupt 2 */
9709 +#define SBIPS_INT2_SHIFT 8
9710 +#define SBIPS_INT3_MASK 0x3f0000 /* which sbflags get routed to mips interrupt 3 */
9711 +#define SBIPS_INT3_SHIFT 16
9712 +#define SBIPS_INT4_MASK 0x3f000000 /* which sbflags get routed to mips interrupt 4 */
9713 +#define SBIPS_INT4_SHIFT 24
9714 +
9715 +/* sbtpsflag */
9716 +#define SBTPS_NUM0_MASK 0x3f /* interrupt sbFlag # generated by this core */
9717 +#define SBTPS_F0EN0 0x40 /* interrupt is always sent on the backplane */
9718 +
9719 +/* sbtmerrlog */
9720 +#define SBTMEL_CM 0x00000007 /* command */
9721 +#define SBTMEL_CI 0x0000ff00 /* connection id */
9722 +#define SBTMEL_EC 0x0f000000 /* error code */
9723 +#define SBTMEL_ME 0x80000000 /* multiple error */
9724 +
9725 +/* sbimstate */
9726 +#define SBIM_PC 0xf /* pipecount */
9727 +#define SBIM_AP_MASK 0x30 /* arbitration policy */
9728 +#define SBIM_AP_BOTH 0x00 /* use both timeslaces and token */
9729 +#define SBIM_AP_TS 0x10 /* use timesliaces only */
9730 +#define SBIM_AP_TK 0x20 /* use token only */
9731 +#define SBIM_AP_RSV 0x30 /* reserved */
9732 +#define SBIM_IBE 0x20000 /* inbanderror */
9733 +#define SBIM_TO 0x40000 /* timeout */
9734 +#define SBIM_BY 0x01800000 /* busy (sonics >= 2.3) */
9735 +#define SBIM_RJ 0x02000000 /* reject (sonics >= 2.3) */
9736 +
9737 +/* sbtmstatelow */
9738 +#define SBTML_RESET 0x1 /* reset */
9739 +#define SBTML_REJ_MASK 0x6 /* reject */
9740 +#define SBTML_REJ_SHIFT 1
9741 +#define SBTML_CLK 0x10000 /* clock enable */
9742 +#define SBTML_FGC 0x20000 /* force gated clocks on */
9743 +#define SBTML_FL_MASK 0x3ffc0000 /* core-specific flags */
9744 +#define SBTML_PE 0x40000000 /* pme enable */
9745 +#define SBTML_BE 0x80000000 /* bist enable */
9746 +
9747 +/* sbtmstatehigh */
9748 +#define SBTMH_SERR 0x1 /* serror */
9749 +#define SBTMH_INT 0x2 /* interrupt */
9750 +#define SBTMH_BUSY 0x4 /* busy */
9751 +#define SBTMH_TO 0x00000020 /* timeout (sonics >= 2.3) */
9752 +#define SBTMH_FL_MASK 0x1fff0000 /* core-specific flags */
9753 +#define SBTMH_DMA64 0x10000000 /* supports DMA with 64-bit addresses */
9754 +#define SBTMH_GCR 0x20000000 /* gated clock request */
9755 +#define SBTMH_BISTF 0x40000000 /* bist failed */
9756 +#define SBTMH_BISTD 0x80000000 /* bist done */
9757 +
9758 +
9759 +/* sbbwa0 */
9760 +#define SBBWA_TAB0_MASK 0xffff /* lookup table 0 */
9761 +#define SBBWA_TAB1_MASK 0xffff /* lookup table 1 */
9762 +#define SBBWA_TAB1_SHIFT 16
9763 +
9764 +/* sbimconfiglow */
9765 +#define SBIMCL_STO_MASK 0x7 /* service timeout */
9766 +#define SBIMCL_RTO_MASK 0x70 /* request timeout */
9767 +#define SBIMCL_RTO_SHIFT 4
9768 +#define SBIMCL_CID_MASK 0xff0000 /* connection id */
9769 +#define SBIMCL_CID_SHIFT 16
9770 +
9771 +/* sbimconfighigh */
9772 +#define SBIMCH_IEM_MASK 0xc /* inband error mode */
9773 +#define SBIMCH_TEM_MASK 0x30 /* timeout error mode */
9774 +#define SBIMCH_TEM_SHIFT 4
9775 +#define SBIMCH_BEM_MASK 0xc0 /* bus error mode */
9776 +#define SBIMCH_BEM_SHIFT 6
9777 +
9778 +/* sbadmatch0 */
9779 +#define SBAM_TYPE_MASK 0x3 /* address type */
9780 +#define SBAM_AD64 0x4 /* reserved */
9781 +#define SBAM_ADINT0_MASK 0xf8 /* type0 size */
9782 +#define SBAM_ADINT0_SHIFT 3
9783 +#define SBAM_ADINT1_MASK 0x1f8 /* type1 size */
9784 +#define SBAM_ADINT1_SHIFT 3
9785 +#define SBAM_ADINT2_MASK 0x1f8 /* type2 size */
9786 +#define SBAM_ADINT2_SHIFT 3
9787 +#define SBAM_ADEN 0x400 /* enable */
9788 +#define SBAM_ADNEG 0x800 /* negative decode */
9789 +#define SBAM_BASE0_MASK 0xffffff00 /* type0 base address */
9790 +#define SBAM_BASE0_SHIFT 8
9791 +#define SBAM_BASE1_MASK 0xfffff000 /* type1 base address for the core */
9792 +#define SBAM_BASE1_SHIFT 12
9793 +#define SBAM_BASE2_MASK 0xffff0000 /* type2 base address for the core */
9794 +#define SBAM_BASE2_SHIFT 16
9795 +
9796 +/* sbtmconfiglow */
9797 +#define SBTMCL_CD_MASK 0xff /* clock divide */
9798 +#define SBTMCL_CO_MASK 0xf800 /* clock offset */
9799 +#define SBTMCL_CO_SHIFT 11
9800 +#define SBTMCL_IF_MASK 0xfc0000 /* interrupt flags */
9801 +#define SBTMCL_IF_SHIFT 18
9802 +#define SBTMCL_IM_MASK 0x3000000 /* interrupt mode */
9803 +#define SBTMCL_IM_SHIFT 24
9804 +
9805 +/* sbtmconfighigh */
9806 +#define SBTMCH_BM_MASK 0x3 /* busy mode */
9807 +#define SBTMCH_RM_MASK 0x3 /* retry mode */
9808 +#define SBTMCH_RM_SHIFT 2
9809 +#define SBTMCH_SM_MASK 0x30 /* stop mode */
9810 +#define SBTMCH_SM_SHIFT 4
9811 +#define SBTMCH_EM_MASK 0x300 /* sb error mode */
9812 +#define SBTMCH_EM_SHIFT 8
9813 +#define SBTMCH_IM_MASK 0xc00 /* int mode */
9814 +#define SBTMCH_IM_SHIFT 10
9815 +
9816 +/* sbbconfig */
9817 +#define SBBC_LAT_MASK 0x3 /* sb latency */
9818 +#define SBBC_MAX0_MASK 0xf0000 /* maxccntr0 */
9819 +#define SBBC_MAX0_SHIFT 16
9820 +#define SBBC_MAX1_MASK 0xf00000 /* maxccntr1 */
9821 +#define SBBC_MAX1_SHIFT 20
9822 +
9823 +/* sbbstate */
9824 +#define SBBS_SRD 0x1 /* st reg disable */
9825 +#define SBBS_HRD 0x2 /* hold reg disable */
9826 +
9827 +/* sbidlow */
9828 +#define SBIDL_CS_MASK 0x3 /* config space */
9829 +#define SBIDL_AR_MASK 0x38 /* # address ranges supported */
9830 +#define SBIDL_AR_SHIFT 3
9831 +#define SBIDL_SYNCH 0x40 /* sync */
9832 +#define SBIDL_INIT 0x80 /* initiator */
9833 +#define SBIDL_MINLAT_MASK 0xf00 /* minimum backplane latency */
9834 +#define SBIDL_MINLAT_SHIFT 8
9835 +#define SBIDL_MAXLAT 0xf000 /* maximum backplane latency */
9836 +#define SBIDL_MAXLAT_SHIFT 12
9837 +#define SBIDL_FIRST 0x10000 /* this initiator is first */
9838 +#define SBIDL_CW_MASK 0xc0000 /* cycle counter width */
9839 +#define SBIDL_CW_SHIFT 18
9840 +#define SBIDL_TP_MASK 0xf00000 /* target ports */
9841 +#define SBIDL_TP_SHIFT 20
9842 +#define SBIDL_IP_MASK 0xf000000 /* initiator ports */
9843 +#define SBIDL_IP_SHIFT 24
9844 +#define SBIDL_RV_MASK 0xf0000000 /* sonics backplane revision code */
9845 +#define SBIDL_RV_SHIFT 28
9846 +#define SBIDL_RV_2_2 0x00000000 /* version 2.2 or earlier */
9847 +#define SBIDL_RV_2_3 0x10000000 /* version 2.3 */
9848 +
9849 +/* sbidhigh */
9850 +#define SBIDH_RC_MASK 0x000f /* revision code */
9851 +#define SBIDH_RCE_MASK 0x7000 /* revision code extension field */
9852 +#define SBIDH_RCE_SHIFT 8
9853 +#define SBCOREREV(sbidh) \
9854 + ((((sbidh) & SBIDH_RCE_MASK) >> SBIDH_RCE_SHIFT) | ((sbidh) & SBIDH_RC_MASK))
9855 +#define SBIDH_CC_MASK 0x8ff0 /* core code */
9856 +#define SBIDH_CC_SHIFT 4
9857 +#define SBIDH_VC_MASK 0xffff0000 /* vendor code */
9858 +#define SBIDH_VC_SHIFT 16
9859 +
9860 +#define SB_COMMIT 0xfd8 /* update buffered registers value */
9861 +
9862 +/* vendor codes */
9863 +#define SB_VEND_BCM 0x4243 /* Broadcom's SB vendor code */
9864 +
9865 +/* core codes */
9866 +#define SB_CC 0x800 /* chipcommon core */
9867 +#define SB_ILINE20 0x801 /* iline20 core */
9868 +#define SB_SDRAM 0x803 /* sdram core */
9869 +#define SB_PCI 0x804 /* pci core */
9870 +#define SB_MIPS 0x805 /* mips core */
9871 +#define SB_ENET 0x806 /* enet mac core */
9872 +#define SB_CODEC 0x807 /* v90 codec core */
9873 +#define SB_USB 0x808 /* usb 1.1 host/device core */
9874 +#define SB_ADSL 0x809 /* ADSL core */
9875 +#define SB_ILINE100 0x80a /* iline100 core */
9876 +#define SB_IPSEC 0x80b /* ipsec core */
9877 +#define SB_PCMCIA 0x80d /* pcmcia core */
9878 +#define SB_SOCRAM 0x80e /* internal memory core */
9879 +#define SB_MEMC 0x80f /* memc sdram core */
9880 +#define SB_EXTIF 0x811 /* external interface core */
9881 +#define SB_D11 0x812 /* 802.11 MAC core */
9882 +#define SB_MIPS33 0x816 /* mips3302 core */
9883 +#define SB_USB11H 0x817 /* usb 1.1 host core */
9884 +#define SB_USB11D 0x818 /* usb 1.1 device core */
9885 +#define SB_USB20H 0x819 /* usb 2.0 host core */
9886 +#define SB_USB20D 0x81a /* usb 2.0 device core */
9887 +#define SB_SDIOH 0x81b /* sdio host core */
9888 +#define SB_ROBO 0x81c /* roboswitch core */
9889 +#define SB_ATA100 0x81d /* parallel ATA core */
9890 +#define SB_SATAXOR 0x81e /* serial ATA & XOR DMA core */
9891 +#define SB_GIGETH 0x81f /* gigabit ethernet core */
9892 +#define SB_PCIE 0x820 /* pci express core */
9893 +#define SB_SRAMC 0x822 /* SRAM controller core */
9894 +#define SB_MINIMAC 0x823 /* MINI MAC/phy core */
9895 +
9896 +#define SB_CC_IDX 0 /* chipc, when present, is always core 0 */
9897 +
9898 +/* Not really related to Silicon Backplane, but a couple of software
9899 + * conventions for the use the flash space:
9900 + */
9901 +
9902 +/* Minumum amount of flash we support */
9903 +#define FLASH_MIN 0x00020000 /* Minimum flash size */
9904 +
9905 +/* A boot/binary may have an embedded block that describes its size */
9906 +#define BISZ_OFFSET 0x3e0 /* At this offset into the binary */
9907 +#define BISZ_MAGIC 0x4249535a /* Marked with this value: 'BISZ' */
9908 +#define BISZ_MAGIC_IDX 0 /* Word 0: magic */
9909 +#define BISZ_TXTST_IDX 1 /* 1: text start */
9910 +#define BISZ_TXTEND_IDX 2 /* 2: text start */
9911 +#define BISZ_DATAST_IDX 3 /* 3: text start */
9912 +#define BISZ_DATAEND_IDX 4 /* 4: text start */
9913 +#define BISZ_BSSST_IDX 5 /* 5: text start */
9914 +#define BISZ_BSSEND_IDX 6 /* 6: text start */
9915 +#define BISZ_SIZE 7 /* descriptor size in 32-bit intergers */
9916 +
9917 +#endif /* _SBCONFIG_H */
9918 diff -urN linux.old/arch/mips/bcm947xx/include/sbextif.h linux.dev/arch/mips/bcm947xx/include/sbextif.h
9919 --- linux.old/arch/mips/bcm947xx/include/sbextif.h 1970-01-01 01:00:00.000000000 +0100
9920 +++ linux.dev/arch/mips/bcm947xx/include/sbextif.h 2005-12-28 16:37:32.898262750 +0100
9921 @@ -0,0 +1,242 @@
9922 +/*
9923 + * Hardware-specific External Interface I/O core definitions
9924 + * for the BCM47xx family of SiliconBackplane-based chips.
9925 + *
9926 + * The External Interface core supports a total of three external chip selects
9927 + * supporting external interfaces. One of the external chip selects is
9928 + * used for Flash, one is used for PCMCIA, and the other may be
9929 + * programmed to support either a synchronous interface or an
9930 + * asynchronous interface. The asynchronous interface can be used to
9931 + * support external devices such as UARTs and the BCM2019 Bluetooth
9932 + * baseband processor.
9933 + * The external interface core also contains 2 on-chip 16550 UARTs, clock
9934 + * frequency control, a watchdog interrupt timer, and a GPIO interface.
9935 + *
9936 + * Copyright 2005, Broadcom Corporation
9937 + * All Rights Reserved.
9938 + *
9939 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
9940 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9941 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
9942 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
9943 + * $Id$
9944 + */
9945 +
9946 +#ifndef _SBEXTIF_H
9947 +#define _SBEXTIF_H
9948 +
9949 +/* external interface address space */
9950 +#define EXTIF_PCMCIA_MEMBASE(x) (x)
9951 +#define EXTIF_PCMCIA_IOBASE(x) ((x) + 0x100000)
9952 +#define EXTIF_PCMCIA_CFGBASE(x) ((x) + 0x200000)
9953 +#define EXTIF_CFGIF_BASE(x) ((x) + 0x800000)
9954 +#define EXTIF_FLASH_BASE(x) ((x) + 0xc00000)
9955 +
9956 +/* cpp contortions to concatenate w/arg prescan */
9957 +#ifndef PAD
9958 +#define _PADLINE(line) pad ## line
9959 +#define _XSTR(line) _PADLINE(line)
9960 +#define PAD _XSTR(__LINE__)
9961 +#endif /* PAD */
9962 +
9963 +/*
9964 + * The multiple instances of output and output enable registers
9965 + * are present to allow driver software for multiple cores to control
9966 + * gpio outputs without needing to share a single register pair.
9967 + */
9968 +struct gpiouser {
9969 + uint32 out;
9970 + uint32 outen;
9971 +};
9972 +#define NGPIOUSER 5
9973 +
9974 +typedef volatile struct {
9975 + uint32 corecontrol;
9976 + uint32 extstatus;
9977 + uint32 PAD[2];
9978 +
9979 + /* pcmcia control registers */
9980 + uint32 pcmcia_config;
9981 + uint32 pcmcia_memwait;
9982 + uint32 pcmcia_attrwait;
9983 + uint32 pcmcia_iowait;
9984 +
9985 + /* programmable interface control registers */
9986 + uint32 prog_config;
9987 + uint32 prog_waitcount;
9988 +
9989 + /* flash control registers */
9990 + uint32 flash_config;
9991 + uint32 flash_waitcount;
9992 + uint32 PAD[4];
9993 +
9994 + uint32 watchdog;
9995 +
9996 + /* clock control */
9997 + uint32 clockcontrol_n;
9998 + uint32 clockcontrol_sb;
9999 + uint32 clockcontrol_pci;
10000 + uint32 clockcontrol_mii;
10001 + uint32 PAD[3];
10002 +
10003 + /* gpio */
10004 + uint32 gpioin;
10005 + struct gpiouser gpio[NGPIOUSER];
10006 + uint32 PAD;
10007 + uint32 ejtagouten;
10008 + uint32 gpiointpolarity;
10009 + uint32 gpiointmask;
10010 + uint32 PAD[153];
10011 +
10012 + uint8 uartdata;
10013 + uint8 PAD[3];
10014 + uint8 uartimer;
10015 + uint8 PAD[3];
10016 + uint8 uartfcr;
10017 + uint8 PAD[3];
10018 + uint8 uartlcr;
10019 + uint8 PAD[3];
10020 + uint8 uartmcr;
10021 + uint8 PAD[3];
10022 + uint8 uartlsr;
10023 + uint8 PAD[3];
10024 + uint8 uartmsr;
10025 + uint8 PAD[3];
10026 + uint8 uartscratch;
10027 + uint8 PAD[3];
10028 +} extifregs_t;
10029 +
10030 +/* corecontrol */
10031 +#define CC_UE (1 << 0) /* uart enable */
10032 +
10033 +/* extstatus */
10034 +#define ES_EM (1 << 0) /* endian mode (ro) */
10035 +#define ES_EI (1 << 1) /* external interrupt pin (ro) */
10036 +#define ES_GI (1 << 2) /* gpio interrupt pin (ro) */
10037 +
10038 +/* gpio bit mask */
10039 +#define GPIO_BIT0 (1 << 0)
10040 +#define GPIO_BIT1 (1 << 1)
10041 +#define GPIO_BIT2 (1 << 2)
10042 +#define GPIO_BIT3 (1 << 3)
10043 +#define GPIO_BIT4 (1 << 4)
10044 +#define GPIO_BIT5 (1 << 5)
10045 +#define GPIO_BIT6 (1 << 6)
10046 +#define GPIO_BIT7 (1 << 7)
10047 +
10048 +
10049 +/* pcmcia/prog/flash_config */
10050 +#define CF_EN (1 << 0) /* enable */
10051 +#define CF_EM_MASK 0xe /* mode */
10052 +#define CF_EM_SHIFT 1
10053 +#define CF_EM_FLASH 0x0 /* flash/asynchronous mode */
10054 +#define CF_EM_SYNC 0x2 /* synchronous mode */
10055 +#define CF_EM_PCMCIA 0x4 /* pcmcia mode */
10056 +#define CF_DS (1 << 4) /* destsize: 0=8bit, 1=16bit */
10057 +#define CF_BS (1 << 5) /* byteswap */
10058 +#define CF_CD_MASK 0xc0 /* clock divider */
10059 +#define CF_CD_SHIFT 6
10060 +#define CF_CD_DIV2 0x0 /* backplane/2 */
10061 +#define CF_CD_DIV3 0x40 /* backplane/3 */
10062 +#define CF_CD_DIV4 0x80 /* backplane/4 */
10063 +#define CF_CE (1 << 8) /* clock enable */
10064 +#define CF_SB (1 << 9) /* size/bytestrobe (synch only) */
10065 +
10066 +/* pcmcia_memwait */
10067 +#define PM_W0_MASK 0x3f /* waitcount0 */
10068 +#define PM_W1_MASK 0x1f00 /* waitcount1 */
10069 +#define PM_W1_SHIFT 8
10070 +#define PM_W2_MASK 0x1f0000 /* waitcount2 */
10071 +#define PM_W2_SHIFT 16
10072 +#define PM_W3_MASK 0x1f000000 /* waitcount3 */
10073 +#define PM_W3_SHIFT 24
10074 +
10075 +/* pcmcia_attrwait */
10076 +#define PA_W0_MASK 0x3f /* waitcount0 */
10077 +#define PA_W1_MASK 0x1f00 /* waitcount1 */
10078 +#define PA_W1_SHIFT 8
10079 +#define PA_W2_MASK 0x1f0000 /* waitcount2 */
10080 +#define PA_W2_SHIFT 16
10081 +#define PA_W3_MASK 0x1f000000 /* waitcount3 */
10082 +#define PA_W3_SHIFT 24
10083 +
10084 +/* pcmcia_iowait */
10085 +#define PI_W0_MASK 0x3f /* waitcount0 */
10086 +#define PI_W1_MASK 0x1f00 /* waitcount1 */
10087 +#define PI_W1_SHIFT 8
10088 +#define PI_W2_MASK 0x1f0000 /* waitcount2 */
10089 +#define PI_W2_SHIFT 16
10090 +#define PI_W3_MASK 0x1f000000 /* waitcount3 */
10091 +#define PI_W3_SHIFT 24
10092 +
10093 +/* prog_waitcount */
10094 +#define PW_W0_MASK 0x0000001f /* waitcount0 */
10095 +#define PW_W1_MASK 0x00001f00 /* waitcount1 */
10096 +#define PW_W1_SHIFT 8
10097 +#define PW_W2_MASK 0x001f0000 /* waitcount2 */
10098 +#define PW_W2_SHIFT 16
10099 +#define PW_W3_MASK 0x1f000000 /* waitcount3 */
10100 +#define PW_W3_SHIFT 24
10101 +
10102 +#define PW_W0 0x0000000c
10103 +#define PW_W1 0x00000a00
10104 +#define PW_W2 0x00020000
10105 +#define PW_W3 0x01000000
10106 +
10107 +/* flash_waitcount */
10108 +#define FW_W0_MASK 0x1f /* waitcount0 */
10109 +#define FW_W1_MASK 0x1f00 /* waitcount1 */
10110 +#define FW_W1_SHIFT 8
10111 +#define FW_W2_MASK 0x1f0000 /* waitcount2 */
10112 +#define FW_W2_SHIFT 16
10113 +#define FW_W3_MASK 0x1f000000 /* waitcount3 */
10114 +#define FW_W3_SHIFT 24
10115 +
10116 +/* watchdog */
10117 +#define WATCHDOG_CLOCK 48000000 /* Hz */
10118 +
10119 +/* clockcontrol_n */
10120 +#define CN_N1_MASK 0x3f /* n1 control */
10121 +#define CN_N2_MASK 0x3f00 /* n2 control */
10122 +#define CN_N2_SHIFT 8
10123 +
10124 +/* clockcontrol_sb/pci/mii */
10125 +#define CC_M1_MASK 0x3f /* m1 control */
10126 +#define CC_M2_MASK 0x3f00 /* m2 control */
10127 +#define CC_M2_SHIFT 8
10128 +#define CC_M3_MASK 0x3f0000 /* m3 control */
10129 +#define CC_M3_SHIFT 16
10130 +#define CC_MC_MASK 0x1f000000 /* mux control */
10131 +#define CC_MC_SHIFT 24
10132 +
10133 +/* Clock control default values */
10134 +#define CC_DEF_N 0x0009 /* Default values for bcm4710 */
10135 +#define CC_DEF_100 0x04020011
10136 +#define CC_DEF_33 0x11030011
10137 +#define CC_DEF_25 0x11050011
10138 +
10139 +/* Clock control values for 125Mhz */
10140 +#define CC_125_N 0x0802
10141 +#define CC_125_M 0x04020009
10142 +#define CC_125_M25 0x11090009
10143 +#define CC_125_M33 0x11090005
10144 +
10145 +/* Clock control magic field values */
10146 +#define CC_F6_2 0x02 /* A factor of 2 in */
10147 +#define CC_F6_3 0x03 /* 6-bit fields like */
10148 +#define CC_F6_4 0x05 /* N1, M1 or M3 */
10149 +#define CC_F6_5 0x09
10150 +#define CC_F6_6 0x11
10151 +#define CC_F6_7 0x21
10152 +
10153 +#define CC_F5_BIAS 5 /* 5-bit fields get this added */
10154 +
10155 +#define CC_MC_BYPASS 0x08
10156 +#define CC_MC_M1 0x04
10157 +#define CC_MC_M1M2 0x02
10158 +#define CC_MC_M1M2M3 0x01
10159 +#define CC_MC_M1M3 0x11
10160 +
10161 +#define CC_CLOCK_BASE 24000000 /* Half the clock freq. in the 4710 */
10162 +
10163 +#endif /* _SBEXTIF_H */
10164 diff -urN linux.old/arch/mips/bcm947xx/include/sbmemc.h linux.dev/arch/mips/bcm947xx/include/sbmemc.h
10165 --- linux.old/arch/mips/bcm947xx/include/sbmemc.h 1970-01-01 01:00:00.000000000 +0100
10166 +++ linux.dev/arch/mips/bcm947xx/include/sbmemc.h 2005-12-28 16:37:32.902263000 +0100
10167 @@ -0,0 +1,148 @@
10168 +/*
10169 + * BCM47XX Sonics SiliconBackplane DDR/SDRAM controller core hardware definitions.
10170 + *
10171 + * Copyright 2005, Broadcom Corporation
10172 + * All Rights Reserved.
10173 + *
10174 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10175 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10176 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10177 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10178 + *
10179 + * $Id$
10180 + */
10181 +
10182 +#ifndef _SBMEMC_H
10183 +#define _SBMEMC_H
10184 +
10185 +#ifdef _LANGUAGE_ASSEMBLY
10186 +
10187 +#define MEMC_CONTROL 0x00
10188 +#define MEMC_CONFIG 0x04
10189 +#define MEMC_REFRESH 0x08
10190 +#define MEMC_BISTSTAT 0x0c
10191 +#define MEMC_MODEBUF 0x10
10192 +#define MEMC_BKCLS 0x14
10193 +#define MEMC_PRIORINV 0x18
10194 +#define MEMC_DRAMTIM 0x1c
10195 +#define MEMC_INTSTAT 0x20
10196 +#define MEMC_INTMASK 0x24
10197 +#define MEMC_INTINFO 0x28
10198 +#define MEMC_NCDLCTL 0x30
10199 +#define MEMC_RDNCDLCOR 0x34
10200 +#define MEMC_WRNCDLCOR 0x38
10201 +#define MEMC_MISCDLYCTL 0x3c
10202 +#define MEMC_DQSGATENCDL 0x40
10203 +#define MEMC_SPARE 0x44
10204 +#define MEMC_TPADDR 0x48
10205 +#define MEMC_TPDATA 0x4c
10206 +#define MEMC_BARRIER 0x50
10207 +#define MEMC_CORE 0x54
10208 +
10209 +
10210 +#else
10211 +
10212 +/* Sonics side: MEMC core registers */
10213 +typedef volatile struct sbmemcregs {
10214 + uint32 control;
10215 + uint32 config;
10216 + uint32 refresh;
10217 + uint32 biststat;
10218 + uint32 modebuf;
10219 + uint32 bkcls;
10220 + uint32 priorinv;
10221 + uint32 dramtim;
10222 + uint32 intstat;
10223 + uint32 intmask;
10224 + uint32 intinfo;
10225 + uint32 reserved1;
10226 + uint32 ncdlctl;
10227 + uint32 rdncdlcor;
10228 + uint32 wrncdlcor;
10229 + uint32 miscdlyctl;
10230 + uint32 dqsgatencdl;
10231 + uint32 spare;
10232 + uint32 tpaddr;
10233 + uint32 tpdata;
10234 + uint32 barrier;
10235 + uint32 core;
10236 +} sbmemcregs_t;
10237 +
10238 +#endif
10239 +
10240 +/* MEMC Core Init values (OCP ID 0x80f) */
10241 +
10242 +/* For sdr: */
10243 +#define MEMC_SD_CONFIG_INIT 0x00048000
10244 +#define MEMC_SD_DRAMTIM2_INIT 0x000754d8
10245 +#define MEMC_SD_DRAMTIM3_INIT 0x000754da
10246 +#define MEMC_SD_RDNCDLCOR_INIT 0x00000000
10247 +#define MEMC_SD_WRNCDLCOR_INIT 0x49351200
10248 +#define MEMC_SD1_WRNCDLCOR_INIT 0x14500200 /* For corerev 1 (4712) */
10249 +#define MEMC_SD_MISCDLYCTL_INIT 0x00061c1b
10250 +#define MEMC_SD1_MISCDLYCTL_INIT 0x00021416 /* For corerev 1 (4712) */
10251 +#define MEMC_SD_CONTROL_INIT0 0x00000002
10252 +#define MEMC_SD_CONTROL_INIT1 0x00000008
10253 +#define MEMC_SD_CONTROL_INIT2 0x00000004
10254 +#define MEMC_SD_CONTROL_INIT3 0x00000010
10255 +#define MEMC_SD_CONTROL_INIT4 0x00000001
10256 +#define MEMC_SD_MODEBUF_INIT 0x00000000
10257 +#define MEMC_SD_REFRESH_INIT 0x0000840f
10258 +
10259 +
10260 +/* This is for SDRM8X8X4 */
10261 +#define MEMC_SDR_INIT 0x0008
10262 +#define MEMC_SDR_MODE 0x32
10263 +#define MEMC_SDR_NCDL 0x00020032
10264 +#define MEMC_SDR1_NCDL 0x0002020f /* For corerev 1 (4712) */
10265 +
10266 +/* For ddr: */
10267 +#define MEMC_CONFIG_INIT 0x00048000
10268 +#define MEMC_DRAMTIM2_INIT 0x000754d8
10269 +#define MEMC_DRAMTIM25_INIT 0x000754d9
10270 +#define MEMC_RDNCDLCOR_INIT 0x00000000
10271 +#define MEMC_RDNCDLCOR_SIMINIT 0xf6f6f6f6 /* For hdl sim */
10272 +#define MEMC_WRNCDLCOR_INIT 0x49351200
10273 +#define MEMC_1_WRNCDLCOR_INIT 0x14500200
10274 +#define MEMC_DQSGATENCDL_INIT 0x00030000
10275 +#define MEMC_MISCDLYCTL_INIT 0x21061c1b
10276 +#define MEMC_1_MISCDLYCTL_INIT 0x21021400
10277 +#define MEMC_NCDLCTL_INIT 0x00002001
10278 +#define MEMC_CONTROL_INIT0 0x00000002
10279 +#define MEMC_CONTROL_INIT1 0x00000008
10280 +#define MEMC_MODEBUF_INIT0 0x00004000
10281 +#define MEMC_CONTROL_INIT2 0x00000010
10282 +#define MEMC_MODEBUF_INIT1 0x00000100
10283 +#define MEMC_CONTROL_INIT3 0x00000010
10284 +#define MEMC_CONTROL_INIT4 0x00000008
10285 +#define MEMC_REFRESH_INIT 0x0000840f
10286 +#define MEMC_CONTROL_INIT5 0x00000004
10287 +#define MEMC_MODEBUF_INIT2 0x00000000
10288 +#define MEMC_CONTROL_INIT6 0x00000010
10289 +#define MEMC_CONTROL_INIT7 0x00000001
10290 +
10291 +
10292 +/* This is for DDRM16X16X2 */
10293 +#define MEMC_DDR_INIT 0x0009
10294 +#define MEMC_DDR_MODE 0x62
10295 +#define MEMC_DDR_NCDL 0x0005050a
10296 +#define MEMC_DDR1_NCDL 0x00000a0a /* For corerev 1 (4712) */
10297 +
10298 +/* mask for sdr/ddr calibration registers */
10299 +#define MEMC_RDNCDLCOR_RD_MASK 0x000000ff
10300 +#define MEMC_WRNCDLCOR_WR_MASK 0x000000ff
10301 +#define MEMC_DQSGATENCDL_G_MASK 0x000000ff
10302 +
10303 +/* masks for miscdlyctl registers */
10304 +#define MEMC_MISC_SM_MASK 0x30000000
10305 +#define MEMC_MISC_SM_SHIFT 28
10306 +#define MEMC_MISC_SD_MASK 0x0f000000
10307 +#define MEMC_MISC_SD_SHIFT 24
10308 +
10309 +/* hw threshhold for calculating wr/rd for sdr memc */
10310 +#define MEMC_CD_THRESHOLD 128
10311 +
10312 +/* Low bit of init register says if memc is ddr or sdr */
10313 +#define MEMC_CONFIG_DDR 0x00000001
10314 +
10315 +#endif /* _SBMEMC_H */
10316 diff -urN linux.old/arch/mips/bcm947xx/include/sbmips.h linux.dev/arch/mips/bcm947xx/include/sbmips.h
10317 --- linux.old/arch/mips/bcm947xx/include/sbmips.h 1970-01-01 01:00:00.000000000 +0100
10318 +++ linux.dev/arch/mips/bcm947xx/include/sbmips.h 2005-12-28 16:37:32.902263000 +0100
10319 @@ -0,0 +1,62 @@
10320 +/*
10321 + * Broadcom SiliconBackplane MIPS definitions
10322 + *
10323 + * SB MIPS cores are custom MIPS32 processors with SiliconBackplane
10324 + * OCP interfaces. The CP0 processor ID is 0x00024000, where bits
10325 + * 23:16 mean Broadcom and bits 15:8 mean a MIPS core with an OCP
10326 + * interface. The core revision is stored in the SB ID register in SB
10327 + * configuration space.
10328 + *
10329 + * Copyright 2005, Broadcom Corporation
10330 + * All Rights Reserved.
10331 + *
10332 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10333 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10334 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10335 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10336 + *
10337 + * $Id$
10338 + */
10339 +
10340 +#ifndef _SBMIPS_H
10341 +#define _SBMIPS_H
10342 +
10343 +#include <mipsinc.h>
10344 +
10345 +#ifndef _LANGUAGE_ASSEMBLY
10346 +
10347 +/* cpp contortions to concatenate w/arg prescan */
10348 +#ifndef PAD
10349 +#define _PADLINE(line) pad ## line
10350 +#define _XSTR(line) _PADLINE(line)
10351 +#define PAD _XSTR(__LINE__)
10352 +#endif /* PAD */
10353 +
10354 +typedef volatile struct {
10355 + uint32 corecontrol;
10356 + uint32 PAD[2];
10357 + uint32 biststatus;
10358 + uint32 PAD[4];
10359 + uint32 intstatus;
10360 + uint32 intmask;
10361 + uint32 timer;
10362 +} mipsregs_t;
10363 +
10364 +extern uint32 sb_flag(sb_t *sbh);
10365 +extern uint sb_irq(sb_t *sbh);
10366 +
10367 +extern void BCMINIT(sb_serial_init)(sb_t *sbh, void (*add)(void *regs, uint irq, uint baud_base, uint reg_shift));
10368 +
10369 +extern void *sb_jtagm_init(sb_t *sbh, uint clkd, bool exttap);
10370 +extern void sb_jtagm_disable(void *h);
10371 +extern uint32 jtag_rwreg(void *h, uint32 ir, uint32 dr);
10372 +extern void BCMINIT(sb_mips_init)(sb_t *sbh);
10373 +extern uint32 BCMINIT(sb_mips_clock)(sb_t *sbh);
10374 +extern bool BCMINIT(sb_mips_setclock)(sb_t *sbh, uint32 mipsclock, uint32 sbclock, uint32 pciclock);
10375 +extern void BCMINIT(enable_pfc)(uint32 mode);
10376 +extern uint32 BCMINIT(sb_memc_get_ncdl)(sb_t *sbh);
10377 +
10378 +
10379 +#endif /* _LANGUAGE_ASSEMBLY */
10380 +
10381 +#endif /* _SBMIPS_H */
10382 diff -urN linux.old/arch/mips/bcm947xx/include/sbpci.h linux.dev/arch/mips/bcm947xx/include/sbpci.h
10383 --- linux.old/arch/mips/bcm947xx/include/sbpci.h 1970-01-01 01:00:00.000000000 +0100
10384 +++ linux.dev/arch/mips/bcm947xx/include/sbpci.h 2005-12-28 16:37:32.902263000 +0100
10385 @@ -0,0 +1,122 @@
10386 +/*
10387 + * BCM47XX Sonics SiliconBackplane PCI core hardware definitions.
10388 + *
10389 + * $Id$
10390 + * Copyright 2005, Broadcom Corporation
10391 + * All Rights Reserved.
10392 + *
10393 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10394 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10395 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10396 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10397 + */
10398 +
10399 +#ifndef _SBPCI_H
10400 +#define _SBPCI_H
10401 +
10402 +/* cpp contortions to concatenate w/arg prescan */
10403 +#ifndef PAD
10404 +#define _PADLINE(line) pad ## line
10405 +#define _XSTR(line) _PADLINE(line)
10406 +#define PAD _XSTR(__LINE__)
10407 +#endif
10408 +
10409 +/* Sonics side: PCI core and host control registers */
10410 +typedef struct sbpciregs {
10411 + uint32 control; /* PCI control */
10412 + uint32 PAD[3];
10413 + uint32 arbcontrol; /* PCI arbiter control */
10414 + uint32 PAD[3];
10415 + uint32 intstatus; /* Interrupt status */
10416 + uint32 intmask; /* Interrupt mask */
10417 + uint32 sbtopcimailbox; /* Sonics to PCI mailbox */
10418 + uint32 PAD[9];
10419 + uint32 bcastaddr; /* Sonics broadcast address */
10420 + uint32 bcastdata; /* Sonics broadcast data */
10421 + uint32 PAD[2];
10422 + uint32 gpioin; /* ro: gpio input (>=rev2) */
10423 + uint32 gpioout; /* rw: gpio output (>=rev2) */
10424 + uint32 gpioouten; /* rw: gpio output enable (>= rev2) */
10425 + uint32 gpiocontrol; /* rw: gpio control (>= rev2) */
10426 + uint32 PAD[36];
10427 + uint32 sbtopci0; /* Sonics to PCI translation 0 */
10428 + uint32 sbtopci1; /* Sonics to PCI translation 1 */
10429 + uint32 sbtopci2; /* Sonics to PCI translation 2 */
10430 + uint32 PAD[445];
10431 + uint16 sprom[36]; /* SPROM shadow Area */
10432 + uint32 PAD[46];
10433 +} sbpciregs_t;
10434 +
10435 +/* PCI control */
10436 +#define PCI_RST_OE 0x01 /* When set, drives PCI_RESET out to pin */
10437 +#define PCI_RST 0x02 /* Value driven out to pin */
10438 +#define PCI_CLK_OE 0x04 /* When set, drives clock as gated by PCI_CLK out to pin */
10439 +#define PCI_CLK 0x08 /* Gate for clock driven out to pin */
10440 +
10441 +/* PCI arbiter control */
10442 +#define PCI_INT_ARB 0x01 /* When set, use an internal arbiter */
10443 +#define PCI_EXT_ARB 0x02 /* When set, use an external arbiter */
10444 +#define PCI_PARKID_MASK 0x06 /* Selects which agent is parked on an idle bus */
10445 +#define PCI_PARKID_SHIFT 1
10446 +#define PCI_PARKID_LAST 0 /* Last requestor */
10447 +#define PCI_PARKID_4710 1 /* 4710 */
10448 +#define PCI_PARKID_EXTREQ0 2 /* External requestor 0 */
10449 +#define PCI_PARKID_EXTREQ1 3 /* External requestor 1 */
10450 +
10451 +/* Interrupt status/mask */
10452 +#define PCI_INTA 0x01 /* PCI INTA# is asserted */
10453 +#define PCI_INTB 0x02 /* PCI INTB# is asserted */
10454 +#define PCI_SERR 0x04 /* PCI SERR# has been asserted (write one to clear) */
10455 +#define PCI_PERR 0x08 /* PCI PERR# has been asserted (write one to clear) */
10456 +#define PCI_PME 0x10 /* PCI PME# is asserted */
10457 +
10458 +/* (General) PCI/SB mailbox interrupts, two bits per pci function */
10459 +#define MAILBOX_F0_0 0x100 /* function 0, int 0 */
10460 +#define MAILBOX_F0_1 0x200 /* function 0, int 1 */
10461 +#define MAILBOX_F1_0 0x400 /* function 1, int 0 */
10462 +#define MAILBOX_F1_1 0x800 /* function 1, int 1 */
10463 +#define MAILBOX_F2_0 0x1000 /* function 2, int 0 */
10464 +#define MAILBOX_F2_1 0x2000 /* function 2, int 1 */
10465 +#define MAILBOX_F3_0 0x4000 /* function 3, int 0 */
10466 +#define MAILBOX_F3_1 0x8000 /* function 3, int 1 */
10467 +
10468 +/* Sonics broadcast address */
10469 +#define BCAST_ADDR_MASK 0xff /* Broadcast register address */
10470 +
10471 +/* Sonics to PCI translation types */
10472 +#define SBTOPCI0_MASK 0xfc000000
10473 +#define SBTOPCI1_MASK 0xfc000000
10474 +#define SBTOPCI2_MASK 0xc0000000
10475 +#define SBTOPCI_MEM 0
10476 +#define SBTOPCI_IO 1
10477 +#define SBTOPCI_CFG0 2
10478 +#define SBTOPCI_CFG1 3
10479 +#define SBTOPCI_PREF 0x4 /* prefetch enable */
10480 +#define SBTOPCI_BURST 0x8 /* burst enable */
10481 +#define SBTOPCI_RC_MASK 0x30 /* read command (>= rev11) */
10482 +#define SBTOPCI_RC_READ 0x00 /* memory read */
10483 +#define SBTOPCI_RC_READLINE 0x10 /* memory read line */
10484 +#define SBTOPCI_RC_READMULTI 0x20 /* memory read multiple */
10485 +
10486 +/* PCI core index in SROM shadow area */
10487 +#define SRSH_PI_OFFSET 0 /* first word */
10488 +#define SRSH_PI_MASK 0xf000 /* bit 15:12 */
10489 +#define SRSH_PI_SHIFT 12 /* bit 15:12 */
10490 +
10491 +/* PCI side: Reserved PCI configuration registers (see pcicfg.h) */
10492 +#define cap_list rsvd_a[0]
10493 +#define bar0_window dev_dep[0x80 - 0x40]
10494 +#define bar1_window dev_dep[0x84 - 0x40]
10495 +#define sprom_control dev_dep[0x88 - 0x40]
10496 +
10497 +#ifndef _LANGUAGE_ASSEMBLY
10498 +
10499 +extern int sbpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len);
10500 +extern int sbpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len);
10501 +extern void sbpci_ban(uint16 core);
10502 +extern int sbpci_init(sb_t *sbh);
10503 +extern void sbpci_check(sb_t *sbh);
10504 +
10505 +#endif /* !_LANGUAGE_ASSEMBLY */
10506 +
10507 +#endif /* _SBPCI_H */
10508 diff -urN linux.old/arch/mips/bcm947xx/include/sbsdram.h linux.dev/arch/mips/bcm947xx/include/sbsdram.h
10509 --- linux.old/arch/mips/bcm947xx/include/sbsdram.h 1970-01-01 01:00:00.000000000 +0100
10510 +++ linux.dev/arch/mips/bcm947xx/include/sbsdram.h 2005-12-28 16:37:32.902263000 +0100
10511 @@ -0,0 +1,75 @@
10512 +/*
10513 + * BCM47XX Sonics SiliconBackplane SDRAM controller core hardware definitions.
10514 + *
10515 + * Copyright 2005, Broadcom Corporation
10516 + * All Rights Reserved.
10517 + *
10518 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10519 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10520 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10521 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10522 + * $Id$
10523 + */
10524 +
10525 +#ifndef _SBSDRAM_H
10526 +#define _SBSDRAM_H
10527 +
10528 +#ifndef _LANGUAGE_ASSEMBLY
10529 +
10530 +/* Sonics side: SDRAM core registers */
10531 +typedef volatile struct sbsdramregs {
10532 + uint32 initcontrol; /* Generates external SDRAM initialization sequence */
10533 + uint32 config; /* Initializes external SDRAM mode register */
10534 + uint32 refresh; /* Controls external SDRAM refresh rate */
10535 + uint32 pad1;
10536 + uint32 pad2;
10537 +} sbsdramregs_t;
10538 +
10539 +#endif
10540 +
10541 +/* SDRAM initialization control (initcontrol) register bits */
10542 +#define SDRAM_CBR 0x0001 /* Writing 1 generates refresh cycle and toggles bit */
10543 +#define SDRAM_PRE 0x0002 /* Writing 1 generates precharge cycle and toggles bit */
10544 +#define SDRAM_MRS 0x0004 /* Writing 1 generates mode register select cycle and toggles bit */
10545 +#define SDRAM_EN 0x0008 /* When set, enables access to SDRAM */
10546 +#define SDRAM_16Mb 0x0000 /* Use 16 Megabit SDRAM */
10547 +#define SDRAM_64Mb 0x0010 /* Use 64 Megabit SDRAM */
10548 +#define SDRAM_128Mb 0x0020 /* Use 128 Megabit SDRAM */
10549 +#define SDRAM_RSVMb 0x0030 /* Use special SDRAM */
10550 +#define SDRAM_RST 0x0080 /* Writing 1 causes soft reset of controller */
10551 +#define SDRAM_SELFREF 0x0100 /* Writing 1 enables self refresh mode */
10552 +#define SDRAM_PWRDOWN 0x0200 /* Writing 1 causes controller to power down */
10553 +#define SDRAM_32BIT 0x0400 /* When set, indicates 32 bit SDRAM interface */
10554 +#define SDRAM_9BITCOL 0x0800 /* When set, indicates 9 bit column */
10555 +
10556 +/* SDRAM configuration (config) register bits */
10557 +#define SDRAM_BURSTFULL 0x0000 /* Use full page bursts */
10558 +#define SDRAM_BURST8 0x0001 /* Use burst of 8 */
10559 +#define SDRAM_BURST4 0x0002 /* Use burst of 4 */
10560 +#define SDRAM_BURST2 0x0003 /* Use burst of 2 */
10561 +#define SDRAM_CAS3 0x0000 /* Use CAS latency of 3 */
10562 +#define SDRAM_CAS2 0x0004 /* Use CAS latency of 2 */
10563 +
10564 +/* SDRAM refresh control (refresh) register bits */
10565 +#define SDRAM_REF(p) (((p)&0xff) | SDRAM_REF_EN) /* Refresh period */
10566 +#define SDRAM_REF_EN 0x8000 /* Writing 1 enables periodic refresh */
10567 +
10568 +/* SDRAM Core default Init values (OCP ID 0x803) */
10569 +#define SDRAM_INIT MEM4MX16X2
10570 +#define SDRAM_CONFIG SDRAM_BURSTFULL
10571 +#define SDRAM_REFRESH SDRAM_REF(0x40)
10572 +
10573 +#define MEM1MX16 0x009 /* 2 MB */
10574 +#define MEM1MX16X2 0x409 /* 4 MB */
10575 +#define MEM2MX8X2 0x809 /* 4 MB */
10576 +#define MEM2MX8X4 0xc09 /* 8 MB */
10577 +#define MEM2MX32 0x439 /* 8 MB */
10578 +#define MEM4MX16 0x019 /* 8 MB */
10579 +#define MEM4MX16X2 0x419 /* 16 MB */
10580 +#define MEM8MX8X2 0x819 /* 16 MB */
10581 +#define MEM8MX16 0x829 /* 16 MB */
10582 +#define MEM4MX32 0x429 /* 16 MB */
10583 +#define MEM8MX8X4 0xc19 /* 32 MB */
10584 +#define MEM8MX16X2 0xc29 /* 32 MB */
10585 +
10586 +#endif /* _SBSDRAM_H */
10587 diff -urN linux.old/arch/mips/bcm947xx/include/sbutils.h linux.dev/arch/mips/bcm947xx/include/sbutils.h
10588 --- linux.old/arch/mips/bcm947xx/include/sbutils.h 1970-01-01 01:00:00.000000000 +0100
10589 +++ linux.dev/arch/mips/bcm947xx/include/sbutils.h 2005-12-28 16:37:32.902263000 +0100
10590 @@ -0,0 +1,136 @@
10591 +/*
10592 + * Misc utility routines for accessing chip-specific features
10593 + * of Broadcom HNBU SiliconBackplane-based chips.
10594 + *
10595 + * Copyright 2005, Broadcom Corporation
10596 + * All Rights Reserved.
10597 + *
10598 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10599 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10600 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10601 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10602 + *
10603 + * $Id$
10604 + */
10605 +
10606 +#ifndef _sbutils_h_
10607 +#define _sbutils_h_
10608 +
10609 +/*
10610 + * Datastructure to export all chip specific common variables
10611 + * public (read-only) portion of sbutils handle returned by
10612 + * sb_attach()/sb_kattach()
10613 +*/
10614 +
10615 +struct sb_pub {
10616 +
10617 + uint bustype; /* SB_BUS, PCI_BUS */
10618 + uint buscoretype; /* SB_PCI, SB_PCMCIA, SB_PCIE*/
10619 + uint buscorerev; /* buscore rev */
10620 + uint buscoreidx; /* buscore index */
10621 + int ccrev; /* chip common core rev */
10622 + uint boardtype; /* board type */
10623 + uint boardvendor; /* board vendor */
10624 + uint chip; /* chip number */
10625 + uint chiprev; /* chip revision */
10626 + uint chippkg; /* chip package option */
10627 + uint sonicsrev; /* sonics backplane rev */
10628 +};
10629 +
10630 +typedef const struct sb_pub sb_t;
10631 +
10632 +/*
10633 + * Many of the routines below take an 'sbh' handle as their first arg.
10634 + * Allocate this by calling sb_attach(). Free it by calling sb_detach().
10635 + * At any one time, the sbh is logically focused on one particular sb core
10636 + * (the "current core").
10637 + * Use sb_setcore() or sb_setcoreidx() to change the association to another core.
10638 + */
10639 +
10640 +/* exported externs */
10641 +extern sb_t * BCMINIT(sb_attach)(uint pcidev, osl_t *osh, void *regs, uint bustype, void *sdh, char **vars, int *varsz);
10642 +extern sb_t * BCMINIT(sb_kattach)(void);
10643 +extern void sb_detach(sb_t *sbh);
10644 +extern uint BCMINIT(sb_chip)(sb_t *sbh);
10645 +extern uint BCMINIT(sb_chiprev)(sb_t *sbh);
10646 +extern uint BCMINIT(sb_chipcrev)(sb_t *sbh);
10647 +extern uint BCMINIT(sb_chippkg)(sb_t *sbh);
10648 +extern uint BCMINIT(sb_pcirev)(sb_t *sbh);
10649 +extern bool BCMINIT(sb_war16165)(sb_t *sbh);
10650 +extern uint BCMINIT(sb_boardvendor)(sb_t *sbh);
10651 +extern uint BCMINIT(sb_boardtype)(sb_t *sbh);
10652 +extern uint sb_bus(sb_t *sbh);
10653 +extern uint sb_buscoretype(sb_t *sbh);
10654 +extern uint sb_buscorerev(sb_t *sbh);
10655 +extern uint sb_corelist(sb_t *sbh, uint coreid[]);
10656 +extern uint sb_coreid(sb_t *sbh);
10657 +extern uint sb_coreidx(sb_t *sbh);
10658 +extern uint sb_coreunit(sb_t *sbh);
10659 +extern uint sb_corevendor(sb_t *sbh);
10660 +extern uint sb_corerev(sb_t *sbh);
10661 +extern void *sb_osh(sb_t *sbh);
10662 +extern void *sb_coreregs(sb_t *sbh);
10663 +extern uint32 sb_coreflags(sb_t *sbh, uint32 mask, uint32 val);
10664 +extern uint32 sb_coreflagshi(sb_t *sbh, uint32 mask, uint32 val);
10665 +extern bool sb_iscoreup(sb_t *sbh);
10666 +extern void *sb_setcoreidx(sb_t *sbh, uint coreidx);
10667 +extern void *sb_setcore(sb_t *sbh, uint coreid, uint coreunit);
10668 +extern int sb_corebist(sb_t *sbh, uint coreid, uint coreunit);
10669 +extern void sb_commit(sb_t *sbh);
10670 +extern uint32 sb_base(uint32 admatch);
10671 +extern uint32 sb_size(uint32 admatch);
10672 +extern void sb_core_reset(sb_t *sbh, uint32 bits);
10673 +extern void sb_core_tofixup(sb_t *sbh);
10674 +extern void sb_core_disable(sb_t *sbh, uint32 bits);
10675 +extern uint32 sb_clock_rate(uint32 pll_type, uint32 n, uint32 m);
10676 +extern uint32 sb_clock(sb_t *sbh);
10677 +extern void sb_pci_setup(sb_t *sbh, uint coremask);
10678 +extern void sb_watchdog(sb_t *sbh, uint ticks);
10679 +extern void *sb_gpiosetcore(sb_t *sbh);
10680 +extern uint32 sb_gpiocontrol(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
10681 +extern uint32 sb_gpioouten(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
10682 +extern uint32 sb_gpioout(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
10683 +extern uint32 sb_gpioin(sb_t *sbh);
10684 +extern uint32 sb_gpiointpolarity(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
10685 +extern uint32 sb_gpiointmask(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
10686 +extern uint32 sb_gpioled(sb_t *sbh, uint32 mask, uint32 val);
10687 +extern uint32 sb_gpioreserve(sb_t *sbh, uint32 gpio_num, uint8 priority);
10688 +extern uint32 sb_gpiorelease(sb_t *sbh, uint32 gpio_num, uint8 priority);
10689 +
10690 +extern void sb_clkctl_init(sb_t *sbh);
10691 +extern uint16 sb_clkctl_fast_pwrup_delay(sb_t *sbh);
10692 +extern bool sb_clkctl_clk(sb_t *sbh, uint mode);
10693 +extern int sb_clkctl_xtal(sb_t *sbh, uint what, bool on);
10694 +extern void sb_register_intr_callback(sb_t *sbh, void *intrsoff_fn,
10695 + void *intrsrestore_fn, void *intrsenabled_fn, void *intr_arg);
10696 +extern uint32 sb_set_initiator_to(sb_t *sbh, uint32 to);
10697 +extern void sb_corepciid(sb_t *sbh, uint16 *pcivendor, uint16 *pcidevice,
10698 + uint8 *pciclass, uint8 *pcisubclass, uint8 *pciprogif);
10699 +extern uint32 sb_gpiotimerval(sb_t *sbh, uint32 mask, uint32 val);
10700 +
10701 +
10702 +
10703 +/*
10704 +* Build device path. Path size must be >= SB_DEVPATH_BUFSZ.
10705 +* The returned path is NULL terminated and has trailing '/'.
10706 +* Return 0 on success, nonzero otherwise.
10707 +*/
10708 +extern int sb_devpath(sb_t *sbh, char *path, int size);
10709 +
10710 +/* clkctl xtal what flags */
10711 +#define XTAL 0x1 /* primary crystal oscillator (2050) */
10712 +#define PLL 0x2 /* main chip pll */
10713 +
10714 +/* clkctl clk mode */
10715 +#define CLK_FAST 0 /* force fast (pll) clock */
10716 +#define CLK_DYNAMIC 2 /* enable dynamic clock control */
10717 +
10718 +
10719 +/* GPIO usage priorities */
10720 +#define GPIO_DRV_PRIORITY 0
10721 +#define GPIO_APP_PRIORITY 1
10722 +
10723 +/* device path */
10724 +#define SB_DEVPATH_BUFSZ 16 /* min buffer size in bytes */
10725 +
10726 +#endif /* _sbutils_h_ */
10727 diff -urN linux.old/arch/mips/bcm947xx/include/sflash.h linux.dev/arch/mips/bcm947xx/include/sflash.h
10728 --- linux.old/arch/mips/bcm947xx/include/sflash.h 1970-01-01 01:00:00.000000000 +0100
10729 +++ linux.dev/arch/mips/bcm947xx/include/sflash.h 2005-12-28 16:37:32.902263000 +0100
10730 @@ -0,0 +1,36 @@
10731 +/*
10732 + * Broadcom SiliconBackplane chipcommon serial flash interface
10733 + *
10734 + * Copyright 2005, Broadcom Corporation
10735 + * All Rights Reserved.
10736 + *
10737 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10738 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10739 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10740 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10741 + *
10742 + * $Id$
10743 + */
10744 +
10745 +#ifndef _sflash_h_
10746 +#define _sflash_h_
10747 +
10748 +#include <typedefs.h>
10749 +#include <sbchipc.h>
10750 +
10751 +struct sflash {
10752 + uint blocksize; /* Block size */
10753 + uint numblocks; /* Number of blocks */
10754 + uint32 type; /* Type */
10755 + uint size; /* Total size in bytes */
10756 +};
10757 +
10758 +/* Utility functions */
10759 +extern int sflash_poll(chipcregs_t *cc, uint offset);
10760 +extern int sflash_read(chipcregs_t *cc, uint offset, uint len, uchar *buf);
10761 +extern int sflash_write(chipcregs_t *cc, uint offset, uint len, const uchar *buf);
10762 +extern int sflash_erase(chipcregs_t *cc, uint offset);
10763 +extern int sflash_commit(chipcregs_t *cc, uint offset, uint len, const uchar *buf);
10764 +extern struct sflash * sflash_init(chipcregs_t *cc);
10765 +
10766 +#endif /* _sflash_h_ */
10767 diff -urN linux.old/arch/mips/bcm947xx/include/trxhdr.h linux.dev/arch/mips/bcm947xx/include/trxhdr.h
10768 --- linux.old/arch/mips/bcm947xx/include/trxhdr.h 1970-01-01 01:00:00.000000000 +0100
10769 +++ linux.dev/arch/mips/bcm947xx/include/trxhdr.h 2005-12-28 16:37:32.902263000 +0100
10770 @@ -0,0 +1,33 @@
10771 +/*
10772 + * TRX image file header format.
10773 + *
10774 + * Copyright 2005, Broadcom Corporation
10775 + * All Rights Reserved.
10776 + *
10777 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10778 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10779 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10780 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10781 + *
10782 + * $Id$
10783 + */
10784 +
10785 +#include <typedefs.h>
10786 +
10787 +#define TRX_MAGIC 0x30524448 /* "HDR0" */
10788 +#define TRX_VERSION 1
10789 +#define TRX_MAX_LEN 0x3A0000
10790 +#define TRX_NO_HEADER 1 /* Do not write TRX header */
10791 +#define TRX_GZ_FILES 0x2 /* Contains up to TRX_MAX_OFFSET individual gzip files */
10792 +#define TRX_MAX_OFFSET 3
10793 +
10794 +struct trx_header {
10795 + uint32 magic; /* "HDR0" */
10796 + uint32 len; /* Length of file including header */
10797 + uint32 crc32; /* 32-bit CRC from flag_version to end of file */
10798 + uint32 flag_version; /* 0:15 flags, 16:31 version */
10799 + uint32 offsets[TRX_MAX_OFFSET]; /* Offsets of partitions from start of header */
10800 +};
10801 +
10802 +/* Compatibility */
10803 +typedef struct trx_header TRXHDR, *PTRXHDR;
10804 diff -urN linux.old/arch/mips/bcm947xx/include/typedefs.h linux.dev/arch/mips/bcm947xx/include/typedefs.h
10805 --- linux.old/arch/mips/bcm947xx/include/typedefs.h 1970-01-01 01:00:00.000000000 +0100
10806 +++ linux.dev/arch/mips/bcm947xx/include/typedefs.h 2005-12-28 16:37:32.906263250 +0100
10807 @@ -0,0 +1,326 @@
10808 +/*
10809 + * Copyright 2005, Broadcom Corporation
10810 + * All Rights Reserved.
10811 + *
10812 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10813 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10814 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10815 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10816 + * $Id$
10817 + */
10818 +
10819 +#ifndef _TYPEDEFS_H_
10820 +#define _TYPEDEFS_H_
10821 +
10822 +
10823 +/* Define 'SITE_TYPEDEFS' in the compile to include a site specific
10824 + * typedef file "site_typedefs.h".
10825 + *
10826 + * If 'SITE_TYPEDEFS' is not defined, then the "Inferred Typedefs"
10827 + * section of this file makes inferences about the compile environment
10828 + * based on defined symbols and possibly compiler pragmas.
10829 + *
10830 + * Following these two sections is the "Default Typedefs"
10831 + * section. This section is only prcessed if 'USE_TYPEDEF_DEFAULTS' is
10832 + * defined. This section has a default set of typedefs and a few
10833 + * proprocessor symbols (TRUE, FALSE, NULL, ...).
10834 + */
10835 +
10836 +#ifdef SITE_TYPEDEFS
10837 +
10838 +/*******************************************************************************
10839 + * Site Specific Typedefs
10840 + *******************************************************************************/
10841 +
10842 +#include "site_typedefs.h"
10843 +
10844 +#else
10845 +
10846 +/*******************************************************************************
10847 + * Inferred Typedefs
10848 + *******************************************************************************/
10849 +
10850 +/* Infer the compile environment based on preprocessor symbols and pramas.
10851 + * Override type definitions as needed, and include configuration dependent
10852 + * header files to define types.
10853 + */
10854 +
10855 +#ifdef __cplusplus
10856 +
10857 +#define TYPEDEF_BOOL
10858 +#ifndef FALSE
10859 +#define FALSE false
10860 +#endif
10861 +#ifndef TRUE
10862 +#define TRUE true
10863 +#endif
10864 +
10865 +#else /* ! __cplusplus */
10866 +
10867 +#if defined(_WIN32)
10868 +
10869 +#define TYPEDEF_BOOL
10870 +typedef unsigned char bool; /* consistent w/BOOL */
10871 +
10872 +#endif /* _WIN32 */
10873 +
10874 +#endif /* ! __cplusplus */
10875 +
10876 +/* use the Windows ULONG_PTR type when compiling for 64 bit */
10877 +#if defined(_WIN64)
10878 +#include <basetsd.h>
10879 +#define TYPEDEF_UINTPTR
10880 +typedef ULONG_PTR uintptr;
10881 +#endif
10882 +
10883 +#ifdef _HNDRTE_
10884 +typedef long unsigned int size_t;
10885 +#endif
10886 +
10887 +#ifdef _MSC_VER /* Microsoft C */
10888 +#define TYPEDEF_INT64
10889 +#define TYPEDEF_UINT64
10890 +typedef signed __int64 int64;
10891 +typedef unsigned __int64 uint64;
10892 +#endif
10893 +
10894 +#if defined(MACOSX) && defined(KERNEL)
10895 +#define TYPEDEF_BOOL
10896 +#endif
10897 +
10898 +
10899 +#if defined(linux)
10900 +#define TYPEDEF_UINT
10901 +#define TYPEDEF_USHORT
10902 +#define TYPEDEF_ULONG
10903 +#endif
10904 +
10905 +#if !defined(linux) && !defined(_WIN32) && !defined(PMON) && !defined(_CFE_) && !defined(_HNDRTE_) && !defined(_MINOSL_)
10906 +#define TYPEDEF_UINT
10907 +#define TYPEDEF_USHORT
10908 +#endif
10909 +
10910 +
10911 +/* Do not support the (u)int64 types with strict ansi for GNU C */
10912 +#if defined(__GNUC__) && defined(__STRICT_ANSI__)
10913 +#define TYPEDEF_INT64
10914 +#define TYPEDEF_UINT64
10915 +#endif
10916 +
10917 +/* ICL accepts unsigned 64 bit type only, and complains in ANSI mode
10918 + * for singned or unsigned */
10919 +#if defined(__ICL)
10920 +
10921 +#define TYPEDEF_INT64
10922 +
10923 +#if defined(__STDC__)
10924 +#define TYPEDEF_UINT64
10925 +#endif
10926 +
10927 +#endif /* __ICL */
10928 +
10929 +
10930 +#if !defined(_WIN32) && !defined(PMON) && !defined(_CFE_) && !defined(_HNDRTE_) && !defined(_MINOSL_)
10931 +
10932 +/* pick up ushort & uint from standard types.h */
10933 +#if defined(linux) && defined(__KERNEL__)
10934 +
10935 +#include <linux/types.h> /* sys/types.h and linux/types.h are oil and water */
10936 +
10937 +#else
10938 +
10939 +#include <sys/types.h>
10940 +
10941 +#endif
10942 +
10943 +#endif /* !_WIN32 && !PMON && !_CFE_ && !_HNDRTE_ && !_MINOSL_ */
10944 +
10945 +#if defined(MACOSX) && defined(KERNEL)
10946 +#include <IOKit/IOTypes.h>
10947 +#endif
10948 +
10949 +
10950 +/* use the default typedefs in the next section of this file */
10951 +#define USE_TYPEDEF_DEFAULTS
10952 +
10953 +#endif /* SITE_TYPEDEFS */
10954 +
10955 +
10956 +/*******************************************************************************
10957 + * Default Typedefs
10958 + *******************************************************************************/
10959 +
10960 +#ifdef USE_TYPEDEF_DEFAULTS
10961 +#undef USE_TYPEDEF_DEFAULTS
10962 +
10963 +#ifndef TYPEDEF_BOOL
10964 +typedef /*@abstract@*/ unsigned char bool;
10965 +#endif
10966 +
10967 +/*----------------------- define uchar, ushort, uint, ulong ------------------*/
10968 +
10969 +#ifndef TYPEDEF_UCHAR
10970 +typedef unsigned char uchar;
10971 +#endif
10972 +
10973 +#ifndef TYPEDEF_USHORT
10974 +typedef unsigned short ushort;
10975 +#endif
10976 +
10977 +#ifndef TYPEDEF_UINT
10978 +typedef unsigned int uint;
10979 +#endif
10980 +
10981 +#ifndef TYPEDEF_ULONG
10982 +typedef unsigned long ulong;
10983 +#endif
10984 +
10985 +/*----------------------- define [u]int8/16/32/64, uintptr --------------------*/
10986 +
10987 +#ifndef TYPEDEF_UINT8
10988 +typedef unsigned char uint8;
10989 +#endif
10990 +
10991 +#ifndef TYPEDEF_UINT16
10992 +typedef unsigned short uint16;
10993 +#endif
10994 +
10995 +#ifndef TYPEDEF_UINT32
10996 +typedef unsigned int uint32;
10997 +#endif
10998 +
10999 +#ifndef TYPEDEF_UINT64
11000 +typedef unsigned long long uint64;
11001 +#endif
11002 +
11003 +#ifndef TYPEDEF_UINTPTR
11004 +typedef unsigned int uintptr;
11005 +#endif
11006 +
11007 +#ifndef TYPEDEF_INT8
11008 +typedef signed char int8;
11009 +#endif
11010 +
11011 +#ifndef TYPEDEF_INT16
11012 +typedef signed short int16;
11013 +#endif
11014 +
11015 +#ifndef TYPEDEF_INT32
11016 +typedef signed int int32;
11017 +#endif
11018 +
11019 +#ifndef TYPEDEF_INT64
11020 +typedef signed long long int64;
11021 +#endif
11022 +
11023 +/*----------------------- define float32/64, float_t -----------------------*/
11024 +
11025 +#ifndef TYPEDEF_FLOAT32
11026 +typedef float float32;
11027 +#endif
11028 +
11029 +#ifndef TYPEDEF_FLOAT64
11030 +typedef double float64;
11031 +#endif
11032 +
11033 +/*
11034 + * abstracted floating point type allows for compile time selection of
11035 + * single or double precision arithmetic. Compiling with -DFLOAT32
11036 + * selects single precision; the default is double precision.
11037 + */
11038 +
11039 +#ifndef TYPEDEF_FLOAT_T
11040 +
11041 +#if defined(FLOAT32)
11042 +typedef float32 float_t;
11043 +#else /* default to double precision floating point */
11044 +typedef float64 float_t;
11045 +#endif
11046 +
11047 +#endif /* TYPEDEF_FLOAT_T */
11048 +
11049 +/*----------------------- define macro values -----------------------------*/
11050 +
11051 +#ifndef FALSE
11052 +#define FALSE 0
11053 +#endif
11054 +
11055 +#ifndef TRUE
11056 +#define TRUE 1
11057 +#endif
11058 +
11059 +#ifndef NULL
11060 +#define NULL 0
11061 +#endif
11062 +
11063 +#ifndef OFF
11064 +#define OFF 0
11065 +#endif
11066 +
11067 +#ifndef ON
11068 +#define ON 1
11069 +#endif
11070 +
11071 +#define AUTO (-1)
11072 +
11073 +/* Reclaiming text and data :
11074 + The following macros specify special linker sections that can be reclaimed
11075 + after a system is considered 'up'.
11076 + */
11077 +#if defined(__GNUC__) && defined(BCMRECLAIM)
11078 +extern bool bcmreclaimed;
11079 +#define BCMINITDATA(_data) __attribute__ ((__section__ (".dataini." #_data))) _data##_ini
11080 +#define BCMINITFN(_fn) __attribute__ ((__section__ (".textini." #_fn))) _fn##_ini
11081 +#define BCMINIT(_id) _id##_ini
11082 +#else
11083 +#define BCMINITDATA(_data) _data
11084 +#define BCMINITFN(_fn) _fn
11085 +#define BCMINIT(_id) _id
11086 +#define bcmreclaimed 0
11087 +#endif
11088 +
11089 +/*----------------------- define PTRSZ, INLINE ----------------------------*/
11090 +
11091 +#ifndef PTRSZ
11092 +#define PTRSZ sizeof (char*)
11093 +#endif
11094 +
11095 +#ifndef INLINE
11096 +
11097 +#ifdef _MSC_VER
11098 +
11099 +#define INLINE __inline
11100 +
11101 +#elif __GNUC__
11102 +
11103 +#define INLINE __inline__
11104 +
11105 +#else
11106 +
11107 +#define INLINE
11108 +
11109 +#endif /* _MSC_VER */
11110 +
11111 +#endif /* INLINE */
11112 +
11113 +#undef TYPEDEF_BOOL
11114 +#undef TYPEDEF_UCHAR
11115 +#undef TYPEDEF_USHORT
11116 +#undef TYPEDEF_UINT
11117 +#undef TYPEDEF_ULONG
11118 +#undef TYPEDEF_UINT8
11119 +#undef TYPEDEF_UINT16
11120 +#undef TYPEDEF_UINT32
11121 +#undef TYPEDEF_UINT64
11122 +#undef TYPEDEF_UINTPTR
11123 +#undef TYPEDEF_INT8
11124 +#undef TYPEDEF_INT16
11125 +#undef TYPEDEF_INT32
11126 +#undef TYPEDEF_INT64
11127 +#undef TYPEDEF_FLOAT32
11128 +#undef TYPEDEF_FLOAT64
11129 +#undef TYPEDEF_FLOAT_T
11130 +
11131 +#endif /* USE_TYPEDEF_DEFAULTS */
11132 +
11133 +#endif /* _TYPEDEFS_H_ */
11134 diff -urN linux.old/arch/mips/bcm947xx/int-handler.S linux.dev/arch/mips/bcm947xx/int-handler.S
11135 --- linux.old/arch/mips/bcm947xx/int-handler.S 1970-01-01 01:00:00.000000000 +0100
11136 +++ linux.dev/arch/mips/bcm947xx/int-handler.S 2005-12-28 16:37:32.906263250 +0100
11137 @@ -0,0 +1,48 @@
11138 +/*
11139 + * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
11140 + *
11141 + * This program is free software; you can redistribute it and/or modify it
11142 + * under the terms of the GNU General Public License as published by the
11143 + * Free Software Foundation; either version 2 of the License, or (at your
11144 + * option) any later version.
11145 + *
11146 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11147 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
11148 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
11149 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
11150 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
11151 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
11152 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
11153 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
11154 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
11155 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
11156 + *
11157 + * You should have received a copy of the GNU General Public License along
11158 + * with this program; if not, write to the Free Software Foundation, Inc.,
11159 + * 675 Mass Ave, Cambridge, MA 02139, USA.
11160 + */
11161 +
11162 +#include <asm/asm.h>
11163 +#include <asm/mipsregs.h>
11164 +#include <asm/regdef.h>
11165 +#include <asm/stackframe.h>
11166 +
11167 + .text
11168 + .set noreorder
11169 + .set noat
11170 + .align 5
11171 +
11172 + NESTED(bcm47xx_irq_handler, PT_SIZE, sp)
11173 + SAVE_ALL
11174 + CLI
11175 +
11176 + .set at
11177 + .set noreorder
11178 +
11179 + jal bcm47xx_irq_dispatch
11180 + move a0, sp
11181 +
11182 + j ret_from_irq
11183 + nop
11184 +
11185 + END(bcm47xx_irq_handler)
11186 diff -urN linux.old/arch/mips/bcm947xx/irq.c linux.dev/arch/mips/bcm947xx/irq.c
11187 --- linux.old/arch/mips/bcm947xx/irq.c 1970-01-01 01:00:00.000000000 +0100
11188 +++ linux.dev/arch/mips/bcm947xx/irq.c 2005-12-28 16:37:32.906263250 +0100
11189 @@ -0,0 +1,67 @@
11190 +/*
11191 + * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
11192 + *
11193 + * This program is free software; you can redistribute it and/or modify it
11194 + * under the terms of the GNU General Public License as published by the
11195 + * Free Software Foundation; either version 2 of the License, or (at your
11196 + * option) any later version.
11197 + *
11198 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11199 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
11200 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
11201 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
11202 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
11203 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
11204 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
11205 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
11206 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
11207 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
11208 + *
11209 + * You should have received a copy of the GNU General Public License along
11210 + * with this program; if not, write to the Free Software Foundation, Inc.,
11211 + * 675 Mass Ave, Cambridge, MA 02139, USA.
11212 + */
11213 +
11214 +#include <linux/config.h>
11215 +#include <linux/errno.h>
11216 +#include <linux/init.h>
11217 +#include <linux/interrupt.h>
11218 +#include <linux/irq.h>
11219 +#include <linux/module.h>
11220 +#include <linux/smp.h>
11221 +#include <linux/types.h>
11222 +
11223 +#include <asm/cpu.h>
11224 +#include <asm/io.h>
11225 +#include <asm/irq.h>
11226 +#include <asm/irq_cpu.h>
11227 +
11228 +extern asmlinkage void bcm47xx_irq_handler(void);
11229 +
11230 +void bcm47xx_irq_dispatch(struct pt_regs *regs)
11231 +{
11232 + u32 cause;
11233 +
11234 + cause = read_c0_cause() & read_c0_status() & CAUSEF_IP;
11235 +
11236 + clear_c0_status(cause);
11237 +
11238 + if (cause & CAUSEF_IP7)
11239 + do_IRQ(7, regs);
11240 + if (cause & CAUSEF_IP2)
11241 + do_IRQ(2, regs);
11242 + if (cause & CAUSEF_IP3)
11243 + do_IRQ(3, regs);
11244 + if (cause & CAUSEF_IP4)
11245 + do_IRQ(4, regs);
11246 + if (cause & CAUSEF_IP5)
11247 + do_IRQ(5, regs);
11248 + if (cause & CAUSEF_IP6)
11249 + do_IRQ(6, regs);
11250 +}
11251 +
11252 +void __init arch_init_irq(void)
11253 +{
11254 + set_except_vector(0, bcm47xx_irq_handler);
11255 + mips_cpu_irq_init(0);
11256 +}
11257 diff -urN linux.old/arch/mips/bcm947xx/pci.c linux.dev/arch/mips/bcm947xx/pci.c
11258 --- linux.old/arch/mips/bcm947xx/pci.c 1970-01-01 01:00:00.000000000 +0100
11259 +++ linux.dev/arch/mips/bcm947xx/pci.c 2005-12-28 16:37:32.906263250 +0100
11260 @@ -0,0 +1,215 @@
11261 +#include <linux/kernel.h>
11262 +#include <linux/init.h>
11263 +#include <linux/pci.h>
11264 +#include <linux/types.h>
11265 +
11266 +#include <asm/cpu.h>
11267 +#include <asm/io.h>
11268 +
11269 +#include <typedefs.h>
11270 +#include <osl.h>
11271 +#include <sbutils.h>
11272 +#include <sbmips.h>
11273 +#include <sbconfig.h>
11274 +#include <sbpci.h>
11275 +#include <bcmdevs.h>
11276 +#include <pcicfg.h>
11277 +
11278 +extern sb_t *sbh;
11279 +extern spinlock_t sbh_lock;
11280 +
11281 +
11282 +static int
11283 +sb_pci_read_config(struct pci_bus *bus, unsigned int devfn,
11284 + int reg, int size, u32 *val)
11285 +{
11286 + int ret;
11287 + unsigned long flags;
11288 +
11289 + spin_lock_irqsave(&sbh_lock, flags);
11290 + ret = sbpci_read_config(sbh, bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), reg, val, size);
11291 + spin_unlock_irqrestore(&sbh_lock, flags);
11292 +
11293 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
11294 +}
11295 +
11296 +static int
11297 +sb_pci_write_config(struct pci_bus *bus, unsigned int devfn,
11298 + int reg, int size, u32 val)
11299 +{
11300 + int ret;
11301 + unsigned long flags;
11302 +
11303 + spin_lock_irqsave(&sbh_lock, flags);
11304 + ret = sbpci_write_config(sbh, bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), reg, &val, size);
11305 + spin_unlock_irqrestore(&sbh_lock, flags);
11306 +
11307 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
11308 +}
11309 +
11310 +
11311 +static struct pci_ops sb_pci_ops = {
11312 + .read = sb_pci_read_config,
11313 + .write = sb_pci_write_config,
11314 +};
11315 +
11316 +static struct resource sb_pci_mem_resource = {
11317 + .name = "SB PCI Memory resources",
11318 + .start = SB_ENUM_BASE,
11319 + .end = SB_ENUM_LIM - 1,
11320 + .flags = IORESOURCE_MEM,
11321 +};
11322 +
11323 +static struct resource sb_pci_io_resource = {
11324 + .name = "SB PCI I/O resources",
11325 + .start = 0x000,
11326 + .end = 0x0FF,
11327 + .flags = IORESOURCE_IO,
11328 +};
11329 +
11330 +static struct pci_controller bcm47xx_sb_pci_controller = {
11331 + .pci_ops = &sb_pci_ops,
11332 + .mem_resource = &sb_pci_mem_resource,
11333 + .io_resource = &sb_pci_io_resource,
11334 +};
11335 +
11336 +static struct resource ext_pci_mem_resource = {
11337 + .name = "Ext PCI Memory resources",
11338 + .start = 0x40000000,
11339 + .end = 0x7fffffff,
11340 + .flags = IORESOURCE_MEM,
11341 +};
11342 +
11343 +static struct resource ext_pci_io_resource = {
11344 + .name = "Ext PCI I/O resources",
11345 + .start = 0x100,
11346 + .end = 0x1FF,
11347 + .flags = IORESOURCE_IO,
11348 +};
11349 +
11350 +static struct pci_controller bcm47xx_ext_pci_controller = {
11351 + .pci_ops = &sb_pci_ops,
11352 + .io_resource = &ext_pci_io_resource,
11353 + .mem_resource = &ext_pci_mem_resource,
11354 + .mem_offset = 0x24000000,
11355 +};
11356 +
11357 +void bcm47xx_pci_init(void)
11358 +{
11359 + unsigned long flags;
11360 +
11361 + spin_lock_irqsave(&sbh_lock, flags);
11362 + sbpci_init(sbh);
11363 + spin_unlock_irqrestore(&sbh_lock, flags);
11364 +
11365 + set_io_port_base((unsigned long) ioremap_nocache(SB_PCI_MEM, 0x04000000));
11366 +
11367 + register_pci_controller(&bcm47xx_sb_pci_controller);
11368 + register_pci_controller(&bcm47xx_ext_pci_controller);
11369 +}
11370 +
11371 +int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
11372 +{
11373 + u8 irq;
11374 +
11375 + if (dev->bus->number == 1)
11376 + return 2;
11377 +
11378 + pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
11379 + return irq + 2;
11380 +}
11381 +
11382 +u32 pci_iobase = 0x100;
11383 +u32 pci_membase = SB_PCI_DMA;
11384 +
11385 +static void bcm47xx_fixup_device(struct pci_dev *d)
11386 +{
11387 + struct resource *res;
11388 + int pos, size;
11389 + u32 *base;
11390 +
11391 + if (d->bus->number == 0)
11392 + return;
11393 +
11394 + printk("PCI: Fixing up device %s\n", pci_name(d));
11395 +
11396 + /* Fix up resource bases */
11397 + for (pos = 0; pos < 6; pos++) {
11398 + res = &d->resource[pos];
11399 + base = ((res->flags & IORESOURCE_IO) ? &pci_iobase : &pci_membase);
11400 + if (res->end) {
11401 + size = res->end - res->start + 1;
11402 + if (*base & (size - 1))
11403 + *base = (*base + size) & ~(size - 1);
11404 + res->start = *base;
11405 + res->end = res->start + size - 1;
11406 + *base += size;
11407 + pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
11408 + }
11409 + /* Fix up PCI bridge BAR0 only */
11410 + if (d->bus->number == 1 && PCI_SLOT(d->devfn) == 0)
11411 + break;
11412 + }
11413 + /* Fix up interrupt lines */
11414 + if (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))
11415 + d->irq = (pci_find_device(VENDOR_BROADCOM, SB_PCI, NULL))->irq;
11416 + pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
11417 +}
11418 +
11419 +
11420 +static void bcm47xx_fixup_bridge(struct pci_dev *dev)
11421 +{
11422 + if (dev->bus->number != 1 || PCI_SLOT(dev->devfn) != 0)
11423 + return;
11424 +
11425 + printk("PCI: fixing up bridge\n");
11426 +
11427 + /* Enable PCI bridge bus mastering and memory space */
11428 + pci_set_master(dev);
11429 + pcibios_enable_device(dev, ~0);
11430 +
11431 + /* Enable PCI bridge BAR1 prefetch and burst */
11432 + pci_write_config_dword(dev, PCI_BAR1_CONTROL, 3);
11433 +}
11434 +
11435 +/* Do platform specific device initialization at pci_enable_device() time */
11436 +int pcibios_plat_dev_init(struct pci_dev *dev)
11437 +{
11438 + uint coreidx;
11439 + unsigned long flags;
11440 +
11441 + bcm47xx_fixup_device(dev);
11442 +
11443 + /* These cores come out of reset enabled */
11444 + if ((dev->bus->number != 0) ||
11445 + (dev->device == SB_MIPS) ||
11446 + (dev->device == SB_MIPS33) ||
11447 + (dev->device == SB_EXTIF) ||
11448 + (dev->device == SB_CC))
11449 + return 0;
11450 +
11451 + /* Do a core reset */
11452 + spin_lock_irqsave(&sbh_lock, flags);
11453 + coreidx = sb_coreidx(sbh);
11454 + if (sb_setcoreidx(sbh, PCI_SLOT(dev->devfn)) && (sb_coreid(sbh) == SB_USB)) {
11455 + /*
11456 + * The USB core requires a special bit to be set during core
11457 + * reset to enable host (OHCI) mode. Resetting the SB core in
11458 + * pcibios_enable_device() is a hack for compatibility with
11459 + * vanilla usb-ohci so that it does not have to know about
11460 + * SB. A driver that wants to use the USB core in device mode
11461 + * should know about SB and should reset the bit back to 0
11462 + * after calling pcibios_enable_device().
11463 + */
11464 + sb_core_disable(sbh, sb_coreflags(sbh, 0, 0));
11465 + sb_core_reset(sbh, 1 << 29);
11466 + } else {
11467 + sb_core_reset(sbh, 0);
11468 + }
11469 + sb_setcoreidx(sbh, coreidx);
11470 + spin_unlock_irqrestore(&sbh_lock, flags);
11471 +
11472 + return 0;
11473 +}
11474 +
11475 +DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, bcm47xx_fixup_bridge);
11476 diff -urN linux.old/arch/mips/bcm947xx/prom.c linux.dev/arch/mips/bcm947xx/prom.c
11477 --- linux.old/arch/mips/bcm947xx/prom.c 1970-01-01 01:00:00.000000000 +0100
11478 +++ linux.dev/arch/mips/bcm947xx/prom.c 2005-12-28 16:37:32.906263250 +0100
11479 @@ -0,0 +1,59 @@
11480 +/*
11481 + * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
11482 + *
11483 + * This program is free software; you can redistribute it and/or modify it
11484 + * under the terms of the GNU General Public License as published by the
11485 + * Free Software Foundation; either version 2 of the License, or (at your
11486 + * option) any later version.
11487 + *
11488 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11489 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
11490 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
11491 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
11492 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
11493 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
11494 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
11495 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
11496 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
11497 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
11498 + *
11499 + * You should have received a copy of the GNU General Public License along
11500 + * with this program; if not, write to the Free Software Foundation, Inc.,
11501 + * 675 Mass Ave, Cambridge, MA 02139, USA.
11502 + */
11503 +
11504 +#include <linux/init.h>
11505 +#include <linux/mm.h>
11506 +#include <linux/sched.h>
11507 +#include <linux/bootmem.h>
11508 +
11509 +#include <asm/addrspace.h>
11510 +#include <asm/bootinfo.h>
11511 +#include <asm/pmon.h>
11512 +
11513 +const char *get_system_type(void)
11514 +{
11515 + return "Broadcom BCM47xx";
11516 +}
11517 +
11518 +void __init prom_init(void)
11519 +{
11520 + unsigned long mem;
11521 +
11522 + mips_machgroup = MACH_GROUP_BRCM;
11523 + mips_machtype = MACH_BCM47XX;
11524 +
11525 + /* Figure out memory size by finding aliases */
11526 + for (mem = (1 << 20); mem < (128 << 20); mem += (1 << 20)) {
11527 + if (*(unsigned long *)((unsigned long)(prom_init) + mem) ==
11528 + *(unsigned long *)(prom_init))
11529 + break;
11530 + }
11531 +
11532 + add_memory_region(0, mem, BOOT_MEM_RAM);
11533 +}
11534 +
11535 +unsigned long __init prom_free_prom_memory(void)
11536 +{
11537 + return 0;
11538 +}
11539 diff -urN linux.old/arch/mips/bcm947xx/setup.c linux.dev/arch/mips/bcm947xx/setup.c
11540 --- linux.old/arch/mips/bcm947xx/setup.c 1970-01-01 01:00:00.000000000 +0100
11541 +++ linux.dev/arch/mips/bcm947xx/setup.c 2005-12-28 19:29:25.870911750 +0100
11542 @@ -0,0 +1,157 @@
11543 +/*
11544 + * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
11545 + * Copyright (C) 2005 Waldemar Brodkorb <wbx@openwrt.org>
11546 + * Copyright (C) 2005 Felix Fietkau <nbd@openwrt.org>
11547 + *
11548 + * This program is free software; you can redistribute it and/or modify it
11549 + * under the terms of the GNU General Public License as published by the
11550 + * Free Software Foundation; either version 2 of the License, or (at your
11551 + * option) any later version.
11552 + *
11553 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11554 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
11555 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
11556 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
11557 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
11558 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
11559 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
11560 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
11561 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
11562 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
11563 + *
11564 + * You should have received a copy of the GNU General Public License along
11565 + * with this program; if not, write to the Free Software Foundation, Inc.,
11566 + * 675 Mass Ave, Cambridge, MA 02139, USA.
11567 + */
11568 +
11569 +#include <linux/init.h>
11570 +#include <linux/types.h>
11571 +#include <linux/tty.h>
11572 +#include <linux/serial.h>
11573 +#include <linux/serial_core.h>
11574 +#include <linux/serial_reg.h>
11575 +#include <asm/bootinfo.h>
11576 +#include <asm/time.h>
11577 +#include <asm/reboot.h>
11578 +
11579 +#include <typedefs.h>
11580 +#include <osl.h>
11581 +#include <sbutils.h>
11582 +#include <sbmips.h>
11583 +#include <sbpci.h>
11584 +#include <sbconfig.h>
11585 +#include <bcmdevs.h>
11586 +#include <bcmutils.h>
11587 +#include <bcmnvram.h>
11588 +
11589 +extern void bcm47xx_pci_init(void);
11590 +extern void bcm47xx_time_init(void);
11591 +extern void bcm47xx_timer_setup(struct irqaction *irq);
11592 +void *sbh;
11593 +spinlock_t sbh_lock = SPIN_LOCK_UNLOCKED;
11594 +int boardflags;
11595 +
11596 +static int ser_line = 0;
11597 +
11598 +typedef struct {
11599 + void *regs;
11600 + uint irq;
11601 + uint baud_base;
11602 + uint reg_shift;
11603 +} serial_port;
11604 +
11605 +static serial_port ports[4];
11606 +static int num_ports = 0;
11607 +
11608 +static void
11609 +serial_add(void *regs, uint irq, uint baud_base, uint reg_shift)
11610 +{
11611 + ports[num_ports].regs = regs;
11612 + ports[num_ports].irq = irq;
11613 + ports[num_ports].baud_base = baud_base;
11614 + ports[num_ports].reg_shift = reg_shift;
11615 + num_ports++;
11616 +}
11617 +
11618 +static void
11619 +do_serial_add(serial_port *port)
11620 +{
11621 + void *regs;
11622 + uint irq;
11623 + uint baud_base;
11624 + uint reg_shift;
11625 + struct uart_port s;
11626 +
11627 + regs = port->regs;
11628 + irq = port->irq;
11629 + baud_base = port->baud_base;
11630 + reg_shift = port->reg_shift;
11631 +
11632 + memset(&s, 0, sizeof(s));
11633 +
11634 + s.line = ser_line++;
11635 + s.membase = regs;
11636 + s.irq = irq + 2;
11637 + s.uartclk = baud_base;
11638 + s.flags = ASYNC_BOOT_AUTOCONF;
11639 + s.iotype = SERIAL_IO_MEM;
11640 + s.regshift = reg_shift;
11641 +
11642 + if (early_serial_setup(&s) != 0) {
11643 + printk(KERN_ERR "Serial setup failed!\n");
11644 + }
11645 +}
11646 +
11647 +static void bcm47xx_machine_restart(char *command)
11648 +{
11649 + printk("Please stand by while rebooting the system...\n");
11650 +
11651 + /* Set the watchdog timer to reset immediately */
11652 + local_irq_disable();
11653 + sb_watchdog(sbh, 1);
11654 + while (1);
11655 +}
11656 +
11657 +static void bcm47xx_machine_halt(void)
11658 +{
11659 + /* Disable interrupts and watchdog and spin forever */
11660 + local_irq_disable();
11661 + sb_watchdog(sbh, 0);
11662 + while (1);
11663 +}
11664 +
11665 +void __init plat_setup(void)
11666 +{
11667 + char *s;
11668 + int i;
11669 +
11670 + sbh = (void *) sb_kattach();
11671 + sb_mips_init(sbh);
11672 +
11673 + bcm47xx_pci_init();
11674 +
11675 + sb_serial_init(sbh, serial_add);
11676 + boardflags = getintvar(NULL, "boardflags");
11677 +
11678 + /* reverse serial ports if the nvram variable kernel_args starts with console=ttyS1 */
11679 + s = early_nvram_get("kernel_args");
11680 + if (!s) s = "";
11681 + if (!strncmp(s, "console=ttyS1", 13)) {
11682 + for (i = num_ports; i; i--)
11683 + do_serial_add(&ports[i - 1]);
11684 + } else {
11685 + for (i = 0; i < num_ports; i++)
11686 + do_serial_add(&ports[i]);
11687 + }
11688 +
11689 + _machine_restart = bcm47xx_machine_restart;
11690 + _machine_halt = bcm47xx_machine_halt;
11691 + _machine_power_off = bcm47xx_machine_halt;
11692 +
11693 + board_time_init = bcm47xx_time_init;
11694 + board_timer_setup = bcm47xx_timer_setup;
11695 +}
11696 +
11697 +EXPORT_SYMBOL(sbh);
11698 +EXPORT_SYMBOL(sbh_lock);
11699 +EXPORT_SYMBOL(boardflags);
11700 diff -urN linux.old/arch/mips/bcm947xx/time.c linux.dev/arch/mips/bcm947xx/time.c
11701 --- linux.old/arch/mips/bcm947xx/time.c 1970-01-01 01:00:00.000000000 +0100
11702 +++ linux.dev/arch/mips/bcm947xx/time.c 2005-12-28 16:37:32.906263250 +0100
11703 @@ -0,0 +1,59 @@
11704 +/*
11705 + * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
11706 + *
11707 + * This program is free software; you can redistribute it and/or modify it
11708 + * under the terms of the GNU General Public License as published by the
11709 + * Free Software Foundation; either version 2 of the License, or (at your
11710 + * option) any later version.
11711 + *
11712 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11713 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
11714 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
11715 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
11716 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
11717 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
11718 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
11719 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
11720 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
11721 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
11722 + *
11723 + * You should have received a copy of the GNU General Public License along
11724 + * with this program; if not, write to the Free Software Foundation, Inc.,
11725 + * 675 Mass Ave, Cambridge, MA 02139, USA.
11726 + */
11727 +
11728 +#include <linux/config.h>
11729 +#include <linux/init.h>
11730 +#include <linux/kernel.h>
11731 +#include <linux/sched.h>
11732 +#include <linux/serial_reg.h>
11733 +#include <linux/interrupt.h>
11734 +#include <asm/addrspace.h>
11735 +#include <asm/io.h>
11736 +#include <asm/time.h>
11737 +
11738 +void __init
11739 +bcm47xx_time_init(void)
11740 +{
11741 + unsigned int hz;
11742 +
11743 + /*
11744 + * Use deterministic values for initial counter interrupt
11745 + * so that calibrate delay avoids encountering a counter wrap.
11746 + */
11747 + write_c0_count(0);
11748 + write_c0_compare(0xffff);
11749 +
11750 + hz = 200 * 1000 * 1000;
11751 +
11752 + /* Set MIPS counter frequency for fixed_rate_gettimeoffset() */
11753 + mips_hpt_frequency = hz / 2;
11754 +
11755 +}
11756 +
11757 +void __init
11758 +bcm47xx_timer_setup(struct irqaction *irq)
11759 +{
11760 + /* Enable the timer interrupt */
11761 + setup_irq(7, irq);
11762 +}
11763 diff -urN linux.old/arch/mips/kernel/cpu-probe.c linux.dev/arch/mips/kernel/cpu-probe.c
11764 --- linux.old/arch/mips/kernel/cpu-probe.c 2005-12-19 01:36:54.000000000 +0100
11765 +++ linux.dev/arch/mips/kernel/cpu-probe.c 2005-12-28 16:37:32.934265000 +0100
11766 @@ -656,6 +656,28 @@
11767 }
11768
11769
11770 +static inline void cpu_probe_broadcom(struct cpuinfo_mips *c)
11771 +{
11772 + decode_config1(c);
11773 + switch (c->processor_id & 0xff00) {
11774 + case PRID_IMP_BCM3302:
11775 + c->cputype = CPU_BCM3302;
11776 + c->isa_level = MIPS_CPU_ISA_M32;
11777 + c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
11778 + MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER;
11779 + break;
11780 + case PRID_IMP_BCM4710:
11781 + c->cputype = CPU_BCM4710;
11782 + c->isa_level = MIPS_CPU_ISA_M32;
11783 + c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
11784 + MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER;
11785 + break;
11786 + default:
11787 + c->cputype = CPU_UNKNOWN;
11788 + break;
11789 + }
11790 +}
11791 +
11792 __init void cpu_probe(void)
11793 {
11794 struct cpuinfo_mips *c = &current_cpu_data;
11795 @@ -678,6 +700,9 @@
11796 case PRID_COMP_SIBYTE:
11797 cpu_probe_sibyte(c);
11798 break;
11799 + case PRID_COMP_BROADCOM:
11800 + cpu_probe_broadcom(c);
11801 + break;
11802 case PRID_COMP_SANDCRAFT:
11803 cpu_probe_sandcraft(c);
11804 break;
11805 diff -urN linux.old/arch/mips/kernel/head.S linux.dev/arch/mips/kernel/head.S
11806 --- linux.old/arch/mips/kernel/head.S 2005-12-19 01:36:54.000000000 +0100
11807 +++ linux.dev/arch/mips/kernel/head.S 2005-12-28 16:37:32.934265000 +0100
11808 @@ -107,6 +107,14 @@
11809 #endif
11810 .endm
11811
11812 +#ifdef CONFIG_BCM4710
11813 +#undef eret
11814 +#define eret nop; nop; eret
11815 +#endif
11816 +
11817 + j kernel_entry
11818 + nop
11819 +
11820 /*
11821 * Reserved space for exception handlers.
11822 * Necessary for machines which link their kernels at KSEG0.
11823 diff -urN linux.old/arch/mips/kernel/proc.c linux.dev/arch/mips/kernel/proc.c
11824 --- linux.old/arch/mips/kernel/proc.c 2005-12-19 01:36:54.000000000 +0100
11825 +++ linux.dev/arch/mips/kernel/proc.c 2005-12-28 16:37:32.946265750 +0100
11826 @@ -82,6 +82,8 @@
11827 [CPU_VR4181] = "NEC VR4181",
11828 [CPU_VR4181A] = "NEC VR4181A",
11829 [CPU_SR71000] = "Sandcraft SR71000",
11830 + [CPU_BCM3302] = "Broadcom BCM3302",
11831 + [CPU_BCM4710] = "Broadcom BCM4710",
11832 [CPU_PR4450] = "Philips PR4450",
11833 };
11834
11835 diff -urN linux.old/arch/mips/mm/tlbex.c linux.dev/arch/mips/mm/tlbex.c
11836 --- linux.old/arch/mips/mm/tlbex.c 2005-12-19 01:36:54.000000000 +0100
11837 +++ linux.dev/arch/mips/mm/tlbex.c 2005-12-28 16:37:32.970267250 +0100
11838 @@ -858,6 +858,8 @@
11839 case CPU_4KSC:
11840 case CPU_20KC:
11841 case CPU_25KF:
11842 + case CPU_BCM3302:
11843 + case CPU_BCM4710:
11844 tlbw(p);
11845 break;
11846
11847 diff -urN linux.old/include/asm-mips/bootinfo.h linux.dev/include/asm-mips/bootinfo.h
11848 --- linux.old/include/asm-mips/bootinfo.h 2005-12-19 01:36:54.000000000 +0100
11849 +++ linux.dev/include/asm-mips/bootinfo.h 2005-12-28 16:37:32.970267250 +0100
11850 @@ -218,6 +218,12 @@
11851 #define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */
11852 #define MACH_TITAN_YOSEMITE 1 /* PMC-Sierra Yosemite */
11853
11854 +/*
11855 + * Valid machtype for group Broadcom
11856 + */
11857 +#define MACH_GROUP_BRCM 23 /* Broadcom */
11858 +#define MACH_BCM47XX 1 /* Broadcom BCM47xx */
11859 +
11860 #define CL_SIZE COMMAND_LINE_SIZE
11861
11862 const char *get_system_type(void);
11863 diff -urN linux.old/include/asm-mips/cpu.h linux.dev/include/asm-mips/cpu.h
11864 --- linux.old/include/asm-mips/cpu.h 2005-12-19 01:36:54.000000000 +0100
11865 +++ linux.dev/include/asm-mips/cpu.h 2005-12-28 16:37:32.974267500 +0100
11866 @@ -102,6 +102,13 @@
11867 #define PRID_IMP_SR71000 0x0400
11868
11869 /*
11870 + * These are the PRID's for when 23:16 == PRID_COMP_BROADCOM
11871 + */
11872 +
11873 +#define PRID_IMP_BCM4710 0x4000
11874 +#define PRID_IMP_BCM3302 0x9000
11875 +
11876 +/*
11877 * Definitions for 7:0 on legacy processors
11878 */
11879
11880 @@ -196,7 +203,9 @@
11881 #define CPU_34K 60
11882 #define CPU_PR4450 61
11883 #define CPU_SB1A 62
11884 -#define CPU_LAST 62
11885 +#define CPU_BCM3302 63
11886 +#define CPU_BCM4710 64
11887 +#define CPU_LAST 64
11888
11889 /*
11890 * ISA Level encodings
11891 diff -urN linux.old/include/linux/init.h linux.dev/include/linux/init.h
11892 --- linux.old/include/linux/init.h 2005-12-19 01:36:54.000000000 +0100
11893 +++ linux.dev/include/linux/init.h 2005-12-28 16:37:32.982268000 +0100
11894 @@ -86,6 +86,8 @@
11895 static initcall_t __initcall_##fn __attribute_used__ \
11896 __attribute__((__section__(".initcall" level ".init"))) = fn
11897
11898 +#define early_initcall(fn) __define_initcall(".early1",fn)
11899 +
11900 #define core_initcall(fn) __define_initcall("1",fn)
11901 #define postcore_initcall(fn) __define_initcall("2",fn)
11902 #define arch_initcall(fn) __define_initcall("3",fn)
11903 diff -urN linux.old/include/linux/pci_ids.h linux.dev/include/linux/pci_ids.h
11904 --- linux.old/include/linux/pci_ids.h 2005-12-19 01:36:54.000000000 +0100
11905 +++ linux.dev/include/linux/pci_ids.h 2005-12-28 16:37:32.994268750 +0100
11906 @@ -1836,6 +1836,7 @@
11907 #define PCI_DEVICE_ID_TIGON3_5901_2 0x170e
11908 #define PCI_DEVICE_ID_BCM4401 0x4401
11909 #define PCI_DEVICE_ID_BCM4401B0 0x4402
11910 +#define PCI_DEVICE_ID_BCM4713 0x4713
11911
11912 #define PCI_VENDOR_ID_TOPIC 0x151f
11913 #define PCI_DEVICE_ID_TOPIC_TP560 0x0000
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