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add cleanup and system code upgrade for brcm-2.6. pci seems to work, but spits out...
[openwrt/staging/dedeckeh.git] / openwrt / target / linux / linux-2.6 / patches / brcm / 001-bcm947xx.patch
1 diff -urN linux.old/arch/mips/Kconfig linux.dev/arch/mips/Kconfig
2 --- linux.old/arch/mips/Kconfig 2005-12-15 13:26:49.758027500 +0100
3 +++ linux.dev/arch/mips/Kconfig 2005-12-15 12:57:27.889182500 +0100
4 @@ -244,6 +244,17 @@
5 Members include the Acer PICA, MIPS Magnum 4000, MIPS Millenium and
6 Olivetti M700-10 workstations.
7
8 +config BCM947XX
9 + bool "Support for BCM947xx based boards"
10 + select DMA_NONCOHERENT
11 + select HW_HAS_PCI
12 + select IRQ_CPU
13 + select SYS_HAS_CPU_MIPS32_R1
14 + select SYS_SUPPORTS_32BIT_KERNEL
15 + select SYS_SUPPORTS_LITTLE_ENDIAN
16 + help
17 + Support for BCM947xx based boards
18 +
19 config LASAT
20 bool "Support for LASAT Networks platforms"
21 select DMA_NONCOHERENT
22 diff -urN linux.old/arch/mips/Makefile linux.dev/arch/mips/Makefile
23 --- linux.old/arch/mips/Makefile 2005-12-15 13:26:49.766024000 +0100
24 +++ linux.dev/arch/mips/Makefile 2005-12-15 12:57:27.921168500 +0100
25 @@ -689,6 +689,13 @@
26 load-$(CONFIG_SIBYTE_BIGSUR) := 0xffffffff80100000
27
28 #
29 +# Broadcom BCM47XX boards
30 +#
31 +core-$(CONFIG_BCM947XX) += arch/mips/bcm947xx/ arch/mips/bcm947xx/broadcom/
32 +cflags-$(CONFIG_BCM947XX) += -Iarch/mips/bcm947xx/include
33 +load-$(CONFIG_BCM947XX) := 0xffffffff80001000
34 +
35 +#
36 # SNI RM200 PCI
37 #
38 core-$(CONFIG_SNI_RM200_PCI) += arch/mips/sni/
39 diff -urN linux.old/arch/mips/bcm947xx/Makefile linux.dev/arch/mips/bcm947xx/Makefile
40 --- linux.old/arch/mips/bcm947xx/Makefile 1970-01-01 01:00:00.000000000 +0100
41 +++ linux.dev/arch/mips/bcm947xx/Makefile 2005-12-15 14:32:03.580639500 +0100
42 @@ -0,0 +1,6 @@
43 +#
44 +# Makefile for the BCM47xx specific kernel interface routines
45 +# under Linux.
46 +#
47 +
48 +obj-y := irq.o int-handler.o prom.o setup.o time.o pci.o
49 diff -urN linux.old/arch/mips/bcm947xx/broadcom/Makefile linux.dev/arch/mips/bcm947xx/broadcom/Makefile
50 --- linux.old/arch/mips/bcm947xx/broadcom/Makefile 1970-01-01 01:00:00.000000000 +0100
51 +++ linux.dev/arch/mips/bcm947xx/broadcom/Makefile 2005-12-15 16:59:40.571216500 +0100
52 @@ -0,0 +1,6 @@
53 +#
54 +# Makefile for the BCM47xx specific kernel interface routines
55 +# under Linux.
56 +#
57 +
58 +obj-y := sbutils.o linux_osl.o bcmsrom.o bcmutils.o sbmips.o sbpci.o sflash.o nvram.o
59 diff -urN linux.old/arch/mips/bcm947xx/broadcom/bcmsrom.c linux.dev/arch/mips/bcm947xx/broadcom/bcmsrom.c
60 --- linux.old/arch/mips/bcm947xx/broadcom/bcmsrom.c 1970-01-01 01:00:00.000000000 +0100
61 +++ linux.dev/arch/mips/bcm947xx/broadcom/bcmsrom.c 2005-12-15 17:35:21.719238750 +0100
62 @@ -0,0 +1,483 @@
63 +/*
64 + * Misc useful routines to access NIC SROM/OTP .
65 + *
66 + * Copyright 2005, Broadcom Corporation
67 + * All Rights Reserved.
68 + *
69 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
70 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
71 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
72 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
73 + * $Id$
74 + */
75 +
76 +#include <typedefs.h>
77 +#include <osl.h>
78 +#include <bcmutils.h>
79 +#include <bcmsrom.h>
80 +#include <bcmdevs.h>
81 +#include <bcmendian.h>
82 +#include <pcicfg.h>
83 +#include <sbutils.h>
84 +
85 +#include <proto/ethernet.h> /* for sprom content groking */
86 +
87 +#define VARS_MAX 4096 /* should be reduced */
88 +
89 +#define WRITE_ENABLE_DELAY 500 /* 500 ms after write enable/disable toggle */
90 +#define WRITE_WORD_DELAY 20 /* 20 ms between each word write */
91 +
92 +static int initvars_srom_pci(void *sbh, void *curmap, char **vars, int *count);
93 +static int sprom_read_pci(uint16 *sprom, uint wordoff, uint16 *buf, uint nwords, bool check_crc);
94 +
95 +static int initvars_table(osl_t *osh, char *start, char *end, char **vars, uint *count);
96 +
97 +/*
98 + * Initialize local vars from the right source for this platform.
99 + * Return 0 on success, nonzero on error.
100 + */
101 +int
102 +srom_var_init(void *sbh, uint bustype, void *curmap, osl_t *osh, char **vars, int *count)
103 +{
104 + ASSERT(bustype == BUSTYPE(bustype));
105 + if (vars == NULL || count == NULL)
106 + return (0);
107 +
108 + switch (BUSTYPE(bustype)) {
109 +
110 + case PCI_BUS:
111 + ASSERT(curmap); /* can not be NULL */
112 + return initvars_srom_pci(sbh, curmap, vars, count);
113 +
114 + default:
115 + return 0;
116 + }
117 + return (-1);
118 +}
119 +
120 +/* support only 16-bit word read from srom */
121 +int
122 +srom_read(uint bustype, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf)
123 +{
124 + void *srom;
125 + uint off, nw;
126 +
127 + ASSERT(bustype == BUSTYPE(bustype));
128 +
129 + /* check input - 16-bit access only */
130 + if (byteoff & 1 || nbytes & 1 || (byteoff + nbytes) > (SPROM_SIZE * 2))
131 + return 1;
132 +
133 + off = byteoff / 2;
134 + nw = nbytes / 2;
135 +
136 + if (BUSTYPE(bustype) == PCI_BUS) {
137 + if (!curmap)
138 + return 1;
139 + srom = (uchar*)curmap + PCI_BAR0_SPROM_OFFSET;
140 + if (sprom_read_pci(srom, off, buf, nw, FALSE))
141 + return 1;
142 + } else {
143 + return 1;
144 + }
145 +
146 + return 0;
147 +}
148 +
149 +/* support only 16-bit word write into srom */
150 +int
151 +srom_write(uint bustype, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf)
152 +{
153 + uint16 *srom;
154 + uint i, off, nw, crc_range;
155 + uint16 image[SPROM_SIZE], *p;
156 + uint8 crc;
157 + volatile uint32 val32;
158 +
159 + ASSERT(bustype == BUSTYPE(bustype));
160 +
161 + /* check input - 16-bit access only */
162 + if (byteoff & 1 || nbytes & 1 || (byteoff + nbytes) > (SPROM_SIZE * 2))
163 + return 1;
164 +
165 + crc_range = (((BUSTYPE(bustype) == SDIO_BUS)) ? SPROM_SIZE : SPROM_CRC_RANGE) * 2;
166 +
167 + /* if changes made inside crc cover range */
168 + if (byteoff < crc_range) {
169 + nw = (((byteoff + nbytes) > crc_range) ? byteoff + nbytes : crc_range) / 2;
170 + /* read data including entire first 64 words from srom */
171 + if (srom_read(bustype, curmap, osh, 0, nw * 2, image))
172 + return 1;
173 + /* make changes */
174 + bcopy((void*)buf, (void*)&image[byteoff / 2], nbytes);
175 + /* calculate crc */
176 + htol16_buf(image, crc_range);
177 + crc = ~hndcrc8((uint8 *)image, crc_range - 1, CRC8_INIT_VALUE);
178 + ltoh16_buf(image, crc_range);
179 + image[(crc_range / 2) - 1] = (crc << 8) | (image[(crc_range / 2) - 1] & 0xff);
180 + p = image;
181 + off = 0;
182 + } else {
183 + p = buf;
184 + off = byteoff / 2;
185 + nw = nbytes / 2;
186 + }
187 +
188 + if (BUSTYPE(bustype) == PCI_BUS) {
189 + srom = (uint16*)((uchar*)curmap + PCI_BAR0_SPROM_OFFSET);
190 + /* enable writes to the SPROM */
191 + val32 = OSL_PCI_READ_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32));
192 + val32 |= SPROM_WRITEEN;
193 + OSL_PCI_WRITE_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32), val32);
194 + bcm_mdelay(WRITE_ENABLE_DELAY);
195 + /* write srom */
196 + for (i = 0; i < nw; i++) {
197 + W_REG(&srom[off + i], p[i]);
198 + bcm_mdelay(WRITE_WORD_DELAY);
199 + }
200 + /* disable writes to the SPROM */
201 + OSL_PCI_WRITE_CONFIG(osh, PCI_SPROM_CONTROL, sizeof(uint32), val32 & ~SPROM_WRITEEN);
202 + } else {
203 + return 1;
204 + }
205 +
206 + bcm_mdelay(WRITE_ENABLE_DELAY);
207 + return 0;
208 +}
209 +
210 +
211 +/*
212 + * Read in and validate sprom.
213 + * Return 0 on success, nonzero on error.
214 + */
215 +static int
216 +sprom_read_pci(uint16 *sprom, uint wordoff, uint16 *buf, uint nwords, bool check_crc)
217 +{
218 + int err = 0;
219 + uint i;
220 +
221 + /* read the sprom */
222 + for (i = 0; i < nwords; i++)
223 + buf[i] = R_REG(&sprom[wordoff + i]);
224 +
225 + if (check_crc) {
226 + /* fixup the endianness so crc8 will pass */
227 + htol16_buf(buf, nwords * 2);
228 + if (hndcrc8((uint8*)buf, nwords * 2, CRC8_INIT_VALUE) != CRC8_GOOD_VALUE)
229 + err = 1;
230 + /* now correct the endianness of the byte array */
231 + ltoh16_buf(buf, nwords * 2);
232 + }
233 +
234 + return err;
235 +}
236 +
237 +/*
238 +* Create variable table from memory.
239 +* Return 0 on success, nonzero on error.
240 +*/
241 +static int
242 +initvars_table(osl_t *osh, char *start, char *end, char **vars, uint *count)
243 +{
244 + int c = (int)(end - start);
245 +
246 + /* do it only when there is more than just the null string */
247 + if (c > 1) {
248 + char *vp = MALLOC(osh, c);
249 + ASSERT(vp);
250 + if (!vp)
251 + return BCME_NOMEM;
252 + bcopy(start, vp, c);
253 + *vars = vp;
254 + *count = c;
255 + }
256 + else {
257 + *vars = NULL;
258 + *count = 0;
259 + }
260 +
261 + return 0;
262 +}
263 +
264 +/*
265 + * Initialize nonvolatile variable table from sprom.
266 + * Return 0 on success, nonzero on error.
267 + */
268 +static int
269 +initvars_srom_pci(void *sbh, void *curmap, char **vars, int *count)
270 +{
271 + uint16 w, b[64];
272 + uint8 sromrev;
273 + struct ether_addr ea;
274 + char eabuf[32];
275 + uint32 w32;
276 + int woff, i;
277 + char *vp, *base;
278 + osl_t *osh = sb_osh(sbh);
279 + char name[SB_DEVPATH_BUFSZ+16], *value;
280 + char devpath[SB_DEVPATH_BUFSZ];
281 + int err;
282 +
283 + /*
284 + * Apply CRC over SROM content regardless SROM is present or not,
285 + * and use variable <devpath>sromrev's existance in flash to decide
286 + * if we should return an error when CRC fails or read SROM variables
287 + * from flash.
288 + */
289 + sprom_read_pci((void*)((int8*)curmap + PCI_BAR0_SPROM_OFFSET), 0, b, sizeof(b)/sizeof(b[0]), TRUE);
290 +
291 + /* top word of sprom contains version and crc8 */
292 + sromrev = b[63] & 0xff;
293 + /* bcm4401 sroms misprogrammed */
294 + if (sromrev == 0x10)
295 + sromrev = 1;
296 +
297 + /* srom version check */
298 + if (sromrev > 3)
299 + return (-2);
300 +
301 + ASSERT(vars);
302 + ASSERT(count);
303 +
304 + base = vp = MALLOC(osh, VARS_MAX);
305 + ASSERT(vp);
306 + if (!vp)
307 + return -2;
308 +
309 + vp += sprintf(vp, "sromrev=%d", sromrev);
310 + vp++;
311 +
312 + if (sromrev >= 3) {
313 + /* New section takes over the 3th hardware function space */
314 +
315 + /* Words 22+23 are 11a (mid) ofdm power offsets */
316 + w32 = ((uint32)b[23] << 16) | b[22];
317 + vp += sprintf(vp, "ofdmapo=%d", w32);
318 + vp++;
319 +
320 + /* Words 24+25 are 11a (low) ofdm power offsets */
321 + w32 = ((uint32)b[25] << 16) | b[24];
322 + vp += sprintf(vp, "ofdmalpo=%d", w32);
323 + vp++;
324 +
325 + /* Words 26+27 are 11a (high) ofdm power offsets */
326 + w32 = ((uint32)b[27] << 16) | b[26];
327 + vp += sprintf(vp, "ofdmahpo=%d", w32);
328 + vp++;
329 +
330 + /*GPIO LED Powersave duty cycle (oncount >> 24) (offcount >> 8)*/
331 + w32 = ((uint32)b[43] << 24) | ((uint32)b[42] << 8);
332 + vp += sprintf(vp, "gpiotimerval=%d", w32);
333 +
334 + /*GPIO LED Powersave duty cycle (oncount >> 24) (offcount >> 8)*/
335 + w32 = ((uint32)((unsigned char)(b[21] >> 8) & 0xFF) << 24) | /* oncount*/
336 + ((uint32)((unsigned char)(b[21] & 0xFF)) << 8); /* offcount */
337 + vp += sprintf(vp, "gpiotimerval=%d", w32);
338 +
339 + vp++;
340 + }
341 +
342 + if (sromrev >= 2) {
343 + /* New section takes over the 4th hardware function space */
344 +
345 + /* Word 29 is max power 11a high/low */
346 + w = b[29];
347 + vp += sprintf(vp, "pa1himaxpwr=%d", w & 0xff);
348 + vp++;
349 + vp += sprintf(vp, "pa1lomaxpwr=%d", (w >> 8) & 0xff);
350 + vp++;
351 +
352 + /* Words 30-32 set the 11alow pa settings,
353 + * 33-35 are the 11ahigh ones.
354 + */
355 + for (i = 0; i < 3; i++) {
356 + vp += sprintf(vp, "pa1lob%d=%d", i, b[30 + i]);
357 + vp++;
358 + vp += sprintf(vp, "pa1hib%d=%d", i, b[33 + i]);
359 + vp++;
360 + }
361 + w = b[59];
362 + if (w == 0)
363 + vp += sprintf(vp, "ccode=");
364 + else
365 + vp += sprintf(vp, "ccode=%c%c", (w >> 8), (w & 0xff));
366 + vp++;
367 +
368 + }
369 +
370 + /* parameter section of sprom starts at byte offset 72 */
371 + woff = 72/2;
372 +
373 + /* first 6 bytes are il0macaddr */
374 + ea.octet[0] = (b[woff] >> 8) & 0xff;
375 + ea.octet[1] = b[woff] & 0xff;
376 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
377 + ea.octet[3] = b[woff+1] & 0xff;
378 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
379 + ea.octet[5] = b[woff+2] & 0xff;
380 + woff += ETHER_ADDR_LEN/2 ;
381 + bcm_ether_ntoa((uchar*)&ea, eabuf);
382 + vp += sprintf(vp, "il0macaddr=%s", eabuf);
383 + vp++;
384 +
385 + /* next 6 bytes are et0macaddr */
386 + ea.octet[0] = (b[woff] >> 8) & 0xff;
387 + ea.octet[1] = b[woff] & 0xff;
388 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
389 + ea.octet[3] = b[woff+1] & 0xff;
390 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
391 + ea.octet[5] = b[woff+2] & 0xff;
392 + woff += ETHER_ADDR_LEN/2 ;
393 + bcm_ether_ntoa((uchar*)&ea, eabuf);
394 + vp += sprintf(vp, "et0macaddr=%s", eabuf);
395 + vp++;
396 +
397 + /* next 6 bytes are et1macaddr */
398 + ea.octet[0] = (b[woff] >> 8) & 0xff;
399 + ea.octet[1] = b[woff] & 0xff;
400 + ea.octet[2] = (b[woff+1] >> 8) & 0xff;
401 + ea.octet[3] = b[woff+1] & 0xff;
402 + ea.octet[4] = (b[woff+2] >> 8) & 0xff;
403 + ea.octet[5] = b[woff+2] & 0xff;
404 + woff += ETHER_ADDR_LEN/2 ;
405 + bcm_ether_ntoa((uchar*)&ea, eabuf);
406 + vp += sprintf(vp, "et1macaddr=%s", eabuf);
407 + vp++;
408 +
409 + /*
410 + * Enet phy settings one or two singles or a dual
411 + * Bits 4-0 : MII address for enet0 (0x1f for not there)
412 + * Bits 9-5 : MII address for enet1 (0x1f for not there)
413 + * Bit 14 : Mdio for enet0
414 + * Bit 15 : Mdio for enet1
415 + */
416 + w = b[woff];
417 + vp += sprintf(vp, "et0phyaddr=%d", (w & 0x1f));
418 + vp++;
419 + vp += sprintf(vp, "et1phyaddr=%d", ((w >> 5) & 0x1f));
420 + vp++;
421 + vp += sprintf(vp, "et0mdcport=%d", ((w >> 14) & 0x1));
422 + vp++;
423 + vp += sprintf(vp, "et1mdcport=%d", ((w >> 15) & 0x1));
424 + vp++;
425 +
426 + /* Word 46 has board rev, antennas 0/1 & Country code/control */
427 + w = b[46];
428 + vp += sprintf(vp, "boardrev=%d", w & 0xff);
429 + vp++;
430 +
431 + if (sromrev > 1)
432 + vp += sprintf(vp, "cctl=%d", (w >> 8) & 0xf);
433 + else
434 + vp += sprintf(vp, "cc=%d", (w >> 8) & 0xf);
435 + vp++;
436 +
437 + vp += sprintf(vp, "aa0=%d", (w >> 12) & 0x3);
438 + vp++;
439 +
440 + vp += sprintf(vp, "aa1=%d", (w >> 14) & 0x3);
441 + vp++;
442 +
443 + /* Words 47-49 set the (wl) pa settings */
444 + woff = 47;
445 +
446 + for (i = 0; i < 3; i++) {
447 + vp += sprintf(vp, "pa0b%d=%d", i, b[woff+i]);
448 + vp++;
449 + vp += sprintf(vp, "pa1b%d=%d", i, b[woff+i+6]);
450 + vp++;
451 + }
452 +
453 + /*
454 + * Words 50-51 set the customer-configured wl led behavior.
455 + * 8 bits/gpio pin. High bit: activehi=0, activelo=1;
456 + * LED behavior values defined in wlioctl.h .
457 + */
458 + w = b[50];
459 + if ((w != 0) && (w != 0xffff)) {
460 + /* gpio0 */
461 + vp += sprintf(vp, "wl0gpio0=%d", (w & 0xff));
462 + vp++;
463 +
464 + /* gpio1 */
465 + vp += sprintf(vp, "wl0gpio1=%d", (w >> 8) & 0xff);
466 + vp++;
467 + }
468 + w = b[51];
469 + if ((w != 0) && (w != 0xffff)) {
470 + /* gpio2 */
471 + vp += sprintf(vp, "wl0gpio2=%d", w & 0xff);
472 + vp++;
473 +
474 + /* gpio3 */
475 + vp += sprintf(vp, "wl0gpio3=%d", (w >> 8) & 0xff);
476 + vp++;
477 + }
478 +
479 + /* Word 52 is max power 0/1 */
480 + w = b[52];
481 + vp += sprintf(vp, "pa0maxpwr=%d", w & 0xff);
482 + vp++;
483 + vp += sprintf(vp, "pa1maxpwr=%d", (w >> 8) & 0xff);
484 + vp++;
485 +
486 + /* Word 56 is idle tssi target 0/1 */
487 + w = b[56];
488 + vp += sprintf(vp, "pa0itssit=%d", w & 0xff);
489 + vp++;
490 + vp += sprintf(vp, "pa1itssit=%d", (w >> 8) & 0xff);
491 + vp++;
492 +
493 + /* Word 57 is boardflags, if not programmed make it zero */
494 + w32 = (uint32)b[57];
495 + if (w32 == 0xffff) w32 = 0;
496 + if (sromrev > 1) {
497 + /* Word 28 is the high bits of boardflags */
498 + w32 |= (uint32)b[28] << 16;
499 + }
500 + vp += sprintf(vp, "boardflags=%d", w32);
501 + vp++;
502 +
503 + /* Word 58 is antenna gain 0/1 */
504 + w = b[58];
505 + vp += sprintf(vp, "ag0=%d", w & 0xff);
506 + vp++;
507 +
508 + vp += sprintf(vp, "ag1=%d", (w >> 8) & 0xff);
509 + vp++;
510 +
511 + if (sromrev == 1) {
512 + /* set the oem string */
513 + vp += sprintf(vp, "oem=%02x%02x%02x%02x%02x%02x%02x%02x",
514 + ((b[59] >> 8) & 0xff), (b[59] & 0xff),
515 + ((b[60] >> 8) & 0xff), (b[60] & 0xff),
516 + ((b[61] >> 8) & 0xff), (b[61] & 0xff),
517 + ((b[62] >> 8) & 0xff), (b[62] & 0xff));
518 + vp++;
519 + } else if (sromrev == 2) {
520 + /* Word 60 OFDM tx power offset from CCK level */
521 + /* OFDM Power Offset - opo */
522 + vp += sprintf(vp, "opo=%d", b[60] & 0xff);
523 + vp++;
524 + } else {
525 + /* Word 60: cck power offsets */
526 + vp += sprintf(vp, "cckpo=%d", b[60]);
527 + vp++;
528 +
529 + /* Words 61+62: 11g ofdm power offsets */
530 + w32 = ((uint32)b[62] << 16) | b[61];
531 + vp += sprintf(vp, "ofdmgpo=%d", w32);
532 + vp++;
533 + }
534 +
535 + /* final nullbyte terminator */
536 + *vp++ = '\0';
537 +
538 + ASSERT((vp - base) <= VARS_MAX);
539 +
540 + err = initvars_table(osh, base, vp, vars, count);
541 +
542 + MFREE(osh, base, VARS_MAX);
543 + return err;
544 +}
545 +
546 diff -urN linux.old/arch/mips/bcm947xx/broadcom/bcmutils.c linux.dev/arch/mips/bcm947xx/broadcom/bcmutils.c
547 --- linux.old/arch/mips/bcm947xx/broadcom/bcmutils.c 1970-01-01 01:00:00.000000000 +0100
548 +++ linux.dev/arch/mips/bcm947xx/broadcom/bcmutils.c 2005-12-15 20:14:31.420035750 +0100
549 @@ -0,0 +1,358 @@
550 +/*
551 + * Misc useful OS-independent routines.
552 + *
553 + * Copyright 2005, Broadcom Corporation
554 + * All Rights Reserved.
555 + *
556 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
557 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
558 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
559 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
560 + * $Id$
561 + */
562 +
563 +#include <typedefs.h>
564 +#include <osl.h>
565 +#include <sbutils.h>
566 +#include <bcmnvram.h>
567 +#include <bcmutils.h>
568 +#include <bcmendian.h>
569 +#include <bcmdevs.h>
570 +
571 +unsigned char bcm_ctype[] = {
572 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 0-7 */
573 + _BCM_C,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C|_BCM_S,_BCM_C,_BCM_C, /* 8-15 */
574 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 16-23 */
575 + _BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C,_BCM_C, /* 24-31 */
576 + _BCM_S|_BCM_SP,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 32-39 */
577 + _BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 40-47 */
578 + _BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D,_BCM_D, /* 48-55 */
579 + _BCM_D,_BCM_D,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 56-63 */
580 + _BCM_P,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U|_BCM_X,_BCM_U, /* 64-71 */
581 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 72-79 */
582 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 80-87 */
583 + _BCM_U,_BCM_U,_BCM_U,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 88-95 */
584 + _BCM_P,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L|_BCM_X,_BCM_L, /* 96-103 */
585 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 104-111 */
586 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 112-119 */
587 + _BCM_L,_BCM_L,_BCM_L,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_C, /* 120-127 */
588 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 128-143 */
589 + 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 144-159 */
590 + _BCM_S|_BCM_SP,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 160-175 */
591 + _BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P,_BCM_P, /* 176-191 */
592 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U, /* 192-207 */
593 + _BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_P,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_U,_BCM_L, /* 208-223 */
594 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L, /* 224-239 */
595 + _BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_P,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L,_BCM_L /* 240-255 */
596 +};
597 +
598 +uchar
599 +bcm_toupper(uchar c)
600 +{
601 + if (bcm_islower(c))
602 + c -= 'a'-'A';
603 + return (c);
604 +}
605 +
606 +ulong
607 +bcm_strtoul(char *cp, char **endp, uint base)
608 +{
609 + ulong result, value;
610 + bool minus;
611 +
612 + minus = FALSE;
613 +
614 + while (bcm_isspace(*cp))
615 + cp++;
616 +
617 + if (cp[0] == '+')
618 + cp++;
619 + else if (cp[0] == '-') {
620 + minus = TRUE;
621 + cp++;
622 + }
623 +
624 + if (base == 0) {
625 + if (cp[0] == '0') {
626 + if ((cp[1] == 'x') || (cp[1] == 'X')) {
627 + base = 16;
628 + cp = &cp[2];
629 + } else {
630 + base = 8;
631 + cp = &cp[1];
632 + }
633 + } else
634 + base = 10;
635 + } else if (base == 16 && (cp[0] == '0') && ((cp[1] == 'x') || (cp[1] == 'X'))) {
636 + cp = &cp[2];
637 + }
638 +
639 + result = 0;
640 +
641 + while (bcm_isxdigit(*cp) &&
642 + (value = bcm_isdigit(*cp) ? *cp-'0' : bcm_toupper(*cp)-'A'+10) < base) {
643 + result = result*base + value;
644 + cp++;
645 + }
646 +
647 + if (minus)
648 + result = (ulong)(result * -1);
649 +
650 + if (endp)
651 + *endp = (char *)cp;
652 +
653 + return (result);
654 +}
655 +
656 +uint
657 +bcm_atoi(char *s)
658 +{
659 + uint n;
660 +
661 + n = 0;
662 +
663 + while (bcm_isdigit(*s))
664 + n = (n * 10) + *s++ - '0';
665 + return (n);
666 +}
667 +
668 +/* return pointer to location of substring 'needle' in 'haystack' */
669 +char*
670 +bcmstrstr(char *haystack, char *needle)
671 +{
672 + int len, nlen;
673 + int i;
674 +
675 + if ((haystack == NULL) || (needle == NULL))
676 + return (haystack);
677 +
678 + nlen = strlen(needle);
679 + len = strlen(haystack) - nlen + 1;
680 +
681 + for (i = 0; i < len; i++)
682 + if (bcmp(needle, &haystack[i], nlen) == 0)
683 + return (&haystack[i]);
684 + return (NULL);
685 +}
686 +
687 +char*
688 +bcmstrcat(char *dest, const char *src)
689 +{
690 + strcpy(&dest[strlen(dest)], src);
691 + return (dest);
692 +}
693 +
694 +
695 +char*
696 +bcm_ether_ntoa(char *ea, char *buf)
697 +{
698 + sprintf(buf,"%02x:%02x:%02x:%02x:%02x:%02x",
699 + (uchar)ea[0]&0xff, (uchar)ea[1]&0xff, (uchar)ea[2]&0xff,
700 + (uchar)ea[3]&0xff, (uchar)ea[4]&0xff, (uchar)ea[5]&0xff);
701 + return (buf);
702 +}
703 +
704 +/* parse a xx:xx:xx:xx:xx:xx format ethernet address */
705 +int
706 +bcm_ether_atoe(char *p, char *ea)
707 +{
708 + int i = 0;
709 +
710 + for (;;) {
711 + ea[i++] = (char) bcm_strtoul(p, &p, 16);
712 + if (!*p++ || i == 6)
713 + break;
714 + }
715 +
716 + return (i == 6);
717 +}
718 +
719 +void
720 +bcm_mdelay(uint ms)
721 +{
722 + uint i;
723 +
724 + for (i = 0; i < ms; i++) {
725 + OSL_DELAY(1000);
726 + }
727 +}
728 +
729 +/*
730 + * Search the name=value vars for a specific one and return its value.
731 + * Returns NULL if not found.
732 + */
733 +char*
734 +getvar(char *vars, char *name)
735 +{
736 + char *s;
737 + int len;
738 +
739 + len = strlen(name);
740 +
741 + /* first look in vars[] */
742 + for (s = vars; s && *s; ) {
743 + if ((bcmp(s, name, len) == 0) && (s[len] == '='))
744 + return (&s[len+1]);
745 +
746 + while (*s++)
747 + ;
748 + }
749 +
750 + /* then query nvram */
751 + return (BCMINIT(nvram_get)(name));
752 +}
753 +
754 +/*
755 + * Search the vars for a specific one and return its value as
756 + * an integer. Returns 0 if not found.
757 + */
758 +int
759 +getintvar(char *vars, char *name)
760 +{
761 + char *val;
762 +
763 + if ((val = getvar(vars, name)) == NULL)
764 + return (0);
765 +
766 + return (bcm_strtoul(val, NULL, 0));
767 +}
768 +
769 +
770 +/* Search for token in comma separated token-string */
771 +static int
772 +findmatch(char *string, char *name)
773 +{
774 + uint len;
775 + char *c;
776 +
777 + len = strlen(name);
778 + while ((c = strchr(string, ',')) != NULL) {
779 + if (len == (uint)(c - string) && !strncmp(string, name, len))
780 + return 1;
781 + string = c + 1;
782 + }
783 +
784 + return (!strcmp(string, name));
785 +}
786 +
787 +/* Return gpio pin number assigned to the named pin */
788 +/*
789 +* Variable should be in format:
790 +*
791 +* gpio<N>=pin_name,pin_name
792 +*
793 +* This format allows multiple features to share the gpio with mutual
794 +* understanding.
795 +*
796 +* 'def_pin' is returned if a specific gpio is not defined for the requested functionality
797 +* and if def_pin is not used by others.
798 +*/
799 +uint
800 +getgpiopin(char *vars, char *pin_name, uint def_pin)
801 +{
802 + char name[] = "gpioXXXX";
803 + char *val;
804 + uint pin;
805 +
806 + /* Go thru all possibilities till a match in pin name */
807 + for (pin = 0; pin < GPIO_NUMPINS; pin ++) {
808 + sprintf(name, "gpio%d", pin);
809 + val = getvar(vars, name);
810 + if (val && findmatch(val, pin_name))
811 + return pin;
812 + }
813 +
814 + if (def_pin != GPIO_PIN_NOTDEFINED) {
815 + /* make sure the default pin is not used by someone else */
816 + sprintf(name, "gpio%d", def_pin);
817 + if (getvar(vars, name)) {
818 + def_pin = GPIO_PIN_NOTDEFINED;
819 + }
820 + }
821 +
822 + return def_pin;
823 +}
824 +
825 +
826 +/*******************************************************************************
827 + * crc8
828 + *
829 + * Computes a crc8 over the input data using the polynomial:
830 + *
831 + * x^8 + x^7 +x^6 + x^4 + x^2 + 1
832 + *
833 + * The caller provides the initial value (either CRC8_INIT_VALUE
834 + * or the previous returned value) to allow for processing of
835 + * discontiguous blocks of data. When generating the CRC the
836 + * caller is responsible for complementing the final return value
837 + * and inserting it into the byte stream. When checking, a final
838 + * return value of CRC8_GOOD_VALUE indicates a valid CRC.
839 + *
840 + * Reference: Dallas Semiconductor Application Note 27
841 + * Williams, Ross N., "A Painless Guide to CRC Error Detection Algorithms",
842 + * ver 3, Aug 1993, ross@guest.adelaide.edu.au, Rocksoft Pty Ltd.,
843 + * ftp://ftp.rocksoft.com/clients/rocksoft/papers/crc_v3.txt
844 + *
845 + ******************************************************************************/
846 +
847 +static uint8 crc8_table[256] = {
848 + 0x00, 0xF7, 0xB9, 0x4E, 0x25, 0xD2, 0x9C, 0x6B,
849 + 0x4A, 0xBD, 0xF3, 0x04, 0x6F, 0x98, 0xD6, 0x21,
850 + 0x94, 0x63, 0x2D, 0xDA, 0xB1, 0x46, 0x08, 0xFF,
851 + 0xDE, 0x29, 0x67, 0x90, 0xFB, 0x0C, 0x42, 0xB5,
852 + 0x7F, 0x88, 0xC6, 0x31, 0x5A, 0xAD, 0xE3, 0x14,
853 + 0x35, 0xC2, 0x8C, 0x7B, 0x10, 0xE7, 0xA9, 0x5E,
854 + 0xEB, 0x1C, 0x52, 0xA5, 0xCE, 0x39, 0x77, 0x80,
855 + 0xA1, 0x56, 0x18, 0xEF, 0x84, 0x73, 0x3D, 0xCA,
856 + 0xFE, 0x09, 0x47, 0xB0, 0xDB, 0x2C, 0x62, 0x95,
857 + 0xB4, 0x43, 0x0D, 0xFA, 0x91, 0x66, 0x28, 0xDF,
858 + 0x6A, 0x9D, 0xD3, 0x24, 0x4F, 0xB8, 0xF6, 0x01,
859 + 0x20, 0xD7, 0x99, 0x6E, 0x05, 0xF2, 0xBC, 0x4B,
860 + 0x81, 0x76, 0x38, 0xCF, 0xA4, 0x53, 0x1D, 0xEA,
861 + 0xCB, 0x3C, 0x72, 0x85, 0xEE, 0x19, 0x57, 0xA0,
862 + 0x15, 0xE2, 0xAC, 0x5B, 0x30, 0xC7, 0x89, 0x7E,
863 + 0x5F, 0xA8, 0xE6, 0x11, 0x7A, 0x8D, 0xC3, 0x34,
864 + 0xAB, 0x5C, 0x12, 0xE5, 0x8E, 0x79, 0x37, 0xC0,
865 + 0xE1, 0x16, 0x58, 0xAF, 0xC4, 0x33, 0x7D, 0x8A,
866 + 0x3F, 0xC8, 0x86, 0x71, 0x1A, 0xED, 0xA3, 0x54,
867 + 0x75, 0x82, 0xCC, 0x3B, 0x50, 0xA7, 0xE9, 0x1E,
868 + 0xD4, 0x23, 0x6D, 0x9A, 0xF1, 0x06, 0x48, 0xBF,
869 + 0x9E, 0x69, 0x27, 0xD0, 0xBB, 0x4C, 0x02, 0xF5,
870 + 0x40, 0xB7, 0xF9, 0x0E, 0x65, 0x92, 0xDC, 0x2B,
871 + 0x0A, 0xFD, 0xB3, 0x44, 0x2F, 0xD8, 0x96, 0x61,
872 + 0x55, 0xA2, 0xEC, 0x1B, 0x70, 0x87, 0xC9, 0x3E,
873 + 0x1F, 0xE8, 0xA6, 0x51, 0x3A, 0xCD, 0x83, 0x74,
874 + 0xC1, 0x36, 0x78, 0x8F, 0xE4, 0x13, 0x5D, 0xAA,
875 + 0x8B, 0x7C, 0x32, 0xC5, 0xAE, 0x59, 0x17, 0xE0,
876 + 0x2A, 0xDD, 0x93, 0x64, 0x0F, 0xF8, 0xB6, 0x41,
877 + 0x60, 0x97, 0xD9, 0x2E, 0x45, 0xB2, 0xFC, 0x0B,
878 + 0xBE, 0x49, 0x07, 0xF0, 0x9B, 0x6C, 0x22, 0xD5,
879 + 0xF4, 0x03, 0x4D, 0xBA, 0xD1, 0x26, 0x68, 0x9F
880 +};
881 +
882 +#define CRC_INNER_LOOP(n, c, x) \
883 + (c) = ((c) >> 8) ^ crc##n##_table[((c) ^ (x)) & 0xff]
884 +
885 +uint8
886 +hndcrc8(
887 + uint8 *pdata, /* pointer to array of data to process */
888 + uint nbytes, /* number of input data bytes to process */
889 + uint8 crc /* either CRC8_INIT_VALUE or previous return value */
890 +)
891 +{
892 + /* hard code the crc loop instead of using CRC_INNER_LOOP macro
893 + * to avoid the undefined and unnecessary (uint8 >> 8) operation. */
894 + while (nbytes-- > 0)
895 + crc = crc8_table[(crc ^ *pdata++) & 0xff];
896 +
897 + return crc;
898 +}
899 +
900 +#ifdef notdef
901 +#define CLEN 1499
902 +#define CBUFSIZ (CLEN+4)
903 +#define CNBUFS 5
904 +
905 +#endif
906 +
907 +
908 diff -urN linux.old/arch/mips/bcm947xx/broadcom/linux_osl.c linux.dev/arch/mips/bcm947xx/broadcom/linux_osl.c
909 --- linux.old/arch/mips/bcm947xx/broadcom/linux_osl.c 1970-01-01 01:00:00.000000000 +0100
910 +++ linux.dev/arch/mips/bcm947xx/broadcom/linux_osl.c 2005-12-15 17:11:05.818041750 +0100
911 @@ -0,0 +1,102 @@
912 +/*
913 + * Linux OS Independent Layer
914 + *
915 + * Copyright 2005, Broadcom Corporation
916 + * All Rights Reserved.
917 + *
918 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
919 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
920 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
921 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
922 + *
923 + * $Id$
924 + */
925 +
926 +#define LINUX_OSL
927 +
928 +#include <typedefs.h>
929 +#include <bcmendian.h>
930 +#include <linux/module.h>
931 +#include <linuxver.h>
932 +#include <osl.h>
933 +#include <bcmutils.h>
934 +#include <linux/delay.h>
935 +#ifdef mips
936 +#include <asm/paccess.h>
937 +#endif
938 +#include <pcicfg.h>
939 +
940 +#define PCI_CFG_RETRY 10
941 +
942 +#define OS_HANDLE_MAGIC 0x1234abcd
943 +#define BCM_MEM_FILENAME_LEN 24
944 +
945 +typedef struct bcm_mem_link {
946 + struct bcm_mem_link *prev;
947 + struct bcm_mem_link *next;
948 + uint size;
949 + int line;
950 + char file[BCM_MEM_FILENAME_LEN];
951 +} bcm_mem_link_t;
952 +
953 +struct os_handle {
954 + uint magic;
955 + void *pdev;
956 + uint malloced;
957 + uint failed;
958 + bcm_mem_link_t *dbgmem_list;
959 +};
960 +
961 +uint32
962 +osl_pci_read_config(osl_t *osh, uint offset, uint size)
963 +{
964 + uint val;
965 + uint retry=PCI_CFG_RETRY;
966 +
967 + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
968 +
969 + /* only 4byte access supported */
970 + ASSERT(size == 4);
971 +
972 + do {
973 + pci_read_config_dword(osh->pdev, offset, &val);
974 + if (val != 0xffffffff)
975 + break;
976 + } while (retry--);
977 +
978 +
979 + return (val);
980 +}
981 +
982 +void
983 +osl_pci_write_config(osl_t *osh, uint offset, uint size, uint val)
984 +{
985 + uint retry=PCI_CFG_RETRY;
986 +
987 + ASSERT((osh && (osh->magic == OS_HANDLE_MAGIC)));
988 +
989 + /* only 4byte access supported */
990 + ASSERT(size == 4);
991 +
992 + do {
993 + pci_write_config_dword(osh->pdev, offset, val);
994 + if (offset!=PCI_BAR0_WIN)
995 + break;
996 + if (osl_pci_read_config(osh,offset,size) == val)
997 + break;
998 + } while (retry--);
999 +
1000 +}
1001 +
1002 +void
1003 +osl_delay(uint usec)
1004 +{
1005 + uint d;
1006 +
1007 + while (usec > 0) {
1008 + d = MIN(usec, 1000);
1009 + udelay(d);
1010 + usec -= d;
1011 + }
1012 +}
1013 +
1014 diff -urN linux.old/arch/mips/bcm947xx/broadcom/nvram.c linux.dev/arch/mips/bcm947xx/broadcom/nvram.c
1015 --- linux.old/arch/mips/bcm947xx/broadcom/nvram.c 1970-01-01 01:00:00.000000000 +0100
1016 +++ linux.dev/arch/mips/bcm947xx/broadcom/nvram.c 2005-12-15 17:36:23.151078000 +0100
1017 @@ -0,0 +1,145 @@
1018 +/*
1019 + * NVRAM variable manipulation (Linux kernel half)
1020 + *
1021 + * Copyright 2005, Broadcom Corporation
1022 + * All Rights Reserved.
1023 + *
1024 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1025 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1026 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1027 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1028 + *
1029 + * $Id$
1030 + */
1031 +
1032 +#include <linux/config.h>
1033 +#include <linux/init.h>
1034 +#include <linux/module.h>
1035 +#include <linux/kernel.h>
1036 +#include <linux/string.h>
1037 +#include <linux/interrupt.h>
1038 +#include <linux/spinlock.h>
1039 +#include <linux/slab.h>
1040 +#include <linux/bootmem.h>
1041 +#include <asm/addrspace.h>
1042 +#include <asm/io.h>
1043 +#include <asm/uaccess.h>
1044 +
1045 +#include <typedefs.h>
1046 +#include <bcmendian.h>
1047 +#include <bcmnvram.h>
1048 +#include <bcmutils.h>
1049 +#include <sbconfig.h>
1050 +#include <sbchipc.h>
1051 +#include <sbutils.h>
1052 +#include <sbmips.h>
1053 +#include <sflash.h>
1054 +
1055 +/* In BSS to minimize text size and page aligned so it can be mmap()-ed */
1056 +static char nvram_buf[NVRAM_SPACE] __attribute__((aligned(PAGE_SIZE)));
1057 +
1058 +/* Global SB handle */
1059 +extern void *sbh;
1060 +extern spinlock_t bcm947xx_sbh_lock;
1061 +
1062 +/* Convenience */
1063 +#define sbh_lock bcm947xx_sbh_lock
1064 +#define KB * 1024
1065 +#define MB * 1024 * 1024
1066 +
1067 +/* Probe for NVRAM header */
1068 +static void __init
1069 +early_nvram_init(void)
1070 +{
1071 + struct nvram_header *header;
1072 + chipcregs_t *cc;
1073 + struct sflash *info = NULL;
1074 + int i;
1075 + uint32 base, off, lim;
1076 + u32 *src, *dst;
1077 +
1078 + if ((cc = sb_setcore(sbh, SB_CC, 0)) != NULL) {
1079 + base = KSEG1ADDR(SB_FLASH2);
1080 + switch (readl(&cc->capabilities) & CAP_FLASH_MASK) {
1081 + case PFLASH:
1082 + lim = SB_FLASH2_SZ;
1083 + break;
1084 +
1085 + case SFLASH_ST:
1086 + case SFLASH_AT:
1087 + if ((info = sflash_init(cc)) == NULL)
1088 + return;
1089 + lim = info->size;
1090 + break;
1091 +
1092 + case FLASH_NONE:
1093 + default:
1094 + return;
1095 + }
1096 + } else {
1097 + /* extif assumed, Stop at 4 MB */
1098 + base = KSEG1ADDR(SB_FLASH1);
1099 + lim = SB_FLASH1_SZ;
1100 + }
1101 +
1102 + off = FLASH_MIN;
1103 + while (off <= lim) {
1104 + /* Windowed flash access */
1105 + header = (struct nvram_header *) KSEG1ADDR(base + off - NVRAM_SPACE);
1106 + if (header->magic == NVRAM_MAGIC)
1107 + goto found;
1108 + off <<= 1;
1109 + }
1110 +
1111 + /* Try embedded NVRAM at 4 KB and 1 KB as last resorts */
1112 + header = (struct nvram_header *) KSEG1ADDR(base + 4 KB);
1113 + if (header->magic == NVRAM_MAGIC)
1114 + goto found;
1115 +
1116 + header = (struct nvram_header *) KSEG1ADDR(base + 1 KB);
1117 + if (header->magic == NVRAM_MAGIC)
1118 + goto found;
1119 +
1120 + printk("early_nvram_init: NVRAM not found\n");
1121 + return;
1122 +
1123 +found:
1124 + src = (u32 *) header;
1125 + dst = (u32 *) nvram_buf;
1126 + for (i = 0; i < sizeof(struct nvram_header); i += 4)
1127 + *dst++ = *src++;
1128 + for (; i < header->len && i < NVRAM_SPACE; i += 4)
1129 + *dst++ = ltoh32(*src++);
1130 +}
1131 +
1132 +/* Early (before mm or mtd) read-only access to NVRAM */
1133 +char * __init nvram_get(const char *name)
1134 +{
1135 + char *var, *value, *end, *eq;
1136 +
1137 + if (!name)
1138 + return NULL;
1139 +
1140 + /* Too early? */
1141 + if (sbh == NULL)
1142 + return NULL;
1143 +
1144 + if (!nvram_buf[0])
1145 + early_nvram_init();
1146 +
1147 + /* Look for name=value and return value */
1148 + var = &nvram_buf[sizeof(struct nvram_header)];
1149 + end = nvram_buf + sizeof(nvram_buf) - 2;
1150 + end[0] = end[1] = '\0';
1151 + for (; *var; var = value + strlen(value) + 1) {
1152 + if (!(eq = strchr(var, '=')))
1153 + break;
1154 + value = eq + 1;
1155 + if ((eq - var) == strlen(name) && strncmp(var, name, (eq - var)) == 0)
1156 + return value;
1157 + }
1158 +
1159 + return NULL;
1160 +}
1161 +
1162 +EXPORT_SYMBOL(nvram_get);
1163 diff -urN linux.old/arch/mips/bcm947xx/broadcom/sbmips.c linux.dev/arch/mips/bcm947xx/broadcom/sbmips.c
1164 --- linux.old/arch/mips/bcm947xx/broadcom/sbmips.c 1970-01-01 01:00:00.000000000 +0100
1165 +++ linux.dev/arch/mips/bcm947xx/broadcom/sbmips.c 2005-12-15 16:46:31.122961250 +0100
1166 @@ -0,0 +1,1038 @@
1167 +/*
1168 + * BCM47XX Sonics SiliconBackplane MIPS core routines
1169 + *
1170 + * Copyright 2005, Broadcom Corporation
1171 + * All Rights Reserved.
1172 + *
1173 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
1174 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
1175 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
1176 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
1177 + *
1178 + * $Id$
1179 + */
1180 +
1181 +#include <typedefs.h>
1182 +#include <osl.h>
1183 +#include <sbutils.h>
1184 +#include <bcmdevs.h>
1185 +#include <bcmnvram.h>
1186 +#include <bcmutils.h>
1187 +#include <hndmips.h>
1188 +#include <sbconfig.h>
1189 +#include <sbextif.h>
1190 +#include <sbchipc.h>
1191 +#include <sbmemc.h>
1192 +#include <mipsinc.h>
1193 +#include <sbutils.h>
1194 +
1195 +/*
1196 + * Returns TRUE if an external UART exists at the given base
1197 + * register.
1198 + */
1199 +static bool
1200 +BCMINITFN(serial_exists)(uint8 *regs)
1201 +{
1202 + uint8 save_mcr, status1;
1203 +
1204 + save_mcr = R_REG(&regs[UART_MCR]);
1205 + W_REG(&regs[UART_MCR], UART_MCR_LOOP | 0x0a);
1206 + status1 = R_REG(&regs[UART_MSR]) & 0xf0;
1207 + W_REG(&regs[UART_MCR], save_mcr);
1208 +
1209 + return (status1 == 0x90);
1210 +}
1211 +
1212 +/*
1213 + * Initializes UART access. The callback function will be called once
1214 + * per found UART.
1215 + */
1216 +void
1217 +BCMINITFN(sb_serial_init)(sb_t *sbh, void (*add)(void *regs, uint irq, uint baud_base, uint reg_shift))
1218 +{
1219 + void *regs;
1220 + ulong base;
1221 + uint irq;
1222 + int i, n;
1223 +
1224 + if ((regs = sb_setcore(sbh, SB_EXTIF, 0))) {
1225 + extifregs_t *eir = (extifregs_t *) regs;
1226 + sbconfig_t *sb;
1227 +
1228 + /* Determine external UART register base */
1229 + sb = (sbconfig_t *)((ulong) eir + SBCONFIGOFF);
1230 + base = EXTIF_CFGIF_BASE(sb_base(R_REG(&sb->sbadmatch1)));
1231 +
1232 + /* Determine IRQ */
1233 + irq = sb_irq(sbh);
1234 +
1235 + /* Disable GPIO interrupt initially */
1236 + W_REG(&eir->gpiointpolarity, 0);
1237 + W_REG(&eir->gpiointmask, 0);
1238 +
1239 + /* Search for external UARTs */
1240 + n = 2;
1241 + for (i = 0; i < 2; i++) {
1242 + regs = (void *) REG_MAP(base + (i * 8), 8);
1243 + if (BCMINIT(serial_exists)(regs)) {
1244 + /* Set GPIO 1 to be the external UART IRQ */
1245 + W_REG(&eir->gpiointmask, 2);
1246 + if (add)
1247 + add(regs, irq, 13500000, 0);
1248 + }
1249 + }
1250 +
1251 + /* Add internal UART if enabled */
1252 + if (R_REG(&eir->corecontrol) & CC_UE)
1253 + if (add)
1254 + add((void *) &eir->uartdata, irq, sb_clock(sbh), 2);
1255 + } else if ((regs = sb_setcore(sbh, SB_CC, 0))) {
1256 + chipcregs_t *cc = (chipcregs_t *) regs;
1257 + uint32 rev, cap, pll, baud_base, div;
1258 +
1259 + /* Determine core revision and capabilities */
1260 + rev = sb_corerev(sbh);
1261 + cap = R_REG(&cc->capabilities);
1262 + pll = cap & CAP_PLL_MASK;
1263 +
1264 + /* Determine IRQ */
1265 + irq = sb_irq(sbh);
1266 +
1267 + if (pll == PLL_TYPE1) {
1268 + /* PLL clock */
1269 + baud_base = sb_clock_rate(pll,
1270 + R_REG(&cc->clockcontrol_n),
1271 + R_REG(&cc->clockcontrol_m2));
1272 + div = 1;
1273 + } else {
1274 + if (rev >= 11) {
1275 + /* Fixed ALP clock */
1276 + baud_base = 20000000;
1277 + div = 1;
1278 + /* Set the override bit so we don't divide it */
1279 + W_REG(&cc->corecontrol, CC_UARTCLKO);
1280 + } else if (rev >= 3) {
1281 + /* Internal backplane clock */
1282 + baud_base = sb_clock(sbh);
1283 + div = 2; /* Minimum divisor */
1284 + W_REG(&cc->clkdiv,
1285 + ((R_REG(&cc->clkdiv) & ~CLKD_UART) | div));
1286 + } else {
1287 + /* Fixed internal backplane clock */
1288 + baud_base = 88000000;
1289 + div = 48;
1290 + }
1291 +
1292 + /* Clock source depends on strapping if UartClkOverride is unset */
1293 + if ((rev > 0) &&
1294 + ((R_REG(&cc->corecontrol) & CC_UARTCLKO) == 0)) {
1295 + if ((cap & CAP_UCLKSEL) == CAP_UINTCLK) {
1296 + /* Internal divided backplane clock */
1297 + baud_base /= div;
1298 + } else {
1299 + /* Assume external clock of 1.8432 MHz */
1300 + baud_base = 1843200;
1301 + }
1302 + }
1303 + }
1304 +
1305 + /* Add internal UARTs */
1306 + n = cap & CAP_UARTS_MASK;
1307 + for (i = 0; i < n; i++) {
1308 + /* Register offset changed after revision 0 */
1309 + if (rev)
1310 + regs = (void *)((ulong) &cc->uart0data + (i * 256));
1311 + else
1312 + regs = (void *)((ulong) &cc->uart0data + (i * 8));
1313 +
1314 + if (add)
1315 + add(regs, irq, baud_base, 0);
1316 + }
1317 + }
1318 +}
1319 +
1320 +/*
1321 + * Initialize jtag master and return handle for
1322 + * jtag_rwreg. Returns NULL on failure.
1323 + */
1324 +void *
1325 +sb_jtagm_init(sb_t *sbh, uint clkd, bool exttap)
1326 +{
1327 + void *regs;
1328 +
1329 + if ((regs = sb_setcore(sbh, SB_CC, 0)) != NULL) {
1330 + chipcregs_t *cc = (chipcregs_t *) regs;
1331 + uint32 tmp;
1332 +
1333 + /*
1334 + * Determine jtagm availability from
1335 + * core revision and capabilities.
1336 + */
1337 + tmp = sb_corerev(sbh);
1338 + /*
1339 + * Corerev 10 has jtagm, but the only chip
1340 + * with it does not have a mips, and
1341 + * the layout of the jtagcmd register is
1342 + * different. We'll only accept >= 11.
1343 + */
1344 + if (tmp < 11)
1345 + return (NULL);
1346 +
1347 + tmp = R_REG(&cc->capabilities);
1348 + if ((tmp & CAP_JTAGP) == 0)
1349 + return (NULL);
1350 +
1351 + /* Set clock divider if requested */
1352 + if (clkd != 0) {
1353 + tmp = R_REG(&cc->clkdiv);
1354 + tmp = (tmp & ~CLKD_JTAG) |
1355 + ((clkd << CLKD_JTAG_SHIFT) & CLKD_JTAG);
1356 + W_REG(&cc->clkdiv, tmp);
1357 + }
1358 +
1359 + /* Enable jtagm */
1360 + tmp = JCTRL_EN | (exttap ? JCTRL_EXT_EN : 0);
1361 + W_REG(&cc->jtagctrl, tmp);
1362 + }
1363 +
1364 + return (regs);
1365 +}
1366 +
1367 +void
1368 +sb_jtagm_disable(void *h)
1369 +{
1370 + chipcregs_t *cc = (chipcregs_t *)h;
1371 +
1372 + W_REG(&cc->jtagctrl, R_REG(&cc->jtagctrl) & ~JCTRL_EN);
1373 +}
1374 +
1375 +/*
1376 + * Read/write a jtag register. Assumes a target with
1377 + * 8 bit IR and 32 bit DR.
1378 + */
1379 +#define IRWIDTH 8
1380 +#define DRWIDTH 32
1381 +uint32
1382 +jtag_rwreg(void *h, uint32 ir, uint32 dr)
1383 +{
1384 + chipcregs_t *cc = (chipcregs_t *) h;
1385 + uint32 tmp;
1386 +
1387 + W_REG(&cc->jtagir, ir);
1388 + W_REG(&cc->jtagdr, dr);
1389 + tmp = JCMD_START | JCMD_ACC_IRDR |
1390 + ((IRWIDTH - 1) << JCMD_IRW_SHIFT) |
1391 + (DRWIDTH - 1);
1392 + W_REG(&cc->jtagcmd, tmp);
1393 + while (((tmp = R_REG(&cc->jtagcmd)) & JCMD_BUSY) == JCMD_BUSY) {
1394 + /* OSL_DELAY(1); */
1395 + }
1396 +
1397 + tmp = R_REG(&cc->jtagdr);
1398 + return (tmp);
1399 +}
1400 +
1401 +/* Returns the SB interrupt flag of the current core. */
1402 +uint32
1403 +sb_flag(sb_t *sbh)
1404 +{
1405 + void *regs;
1406 + sbconfig_t *sb;
1407 +
1408 + regs = sb_coreregs(sbh);
1409 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
1410 +
1411 + return (R_REG(&sb->sbtpsflag) & SBTPS_NUM0_MASK);
1412 +}
1413 +
1414 +static const uint32 sbips_int_mask[] = {
1415 + 0,
1416 + SBIPS_INT1_MASK,
1417 + SBIPS_INT2_MASK,
1418 + SBIPS_INT3_MASK,
1419 + SBIPS_INT4_MASK
1420 +};
1421 +
1422 +static const uint32 sbips_int_shift[] = {
1423 + 0,
1424 + 0,
1425 + SBIPS_INT2_SHIFT,
1426 + SBIPS_INT3_SHIFT,
1427 + SBIPS_INT4_SHIFT
1428 +};
1429 +
1430 +/*
1431 + * Returns the MIPS IRQ assignment of the current core. If unassigned,
1432 + * 0 is returned.
1433 + */
1434 +uint
1435 +sb_irq(sb_t *sbh)
1436 +{
1437 + uint idx;
1438 + void *regs;
1439 + sbconfig_t *sb;
1440 + uint32 flag, sbipsflag;
1441 + uint irq = 0;
1442 +
1443 + flag = sb_flag(sbh);
1444 +
1445 + idx = sb_coreidx(sbh);
1446 +
1447 + if ((regs = sb_setcore(sbh, SB_MIPS, 0)) ||
1448 + (regs = sb_setcore(sbh, SB_MIPS33, 0))) {
1449 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
1450 +
1451 + /* sbipsflag specifies which core is routed to interrupts 1 to 4 */
1452 + sbipsflag = R_REG(&sb->sbipsflag);
1453 + for (irq = 1; irq <= 4; irq++) {
1454 + if (((sbipsflag & sbips_int_mask[irq]) >> sbips_int_shift[irq]) == flag)
1455 + break;
1456 + }
1457 + if (irq == 5)
1458 + irq = 0;
1459 + }
1460 +
1461 + sb_setcoreidx(sbh, idx);
1462 +
1463 + return irq;
1464 +}
1465 +
1466 +/* Clears the specified MIPS IRQ. */
1467 +static void
1468 +BCMINITFN(sb_clearirq)(sb_t *sbh, uint irq)
1469 +{
1470 + void *regs;
1471 + sbconfig_t *sb;
1472 +
1473 + if (!(regs = sb_setcore(sbh, SB_MIPS, 0)) &&
1474 + !(regs = sb_setcore(sbh, SB_MIPS33, 0)))
1475 + ASSERT(regs);
1476 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
1477 +
1478 + if (irq == 0)
1479 + W_REG(&sb->sbintvec, 0);
1480 + else
1481 + OR_REG(&sb->sbipsflag, sbips_int_mask[irq]);
1482 +}
1483 +
1484 +/*
1485 + * Assigns the specified MIPS IRQ to the specified core. Shared MIPS
1486 + * IRQ 0 may be assigned more than once.
1487 + */
1488 +static void
1489 +BCMINITFN(sb_setirq)(sb_t *sbh, uint irq, uint coreid, uint coreunit)
1490 +{
1491 + void *regs;
1492 + sbconfig_t *sb;
1493 + uint32 flag;
1494 +
1495 + regs = sb_setcore(sbh, coreid, coreunit);
1496 + ASSERT(regs);
1497 + flag = sb_flag(sbh);
1498 +
1499 + if (!(regs = sb_setcore(sbh, SB_MIPS, 0)) &&
1500 + !(regs = sb_setcore(sbh, SB_MIPS33, 0)))
1501 + ASSERT(regs);
1502 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
1503 +
1504 + if (irq == 0)
1505 + OR_REG(&sb->sbintvec, 1 << flag);
1506 + else {
1507 + flag <<= sbips_int_shift[irq];
1508 + ASSERT(!(flag & ~sbips_int_mask[irq]));
1509 + flag |= R_REG(&sb->sbipsflag) & ~sbips_int_mask[irq];
1510 + W_REG(&sb->sbipsflag, flag);
1511 + }
1512 +}
1513 +
1514 +/*
1515 + * Initializes clocks and interrupts. SB and NVRAM access must be
1516 + * initialized prior to calling.
1517 + */
1518 +void
1519 +BCMINITFN(sb_mips_init)(sb_t *sbh)
1520 +{
1521 + ulong hz, ns, tmp;
1522 + extifregs_t *eir;
1523 + chipcregs_t *cc;
1524 + char *value;
1525 + uint irq;
1526 +
1527 + /* Figure out current SB clock speed */
1528 + if ((hz = sb_clock(sbh)) == 0)
1529 + hz = 100000000;
1530 + ns = 1000000000 / hz;
1531 +
1532 + /* Setup external interface timing */
1533 + if ((eir = sb_setcore(sbh, SB_EXTIF, 0))) {
1534 + /* Initialize extif so we can get to the LEDs and external UART */
1535 + W_REG(&eir->prog_config, CF_EN);
1536 +
1537 + /* Set timing for the flash */
1538 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
1539 + tmp = tmp | (CEIL(40, ns) << FW_W1_SHIFT); /* W1 = 40nS */
1540 + tmp = tmp | CEIL(120, ns); /* W0 = 120nS */
1541 + W_REG(&eir->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
1542 +
1543 + /* Set programmable interface timing for external uart */
1544 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
1545 + tmp = tmp | (CEIL(20, ns) << FW_W2_SHIFT); /* W2 = 20nS */
1546 + tmp = tmp | (CEIL(100, ns) << FW_W1_SHIFT); /* W1 = 100nS */
1547 + tmp = tmp | CEIL(120, ns); /* W0 = 120nS */
1548 + W_REG(&eir->prog_waitcount, tmp); /* 0x01020a0c for a 100Mhz clock */
1549 + } else if ((cc = sb_setcore(sbh, SB_CC, 0))) {
1550 + /* Set timing for the flash */
1551 + tmp = CEIL(10, ns) << FW_W3_SHIFT; /* W3 = 10nS */
1552 + tmp |= CEIL(10, ns) << FW_W1_SHIFT; /* W1 = 10nS */
1553 + tmp |= CEIL(120, ns); /* W0 = 120nS */
1554 +
1555 + // Added by Chen-I for 5365
1556 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID)
1557 + {
1558 + W_REG(&cc->flash_waitcount, tmp);
1559 + W_REG(&cc->pcmcia_memwait, tmp);
1560 + }
1561 + else
1562 + {
1563 + if (sb_corerev(sbh) < 9)
1564 + W_REG(&cc->flash_waitcount, tmp);
1565 +
1566 + if ((sb_corerev(sbh) < 9) ||
1567 + ((BCMINIT(sb_chip)(sbh) == BCM5350_DEVICE_ID) && BCMINIT(sb_chiprev)(sbh) == 0)) {
1568 + W_REG(&cc->pcmcia_memwait, tmp);
1569 + }
1570 + }
1571 + }
1572 +
1573 + /* Chip specific initialization */
1574 + switch (BCMINIT(sb_chip)(sbh)) {
1575 + case BCM4710_DEVICE_ID:
1576 + /* Clear interrupt map */
1577 + for (irq = 0; irq <= 4; irq++)
1578 + BCMINIT(sb_clearirq)(sbh, irq);
1579 + BCMINIT(sb_setirq)(sbh, 0, SB_CODEC, 0);
1580 + BCMINIT(sb_setirq)(sbh, 0, SB_EXTIF, 0);
1581 + BCMINIT(sb_setirq)(sbh, 2, SB_ENET, 1);
1582 + BCMINIT(sb_setirq)(sbh, 3, SB_ILINE20, 0);
1583 + BCMINIT(sb_setirq)(sbh, 4, SB_PCI, 0);
1584 + ASSERT(eir);
1585 + value = BCMINIT(nvram_get)("et0phyaddr");
1586 + if (value && !strcmp(value, "31")) {
1587 + /* Enable internal UART */
1588 + W_REG(&eir->corecontrol, CC_UE);
1589 + /* Give USB its own interrupt */
1590 + BCMINIT(sb_setirq)(sbh, 1, SB_USB, 0);
1591 + } else {
1592 + /* Disable internal UART */
1593 + W_REG(&eir->corecontrol, 0);
1594 + /* Give Ethernet its own interrupt */
1595 + BCMINIT(sb_setirq)(sbh, 1, SB_ENET, 0);
1596 + BCMINIT(sb_setirq)(sbh, 0, SB_USB, 0);
1597 + }
1598 + break;
1599 + case BCM5350_DEVICE_ID:
1600 + /* Clear interrupt map */
1601 + for (irq = 0; irq <= 4; irq++)
1602 + BCMINIT(sb_clearirq)(sbh, irq);
1603 + BCMINIT(sb_setirq)(sbh, 0, SB_CC, 0);
1604 + BCMINIT(sb_setirq)(sbh, 1, SB_D11, 0);
1605 + BCMINIT(sb_setirq)(sbh, 2, SB_ENET, 0);
1606 + BCMINIT(sb_setirq)(sbh, 3, SB_PCI, 0);
1607 + BCMINIT(sb_setirq)(sbh, 4, SB_USB, 0);
1608 + break;
1609 + }
1610 +}
1611 +
1612 +uint32
1613 +BCMINITFN(sb_mips_clock)(sb_t *sbh)
1614 +{
1615 + extifregs_t *eir;
1616 + chipcregs_t *cc;
1617 + uint32 n, m;
1618 + uint idx;
1619 + uint32 pll_type, rate = 0;
1620 +
1621 + /* get index of the current core */
1622 + idx = sb_coreidx(sbh);
1623 + pll_type = PLL_TYPE1;
1624 +
1625 + /* switch to extif or chipc core */
1626 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
1627 + n = R_REG(&eir->clockcontrol_n);
1628 + m = R_REG(&eir->clockcontrol_sb);
1629 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
1630 + pll_type = R_REG(&cc->capabilities) & CAP_PLL_MASK;
1631 + n = R_REG(&cc->clockcontrol_n);
1632 + if ((pll_type == PLL_TYPE2) ||
1633 + (pll_type == PLL_TYPE4) ||
1634 + (pll_type == PLL_TYPE6) ||
1635 + (pll_type == PLL_TYPE7))
1636 + m = R_REG(&cc->clockcontrol_mips);
1637 + else if (pll_type == PLL_TYPE5) {
1638 + rate = 200000000;
1639 + goto out;
1640 + }
1641 + else if (pll_type == PLL_TYPE3) {
1642 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID) { /* 5365 is also type3 */
1643 + rate = 200000000;
1644 + goto out;
1645 + } else
1646 + m = R_REG(&cc->clockcontrol_m2); /* 5350 uses m2 to control mips */
1647 + } else
1648 + m = R_REG(&cc->clockcontrol_sb);
1649 + } else
1650 + goto out;
1651 +
1652 + // Added by Chen-I for 5365
1653 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID)
1654 + rate = 100000000;
1655 + else
1656 + /* calculate rate */
1657 + rate = sb_clock_rate(pll_type, n, m);
1658 +
1659 + if (pll_type == PLL_TYPE6)
1660 + rate = SB2MIPS_T6(rate);
1661 +
1662 +out:
1663 + /* switch back to previous core */
1664 + sb_setcoreidx(sbh, idx);
1665 +
1666 + return rate;
1667 +}
1668 +
1669 +#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4)
1670 +
1671 +static void
1672 +BCMINITFN(handler)(void)
1673 +{
1674 + /* Step 11 */
1675 + __asm__ (
1676 + ".set\tmips32\n\t"
1677 + "ssnop\n\t"
1678 + "ssnop\n\t"
1679 + /* Disable interrupts */
1680 + /* MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) & ~(ALLINTS | STO_IE)); */
1681 + "mfc0 $15, $12\n\t"
1682 + /* Just a Hack to not to use reg 'at' which was causing problems on 4704 A2 */
1683 + "li $14, -31746\n\t"
1684 + "and $15, $15, $14\n\t"
1685 + "mtc0 $15, $12\n\t"
1686 + "eret\n\t"
1687 + "nop\n\t"
1688 + "nop\n\t"
1689 + ".set\tmips0"
1690 + );
1691 +}
1692 +
1693 +/* The following MUST come right after handler() */
1694 +static void
1695 +BCMINITFN(afterhandler)(void)
1696 +{
1697 +}
1698 +
1699 +/*
1700 + * Set the MIPS, backplane and PCI clocks as closely as possible.
1701 + */
1702 +bool
1703 +BCMINITFN(sb_mips_setclock)(sb_t *sbh, uint32 mipsclock, uint32 sbclock, uint32 pciclock)
1704 +{
1705 + extifregs_t *eir = NULL;
1706 + chipcregs_t *cc = NULL;
1707 + mipsregs_t *mipsr = NULL;
1708 + volatile uint32 *clockcontrol_n, *clockcontrol_sb, *clockcontrol_pci, *clockcontrol_m2;
1709 + uint32 orig_n, orig_sb, orig_pci, orig_m2, orig_mips, orig_ratio_parm, orig_ratio_cfg;
1710 + uint32 pll_type, sync_mode;
1711 + uint ic_size, ic_lsize;
1712 + uint idx, i;
1713 + typedef struct {
1714 + uint32 mipsclock;
1715 + uint16 n;
1716 + uint32 sb;
1717 + uint32 pci33;
1718 + uint32 pci25;
1719 + } n3m_table_t;
1720 + static n3m_table_t BCMINITDATA(type1_table)[] = {
1721 + { 96000000, 0x0303, 0x04020011, 0x11030011, 0x11050011 }, /* 96.000 32.000 24.000 */
1722 + { 100000000, 0x0009, 0x04020011, 0x11030011, 0x11050011 }, /* 100.000 33.333 25.000 */
1723 + { 104000000, 0x0802, 0x04020011, 0x11050009, 0x11090009 }, /* 104.000 31.200 24.960 */
1724 + { 108000000, 0x0403, 0x04020011, 0x11050009, 0x02000802 }, /* 108.000 32.400 24.923 */
1725 + { 112000000, 0x0205, 0x04020011, 0x11030021, 0x02000403 }, /* 112.000 32.000 24.889 */
1726 + { 115200000, 0x0303, 0x04020009, 0x11030011, 0x11050011 }, /* 115.200 32.000 24.000 */
1727 + { 120000000, 0x0011, 0x04020011, 0x11050011, 0x11090011 }, /* 120.000 30.000 24.000 */
1728 + { 124800000, 0x0802, 0x04020009, 0x11050009, 0x11090009 }, /* 124.800 31.200 24.960 */
1729 + { 128000000, 0x0305, 0x04020011, 0x11050011, 0x02000305 }, /* 128.000 32.000 24.000 */
1730 + { 132000000, 0x0603, 0x04020011, 0x11050011, 0x02000305 }, /* 132.000 33.000 24.750 */
1731 + { 136000000, 0x0c02, 0x04020011, 0x11090009, 0x02000603 }, /* 136.000 32.640 24.727 */
1732 + { 140000000, 0x0021, 0x04020011, 0x11050021, 0x02000c02 }, /* 140.000 30.000 24.706 */
1733 + { 144000000, 0x0405, 0x04020011, 0x01020202, 0x11090021 }, /* 144.000 30.857 24.686 */
1734 + { 150857142, 0x0605, 0x04020021, 0x02000305, 0x02000605 }, /* 150.857 33.000 24.000 */
1735 + { 152000000, 0x0e02, 0x04020011, 0x11050021, 0x02000e02 }, /* 152.000 32.571 24.000 */
1736 + { 156000000, 0x0802, 0x04020005, 0x11050009, 0x11090009 }, /* 156.000 31.200 24.960 */
1737 + { 160000000, 0x0309, 0x04020011, 0x11090011, 0x02000309 }, /* 160.000 32.000 24.000 */
1738 + { 163200000, 0x0c02, 0x04020009, 0x11090009, 0x02000603 }, /* 163.200 32.640 24.727 */
1739 + { 168000000, 0x0205, 0x04020005, 0x11030021, 0x02000403 }, /* 168.000 32.000 24.889 */
1740 + { 176000000, 0x0602, 0x04020003, 0x11050005, 0x02000602 }, /* 176.000 33.000 24.000 */
1741 + };
1742 + typedef struct {
1743 + uint32 mipsclock;
1744 + uint16 n;
1745 + uint32 m2; /* that is the clockcontrol_m2 */
1746 + } type3_table_t;
1747 + static type3_table_t type3_table[] = { /* for 5350, mips clock is always double sb clock */
1748 + { 150000000, 0x311, 0x4020005 },
1749 + { 200000000, 0x311, 0x4020003 },
1750 + };
1751 + typedef struct {
1752 + uint32 mipsclock;
1753 + uint32 sbclock;
1754 + uint16 n;
1755 + uint32 sb;
1756 + uint32 pci33;
1757 + uint32 m2;
1758 + uint32 m3;
1759 + uint32 ratio_cfg;
1760 + uint32 ratio_parm;
1761 + } n4m_table_t;
1762 +
1763 + static n4m_table_t BCMINITDATA(type2_table)[] = {
1764 + { 180000000, 80000000, 0x0403, 0x01010000, 0x01020300, 0x01020600, 0x05000100, 8, 0x012a00a9 },
1765 + { 180000000, 90000000, 0x0403, 0x01000100, 0x01020300, 0x01000100, 0x05000100, 11, 0x0aaa0555 },
1766 + { 200000000, 100000000, 0x0303, 0x02010000, 0x02040001, 0x02010000, 0x06000001, 11, 0x0aaa0555 },
1767 + { 211200000, 105600000, 0x0902, 0x01000200, 0x01030400, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
1768 + { 220800000, 110400000, 0x1500, 0x01000200, 0x01030400, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
1769 + { 230400000, 115200000, 0x0604, 0x01000200, 0x01020600, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
1770 + { 234000000, 104000000, 0x0b01, 0x01010000, 0x01010700, 0x01020600, 0x05000100, 8, 0x012a00a9 },
1771 + { 240000000, 120000000, 0x0803, 0x01000200, 0x01020600, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
1772 + { 252000000, 126000000, 0x0504, 0x01000100, 0x01020500, 0x01000100, 0x05000100, 11, 0x0aaa0555 },
1773 + { 264000000, 132000000, 0x0903, 0x01000200, 0x01020700, 0x01000200, 0x05000200, 11, 0x0aaa0555 },
1774 + { 270000000, 120000000, 0x0703, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 8, 0x012a00a9 },
1775 + { 276000000, 122666666, 0x1500, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 8, 0x012a00a9 },
1776 + { 280000000, 140000000, 0x0503, 0x01000000, 0x01010600, 0x01000000, 0x05000000, 11, 0x0aaa0555 },
1777 + { 288000000, 128000000, 0x0604, 0x01010000, 0x01030400, 0x01020600, 0x05000100, 8, 0x012a00a9 },
1778 + { 288000000, 144000000, 0x0404, 0x01000000, 0x01010600, 0x01000000, 0x05000000, 11, 0x0aaa0555 },
1779 + { 300000000, 133333333, 0x0803, 0x01010000, 0x01020600, 0x01020600, 0x05000100, 8, 0x012a00a9 },
1780 + { 300000000, 150000000, 0x0803, 0x01000100, 0x01020600, 0x01000100, 0x05000100, 11, 0x0aaa0555 }
1781 + };
1782 +
1783 + static n4m_table_t BCMINITDATA(type4_table)[] = {
1784 + { 192000000, 96000000, 0x0702, 0x04000011, 0x11030011, 0x04000011, 0x04000003, 11, 0x0aaa0555 },
1785 + { 198000000, 99000000, 0x0603, 0x11020005, 0x11030011, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
1786 + { 200000000, 100000000, 0x0009, 0x04020011, 0x11030011, 0x04020011, 0x04020003, 11, 0x0aaa0555 },
1787 + { 204000000, 102000000, 0x0c02, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
1788 + { 208000000, 104000000, 0x0802, 0x11030002, 0x11090005, 0x11030002, 0x04000003, 11, 0x0aaa0555 },
1789 + { 210000000, 105000000, 0x0209, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
1790 + { 216000000, 108000000, 0x0111, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
1791 + { 224000000, 112000000, 0x0205, 0x11030002, 0x02002103, 0x11030002, 0x04000003, 11, 0x0aaa0555 },
1792 + { 228000000, 101333333, 0x0e02, 0x11030003, 0x11210005, 0x01030305, 0x04000005, 8, 0x012a00a9 },
1793 + { 228000000, 114000000, 0x0e02, 0x11020005, 0x11210005, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
1794 + { 240000000, 102857143, 0x0109, 0x04000021, 0x01050203, 0x11030021, 0x04000003, 13, 0x254a14a9 },
1795 + { 240000000, 120000000, 0x0109, 0x11030002, 0x01050203, 0x11030002, 0x04000003, 11, 0x0aaa0555 },
1796 + { 252000000, 100800000, 0x0203, 0x04000009, 0x11050005, 0x02000209, 0x04000002, 9, 0x02520129 },
1797 + { 252000000, 126000000, 0x0203, 0x04000005, 0x11050005, 0x04000005, 0x04000002, 11, 0x0aaa0555 },
1798 + { 264000000, 132000000, 0x0602, 0x04000005, 0x11050005, 0x04000005, 0x04000002, 11, 0x0aaa0555 },
1799 + { 272000000, 116571428, 0x0c02, 0x04000021, 0x02000909, 0x02000221, 0x04000003, 13, 0x254a14a9 },
1800 + { 280000000, 120000000, 0x0209, 0x04000021, 0x01030303, 0x02000221, 0x04000003, 13, 0x254a14a9 },
1801 + { 288000000, 123428571, 0x0111, 0x04000021, 0x01030303, 0x02000221, 0x04000003, 13, 0x254a14a9 },
1802 + { 300000000, 120000000, 0x0009, 0x04000009, 0x01030203, 0x02000902, 0x04000002, 9, 0x02520129 },
1803 + { 300000000, 150000000, 0x0009, 0x04000005, 0x01030203, 0x04000005, 0x04000002, 11, 0x0aaa0555 }
1804 + };
1805 +
1806 + static n4m_table_t BCMINITDATA(type7_table)[] = {
1807 + { 183333333, 91666666, 0x0605, 0x04000011, 0x11030011, 0x04000011, 0x04000003, 11, 0x0aaa0555 },
1808 + { 187500000, 93750000, 0x0a03, 0x04000011, 0x11030011, 0x04000011, 0x04000003, 11, 0x0aaa0555 },
1809 + { 196875000, 98437500, 0x1003, 0x11020005, 0x11050011, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
1810 + { 200000000, 100000000, 0x0311, 0x04000011, 0x11030011, 0x04000009, 0x04000003, 11, 0x0aaa0555 },
1811 + { 200000000, 100000000, 0x0311, 0x04020011, 0x11030011, 0x04020011, 0x04020003, 11, 0x0aaa0555 },
1812 + { 206250000, 103125000, 0x1103, 0x11020005, 0x11050011, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
1813 + { 212500000, 106250000, 0x0c05, 0x11020005, 0x01030303, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
1814 + { 215625000, 107812500, 0x1203, 0x11090009, 0x11050005, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
1815 + { 216666666, 108333333, 0x0805, 0x11020003, 0x11030011, 0x11020003, 0x04000003, 11, 0x0aaa0555 },
1816 + { 225000000, 112500000, 0x0d03, 0x11020003, 0x11030011, 0x11020003, 0x04000003, 11, 0x0aaa0555 },
1817 + { 233333333, 116666666, 0x0905, 0x11020003, 0x11030011, 0x11020003, 0x04000003, 11, 0x0aaa0555 },
1818 + { 237500000, 118750000, 0x0e05, 0x11020005, 0x11210005, 0x11020005, 0x04000005, 11, 0x0aaa0555 },
1819 + { 240000000, 120000000, 0x0b11, 0x11020009, 0x11210009, 0x11020009, 0x04000009, 11, 0x0aaa0555 },
1820 + { 250000000, 125000000, 0x0f03, 0x11020003, 0x11210003, 0x11020003, 0x04000003, 11, 0x0aaa0555 }
1821 + };
1822 +
1823 + ulong start, end, dst;
1824 + bool ret = FALSE;
1825 +
1826 + /* get index of the current core */
1827 + idx = sb_coreidx(sbh);
1828 + clockcontrol_m2 = NULL;
1829 +
1830 + /* switch to extif or chipc core */
1831 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
1832 + pll_type = PLL_TYPE1;
1833 + clockcontrol_n = &eir->clockcontrol_n;
1834 + clockcontrol_sb = &eir->clockcontrol_sb;
1835 + clockcontrol_pci = &eir->clockcontrol_pci;
1836 + clockcontrol_m2 = &cc->clockcontrol_m2;
1837 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
1838 + pll_type = R_REG(&cc->capabilities) & CAP_PLL_MASK;
1839 + if (pll_type == PLL_TYPE6) {
1840 + clockcontrol_n = NULL;
1841 + clockcontrol_sb = NULL;
1842 + clockcontrol_pci = NULL;
1843 + } else {
1844 + clockcontrol_n = &cc->clockcontrol_n;
1845 + clockcontrol_sb = &cc->clockcontrol_sb;
1846 + clockcontrol_pci = &cc->clockcontrol_pci;
1847 + clockcontrol_m2 = &cc->clockcontrol_m2;
1848 + }
1849 + } else
1850 + goto done;
1851 +
1852 + if (pll_type == PLL_TYPE6) {
1853 + /* Silence compilers */
1854 + orig_n = orig_sb = orig_pci = 0;
1855 + } else {
1856 + /* Store the current clock register values */
1857 + orig_n = R_REG(clockcontrol_n);
1858 + orig_sb = R_REG(clockcontrol_sb);
1859 + orig_pci = R_REG(clockcontrol_pci);
1860 + }
1861 +
1862 + if (pll_type == PLL_TYPE1) {
1863 + /* Keep the current PCI clock if not specified */
1864 + if (pciclock == 0) {
1865 + pciclock = sb_clock_rate(pll_type, R_REG(clockcontrol_n), R_REG(clockcontrol_pci));
1866 + pciclock = (pciclock <= 25000000) ? 25000000 : 33000000;
1867 + }
1868 +
1869 + /* Search for the closest MIPS clock less than or equal to a preferred value */
1870 + for (i = 0; i < ARRAYSIZE(BCMINIT(type1_table)); i++) {
1871 + ASSERT(BCMINIT(type1_table)[i].mipsclock ==
1872 + sb_clock_rate(pll_type, BCMINIT(type1_table)[i].n, BCMINIT(type1_table)[i].sb));
1873 + if (BCMINIT(type1_table)[i].mipsclock > mipsclock)
1874 + break;
1875 + }
1876 + if (i == 0) {
1877 + ret = FALSE;
1878 + goto done;
1879 + } else {
1880 + ret = TRUE;
1881 + i--;
1882 + }
1883 + ASSERT(BCMINIT(type1_table)[i].mipsclock <= mipsclock);
1884 +
1885 + /* No PLL change */
1886 + if ((orig_n == BCMINIT(type1_table)[i].n) &&
1887 + (orig_sb == BCMINIT(type1_table)[i].sb) &&
1888 + (orig_pci == BCMINIT(type1_table)[i].pci33))
1889 + goto done;
1890 +
1891 + /* Set the PLL controls */
1892 + W_REG(clockcontrol_n, BCMINIT(type1_table)[i].n);
1893 + W_REG(clockcontrol_sb, BCMINIT(type1_table)[i].sb);
1894 + if (pciclock == 25000000)
1895 + W_REG(clockcontrol_pci, BCMINIT(type1_table)[i].pci25);
1896 + else
1897 + W_REG(clockcontrol_pci, BCMINIT(type1_table)[i].pci33);
1898 +
1899 + /* Reset */
1900 + sb_watchdog(sbh, 1);
1901 +
1902 + while (1);
1903 + } else if ((pll_type == PLL_TYPE3) &&
1904 + (BCMINIT(sb_chip)(sbh) != BCM5365_DEVICE_ID)) {
1905 + /* 5350 */
1906 + /* Search for the closest MIPS clock less than or equal to a preferred value */
1907 +
1908 + for (i = 0; i < ARRAYSIZE(type3_table); i++) {
1909 + if (type3_table[i].mipsclock > mipsclock)
1910 + break;
1911 + }
1912 + if (i == 0) {
1913 + ret = FALSE;
1914 + goto done;
1915 + } else {
1916 + ret = TRUE;
1917 + i--;
1918 + }
1919 + ASSERT(type3_table[i].mipsclock <= mipsclock);
1920 +
1921 + /* No PLL change */
1922 + orig_m2 = R_REG(&cc->clockcontrol_m2);
1923 + if ((orig_n == type3_table[i].n) &&
1924 + (orig_m2 == type3_table[i].m2)) {
1925 + goto done;
1926 + }
1927 +
1928 + /* Set the PLL controls */
1929 + W_REG(clockcontrol_n, type3_table[i].n);
1930 + W_REG(clockcontrol_m2, type3_table[i].m2);
1931 +
1932 + /* Reset */
1933 + sb_watchdog(sbh, 1);
1934 + while (1);
1935 + } else if ((pll_type == PLL_TYPE2) ||
1936 + (pll_type == PLL_TYPE4) ||
1937 + (pll_type == PLL_TYPE6) ||
1938 + (pll_type == PLL_TYPE7)) {
1939 + n4m_table_t *table = NULL, *te;
1940 + uint tabsz = 0;
1941 +
1942 + ASSERT(cc);
1943 +
1944 + orig_mips = R_REG(&cc->clockcontrol_mips);
1945 +
1946 + if (pll_type == PLL_TYPE6) {
1947 + uint32 new_mips = 0;
1948 +
1949 + ret = TRUE;
1950 + if (mipsclock <= SB2MIPS_T6(CC_T6_M1))
1951 + new_mips = CC_T6_MMASK;
1952 +
1953 + if (orig_mips == new_mips)
1954 + goto done;
1955 +
1956 + W_REG(&cc->clockcontrol_mips, new_mips);
1957 + goto end_fill;
1958 + }
1959 +
1960 + if (pll_type == PLL_TYPE2) {
1961 + table = BCMINIT(type2_table);
1962 + tabsz = ARRAYSIZE(BCMINIT(type2_table));
1963 + } else if (pll_type == PLL_TYPE4) {
1964 + table = BCMINIT(type4_table);
1965 + tabsz = ARRAYSIZE(BCMINIT(type4_table));
1966 + } else if (pll_type == PLL_TYPE7) {
1967 + table = BCMINIT(type7_table);
1968 + tabsz = ARRAYSIZE(BCMINIT(type7_table));
1969 + } else
1970 + ASSERT("No table for plltype" == NULL);
1971 +
1972 + /* Store the current clock register values */
1973 + orig_m2 = R_REG(&cc->clockcontrol_m2);
1974 + orig_ratio_parm = 0;
1975 + orig_ratio_cfg = 0;
1976 +
1977 + /* Look up current ratio */
1978 + for (i = 0; i < tabsz; i++) {
1979 + if ((orig_n == table[i].n) &&
1980 + (orig_sb == table[i].sb) &&
1981 + (orig_pci == table[i].pci33) &&
1982 + (orig_m2 == table[i].m2) &&
1983 + (orig_mips == table[i].m3)) {
1984 + orig_ratio_parm = table[i].ratio_parm;
1985 + orig_ratio_cfg = table[i].ratio_cfg;
1986 + break;
1987 + }
1988 + }
1989 +
1990 + /* Search for the closest MIPS clock greater or equal to a preferred value */
1991 + for (i = 0; i < tabsz; i++) {
1992 + ASSERT(table[i].mipsclock ==
1993 + sb_clock_rate(pll_type, table[i].n, table[i].m3));
1994 + if ((mipsclock <= table[i].mipsclock) &&
1995 + ((sbclock == 0) || (sbclock <= table[i].sbclock)))
1996 + break;
1997 + }
1998 + if (i == tabsz) {
1999 + ret = FALSE;
2000 + goto done;
2001 + } else {
2002 + te = &table[i];
2003 + ret = TRUE;
2004 + }
2005 +
2006 + /* No PLL change */
2007 + if ((orig_n == te->n) &&
2008 + (orig_sb == te->sb) &&
2009 + (orig_pci == te->pci33) &&
2010 + (orig_m2 == te->m2) &&
2011 + (orig_mips == te->m3))
2012 + goto done;
2013 +
2014 + /* Set the PLL controls */
2015 + W_REG(clockcontrol_n, te->n);
2016 + W_REG(clockcontrol_sb, te->sb);
2017 + W_REG(clockcontrol_pci, te->pci33);
2018 + W_REG(&cc->clockcontrol_m2, te->m2);
2019 + W_REG(&cc->clockcontrol_mips, te->m3);
2020 +
2021 + /* Set the chipcontrol bit to change mipsref to the backplane divider if needed */
2022 + if ((pll_type == PLL_TYPE7) &&
2023 + (te->sb != te->m2) &&
2024 + (sb_clock_rate(pll_type, te->n, te->m2) == 120000000))
2025 + W_REG(&cc->chipcontrol, R_REG(&cc->chipcontrol) | 0x100);
2026 +
2027 + /* No ratio change */
2028 + if (orig_ratio_parm == te->ratio_parm)
2029 + goto end_fill;
2030 +
2031 + icache_probe(MFC0(C0_CONFIG, 1), &ic_size, &ic_lsize);
2032 +
2033 + /* Preload the code into the cache */
2034 + start = ((ulong) &&start_fill) & ~(ic_lsize - 1);
2035 + end = ((ulong) &&end_fill + (ic_lsize - 1)) & ~(ic_lsize - 1);
2036 + while (start < end) {
2037 + cache_op(start, Fill_I);
2038 + start += ic_lsize;
2039 + }
2040 +
2041 + /* Copy the handler */
2042 + start = (ulong) &BCMINIT(handler);
2043 + end = (ulong) &BCMINIT(afterhandler);
2044 + dst = KSEG1ADDR(0x180);
2045 + for (i = 0; i < (end - start); i += 4)
2046 + *((ulong *)(dst + i)) = *((ulong *)(start + i));
2047 +
2048 + /* Preload handler into the cache one line at a time */
2049 + for (i = 0; i < (end - start); i += 4)
2050 + cache_op(dst + i, Fill_I);
2051 +
2052 + /* Clear BEV bit */
2053 + MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) & ~ST0_BEV);
2054 +
2055 + /* Enable interrupts */
2056 + MTC0(C0_STATUS, 0, MFC0(C0_STATUS, 0) | (ALLINTS | ST0_IE));
2057 +
2058 + /* Enable MIPS timer interrupt */
2059 + if (!(mipsr = sb_setcore(sbh, SB_MIPS, 0)) &&
2060 + !(mipsr = sb_setcore(sbh, SB_MIPS33, 0)))
2061 + ASSERT(mipsr);
2062 + W_REG(&mipsr->intmask, 1);
2063 +
2064 + start_fill:
2065 + /* step 1, set clock ratios */
2066 + MTC0(C0_BROADCOM, 3, te->ratio_parm);
2067 + MTC0(C0_BROADCOM, 1, te->ratio_cfg);
2068 +
2069 + /* step 2: program timer intr */
2070 + W_REG(&mipsr->timer, 100);
2071 + (void) R_REG(&mipsr->timer);
2072 +
2073 + /* step 3, switch to async */
2074 + sync_mode = MFC0(C0_BROADCOM, 4);
2075 + MTC0(C0_BROADCOM, 4, 1 << 22);
2076 +
2077 + /* step 4, set cfg active */
2078 + MTC0(C0_BROADCOM, 2, 0x9);
2079 +
2080 +
2081 + /* steps 5 & 6 */
2082 + __asm__ __volatile__ (
2083 + ".set\tmips3\n\t"
2084 + "wait\n\t"
2085 + ".set\tmips0"
2086 + );
2087 +
2088 + /* step 7, clear cfg_active */
2089 + MTC0(C0_BROADCOM, 2, 0);
2090 +
2091 + /* Additional Step: set back to orig sync mode */
2092 + MTC0(C0_BROADCOM, 4, sync_mode);
2093 +
2094 + /* step 8, fake soft reset */
2095 + MTC0(C0_BROADCOM, 5, MFC0(C0_BROADCOM, 5) | 4);
2096 +
2097 + end_fill:
2098 + /* step 9 set watchdog timer */
2099 + sb_watchdog(sbh, 20);
2100 + (void) R_REG(&cc->chipid);
2101 +
2102 + /* step 11 */
2103 + __asm__ __volatile__ (
2104 + ".set\tmips3\n\t"
2105 + "sync\n\t"
2106 + "wait\n\t"
2107 + ".set\tmips0"
2108 + );
2109 + while (1);
2110 + }
2111 +
2112 +done:
2113 + /* switch back to previous core */
2114 + sb_setcoreidx(sbh, idx);
2115 +
2116 + return ret;
2117 +}
2118 +
2119 +/*
2120 + * This also must be run from the cache on 47xx
2121 + * so there are no mips core BIU ops in progress
2122 + * when the PFC is enabled.
2123 + */
2124 +
2125 +static void
2126 +BCMINITFN(_enable_pfc)(uint32 mode)
2127 +{
2128 + /* write range */
2129 + *(volatile uint32 *)PFC_CR1 = 0xffff0000;
2130 +
2131 + /* enable */
2132 + *(volatile uint32 *)PFC_CR0 = mode;
2133 +}
2134 +
2135 +void
2136 +BCMINITFN(enable_pfc)(uint32 mode)
2137 +{
2138 + ulong start, end;
2139 + int i;
2140 +
2141 + /* If auto then choose the correct mode for this
2142 + platform, currently we only ever select one mode */
2143 + if (mode == PFC_AUTO)
2144 + mode = PFC_INST;
2145 +
2146 + /* enable prefetch cache if available */
2147 + if (MFC0(C0_BROADCOM, 0) & BRCM_PFC_AVAIL) {
2148 + start = (ulong) &BCMINIT(_enable_pfc);
2149 + end = (ulong) &BCMINIT(enable_pfc);
2150 +
2151 + /* Preload handler into the cache one line at a time */
2152 + for (i = 0; i < (end - start); i += 4)
2153 + cache_op(start + i, Fill_I);
2154 +
2155 + BCMINIT(_enable_pfc)(mode);
2156 + }
2157 +}
2158 +
2159 +/* returns the ncdl value to be programmed into sdram_ncdl for calibration */
2160 +uint32
2161 +BCMINITFN(sb_memc_get_ncdl)(sb_t *sbh)
2162 +{
2163 + sbmemcregs_t *memc;
2164 + uint32 ret = 0;
2165 + uint32 config, rd, wr, misc, dqsg, cd, sm, sd;
2166 + uint idx, rev;
2167 +
2168 + idx = sb_coreidx(sbh);
2169 +
2170 + memc = (sbmemcregs_t *)sb_setcore(sbh, SB_MEMC, 0);
2171 + if (memc == 0)
2172 + goto out;
2173 +
2174 + rev = sb_corerev(sbh);
2175 +
2176 + config = R_REG(&memc->config);
2177 + wr = R_REG(&memc->wrncdlcor);
2178 + rd = R_REG(&memc->rdncdlcor);
2179 + misc = R_REG(&memc->miscdlyctl);
2180 + dqsg = R_REG(&memc->dqsgatencdl);
2181 +
2182 + rd &= MEMC_RDNCDLCOR_RD_MASK;
2183 + wr &= MEMC_WRNCDLCOR_WR_MASK;
2184 + dqsg &= MEMC_DQSGATENCDL_G_MASK;
2185 +
2186 + if (config & MEMC_CONFIG_DDR) {
2187 + ret = (wr << 16) | (rd << 8) | dqsg;
2188 + } else {
2189 + if (rev > 0)
2190 + cd = rd;
2191 + else
2192 + cd = (rd == MEMC_CD_THRESHOLD) ? rd : (wr + MEMC_CD_THRESHOLD);
2193 + sm = (misc & MEMC_MISC_SM_MASK) >> MEMC_MISC_SM_SHIFT;
2194 + sd = (misc & MEMC_MISC_SD_MASK) >> MEMC_MISC_SD_SHIFT;
2195 + ret = (sm << 16) | (sd << 8) | cd;
2196 + }
2197 +
2198 +out:
2199 + /* switch back to previous core */
2200 + sb_setcoreidx(sbh, idx);
2201 +
2202 + return ret;
2203 +}
2204 +
2205 diff -urN linux.old/arch/mips/bcm947xx/broadcom/sbpci.c linux.dev/arch/mips/bcm947xx/broadcom/sbpci.c
2206 --- linux.old/arch/mips/bcm947xx/broadcom/sbpci.c 1970-01-01 01:00:00.000000000 +0100
2207 +++ linux.dev/arch/mips/bcm947xx/broadcom/sbpci.c 2005-12-15 20:09:46.562233250 +0100
2208 @@ -0,0 +1,529 @@
2209 +/*
2210 + * Low-Level PCI and SB support for BCM47xx
2211 + *
2212 + * Copyright 2005, Broadcom Corporation
2213 + * All Rights Reserved.
2214 + *
2215 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2216 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2217 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2218 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2219 + *
2220 + * $Id$
2221 + */
2222 +
2223 +#include <typedefs.h>
2224 +#include <pcicfg.h>
2225 +#include <bcmdevs.h>
2226 +#include <sbconfig.h>
2227 +#include <osl.h>
2228 +#include <sbutils.h>
2229 +#include <sbpci.h>
2230 +#include <bcmendian.h>
2231 +#include <bcmutils.h>
2232 +#include <bcmnvram.h>
2233 +#include <hndmips.h>
2234 +
2235 +/* Can free sbpci_init() memory after boot */
2236 +#ifndef linux
2237 +#define __init
2238 +#endif
2239 +
2240 +/* Emulated configuration space */
2241 +static pci_config_regs sb_config_regs[SB_MAXCORES];
2242 +
2243 +/* Banned cores */
2244 +static uint16 pci_ban[32] = { 0 };
2245 +static uint pci_banned = 0;
2246 +
2247 +/* CardBus mode */
2248 +static bool cardbus = FALSE;
2249 +
2250 +/* Disable PCI host core */
2251 +static bool pci_disabled = FALSE;
2252 +
2253 +/*
2254 + * Functions for accessing external PCI configuration space
2255 + */
2256 +
2257 +/* Assume one-hot slot wiring */
2258 +#define PCI_SLOT_MAX 16
2259 +
2260 +static uint32
2261 +config_cmd(sb_t *sbh, uint bus, uint dev, uint func, uint off)
2262 +{
2263 + uint coreidx;
2264 + sbpciregs_t *regs;
2265 + uint32 addr = 0;
2266 +
2267 + /* CardBusMode supports only one device */
2268 + if (cardbus && dev > 1)
2269 + return 0;
2270 +
2271 + coreidx = sb_coreidx(sbh);
2272 + regs = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0);
2273 +
2274 + /* Type 0 transaction */
2275 + if (bus == 1) {
2276 + /* Skip unwired slots */
2277 + if (dev < PCI_SLOT_MAX) {
2278 + /* Slide the PCI window to the appropriate slot */
2279 + W_REG(&regs->sbtopci1, SBTOPCI_CFG0 | ((1 << (dev + 16)) & SBTOPCI1_MASK));
2280 + addr = SB_PCI_CFG | ((1 << (dev + 16)) & ~SBTOPCI1_MASK) |
2281 + (func << 8) | (off & ~3);
2282 + }
2283 + }
2284 +
2285 + /* Type 1 transaction */
2286 + else {
2287 + W_REG(&regs->sbtopci1, SBTOPCI_CFG1);
2288 + addr = SB_PCI_CFG | (bus << 16) | (dev << 11) | (func << 8) | (off & ~3);
2289 + }
2290 +
2291 + sb_setcoreidx(sbh, coreidx);
2292 +
2293 + return addr;
2294 +}
2295 +
2296 +static int
2297 +extpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
2298 +{
2299 + uint32 addr, *reg = NULL, val;
2300 + int ret = 0;
2301 +
2302 + if (pci_disabled ||
2303 + !(addr = config_cmd(sbh, bus, dev, func, off)) ||
2304 + !(reg = (uint32 *) REG_MAP(addr, len)) ||
2305 + BUSPROBE(val, reg))
2306 + val = 0xffffffff;
2307 +
2308 + val >>= 8 * (off & 3);
2309 + if (len == 4)
2310 + *((uint32 *) buf) = val;
2311 + else if (len == 2)
2312 + *((uint16 *) buf) = (uint16) val;
2313 + else if (len == 1)
2314 + *((uint8 *) buf) = (uint8) val;
2315 + else
2316 + ret = -1;
2317 +
2318 + if (reg)
2319 + REG_UNMAP(reg);
2320 +
2321 + return ret;
2322 +}
2323 +
2324 +static int
2325 +extpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
2326 +{
2327 + uint32 addr, *reg = NULL, val;
2328 + int ret = 0;
2329 +
2330 + if (pci_disabled ||
2331 + !(addr = config_cmd(sbh, bus, dev, func, off)) ||
2332 + !(reg = (uint32 *) REG_MAP(addr, len)) ||
2333 + BUSPROBE(val, reg))
2334 + goto done;
2335 +
2336 + if (len == 4)
2337 + val = *((uint32 *) buf);
2338 + else if (len == 2) {
2339 + val &= ~(0xffff << (8 * (off & 3)));
2340 + val |= *((uint16 *) buf) << (8 * (off & 3));
2341 + } else if (len == 1) {
2342 + val &= ~(0xff << (8 * (off & 3)));
2343 + val |= *((uint8 *) buf) << (8 * (off & 3));
2344 + } else
2345 + ret = -1;
2346 +
2347 + W_REG(reg, val);
2348 +
2349 + done:
2350 + if (reg)
2351 + REG_UNMAP(reg);
2352 +
2353 + return ret;
2354 +}
2355 +
2356 +/*
2357 + * Functions for accessing translated SB configuration space
2358 + */
2359 +
2360 +static int
2361 +sb_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
2362 +{
2363 + pci_config_regs *cfg;
2364 +
2365 + if (dev >= SB_MAXCORES || (off + len) > sizeof(pci_config_regs))
2366 + return -1;
2367 + cfg = &sb_config_regs[dev];
2368 +
2369 + ASSERT(ISALIGNED(off, len));
2370 + ASSERT(ISALIGNED((uintptr)buf, len));
2371 +
2372 + if (len == 4)
2373 + *((uint32 *) buf) = ltoh32(*((uint32 *)((ulong) cfg + off)));
2374 + else if (len == 2)
2375 + *((uint16 *) buf) = ltoh16(*((uint16 *)((ulong) cfg + off)));
2376 + else if (len == 1)
2377 + *((uint8 *) buf) = *((uint8 *)((ulong) cfg + off));
2378 + else
2379 + return -1;
2380 +
2381 + return 0;
2382 +}
2383 +
2384 +static int
2385 +sb_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
2386 +{
2387 + uint coreidx, n;
2388 + void *regs;
2389 + sbconfig_t *sb;
2390 + pci_config_regs *cfg;
2391 +
2392 + if (dev >= SB_MAXCORES || (off + len) > sizeof(pci_config_regs))
2393 + return -1;
2394 + cfg = &sb_config_regs[dev];
2395 +
2396 + ASSERT(ISALIGNED(off, len));
2397 + ASSERT(ISALIGNED((uintptr)buf, len));
2398 +
2399 + /* Emulate BAR sizing */
2400 + if (off >= OFFSETOF(pci_config_regs, base[0]) && off <= OFFSETOF(pci_config_regs, base[3]) &&
2401 + len == 4 && *((uint32 *) buf) == ~0) {
2402 + coreidx = sb_coreidx(sbh);
2403 + if ((regs = sb_setcoreidx(sbh, dev))) {
2404 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
2405 + /* Highest numbered address match register */
2406 + n = (R_REG(&sb->sbidlow) & SBIDL_AR_MASK) >> SBIDL_AR_SHIFT;
2407 + if (off == OFFSETOF(pci_config_regs, base[0]))
2408 + cfg->base[0] = ~(sb_size(R_REG(&sb->sbadmatch0)) - 1);
2409 + else if (off == OFFSETOF(pci_config_regs, base[1]) && n >= 1)
2410 + cfg->base[1] = ~(sb_size(R_REG(&sb->sbadmatch1)) - 1);
2411 + else if (off == OFFSETOF(pci_config_regs, base[2]) && n >= 2)
2412 + cfg->base[2] = ~(sb_size(R_REG(&sb->sbadmatch2)) - 1);
2413 + else if (off == OFFSETOF(pci_config_regs, base[3]) && n >= 3)
2414 + cfg->base[3] = ~(sb_size(R_REG(&sb->sbadmatch3)) - 1);
2415 + }
2416 + sb_setcoreidx(sbh, coreidx);
2417 + return 0;
2418 + }
2419 +
2420 + if (len == 4)
2421 + *((uint32 *)((ulong) cfg + off)) = htol32(*((uint32 *) buf));
2422 + else if (len == 2)
2423 + *((uint16 *)((ulong) cfg + off)) = htol16(*((uint16 *) buf));
2424 + else if (len == 1)
2425 + *((uint8 *)((ulong) cfg + off)) = *((uint8 *) buf);
2426 + else
2427 + return -1;
2428 +
2429 + return 0;
2430 +}
2431 +
2432 +int
2433 +sbpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
2434 +{
2435 + if (bus == 0)
2436 + return sb_read_config(sbh, bus, dev, func, off, buf, len);
2437 + else
2438 + return extpci_read_config(sbh, bus, dev, func, off, buf, len);
2439 +}
2440 +
2441 +int
2442 +sbpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len)
2443 +{
2444 + if (bus == 0)
2445 + return sb_write_config(sbh, bus, dev, func, off, buf, len);
2446 + else
2447 + return extpci_write_config(sbh, bus, dev, func, off, buf, len);
2448 +}
2449 +
2450 +void
2451 +sbpci_ban(uint16 core)
2452 +{
2453 + if (pci_banned < ARRAYSIZE(pci_ban))
2454 + pci_ban[pci_banned++] = core;
2455 +}
2456 +
2457 +static int
2458 +sbpci_init_pci(sb_t *sbh)
2459 +{
2460 + uint chip, chiprev, chippkg, host;
2461 + uint32 boardflags;
2462 + sbpciregs_t *pci;
2463 + sbconfig_t *sb;
2464 + uint32 val;
2465 +
2466 + chip = sb_chip(sbh);
2467 + chiprev = sb_chiprev(sbh);
2468 + chippkg = sb_chippkg(sbh);
2469 +
2470 + if (!(pci = (sbpciregs_t *) sb_setcore(sbh, SB_PCI, 0))) {
2471 + printf("PCI: no core\n");
2472 + pci_disabled = TRUE;
2473 + return -1;
2474 + }
2475 + sb_core_reset(sbh, 0);
2476 +
2477 + boardflags = (uint32) getintvar(NULL, "boardflags");
2478 +
2479 + if ((chip == BCM4310_DEVICE_ID) && (chiprev == 0))
2480 + pci_disabled = TRUE;
2481 +
2482 + /*
2483 + * The 200-pin BCM4712 package does not bond out PCI. Even when
2484 + * PCI is bonded out, some boards may leave the pins
2485 + * floating.
2486 + */
2487 + if (((chip == BCM4712_DEVICE_ID) &&
2488 + ((chippkg == BCM4712SMALL_PKG_ID) ||
2489 + (chippkg == BCM4712MID_PKG_ID))) ||
2490 + (boardflags & BFL_NOPCI))
2491 + pci_disabled = TRUE;
2492 +
2493 + /*
2494 + * If the PCI core should not be touched (disabled, not bonded
2495 + * out, or pins floating), do not even attempt to access core
2496 + * registers. Otherwise, try to determine if it is in host
2497 + * mode.
2498 + */
2499 + if (pci_disabled)
2500 + host = 0;
2501 + else
2502 + host = !BUSPROBE(val, &pci->control);
2503 +
2504 + if (!host) {
2505 + /* Disable PCI interrupts in client mode */
2506 + sb = (sbconfig_t *)((ulong) pci + SBCONFIGOFF);
2507 + W_REG(&sb->sbintvec, 0);
2508 +
2509 + /* Disable the PCI bridge in client mode */
2510 + sbpci_ban(SB_PCI);
2511 + printf("PCI: Disabled\n");
2512 + } else {
2513 + /* Reset the external PCI bus and enable the clock */
2514 + W_REG(&pci->control, 0x5); /* enable the tristate drivers */
2515 + W_REG(&pci->control, 0xd); /* enable the PCI clock */
2516 + OSL_DELAY(150); /* delay > 100 us */
2517 + W_REG(&pci->control, 0xf); /* deassert PCI reset */
2518 + W_REG(&pci->arbcontrol, PCI_INT_ARB); /* use internal arbiter */
2519 + OSL_DELAY(1); /* delay 1 us */
2520 +
2521 + /* Enable CardBusMode */
2522 + cardbus = nvram_match("cardbus", "1");
2523 + if (cardbus) {
2524 + printf("PCI: Enabling CardBus\n");
2525 + /* GPIO 1 resets the CardBus device on bcm94710ap */
2526 + sb_gpioout(sbh, 1, 1, GPIO_DRV_PRIORITY);
2527 + sb_gpioouten(sbh, 1, 1, GPIO_DRV_PRIORITY);
2528 + W_REG(&pci->sprom[0], R_REG(&pci->sprom[0]) | 0x400);
2529 + }
2530 +
2531 + /* 64 MB I/O access window */
2532 + W_REG(&pci->sbtopci0, SBTOPCI_IO);
2533 + /* 64 MB configuration access window */
2534 + W_REG(&pci->sbtopci1, SBTOPCI_CFG0);
2535 + /* 1 GB memory access window */
2536 + W_REG(&pci->sbtopci2, SBTOPCI_MEM | SB_PCI_DMA);
2537 +
2538 + /* Enable PCI bridge BAR0 prefetch and burst */
2539 + val = 6;
2540 + sbpci_write_config(sbh, 1, 0, 0, PCI_CFG_CMD, &val, sizeof(val));
2541 +
2542 + /* Enable PCI interrupts */
2543 + W_REG(&pci->intmask, PCI_INTA);
2544 + }
2545 +
2546 + return 0;
2547 +}
2548 +
2549 +static int
2550 +sbpci_init_cores(sb_t *sbh)
2551 +{
2552 + uint chip, chiprev, chippkg, coreidx, i;
2553 + sbconfig_t *sb;
2554 + pci_config_regs *cfg;
2555 + void *regs;
2556 + char varname[8];
2557 + uint wlidx = 0;
2558 + uint16 vendor, core;
2559 + uint8 class, subclass, progif;
2560 + uint32 val;
2561 + uint32 sbips_int_mask[] = { 0, SBIPS_INT1_MASK, SBIPS_INT2_MASK, SBIPS_INT3_MASK, SBIPS_INT4_MASK };
2562 + uint32 sbips_int_shift[] = { 0, 0, SBIPS_INT2_SHIFT, SBIPS_INT3_SHIFT, SBIPS_INT4_SHIFT };
2563 +
2564 + chip = sb_chip(sbh);
2565 + chiprev = sb_chiprev(sbh);
2566 + chippkg = sb_chippkg(sbh);
2567 + coreidx = sb_coreidx(sbh);
2568 +
2569 + /* Scan the SB bus */
2570 + bzero(sb_config_regs, sizeof(sb_config_regs));
2571 + for (cfg = sb_config_regs; cfg < &sb_config_regs[SB_MAXCORES]; cfg++) {
2572 + cfg->vendor = 0xffff;
2573 + if (!(regs = sb_setcoreidx(sbh, cfg - sb_config_regs)))
2574 + continue;
2575 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
2576 +
2577 + /* Read ID register and parse vendor and core */
2578 + val = R_REG(&sb->sbidhigh);
2579 + vendor = (val & SBIDH_VC_MASK) >> SBIDH_VC_SHIFT;
2580 + core = (val & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT;
2581 + progif = 0;
2582 +
2583 + /* Check if this core is banned */
2584 + for (i = 0; i < pci_banned; i++)
2585 + if (core == pci_ban[i])
2586 + break;
2587 + if (i < pci_banned)
2588 + continue;
2589 +
2590 + /* Known vendor translations */
2591 + switch (vendor) {
2592 + case SB_VEND_BCM:
2593 + vendor = VENDOR_BROADCOM;
2594 + break;
2595 + }
2596 +
2597 + /* Determine class based on known core codes */
2598 + switch (core) {
2599 + case SB_ILINE20:
2600 + class = PCI_CLASS_NET;
2601 + subclass = PCI_NET_ETHER;
2602 + core = BCM47XX_ILINE_ID;
2603 + break;
2604 + case SB_ILINE100:
2605 + class = PCI_CLASS_NET;
2606 + subclass = PCI_NET_ETHER;
2607 + core = BCM4610_ILINE_ID;
2608 + break;
2609 + case SB_ENET:
2610 + class = PCI_CLASS_NET;
2611 + subclass = PCI_NET_ETHER;
2612 + core = BCM47XX_ENET_ID;
2613 + break;
2614 + case SB_SDRAM:
2615 + case SB_MEMC:
2616 + class = PCI_CLASS_MEMORY;
2617 + subclass = PCI_MEMORY_RAM;
2618 + break;
2619 + case SB_PCI:
2620 + class = PCI_CLASS_BRIDGE;
2621 + subclass = PCI_BRIDGE_PCI;
2622 + break;
2623 + case SB_MIPS:
2624 + case SB_MIPS33:
2625 + class = PCI_CLASS_CPU;
2626 + subclass = PCI_CPU_MIPS;
2627 + break;
2628 + case SB_CODEC:
2629 + class = PCI_CLASS_COMM;
2630 + subclass = PCI_COMM_MODEM;
2631 + core = BCM47XX_V90_ID;
2632 + break;
2633 + case SB_USB:
2634 + class = PCI_CLASS_SERIAL;
2635 + subclass = PCI_SERIAL_USB;
2636 + progif = 0x10; /* OHCI */
2637 + core = BCM47XX_USB_ID;
2638 + break;
2639 + case SB_USB11H:
2640 + class = PCI_CLASS_SERIAL;
2641 + subclass = PCI_SERIAL_USB;
2642 + progif = 0x10; /* OHCI */
2643 + core = BCM47XX_USBH_ID;
2644 + break;
2645 + case SB_USB11D:
2646 + class = PCI_CLASS_SERIAL;
2647 + subclass = PCI_SERIAL_USB;
2648 + core = BCM47XX_USBD_ID;
2649 + break;
2650 + case SB_IPSEC:
2651 + class = PCI_CLASS_CRYPT;
2652 + subclass = PCI_CRYPT_NETWORK;
2653 + core = BCM47XX_IPSEC_ID;
2654 + break;
2655 + case SB_ROBO:
2656 + class = PCI_CLASS_NET;
2657 + subclass = PCI_NET_OTHER;
2658 + core = BCM47XX_ROBO_ID;
2659 + break;
2660 + case SB_EXTIF:
2661 + case SB_CC:
2662 + class = PCI_CLASS_MEMORY;
2663 + subclass = PCI_MEMORY_FLASH;
2664 + break;
2665 + case SB_D11:
2666 + class = PCI_CLASS_NET;
2667 + subclass = PCI_NET_OTHER;
2668 + /* Let an nvram variable override this */
2669 + sprintf(varname, "wl%did", wlidx);
2670 + wlidx++;
2671 + if ((core = getintvar(NULL, varname)) == 0) {
2672 + if (chip == BCM4712_DEVICE_ID) {
2673 + if (chippkg == BCM4712SMALL_PKG_ID)
2674 + core = BCM4306_D11G_ID;
2675 + else
2676 + core = BCM4306_D11DUAL_ID;
2677 + } else {
2678 + /* 4310 */
2679 + core = BCM4310_D11B_ID;
2680 + }
2681 + }
2682 + break;
2683 +
2684 + default:
2685 + class = subclass = progif = 0xff;
2686 + break;
2687 + }
2688 +
2689 + /* Supported translations */
2690 + cfg->vendor = htol16(vendor);
2691 + cfg->device = htol16(core);
2692 + cfg->rev_id = chiprev;
2693 + cfg->prog_if = progif;
2694 + cfg->sub_class = subclass;
2695 + cfg->base_class = class;
2696 + cfg->base[0] = htol32(sb_base(R_REG(&sb->sbadmatch0)));
2697 + cfg->base[1] = htol32(sb_base(R_REG(&sb->sbadmatch1)));
2698 + cfg->base[2] = htol32(sb_base(R_REG(&sb->sbadmatch2)));
2699 + cfg->base[3] = htol32(sb_base(R_REG(&sb->sbadmatch3)));
2700 + cfg->base[4] = 0;
2701 + cfg->base[5] = 0;
2702 + if (class == PCI_CLASS_BRIDGE && subclass == PCI_BRIDGE_PCI)
2703 + cfg->header_type = PCI_HEADER_BRIDGE;
2704 + else
2705 + cfg->header_type = PCI_HEADER_NORMAL;
2706 + /* Save core interrupt flag */
2707 + cfg->int_pin = R_REG(&sb->sbtpsflag) & SBTPS_NUM0_MASK;
2708 + /* Default to MIPS shared interrupt 0 */
2709 + cfg->int_line = 0;
2710 + /* MIPS sbipsflag maps core interrupt flags to interrupts 1 through 4 */
2711 + if ((regs = sb_setcore(sbh, SB_MIPS, 0)) ||
2712 + (regs = sb_setcore(sbh, SB_MIPS33, 0))) {
2713 + sb = (sbconfig_t *)((ulong) regs + SBCONFIGOFF);
2714 + val = R_REG(&sb->sbipsflag);
2715 + for (cfg->int_line = 1; cfg->int_line <= 4; cfg->int_line++) {
2716 + if (((val & sbips_int_mask[cfg->int_line]) >> sbips_int_shift[cfg->int_line]) == cfg->int_pin)
2717 + break;
2718 + }
2719 + if (cfg->int_line > 4)
2720 + cfg->int_line = 0;
2721 + }
2722 + /* Emulated core */
2723 + *((uint32 *) &cfg->sprom_control) = 0xffffffff;
2724 + }
2725 +
2726 + sb_setcoreidx(sbh, coreidx);
2727 + return 0;
2728 +}
2729 +
2730 +int __init
2731 +sbpci_init(sb_t *sbh)
2732 +{
2733 + sbpci_init_pci(sbh);
2734 + sbpci_init_cores(sbh);
2735 + return 0;
2736 +}
2737 +
2738 diff -urN linux.old/arch/mips/bcm947xx/broadcom/sbutils.c linux.dev/arch/mips/bcm947xx/broadcom/sbutils.c
2739 --- linux.old/arch/mips/bcm947xx/broadcom/sbutils.c 1970-01-01 01:00:00.000000000 +0100
2740 +++ linux.dev/arch/mips/bcm947xx/broadcom/sbutils.c 2005-12-15 17:31:12.211645500 +0100
2741 @@ -0,0 +1,2407 @@
2742 +/*
2743 + * Misc utility routines for accessing chip-specific features
2744 + * of the SiliconBackplane-based Broadcom chips.
2745 + *
2746 + * Copyright 2005, Broadcom Corporation
2747 + * All Rights Reserved.
2748 + *
2749 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
2750 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
2751 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
2752 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
2753 + * $Id$
2754 + */
2755 +
2756 +#include <typedefs.h>
2757 +#include <osl.h>
2758 +#include <sbutils.h>
2759 +#include <bcmutils.h>
2760 +#include <bcmdevs.h>
2761 +#include <sbconfig.h>
2762 +#include <sbchipc.h>
2763 +#include <sbpci.h>
2764 +#include <pcicfg.h>
2765 +#include <sbextif.h>
2766 +#include <bcmsrom.h>
2767 +
2768 +/* debug/trace */
2769 +#define SB_ERROR(args)
2770 +
2771 +
2772 +typedef uint32 (*sb_intrsoff_t)(void *intr_arg);
2773 +typedef void (*sb_intrsrestore_t)(void *intr_arg, uint32 arg);
2774 +typedef bool (*sb_intrsenabled_t)(void *intr_arg);
2775 +
2776 +/* misc sb info needed by some of the routines */
2777 +typedef struct sb_info {
2778 +
2779 + struct sb_pub sb; /* back plane public state(must be first field of sb_info */
2780 +
2781 + void *osh; /* osl os handle */
2782 + void *sdh; /* bcmsdh handle */
2783 +
2784 + void *curmap; /* current regs va */
2785 + void *regs[SB_MAXCORES]; /* other regs va */
2786 +
2787 + uint curidx; /* current core index */
2788 + uint dev_coreid; /* the core provides driver functions */
2789 +
2790 + uint gpioidx; /* gpio control core index */
2791 + uint gpioid; /* gpio control coretype */
2792 +
2793 + uint numcores; /* # discovered cores */
2794 + uint coreid[SB_MAXCORES]; /* id of each core */
2795 +
2796 + void *intr_arg; /* interrupt callback function arg */
2797 + sb_intrsoff_t intrsoff_fn; /* function turns chip interrupts off */
2798 + sb_intrsrestore_t intrsrestore_fn; /* function restore chip interrupts */
2799 + sb_intrsenabled_t intrsenabled_fn; /* function to check if chip interrupts are enabled */
2800 +
2801 +} sb_info_t;
2802 +
2803 +/* local prototypes */
2804 +static sb_info_t * BCMINIT(sb_doattach)(sb_info_t *si, uint devid, osl_t *osh, void *regs,
2805 + uint bustype, void *sdh, char **vars, int *varsz);
2806 +static void BCMINIT(sb_scan)(sb_info_t *si);
2807 +static uint sb_corereg(sb_info_t *si, uint coreidx, uint regoff, uint mask, uint val);
2808 +static uint _sb_coreidx(sb_info_t *si);
2809 +static uint sb_findcoreidx(sb_info_t *si, uint coreid, uint coreunit);
2810 +static uint BCMINIT(sb_pcidev2chip)(uint pcidev);
2811 +static uint BCMINIT(sb_chip2numcores)(uint chip);
2812 +static int sb_pci_fixcfg(sb_info_t *si);
2813 +
2814 +/* delay needed between the mdio control/ mdiodata register data access */
2815 +#define PR28829_DELAY() OSL_DELAY(10)
2816 +
2817 +
2818 +/* global variable to indicate reservation/release of gpio's*/
2819 +static uint32 sb_gpioreservation = 0;
2820 +
2821 +#define SB_INFO(sbh) (sb_info_t*)sbh
2822 +#define SET_SBREG(sbh, r, mask, val) W_SBREG((sbh), (r), ((R_SBREG((sbh), (r)) & ~(mask)) | (val)))
2823 +#define GOODCOREADDR(x) (((x) >= SB_ENUM_BASE) && ((x) <= SB_ENUM_LIM) && ISALIGNED((x), SB_CORE_SIZE))
2824 +#define GOODREGS(regs) ((regs) && ISALIGNED((uintptr)(regs), SB_CORE_SIZE))
2825 +#define REGS2SB(va) (sbconfig_t*) ((int8*)(va) + SBCONFIGOFF)
2826 +#define GOODIDX(idx) (((uint)idx) < SB_MAXCORES)
2827 +#define BADIDX (SB_MAXCORES+1)
2828 +#define NOREV -1
2829 +
2830 +#define PCI(si) ((BUSTYPE(si->sb.bustype) == PCI_BUS) && (si->sb.buscoretype == SB_PCI))
2831 +
2832 +/* sonicsrev */
2833 +#define SONICS_2_2 (SBIDL_RV_2_2 >> SBIDL_RV_SHIFT)
2834 +#define SONICS_2_3 (SBIDL_RV_2_3 >> SBIDL_RV_SHIFT)
2835 +
2836 +#define R_SBREG(sbh, sbr) sb_read_sbreg((sbh), (sbr))
2837 +#define W_SBREG(sbh, sbr, v) sb_write_sbreg((sbh), (sbr), (v))
2838 +#define AND_SBREG(sbh, sbr, v) W_SBREG((sbh), (sbr), (R_SBREG((sbh), (sbr)) & (v)))
2839 +#define OR_SBREG(sbh, sbr, v) W_SBREG((sbh), (sbr), (R_SBREG((sbh), (sbr)) | (v)))
2840 +
2841 +/*
2842 + * Macros to disable/restore function core(D11, ENET, ILINE20, etc) interrupts before/
2843 + * after core switching to avoid invalid register accesss inside ISR.
2844 + */
2845 +#define INTR_OFF(si, intr_val) \
2846 + if ((si)->intrsoff_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
2847 + intr_val = (*(si)->intrsoff_fn)((si)->intr_arg); }
2848 +#define INTR_RESTORE(si, intr_val) \
2849 + if ((si)->intrsrestore_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \
2850 + (*(si)->intrsrestore_fn)((si)->intr_arg, intr_val); }
2851 +
2852 +/* dynamic clock control defines */
2853 +#define LPOMINFREQ 25000 /* low power oscillator min */
2854 +#define LPOMAXFREQ 43000 /* low power oscillator max */
2855 +#define XTALMINFREQ 19800000 /* 20 MHz - 1% */
2856 +#define XTALMAXFREQ 20200000 /* 20 MHz + 1% */
2857 +#define PCIMINFREQ 25000000 /* 25 MHz */
2858 +#define PCIMAXFREQ 34000000 /* 33 MHz + fudge */
2859 +
2860 +#define ILP_DIV_5MHZ 0 /* ILP = 5 MHz */
2861 +#define ILP_DIV_1MHZ 4 /* ILP = 1 MHz */
2862 +
2863 +#define MIN_DUMPBUFLEN 32 /* debug */
2864 +
2865 +/* GPIO Based LED powersave defines */
2866 +#define DEFAULT_GPIO_ONTIME 10
2867 +#define DEFAULT_GPIO_OFFTIME 90
2868 +
2869 +#define DEFAULT_GPIOTIMERVAL ((DEFAULT_GPIO_ONTIME << GPIO_ONTIME_SHIFT) | DEFAULT_GPIO_OFFTIME)
2870 +
2871 +static uint32
2872 +sb_read_sbreg(sb_info_t *si, volatile uint32 *sbr)
2873 +{
2874 + uint32 val = R_REG(sbr);
2875 +
2876 + return (val);
2877 +}
2878 +
2879 +static void
2880 +sb_write_sbreg(sb_info_t *si, volatile uint32 *sbr, uint32 v)
2881 +{
2882 + W_REG(sbr, v);
2883 +}
2884 +
2885 +/* Using sb_kattach depends on SB_BUS support, either implicit */
2886 +/* no limiting BCMBUSTYPE value) or explicit (value is SB_BUS). */
2887 +#if !defined(BCMBUSTYPE) || (BCMBUSTYPE == SB_BUS)
2888 +
2889 +/* global kernel resource */
2890 +static sb_info_t ksi;
2891 +
2892 +/* generic kernel variant of sb_attach() */
2893 +sb_t *
2894 +BCMINITFN(sb_kattach)()
2895 +{
2896 + uint32 *regs;
2897 +
2898 + if (ksi.curmap == NULL) {
2899 + uint32 cid;
2900 +
2901 + regs = (uint32 *)REG_MAP(SB_ENUM_BASE, SB_CORE_SIZE);
2902 + cid = R_REG((uint32 *)regs);
2903 + if (((cid & CID_ID_MASK) == BCM4712_DEVICE_ID) &&
2904 + ((cid & CID_PKG_MASK) != BCM4712LARGE_PKG_ID) &&
2905 + ((cid & CID_REV_MASK) <= (3 << CID_REV_SHIFT))) {
2906 + uint32 *scc, val;
2907 +
2908 + scc = (uint32 *)((uchar*)regs + OFFSETOF(chipcregs_t, slow_clk_ctl));
2909 + val = R_REG(scc);
2910 + SB_ERROR((" initial scc = 0x%x\n", val));
2911 + val |= SCC_SS_XTAL;
2912 + W_REG(scc, val);
2913 + }
2914 +
2915 + if (BCMINIT(sb_doattach)(&ksi, BCM4710_DEVICE_ID, NULL, (void*)regs,
2916 + SB_BUS, NULL, NULL, NULL) == NULL) {
2917 + return NULL;
2918 + }
2919 + }
2920 +
2921 + return (sb_t *)&ksi;
2922 +}
2923 +#endif
2924 +
2925 +static sb_info_t *
2926 +BCMINITFN(sb_doattach)(sb_info_t *si, uint devid, osl_t *osh, void *regs,
2927 + uint bustype, void *sdh, char **vars, int *varsz)
2928 +{
2929 + uint origidx;
2930 + chipcregs_t *cc;
2931 + sbconfig_t *sb;
2932 + uint32 w;
2933 +
2934 + ASSERT(GOODREGS(regs));
2935 +
2936 + bzero((uchar*)si, sizeof (sb_info_t));
2937 +
2938 + si->sb.buscoreidx = si->gpioidx = BADIDX;
2939 +
2940 + si->osh = osh;
2941 + si->curmap = regs;
2942 + si->sdh = sdh;
2943 +
2944 + /* check to see if we are a sb core mimic'ing a pci core */
2945 + if (bustype == PCI_BUS) {
2946 + if (OSL_PCI_READ_CONFIG(osh, PCI_SPROM_CONTROL, sizeof (uint32)) == 0xffffffff)
2947 + bustype = SB_BUS;
2948 + else
2949 + bustype = PCI_BUS;
2950 + }
2951 +
2952 + si->sb.bustype = bustype;
2953 + if (si->sb.bustype != BUSTYPE(si->sb.bustype)) {
2954 + SB_ERROR(("sb_doattach: bus type %d does not match configured bus type %d\n",
2955 + si->sb.bustype, BUSTYPE(si->sb.bustype)));
2956 + return NULL;
2957 + }
2958 +
2959 + /* kludge to enable the clock on the 4306 which lacks a slowclock */
2960 + if (BUSTYPE(si->sb.bustype) == PCI_BUS)
2961 + sb_clkctl_xtal(&si->sb, XTAL|PLL, ON);
2962 +
2963 + if (BUSTYPE(si->sb.bustype) == PCI_BUS) {
2964 + w = OSL_PCI_READ_CONFIG(osh, PCI_BAR0_WIN, sizeof (uint32));
2965 + if (!GOODCOREADDR(w))
2966 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_BAR0_WIN, sizeof (uint32), SB_ENUM_BASE);
2967 + }
2968 +
2969 + /* initialize current core index value */
2970 + si->curidx = _sb_coreidx(si);
2971 +
2972 + if (si->curidx == BADIDX) {
2973 + SB_ERROR(("sb_doattach: bad core index\n"));
2974 + return NULL;
2975 + }
2976 +
2977 + /* get sonics backplane revision */
2978 + sb = REGS2SB(si->curmap);
2979 + si->sb.sonicsrev = (R_SBREG(si, &(sb)->sbidlow) & SBIDL_RV_MASK) >> SBIDL_RV_SHIFT;
2980 +
2981 + /* keep and reuse the initial register mapping */
2982 + origidx = si->curidx;
2983 + if (BUSTYPE(si->sb.bustype) == SB_BUS)
2984 + si->regs[origidx] = regs;
2985 +
2986 + /* is core-0 a chipcommon core? */
2987 + si->numcores = 1;
2988 + cc = (chipcregs_t*) sb_setcoreidx(&si->sb, 0);
2989 + if (sb_coreid(&si->sb) != SB_CC)
2990 + cc = NULL;
2991 +
2992 + /* determine chip id and rev */
2993 + if (cc) {
2994 + /* chip common core found! */
2995 + si->sb.chip = R_REG(&cc->chipid) & CID_ID_MASK;
2996 + si->sb.chiprev = (R_REG(&cc->chipid) & CID_REV_MASK) >> CID_REV_SHIFT;
2997 + si->sb.chippkg = (R_REG(&cc->chipid) & CID_PKG_MASK) >> CID_PKG_SHIFT;
2998 + } else {
2999 + /* no chip common core -- must convert device id to chip id */
3000 + if ((si->sb.chip = BCMINIT(sb_pcidev2chip)(devid)) == 0) {
3001 + SB_ERROR(("sb_doattach: unrecognized device id 0x%04x\n", devid));
3002 + sb_setcoreidx(&si->sb, origidx);
3003 + return NULL;
3004 + }
3005 + }
3006 +
3007 + /* get chipcommon rev */
3008 + si->sb.ccrev = cc ? (int)sb_corerev(&si->sb) : NOREV;
3009 +
3010 + /* determine numcores */
3011 + if (cc && ((si->sb.ccrev == 4) || (si->sb.ccrev >= 6)))
3012 + si->numcores = (R_REG(&cc->chipid) & CID_CC_MASK) >> CID_CC_SHIFT;
3013 + else
3014 + si->numcores = BCMINIT(sb_chip2numcores)(si->sb.chip);
3015 +
3016 + /* return to original core */
3017 + sb_setcoreidx(&si->sb, origidx);
3018 +
3019 + /* sanity checks */
3020 + ASSERT(si->sb.chip);
3021 +
3022 + /* scan for cores */
3023 + BCMINIT(sb_scan)(si);
3024 +
3025 + /* fixup necessary chip/core configurations */
3026 + if (BUSTYPE(si->sb.bustype) == PCI_BUS) {
3027 + if (sb_pci_fixcfg(si)) {
3028 + SB_ERROR(("sb_doattach: sb_pci_fixcfg failed\n"));
3029 + return NULL;
3030 + }
3031 + }
3032 +
3033 + /* srom_var_init() depends on sb_scan() info */
3034 + if (srom_var_init(si, si->sb.bustype, si->curmap, osh, vars, varsz)) {
3035 + SB_ERROR(("sb_doattach: srom_var_init failed: bad srom\n"));
3036 + return (NULL);
3037 + }
3038 +
3039 + if (cc == NULL) {
3040 + /*
3041 + * The chip revision number is hardwired into all
3042 + * of the pci function config rev fields and is
3043 + * independent from the individual core revision numbers.
3044 + * For example, the "A0" silicon of each chip is chip rev 0.
3045 + */
3046 + if (BUSTYPE(si->sb.bustype) == PCI_BUS) {
3047 + w = OSL_PCI_READ_CONFIG(osh, PCI_CFG_REV, sizeof (uint32));
3048 + si->sb.chiprev = w & 0xff;
3049 + } else
3050 + si->sb.chiprev = 0;
3051 + }
3052 +
3053 + /* gpio control core is required */
3054 + if (!GOODIDX(si->gpioidx)) {
3055 + SB_ERROR(("sb_doattach: gpio control core not found\n"));
3056 + return NULL;
3057 + }
3058 +
3059 + /* get boardtype and boardrev */
3060 + switch (BUSTYPE(si->sb.bustype)) {
3061 + case PCI_BUS:
3062 + /* do a pci config read to get subsystem id and subvendor id */
3063 + w = OSL_PCI_READ_CONFIG(osh, PCI_CFG_SVID, sizeof (uint32));
3064 + si->sb.boardvendor = w & 0xffff;
3065 + si->sb.boardtype = (w >> 16) & 0xffff;
3066 + break;
3067 +
3068 + case SB_BUS:
3069 + case JTAG_BUS:
3070 + si->sb.boardvendor = VENDOR_BROADCOM;
3071 + if ((si->sb.boardtype = getintvar(NULL, "boardtype")) == 0)
3072 + si->sb.boardtype = 0xffff;
3073 + break;
3074 + }
3075 +
3076 + if (si->sb.boardtype == 0) {
3077 + SB_ERROR(("sb_doattach: unknown board type\n"));
3078 + ASSERT(si->sb.boardtype);
3079 + }
3080 +
3081 + /* setup the GPIO based LED powersave register */
3082 + if (si->sb.ccrev >= 16) {
3083 + w = getintvar(*vars, "gpiotimerval");
3084 + if (!w)
3085 + w = DEFAULT_GPIOTIMERVAL;
3086 + sb_corereg(si, 0, OFFSETOF(chipcregs_t, gpiotimerval), ~0, w);
3087 + }
3088 +
3089 +
3090 + return (si);
3091 +}
3092 +
3093 +uint
3094 +sb_coreid(sb_t *sbh)
3095 +{
3096 + sb_info_t *si;
3097 + sbconfig_t *sb;
3098 +
3099 + si = SB_INFO(sbh);
3100 + sb = REGS2SB(si->curmap);
3101 +
3102 + return ((R_SBREG(si, &(sb)->sbidhigh) & SBIDH_CC_MASK) >> SBIDH_CC_SHIFT);
3103 +}
3104 +
3105 +uint
3106 +sb_coreidx(sb_t *sbh)
3107 +{
3108 + sb_info_t *si;
3109 +
3110 + si = SB_INFO(sbh);
3111 + return (si->curidx);
3112 +}
3113 +
3114 +/* return current index of core */
3115 +static uint
3116 +_sb_coreidx(sb_info_t *si)
3117 +{
3118 + sbconfig_t *sb;
3119 + uint32 sbaddr = 0;
3120 +
3121 + ASSERT(si);
3122 +
3123 + switch (BUSTYPE(si->sb.bustype)) {
3124 + case SB_BUS:
3125 + sb = REGS2SB(si->curmap);
3126 + sbaddr = sb_base(R_SBREG(si, &sb->sbadmatch0));
3127 + break;
3128 +
3129 + case PCI_BUS:
3130 + sbaddr = OSL_PCI_READ_CONFIG(si->osh, PCI_BAR0_WIN, sizeof (uint32));
3131 + break;
3132 +
3133 +#ifdef BCMJTAG
3134 + case JTAG_BUS:
3135 + sbaddr = (uint32)si->curmap;
3136 + break;
3137 +#endif /* BCMJTAG */
3138 +
3139 + default:
3140 + ASSERT(0);
3141 + }
3142 +
3143 + if (!GOODCOREADDR(sbaddr))
3144 + return BADIDX;
3145 +
3146 + return ((sbaddr - SB_ENUM_BASE) / SB_CORE_SIZE);
3147 +}
3148 +
3149 +uint
3150 +sb_corevendor(sb_t *sbh)
3151 +{
3152 + sb_info_t *si;
3153 + sbconfig_t *sb;
3154 +
3155 + si = SB_INFO(sbh);
3156 + sb = REGS2SB(si->curmap);
3157 +
3158 + return ((R_SBREG(si, &(sb)->sbidhigh) & SBIDH_VC_MASK) >> SBIDH_VC_SHIFT);
3159 +}
3160 +
3161 +uint
3162 +sb_corerev(sb_t *sbh)
3163 +{
3164 + sb_info_t *si;
3165 + sbconfig_t *sb;
3166 + uint sbidh;
3167 +
3168 + si = SB_INFO(sbh);
3169 + sb = REGS2SB(si->curmap);
3170 + sbidh = R_SBREG(si, &(sb)->sbidhigh);
3171 +
3172 + return (SBCOREREV(sbidh));
3173 +}
3174 +
3175 +void *
3176 +sb_osh(sb_t *sbh)
3177 +{
3178 + sb_info_t *si;
3179 +
3180 + si = SB_INFO(sbh);
3181 + return si->osh;
3182 +}
3183 +
3184 +#define SBTML_ALLOW (SBTML_PE | SBTML_FGC | SBTML_FL_MASK)
3185 +
3186 +/* set/clear sbtmstatelow core-specific flags */
3187 +uint32
3188 +sb_coreflags(sb_t *sbh, uint32 mask, uint32 val)
3189 +{
3190 + sb_info_t *si;
3191 + sbconfig_t *sb;
3192 + uint32 w;
3193 +
3194 + si = SB_INFO(sbh);
3195 + sb = REGS2SB(si->curmap);
3196 +
3197 + ASSERT((val & ~mask) == 0);
3198 + ASSERT((mask & ~SBTML_ALLOW) == 0);
3199 +
3200 + /* mask and set */
3201 + if (mask || val) {
3202 + w = (R_SBREG(si, &sb->sbtmstatelow) & ~mask) | val;
3203 + W_SBREG(si, &sb->sbtmstatelow, w);
3204 + }
3205 +
3206 + /* return the new value */
3207 + return (R_SBREG(si, &sb->sbtmstatelow) & SBTML_ALLOW);
3208 +}
3209 +
3210 +/* set/clear sbtmstatehigh core-specific flags */
3211 +uint32
3212 +sb_coreflagshi(sb_t *sbh, uint32 mask, uint32 val)
3213 +{
3214 + sb_info_t *si;
3215 + sbconfig_t *sb;
3216 + uint32 w;
3217 +
3218 + si = SB_INFO(sbh);
3219 + sb = REGS2SB(si->curmap);
3220 +
3221 + ASSERT((val & ~mask) == 0);
3222 + ASSERT((mask & ~SBTMH_FL_MASK) == 0);
3223 +
3224 + /* mask and set */
3225 + if (mask || val) {
3226 + w = (R_SBREG(si, &sb->sbtmstatehigh) & ~mask) | val;
3227 + W_SBREG(si, &sb->sbtmstatehigh, w);
3228 + }
3229 +
3230 + /* return the new value */
3231 + return (R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_FL_MASK);
3232 +}
3233 +
3234 +/* caller needs to take care of core-specific bist hazards */
3235 +int
3236 +sb_corebist(sb_t *sbh, uint coreid, uint coreunit)
3237 +{
3238 + uint32 sblo;
3239 + uint coreidx;
3240 + sb_info_t *si;
3241 + int result = 0;
3242 +
3243 + si = SB_INFO(sbh);
3244 +
3245 + coreidx = sb_findcoreidx(si, coreid, coreunit);
3246 + if (!GOODIDX(coreidx))
3247 + result = BCME_ERROR;
3248 + else {
3249 + sblo = sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatelow), 0, 0);
3250 + sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatelow), ~0, (sblo | SBTML_FGC | SBTML_BE));
3251 +
3252 + SPINWAIT(((sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatehigh), 0, 0) & SBTMH_BISTD) == 0), 100000);
3253 +
3254 + if (sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatehigh), 0, 0) & SBTMH_BISTF)
3255 + result = BCME_ERROR;
3256 +
3257 + sb_corereg(si, coreidx, SBCONFIGOFF + OFFSETOF(sbconfig_t, sbtmstatelow), ~0, sblo);
3258 + }
3259 +
3260 + return result;
3261 +}
3262 +
3263 +bool
3264 +sb_iscoreup(sb_t *sbh)
3265 +{
3266 + sb_info_t *si;
3267 + sbconfig_t *sb;
3268 +
3269 + si = SB_INFO(sbh);
3270 + sb = REGS2SB(si->curmap);
3271 +
3272 + return ((R_SBREG(si, &(sb)->sbtmstatelow) & (SBTML_RESET | SBTML_REJ_MASK | SBTML_CLK)) == SBTML_CLK);
3273 +}
3274 +
3275 +/*
3276 + * Switch to 'coreidx', issue a single arbitrary 32bit register mask&set operation,
3277 + * switch back to the original core, and return the new value.
3278 + */
3279 +static uint
3280 +sb_corereg(sb_info_t *si, uint coreidx, uint regoff, uint mask, uint val)
3281 +{
3282 + uint origidx;
3283 + uint32 *r;
3284 + uint w;
3285 + uint intr_val = 0;
3286 +
3287 + ASSERT(GOODIDX(coreidx));
3288 + ASSERT(regoff < SB_CORE_SIZE);
3289 + ASSERT((val & ~mask) == 0);
3290 +
3291 + INTR_OFF(si, intr_val);
3292 +
3293 + /* save current core index */
3294 + origidx = sb_coreidx(&si->sb);
3295 +
3296 + /* switch core */
3297 + r = (uint32*) ((uchar*) sb_setcoreidx(&si->sb, coreidx) + regoff);
3298 +
3299 + /* mask and set */
3300 + if (mask || val) {
3301 + if (regoff >= SBCONFIGOFF) {
3302 + w = (R_SBREG(si, r) & ~mask) | val;
3303 + W_SBREG(si, r, w);
3304 + } else {
3305 + w = (R_REG(r) & ~mask) | val;
3306 + W_REG(r, w);
3307 + }
3308 + }
3309 +
3310 + /* readback */
3311 + if (regoff >= SBCONFIGOFF)
3312 + w = R_SBREG(si, r);
3313 + else
3314 + w = R_REG(r);
3315 +
3316 + /* restore core index */
3317 + if (origidx != coreidx)
3318 + sb_setcoreidx(&si->sb, origidx);
3319 +
3320 + INTR_RESTORE(si, intr_val);
3321 + return (w);
3322 +}
3323 +
3324 +#define DWORD_ALIGN(x) (x & ~(0x03))
3325 +#define BYTE_POS(x) (x & 0x3)
3326 +#define WORD_POS(x) (x & 0x1)
3327 +
3328 +#define BYTE_SHIFT(x) (8 * BYTE_POS(x))
3329 +#define WORD_SHIFT(x) (16 * WORD_POS(x))
3330 +
3331 +#define BYTE_VAL(a, x) ((a >> BYTE_SHIFT(x)) & 0xFF)
3332 +#define WORD_VAL(a, x) ((a >> WORD_SHIFT(x)) & 0xFFFF)
3333 +
3334 +#define read_pci_cfg_byte(a) \
3335 + (BYTE_VAL(OSL_PCI_READ_CONFIG(si->osh, DWORD_ALIGN(a), 4), a) & 0xff)
3336 +
3337 +#define read_pci_cfg_write(a) \
3338 + (WORD_VAL(OSL_PCI_READ_CONFIG(si->osh, DWORD_ALIGN(a), 4), a) & 0xffff)
3339 +
3340 +
3341 +/* scan the sb enumerated space to identify all cores */
3342 +static void
3343 +BCMINITFN(sb_scan)(sb_info_t *si)
3344 +{
3345 + uint origidx;
3346 + uint i;
3347 + bool pci;
3348 + uint pciidx;
3349 + uint pcirev;
3350 +
3351 +
3352 +
3353 + /* numcores should already be set */
3354 + ASSERT((si->numcores > 0) && (si->numcores <= SB_MAXCORES));
3355 +
3356 + /* save current core index */
3357 + origidx = sb_coreidx(&si->sb);
3358 +
3359 + si->sb.buscorerev = NOREV;
3360 + si->sb.buscoreidx = BADIDX;
3361 +
3362 + si->gpioidx = BADIDX;
3363 +
3364 + pci = FALSE;
3365 + pcirev = NOREV;
3366 + pciidx = BADIDX;
3367 +
3368 + for (i = 0; i < si->numcores; i++) {
3369 + sb_setcoreidx(&si->sb, i);
3370 + si->coreid[i] = sb_coreid(&si->sb);
3371 +
3372 + if (si->coreid[i] == SB_PCI) {
3373 + pciidx = i;
3374 + pcirev = sb_corerev(&si->sb);
3375 + pci = TRUE;
3376 + }
3377 + }
3378 + if (pci) {
3379 + si->sb.buscoretype = SB_PCI;
3380 + si->sb.buscorerev = pcirev;
3381 + si->sb.buscoreidx = pciidx;
3382 + }
3383 +
3384 + /*
3385 + * Find the gpio "controlling core" type and index.
3386 + * Precedence:
3387 + * - if there's a chip common core - use that
3388 + * - else if there's a pci core (rev >= 2) - use that
3389 + * - else there had better be an extif core (4710 only)
3390 + */
3391 + if (GOODIDX(sb_findcoreidx(si, SB_CC, 0))) {
3392 + si->gpioidx = sb_findcoreidx(si, SB_CC, 0);
3393 + si->gpioid = SB_CC;
3394 + } else if (PCI(si) && (si->sb.buscorerev >= 2)) {
3395 + si->gpioidx = si->sb.buscoreidx;
3396 + si->gpioid = SB_PCI;
3397 + } else if (sb_findcoreidx(si, SB_EXTIF, 0)) {
3398 + si->gpioidx = sb_findcoreidx(si, SB_EXTIF, 0);
3399 + si->gpioid = SB_EXTIF;
3400 + } else
3401 + ASSERT(si->gpioidx != BADIDX);
3402 +
3403 + /* return to original core index */
3404 + sb_setcoreidx(&si->sb, origidx);
3405 +}
3406 +
3407 +/* may be called with core in reset */
3408 +void
3409 +sb_detach(sb_t *sbh)
3410 +{
3411 + sb_info_t *si;
3412 + uint idx;
3413 +
3414 + si = SB_INFO(sbh);
3415 +
3416 + if (si == NULL)
3417 + return;
3418 +
3419 + if (BUSTYPE(si->sb.bustype) == SB_BUS)
3420 + for (idx = 0; idx < SB_MAXCORES; idx++)
3421 + if (si->regs[idx]) {
3422 + REG_UNMAP(si->regs[idx]);
3423 + si->regs[idx] = NULL;
3424 + }
3425 +
3426 + if (si != &ksi)
3427 + MFREE(si->osh, si, sizeof (sb_info_t));
3428 +}
3429 +
3430 +/* use pci dev id to determine chip id for chips not having a chipcommon core */
3431 +static uint
3432 +BCMINITFN(sb_pcidev2chip)(uint pcidev)
3433 +{
3434 + if ((pcidev >= BCM4710_DEVICE_ID) && (pcidev <= BCM47XX_USB_ID))
3435 + return (BCM4710_DEVICE_ID);
3436 + if ((pcidev >= BCM4402_DEVICE_ID) && (pcidev <= BCM4402_V90_ID))
3437 + return (BCM4402_DEVICE_ID);
3438 + if (pcidev == BCM4401_ENET_ID)
3439 + return (BCM4402_DEVICE_ID);
3440 + if ((pcidev >= BCM4307_V90_ID) && (pcidev <= BCM4307_D11B_ID))
3441 + return (BCM4307_DEVICE_ID);
3442 + if (pcidev == BCM4301_DEVICE_ID)
3443 + return (BCM4301_DEVICE_ID);
3444 +
3445 + return (0);
3446 +}
3447 +
3448 +/* convert chip number to number of i/o cores */
3449 +static uint
3450 +BCMINITFN(sb_chip2numcores)(uint chip)
3451 +{
3452 + if (chip == BCM4710_DEVICE_ID)
3453 + return (9);
3454 + if (chip == BCM4402_DEVICE_ID)
3455 + return (3);
3456 + if ((chip == BCM4301_DEVICE_ID) || (chip == BCM4307_DEVICE_ID))
3457 + return (5);
3458 + if (chip == BCM4306_DEVICE_ID) /* < 4306c0 */
3459 + return (6);
3460 + if (chip == BCM4704_DEVICE_ID)
3461 + return (9);
3462 + if (chip == BCM5365_DEVICE_ID)
3463 + return (7);
3464 +
3465 + SB_ERROR(("sb_chip2numcores: unsupported chip 0x%x\n", chip));
3466 + ASSERT(0);
3467 + return (1);
3468 +}
3469 +
3470 +/* return index of coreid or BADIDX if not found */
3471 +static uint
3472 +sb_findcoreidx( sb_info_t *si, uint coreid, uint coreunit)
3473 +{
3474 + uint found;
3475 + uint i;
3476 +
3477 + found = 0;
3478 +
3479 + for (i = 0; i < si->numcores; i++)
3480 + if (si->coreid[i] == coreid) {
3481 + if (found == coreunit)
3482 + return (i);
3483 + found++;
3484 + }
3485 +
3486 + return (BADIDX);
3487 +}
3488 +
3489 +/*
3490 + * this function changes logical "focus" to the indiciated core,
3491 + * must be called with interrupt off.
3492 + * Moreover, callers should keep interrupts off during switching out of and back to d11 core
3493 + */
3494 +void*
3495 +sb_setcoreidx(sb_t *sbh, uint coreidx)
3496 +{
3497 + sb_info_t *si;
3498 + uint32 sbaddr;
3499 +
3500 + si = SB_INFO(sbh);
3501 +
3502 + if (coreidx >= si->numcores)
3503 + return (NULL);
3504 +
3505 + /*
3506 + * If the user has provided an interrupt mask enabled function,
3507 + * then assert interrupts are disabled before switching the core.
3508 + */
3509 + ASSERT((si->intrsenabled_fn == NULL) || !(*(si)->intrsenabled_fn)((si)->intr_arg));
3510 +
3511 + sbaddr = SB_ENUM_BASE + (coreidx * SB_CORE_SIZE);
3512 +
3513 + switch (BUSTYPE(si->sb.bustype)) {
3514 + case SB_BUS:
3515 + /* map new one */
3516 + if (!si->regs[coreidx]) {
3517 + si->regs[coreidx] = (void*)REG_MAP(sbaddr, SB_CORE_SIZE);
3518 + ASSERT(GOODREGS(si->regs[coreidx]));
3519 + }
3520 + si->curmap = si->regs[coreidx];
3521 + break;
3522 +
3523 + case PCI_BUS:
3524 + /* point bar0 window */
3525 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_BAR0_WIN, 4, sbaddr);
3526 + break;
3527 +
3528 +#ifdef BCMJTAG
3529 + case JTAG_BUS:
3530 + /* map new one */
3531 + if (!si->regs[coreidx]) {
3532 + si->regs[coreidx] = (void *)sbaddr;
3533 + ASSERT(GOODREGS(si->regs[coreidx]));
3534 + }
3535 + si->curmap = si->regs[coreidx];
3536 + break;
3537 +#endif /* BCMJTAG */
3538 + }
3539 +
3540 + si->curidx = coreidx;
3541 +
3542 + return (si->curmap);
3543 +}
3544 +
3545 +/*
3546 + * this function changes logical "focus" to the indiciated core,
3547 + * must be called with interrupt off.
3548 + * Moreover, callers should keep interrupts off during switching out of and back to d11 core
3549 + */
3550 +void*
3551 +sb_setcore(sb_t *sbh, uint coreid, uint coreunit)
3552 +{
3553 + sb_info_t *si;
3554 + uint idx;
3555 +
3556 + si = SB_INFO(sbh);
3557 + idx = sb_findcoreidx(si, coreid, coreunit);
3558 + if (!GOODIDX(idx))
3559 + return (NULL);
3560 +
3561 + return (sb_setcoreidx(sbh, idx));
3562 +}
3563 +
3564 +/* return chip number */
3565 +uint
3566 +BCMINITFN(sb_chip)(sb_t *sbh)
3567 +{
3568 + sb_info_t *si;
3569 +
3570 + si = SB_INFO(sbh);
3571 + return (si->sb.chip);
3572 +}
3573 +
3574 +/* return chip revision number */
3575 +uint
3576 +BCMINITFN(sb_chiprev)(sb_t *sbh)
3577 +{
3578 + sb_info_t *si;
3579 +
3580 + si = SB_INFO(sbh);
3581 + return (si->sb.chiprev);
3582 +}
3583 +
3584 +/* return chip common revision number */
3585 +uint
3586 +BCMINITFN(sb_chipcrev)(sb_t *sbh)
3587 +{
3588 + sb_info_t *si;
3589 +
3590 + si = SB_INFO(sbh);
3591 + return (si->sb.ccrev);
3592 +}
3593 +
3594 +/* return chip package option */
3595 +uint
3596 +BCMINITFN(sb_chippkg)(sb_t *sbh)
3597 +{
3598 + sb_info_t *si;
3599 +
3600 + si = SB_INFO(sbh);
3601 + return (si->sb.chippkg);
3602 +}
3603 +
3604 +/* return PCI core rev. */
3605 +uint
3606 +BCMINITFN(sb_pcirev)(sb_t *sbh)
3607 +{
3608 + sb_info_t *si;
3609 +
3610 + si = SB_INFO(sbh);
3611 + return (si->sb.buscorerev);
3612 +}
3613 +
3614 +bool
3615 +BCMINITFN(sb_war16165)(sb_t *sbh)
3616 +{
3617 + sb_info_t *si;
3618 +
3619 + si = SB_INFO(sbh);
3620 +
3621 + return (PCI(si) && (si->sb.buscorerev <= 10));
3622 +}
3623 +
3624 +/* return board vendor id */
3625 +uint
3626 +BCMINITFN(sb_boardvendor)(sb_t *sbh)
3627 +{
3628 + sb_info_t *si;
3629 +
3630 + si = SB_INFO(sbh);
3631 + return (si->sb.boardvendor);
3632 +}
3633 +
3634 +/* return boardtype */
3635 +uint
3636 +BCMINITFN(sb_boardtype)(sb_t *sbh)
3637 +{
3638 + sb_info_t *si;
3639 + char *var;
3640 +
3641 + si = SB_INFO(sbh);
3642 +
3643 + if (BUSTYPE(si->sb.bustype) == SB_BUS && si->sb.boardtype == 0xffff) {
3644 + /* boardtype format is a hex string */
3645 + si->sb.boardtype = getintvar(NULL, "boardtype");
3646 +
3647 + /* backward compatibility for older boardtype string format */
3648 + if ((si->sb.boardtype == 0) && (var = getvar(NULL, "boardtype"))) {
3649 + if (!strcmp(var, "bcm94710dev"))
3650 + si->sb.boardtype = BCM94710D_BOARD;
3651 + else if (!strcmp(var, "bcm94710ap"))
3652 + si->sb.boardtype = BCM94710AP_BOARD;
3653 + else if (!strcmp(var, "bu4710"))
3654 + si->sb.boardtype = BU4710_BOARD;
3655 + else if (!strcmp(var, "bcm94702mn"))
3656 + si->sb.boardtype = BCM94702MN_BOARD;
3657 + else if (!strcmp(var, "bcm94710r1"))
3658 + si->sb.boardtype = BCM94710R1_BOARD;
3659 + else if (!strcmp(var, "bcm94710r4"))
3660 + si->sb.boardtype = BCM94710R4_BOARD;
3661 + else if (!strcmp(var, "bcm94702cpci"))
3662 + si->sb.boardtype = BCM94702CPCI_BOARD;
3663 + else if (!strcmp(var, "bcm95380_rr"))
3664 + si->sb.boardtype = BCM95380RR_BOARD;
3665 + }
3666 + }
3667 +
3668 + return (si->sb.boardtype);
3669 +}
3670 +
3671 +/* return bus type of sbh device */
3672 +uint
3673 +sb_bus(sb_t *sbh)
3674 +{
3675 + sb_info_t *si;
3676 +
3677 + si = SB_INFO(sbh);
3678 + return (si->sb.bustype);
3679 +}
3680 +
3681 +/* return bus core type */
3682 +uint
3683 +sb_buscoretype(sb_t *sbh)
3684 +{
3685 + sb_info_t *si;
3686 +
3687 + si = SB_INFO(sbh);
3688 +
3689 + return (si->sb.buscoretype);
3690 +}
3691 +
3692 +/* return bus core revision */
3693 +uint
3694 +sb_buscorerev(sb_t *sbh)
3695 +{
3696 + sb_info_t *si;
3697 + si = SB_INFO(sbh);
3698 +
3699 + return (si->sb.buscorerev);
3700 +}
3701 +
3702 +/* return list of found cores */
3703 +uint
3704 +sb_corelist(sb_t *sbh, uint coreid[])
3705 +{
3706 + sb_info_t *si;
3707 +
3708 + si = SB_INFO(sbh);
3709 +
3710 + bcopy((uchar*)si->coreid, (uchar*)coreid, (si->numcores * sizeof (uint)));
3711 + return (si->numcores);
3712 +}
3713 +
3714 +/* return current register mapping */
3715 +void *
3716 +sb_coreregs(sb_t *sbh)
3717 +{
3718 + sb_info_t *si;
3719 +
3720 + si = SB_INFO(sbh);
3721 + ASSERT(GOODREGS(si->curmap));
3722 +
3723 + return (si->curmap);
3724 +}
3725 +
3726 +
3727 +/* do buffered registers update */
3728 +void
3729 +sb_commit(sb_t *sbh)
3730 +{
3731 + sb_info_t *si;
3732 + uint origidx;
3733 + uint intr_val = 0;
3734 +
3735 + si = SB_INFO(sbh);
3736 +
3737 + origidx = si->curidx;
3738 + ASSERT(GOODIDX(origidx));
3739 +
3740 + INTR_OFF(si, intr_val);
3741 +
3742 + /* switch over to chipcommon core if there is one, else use pci */
3743 + if (si->sb.ccrev != NOREV) {
3744 + chipcregs_t *ccregs = (chipcregs_t *)sb_setcore(sbh, SB_CC, 0);
3745 +
3746 + /* do the buffer registers update */
3747 + W_REG(&ccregs->broadcastaddress, SB_COMMIT);
3748 + W_REG(&ccregs->broadcastdata, 0x0);
3749 + } else if (PCI(si)) {
3750 + sbpciregs_t *pciregs = (sbpciregs_t *)sb_setcore(sbh, SB_PCI, 0);
3751 +
3752 + /* do the buffer registers update */
3753 + W_REG(&pciregs->bcastaddr, SB_COMMIT);
3754 + W_REG(&pciregs->bcastdata, 0x0);
3755 + } else
3756 + ASSERT(0);
3757 +
3758 + /* restore core index */
3759 + sb_setcoreidx(sbh, origidx);
3760 + INTR_RESTORE(si, intr_val);
3761 +}
3762 +
3763 +/* reset and re-enable a core */
3764 +void
3765 +sb_core_reset(sb_t *sbh, uint32 bits)
3766 +{
3767 + sb_info_t *si;
3768 + sbconfig_t *sb;
3769 + volatile uint32 dummy;
3770 +
3771 + si = SB_INFO(sbh);
3772 + ASSERT(GOODREGS(si->curmap));
3773 + sb = REGS2SB(si->curmap);
3774 +
3775 + /*
3776 + * Must do the disable sequence first to work for arbitrary current core state.
3777 + */
3778 + sb_core_disable(sbh, bits);
3779 +
3780 + /*
3781 + * Now do the initialization sequence.
3782 + */
3783 +
3784 + /* set reset while enabling the clock and forcing them on throughout the core */
3785 + W_SBREG(si, &sb->sbtmstatelow, (SBTML_FGC | SBTML_CLK | SBTML_RESET | bits));
3786 + dummy = R_SBREG(si, &sb->sbtmstatelow);
3787 + OSL_DELAY(1);
3788 +
3789 + if (R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_SERR) {
3790 + W_SBREG(si, &sb->sbtmstatehigh, 0);
3791 + }
3792 + if ((dummy = R_SBREG(si, &sb->sbimstate)) & (SBIM_IBE | SBIM_TO)) {
3793 + AND_SBREG(si, &sb->sbimstate, ~(SBIM_IBE | SBIM_TO));
3794 + }
3795 +
3796 + /* clear reset and allow it to propagate throughout the core */
3797 + W_SBREG(si, &sb->sbtmstatelow, (SBTML_FGC | SBTML_CLK | bits));
3798 + dummy = R_SBREG(si, &sb->sbtmstatelow);
3799 + OSL_DELAY(1);
3800 +
3801 + /* leave clock enabled */
3802 + W_SBREG(si, &sb->sbtmstatelow, (SBTML_CLK | bits));
3803 + dummy = R_SBREG(si, &sb->sbtmstatelow);
3804 + OSL_DELAY(1);
3805 +}
3806 +
3807 +void
3808 +sb_core_tofixup(sb_t *sbh)
3809 +{
3810 + sb_info_t *si;
3811 + sbconfig_t *sb;
3812 +
3813 + si = SB_INFO(sbh);
3814 +
3815 + if ( (BUSTYPE(si->sb.bustype) != PCI_BUS) || (PCI(si) && (si->sb.buscorerev >= 5)) )
3816 + return;
3817 +
3818 + ASSERT(GOODREGS(si->curmap));
3819 + sb = REGS2SB(si->curmap);
3820 +
3821 + if (BUSTYPE(si->sb.bustype) == SB_BUS) {
3822 + SET_SBREG(si, &sb->sbimconfiglow,
3823 + SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
3824 + (0x5 << SBIMCL_RTO_SHIFT) | 0x3);
3825 + } else {
3826 + if (sb_coreid(sbh) == SB_PCI) {
3827 + SET_SBREG(si, &sb->sbimconfiglow,
3828 + SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
3829 + (0x3 << SBIMCL_RTO_SHIFT) | 0x2);
3830 + } else {
3831 + SET_SBREG(si, &sb->sbimconfiglow, (SBIMCL_RTO_MASK | SBIMCL_STO_MASK), 0);
3832 + }
3833 + }
3834 +
3835 + sb_commit(sbh);
3836 +}
3837 +
3838 +/*
3839 + * Set the initiator timeout for the "master core".
3840 + * The master core is defined to be the core in control
3841 + * of the chip and so it issues accesses to non-memory
3842 + * locations (Because of dma *any* core can access memeory).
3843 + *
3844 + * The routine uses the bus to decide who is the master:
3845 + * SB_BUS => mips
3846 + * JTAG_BUS => chipc
3847 + * PCI_BUS => pci
3848 + *
3849 + * This routine exists so callers can disable initiator
3850 + * timeouts so accesses to very slow devices like otp
3851 + * won't cause an abort. The routine allows arbitrary
3852 + * settings of the service and request timeouts, though.
3853 + *
3854 + * Returns the timeout state before changing it or -1
3855 + * on error.
3856 + */
3857 +
3858 +#define TO_MASK (SBIMCL_RTO_MASK | SBIMCL_STO_MASK)
3859 +
3860 +uint32
3861 +sb_set_initiator_to(sb_t *sbh, uint32 to)
3862 +{
3863 + sb_info_t *si;
3864 + uint origidx, idx;
3865 + uint intr_val = 0;
3866 + uint32 tmp, ret = 0xffffffff;
3867 + sbconfig_t *sb;
3868 +
3869 + si = SB_INFO(sbh);
3870 +
3871 + if ((to & ~TO_MASK) != 0)
3872 + return ret;
3873 +
3874 + /* Figure out the master core */
3875 + idx = BADIDX;
3876 + switch (BUSTYPE(si->sb.bustype)) {
3877 + case PCI_BUS:
3878 + idx = si->sb.buscoreidx;
3879 + break;
3880 + case JTAG_BUS:
3881 + idx = SB_CC_IDX;
3882 + break;
3883 + case SB_BUS:
3884 + if ((idx = sb_findcoreidx(si, SB_MIPS33, 0)) == BADIDX)
3885 + idx = sb_findcoreidx(si, SB_MIPS, 0);
3886 + break;
3887 + default:
3888 + ASSERT(0);
3889 + }
3890 + if (idx == BADIDX)
3891 + return ret;
3892 +
3893 + INTR_OFF(si, intr_val);
3894 + origidx = sb_coreidx(sbh);
3895 +
3896 + sb = REGS2SB(sb_setcoreidx(sbh, idx));
3897 +
3898 + tmp = R_SBREG(si, &sb->sbimconfiglow);
3899 + ret = tmp & TO_MASK;
3900 + W_SBREG(si, &sb->sbimconfiglow, (tmp & ~TO_MASK) | to);
3901 +
3902 + sb_commit(sbh);
3903 + sb_setcoreidx(sbh, origidx);
3904 + INTR_RESTORE(si, intr_val);
3905 + return ret;
3906 +}
3907 +
3908 +void
3909 +sb_core_disable(sb_t *sbh, uint32 bits)
3910 +{
3911 + sb_info_t *si;
3912 + volatile uint32 dummy;
3913 + uint32 rej;
3914 + sbconfig_t *sb;
3915 +
3916 + si = SB_INFO(sbh);
3917 +
3918 + ASSERT(GOODREGS(si->curmap));
3919 + sb = REGS2SB(si->curmap);
3920 +
3921 + /* if core is already in reset, just return */
3922 + if (R_SBREG(si, &sb->sbtmstatelow) & SBTML_RESET)
3923 + return;
3924 +
3925 + /* reject value changed between sonics 2.2 and 2.3 */
3926 + if (si->sb.sonicsrev == SONICS_2_2)
3927 + rej = (1 << SBTML_REJ_SHIFT);
3928 + else
3929 + rej = (2 << SBTML_REJ_SHIFT);
3930 +
3931 + /* if clocks are not enabled, put into reset and return */
3932 + if ((R_SBREG(si, &sb->sbtmstatelow) & SBTML_CLK) == 0)
3933 + goto disable;
3934 +
3935 + /* set target reject and spin until busy is clear (preserve core-specific bits) */
3936 + OR_SBREG(si, &sb->sbtmstatelow, rej);
3937 + dummy = R_SBREG(si, &sb->sbtmstatelow);
3938 + OSL_DELAY(1);
3939 + SPINWAIT((R_SBREG(si, &sb->sbtmstatehigh) & SBTMH_BUSY), 100000);
3940 +
3941 + if (R_SBREG(si, &sb->sbidlow) & SBIDL_INIT) {
3942 + OR_SBREG(si, &sb->sbimstate, SBIM_RJ);
3943 + dummy = R_SBREG(si, &sb->sbimstate);
3944 + OSL_DELAY(1);
3945 + SPINWAIT((R_SBREG(si, &sb->sbimstate) & SBIM_BY), 100000);
3946 + }
3947 +
3948 + /* set reset and reject while enabling the clocks */
3949 + W_SBREG(si, &sb->sbtmstatelow, (bits | SBTML_FGC | SBTML_CLK | rej | SBTML_RESET));
3950 + dummy = R_SBREG(si, &sb->sbtmstatelow);
3951 + OSL_DELAY(10);
3952 +
3953 + /* don't forget to clear the initiator reject bit */
3954 + if (R_SBREG(si, &sb->sbidlow) & SBIDL_INIT)
3955 + AND_SBREG(si, &sb->sbimstate, ~SBIM_RJ);
3956 +
3957 +disable:
3958 + /* leave reset and reject asserted */
3959 + W_SBREG(si, &sb->sbtmstatelow, (bits | rej | SBTML_RESET));
3960 + OSL_DELAY(1);
3961 +}
3962 +
3963 +/* set chip watchdog reset timer to fire in 'ticks' backplane cycles */
3964 +void
3965 +sb_watchdog(sb_t *sbh, uint ticks)
3966 +{
3967 + sb_info_t *si = SB_INFO(sbh);
3968 +
3969 + /* instant NMI */
3970 + switch (si->gpioid) {
3971 + case SB_CC:
3972 + sb_corereg(si, 0, OFFSETOF(chipcregs_t, watchdog), ~0, ticks);
3973 + break;
3974 + case SB_EXTIF:
3975 + sb_corereg(si, si->gpioidx, OFFSETOF(extifregs_t, watchdog), ~0, ticks);
3976 + break;
3977 + }
3978 +}
3979 +
3980 +
3981 +/*
3982 + * Configure the pci core for pci client (NIC) action
3983 + * coremask is the bitvec of cores by index to be enabled.
3984 + */
3985 +void
3986 +sb_pci_setup(sb_t *sbh, uint coremask)
3987 +{
3988 + sb_info_t *si;
3989 + sbconfig_t *sb;
3990 + sbpciregs_t *pciregs;
3991 + uint32 sbflag;
3992 + uint32 w;
3993 + uint idx;
3994 +
3995 + si = SB_INFO(sbh);
3996 +
3997 + /* if not pci bus, we're done */
3998 + if (BUSTYPE(si->sb.bustype) != PCI_BUS)
3999 + return;
4000 +
4001 + ASSERT(PCI(si));
4002 + ASSERT(si->sb.buscoreidx != BADIDX);
4003 +
4004 + /* get current core index */
4005 + idx = si->curidx;
4006 +
4007 + /* we interrupt on this backplane flag number */
4008 + ASSERT(GOODREGS(si->curmap));
4009 + sb = REGS2SB(si->curmap);
4010 + sbflag = R_SBREG(si, &sb->sbtpsflag) & SBTPS_NUM0_MASK;
4011 +
4012 + /* switch over to pci core */
4013 + pciregs = (sbpciregs_t*) sb_setcoreidx(sbh, si->sb.buscoreidx);
4014 + sb = REGS2SB(pciregs);
4015 +
4016 + /*
4017 + * Enable sb->pci interrupts. Assume
4018 + * PCI rev 2.3 support was added in pci core rev 6 and things changed..
4019 + */
4020 + if ((PCI(si) && ((si->sb.buscorerev) >= 6))) {
4021 + /* pci config write to set this core bit in PCIIntMask */
4022 + w = OSL_PCI_READ_CONFIG(si->osh, PCI_INT_MASK, sizeof(uint32));
4023 + w |= (coremask << PCI_SBIM_SHIFT);
4024 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_INT_MASK, sizeof(uint32), w);
4025 + } else {
4026 + /* set sbintvec bit for our flag number */
4027 + OR_SBREG(si, &sb->sbintvec, (1 << sbflag));
4028 + }
4029 +
4030 + if (PCI(si)) {
4031 + OR_REG(&pciregs->sbtopci2, (SBTOPCI_PREF|SBTOPCI_BURST));
4032 + if (si->sb.buscorerev >= 11)
4033 + OR_REG(&pciregs->sbtopci2, SBTOPCI_RC_READMULTI);
4034 + if (si->sb.buscorerev < 5) {
4035 + SET_SBREG(si, &sb->sbimconfiglow, SBIMCL_RTO_MASK | SBIMCL_STO_MASK,
4036 + (0x3 << SBIMCL_RTO_SHIFT) | 0x2);
4037 + sb_commit(sbh);
4038 + }
4039 + }
4040 +
4041 + /* switch back to previous core */
4042 + sb_setcoreidx(sbh, idx);
4043 +}
4044 +
4045 +uint32
4046 +sb_base(uint32 admatch)
4047 +{
4048 + uint32 base;
4049 + uint type;
4050 +
4051 + type = admatch & SBAM_TYPE_MASK;
4052 + ASSERT(type < 3);
4053 +
4054 + base = 0;
4055 +
4056 + if (type == 0) {
4057 + base = admatch & SBAM_BASE0_MASK;
4058 + } else if (type == 1) {
4059 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
4060 + base = admatch & SBAM_BASE1_MASK;
4061 + } else if (type == 2) {
4062 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
4063 + base = admatch & SBAM_BASE2_MASK;
4064 + }
4065 +
4066 + return (base);
4067 +}
4068 +
4069 +uint32
4070 +sb_size(uint32 admatch)
4071 +{
4072 + uint32 size;
4073 + uint type;
4074 +
4075 + type = admatch & SBAM_TYPE_MASK;
4076 + ASSERT(type < 3);
4077 +
4078 + size = 0;
4079 +
4080 + if (type == 0) {
4081 + size = 1 << (((admatch & SBAM_ADINT0_MASK) >> SBAM_ADINT0_SHIFT) + 1);
4082 + } else if (type == 1) {
4083 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
4084 + size = 1 << (((admatch & SBAM_ADINT1_MASK) >> SBAM_ADINT1_SHIFT) + 1);
4085 + } else if (type == 2) {
4086 + ASSERT(!(admatch & SBAM_ADNEG)); /* neg not supported */
4087 + size = 1 << (((admatch & SBAM_ADINT2_MASK) >> SBAM_ADINT2_SHIFT) + 1);
4088 + }
4089 +
4090 + return (size);
4091 +}
4092 +
4093 +/* return the core-type instantiation # of the current core */
4094 +uint
4095 +sb_coreunit(sb_t *sbh)
4096 +{
4097 + sb_info_t *si;
4098 + uint idx;
4099 + uint coreid;
4100 + uint coreunit;
4101 + uint i;
4102 +
4103 + si = SB_INFO(sbh);
4104 + coreunit = 0;
4105 +
4106 + idx = si->curidx;
4107 +
4108 + ASSERT(GOODREGS(si->curmap));
4109 + coreid = sb_coreid(sbh);
4110 +
4111 + /* count the cores of our type */
4112 + for (i = 0; i < idx; i++)
4113 + if (si->coreid[i] == coreid)
4114 + coreunit++;
4115 +
4116 + return (coreunit);
4117 +}
4118 +
4119 +static INLINE uint32
4120 +factor6(uint32 x)
4121 +{
4122 + switch (x) {
4123 + case CC_F6_2: return 2;
4124 + case CC_F6_3: return 3;
4125 + case CC_F6_4: return 4;
4126 + case CC_F6_5: return 5;
4127 + case CC_F6_6: return 6;
4128 + case CC_F6_7: return 7;
4129 + default: return 0;
4130 + }
4131 +}
4132 +
4133 +/* calculate the speed the SB would run at given a set of clockcontrol values */
4134 +uint32
4135 +sb_clock_rate(uint32 pll_type, uint32 n, uint32 m)
4136 +{
4137 + uint32 n1, n2, clock, m1, m2, m3, mc;
4138 +
4139 + n1 = n & CN_N1_MASK;
4140 + n2 = (n & CN_N2_MASK) >> CN_N2_SHIFT;
4141 +
4142 + if (pll_type == PLL_TYPE6) {
4143 + if (m & CC_T6_MMASK)
4144 + return CC_T6_M1;
4145 + else
4146 + return CC_T6_M0;
4147 + } else if ((pll_type == PLL_TYPE1) ||
4148 + (pll_type == PLL_TYPE3) ||
4149 + (pll_type == PLL_TYPE4) ||
4150 + (pll_type == PLL_TYPE7)) {
4151 + n1 = factor6(n1);
4152 + n2 += CC_F5_BIAS;
4153 + } else if (pll_type == PLL_TYPE2) {
4154 + n1 += CC_T2_BIAS;
4155 + n2 += CC_T2_BIAS;
4156 + ASSERT((n1 >= 2) && (n1 <= 7));
4157 + ASSERT((n2 >= 5) && (n2 <= 23));
4158 + } else if (pll_type == PLL_TYPE5) {
4159 + return (100000000);
4160 + } else
4161 + ASSERT(0);
4162 + /* PLL types 3 and 7 use BASE2 (25Mhz) */
4163 + if ((pll_type == PLL_TYPE3) ||
4164 + (pll_type == PLL_TYPE7)) {
4165 + clock = CC_CLOCK_BASE2 * n1 * n2;
4166 + }
4167 + else
4168 + clock = CC_CLOCK_BASE1 * n1 * n2;
4169 +
4170 + if (clock == 0)
4171 + return 0;
4172 +
4173 + m1 = m & CC_M1_MASK;
4174 + m2 = (m & CC_M2_MASK) >> CC_M2_SHIFT;
4175 + m3 = (m & CC_M3_MASK) >> CC_M3_SHIFT;
4176 + mc = (m & CC_MC_MASK) >> CC_MC_SHIFT;
4177 +
4178 + if ((pll_type == PLL_TYPE1) ||
4179 + (pll_type == PLL_TYPE3) ||
4180 + (pll_type == PLL_TYPE4) ||
4181 + (pll_type == PLL_TYPE7)) {
4182 + m1 = factor6(m1);
4183 + if ((pll_type == PLL_TYPE1) || (pll_type == PLL_TYPE3))
4184 + m2 += CC_F5_BIAS;
4185 + else
4186 + m2 = factor6(m2);
4187 + m3 = factor6(m3);
4188 +
4189 + switch (mc) {
4190 + case CC_MC_BYPASS: return (clock);
4191 + case CC_MC_M1: return (clock / m1);
4192 + case CC_MC_M1M2: return (clock / (m1 * m2));
4193 + case CC_MC_M1M2M3: return (clock / (m1 * m2 * m3));
4194 + case CC_MC_M1M3: return (clock / (m1 * m3));
4195 + default: return (0);
4196 + }
4197 + } else {
4198 + ASSERT(pll_type == PLL_TYPE2);
4199 +
4200 + m1 += CC_T2_BIAS;
4201 + m2 += CC_T2M2_BIAS;
4202 + m3 += CC_T2_BIAS;
4203 + ASSERT((m1 >= 2) && (m1 <= 7));
4204 + ASSERT((m2 >= 3) && (m2 <= 10));
4205 + ASSERT((m3 >= 2) && (m3 <= 7));
4206 +
4207 + if ((mc & CC_T2MC_M1BYP) == 0)
4208 + clock /= m1;
4209 + if ((mc & CC_T2MC_M2BYP) == 0)
4210 + clock /= m2;
4211 + if ((mc & CC_T2MC_M3BYP) == 0)
4212 + clock /= m3;
4213 +
4214 + return(clock);
4215 + }
4216 +}
4217 +
4218 +/* returns the current speed the SB is running at */
4219 +uint32
4220 +sb_clock(sb_t *sbh)
4221 +{
4222 + sb_info_t *si;
4223 + extifregs_t *eir;
4224 + chipcregs_t *cc;
4225 + uint32 n, m;
4226 + uint idx;
4227 + uint32 pll_type, rate;
4228 + uint intr_val = 0;
4229 +
4230 + si = SB_INFO(sbh);
4231 + idx = si->curidx;
4232 + pll_type = PLL_TYPE1;
4233 +
4234 + INTR_OFF(si, intr_val);
4235 +
4236 + /* switch to extif or chipc core */
4237 + if ((eir = (extifregs_t *) sb_setcore(sbh, SB_EXTIF, 0))) {
4238 + n = R_REG(&eir->clockcontrol_n);
4239 + m = R_REG(&eir->clockcontrol_sb);
4240 + } else if ((cc = (chipcregs_t *) sb_setcore(sbh, SB_CC, 0))) {
4241 + pll_type = R_REG(&cc->capabilities) & CAP_PLL_MASK;
4242 + n = R_REG(&cc->clockcontrol_n);
4243 + if (pll_type == PLL_TYPE6)
4244 + m = R_REG(&cc->clockcontrol_mips);
4245 + else if (pll_type == PLL_TYPE3)
4246 + {
4247 + // Added by Chen-I for 5365
4248 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID)
4249 + m = R_REG(&cc->clockcontrol_sb);
4250 + else
4251 + m = R_REG(&cc->clockcontrol_m2);
4252 + }
4253 + else
4254 + m = R_REG(&cc->clockcontrol_sb);
4255 + } else {
4256 + INTR_RESTORE(si, intr_val);
4257 + return 0;
4258 + }
4259 +
4260 + // Added by Chen-I for 5365
4261 + if (BCMINIT(sb_chip)(sbh) == BCM5365_DEVICE_ID)
4262 + {
4263 + rate = 100000000;
4264 + }
4265 + else
4266 + {
4267 + /* calculate rate */
4268 + rate = sb_clock_rate(pll_type, n, m);
4269 + if (pll_type == PLL_TYPE3)
4270 + rate = rate / 2;
4271 + }
4272 +
4273 + /* switch back to previous core */
4274 + sb_setcoreidx(sbh, idx);
4275 +
4276 + INTR_RESTORE(si, intr_val);
4277 +
4278 + return rate;
4279 +}
4280 +
4281 +/* change logical "focus" to the gpio core for optimized access */
4282 +void*
4283 +sb_gpiosetcore(sb_t *sbh)
4284 +{
4285 + sb_info_t *si;
4286 +
4287 + si = SB_INFO(sbh);
4288 +
4289 + return (sb_setcoreidx(sbh, si->gpioidx));
4290 +}
4291 +
4292 +/* mask&set gpiocontrol bits */
4293 +uint32
4294 +sb_gpiocontrol(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
4295 +{
4296 + sb_info_t *si;
4297 + uint regoff;
4298 +
4299 + si = SB_INFO(sbh);
4300 + regoff = 0;
4301 +
4302 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
4303 +
4304 + /* gpios could be shared on router platforms */
4305 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
4306 + mask = priority ? (sb_gpioreservation & mask) :
4307 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
4308 + val &= mask;
4309 + }
4310 +
4311 + switch (si->gpioid) {
4312 + case SB_CC:
4313 + regoff = OFFSETOF(chipcregs_t, gpiocontrol);
4314 + break;
4315 +
4316 + case SB_PCI:
4317 + regoff = OFFSETOF(sbpciregs_t, gpiocontrol);
4318 + break;
4319 +
4320 + case SB_EXTIF:
4321 + return (0);
4322 + }
4323 +
4324 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
4325 +}
4326 +
4327 +/* mask&set gpio output enable bits */
4328 +uint32
4329 +sb_gpioouten(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
4330 +{
4331 + sb_info_t *si;
4332 + uint regoff;
4333 +
4334 + si = SB_INFO(sbh);
4335 + regoff = 0;
4336 +
4337 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
4338 +
4339 + /* gpios could be shared on router platforms */
4340 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
4341 + mask = priority ? (sb_gpioreservation & mask) :
4342 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
4343 + val &= mask;
4344 + }
4345 +
4346 + switch (si->gpioid) {
4347 + case SB_CC:
4348 + regoff = OFFSETOF(chipcregs_t, gpioouten);
4349 + break;
4350 +
4351 + case SB_PCI:
4352 + regoff = OFFSETOF(sbpciregs_t, gpioouten);
4353 + break;
4354 +
4355 + case SB_EXTIF:
4356 + regoff = OFFSETOF(extifregs_t, gpio[0].outen);
4357 + break;
4358 + }
4359 +
4360 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
4361 +}
4362 +
4363 +/* mask&set gpio output bits */
4364 +uint32
4365 +sb_gpioout(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
4366 +{
4367 + sb_info_t *si;
4368 + uint regoff;
4369 +
4370 + si = SB_INFO(sbh);
4371 + regoff = 0;
4372 +
4373 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
4374 +
4375 + /* gpios could be shared on router platforms */
4376 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
4377 + mask = priority ? (sb_gpioreservation & mask) :
4378 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
4379 + val &= mask;
4380 + }
4381 +
4382 + switch (si->gpioid) {
4383 + case SB_CC:
4384 + regoff = OFFSETOF(chipcregs_t, gpioout);
4385 + break;
4386 +
4387 + case SB_PCI:
4388 + regoff = OFFSETOF(sbpciregs_t, gpioout);
4389 + break;
4390 +
4391 + case SB_EXTIF:
4392 + regoff = OFFSETOF(extifregs_t, gpio[0].out);
4393 + break;
4394 + }
4395 +
4396 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
4397 +}
4398 +
4399 +/* reserve one gpio */
4400 +uint32
4401 +sb_gpioreserve(sb_t *sbh, uint32 gpio_bitmask, uint8 priority)
4402 +{
4403 + sb_info_t *si;
4404 +
4405 + si = SB_INFO(sbh);
4406 +
4407 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
4408 +
4409 + /* only cores on SB_BUS share GPIO's and only applcation users need to reserve/release GPIO */
4410 + if ( (BUSTYPE(si->sb.bustype) != SB_BUS) || (!priority)) {
4411 + ASSERT((BUSTYPE(si->sb.bustype) == SB_BUS) && (priority));
4412 + return -1;
4413 + }
4414 + /* make sure only one bit is set */
4415 + if ((!gpio_bitmask) || ((gpio_bitmask) & (gpio_bitmask - 1))) {
4416 + ASSERT((gpio_bitmask) && !((gpio_bitmask) & (gpio_bitmask - 1)));
4417 + return -1;
4418 + }
4419 +
4420 + /* already reserved */
4421 + if (sb_gpioreservation & gpio_bitmask)
4422 + return -1;
4423 + /* set reservation */
4424 + sb_gpioreservation |= gpio_bitmask;
4425 +
4426 + return sb_gpioreservation;
4427 +}
4428 +
4429 +/* release one gpio */
4430 +/*
4431 + * releasing the gpio doesn't change the current value on the GPIO last write value
4432 + * persists till some one overwrites it
4433 +*/
4434 +
4435 +uint32
4436 +sb_gpiorelease(sb_t *sbh, uint32 gpio_bitmask, uint8 priority)
4437 +{
4438 + sb_info_t *si;
4439 +
4440 + si = SB_INFO(sbh);
4441 +
4442 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
4443 +
4444 + /* only cores on SB_BUS share GPIO's and only applcation users need to reserve/release GPIO */
4445 + if ( (BUSTYPE(si->sb.bustype) != SB_BUS) || (!priority)) {
4446 + ASSERT((BUSTYPE(si->sb.bustype) == SB_BUS) && (priority));
4447 + return -1;
4448 + }
4449 + /* make sure only one bit is set */
4450 + if ((!gpio_bitmask) || ((gpio_bitmask) & (gpio_bitmask - 1))) {
4451 + ASSERT((gpio_bitmask) && !((gpio_bitmask) & (gpio_bitmask - 1)));
4452 + return -1;
4453 + }
4454 +
4455 + /* already released */
4456 + if (!(sb_gpioreservation & gpio_bitmask))
4457 + return -1;
4458 +
4459 + /* clear reservation */
4460 + sb_gpioreservation &= ~gpio_bitmask;
4461 +
4462 + return sb_gpioreservation;
4463 +}
4464 +
4465 +/* return the current gpioin register value */
4466 +uint32
4467 +sb_gpioin(sb_t *sbh)
4468 +{
4469 + sb_info_t *si;
4470 + uint regoff;
4471 +
4472 + si = SB_INFO(sbh);
4473 + regoff = 0;
4474 +
4475 + switch (si->gpioid) {
4476 + case SB_CC:
4477 + regoff = OFFSETOF(chipcregs_t, gpioin);
4478 + break;
4479 +
4480 + case SB_PCI:
4481 + regoff = OFFSETOF(sbpciregs_t, gpioin);
4482 + break;
4483 +
4484 + case SB_EXTIF:
4485 + regoff = OFFSETOF(extifregs_t, gpioin);
4486 + break;
4487 + }
4488 +
4489 + return (sb_corereg(si, si->gpioidx, regoff, 0, 0));
4490 +}
4491 +
4492 +/* mask&set gpio interrupt polarity bits */
4493 +uint32
4494 +sb_gpiointpolarity(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
4495 +{
4496 + sb_info_t *si;
4497 + uint regoff;
4498 +
4499 + si = SB_INFO(sbh);
4500 + regoff = 0;
4501 +
4502 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
4503 +
4504 + /* gpios could be shared on router platforms */
4505 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
4506 + mask = priority ? (sb_gpioreservation & mask) :
4507 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
4508 + val &= mask;
4509 + }
4510 +
4511 + switch (si->gpioid) {
4512 + case SB_CC:
4513 + regoff = OFFSETOF(chipcregs_t, gpiointpolarity);
4514 + break;
4515 +
4516 + case SB_PCI:
4517 + /* pci gpio implementation does not support interrupt polarity */
4518 + ASSERT(0);
4519 + break;
4520 +
4521 + case SB_EXTIF:
4522 + regoff = OFFSETOF(extifregs_t, gpiointpolarity);
4523 + break;
4524 + }
4525 +
4526 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
4527 +}
4528 +
4529 +/* mask&set gpio interrupt mask bits */
4530 +uint32
4531 +sb_gpiointmask(sb_t *sbh, uint32 mask, uint32 val, uint8 priority)
4532 +{
4533 + sb_info_t *si;
4534 + uint regoff;
4535 +
4536 + si = SB_INFO(sbh);
4537 + regoff = 0;
4538 +
4539 + priority = GPIO_DRV_PRIORITY; /* compatibility hack */
4540 +
4541 + /* gpios could be shared on router platforms */
4542 + if ((BUSTYPE(si->sb.bustype) == SB_BUS) && (val || mask)) {
4543 + mask = priority ? (sb_gpioreservation & mask) :
4544 + ((sb_gpioreservation | mask) & ~(sb_gpioreservation));
4545 + val &= mask;
4546 + }
4547 +
4548 + switch (si->gpioid) {
4549 + case SB_CC:
4550 + regoff = OFFSETOF(chipcregs_t, gpiointmask);
4551 + break;
4552 +
4553 + case SB_PCI:
4554 + /* pci gpio implementation does not support interrupt mask */
4555 + ASSERT(0);
4556 + break;
4557 +
4558 + case SB_EXTIF:
4559 + regoff = OFFSETOF(extifregs_t, gpiointmask);
4560 + break;
4561 + }
4562 +
4563 + return (sb_corereg(si, si->gpioidx, regoff, mask, val));
4564 +}
4565 +
4566 +/* assign the gpio to an led */
4567 +uint32
4568 +sb_gpioled(sb_t *sbh, uint32 mask, uint32 val)
4569 +{
4570 + sb_info_t *si;
4571 +
4572 + si = SB_INFO(sbh);
4573 + if (si->sb.ccrev < 16)
4574 + return -1;
4575 +
4576 + /* gpio led powersave reg */
4577 + return(sb_corereg(si, 0, OFFSETOF(chipcregs_t, gpiotimeroutmask), mask, val));
4578 +}
4579 +
4580 +/* mask&set gpio timer val */
4581 +uint32
4582 +sb_gpiotimerval(sb_t *sbh, uint32 mask, uint32 gpiotimerval)
4583 +{
4584 + sb_info_t *si;
4585 + si = SB_INFO(sbh);
4586 +
4587 + if (si->sb.ccrev < 16)
4588 + return -1;
4589 +
4590 + return(sb_corereg(si, 0, OFFSETOF(chipcregs_t, gpiotimerval), mask, gpiotimerval));
4591 +}
4592 +
4593 +
4594 +/* return the slow clock source - LPO, XTAL, or PCI */
4595 +static uint
4596 +sb_slowclk_src(sb_info_t *si)
4597 +{
4598 + chipcregs_t *cc;
4599 +
4600 +
4601 + ASSERT(sb_coreid(&si->sb) == SB_CC);
4602 +
4603 + if (si->sb.ccrev < 6) {
4604 + if ((BUSTYPE(si->sb.bustype) == PCI_BUS)
4605 + && (OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32)) & PCI_CFG_GPIO_SCS))
4606 + return (SCC_SS_PCI);
4607 + else
4608 + return (SCC_SS_XTAL);
4609 + } else if (si->sb.ccrev < 10) {
4610 + cc = (chipcregs_t*) sb_setcoreidx(&si->sb, si->curidx);
4611 + return (R_REG(&cc->slow_clk_ctl) & SCC_SS_MASK);
4612 + } else /* Insta-clock */
4613 + return (SCC_SS_XTAL);
4614 +}
4615 +
4616 +/* return the ILP (slowclock) min or max frequency */
4617 +static uint
4618 +sb_slowclk_freq(sb_info_t *si, bool max)
4619 +{
4620 + chipcregs_t *cc;
4621 + uint32 slowclk;
4622 + uint div;
4623 +
4624 +
4625 + ASSERT(sb_coreid(&si->sb) == SB_CC);
4626 +
4627 + cc = (chipcregs_t*) sb_setcoreidx(&si->sb, si->curidx);
4628 +
4629 + /* shouldn't be here unless we've established the chip has dynamic clk control */
4630 + ASSERT(R_REG(&cc->capabilities) & CAP_PWR_CTL);
4631 +
4632 + slowclk = sb_slowclk_src(si);
4633 + if (si->sb.ccrev < 6) {
4634 + if (slowclk == SCC_SS_PCI)
4635 + return (max? (PCIMAXFREQ/64) : (PCIMINFREQ/64));
4636 + else
4637 + return (max? (XTALMAXFREQ/32) : (XTALMINFREQ/32));
4638 + } else if (si->sb.ccrev < 10) {
4639 + div = 4 * (((R_REG(&cc->slow_clk_ctl) & SCC_CD_MASK) >> SCC_CD_SHIFT) + 1);
4640 + if (slowclk == SCC_SS_LPO)
4641 + return (max? LPOMAXFREQ : LPOMINFREQ);
4642 + else if (slowclk == SCC_SS_XTAL)
4643 + return (max? (XTALMAXFREQ/div) : (XTALMINFREQ/div));
4644 + else if (slowclk == SCC_SS_PCI)
4645 + return (max? (PCIMAXFREQ/div) : (PCIMINFREQ/div));
4646 + else
4647 + ASSERT(0);
4648 + } else {
4649 + /* Chipc rev 10 is InstaClock */
4650 + div = R_REG(&cc->system_clk_ctl) >> SYCC_CD_SHIFT;
4651 + div = 4 * (div + 1);
4652 + return (max ? XTALMAXFREQ : (XTALMINFREQ/div));
4653 + }
4654 + return (0);
4655 +}
4656 +
4657 +static void
4658 +sb_clkctl_setdelay(sb_info_t *si, void *chipcregs)
4659 +{
4660 + chipcregs_t * cc;
4661 + uint slowmaxfreq, pll_delay, slowclk;
4662 + uint pll_on_delay, fref_sel_delay;
4663 +
4664 + pll_delay = PLL_DELAY;
4665 +
4666 + /* If the slow clock is not sourced by the xtal then add the xtal_on_delay
4667 + * since the xtal will also be powered down by dynamic clk control logic.
4668 + */
4669 + slowclk = sb_slowclk_src(si);
4670 + if (slowclk != SCC_SS_XTAL)
4671 + pll_delay += XTAL_ON_DELAY;
4672 +
4673 + /* Starting with 4318 it is ILP that is used for the delays */
4674 + slowmaxfreq = sb_slowclk_freq(si, (si->sb.ccrev >= 10) ? FALSE : TRUE);
4675 +
4676 + pll_on_delay = ((slowmaxfreq * pll_delay) + 999999) / 1000000;
4677 + fref_sel_delay = ((slowmaxfreq * FREF_DELAY) + 999999) / 1000000;
4678 +
4679 + cc = (chipcregs_t *)chipcregs;
4680 + W_REG(&cc->pll_on_delay, pll_on_delay);
4681 + W_REG(&cc->fref_sel_delay, fref_sel_delay);
4682 +}
4683 +
4684 +int
4685 +sb_pwrctl_slowclk(void *sbh, bool set, uint *div)
4686 +{
4687 + sb_info_t *si;
4688 + uint origidx;
4689 + chipcregs_t *cc;
4690 + uint intr_val = 0;
4691 + uint err = 0;
4692 +
4693 + si = SB_INFO(sbh);
4694 +
4695 + /* chipcommon cores prior to rev6 don't support slowclkcontrol */
4696 + if (si->sb.ccrev < 6)
4697 + return 1;
4698 +
4699 + /* chipcommon cores rev10 are a whole new ball game */
4700 + if (si->sb.ccrev >= 10)
4701 + return 1;
4702 +
4703 + if (set && ((*div % 4) || (*div < 4)))
4704 + return 2;
4705 +
4706 + INTR_OFF(si, intr_val);
4707 + origidx = si->curidx;
4708 + cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0);
4709 + ASSERT(cc != NULL);
4710 +
4711 + if (!(R_REG(&cc->capabilities) & CAP_PWR_CTL)) {
4712 + err = 3;
4713 + goto done;
4714 + }
4715 +
4716 + if (set) {
4717 + SET_REG(&cc->slow_clk_ctl, SCC_CD_MASK, ((*div / 4 - 1) << SCC_CD_SHIFT));
4718 + sb_clkctl_setdelay(sbh, (void *)cc);
4719 + } else
4720 + *div = 4 * (((R_REG(&cc->slow_clk_ctl) & SCC_CD_MASK) >> SCC_CD_SHIFT) + 1);
4721 +
4722 +done:
4723 + sb_setcoreidx(sbh, origidx);
4724 + INTR_RESTORE(si, intr_val);
4725 + return err;
4726 +}
4727 +
4728 +/* initialize power control delay registers */
4729 +void sb_clkctl_init(sb_t *sbh)
4730 +{
4731 + sb_info_t *si;
4732 + uint origidx;
4733 + chipcregs_t *cc;
4734 +
4735 + si = SB_INFO(sbh);
4736 +
4737 + origidx = si->curidx;
4738 +
4739 + if ((cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0)) == NULL)
4740 + return;
4741 +
4742 + if (!(R_REG(&cc->capabilities) & CAP_PWR_CTL))
4743 + goto done;
4744 +
4745 + /* set all Instaclk chip ILP to 1 MHz */
4746 + if (si->sb.ccrev >= 10)
4747 + SET_REG(&cc->system_clk_ctl, SYCC_CD_MASK, (ILP_DIV_1MHZ << SYCC_CD_SHIFT));
4748 +
4749 + sb_clkctl_setdelay(si, (void *)cc);
4750 +
4751 +done:
4752 + sb_setcoreidx(sbh, origidx);
4753 +}
4754 +void sb_pwrctl_init(sb_t *sbh)
4755 +{
4756 +sb_clkctl_init(sbh);
4757 +}
4758 +/* return the value suitable for writing to the dot11 core FAST_PWRUP_DELAY register */
4759 +uint16
4760 +sb_clkctl_fast_pwrup_delay(sb_t *sbh)
4761 +{
4762 + sb_info_t *si;
4763 + uint origidx;
4764 + chipcregs_t *cc;
4765 + uint slowminfreq;
4766 + uint16 fpdelay;
4767 + uint intr_val = 0;
4768 +
4769 + si = SB_INFO(sbh);
4770 + fpdelay = 0;
4771 + origidx = si->curidx;
4772 +
4773 + INTR_OFF(si, intr_val);
4774 +
4775 + if ((cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0)) == NULL)
4776 + goto done;
4777 +
4778 + if (!(R_REG(&cc->capabilities) & CAP_PWR_CTL))
4779 + goto done;
4780 +
4781 + slowminfreq = sb_slowclk_freq(si, FALSE);
4782 + fpdelay = (((R_REG(&cc->pll_on_delay) + 2) * 1000000) + (slowminfreq - 1)) / slowminfreq;
4783 +
4784 +done:
4785 + sb_setcoreidx(sbh, origidx);
4786 + INTR_RESTORE(si, intr_val);
4787 + return (fpdelay);
4788 +}
4789 +uint16 sb_pwrctl_fast_pwrup_delay(sb_t *sbh)
4790 +{
4791 +return sb_clkctl_fast_pwrup_delay(sbh);
4792 +}
4793 +/* turn primary xtal and/or pll off/on */
4794 +int
4795 +sb_clkctl_xtal(sb_t *sbh, uint what, bool on)
4796 +{
4797 + sb_info_t *si;
4798 + uint32 in, out, outen;
4799 +
4800 + si = SB_INFO(sbh);
4801 +
4802 + switch (BUSTYPE(si->sb.bustype)) {
4803 + case PCI_BUS:
4804 +
4805 + in = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_IN, sizeof (uint32));
4806 + out = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32));
4807 + outen = OSL_PCI_READ_CONFIG(si->osh, PCI_GPIO_OUTEN, sizeof (uint32));
4808 +
4809 + /*
4810 + * Avoid glitching the clock if GPRS is already using it.
4811 + * We can't actually read the state of the PLLPD so we infer it
4812 + * by the value of XTAL_PU which *is* readable via gpioin.
4813 + */
4814 + if (on && (in & PCI_CFG_GPIO_XTAL))
4815 + return (0);
4816 +
4817 + if (what & XTAL)
4818 + outen |= PCI_CFG_GPIO_XTAL;
4819 + if (what & PLL)
4820 + outen |= PCI_CFG_GPIO_PLL;
4821 +
4822 + if (on) {
4823 + /* turn primary xtal on */
4824 + if (what & XTAL) {
4825 + out |= PCI_CFG_GPIO_XTAL;
4826 + if (what & PLL)
4827 + out |= PCI_CFG_GPIO_PLL;
4828 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32), out);
4829 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUTEN, sizeof (uint32), outen);
4830 + OSL_DELAY(XTAL_ON_DELAY);
4831 + }
4832 +
4833 + /* turn pll on */
4834 + if (what & PLL) {
4835 + out &= ~PCI_CFG_GPIO_PLL;
4836 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32), out);
4837 + OSL_DELAY(2000);
4838 + }
4839 + } else {
4840 + if (what & XTAL)
4841 + out &= ~PCI_CFG_GPIO_XTAL;
4842 + if (what & PLL)
4843 + out |= PCI_CFG_GPIO_PLL;
4844 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUT, sizeof (uint32), out);
4845 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_GPIO_OUTEN, sizeof (uint32), outen);
4846 + }
4847 +
4848 + default:
4849 + return (-1);
4850 + }
4851 +
4852 + return (0);
4853 +}
4854 +
4855 +int sb_pwrctl_xtal(sb_t *sbh, uint what, bool on)
4856 +{
4857 +return sb_clkctl_xtal(sbh,what,on);
4858 +}
4859 +
4860 +/* set dynamic clk control mode (forceslow, forcefast, dynamic) */
4861 +/* returns true if ignore pll off is set and false if it is not */
4862 +bool
4863 +sb_clkctl_clk(sb_t *sbh, uint mode)
4864 +{
4865 + sb_info_t *si;
4866 + uint origidx;
4867 + chipcregs_t *cc;
4868 + uint32 scc;
4869 + bool forcefastclk=FALSE;
4870 + uint intr_val = 0;
4871 +
4872 + si = SB_INFO(sbh);
4873 +
4874 + /* chipcommon cores prior to rev6 don't support dynamic clock control */
4875 + if (si->sb.ccrev < 6)
4876 + return (FALSE);
4877 +
4878 + /* chipcommon cores rev10 are a whole new ball game */
4879 + if (si->sb.ccrev >= 10)
4880 + return (FALSE);
4881 +
4882 + INTR_OFF(si, intr_val);
4883 +
4884 + origidx = si->curidx;
4885 +
4886 + cc = (chipcregs_t*) sb_setcore(sbh, SB_CC, 0);
4887 + ASSERT(cc != NULL);
4888 +
4889 + if (!(R_REG(&cc->capabilities) & CAP_PWR_CTL))
4890 + goto done;
4891 +
4892 + switch (mode) {
4893 + case CLK_FAST: /* force fast (pll) clock */
4894 + /* don't forget to force xtal back on before we clear SCC_DYN_XTAL.. */
4895 + sb_clkctl_xtal(&si->sb, XTAL, ON);
4896 +
4897 + SET_REG(&cc->slow_clk_ctl, (SCC_XC | SCC_FS | SCC_IP), SCC_IP);
4898 + break;
4899 +
4900 + case CLK_DYNAMIC: /* enable dynamic clock control */
4901 + scc = R_REG(&cc->slow_clk_ctl);
4902 + scc &= ~(SCC_FS | SCC_IP | SCC_XC);
4903 + if ((scc & SCC_SS_MASK) != SCC_SS_XTAL)
4904 + scc |= SCC_XC;
4905 + W_REG(&cc->slow_clk_ctl, scc);
4906 +
4907 + /* for dynamic control, we have to release our xtal_pu "force on" */
4908 + if (scc & SCC_XC)
4909 + sb_clkctl_xtal(&si->sb, XTAL, OFF);
4910 + break;
4911 +
4912 + default:
4913 + ASSERT(0);
4914 + }
4915 +
4916 + /* Is the h/w forcing the use of the fast clk */
4917 + forcefastclk = (bool)((R_REG(&cc->slow_clk_ctl) & SCC_IP) == SCC_IP);
4918 +
4919 +done:
4920 + sb_setcoreidx(sbh, origidx);
4921 + INTR_RESTORE(si, intr_val);
4922 + return (forcefastclk);
4923 +}
4924 +
4925 +bool sb_pwrctl_clk(sb_t *sbh, uint mode)
4926 +{
4927 +return sb_clkctl_clk(sbh, mode);
4928 +}
4929 +/* register driver interrupt disabling and restoring callback functions */
4930 +void
4931 +sb_register_intr_callback(sb_t *sbh, void *intrsoff_fn, void *intrsrestore_fn, void *intrsenabled_fn, void *intr_arg)
4932 +{
4933 + sb_info_t *si;
4934 +
4935 + si = SB_INFO(sbh);
4936 + si->intr_arg = intr_arg;
4937 + si->intrsoff_fn = (sb_intrsoff_t)intrsoff_fn;
4938 + si->intrsrestore_fn = (sb_intrsrestore_t)intrsrestore_fn;
4939 + si->intrsenabled_fn = (sb_intrsenabled_t)intrsenabled_fn;
4940 + /* save current core id. when this function called, the current core
4941 + * must be the core which provides driver functions(il, et, wl, etc.)
4942 + */
4943 + si->dev_coreid = si->coreid[si->curidx];
4944 +}
4945 +
4946 +
4947 +void
4948 +sb_corepciid(sb_t *sbh, uint16 *pcivendor, uint16 *pcidevice,
4949 + uint8 *pciclass, uint8 *pcisubclass, uint8 *pciprogif)
4950 +{
4951 + uint vendor, core, unit;
4952 + uint chip, chippkg;
4953 + char varname[8];
4954 + uint8 class, subclass, progif;
4955 +
4956 + vendor = sb_corevendor(sbh);
4957 + core = sb_coreid(sbh);
4958 + unit = sb_coreunit(sbh);
4959 +
4960 + chip = BCMINIT(sb_chip)(sbh);
4961 + chippkg = BCMINIT(sb_chippkg)(sbh);
4962 +
4963 + progif = 0;
4964 +
4965 + /* Known vendor translations */
4966 + switch (vendor) {
4967 + case SB_VEND_BCM:
4968 + vendor = VENDOR_BROADCOM;
4969 + break;
4970 + }
4971 +
4972 + /* Determine class based on known core codes */
4973 + switch (core) {
4974 + case SB_ILINE20:
4975 + class = PCI_CLASS_NET;
4976 + subclass = PCI_NET_ETHER;
4977 + core = BCM47XX_ILINE_ID;
4978 + break;
4979 + case SB_ENET:
4980 + class = PCI_CLASS_NET;
4981 + subclass = PCI_NET_ETHER;
4982 + core = BCM47XX_ENET_ID;
4983 + break;
4984 + case SB_SDRAM:
4985 + case SB_MEMC:
4986 + class = PCI_CLASS_MEMORY;
4987 + subclass = PCI_MEMORY_RAM;
4988 + break;
4989 + case SB_PCI:
4990 + class = PCI_CLASS_BRIDGE;
4991 + subclass = PCI_BRIDGE_PCI;
4992 + break;
4993 + case SB_MIPS:
4994 + case SB_MIPS33:
4995 + class = PCI_CLASS_CPU;
4996 + subclass = PCI_CPU_MIPS;
4997 + break;
4998 + case SB_CODEC:
4999 + class = PCI_CLASS_COMM;
5000 + subclass = PCI_COMM_MODEM;
5001 + core = BCM47XX_V90_ID;
5002 + break;
5003 + case SB_USB:
5004 + class = PCI_CLASS_SERIAL;
5005 + subclass = PCI_SERIAL_USB;
5006 + progif = 0x10; /* OHCI */
5007 + core = BCM47XX_USB_ID;
5008 + break;
5009 + case SB_USB11H:
5010 + class = PCI_CLASS_SERIAL;
5011 + subclass = PCI_SERIAL_USB;
5012 + progif = 0x10; /* OHCI */
5013 + core = BCM47XX_USBH_ID;
5014 + break;
5015 + case SB_USB11D:
5016 + class = PCI_CLASS_SERIAL;
5017 + subclass = PCI_SERIAL_USB;
5018 + core = BCM47XX_USBD_ID;
5019 + break;
5020 + case SB_IPSEC:
5021 + class = PCI_CLASS_CRYPT;
5022 + subclass = PCI_CRYPT_NETWORK;
5023 + core = BCM47XX_IPSEC_ID;
5024 + break;
5025 + case SB_ROBO:
5026 + class = PCI_CLASS_NET;
5027 + subclass = PCI_NET_OTHER;
5028 + core = BCM47XX_ROBO_ID;
5029 + break;
5030 + case SB_EXTIF:
5031 + case SB_CC:
5032 + class = PCI_CLASS_MEMORY;
5033 + subclass = PCI_MEMORY_FLASH;
5034 + break;
5035 + case SB_D11:
5036 + class = PCI_CLASS_NET;
5037 + subclass = PCI_NET_OTHER;
5038 + /* Let an nvram variable override this */
5039 + sprintf(varname, "wl%did", unit);
5040 + if ((core = getintvar(NULL, varname)) == 0) {
5041 + if (chip == BCM4712_DEVICE_ID) {
5042 + if (chippkg == BCM4712SMALL_PKG_ID)
5043 + core = BCM4306_D11G_ID;
5044 + else
5045 + core = BCM4306_D11DUAL_ID;
5046 + }
5047 + }
5048 + break;
5049 +
5050 + default:
5051 + class = subclass = progif = 0xff;
5052 + break;
5053 + }
5054 +
5055 + *pcivendor = (uint16)vendor;
5056 + *pcidevice = (uint16)core;
5057 + *pciclass = class;
5058 + *pcisubclass = subclass;
5059 + *pciprogif = progif;
5060 +}
5061 +
5062 +#if 0
5063 +/* Build device path. Support SB, PCI, and JTAG for now. */
5064 +int
5065 +sb_devpath(sb_t *sbh, char *path, int size)
5066 +{
5067 + ASSERT(path);
5068 + ASSERT(size >= SB_DEVPATH_BUFSZ);
5069 +
5070 + switch (BUSTYPE((SB_INFO(sbh))->sb.bustype)) {
5071 + case SB_BUS:
5072 + case JTAG_BUS:
5073 + sprintf(path, "sb/%u/", sb_coreidx(sbh));
5074 + break;
5075 + case PCI_BUS:
5076 + ASSERT((SB_INFO(sbh))->osh);
5077 + sprintf(path, "pci/%u/%u/", OSL_PCI_BUS((SB_INFO(sbh))->osh),
5078 + PCI_SLOT(((struct pci_dev *)(SB_INFO(sbh))->osh)->pdev)->devfn);
5079 + break;
5080 + case SDIO_BUS:
5081 + SB_ERROR(("sb_devpath: device 0 assumed\n"));
5082 + sprintf(path, "sd/%u/", sb_coreidx(sbh));
5083 + break;
5084 + default:
5085 + ASSERT(0);
5086 + break;
5087 + }
5088 +
5089 + return 0;
5090 +}
5091 +#endif
5092 +
5093 +/* Fix chip's configuration. The current core may be changed upon return */
5094 +static int
5095 +sb_pci_fixcfg(sb_info_t *si)
5096 +{
5097 + uint origidx, pciidx;
5098 + sbpciregs_t *pciregs;
5099 + uint16 val16, *reg16;
5100 + char name[SB_DEVPATH_BUFSZ+16], *value;
5101 + char devpath[SB_DEVPATH_BUFSZ];
5102 +
5103 + ASSERT(BUSTYPE(si->sb.bustype) == PCI_BUS);
5104 +
5105 + /* Fix PCI(e) SROM shadow area */
5106 + /* save the current index */
5107 + origidx = sb_coreidx(&si->sb);
5108 +
5109 + if (si->sb.buscoretype == SB_PCI) {
5110 + pciregs = (sbpciregs_t *)sb_setcore(&si->sb, SB_PCI, 0);
5111 + ASSERT(pciregs);
5112 + reg16 = &pciregs->sprom[SRSH_PI_OFFSET];
5113 + }
5114 + else {
5115 + ASSERT(0);
5116 + return -1;
5117 + }
5118 + pciidx = sb_coreidx(&si->sb);
5119 + val16 = R_REG(reg16);
5120 + if (((val16 & SRSH_PI_MASK) >> SRSH_PI_SHIFT) != (uint16)pciidx) {
5121 + val16 = (uint16)(pciidx << SRSH_PI_SHIFT) | (val16 & ~SRSH_PI_MASK);
5122 + W_REG(reg16, val16);
5123 + }
5124 +
5125 + /* restore the original index */
5126 + sb_setcoreidx(&si->sb, origidx);
5127 +
5128 +#if 0
5129 + /* Fix bar0window */
5130 + /* !do it last, it changes the current core! */
5131 + if (sb_devpath(&si->sb, devpath, sizeof(devpath)))
5132 + return -1;
5133 + sprintf(name, "%sb0w", devpath);
5134 + if ((value = getvar(NULL, name))) {
5135 + OSL_PCI_WRITE_CONFIG(si->osh, PCI_BAR0_WIN, sizeof(uint32),
5136 + bcm_strtoul(value, NULL, 16));
5137 + /* update curidx since the current core is changed */
5138 + si->curidx = _sb_coreidx(si);
5139 + if (si->curidx == BADIDX) {
5140 + SB_ERROR(("sb_pci_fixcfg: bad core index\n"));
5141 + return -1;
5142 + }
5143 + }
5144 +#endif
5145 +
5146 + return 0;
5147 +}
5148 +
5149 diff -urN linux.old/arch/mips/bcm947xx/broadcom/sflash.c linux.dev/arch/mips/bcm947xx/broadcom/sflash.c
5150 --- linux.old/arch/mips/bcm947xx/broadcom/sflash.c 1970-01-01 01:00:00.000000000 +0100
5151 +++ linux.dev/arch/mips/bcm947xx/broadcom/sflash.c 2005-12-15 16:59:20.045933750 +0100
5152 @@ -0,0 +1,418 @@
5153 +/*
5154 + * Broadcom SiliconBackplane chipcommon serial flash interface
5155 + *
5156 + * Copyright 2005, Broadcom Corporation
5157 + * All Rights Reserved.
5158 + *
5159 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
5160 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
5161 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
5162 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
5163 + *
5164 + * $Id$
5165 + */
5166 +
5167 +#include <osl.h>
5168 +#include <typedefs.h>
5169 +#include <sbconfig.h>
5170 +#include <sbchipc.h>
5171 +#include <mipsinc.h>
5172 +#include <bcmutils.h>
5173 +#include <bcmdevs.h>
5174 +#include <sflash.h>
5175 +
5176 +/* Private global state */
5177 +static struct sflash sflash;
5178 +
5179 +/* Issue a serial flash command */
5180 +static INLINE void
5181 +sflash_cmd(chipcregs_t *cc, uint opcode)
5182 +{
5183 + W_REG(&cc->flashcontrol, SFLASH_START | opcode);
5184 + while (R_REG(&cc->flashcontrol) & SFLASH_BUSY);
5185 +}
5186 +
5187 +/* Initialize serial flash access */
5188 +struct sflash *
5189 +sflash_init(chipcregs_t *cc)
5190 +{
5191 + uint32 id, id2;
5192 +
5193 + bzero(&sflash, sizeof(sflash));
5194 +
5195 + sflash.type = R_REG(&cc->capabilities) & CAP_FLASH_MASK;
5196 +
5197 + switch (sflash.type) {
5198 + case SFLASH_ST:
5199 + /* Probe for ST chips */
5200 + sflash_cmd(cc, SFLASH_ST_DP);
5201 + sflash_cmd(cc, SFLASH_ST_RES);
5202 + id = R_REG(&cc->flashdata);
5203 + switch (id) {
5204 + case 0x11:
5205 + /* ST M25P20 2 Mbit Serial Flash */
5206 + sflash.blocksize = 64 * 1024;
5207 + sflash.numblocks = 4;
5208 + break;
5209 + case 0x12:
5210 + /* ST M25P40 4 Mbit Serial Flash */
5211 + sflash.blocksize = 64 * 1024;
5212 + sflash.numblocks = 8;
5213 + break;
5214 + case 0x13:
5215 + /* ST M25P80 8 Mbit Serial Flash */
5216 + sflash.blocksize = 64 * 1024;
5217 + sflash.numblocks = 16;
5218 + break;
5219 + case 0x14:
5220 + /* ST M25P16 16 Mbit Serial Flash */
5221 + sflash.blocksize = 64 * 1024;
5222 + sflash.numblocks = 32;
5223 + break;
5224 + case 0x15:
5225 + /* ST M25P32 32 Mbit Serial Flash */
5226 + sflash.blocksize = 64 * 1024;
5227 + sflash.numblocks = 64;
5228 + break;
5229 + case 0xbf:
5230 + W_REG(&cc->flashaddress, 1);
5231 + sflash_cmd(cc, SFLASH_ST_RES);
5232 + id2 = R_REG(&cc->flashdata);
5233 + if (id2 == 0x44) {
5234 + /* SST M25VF80 4 Mbit Serial Flash */
5235 + sflash.blocksize = 64 * 1024;
5236 + sflash.numblocks = 8;
5237 + }
5238 + break;
5239 + }
5240 + break;
5241 +
5242 + case SFLASH_AT:
5243 + /* Probe for Atmel chips */
5244 + sflash_cmd(cc, SFLASH_AT_STATUS);
5245 + id = R_REG(&cc->flashdata) & 0x3c;
5246 + switch (id) {
5247 + case 0xc:
5248 + /* Atmel AT45DB011 1Mbit Serial Flash */
5249 + sflash.blocksize = 256;
5250 + sflash.numblocks = 512;
5251 + break;
5252 + case 0x14:
5253 + /* Atmel AT45DB021 2Mbit Serial Flash */
5254 + sflash.blocksize = 256;
5255 + sflash.numblocks = 1024;
5256 + break;
5257 + case 0x1c:
5258 + /* Atmel AT45DB041 4Mbit Serial Flash */
5259 + sflash.blocksize = 256;
5260 + sflash.numblocks = 2048;
5261 + break;
5262 + case 0x24:
5263 + /* Atmel AT45DB081 8Mbit Serial Flash */
5264 + sflash.blocksize = 256;
5265 + sflash.numblocks = 4096;
5266 + break;
5267 + case 0x2c:
5268 + /* Atmel AT45DB161 16Mbit Serial Flash */
5269 + sflash.blocksize = 512;
5270 + sflash.numblocks = 4096;
5271 + break;
5272 + case 0x34:
5273 + /* Atmel AT45DB321 32Mbit Serial Flash */
5274 + sflash.blocksize = 512;
5275 + sflash.numblocks = 8192;
5276 + break;
5277 + case 0x3c:
5278 + /* Atmel AT45DB642 64Mbit Serial Flash */
5279 + sflash.blocksize = 1024;
5280 + sflash.numblocks = 8192;
5281 + break;
5282 + }
5283 + break;
5284 + }
5285 +
5286 + sflash.size = sflash.blocksize * sflash.numblocks;
5287 + return sflash.size ? &sflash : NULL;
5288 +}
5289 +
5290 +/* Read len bytes starting at offset into buf. Returns number of bytes read. */
5291 +int
5292 +sflash_read(chipcregs_t *cc, uint offset, uint len, uchar *buf)
5293 +{
5294 + int cnt;
5295 + uint32 *from, *to;
5296 +
5297 + if (!len)
5298 + return 0;
5299 +
5300 + if ((offset + len) > sflash.size)
5301 + return -22;
5302 +
5303 + if ((len >= 4) && (offset & 3))
5304 + cnt = 4 - (offset & 3);
5305 + else if ((len >= 4) && ((uint32)buf & 3))
5306 + cnt = 4 - ((uint32)buf & 3);
5307 + else
5308 + cnt = len;
5309 +
5310 + from = (uint32 *)KSEG1ADDR(SB_FLASH2 + offset);
5311 + to = (uint32 *)buf;
5312 +
5313 + if (cnt < 4) {
5314 + bcopy(from, to, cnt);
5315 + return cnt;
5316 + }
5317 +
5318 + while (cnt >= 4) {
5319 + *to++ = *from++;
5320 + cnt -= 4;
5321 + }
5322 +
5323 + return (len - cnt);
5324 +}
5325 +
5326 +/* Poll for command completion. Returns zero when complete. */
5327 +int
5328 +sflash_poll(chipcregs_t *cc, uint offset)
5329 +{
5330 + if (offset >= sflash.size)
5331 + return -22;
5332 +
5333 + switch (sflash.type) {
5334 + case SFLASH_ST:
5335 + /* Check for ST Write In Progress bit */
5336 + sflash_cmd(cc, SFLASH_ST_RDSR);
5337 + return R_REG(&cc->flashdata) & SFLASH_ST_WIP;
5338 + case SFLASH_AT:
5339 + /* Check for Atmel Ready bit */
5340 + sflash_cmd(cc, SFLASH_AT_STATUS);
5341 + return !(R_REG(&cc->flashdata) & SFLASH_AT_READY);
5342 + }
5343 +
5344 + return 0;
5345 +}
5346 +
5347 +/* Write len bytes starting at offset into buf. Returns number of bytes
5348 + * written. Caller should poll for completion.
5349 + */
5350 +int
5351 +sflash_write(chipcregs_t *cc, uint offset, uint len, const uchar *buf)
5352 +{
5353 + struct sflash *sfl;
5354 + int ret = 0;
5355 + bool is4712b0;
5356 + uint32 page, byte, mask;
5357 +
5358 + if (!len)
5359 + return 0;
5360 +
5361 + if ((offset + len) > sflash.size)
5362 + return -22;
5363 +
5364 + sfl = &sflash;
5365 + switch (sfl->type) {
5366 + case SFLASH_ST:
5367 + mask = R_REG(&cc->chipid);
5368 + is4712b0 = (((mask & CID_ID_MASK) == BCM4712_DEVICE_ID) &&
5369 + ((mask & CID_REV_MASK) == (3 << CID_REV_SHIFT)));
5370 + /* Enable writes */
5371 + sflash_cmd(cc, SFLASH_ST_WREN);
5372 + if (is4712b0) {
5373 + mask = 1 << 14;
5374 + W_REG(&cc->flashaddress, offset);
5375 + W_REG(&cc->flashdata, *buf++);
5376 + /* Set chip select */
5377 + OR_REG(&cc->gpioout, mask);
5378 + /* Issue a page program with the first byte */
5379 + sflash_cmd(cc, SFLASH_ST_PP);
5380 + ret = 1;
5381 + offset++;
5382 + len--;
5383 + while (len > 0) {
5384 + if ((offset & 255) == 0) {
5385 + /* Page boundary, drop cs and return */
5386 + AND_REG(&cc->gpioout, ~mask);
5387 + if (!sflash_poll(cc, offset)) {
5388 + /* Flash rejected command */
5389 + return -11;
5390 + }
5391 + return ret;
5392 + } else {
5393 + /* Write single byte */
5394 + sflash_cmd(cc, *buf++);
5395 + }
5396 + ret++;
5397 + offset++;
5398 + len--;
5399 + }
5400 + /* All done, drop cs if needed */
5401 + if ((offset & 255) != 1) {
5402 + /* Drop cs */
5403 + AND_REG(&cc->gpioout, ~mask);
5404 + if (!sflash_poll(cc, offset)) {
5405 + /* Flash rejected command */
5406 + return -12;
5407 + }
5408 + }
5409 + } else {
5410 + ret = 1;
5411 + W_REG(&cc->flashaddress, offset);
5412 + W_REG(&cc->flashdata, *buf);
5413 + /* Page program */
5414 + sflash_cmd(cc, SFLASH_ST_PP);
5415 + }
5416 + break;
5417 + case SFLASH_AT:
5418 + mask = sfl->blocksize - 1;
5419 + page = (offset & ~mask) << 1;
5420 + byte = offset & mask;
5421 + /* Read main memory page into buffer 1 */
5422 + if (byte || len < sfl->blocksize) {
5423 + W_REG(&cc->flashaddress, page);
5424 + sflash_cmd(cc, SFLASH_AT_BUF1_LOAD);
5425 + /* 250 us for AT45DB321B */
5426 + SPINWAIT(sflash_poll(cc, offset), 1000);
5427 + ASSERT(!sflash_poll(cc, offset));
5428 + }
5429 + /* Write into buffer 1 */
5430 + for (ret = 0; ret < len && byte < sfl->blocksize; ret++) {
5431 + W_REG(&cc->flashaddress, byte++);
5432 + W_REG(&cc->flashdata, *buf++);
5433 + sflash_cmd(cc, SFLASH_AT_BUF1_WRITE);
5434 + }
5435 + /* Write buffer 1 into main memory page */
5436 + W_REG(&cc->flashaddress, page);
5437 + sflash_cmd(cc, SFLASH_AT_BUF1_PROGRAM);
5438 + break;
5439 + }
5440 +
5441 + return ret;
5442 +}
5443 +
5444 +/* Erase a region. Returns number of bytes scheduled for erasure.
5445 + * Caller should poll for completion.
5446 + */
5447 +int
5448 +sflash_erase(chipcregs_t *cc, uint offset)
5449 +{
5450 + struct sflash *sfl;
5451 +
5452 + if (offset >= sflash.size)
5453 + return -22;
5454 +
5455 + sfl = &sflash;
5456 + switch (sfl->type) {
5457 + case SFLASH_ST:
5458 + sflash_cmd(cc, SFLASH_ST_WREN);
5459 + W_REG(&cc->flashaddress, offset);
5460 + sflash_cmd(cc, SFLASH_ST_SE);
5461 + return sfl->blocksize;
5462 + case SFLASH_AT:
5463 + W_REG(&cc->flashaddress, offset << 1);
5464 + sflash_cmd(cc, SFLASH_AT_PAGE_ERASE);
5465 + return sfl->blocksize;
5466 + }
5467 +
5468 + return 0;
5469 +}
5470 +
5471 +/*
5472 + * writes the appropriate range of flash, a NULL buf simply erases
5473 + * the region of flash
5474 + */
5475 +int
5476 +sflash_commit(chipcregs_t *cc, uint offset, uint len, const uchar *buf)
5477 +{
5478 + struct sflash *sfl;
5479 + uchar *block = NULL, *cur_ptr, *blk_ptr;
5480 + uint blocksize = 0, mask, cur_offset, cur_length, cur_retlen, remainder;
5481 + uint blk_offset, blk_len, copied;
5482 + int bytes, ret = 0;
5483 +
5484 + /* Check address range */
5485 + if (len <= 0)
5486 + return 0;
5487 +
5488 + sfl = &sflash;
5489 + if ((offset + len) > sfl->size)
5490 + return -1;
5491 +
5492 + blocksize = sfl->blocksize;
5493 + mask = blocksize - 1;
5494 +
5495 + /* Allocate a block of mem */
5496 + if (!(block = MALLOC(NULL, blocksize)))
5497 + return -1;
5498 +
5499 + while (len) {
5500 + /* Align offset */
5501 + cur_offset = offset & ~mask;
5502 + cur_length = blocksize;
5503 + cur_ptr = block;
5504 +
5505 + remainder = blocksize - (offset & mask);
5506 + if (len < remainder)
5507 + cur_retlen = len;
5508 + else
5509 + cur_retlen = remainder;
5510 +
5511 + /* buf == NULL means erase only */
5512 + if (buf) {
5513 + /* Copy existing data into holding block if necessary */
5514 + if ((offset & mask) || (len < blocksize)) {
5515 + blk_offset = cur_offset;
5516 + blk_len = cur_length;
5517 + blk_ptr = cur_ptr;
5518 +
5519 + /* Copy entire block */
5520 + while(blk_len) {
5521 + copied = sflash_read(cc, blk_offset, blk_len, blk_ptr);
5522 + blk_offset += copied;
5523 + blk_len -= copied;
5524 + blk_ptr += copied;
5525 + }
5526 + }
5527 +
5528 + /* Copy input data into holding block */
5529 + memcpy(cur_ptr + (offset & mask), buf, cur_retlen);
5530 + }
5531 +
5532 + /* Erase block */
5533 + if ((ret = sflash_erase(cc, (uint) cur_offset)) < 0)
5534 + goto done;
5535 + while (sflash_poll(cc, (uint) cur_offset));
5536 +
5537 + /* buf == NULL means erase only */
5538 + if (!buf) {
5539 + offset += cur_retlen;
5540 + len -= cur_retlen;
5541 + continue;
5542 + }
5543 +
5544 + /* Write holding block */
5545 + while (cur_length > 0) {
5546 + if ((bytes = sflash_write(cc,
5547 + (uint) cur_offset,
5548 + (uint) cur_length,
5549 + (uchar *) cur_ptr)) < 0) {
5550 + ret = bytes;
5551 + goto done;
5552 + }
5553 + while (sflash_poll(cc, (uint) cur_offset));
5554 + cur_offset += bytes;
5555 + cur_length -= bytes;
5556 + cur_ptr += bytes;
5557 + }
5558 +
5559 + offset += cur_retlen;
5560 + len -= cur_retlen;
5561 + buf += cur_retlen;
5562 + }
5563 +
5564 + ret = len;
5565 +done:
5566 + if (block)
5567 + MFREE(NULL, block, blocksize);
5568 + return ret;
5569 +}
5570 +
5571 diff -urN linux.old/arch/mips/bcm947xx/include/bcmdevs.h linux.dev/arch/mips/bcm947xx/include/bcmdevs.h
5572 --- linux.old/arch/mips/bcm947xx/include/bcmdevs.h 1970-01-01 01:00:00.000000000 +0100
5573 +++ linux.dev/arch/mips/bcm947xx/include/bcmdevs.h 2005-12-15 15:25:24.905340500 +0100
5574 @@ -0,0 +1,391 @@
5575 +/*
5576 + * Broadcom device-specific manifest constants.
5577 + *
5578 + * Copyright 2005, Broadcom Corporation
5579 + * All Rights Reserved.
5580 + *
5581 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
5582 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
5583 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
5584 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
5585 + * $Id$
5586 + */
5587 +
5588 +#ifndef _BCMDEVS_H
5589 +#define _BCMDEVS_H
5590 +
5591 +
5592 +/* Known PCI vendor Id's */
5593 +#define VENDOR_EPIGRAM 0xfeda
5594 +#define VENDOR_BROADCOM 0x14e4
5595 +#define VENDOR_3COM 0x10b7
5596 +#define VENDOR_NETGEAR 0x1385
5597 +#define VENDOR_DIAMOND 0x1092
5598 +#define VENDOR_DELL 0x1028
5599 +#define VENDOR_HP 0x0e11
5600 +#define VENDOR_APPLE 0x106b
5601 +
5602 +/* PCI Device Id's */
5603 +#define BCM4210_DEVICE_ID 0x1072 /* never used */
5604 +#define BCM4211_DEVICE_ID 0x4211
5605 +#define BCM4230_DEVICE_ID 0x1086 /* never used */
5606 +#define BCM4231_DEVICE_ID 0x4231
5607 +
5608 +#define BCM4410_DEVICE_ID 0x4410 /* bcm44xx family pci iline */
5609 +#define BCM4430_DEVICE_ID 0x4430 /* bcm44xx family cardbus iline */
5610 +#define BCM4412_DEVICE_ID 0x4412 /* bcm44xx family pci enet */
5611 +#define BCM4432_DEVICE_ID 0x4432 /* bcm44xx family cardbus enet */
5612 +
5613 +#define BCM3352_DEVICE_ID 0x3352 /* bcm3352 device id */
5614 +#define BCM3360_DEVICE_ID 0x3360 /* bcm3360 device id */
5615 +
5616 +#define EPI41210_DEVICE_ID 0xa0fa /* bcm4210 */
5617 +#define EPI41230_DEVICE_ID 0xa10e /* bcm4230 */
5618 +
5619 +#define BCM47XX_ILINE_ID 0x4711 /* 47xx iline20 */
5620 +#define BCM47XX_V90_ID 0x4712 /* 47xx v90 codec */
5621 +#define BCM47XX_ENET_ID 0x4713 /* 47xx enet */
5622 +#define BCM47XX_EXT_ID 0x4714 /* 47xx external i/f */
5623 +#define BCM47XX_USB_ID 0x4715 /* 47xx usb */
5624 +#define BCM47XX_USBH_ID 0x4716 /* 47xx usb host */
5625 +#define BCM47XX_USBD_ID 0x4717 /* 47xx usb device */
5626 +#define BCM47XX_IPSEC_ID 0x4718 /* 47xx ipsec */
5627 +#define BCM47XX_ROBO_ID 0x4719 /* 47xx/53xx roboswitch core */
5628 +#define BCM47XX_USB20H_ID 0x471a /* 47xx usb 2.0 host */
5629 +#define BCM47XX_USB20D_ID 0x471b /* 47xx usb 2.0 device */
5630 +
5631 +#define BCM4710_DEVICE_ID 0x4710 /* 4710 primary function 0 */
5632 +
5633 +#define BCM4610_DEVICE_ID 0x4610 /* 4610 primary function 0 */
5634 +#define BCM4610_ILINE_ID 0x4611 /* 4610 iline100 */
5635 +#define BCM4610_V90_ID 0x4612 /* 4610 v90 codec */
5636 +#define BCM4610_ENET_ID 0x4613 /* 4610 enet */
5637 +#define BCM4610_EXT_ID 0x4614 /* 4610 external i/f */
5638 +#define BCM4610_USB_ID 0x4615 /* 4610 usb */
5639 +
5640 +#define BCM4402_DEVICE_ID 0x4402 /* 4402 primary function 0 */
5641 +#define BCM4402_ENET_ID 0x4402 /* 4402 enet */
5642 +#define BCM4402_V90_ID 0x4403 /* 4402 v90 codec */
5643 +#define BCM4401_ENET_ID 0x170c /* 4401b0 production enet cards */
5644 +
5645 +#define BCM4301_DEVICE_ID 0x4301 /* 4301 primary function 0 */
5646 +#define BCM4301_D11B_ID 0x4301 /* 4301 802.11b */
5647 +
5648 +#define BCM4307_DEVICE_ID 0x4307 /* 4307 primary function 0 */
5649 +#define BCM4307_V90_ID 0x4305 /* 4307 v90 codec */
5650 +#define BCM4307_ENET_ID 0x4306 /* 4307 enet */
5651 +#define BCM4307_D11B_ID 0x4307 /* 4307 802.11b */
5652 +
5653 +#define BCM4306_DEVICE_ID 0x4306 /* 4306 chipcommon chipid */
5654 +#define BCM4306_D11G_ID 0x4320 /* 4306 802.11g */
5655 +#define BCM4306_D11G_ID2 0x4325
5656 +#define BCM4306_D11A_ID 0x4321 /* 4306 802.11a */
5657 +#define BCM4306_UART_ID 0x4322 /* 4306 uart */
5658 +#define BCM4306_V90_ID 0x4323 /* 4306 v90 codec */
5659 +#define BCM4306_D11DUAL_ID 0x4324 /* 4306 dual A+B */
5660 +
5661 +#define BCM4309_PKG_ID 1 /* 4309 package id */
5662 +
5663 +#define BCM4303_D11B_ID 0x4303 /* 4303 802.11b */
5664 +#define BCM4303_PKG_ID 2 /* 4303 package id */
5665 +
5666 +#define BCM4310_DEVICE_ID 0x4310 /* 4310 chipcommon chipid */
5667 +#define BCM4310_D11B_ID 0x4311 /* 4310 802.11b */
5668 +#define BCM4310_UART_ID 0x4312 /* 4310 uart */
5669 +#define BCM4310_ENET_ID 0x4313 /* 4310 enet */
5670 +#define BCM4310_USB_ID 0x4315 /* 4310 usb */
5671 +
5672 +#define BCMGPRS_UART_ID 0x4333 /* Uart id used by 4306/gprs card */
5673 +#define BCMGPRS2_UART_ID 0x4344 /* Uart id used by 4306/gprs card */
5674 +
5675 +
5676 +#define BCM4704_DEVICE_ID 0x4704 /* 4704 chipcommon chipid */
5677 +#define BCM4704_ENET_ID 0x4706 /* 4704 enet (Use 47XX_ENET_ID instead!) */
5678 +
5679 +#define BCM4317_DEVICE_ID 0x4317 /* 4317 chip common chipid */
5680 +
5681 +#define BCM4318_DEVICE_ID 0x4318 /* 4318 chip common chipid */
5682 +#define BCM4318_D11G_ID 0x4318 /* 4318 801.11b/g id */
5683 +#define BCM4318_D11DUAL_ID 0x4319 /* 4318 801.11a/b/g id */
5684 +#define BCM4318_JTAGM_ID 0x4331 /* 4318 jtagm device id */
5685 +
5686 +#define FPGA_JTAGM_ID 0x4330 /* ??? */
5687 +
5688 +/* Address map */
5689 +#define BCM4710_SDRAM 0x00000000 /* Physical SDRAM */
5690 +#define BCM4710_PCI_MEM 0x08000000 /* Host Mode PCI memory access space (64 MB) */
5691 +#define BCM4710_PCI_CFG 0x0c000000 /* Host Mode PCI configuration space (64 MB) */
5692 +#define BCM4710_PCI_DMA 0x40000000 /* Client Mode PCI memory access space (1 GB) */
5693 +#define BCM4710_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
5694 +#define BCM4710_ENUM 0x18000000 /* Beginning of core enumeration space */
5695 +
5696 +/* Core register space */
5697 +#define BCM4710_REG_SDRAM 0x18000000 /* SDRAM core registers */
5698 +#define BCM4710_REG_ILINE20 0x18001000 /* InsideLine20 core registers */
5699 +#define BCM4710_REG_EMAC0 0x18002000 /* Ethernet MAC 0 core registers */
5700 +#define BCM4710_REG_CODEC 0x18003000 /* Codec core registers */
5701 +#define BCM4710_REG_USB 0x18004000 /* USB core registers */
5702 +#define BCM4710_REG_PCI 0x18005000 /* PCI core registers */
5703 +#define BCM4710_REG_MIPS 0x18006000 /* MIPS core registers */
5704 +#define BCM4710_REG_EXTIF 0x18007000 /* External Interface core registers */
5705 +#define BCM4710_REG_EMAC1 0x18008000 /* Ethernet MAC 1 core registers */
5706 +
5707 +#define BCM4710_EXTIF 0x1f000000 /* External Interface base address */
5708 +#define BCM4710_PCMCIA_MEM 0x1f000000 /* External Interface PCMCIA memory access */
5709 +#define BCM4710_PCMCIA_IO 0x1f100000 /* PCMCIA I/O access */
5710 +#define BCM4710_PCMCIA_CONF 0x1f200000 /* PCMCIA configuration */
5711 +#define BCM4710_PROG 0x1f800000 /* Programable interface */
5712 +#define BCM4710_FLASH 0x1fc00000 /* Flash */
5713 +
5714 +#define BCM4710_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
5715 +
5716 +#define BCM4710_UART (BCM4710_REG_EXTIF + 0x00000300)
5717 +
5718 +#define BCM4710_EUART (BCM4710_EXTIF + 0x00800000)
5719 +#define BCM4710_LED (BCM4710_EXTIF + 0x00900000)
5720 +
5721 +#define BCM4712_DEVICE_ID 0x4712 /* 4712 chipcommon chipid */
5722 +#define BCM4712_MIPS_ID 0x4720 /* 4712 base devid */
5723 +#define BCM4712LARGE_PKG_ID 0 /* 340pin 4712 package id */
5724 +#define BCM4712SMALL_PKG_ID 1 /* 200pin 4712 package id */
5725 +#define BCM4712MID_PKG_ID 2 /* 225pin 4712 package id */
5726 +
5727 +#define SDIOH_FPGA_ID 0x4380 /* sdio host fpga */
5728 +
5729 +#define BCM5365_DEVICE_ID 0x5365 /* 5365 chipcommon chipid */
5730 +#define BCM5350_DEVICE_ID 0x5350 /* bcm5350 chipcommon chipid */
5731 +#define BCM5352_DEVICE_ID 0x5352 /* bcm5352 chipcommon chipid */
5732 +
5733 +#define BCM4320_DEVICE_ID 0x4320 /* bcm4320 chipcommon chipid */
5734 +
5735 +/* PCMCIA vendor Id's */
5736 +
5737 +#define VENDOR_BROADCOM_PCMCIA 0x02d0
5738 +
5739 +/* SDIO vendor Id's */
5740 +#define VENDOR_BROADCOM_SDIO 0x00BF
5741 +
5742 +
5743 +/* boardflags */
5744 +#define BFL_BTCOEXIST 0x0001 /* This board implements Bluetooth coexistance */
5745 +#define BFL_PACTRL 0x0002 /* This board has gpio 9 controlling the PA */
5746 +#define BFL_AIRLINEMODE 0x0004 /* This board implements gpio13 radio disable indication */
5747 +#define BFL_ENETROBO 0x0010 /* This board has robo switch or core */
5748 +#define BFL_CCKHIPWR 0x0040 /* Can do high-power CCK transmission */
5749 +#define BFL_ENETADM 0x0080 /* This board has ADMtek switch */
5750 +#define BFL_ENETVLAN 0x0100 /* This board has vlan capability */
5751 +#define BFL_AFTERBURNER 0x0200 /* This board supports Afterburner mode */
5752 +#define BFL_NOPCI 0x0400 /* This board leaves PCI floating */
5753 +#define BFL_FEM 0x0800 /* This board supports the Front End Module */
5754 +#define BFL_EXTLNA 0x1000 /* This board has an external LNA */
5755 +#define BFL_HGPA 0x2000 /* This board has a high gain PA */
5756 +#define BFL_BTCMOD 0x4000 /* This board' BTCOEXIST is in the alternate gpios */
5757 +#define BFL_ALTIQ 0x8000 /* Alternate I/Q settings */
5758 +
5759 +/* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */
5760 +#define BOARD_GPIO_HWRAD_B 0x010 /* bit 4 is HWRAD input on 4301 */
5761 +#define BOARD_GPIO_BTCMOD_IN 0x010 /* bit 4 is the alternate BT Coexistance Input */
5762 +#define BOARD_GPIO_BTCMOD_OUT 0x020 /* bit 5 is the alternate BT Coexistance Out */
5763 +#define BOARD_GPIO_BTC_IN 0x080 /* bit 7 is BT Coexistance Input */
5764 +#define BOARD_GPIO_BTC_OUT 0x100 /* bit 8 is BT Coexistance Out */
5765 +#define BOARD_GPIO_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */
5766 +#define PCI_CFG_GPIO_SCS 0x10 /* PCI config space bit 4 for 4306c0 slow clock source */
5767 +#define PCI_CFG_GPIO_HWRAD 0x20 /* PCI config space GPIO 13 for hw radio disable */
5768 +#define PCI_CFG_GPIO_XTAL 0x40 /* PCI config space GPIO 14 for Xtal powerup */
5769 +#define PCI_CFG_GPIO_PLL 0x80 /* PCI config space GPIO 15 for PLL powerdown */
5770 +
5771 +/* Bus types */
5772 +#define SB_BUS 0 /* Silicon Backplane */
5773 +#define PCI_BUS 1 /* PCI target */
5774 +#define PCMCIA_BUS 2 /* PCMCIA target */
5775 +#define SDIO_BUS 3 /* SDIO target */
5776 +#define JTAG_BUS 4 /* JTAG */
5777 +
5778 +/* Allows optimization for single-bus support */
5779 +#ifdef BCMBUSTYPE
5780 +#define BUSTYPE(bus) (BCMBUSTYPE)
5781 +#else
5782 +#define BUSTYPE(bus) (bus)
5783 +#endif
5784 +
5785 +/* power control defines */
5786 +#define PLL_DELAY 150 /* us pll on delay */
5787 +#define FREF_DELAY 200 /* us fref change delay */
5788 +#define MIN_SLOW_CLK 32 /* us Slow clock period */
5789 +#define XTAL_ON_DELAY 1000 /* us crystal power-on delay */
5790 +
5791 +/* Reference Board Types */
5792 +
5793 +#define BU4710_BOARD 0x0400
5794 +#define VSIM4710_BOARD 0x0401
5795 +#define QT4710_BOARD 0x0402
5796 +
5797 +#define BU4610_BOARD 0x0403
5798 +#define VSIM4610_BOARD 0x0404
5799 +
5800 +#define BU4307_BOARD 0x0405
5801 +#define BCM94301CB_BOARD 0x0406
5802 +#define BCM94301PC_BOARD 0x0406 /* Pcmcia 5v card */
5803 +#define BCM94301MP_BOARD 0x0407
5804 +#define BCM94307MP_BOARD 0x0408
5805 +#define BCMAP4307_BOARD 0x0409
5806 +
5807 +#define BU4309_BOARD 0x040a
5808 +#define BCM94309CB_BOARD 0x040b
5809 +#define BCM94309MP_BOARD 0x040c
5810 +#define BCM4309AP_BOARD 0x040d
5811 +
5812 +#define BCM94302MP_BOARD 0x040e
5813 +
5814 +#define VSIM4310_BOARD 0x040f
5815 +#define BU4711_BOARD 0x0410
5816 +#define BCM94310U_BOARD 0x0411
5817 +#define BCM94310AP_BOARD 0x0412
5818 +#define BCM94310MP_BOARD 0x0414
5819 +
5820 +#define BU4306_BOARD 0x0416
5821 +#define BCM94306CB_BOARD 0x0417
5822 +#define BCM94306MP_BOARD 0x0418
5823 +
5824 +#define BCM94710D_BOARD 0x041a
5825 +#define BCM94710R1_BOARD 0x041b
5826 +#define BCM94710R4_BOARD 0x041c
5827 +#define BCM94710AP_BOARD 0x041d
5828 +
5829 +
5830 +#define BU2050_BOARD 0x041f
5831 +
5832 +
5833 +#define BCM94309G_BOARD 0x0421
5834 +
5835 +#define BCM94301PC3_BOARD 0x0422 /* Pcmcia 3.3v card */
5836 +
5837 +#define BU4704_BOARD 0x0423
5838 +#define BU4702_BOARD 0x0424
5839 +
5840 +#define BCM94306PC_BOARD 0x0425 /* pcmcia 3.3v 4306 card */
5841 +
5842 +#define BU4317_BOARD 0x0426
5843 +
5844 +
5845 +#define BCM94702MN_BOARD 0x0428
5846 +
5847 +/* BCM4702 1U CompactPCI Board */
5848 +#define BCM94702CPCI_BOARD 0x0429
5849 +
5850 +/* BCM4702 with BCM95380 VLAN Router */
5851 +#define BCM95380RR_BOARD 0x042a
5852 +
5853 +/* cb4306 with SiGe PA */
5854 +#define BCM94306CBSG_BOARD 0x042b
5855 +
5856 +/* mp4301 with 2050 radio */
5857 +#define BCM94301MPL_BOARD 0x042c
5858 +
5859 +/* cb4306 with SiGe PA */
5860 +#define PCSG94306_BOARD 0x042d
5861 +
5862 +/* bu4704 with sdram */
5863 +#define BU4704SD_BOARD 0x042e
5864 +
5865 +/* Dual 11a/11g Router */
5866 +#define BCM94704AGR_BOARD 0x042f
5867 +
5868 +/* 11a-only minipci */
5869 +#define BCM94308MP_BOARD 0x0430
5870 +
5871 +
5872 +
5873 +/* BCM94317 boards */
5874 +#define BCM94317CB_BOARD 0x0440
5875 +#define BCM94317MP_BOARD 0x0441
5876 +#define BCM94317PCMCIA_BOARD 0x0442
5877 +#define BCM94317SDIO_BOARD 0x0443
5878 +
5879 +#define BU4712_BOARD 0x0444
5880 +#define BU4712SD_BOARD 0x045d
5881 +#define BU4712L_BOARD 0x045f
5882 +
5883 +/* BCM4712 boards */
5884 +#define BCM94712AP_BOARD 0x0445
5885 +#define BCM94712P_BOARD 0x0446
5886 +
5887 +/* BCM4318 boards */
5888 +#define BU4318_BOARD 0x0447
5889 +#define CB4318_BOARD 0x0448
5890 +#define MPG4318_BOARD 0x0449
5891 +#define MP4318_BOARD 0x044a
5892 +#define SD4318_BOARD 0x044b
5893 +
5894 +/* BCM63XX boards */
5895 +#define BCM96338_BOARD 0x6338
5896 +#define BCM96345_BOARD 0x6345
5897 +#define BCM96348_BOARD 0x6348
5898 +
5899 +/* Another mp4306 with SiGe */
5900 +#define BCM94306P_BOARD 0x044c
5901 +
5902 +/* CF-like 4317 modules */
5903 +#define BCM94317CF_BOARD 0x044d
5904 +
5905 +/* mp4303 */
5906 +#define BCM94303MP_BOARD 0x044e
5907 +
5908 +/* mpsgh4306 */
5909 +#define BCM94306MPSGH_BOARD 0x044f
5910 +
5911 +/* BRCM 4306 w/ Front End Modules */
5912 +#define BCM94306MPM 0x0450
5913 +#define BCM94306MPL 0x0453
5914 +
5915 +/* 4712agr */
5916 +#define BCM94712AGR_BOARD 0x0451
5917 +
5918 +/* The real CF 4317 board */
5919 +#define CFI4317_BOARD 0x0452
5920 +
5921 +/* pcmcia 4303 */
5922 +#define PC4303_BOARD 0x0454
5923 +
5924 +/* 5350K */
5925 +#define BCM95350K_BOARD 0x0455
5926 +
5927 +/* 5350R */
5928 +#define BCM95350R_BOARD 0x0456
5929 +
5930 +/* 4306mplna */
5931 +#define BCM94306MPLNA_BOARD 0x0457
5932 +
5933 +/* 4320 boards */
5934 +#define BU4320_BOARD 0x0458
5935 +#define BU4320S_BOARD 0x0459
5936 +#define BCM94320PH_BOARD 0x045a
5937 +
5938 +/* 4306mph */
5939 +#define BCM94306MPH_BOARD 0x045b
5940 +
5941 +/* 4306pciv */
5942 +#define BCM94306PCIV_BOARD 0x045c
5943 +
5944 +#define BU4712SD_BOARD 0x045d
5945 +
5946 +#define BCM94320PFLSH_BOARD 0x045e
5947 +
5948 +#define BU4712L_BOARD 0x045f
5949 +#define BCM94712LGR_BOARD 0x0460
5950 +#define BCM94320R_BOARD 0x0461
5951 +
5952 +#define BU5352_BOARD 0x0462
5953 +
5954 +#define BCM94318MPGH_BOARD 0x0463
5955 +
5956 +
5957 +#define BCM95352GR_BOARD 0x0467
5958 +
5959 +/* bcm95351agr */
5960 +#define BCM95351AGR_BOARD 0x0470
5961 +
5962 +/* # of GPIO pins */
5963 +#define GPIO_NUMPINS 16
5964 +
5965 +#endif /* _BCMDEVS_H */
5966 diff -urN linux.old/arch/mips/bcm947xx/include/bcmendian.h linux.dev/arch/mips/bcm947xx/include/bcmendian.h
5967 --- linux.old/arch/mips/bcm947xx/include/bcmendian.h 1970-01-01 01:00:00.000000000 +0100
5968 +++ linux.dev/arch/mips/bcm947xx/include/bcmendian.h 2005-12-15 15:25:47.146730500 +0100
5969 @@ -0,0 +1,152 @@
5970 +/*
5971 + * local version of endian.h - byte order defines
5972 + *
5973 + * Copyright 2005, Broadcom Corporation
5974 + * All Rights Reserved.
5975 + *
5976 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
5977 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
5978 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
5979 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
5980 + *
5981 + * $Id$
5982 +*/
5983 +
5984 +#ifndef _BCMENDIAN_H_
5985 +#define _BCMENDIAN_H_
5986 +
5987 +#include <typedefs.h>
5988 +
5989 +/* Byte swap a 16 bit value */
5990 +#define BCMSWAP16(val) \
5991 + ((uint16)( \
5992 + (((uint16)(val) & (uint16)0x00ffU) << 8) | \
5993 + (((uint16)(val) & (uint16)0xff00U) >> 8) ))
5994 +
5995 +/* Byte swap a 32 bit value */
5996 +#define BCMSWAP32(val) \
5997 + ((uint32)( \
5998 + (((uint32)(val) & (uint32)0x000000ffUL) << 24) | \
5999 + (((uint32)(val) & (uint32)0x0000ff00UL) << 8) | \
6000 + (((uint32)(val) & (uint32)0x00ff0000UL) >> 8) | \
6001 + (((uint32)(val) & (uint32)0xff000000UL) >> 24) ))
6002 +
6003 +/* 2 Byte swap a 32 bit value */
6004 +#define BCMSWAP32BY16(val) \
6005 + ((uint32)( \
6006 + (((uint32)(val) & (uint32)0x0000ffffUL) << 16) | \
6007 + (((uint32)(val) & (uint32)0xffff0000UL) >> 16) ))
6008 +
6009 +
6010 +static INLINE uint16
6011 +bcmswap16(uint16 val)
6012 +{
6013 + return BCMSWAP16(val);
6014 +}
6015 +
6016 +static INLINE uint32
6017 +bcmswap32(uint32 val)
6018 +{
6019 + return BCMSWAP32(val);
6020 +}
6021 +
6022 +static INLINE uint32
6023 +bcmswap32by16(uint32 val)
6024 +{
6025 + return BCMSWAP32BY16(val);
6026 +}
6027 +
6028 +/* buf - start of buffer of shorts to swap */
6029 +/* len - byte length of buffer */
6030 +static INLINE void
6031 +bcmswap16_buf(uint16 *buf, uint len)
6032 +{
6033 + len = len/2;
6034 +
6035 + while(len--){
6036 + *buf = bcmswap16(*buf);
6037 + buf++;
6038 + }
6039 +}
6040 +
6041 +#ifndef hton16
6042 +#ifndef IL_BIGENDIAN
6043 +#define HTON16(i) BCMSWAP16(i)
6044 +#define hton16(i) bcmswap16(i)
6045 +#define hton32(i) bcmswap32(i)
6046 +#define ntoh16(i) bcmswap16(i)
6047 +#define ntoh32(i) bcmswap32(i)
6048 +#define ltoh16(i) (i)
6049 +#define ltoh32(i) (i)
6050 +#define htol16(i) (i)
6051 +#define htol32(i) (i)
6052 +#else
6053 +#define HTON16(i) (i)
6054 +#define hton16(i) (i)
6055 +#define hton32(i) (i)
6056 +#define ntoh16(i) (i)
6057 +#define ntoh32(i) (i)
6058 +#define ltoh16(i) bcmswap16(i)
6059 +#define ltoh32(i) bcmswap32(i)
6060 +#define htol16(i) bcmswap16(i)
6061 +#define htol32(i) bcmswap32(i)
6062 +#endif
6063 +#endif
6064 +
6065 +#ifndef IL_BIGENDIAN
6066 +#define ltoh16_buf(buf, i)
6067 +#define htol16_buf(buf, i)
6068 +#else
6069 +#define ltoh16_buf(buf, i) bcmswap16_buf((uint16*)buf, i)
6070 +#define htol16_buf(buf, i) bcmswap16_buf((uint16*)buf, i)
6071 +#endif
6072 +
6073 +/*
6074 +* load 16-bit value from unaligned little endian byte array.
6075 +*/
6076 +static INLINE uint16
6077 +ltoh16_ua(uint8 *bytes)
6078 +{
6079 + return (bytes[1]<<8)+bytes[0];
6080 +}
6081 +
6082 +/*
6083 +* load 32-bit value from unaligned little endian byte array.
6084 +*/
6085 +static INLINE uint32
6086 +ltoh32_ua(uint8 *bytes)
6087 +{
6088 + return (bytes[3]<<24)+(bytes[2]<<16)+(bytes[1]<<8)+bytes[0];
6089 +}
6090 +
6091 +/*
6092 +* load 16-bit value from unaligned big(network) endian byte array.
6093 +*/
6094 +static INLINE uint16
6095 +ntoh16_ua(uint8 *bytes)
6096 +{
6097 + return (bytes[0]<<8)+bytes[1];
6098 +}
6099 +
6100 +/*
6101 +* load 32-bit value from unaligned big(network) endian byte array.
6102 +*/
6103 +static INLINE uint32
6104 +ntoh32_ua(uint8 *bytes)
6105 +{
6106 + return (bytes[0]<<24)+(bytes[1]<<16)+(bytes[2]<<8)+bytes[3];
6107 +}
6108 +
6109 +#define ltoh_ua(ptr) ( \
6110 + sizeof(*(ptr)) == sizeof(uint8) ? *(uint8 *)ptr : \
6111 + sizeof(*(ptr)) == sizeof(uint16) ? (((uint8 *)ptr)[1]<<8)+((uint8 *)ptr)[0] : \
6112 + (((uint8 *)ptr)[3]<<24)+(((uint8 *)ptr)[2]<<16)+(((uint8 *)ptr)[1]<<8)+((uint8 *)ptr)[0] \
6113 +)
6114 +
6115 +#define ntoh_ua(ptr) ( \
6116 + sizeof(*(ptr)) == sizeof(uint8) ? *(uint8 *)ptr : \
6117 + sizeof(*(ptr)) == sizeof(uint16) ? (((uint8 *)ptr)[0]<<8)+((uint8 *)ptr)[1] : \
6118 + (((uint8 *)ptr)[0]<<24)+(((uint8 *)ptr)[1]<<16)+(((uint8 *)ptr)[2]<<8)+((uint8 *)ptr)[3] \
6119 +)
6120 +
6121 +#endif /* _BCMENDIAN_H_ */
6122 diff -urN linux.old/arch/mips/bcm947xx/include/bcmnvram.h linux.dev/arch/mips/bcm947xx/include/bcmnvram.h
6123 --- linux.old/arch/mips/bcm947xx/include/bcmnvram.h 1970-01-01 01:00:00.000000000 +0100
6124 +++ linux.dev/arch/mips/bcm947xx/include/bcmnvram.h 2005-12-15 16:04:35.850827500 +0100
6125 @@ -0,0 +1,87 @@
6126 +/*
6127 + * NVRAM variable manipulation
6128 + *
6129 + * Copyright 2005, Broadcom Corporation
6130 + * All Rights Reserved.
6131 + *
6132 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6133 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6134 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6135 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6136 + *
6137 + * $Id$
6138 + */
6139 +
6140 +#ifndef _bcmnvram_h_
6141 +#define _bcmnvram_h_
6142 +
6143 +#ifndef _LANGUAGE_ASSEMBLY
6144 +
6145 +#include <typedefs.h>
6146 +
6147 +struct nvram_header {
6148 + uint32 magic;
6149 + uint32 len;
6150 + uint32 crc_ver_init; /* 0:7 crc, 8:15 ver, 16:31 sdram_init */
6151 + uint32 config_refresh; /* 0:15 sdram_config, 16:31 sdram_refresh */
6152 + uint32 config_ncdl; /* ncdl values for memc */
6153 +};
6154 +
6155 +struct nvram_tuple {
6156 + char *name;
6157 + char *value;
6158 + struct nvram_tuple *next;
6159 +};
6160 +
6161 +/*
6162 + * Get the value of an NVRAM variable. The pointer returned may be
6163 + * invalid after a set.
6164 + * @param name name of variable to get
6165 + * @return value of variable or NULL if undefined
6166 + */
6167 +extern char * __init nvram_get(const char *name);
6168 +
6169 +/*
6170 + * Get the value of an NVRAM variable.
6171 + * @param name name of variable to get
6172 + * @return value of variable or NUL if undefined
6173 + */
6174 +#define nvram_safe_get(name) (BCMINIT(nvram_get)(name) ? : "")
6175 +
6176 +/*
6177 + * Match an NVRAM variable.
6178 + * @param name name of variable to match
6179 + * @param match value to compare against value of variable
6180 + * @return TRUE if variable is defined and its value is string equal
6181 + * to match or FALSE otherwise
6182 + */
6183 +static inline int
6184 +nvram_match(char *name, char *match) {
6185 + const char *value = BCMINIT(nvram_get)(name);
6186 + return (value && !strcmp(value, match));
6187 +}
6188 +
6189 +/*
6190 + * Inversely match an NVRAM variable.
6191 + * @param name name of variable to match
6192 + * @param match value to compare against value of variable
6193 + * @return TRUE if variable is defined and its value is not string
6194 + * equal to invmatch or FALSE otherwise
6195 + */
6196 +static inline int
6197 +nvram_invmatch(char *name, char *invmatch) {
6198 + const char *value = BCMINIT(nvram_get)(name);
6199 + return (value && strcmp(value, invmatch));
6200 +}
6201 +
6202 +#endif /* _LANGUAGE_ASSEMBLY */
6203 +
6204 +#define NVRAM_MAGIC 0x48534C46 /* 'FLSH' */
6205 +#define NVRAM_VERSION 1
6206 +#define NVRAM_HEADER_SIZE 20
6207 +#define NVRAM_SPACE 0x8000
6208 +
6209 +#define NVRAM_MAX_VALUE_LEN 255
6210 +#define NVRAM_MAX_PARAM_LEN 64
6211 +
6212 +#endif /* _bcmnvram_h_ */
6213 diff -urN linux.old/arch/mips/bcm947xx/include/bcmsrom.h linux.dev/arch/mips/bcm947xx/include/bcmsrom.h
6214 --- linux.old/arch/mips/bcm947xx/include/bcmsrom.h 1970-01-01 01:00:00.000000000 +0100
6215 +++ linux.dev/arch/mips/bcm947xx/include/bcmsrom.h 2005-12-15 15:34:32.919589250 +0100
6216 @@ -0,0 +1,23 @@
6217 +/*
6218 + * Misc useful routines to access NIC local SROM/OTP .
6219 + *
6220 + * Copyright 2005, Broadcom Corporation
6221 + * All Rights Reserved.
6222 + *
6223 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6224 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6225 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6226 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6227 + *
6228 + * $Id$
6229 + */
6230 +
6231 +#ifndef _bcmsrom_h_
6232 +#define _bcmsrom_h_
6233 +
6234 +extern int srom_var_init(void *sbh, uint bus, void *curmap, osl_t *osh, char **vars, int *count);
6235 +
6236 +extern int srom_read(uint bus, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf);
6237 +extern int srom_write(uint bus, void *curmap, osl_t *osh, uint byteoff, uint nbytes, uint16 *buf);
6238 +
6239 +#endif /* _bcmsrom_h_ */
6240 diff -urN linux.old/arch/mips/bcm947xx/include/bcmutils.h linux.dev/arch/mips/bcm947xx/include/bcmutils.h
6241 --- linux.old/arch/mips/bcm947xx/include/bcmutils.h 1970-01-01 01:00:00.000000000 +0100
6242 +++ linux.dev/arch/mips/bcm947xx/include/bcmutils.h 2005-12-15 16:44:25.619117750 +0100
6243 @@ -0,0 +1,308 @@
6244 +/*
6245 + * Misc useful os-independent macros and functions.
6246 + *
6247 + * Copyright 2005, Broadcom Corporation
6248 + * All Rights Reserved.
6249 + *
6250 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6251 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6252 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6253 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6254 + * $Id$
6255 + */
6256 +
6257 +#ifndef _bcmutils_h_
6258 +#define _bcmutils_h_
6259 +
6260 +/*** driver-only section ***/
6261 +#include <osl.h>
6262 +
6263 +#define _BCM_U 0x01 /* upper */
6264 +#define _BCM_L 0x02 /* lower */
6265 +#define _BCM_D 0x04 /* digit */
6266 +#define _BCM_C 0x08 /* cntrl */
6267 +#define _BCM_P 0x10 /* punct */
6268 +#define _BCM_S 0x20 /* white space (space/lf/tab) */
6269 +#define _BCM_X 0x40 /* hex digit */
6270 +#define _BCM_SP 0x80 /* hard space (0x20) */
6271 +
6272 +#define GPIO_PIN_NOTDEFINED 0x20
6273 +
6274 +extern unsigned char bcm_ctype[];
6275 +#define bcm_ismask(x) (bcm_ctype[(int)(unsigned char)(x)])
6276 +
6277 +#define bcm_isalnum(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L|_BCM_D)) != 0)
6278 +#define bcm_isalpha(c) ((bcm_ismask(c)&(_BCM_U|_BCM_L)) != 0)
6279 +#define bcm_iscntrl(c) ((bcm_ismask(c)&(_BCM_C)) != 0)
6280 +#define bcm_isdigit(c) ((bcm_ismask(c)&(_BCM_D)) != 0)
6281 +#define bcm_isgraph(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D)) != 0)
6282 +#define bcm_islower(c) ((bcm_ismask(c)&(_BCM_L)) != 0)
6283 +#define bcm_isprint(c) ((bcm_ismask(c)&(_BCM_P|_BCM_U|_BCM_L|_BCM_D|_BCM_SP)) != 0)
6284 +#define bcm_ispunct(c) ((bcm_ismask(c)&(_BCM_P)) != 0)
6285 +#define bcm_isspace(c) ((bcm_ismask(c)&(_BCM_S)) != 0)
6286 +#define bcm_isupper(c) ((bcm_ismask(c)&(_BCM_U)) != 0)
6287 +#define bcm_isxdigit(c) ((bcm_ismask(c)&(_BCM_D|_BCM_X)) != 0)
6288 +
6289 +/*
6290 + * Spin at most 'us' microseconds while 'exp' is true.
6291 + * Caller should explicitly test 'exp' when this completes
6292 + * and take appropriate error action if 'exp' is still true.
6293 + */
6294 +#define SPINWAIT(exp, us) { \
6295 + uint countdown = (us) + 9; \
6296 + while ((exp) && (countdown >= 10)) {\
6297 + OSL_DELAY(10); \
6298 + countdown -= 10; \
6299 + } \
6300 +}
6301 +
6302 +/* generic osl packet queue */
6303 +struct pktq {
6304 + void *head; /* first packet to dequeue */
6305 + void *tail; /* last packet to dequeue */
6306 + uint len; /* number of queued packets */
6307 + uint maxlen; /* maximum number of queued packets */
6308 + bool priority; /* enqueue by packet priority */
6309 + uint8 prio_map[MAXPRIO+1]; /* user priority to packet enqueue policy map */
6310 +};
6311 +#define DEFAULT_QLEN 128
6312 +
6313 +#define pktq_len(q) ((q)->len)
6314 +#define pktq_avail(q) ((q)->maxlen - (q)->len)
6315 +#define pktq_head(q) ((q)->head)
6316 +#define pktq_full(q) ((q)->len >= (q)->maxlen)
6317 +#define _pktq_pri(q, pri) ((q)->prio_map[pri])
6318 +#define pktq_tailpri(q) ((q)->tail ? _pktq_pri(q, PKTPRIO((q)->tail)) : _pktq_pri(q, 0))
6319 +
6320 +/* externs */
6321 +/* packet */
6322 +extern uint pktcopy(osl_t *osh, void *p, uint offset, int len, uchar *buf);
6323 +extern uint pkttotlen(osl_t *osh, void *);
6324 +extern void pktq_init(struct pktq *q, uint maxlen, const uint8 prio_map[]);
6325 +extern void pktenq(struct pktq *q, void *p, bool lifo);
6326 +extern void *pktdeq(struct pktq *q);
6327 +extern void *pktdeqtail(struct pktq *q);
6328 +/* string */
6329 +extern uint bcm_atoi(char *s);
6330 +extern uchar bcm_toupper(uchar c);
6331 +extern ulong bcm_strtoul(char *cp, char **endp, uint base);
6332 +extern char *bcmstrstr(char *haystack, char *needle);
6333 +extern char *bcmstrcat(char *dest, const char *src);
6334 +extern ulong wchar2ascii(char *abuf, ushort *wbuf, ushort wbuflen, ulong abuflen);
6335 +/* ethernet address */
6336 +extern char *bcm_ether_ntoa(char *ea, char *buf);
6337 +extern int bcm_ether_atoe(char *p, char *ea);
6338 +/* delay */
6339 +extern void bcm_mdelay(uint ms);
6340 +/* variable access */
6341 +extern char *getvar(char *vars, char *name);
6342 +extern int getintvar(char *vars, char *name);
6343 +extern uint getgpiopin(char *vars, char *pin_name, uint def_pin);
6344 +#define bcmlog(fmt, a1, a2)
6345 +#define bcmdumplog(buf, size) *buf = '\0'
6346 +#define bcmdumplogent(buf, idx) -1
6347 +
6348 +/*** driver/apps-shared section ***/
6349 +
6350 +#define BCME_STRLEN 64
6351 +#define VALID_BCMERROR(e) ((e <= 0) && (e >= BCME_LAST))
6352 +
6353 +
6354 +/*
6355 + * error codes could be added but the defined ones shouldn't be changed/deleted
6356 + * these error codes are exposed to the user code
6357 + * when ever a new error code is added to this list
6358 + * please update errorstring table with the related error string and
6359 + * update osl files with os specific errorcode map
6360 +*/
6361 +
6362 +#define BCME_ERROR -1 /* Error generic */
6363 +#define BCME_BADARG -2 /* Bad Argument */
6364 +#define BCME_BADOPTION -3 /* Bad option */
6365 +#define BCME_NOTUP -4 /* Not up */
6366 +#define BCME_NOTDOWN -5 /* Not down */
6367 +#define BCME_NOTAP -6 /* Not AP */
6368 +#define BCME_NOTSTA -7 /* Not STA */
6369 +#define BCME_BADKEYIDX -8 /* BAD Key Index */
6370 +#define BCME_RADIOOFF -9 /* Radio Off */
6371 +#define BCME_NOTBANDLOCKED -10 /* Not bandlocked */
6372 +#define BCME_NOCLK -11 /* No Clock*/
6373 +#define BCME_BADRATESET -12 /* BAD RateSet*/
6374 +#define BCME_BADBAND -13 /* BAD Band */
6375 +#define BCME_BUFTOOSHORT -14 /* Buffer too short */
6376 +#define BCME_BUFTOOLONG -15 /* Buffer too Long */
6377 +#define BCME_BUSY -16 /* Busy*/
6378 +#define BCME_NOTASSOCIATED -17 /* Not associated*/
6379 +#define BCME_BADSSIDLEN -18 /* BAD SSID Len */
6380 +#define BCME_OUTOFRANGECHAN -19 /* Out of Range Channel*/
6381 +#define BCME_BADCHAN -20 /* BAD Channel */
6382 +#define BCME_BADADDR -21 /* BAD Address*/
6383 +#define BCME_NORESOURCE -22 /* No resources*/
6384 +#define BCME_UNSUPPORTED -23 /* Unsupported*/
6385 +#define BCME_BADLEN -24 /* Bad Length*/
6386 +#define BCME_NOTREADY -25 /* Not ready Yet*/
6387 +#define BCME_EPERM -26 /* Not Permitted */
6388 +#define BCME_NOMEM -27 /* No Memory */
6389 +#define BCME_ASSOCIATED -28 /* Associated */
6390 +#define BCME_RANGE -29 /* Range Error*/
6391 +#define BCME_NOTFOUND -30 /* Not found */
6392 +#define BCME_LAST BCME_NOTFOUND
6393 +
6394 +#ifndef ABS
6395 +#define ABS(a) (((a)<0)?-(a):(a))
6396 +#endif
6397 +
6398 +#ifndef MIN
6399 +#define MIN(a, b) (((a)<(b))?(a):(b))
6400 +#endif
6401 +
6402 +#ifndef MAX
6403 +#define MAX(a, b) (((a)>(b))?(a):(b))
6404 +#endif
6405 +
6406 +#define CEIL(x, y) (((x) + ((y)-1)) / (y))
6407 +#define ROUNDUP(x, y) ((((x)+((y)-1))/(y))*(y))
6408 +#define ISALIGNED(a, x) (((a) & ((x)-1)) == 0)
6409 +#define ISPOWEROF2(x) ((((x)-1)&(x))==0)
6410 +#define VALID_MASK(mask) !((mask) & ((mask) + 1))
6411 +#define OFFSETOF(type, member) ((uint)(uintptr)&((type *)0)->member)
6412 +#define ARRAYSIZE(a) (sizeof(a)/sizeof(a[0]))
6413 +
6414 +/* bit map related macros */
6415 +#ifndef setbit
6416 +#define NBBY 8 /* 8 bits per byte */
6417 +#define setbit(a,i) (((uint8 *)a)[(i)/NBBY] |= 1<<((i)%NBBY))
6418 +#define clrbit(a,i) (((uint8 *)a)[(i)/NBBY] &= ~(1<<((i)%NBBY)))
6419 +#define isset(a,i) (((uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY)))
6420 +#define isclr(a,i) ((((uint8 *)a)[(i)/NBBY] & (1<<((i)%NBBY))) == 0)
6421 +#endif
6422 +
6423 +#define NBITS(type) (sizeof(type) * 8)
6424 +#define NBITVAL(bits) (1 << (bits))
6425 +#define MAXBITVAL(bits) ((1 << (bits)) - 1)
6426 +
6427 +/* crc defines */
6428 +#define CRC8_INIT_VALUE 0xff /* Initial CRC8 checksum value */
6429 +#define CRC8_GOOD_VALUE 0x9f /* Good final CRC8 checksum value */
6430 +#define CRC16_INIT_VALUE 0xffff /* Initial CRC16 checksum value */
6431 +#define CRC16_GOOD_VALUE 0xf0b8 /* Good final CRC16 checksum value */
6432 +#define CRC32_INIT_VALUE 0xffffffff /* Initial CRC32 checksum value */
6433 +#define CRC32_GOOD_VALUE 0xdebb20e3 /* Good final CRC32 checksum value */
6434 +
6435 +/* bcm_format_flags() bit description structure */
6436 +typedef struct bcm_bit_desc {
6437 + uint32 bit;
6438 + char* name;
6439 +} bcm_bit_desc_t;
6440 +
6441 +/* tag_ID/length/value_buffer tuple */
6442 +typedef struct bcm_tlv {
6443 + uint8 id;
6444 + uint8 len;
6445 + uint8 data[1];
6446 +} bcm_tlv_t;
6447 +
6448 +/* Check that bcm_tlv_t fits into the given buflen */
6449 +#define bcm_valid_tlv(elt, buflen) ((buflen) >= 2 && (int)(buflen) >= (int)(2 + (elt)->len))
6450 +
6451 +/* buffer length for ethernet address from bcm_ether_ntoa() */
6452 +#define ETHER_ADDR_STR_LEN 18
6453 +
6454 +/* unaligned load and store macros */
6455 +#ifdef IL_BIGENDIAN
6456 +static INLINE uint32
6457 +load32_ua(uint8 *a)
6458 +{
6459 + return ((a[0] << 24) | (a[1] << 16) | (a[2] << 8) | a[3]);
6460 +}
6461 +
6462 +static INLINE void
6463 +store32_ua(uint8 *a, uint32 v)
6464 +{
6465 + a[0] = (v >> 24) & 0xff;
6466 + a[1] = (v >> 16) & 0xff;
6467 + a[2] = (v >> 8) & 0xff;
6468 + a[3] = v & 0xff;
6469 +}
6470 +
6471 +static INLINE uint16
6472 +load16_ua(uint8 *a)
6473 +{
6474 + return ((a[0] << 8) | a[1]);
6475 +}
6476 +
6477 +static INLINE void
6478 +store16_ua(uint8 *a, uint16 v)
6479 +{
6480 + a[0] = (v >> 8) & 0xff;
6481 + a[1] = v & 0xff;
6482 +}
6483 +
6484 +#else
6485 +
6486 +static INLINE uint32
6487 +load32_ua(uint8 *a)
6488 +{
6489 + return ((a[3] << 24) | (a[2] << 16) | (a[1] << 8) | a[0]);
6490 +}
6491 +
6492 +static INLINE void
6493 +store32_ua(uint8 *a, uint32 v)
6494 +{
6495 + a[3] = (v >> 24) & 0xff;
6496 + a[2] = (v >> 16) & 0xff;
6497 + a[1] = (v >> 8) & 0xff;
6498 + a[0] = v & 0xff;
6499 +}
6500 +
6501 +static INLINE uint16
6502 +load16_ua(uint8 *a)
6503 +{
6504 + return ((a[1] << 8) | a[0]);
6505 +}
6506 +
6507 +static INLINE void
6508 +store16_ua(uint8 *a, uint16 v)
6509 +{
6510 + a[1] = (v >> 8) & 0xff;
6511 + a[0] = v & 0xff;
6512 +}
6513 +
6514 +#endif
6515 +
6516 +/* externs */
6517 +/* crc */
6518 +extern uint8 hndcrc8(uint8 *p, uint nbytes, uint8 crc);
6519 +/* format/print */
6520 +/* IE parsing */
6521 +extern bcm_tlv_t *bcm_next_tlv(bcm_tlv_t *elt, int *buflen);
6522 +extern bcm_tlv_t *bcm_parse_tlvs(void *buf, int buflen, uint key);
6523 +extern bcm_tlv_t *bcm_parse_ordered_tlvs(void *buf, int buflen, uint key);
6524 +
6525 +/* bcmerror*/
6526 +extern const char *bcmerrorstr(int bcmerror);
6527 +
6528 +/* multi-bool data type: set of bools, mbool is true if any is set */
6529 +typedef uint32 mbool;
6530 +#define mboolset(mb, bit) (mb |= bit) /* set one bool */
6531 +#define mboolclr(mb, bit) (mb &= ~bit) /* clear one bool */
6532 +#define mboolisset(mb, bit) ((mb & bit) != 0) /* TRUE if one bool is set */
6533 +#define mboolmaskset(mb, mask, val) ((mb) = (((mb) & ~(mask)) | (val)))
6534 +
6535 +/* power conversion */
6536 +extern uint16 bcm_qdbm_to_mw(uint8 qdbm);
6537 +extern uint8 bcm_mw_to_qdbm(uint16 mw);
6538 +
6539 +/* generic datastruct to help dump routines */
6540 +struct fielddesc {
6541 + char *nameandfmt;
6542 + uint32 offset;
6543 + uint32 len;
6544 +};
6545 +
6546 +typedef uint32 (*readreg_rtn)(void *arg0, void *arg1, uint32 offset);
6547 +extern uint bcmdumpfields(readreg_rtn func_ptr, void *arg0, void *arg1, struct fielddesc *str, char *buf, uint32 bufsize);
6548 +
6549 +extern uint bcm_mkiovar(char *name, char *data, uint datalen, char *buf, uint len);
6550 +
6551 +#endif /* _bcmutils_h_ */
6552 diff -urN linux.old/arch/mips/bcm947xx/include/bitfuncs.h linux.dev/arch/mips/bcm947xx/include/bitfuncs.h
6553 --- linux.old/arch/mips/bcm947xx/include/bitfuncs.h 1970-01-01 01:00:00.000000000 +0100
6554 +++ linux.dev/arch/mips/bcm947xx/include/bitfuncs.h 2005-12-15 15:34:40.268048500 +0100
6555 @@ -0,0 +1,85 @@
6556 +/*
6557 + * bit manipulation utility functions
6558 + *
6559 + * Copyright 2005, Broadcom Corporation
6560 + * All Rights Reserved.
6561 + *
6562 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6563 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6564 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6565 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6566 + * $Id$
6567 + */
6568 +
6569 +#ifndef _BITFUNCS_H
6570 +#define _BITFUNCS_H
6571 +
6572 +#include <typedefs.h>
6573 +
6574 +/* local prototypes */
6575 +static INLINE uint32 find_msbit(uint32 x);
6576 +
6577 +
6578 +/*
6579 + * find_msbit: returns index of most significant set bit in x, with index
6580 + * range defined as 0-31. NOTE: returns zero if input is zero.
6581 + */
6582 +
6583 +#if defined(USE_PENTIUM_BSR) && defined(__GNUC__)
6584 +
6585 +/*
6586 + * Implementation for Pentium processors and gcc. Note that this
6587 + * instruction is actually very slow on some processors (e.g., family 5,
6588 + * model 2, stepping 12, "Pentium 75 - 200"), so we use the generic
6589 + * implementation instead.
6590 + */
6591 +static INLINE uint32 find_msbit(uint32 x)
6592 +{
6593 + uint msbit;
6594 + __asm__("bsrl %1,%0"
6595 + :"=r" (msbit)
6596 + :"r" (x));
6597 + return msbit;
6598 +}
6599 +
6600 +#else
6601 +
6602 +/*
6603 + * Generic Implementation
6604 + */
6605 +
6606 +#define DB_POW_MASK16 0xffff0000
6607 +#define DB_POW_MASK8 0x0000ff00
6608 +#define DB_POW_MASK4 0x000000f0
6609 +#define DB_POW_MASK2 0x0000000c
6610 +#define DB_POW_MASK1 0x00000002
6611 +
6612 +static INLINE uint32 find_msbit(uint32 x)
6613 +{
6614 + uint32 temp_x = x;
6615 + uint msbit = 0;
6616 + if (temp_x & DB_POW_MASK16) {
6617 + temp_x >>= 16;
6618 + msbit = 16;
6619 + }
6620 + if (temp_x & DB_POW_MASK8) {
6621 + temp_x >>= 8;
6622 + msbit += 8;
6623 + }
6624 + if (temp_x & DB_POW_MASK4) {
6625 + temp_x >>= 4;
6626 + msbit += 4;
6627 + }
6628 + if (temp_x & DB_POW_MASK2) {
6629 + temp_x >>= 2;
6630 + msbit += 2;
6631 + }
6632 + if (temp_x & DB_POW_MASK1) {
6633 + msbit += 1;
6634 + }
6635 + return(msbit);
6636 +}
6637 +
6638 +#endif
6639 +
6640 +#endif /* _BITFUNCS_H */
6641 diff -urN linux.old/arch/mips/bcm947xx/include/flash.h linux.dev/arch/mips/bcm947xx/include/flash.h
6642 --- linux.old/arch/mips/bcm947xx/include/flash.h 1970-01-01 01:00:00.000000000 +0100
6643 +++ linux.dev/arch/mips/bcm947xx/include/flash.h 2005-12-15 15:34:44.280299250 +0100
6644 @@ -0,0 +1,188 @@
6645 +/*
6646 + * flash.h: Common definitions for flash access.
6647 + *
6648 + * Copyright 2005, Broadcom Corporation
6649 + * All Rights Reserved.
6650 + *
6651 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6652 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6653 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6654 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6655 + *
6656 + * $Id$
6657 + */
6658 +
6659 +/* Types of flashes we know about */
6660 +typedef enum _flash_type {OLD, BSC, SCS, AMD, SST, SFLASH} flash_type_t;
6661 +
6662 +/* Commands to write/erase the flases */
6663 +typedef struct _flash_cmds{
6664 + flash_type_t type;
6665 + bool need_unlock;
6666 + uint16 pre_erase;
6667 + uint16 erase_block;
6668 + uint16 erase_chip;
6669 + uint16 write_word;
6670 + uint16 write_buf;
6671 + uint16 clear_csr;
6672 + uint16 read_csr;
6673 + uint16 read_id;
6674 + uint16 confirm;
6675 + uint16 read_array;
6676 +} flash_cmds_t;
6677 +
6678 +#define UNLOCK_CMD_WORDS 2
6679 +
6680 +typedef struct _unlock_cmd {
6681 + uint addr[UNLOCK_CMD_WORDS];
6682 + uint16 cmd[UNLOCK_CMD_WORDS];
6683 +} unlock_cmd_t;
6684 +
6685 +/* Flash descriptors */
6686 +typedef struct _flash_desc {
6687 + uint16 mfgid; /* Manufacturer Id */
6688 + uint16 devid; /* Device Id */
6689 + uint size; /* Total size in bytes */
6690 + uint width; /* Device width in bytes */
6691 + flash_type_t type; /* Device type old, S, J */
6692 + uint bsize; /* Block size */
6693 + uint nb; /* Number of blocks */
6694 + uint ff; /* First full block */
6695 + uint lf; /* Last full block */
6696 + uint nsub; /* Number of subblocks */
6697 + uint *subblocks; /* Offsets for subblocks */
6698 + char *desc; /* Description */
6699 +} flash_desc_t;
6700 +
6701 +
6702 +#ifdef DECLARE_FLASHES
6703 +flash_cmds_t sflash_cmd_t =
6704 + { SFLASH, 0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
6705 +
6706 +flash_cmds_t flash_cmds[] = {
6707 +/* type needu preera eraseb erasech write wbuf clcsr rdcsr rdid confrm read */
6708 + { BSC, 0, 0x00, 0x20, 0x00, 0x40, 0x00, 0x50, 0x70, 0x90, 0xd0, 0xff },
6709 + { SCS, 0, 0x00, 0x20, 0x00, 0x40, 0xe8, 0x50, 0x70, 0x90, 0xd0, 0xff },
6710 + { AMD, 1, 0x80, 0x30, 0x10, 0xa0, 0x00, 0x00, 0x00, 0x90, 0x00, 0xf0 },
6711 + { SST, 1, 0x80, 0x50, 0x10, 0xa0, 0x00, 0x00, 0x00, 0x90, 0x00, 0xf0 },
6712 + { 0 }
6713 +};
6714 +
6715 +unlock_cmd_t unlock_cmd_amd = {
6716 +#ifdef MIPSEB
6717 +/* addr: */ { 0x0aa8, 0x0556},
6718 +#else
6719 +/* addr: */ { 0x0aaa, 0x0554},
6720 +#endif
6721 +/* data: */ { 0xaa, 0x55}
6722 +};
6723 +
6724 +unlock_cmd_t unlock_cmd_sst = {
6725 +#ifdef MIPSEB
6726 +/* addr: */ { 0xaaa8, 0x5556},
6727 +#else
6728 +/* addr: */ { 0xaaaa, 0x5554},
6729 +#endif
6730 +/* data: */ { 0xaa, 0x55}
6731 +};
6732 +
6733 +#define AMD_CMD 0xaaa
6734 +#define SST_CMD 0xaaaa
6735 +
6736 +/* intel unlock block cmds */
6737 +#define INTEL_UNLOCK1 0x60
6738 +#define INTEL_UNLOCK2 0xD0
6739 +
6740 +/* Just eight blocks of 8KB byte each */
6741 +
6742 +uint blk8x8k[] = { 0x00000000,
6743 + 0x00002000,
6744 + 0x00004000,
6745 + 0x00006000,
6746 + 0x00008000,
6747 + 0x0000a000,
6748 + 0x0000c000,
6749 + 0x0000e000,
6750 + 0x00010000
6751 +};
6752 +
6753 +/* Funky AMD arrangement for 29xx800's */
6754 +uint amd800[] = { 0x00000000, /* 16KB */
6755 + 0x00004000, /* 32KB */
6756 + 0x0000c000, /* 8KB */
6757 + 0x0000e000, /* 8KB */
6758 + 0x00010000, /* 8KB */
6759 + 0x00012000, /* 8KB */
6760 + 0x00014000, /* 32KB */
6761 + 0x0001c000, /* 16KB */
6762 + 0x00020000
6763 +};
6764 +
6765 +/* AMD arrangement for 29xx160's */
6766 +uint amd4112[] = { 0x00000000, /* 32KB */
6767 + 0x00008000, /* 8KB */
6768 + 0x0000a000, /* 8KB */
6769 + 0x0000c000, /* 16KB */
6770 + 0x00010000
6771 +};
6772 +uint amd2114[] = { 0x00000000, /* 16KB */
6773 + 0x00004000, /* 8KB */
6774 + 0x00006000, /* 8KB */
6775 + 0x00008000, /* 32KB */
6776 + 0x00010000
6777 +};
6778 +
6779 +
6780 +flash_desc_t sflash_desc =
6781 + { 0, 0, 0, 0, SFLASH, 0, 0, 0, 0, 0, NULL, "SFLASH" };
6782 +
6783 +flash_desc_t flashes[] = {
6784 + { 0x00b0, 0x00d0, 0x0200000, 2, SCS, 0x10000, 32, 0, 31, 0, NULL, "Intel 28F160S3/5 1Mx16" },
6785 + { 0x00b0, 0x00d4, 0x0400000, 2, SCS, 0x10000, 64, 0, 63, 0, NULL, "Intel 28F320S3/5 2Mx16" },
6786 + { 0x0089, 0x8890, 0x0200000, 2, BSC, 0x10000, 32, 0, 30, 8, blk8x8k, "Intel 28F160B3 1Mx16 TopB" },
6787 + { 0x0089, 0x8891, 0x0200000, 2, BSC, 0x10000, 32, 1, 31, 8, blk8x8k, "Intel 28F160B3 1Mx16 BotB" },
6788 + { 0x0089, 0x8896, 0x0400000, 2, BSC, 0x10000, 64, 0, 62, 8, blk8x8k, "Intel 28F320B3 2Mx16 TopB" },
6789 + { 0x0089, 0x8897, 0x0400000, 2, BSC, 0x10000, 64, 1, 63, 8, blk8x8k, "Intel 28F320B3 2Mx16 BotB" },
6790 + { 0x0089, 0x8898, 0x0800000, 2, BSC, 0x10000, 128, 0, 126, 8, blk8x8k, "Intel 28F640B3 4Mx16 TopB" },
6791 + { 0x0089, 0x8899, 0x0800000, 2, BSC, 0x10000, 128, 1, 127, 8, blk8x8k, "Intel 28F640B3 4Mx16 BotB" },
6792 + { 0x0089, 0x88C2, 0x0200000, 2, BSC, 0x10000, 32, 0, 30, 8, blk8x8k, "Intel 28F160C3 1Mx16 TopB" },
6793 + { 0x0089, 0x88C3, 0x0200000, 2, BSC, 0x10000, 32, 1, 31, 8, blk8x8k, "Intel 28F160C3 1Mx16 BotB" },
6794 + { 0x0089, 0x88C4, 0x0400000, 2, BSC, 0x10000, 64, 0, 62, 8, blk8x8k, "Intel 28F320C3 2Mx16 TopB" },
6795 + { 0x0089, 0x88C5, 0x0400000, 2, BSC, 0x10000, 64, 1, 63, 8, blk8x8k, "Intel 28F320C3 2Mx16 BotB" },
6796 + { 0x0089, 0x88CC, 0x0800000, 2, BSC, 0x10000, 128, 0, 126, 8, blk8x8k, "Intel 28F640C3 4Mx16 TopB" },
6797 + { 0x0089, 0x88CD, 0x0800000, 2, BSC, 0x10000, 128, 1, 127, 8, blk8x8k, "Intel 28F640C3 4Mx16 BotB" },
6798 + { 0x0089, 0x0014, 0x0400000, 2, SCS, 0x20000, 32, 0, 31, 0, NULL, "Intel 28F320J5 2Mx16" },
6799 + { 0x0089, 0x0015, 0x0800000, 2, SCS, 0x20000, 64, 0, 63, 0, NULL, "Intel 28F640J5 4Mx16" },
6800 + { 0x0089, 0x0016, 0x0400000, 2, SCS, 0x20000, 32, 0, 31, 0, NULL, "Intel 28F320J3 2Mx16" },
6801 + { 0x0089, 0x0017, 0x0800000, 2, SCS, 0x20000, 64, 0, 63, 0, NULL, "Intel 28F640J3 4Mx16" },
6802 + { 0x0089, 0x0018, 0x1000000, 2, SCS, 0x20000, 128, 0, 127, 0, NULL, "Intel 28F128J3 8Mx16" },
6803 + { 0x00b0, 0x00e3, 0x0400000, 2, BSC, 0x10000, 64, 1, 63, 8, blk8x8k, "Sharp 28F320BJE 2Mx16 BotB" },
6804 + { 0x0001, 0x224a, 0x0100000, 2, AMD, 0x10000, 16, 0, 13, 8, amd800, "AMD 29DL800BT 512Kx16 TopB" },
6805 + { 0x0001, 0x22cb, 0x0100000, 2, AMD, 0x10000, 16, 2, 15, 8, amd800, "AMD 29DL800BB 512Kx16 BotB" },
6806 + { 0x0001, 0x22c4, 0x0200000, 2, AMD, 0x10000, 32, 0, 30, 4, amd2114, "AMD 29lv160DT 1Mx16 TopB" },
6807 + { 0x0001, 0x2249, 0x0200000, 2, AMD, 0x10000, 32, 1, 31, 4, amd4112, "AMD 29lv160DB 1Mx16 BotB" },
6808 + { 0x0001, 0x22f6, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 8, blk8x8k, "AMD 29lv320DT 2Mx16 TopB" },
6809 + { 0x0001, 0x22f9, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 8, blk8x8k, "AMD 29lv320DB 2Mx16 BotB" },
6810 + { 0x0001, 0x227e, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 8, blk8x8k, "AMD 29lv320MT 2Mx16 TopB" },
6811 + { 0x0001, 0x2200, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 8, blk8x8k, "AMD 29lv320MB 2Mx16 BotB" },
6812 + { 0x0020, 0x22CA, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "ST 29w320DT 2Mx16 TopB" },
6813 + { 0x0020, 0x22CB, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "ST 29w320DB 2Mx16 BotB" },
6814 + { 0x00C2, 0x00A7, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "MX29LV320T 2Mx16 TopB" },
6815 + { 0x00C2, 0x00A8, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "MX29LV320B 2Mx16 BotB" },
6816 + { 0x0004, 0x22F6, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "MBM29LV320TE 2Mx16 TopB" },
6817 + { 0x0004, 0x22F9, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "MBM29LV320BE 2Mx16 BotB" },
6818 + { 0x0098, 0x009A, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "TC58FVT321 2Mx16 TopB" },
6819 + { 0x0098, 0x009C, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "TC58FVB321 2Mx16 BotB" },
6820 + { 0x00C2, 0x22A7, 0x0400000, 2, AMD, 0x10000, 64, 0, 62, 4, amd4112, "MX29LV320T 2Mx16 TopB" },
6821 + { 0x00C2, 0x22A8, 0x0400000, 2, AMD, 0x10000, 64, 1, 63, 4, amd2114, "MX29LV320B 2Mx16 BotB" },
6822 + { 0x00BF, 0x2783, 0x0400000, 2, SST, 0x10000, 64, 0, 63, 0, NULL, "SST39VF320 2Mx16" },
6823 + { 0, 0, 0, 0, OLD, 0, 0, 0, 0, 0, NULL, NULL },
6824 +};
6825 +
6826 +#else
6827 +
6828 +extern flash_cmds_t flash_cmds[];
6829 +extern unlock_cmd_t unlock_cmd;
6830 +extern flash_desc_t flashes[];
6831 +
6832 +#endif
6833 diff -urN linux.old/arch/mips/bcm947xx/include/flashutl.h linux.dev/arch/mips/bcm947xx/include/flashutl.h
6834 --- linux.old/arch/mips/bcm947xx/include/flashutl.h 1970-01-01 01:00:00.000000000 +0100
6835 +++ linux.dev/arch/mips/bcm947xx/include/flashutl.h 2005-12-15 15:34:48.160541750 +0100
6836 @@ -0,0 +1,27 @@
6837 +/*
6838 + * BCM47XX FLASH driver interface
6839 + *
6840 + * Copyright 2005, Broadcom Corporation
6841 + * All Rights Reserved.
6842 + *
6843 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6844 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6845 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6846 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6847 + * $Id$
6848 + */
6849 +
6850 +#ifndef _flashutl_h_
6851 +#define _flashutl_h_
6852 +
6853 +
6854 +#ifndef _LANGUAGE_ASSEMBLY
6855 +
6856 +int sysFlashInit(char *flash_str);
6857 +int sysFlashRead(uint off, uchar *dst, uint bytes);
6858 +int sysFlashWrite(uint off, uchar *src, uint bytes);
6859 +void nvWrite(unsigned short *data, unsigned int len);
6860 +
6861 +#endif /* _LANGUAGE_ASSEMBLY */
6862 +
6863 +#endif /* _flashutl_h_ */
6864 diff -urN linux.old/arch/mips/bcm947xx/include/hndmips.h linux.dev/arch/mips/bcm947xx/include/hndmips.h
6865 --- linux.old/arch/mips/bcm947xx/include/hndmips.h 1970-01-01 01:00:00.000000000 +0100
6866 +++ linux.dev/arch/mips/bcm947xx/include/hndmips.h 2005-12-15 15:34:53.396869000 +0100
6867 @@ -0,0 +1,16 @@
6868 +/*
6869 + * Alternate include file for HND sbmips.h since CFE also ships with
6870 + * a sbmips.h.
6871 + *
6872 + * Copyright 2005, Broadcom Corporation
6873 + * All Rights Reserved.
6874 + *
6875 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6876 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6877 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6878 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6879 + *
6880 + * $Id$
6881 + */
6882 +
6883 +#include "sbmips.h"
6884 diff -urN linux.old/arch/mips/bcm947xx/include/linux_osl.h linux.dev/arch/mips/bcm947xx/include/linux_osl.h
6885 --- linux.old/arch/mips/bcm947xx/include/linux_osl.h 1970-01-01 01:00:00.000000000 +0100
6886 +++ linux.dev/arch/mips/bcm947xx/include/linux_osl.h 2005-12-15 17:23:39.225126750 +0100
6887 @@ -0,0 +1,331 @@
6888 +/*
6889 + * Linux OS Independent Layer
6890 + *
6891 + * Copyright 2005, Broadcom Corporation
6892 + * All Rights Reserved.
6893 + *
6894 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
6895 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
6896 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
6897 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
6898 + *
6899 + * $Id$
6900 + */
6901 +
6902 +#ifndef _linux_osl_h_
6903 +#define _linux_osl_h_
6904 +
6905 +#include <typedefs.h>
6906 +
6907 +/* use current 2.4.x calling conventions */
6908 +#include <linuxver.h>
6909 +
6910 +/* assert and panic */
6911 +#ifdef __GNUC__
6912 +#define GCC_VERSION (__GNUC__ * 10000 + __GNUC_MINOR__ * 100 + __GNUC_PATCHLEVEL__)
6913 +#if GCC_VERSION > 30100
6914 +#define ASSERT(exp) do {} while (0)
6915 +#else
6916 +/* ASSERT could causes segmentation fault on GCC3.1, use empty instead*/
6917 +#define ASSERT(exp)
6918 +#endif
6919 +#endif
6920 +
6921 +/* microsecond delay */
6922 +#define OSL_DELAY(usec) osl_delay(usec)
6923 +extern void osl_delay(uint usec);
6924 +
6925 +/* PCI configuration space access macros */
6926 +#define OSL_PCI_READ_CONFIG(osh, offset, size) \
6927 + osl_pci_read_config((osh), (offset), (size))
6928 +#define OSL_PCI_WRITE_CONFIG(osh, offset, size, val) \
6929 + osl_pci_write_config((osh), (offset), (size), (val))
6930 +extern uint32 osl_pci_read_config(osl_t *osh, uint size, uint offset);
6931 +extern void osl_pci_write_config(osl_t *osh, uint offset, uint size, uint val);
6932 +
6933 +/* PCI device bus # and slot # */
6934 +#define OSL_PCI_BUS(osh) osl_pci_bus(osh)
6935 +#define OSL_PCI_SLOT(osh) osl_pci_slot(osh)
6936 +extern uint osl_pci_bus(osl_t *osh);
6937 +extern uint osl_pci_slot(osl_t *osh);
6938 +
6939 +/* OSL initialization */
6940 +extern osl_t *osl_attach(void *pdev);
6941 +extern void osl_detach(osl_t *osh);
6942 +
6943 +/* host/bus architecture-specific byte swap */
6944 +#define BUS_SWAP32(v) (v)
6945 +
6946 +/* general purpose memory allocation */
6947 +
6948 +#define MALLOC(osh, size) kmalloc(size, GFP_ATOMIC)
6949 +#define MFREE(osh, addr, size) kfree(addr);
6950 +
6951 +#define MALLOC_FAILED(osh) osl_malloc_failed((osh))
6952 +
6953 +extern void *osl_malloc(osl_t *osh, uint size);
6954 +extern void osl_mfree(osl_t *osh, void *addr, uint size);
6955 +extern uint osl_malloced(osl_t *osh);
6956 +extern uint osl_malloc_failed(osl_t *osh);
6957 +
6958 +/* allocate/free shared (dma-able) consistent memory */
6959 +#define DMA_CONSISTENT_ALIGN PAGE_SIZE
6960 +#define DMA_ALLOC_CONSISTENT(osh, size, pap) \
6961 + osl_dma_alloc_consistent((osh), (size), (pap))
6962 +#define DMA_FREE_CONSISTENT(osh, va, size, pa) \
6963 + osl_dma_free_consistent((osh), (void*)(va), (size), (pa))
6964 +extern void *osl_dma_alloc_consistent(osl_t *osh, uint size, ulong *pap);
6965 +extern void osl_dma_free_consistent(osl_t *osh, void *va, uint size, ulong pa);
6966 +
6967 +/* map/unmap direction */
6968 +#define DMA_TX 1
6969 +#define DMA_RX 2
6970 +
6971 +/* register access macros */
6972 +#if defined(BCMJTAG)
6973 +#include <bcmjtag.h>
6974 +#define R_REG(r) bcmjtag_read(NULL, (uint32)(r), sizeof (*(r)))
6975 +#define W_REG(r, v) bcmjtag_write(NULL, (uint32)(r), (uint32)(v), sizeof (*(r)))
6976 +#endif
6977 +
6978 +/*
6979 + * BINOSL selects the slightly slower function-call-based binary compatible osl.
6980 + * Macros expand to calls to functions defined in linux_osl.c .
6981 + */
6982 +#ifndef BINOSL
6983 +
6984 +/* string library, kernel mode */
6985 +#define printf(fmt, args...) printk(fmt, ## args)
6986 +#include <linux/kernel.h>
6987 +#include <linux/string.h>
6988 +
6989 +/* register access macros */
6990 +#if !defined(BCMJTAG)
6991 +#ifndef IL_BIGENDIAN
6992 +#define R_REG(r) ( \
6993 + sizeof(*(r)) == sizeof(uint8) ? readb((volatile uint8*)(r)) : \
6994 + sizeof(*(r)) == sizeof(uint16) ? readw((volatile uint16*)(r)) : \
6995 + readl((volatile uint32*)(r)) \
6996 +)
6997 +#define W_REG(r, v) do { \
6998 + switch (sizeof(*(r))) { \
6999 + case sizeof(uint8): writeb((uint8)(v), (volatile uint8*)(r)); break; \
7000 + case sizeof(uint16): writew((uint16)(v), (volatile uint16*)(r)); break; \
7001 + case sizeof(uint32): writel((uint32)(v), (volatile uint32*)(r)); break; \
7002 + } \
7003 +} while (0)
7004 +#else /* IL_BIGENDIAN */
7005 +#define R_REG(r) ({ \
7006 + __typeof(*(r)) __osl_v; \
7007 + switch (sizeof(*(r))) { \
7008 + case sizeof(uint8): __osl_v = readb((volatile uint8*)((uint32)r^3)); break; \
7009 + case sizeof(uint16): __osl_v = readw((volatile uint16*)((uint32)r^2)); break; \
7010 + case sizeof(uint32): __osl_v = readl((volatile uint32*)(r)); break; \
7011 + } \
7012 + __osl_v; \
7013 +})
7014 +#define W_REG(r, v) do { \
7015 + switch (sizeof(*(r))) { \
7016 + case sizeof(uint8): writeb((uint8)(v), (volatile uint8*)((uint32)r^3)); break; \
7017 + case sizeof(uint16): writew((uint16)(v), (volatile uint16*)((uint32)r^2)); break; \
7018 + case sizeof(uint32): writel((uint32)(v), (volatile uint32*)(r)); break; \
7019 + } \
7020 +} while (0)
7021 +#endif
7022 +#endif
7023 +
7024 +#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
7025 +#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
7026 +
7027 +/* bcopy, bcmp, and bzero */
7028 +#define bcopy(src, dst, len) memcpy((dst), (src), (len))
7029 +#define bcmp(b1, b2, len) memcmp((b1), (b2), (len))
7030 +#define bzero(b, len) memset((b), '\0', (len))
7031 +
7032 +/* uncached virtual address */
7033 +#ifdef mips
7034 +#define OSL_UNCACHED(va) KSEG1ADDR((va))
7035 +#include <asm/addrspace.h>
7036 +#else
7037 +#define OSL_UNCACHED(va) (va)
7038 +#endif
7039 +
7040 +/* get processor cycle count */
7041 +#if defined(mips)
7042 +#define OSL_GETCYCLES(x) ((x) = read_c0_count() * 2)
7043 +#elif defined(__i386__)
7044 +#define OSL_GETCYCLES(x) rdtscl((x))
7045 +#else
7046 +#define OSL_GETCYCLES(x) ((x) = 0)
7047 +#endif
7048 +
7049 +/* dereference an address that may cause a bus exception */
7050 +#ifdef mips
7051 +#if defined(MODULE) && (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,17))
7052 +#define BUSPROBE(val, addr) panic("get_dbe() will not fixup a bus exception when compiled into a module")
7053 +#else
7054 +#define BUSPROBE(val, addr) get_dbe((val), (addr))
7055 +#include <asm/paccess.h>
7056 +#endif
7057 +#else
7058 +#define BUSPROBE(val, addr) ({ (val) = R_REG((addr)); 0; })
7059 +#endif
7060 +
7061 +/* map/unmap physical to virtual I/O */
7062 +#define REG_MAP(pa, size) ioremap_nocache((unsigned long)(pa), (unsigned long)(size))
7063 +#define REG_UNMAP(va) iounmap((void *)(va))
7064 +
7065 +/* shared (dma-able) memory access macros */
7066 +#define R_SM(r) *(r)
7067 +#define W_SM(r, v) (*(r) = (v))
7068 +#define BZERO_SM(r, len) memset((r), '\0', (len))
7069 +
7070 +/* packet primitives */
7071 +#define PKTGET(osh, len, send) osl_pktget((osh), (len), (send))
7072 +#define PKTFREE(osh, skb, send) osl_pktfree((skb))
7073 +#define PKTDATA(osh, skb) (((struct sk_buff*)(skb))->data)
7074 +#define PKTLEN(osh, skb) (((struct sk_buff*)(skb))->len)
7075 +#define PKTHEADROOM(osh, skb) (PKTDATA(osh,skb)-(((struct sk_buff*)(skb))->head))
7076 +#define PKTTAILROOM(osh, skb) ((((struct sk_buff*)(skb))->end)-(((struct sk_buff*)(skb))->tail))
7077 +#define PKTNEXT(osh, skb) (((struct sk_buff*)(skb))->next)
7078 +#define PKTSETNEXT(skb, x) (((struct sk_buff*)(skb))->next = (struct sk_buff*)(x))
7079 +#define PKTSETLEN(osh, skb, len) __skb_trim((struct sk_buff*)(skb), (len))
7080 +#define PKTPUSH(osh, skb, bytes) skb_push((struct sk_buff*)(skb), (bytes))
7081 +#define PKTPULL(osh, skb, bytes) skb_pull((struct sk_buff*)(skb), (bytes))
7082 +#define PKTDUP(osh, skb) skb_clone((struct sk_buff*)(skb), GFP_ATOMIC)
7083 +#define PKTCOOKIE(skb) ((void*)((struct sk_buff*)(skb))->csum)
7084 +#define PKTSETCOOKIE(skb, x) (((struct sk_buff*)(skb))->csum = (uint)(x))
7085 +#define PKTLINK(skb) (((struct sk_buff*)(skb))->prev)
7086 +#define PKTSETLINK(skb, x) (((struct sk_buff*)(skb))->prev = (struct sk_buff*)(x))
7087 +#define PKTPRIO(skb) (((struct sk_buff*)(skb))->priority)
7088 +#define PKTSETPRIO(skb, x) (((struct sk_buff*)(skb))->priority = (x))
7089 +extern void *osl_pktget(osl_t *osh, uint len, bool send);
7090 +extern void osl_pktfree(void *skb);
7091 +
7092 +#else /* BINOSL */
7093 +
7094 +/* string library */
7095 +#ifndef LINUX_OSL
7096 +#undef printf
7097 +#define printf(fmt, args...) osl_printf((fmt), ## args)
7098 +#undef sprintf
7099 +#define sprintf(buf, fmt, args...) osl_sprintf((buf), (fmt), ## args)
7100 +#undef strcmp
7101 +#define strcmp(s1, s2) osl_strcmp((s1), (s2))
7102 +#undef strncmp
7103 +#define strncmp(s1, s2, n) osl_strncmp((s1), (s2), (n))
7104 +#undef strlen
7105 +#define strlen(s) osl_strlen((s))
7106 +#undef strcpy
7107 +#define strcpy(d, s) osl_strcpy((d), (s))
7108 +#undef strncpy
7109 +#define strncpy(d, s, n) osl_strncpy((d), (s), (n))
7110 +#endif
7111 +extern int osl_printf(const char *format, ...);
7112 +extern int osl_sprintf(char *buf, const char *format, ...);
7113 +extern int osl_strcmp(const char *s1, const char *s2);
7114 +extern int osl_strncmp(const char *s1, const char *s2, uint n);
7115 +extern int osl_strlen(const char *s);
7116 +extern char* osl_strcpy(char *d, const char *s);
7117 +extern char* osl_strncpy(char *d, const char *s, uint n);
7118 +
7119 +/* register access macros */
7120 +#if !defined(BCMJTAG)
7121 +#define R_REG(r) ( \
7122 + sizeof(*(r)) == sizeof(uint8) ? osl_readb((volatile uint8*)(r)) : \
7123 + sizeof(*(r)) == sizeof(uint16) ? osl_readw((volatile uint16*)(r)) : \
7124 + osl_readl((volatile uint32*)(r)) \
7125 +)
7126 +#define W_REG(r, v) do { \
7127 + switch (sizeof(*(r))) { \
7128 + case sizeof(uint8): osl_writeb((uint8)(v), (volatile uint8*)(r)); break; \
7129 + case sizeof(uint16): osl_writew((uint16)(v), (volatile uint16*)(r)); break; \
7130 + case sizeof(uint32): osl_writel((uint32)(v), (volatile uint32*)(r)); break; \
7131 + } \
7132 +} while (0)
7133 +#endif
7134 +
7135 +#define AND_REG(r, v) W_REG((r), R_REG(r) & (v))
7136 +#define OR_REG(r, v) W_REG((r), R_REG(r) | (v))
7137 +extern uint8 osl_readb(volatile uint8 *r);
7138 +extern uint16 osl_readw(volatile uint16 *r);
7139 +extern uint32 osl_readl(volatile uint32 *r);
7140 +extern void osl_writeb(uint8 v, volatile uint8 *r);
7141 +extern void osl_writew(uint16 v, volatile uint16 *r);
7142 +extern void osl_writel(uint32 v, volatile uint32 *r);
7143 +
7144 +/* bcopy, bcmp, and bzero */
7145 +extern void bcopy(const void *src, void *dst, int len);
7146 +extern int bcmp(const void *b1, const void *b2, int len);
7147 +extern void bzero(void *b, int len);
7148 +
7149 +/* uncached virtual address */
7150 +#define OSL_UNCACHED(va) osl_uncached((va))
7151 +extern void *osl_uncached(void *va);
7152 +
7153 +/* get processor cycle count */
7154 +#define OSL_GETCYCLES(x) ((x) = osl_getcycles())
7155 +extern uint osl_getcycles(void);
7156 +
7157 +/* dereference an address that may target abort */
7158 +#define BUSPROBE(val, addr) osl_busprobe(&(val), (addr))
7159 +extern int osl_busprobe(uint32 *val, uint32 addr);
7160 +
7161 +/* map/unmap physical to virtual */
7162 +#define REG_MAP(pa, size) osl_reg_map((pa), (size))
7163 +#define REG_UNMAP(va) osl_reg_unmap((va))
7164 +extern void *osl_reg_map(uint32 pa, uint size);
7165 +extern void osl_reg_unmap(void *va);
7166 +
7167 +/* shared (dma-able) memory access macros */
7168 +#define R_SM(r) *(r)
7169 +#define W_SM(r, v) (*(r) = (v))
7170 +#define BZERO_SM(r, len) bzero((r), (len))
7171 +
7172 +/* packet primitives */
7173 +#define PKTGET(osh, len, send) osl_pktget((osh), (len), (send))
7174 +#define PKTFREE(osh, skb, send) osl_pktfree((skb))
7175 +#define PKTDATA(osh, skb) osl_pktdata((osh), (skb))
7176 +#define PKTLEN(osh, skb) osl_pktlen((osh), (skb))
7177 +#define PKTHEADROOM(osh, skb) osl_pktheadroom((osh), (skb))
7178 +#define PKTTAILROOM(osh, skb) osl_pkttailroom((osh), (skb))
7179 +#define PKTNEXT(osh, skb) osl_pktnext((osh), (skb))
7180 +#define PKTSETNEXT(skb, x) osl_pktsetnext((skb), (x))
7181 +#define PKTSETLEN(osh, skb, len) osl_pktsetlen((osh), (skb), (len))
7182 +#define PKTPUSH(osh, skb, bytes) osl_pktpush((osh), (skb), (bytes))
7183 +#define PKTPULL(osh, skb, bytes) osl_pktpull((osh), (skb), (bytes))
7184 +#define PKTDUP(osh, skb) osl_pktdup((osh), (skb))
7185 +#define PKTCOOKIE(skb) osl_pktcookie((skb))
7186 +#define PKTSETCOOKIE(skb, x) osl_pktsetcookie((skb), (x))
7187 +#define PKTLINK(skb) osl_pktlink((skb))
7188 +#define PKTSETLINK(skb, x) osl_pktsetlink((skb), (x))
7189 +#define PKTPRIO(skb) osl_pktprio((skb))
7190 +#define PKTSETPRIO(skb, x) osl_pktsetprio((skb), (x))
7191 +extern void *osl_pktget(osl_t *osh, uint len, bool send);
7192 +extern void osl_pktfree(void *skb);
7193 +extern uchar *osl_pktdata(osl_t *osh, void *skb);
7194 +extern uint osl_pktlen(osl_t *osh, void *skb);
7195 +extern uint osl_pktheadroom(osl_t *osh, void *skb);
7196 +extern uint osl_pkttailroom(osl_t *osh, void *skb);
7197 +extern void *osl_pktnext(osl_t *osh, void *skb);
7198 +extern void osl_pktsetnext(void *skb, void *x);
7199 +extern void osl_pktsetlen(osl_t *osh, void *skb, uint len);
7200 +extern uchar *osl_pktpush(osl_t *osh, void *skb, int bytes);
7201 +extern uchar *osl_pktpull(osl_t *osh, void *skb, int bytes);
7202 +extern void *osl_pktdup(osl_t *osh, void *skb);
7203 +extern void *osl_pktcookie(void *skb);
7204 +extern void osl_pktsetcookie(void *skb, void *x);
7205 +extern void *osl_pktlink(void *skb);
7206 +extern void osl_pktsetlink(void *skb, void *x);
7207 +extern uint osl_pktprio(void *skb);
7208 +extern void osl_pktsetprio(void *skb, uint x);
7209 +
7210 +#endif /* BINOSL */
7211 +
7212 +#define OSL_ERROR(bcmerror) osl_error(bcmerror)
7213 +extern int osl_error(int bcmerror);
7214 +
7215 +/* the largest reasonable packet buffer driver uses for ethernet MTU in bytes */
7216 +#define PKTBUFSZ 2048
7217 +
7218 +#endif /* _linux_osl_h_ */
7219 diff -urN linux.old/arch/mips/bcm947xx/include/linuxver.h linux.dev/arch/mips/bcm947xx/include/linuxver.h
7220 --- linux.old/arch/mips/bcm947xx/include/linuxver.h 1970-01-01 01:00:00.000000000 +0100
7221 +++ linux.dev/arch/mips/bcm947xx/include/linuxver.h 2005-12-15 16:02:45.467929000 +0100
7222 @@ -0,0 +1,389 @@
7223 +/*
7224 + * Linux-specific abstractions to gain some independence from linux kernel versions.
7225 + * Pave over some 2.2 versus 2.4 versus 2.6 kernel differences.
7226 + *
7227 + * Copyright 2005, Broadcom Corporation
7228 + * All Rights Reserved.
7229 + *
7230 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7231 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7232 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7233 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7234 + *
7235 + * $Id$
7236 + */
7237 +
7238 +#ifndef _linuxver_h_
7239 +#define _linuxver_h_
7240 +
7241 +#include <linux/config.h>
7242 +#include <linux/version.h>
7243 +
7244 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,0))
7245 +/* __NO_VERSION__ must be defined for all linkables except one in 2.2 */
7246 +#ifdef __UNDEF_NO_VERSION__
7247 +#undef __NO_VERSION__
7248 +#else
7249 +#define __NO_VERSION__
7250 +#endif
7251 +#endif
7252 +
7253 +#if defined(MODULE) && defined(MODVERSIONS)
7254 +#include <linux/modversions.h>
7255 +#endif
7256 +
7257 +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2,5,0)
7258 +#include <linux/moduleparam.h>
7259 +#endif
7260 +
7261 +
7262 +#if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
7263 +#define module_param(_name_, _type_, _perm_) MODULE_PARM(_name_, "i")
7264 +#define module_param_string(_name_, _string_, _size_, _perm_) MODULE_PARM(_string_, "c" __MODULE_STRING(_size_))
7265 +#endif
7266 +
7267 +/* linux/malloc.h is deprecated, use linux/slab.h instead. */
7268 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,9))
7269 +#include <linux/malloc.h>
7270 +#else
7271 +#include <linux/slab.h>
7272 +#endif
7273 +
7274 +#include <linux/types.h>
7275 +#include <linux/init.h>
7276 +#include <linux/mm.h>
7277 +#include <linux/string.h>
7278 +#include <linux/pci.h>
7279 +#include <linux/interrupt.h>
7280 +#include <linux/netdevice.h>
7281 +#include <asm/io.h>
7282 +
7283 +#if (LINUX_VERSION_CODE > KERNEL_VERSION(2,5,41))
7284 +#include <linux/workqueue.h>
7285 +#else
7286 +#include <linux/tqueue.h>
7287 +#ifndef work_struct
7288 +#define work_struct tq_struct
7289 +#endif
7290 +#ifndef INIT_WORK
7291 +#define INIT_WORK(_work, _func, _data) INIT_TQUEUE((_work), (_func), (_data))
7292 +#endif
7293 +#ifndef schedule_work
7294 +#define schedule_work(_work) schedule_task((_work))
7295 +#endif
7296 +#ifndef flush_scheduled_work
7297 +#define flush_scheduled_work() flush_scheduled_tasks()
7298 +#endif
7299 +#endif
7300 +
7301 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0))
7302 +/* Some distributions have their own 2.6.x compatibility layers */
7303 +#ifndef IRQ_NONE
7304 +typedef void irqreturn_t;
7305 +#define IRQ_NONE
7306 +#define IRQ_HANDLED
7307 +#define IRQ_RETVAL(x)
7308 +#endif
7309 +#else
7310 +typedef irqreturn_t (*FN_ISR) (int irq, void *dev_id, struct pt_regs *ptregs);
7311 +#endif
7312 +
7313 +#ifndef __exit
7314 +#define __exit
7315 +#endif
7316 +#ifndef __devexit
7317 +#define __devexit
7318 +#endif
7319 +#ifndef __devinit
7320 +#define __devinit __init
7321 +#endif
7322 +#ifndef __devinitdata
7323 +#define __devinitdata
7324 +#endif
7325 +#ifndef __devexit_p
7326 +#define __devexit_p(x) x
7327 +#endif
7328 +
7329 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,0))
7330 +
7331 +#define pci_get_drvdata(dev) (dev)->sysdata
7332 +#define pci_set_drvdata(dev, value) (dev)->sysdata=(value)
7333 +
7334 +/*
7335 + * New-style (2.4.x) PCI/hot-pluggable PCI/CardBus registration
7336 + */
7337 +
7338 +struct pci_device_id {
7339 + unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
7340 + unsigned int subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */
7341 + unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */
7342 + unsigned long driver_data; /* Data private to the driver */
7343 +};
7344 +
7345 +struct pci_driver {
7346 + struct list_head node;
7347 + char *name;
7348 + const struct pci_device_id *id_table; /* NULL if wants all devices */
7349 + int (*probe)(struct pci_dev *dev, const struct pci_device_id *id); /* New device inserted */
7350 + void (*remove)(struct pci_dev *dev); /* Device removed (NULL if not a hot-plug capable driver) */
7351 + void (*suspend)(struct pci_dev *dev); /* Device suspended */
7352 + void (*resume)(struct pci_dev *dev); /* Device woken up */
7353 +};
7354 +
7355 +#define MODULE_DEVICE_TABLE(type, name)
7356 +#define PCI_ANY_ID (~0)
7357 +
7358 +/* compatpci.c */
7359 +#define pci_module_init pci_register_driver
7360 +extern int pci_register_driver(struct pci_driver *drv);
7361 +extern void pci_unregister_driver(struct pci_driver *drv);
7362 +
7363 +#endif /* PCI registration */
7364 +
7365 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,2,18))
7366 +#ifdef MODULE
7367 +#define module_init(x) int init_module(void) { return x(); }
7368 +#define module_exit(x) void cleanup_module(void) { x(); }
7369 +#else
7370 +#define module_init(x) __initcall(x);
7371 +#define module_exit(x) __exitcall(x);
7372 +#endif
7373 +#endif
7374 +
7375 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,48))
7376 +#define list_for_each(pos, head) \
7377 + for (pos = (head)->next; pos != (head); pos = pos->next)
7378 +#endif
7379 +
7380 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,13))
7381 +#define pci_resource_start(dev, bar) ((dev)->base_address[(bar)])
7382 +#elif (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,44))
7383 +#define pci_resource_start(dev, bar) ((dev)->resource[(bar)].start)
7384 +#endif
7385 +
7386 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,23))
7387 +#define pci_enable_device(dev) do { } while (0)
7388 +#endif
7389 +
7390 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,14))
7391 +#define net_device device
7392 +#endif
7393 +
7394 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,42))
7395 +
7396 +/*
7397 + * DMA mapping
7398 + *
7399 + * See linux/Documentation/DMA-mapping.txt
7400 + */
7401 +
7402 +#ifndef PCI_DMA_TODEVICE
7403 +#define PCI_DMA_TODEVICE 1
7404 +#define PCI_DMA_FROMDEVICE 2
7405 +#endif
7406 +
7407 +typedef u32 dma_addr_t;
7408 +
7409 +/* Pure 2^n version of get_order */
7410 +static inline int get_order(unsigned long size)
7411 +{
7412 + int order;
7413 +
7414 + size = (size-1) >> (PAGE_SHIFT-1);
7415 + order = -1;
7416 + do {
7417 + size >>= 1;
7418 + order++;
7419 + } while (size);
7420 + return order;
7421 +}
7422 +
7423 +static inline void *pci_alloc_consistent(struct pci_dev *hwdev, size_t size,
7424 + dma_addr_t *dma_handle)
7425 +{
7426 + void *ret;
7427 + int gfp = GFP_ATOMIC | GFP_DMA;
7428 +
7429 + ret = (void *)__get_free_pages(gfp, get_order(size));
7430 +
7431 + if (ret != NULL) {
7432 + memset(ret, 0, size);
7433 + *dma_handle = virt_to_bus(ret);
7434 + }
7435 + return ret;
7436 +}
7437 +static inline void pci_free_consistent(struct pci_dev *hwdev, size_t size,
7438 + void *vaddr, dma_addr_t dma_handle)
7439 +{
7440 + free_pages((unsigned long)vaddr, get_order(size));
7441 +}
7442 +#ifdef ILSIM
7443 +extern uint pci_map_single(void *dev, void *va, uint size, int direction);
7444 +extern void pci_unmap_single(void *dev, uint pa, uint size, int direction);
7445 +#else
7446 +#define pci_map_single(cookie, address, size, dir) virt_to_bus(address)
7447 +#define pci_unmap_single(cookie, address, size, dir)
7448 +#endif
7449 +
7450 +#endif /* DMA mapping */
7451 +
7452 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,3,43))
7453 +
7454 +#define dev_kfree_skb_any(a) dev_kfree_skb(a)
7455 +#define netif_down(dev) do { (dev)->start = 0; } while(0)
7456 +
7457 +/* pcmcia-cs provides its own netdevice compatibility layer */
7458 +#ifndef _COMPAT_NETDEVICE_H
7459 +
7460 +/*
7461 + * SoftNet
7462 + *
7463 + * For pre-softnet kernels we need to tell the upper layer not to
7464 + * re-enter start_xmit() while we are in there. However softnet
7465 + * guarantees not to enter while we are in there so there is no need
7466 + * to do the netif_stop_queue() dance unless the transmit queue really
7467 + * gets stuck. This should also improve performance according to tests
7468 + * done by Aman Singla.
7469 + */
7470 +
7471 +#define dev_kfree_skb_irq(a) dev_kfree_skb(a)
7472 +#define netif_wake_queue(dev) do { clear_bit(0, &(dev)->tbusy); mark_bh(NET_BH); } while(0)
7473 +#define netif_stop_queue(dev) set_bit(0, &(dev)->tbusy)
7474 +
7475 +static inline void netif_start_queue(struct net_device *dev)
7476 +{
7477 + dev->tbusy = 0;
7478 + dev->interrupt = 0;
7479 + dev->start = 1;
7480 +}
7481 +
7482 +#define netif_queue_stopped(dev) (dev)->tbusy
7483 +#define netif_running(dev) (dev)->start
7484 +
7485 +#endif /* _COMPAT_NETDEVICE_H */
7486 +
7487 +#define netif_device_attach(dev) netif_start_queue(dev)
7488 +#define netif_device_detach(dev) netif_stop_queue(dev)
7489 +
7490 +/* 2.4.x renamed bottom halves to tasklets */
7491 +#define tasklet_struct tq_struct
7492 +static inline void tasklet_schedule(struct tasklet_struct *tasklet)
7493 +{
7494 + queue_task(tasklet, &tq_immediate);
7495 + mark_bh(IMMEDIATE_BH);
7496 +}
7497 +
7498 +static inline void tasklet_init(struct tasklet_struct *tasklet,
7499 + void (*func)(unsigned long),
7500 + unsigned long data)
7501 +{
7502 + tasklet->next = NULL;
7503 + tasklet->sync = 0;
7504 + tasklet->routine = (void (*)(void *))func;
7505 + tasklet->data = (void *)data;
7506 +}
7507 +#define tasklet_kill(tasklet) {do{} while(0);}
7508 +
7509 +/* 2.4.x introduced del_timer_sync() */
7510 +#define del_timer_sync(timer) del_timer(timer)
7511 +
7512 +#else
7513 +
7514 +#define netif_down(dev)
7515 +
7516 +#endif /* SoftNet */
7517 +
7518 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,3))
7519 +
7520 +/*
7521 + * Emit code to initialise a tq_struct's routine and data pointers
7522 + */
7523 +#define PREPARE_TQUEUE(_tq, _routine, _data) \
7524 + do { \
7525 + (_tq)->routine = _routine; \
7526 + (_tq)->data = _data; \
7527 + } while (0)
7528 +
7529 +/*
7530 + * Emit code to initialise all of a tq_struct
7531 + */
7532 +#define INIT_TQUEUE(_tq, _routine, _data) \
7533 + do { \
7534 + INIT_LIST_HEAD(&(_tq)->list); \
7535 + (_tq)->sync = 0; \
7536 + PREPARE_TQUEUE((_tq), (_routine), (_data)); \
7537 + } while (0)
7538 +
7539 +#endif
7540 +
7541 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,6))
7542 +
7543 +/* Power management related routines */
7544 +
7545 +static inline int
7546 +pci_save_state(struct pci_dev *dev, u32 *buffer)
7547 +{
7548 + int i;
7549 + if (buffer) {
7550 + for (i = 0; i < 16; i++)
7551 + pci_read_config_dword(dev, i * 4,&buffer[i]);
7552 + }
7553 + return 0;
7554 +}
7555 +
7556 +static inline int
7557 +pci_restore_state(struct pci_dev *dev, u32 *buffer)
7558 +{
7559 + int i;
7560 +
7561 + if (buffer) {
7562 + for (i = 0; i < 16; i++)
7563 + pci_write_config_dword(dev,i * 4, buffer[i]);
7564 + }
7565 + /*
7566 + * otherwise, write the context information we know from bootup.
7567 + * This works around a problem where warm-booting from Windows
7568 + * combined with a D3(hot)->D0 transition causes PCI config
7569 + * header data to be forgotten.
7570 + */
7571 + else {
7572 + for (i = 0; i < 6; i ++)
7573 + pci_write_config_dword(dev,
7574 + PCI_BASE_ADDRESS_0 + (i * 4),
7575 + pci_resource_start(dev, i));
7576 + pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
7577 + }
7578 + return 0;
7579 +}
7580 +
7581 +#endif /* PCI power management */
7582 +
7583 +/* Old cp0 access macros deprecated in 2.4.19 */
7584 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,4,19))
7585 +#define read_c0_count() read_32bit_cp0_register(CP0_COUNT)
7586 +#endif
7587 +
7588 +/* Module refcount handled internally in 2.6.x */
7589 +#ifndef SET_MODULE_OWNER
7590 +#define SET_MODULE_OWNER(dev) do {} while (0)
7591 +#define OLD_MOD_INC_USE_COUNT MOD_INC_USE_COUNT
7592 +#define OLD_MOD_DEC_USE_COUNT MOD_DEC_USE_COUNT
7593 +#else
7594 +#define OLD_MOD_INC_USE_COUNT do {} while (0)
7595 +#define OLD_MOD_DEC_USE_COUNT do {} while (0)
7596 +#endif
7597 +
7598 +#ifndef SET_NETDEV_DEV
7599 +#define SET_NETDEV_DEV(net, pdev) do {} while (0)
7600 +#endif
7601 +
7602 +#ifndef HAVE_FREE_NETDEV
7603 +#define free_netdev(dev) kfree(dev)
7604 +#endif
7605 +
7606 +#if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0))
7607 +/* struct packet_type redefined in 2.6.x */
7608 +#define af_packet_priv data
7609 +#endif
7610 +
7611 +#endif /* _linuxver_h_ */
7612 diff -urN linux.old/arch/mips/bcm947xx/include/mipsinc.h linux.dev/arch/mips/bcm947xx/include/mipsinc.h
7613 --- linux.old/arch/mips/bcm947xx/include/mipsinc.h 1970-01-01 01:00:00.000000000 +0100
7614 +++ linux.dev/arch/mips/bcm947xx/include/mipsinc.h 2005-12-15 16:47:29.886633750 +0100
7615 @@ -0,0 +1,552 @@
7616 +/*
7617 + * HND Run Time Environment for standalone MIPS programs.
7618 + *
7619 + * Copyright 2005, Broadcom Corporation
7620 + * All Rights Reserved.
7621 + *
7622 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
7623 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
7624 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
7625 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
7626 + *
7627 + * $Id$
7628 + */
7629 +
7630 +#ifndef _MISPINC_H
7631 +#define _MISPINC_H
7632 +
7633 +
7634 +/* MIPS defines */
7635 +
7636 +#ifdef _LANGUAGE_ASSEMBLY
7637 +
7638 +/*
7639 + * Symbolic register names for 32 bit ABI
7640 + */
7641 +#define zero $0 /* wired zero */
7642 +#define AT $1 /* assembler temp - uppercase because of ".set at" */
7643 +#define v0 $2 /* return value */
7644 +#define v1 $3
7645 +#define a0 $4 /* argument registers */
7646 +#define a1 $5
7647 +#define a2 $6
7648 +#define a3 $7
7649 +#define t0 $8 /* caller saved */
7650 +#define t1 $9
7651 +#define t2 $10
7652 +#define t3 $11
7653 +#define t4 $12
7654 +#define t5 $13
7655 +#define t6 $14
7656 +#define t7 $15
7657 +#define s0 $16 /* callee saved */
7658 +#define s1 $17
7659 +#define s2 $18
7660 +#define s3 $19
7661 +#define s4 $20
7662 +#define s5 $21
7663 +#define s6 $22
7664 +#define s7 $23
7665 +#define t8 $24 /* caller saved */
7666 +#define t9 $25
7667 +#define jp $25 /* PIC jump register */
7668 +#define k0 $26 /* kernel scratch */
7669 +#define k1 $27
7670 +#define gp $28 /* global pointer */
7671 +#define sp $29 /* stack pointer */
7672 +#define fp $30 /* frame pointer */
7673 +#define s8 $30 /* same like fp! */
7674 +#define ra $31 /* return address */
7675 +
7676 +
7677 +/*
7678 + * CP0 Registers
7679 + */
7680 +
7681 +#define C0_INX $0
7682 +#define C0_RAND $1
7683 +#define C0_TLBLO0 $2
7684 +#define C0_TLBLO C0_TLBLO0
7685 +#define C0_TLBLO1 $3
7686 +#define C0_CTEXT $4
7687 +#define C0_PGMASK $5
7688 +#define C0_WIRED $6
7689 +#define C0_BADVADDR $8
7690 +#define C0_COUNT $9
7691 +#define C0_TLBHI $10
7692 +#define C0_COMPARE $11
7693 +#define C0_SR $12
7694 +#define C0_STATUS C0_SR
7695 +#define C0_CAUSE $13
7696 +#define C0_EPC $14
7697 +#define C0_PRID $15
7698 +#define C0_CONFIG $16
7699 +#define C0_LLADDR $17
7700 +#define C0_WATCHLO $18
7701 +#define C0_WATCHHI $19
7702 +#define C0_XCTEXT $20
7703 +#define C0_DIAGNOSTIC $22
7704 +#define C0_BROADCOM C0_DIAGNOSTIC
7705 +#define C0_PERFORMANCE $25
7706 +#define C0_ECC $26
7707 +#define C0_CACHEERR $27
7708 +#define C0_TAGLO $28
7709 +#define C0_TAGHI $29
7710 +#define C0_ERREPC $30
7711 +#define C0_DESAVE $31
7712 +
7713 +/*
7714 + * LEAF - declare leaf routine
7715 + */
7716 +#define LEAF(symbol) \
7717 + .globl symbol; \
7718 + .align 2; \
7719 + .type symbol,@function; \
7720 + .ent symbol,0; \
7721 +symbol: .frame sp,0,ra
7722 +
7723 +/*
7724 + * END - mark end of function
7725 + */
7726 +#define END(function) \
7727 + .end function; \
7728 + .size function,.-function
7729 +
7730 +#define _ULCAST_
7731 +
7732 +#else
7733 +
7734 +/*
7735 + * The following macros are especially useful for __asm__
7736 + * inline assembler.
7737 + */
7738 +#ifndef __STR
7739 +#define __STR(x) #x
7740 +#endif
7741 +#ifndef STR
7742 +#define STR(x) __STR(x)
7743 +#endif
7744 +
7745 +#define _ULCAST_ (unsigned long)
7746 +
7747 +
7748 +/*
7749 + * CP0 Registers
7750 + */
7751 +
7752 +#define C0_INX 0 /* CP0: TLB Index */
7753 +#define C0_RAND 1 /* CP0: TLB Random */
7754 +#define C0_TLBLO0 2 /* CP0: TLB EntryLo0 */
7755 +#define C0_TLBLO C0_TLBLO0 /* CP0: TLB EntryLo0 */
7756 +#define C0_TLBLO1 3 /* CP0: TLB EntryLo1 */
7757 +#define C0_CTEXT 4 /* CP0: Context */
7758 +#define C0_PGMASK 5 /* CP0: TLB PageMask */
7759 +#define C0_WIRED 6 /* CP0: TLB Wired */
7760 +#define C0_BADVADDR 8 /* CP0: Bad Virtual Address */
7761 +#define C0_COUNT 9 /* CP0: Count */
7762 +#define C0_TLBHI 10 /* CP0: TLB EntryHi */
7763 +#define C0_COMPARE 11 /* CP0: Compare */
7764 +#define C0_SR 12 /* CP0: Processor Status */
7765 +#define C0_STATUS C0_SR /* CP0: Processor Status */
7766 +#define C0_CAUSE 13 /* CP0: Exception Cause */
7767 +#define C0_EPC 14 /* CP0: Exception PC */
7768 +#define C0_PRID 15 /* CP0: Processor Revision Indentifier */
7769 +#define C0_CONFIG 16 /* CP0: Config */
7770 +#define C0_LLADDR 17 /* CP0: LLAddr */
7771 +#define C0_WATCHLO 18 /* CP0: WatchpointLo */
7772 +#define C0_WATCHHI 19 /* CP0: WatchpointHi */
7773 +#define C0_XCTEXT 20 /* CP0: XContext */
7774 +#define C0_DIAGNOSTIC 22 /* CP0: Diagnostic */
7775 +#define C0_BROADCOM C0_DIAGNOSTIC /* CP0: Broadcom Register */
7776 +#define C0_PERFORMANCE 25 /* CP0: Performance Counter/Control Registers */
7777 +#define C0_ECC 26 /* CP0: ECC */
7778 +#define C0_CACHEERR 27 /* CP0: CacheErr */
7779 +#define C0_TAGLO 28 /* CP0: TagLo */
7780 +#define C0_TAGHI 29 /* CP0: TagHi */
7781 +#define C0_ERREPC 30 /* CP0: ErrorEPC */
7782 +#define C0_DESAVE 31 /* CP0: DebugSave */
7783 +
7784 +#endif /* _LANGUAGE_ASSEMBLY */
7785 +
7786 +/*
7787 + * Memory segments (32bit kernel mode addresses)
7788 + */
7789 +#undef KUSEG
7790 +#undef KSEG0
7791 +#undef KSEG1
7792 +#undef KSEG2
7793 +#undef KSEG3
7794 +#define KUSEG 0x00000000
7795 +#define KSEG0 0x80000000
7796 +#define KSEG1 0xa0000000
7797 +#define KSEG2 0xc0000000
7798 +#define KSEG3 0xe0000000
7799 +#define PHYSADDR_MASK 0x1fffffff
7800 +
7801 +/*
7802 + * Map an address to a certain kernel segment
7803 + */
7804 +#undef PHYSADDR
7805 +#undef KSEG0ADDR
7806 +#undef KSEG1ADDR
7807 +#undef KSEG2ADDR
7808 +#undef KSEG3ADDR
7809 +
7810 +#define PHYSADDR(a) (_ULCAST_(a) & PHYSADDR_MASK)
7811 +#define KSEG0ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG0)
7812 +#define KSEG1ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG1)
7813 +#define KSEG2ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG2)
7814 +#define KSEG3ADDR(a) ((_ULCAST_(a) & PHYSADDR_MASK) | KSEG3)
7815 +
7816 +
7817 +#ifndef Index_Invalidate_I
7818 +/*
7819 + * Cache Operations
7820 + */
7821 +#define Index_Invalidate_I 0x00
7822 +#define Index_Writeback_Inv_D 0x01
7823 +#define Index_Invalidate_SI 0x02
7824 +#define Index_Writeback_Inv_SD 0x03
7825 +#define Index_Load_Tag_I 0x04
7826 +#define Index_Load_Tag_D 0x05
7827 +#define Index_Load_Tag_SI 0x06
7828 +#define Index_Load_Tag_SD 0x07
7829 +#define Index_Store_Tag_I 0x08
7830 +#define Index_Store_Tag_D 0x09
7831 +#define Index_Store_Tag_SI 0x0A
7832 +#define Index_Store_Tag_SD 0x0B
7833 +#define Create_Dirty_Excl_D 0x0d
7834 +#define Create_Dirty_Excl_SD 0x0f
7835 +#define Hit_Invalidate_I 0x10
7836 +#define Hit_Invalidate_D 0x11
7837 +#define Hit_Invalidate_SI 0x12
7838 +#define Hit_Invalidate_SD 0x13
7839 +#define Fill_I 0x14
7840 +#define Hit_Writeback_Inv_D 0x15
7841 + /* 0x16 is unused */
7842 +#define Hit_Writeback_Inv_SD 0x17
7843 +#define R5K_Page_Invalidate_S 0x17
7844 +#define Hit_Writeback_I 0x18
7845 +#define Hit_Writeback_D 0x19
7846 + /* 0x1a is unused */
7847 +#define Hit_Writeback_SD 0x1b
7848 + /* 0x1c is unused */
7849 + /* 0x1e is unused */
7850 +#define Hit_Set_Virtual_SI 0x1e
7851 +#define Hit_Set_Virtual_SD 0x1f
7852 +#endif
7853 +
7854 +
7855 +/*
7856 + * R4x00 interrupt enable / cause bits
7857 + */
7858 +#define IE_SW0 (_ULCAST_(1) << 8)
7859 +#define IE_SW1 (_ULCAST_(1) << 9)
7860 +#define IE_IRQ0 (_ULCAST_(1) << 10)
7861 +#define IE_IRQ1 (_ULCAST_(1) << 11)
7862 +#define IE_IRQ2 (_ULCAST_(1) << 12)
7863 +#define IE_IRQ3 (_ULCAST_(1) << 13)
7864 +#define IE_IRQ4 (_ULCAST_(1) << 14)
7865 +#define IE_IRQ5 (_ULCAST_(1) << 15)
7866 +
7867 +#ifndef ST0_UM
7868 +/*
7869 + * Bitfields in the mips32 cp0 status register
7870 + */
7871 +#define ST0_IE 0x00000001
7872 +#define ST0_EXL 0x00000002
7873 +#define ST0_ERL 0x00000004
7874 +#define ST0_UM 0x00000010
7875 +#define ST0_SWINT0 0x00000100
7876 +#define ST0_SWINT1 0x00000200
7877 +#define ST0_HWINT0 0x00000400
7878 +#define ST0_HWINT1 0x00000800
7879 +#define ST0_HWINT2 0x00001000
7880 +#define ST0_HWINT3 0x00002000
7881 +#define ST0_HWINT4 0x00004000
7882 +#define ST0_HWINT5 0x00008000
7883 +#define ST0_IM 0x0000ff00
7884 +#define ST0_NMI 0x00080000
7885 +#define ST0_SR 0x00100000
7886 +#define ST0_TS 0x00200000
7887 +#define ST0_BEV 0x00400000
7888 +#define ST0_RE 0x02000000
7889 +#define ST0_RP 0x08000000
7890 +#define ST0_CU 0xf0000000
7891 +#define ST0_CU0 0x10000000
7892 +#define ST0_CU1 0x20000000
7893 +#define ST0_CU2 0x40000000
7894 +#define ST0_CU3 0x80000000
7895 +#endif
7896 +
7897 +
7898 +/*
7899 + * Bitfields in the mips32 cp0 cause register
7900 + */
7901 +#define C_EXC 0x0000007c
7902 +#define C_EXC_SHIFT 2
7903 +#define C_INT 0x0000ff00
7904 +#define C_INT_SHIFT 8
7905 +#define C_SW0 (_ULCAST_(1) << 8)
7906 +#define C_SW1 (_ULCAST_(1) << 9)
7907 +#define C_IRQ0 (_ULCAST_(1) << 10)
7908 +#define C_IRQ1 (_ULCAST_(1) << 11)
7909 +#define C_IRQ2 (_ULCAST_(1) << 12)
7910 +#define C_IRQ3 (_ULCAST_(1) << 13)
7911 +#define C_IRQ4 (_ULCAST_(1) << 14)
7912 +#define C_IRQ5 (_ULCAST_(1) << 15)
7913 +#define C_WP 0x00400000
7914 +#define C_IV 0x00800000
7915 +#define C_CE 0x30000000
7916 +#define C_CE_SHIFT 28
7917 +#define C_BD 0x80000000
7918 +
7919 +/* Values in C_EXC */
7920 +#define EXC_INT 0
7921 +#define EXC_TLBM 1
7922 +#define EXC_TLBL 2
7923 +#define EXC_TLBS 3
7924 +#define EXC_AEL 4
7925 +#define EXC_AES 5
7926 +#define EXC_IBE 6
7927 +#define EXC_DBE 7
7928 +#define EXC_SYS 8
7929 +#define EXC_BPT 9
7930 +#define EXC_RI 10
7931 +#define EXC_CU 11
7932 +#define EXC_OV 12
7933 +#define EXC_TR 13
7934 +#define EXC_WATCH 23
7935 +#define EXC_MCHK 24
7936 +
7937 +
7938 +/*
7939 + * Bits in the cp0 config register.
7940 + */
7941 +#define CONF_CM_CACHABLE_NO_WA 0
7942 +#define CONF_CM_CACHABLE_WA 1
7943 +#define CONF_CM_UNCACHED 2
7944 +#define CONF_CM_CACHABLE_NONCOHERENT 3
7945 +#define CONF_CM_CACHABLE_CE 4
7946 +#define CONF_CM_CACHABLE_COW 5
7947 +#define CONF_CM_CACHABLE_CUW 6
7948 +#define CONF_CM_CACHABLE_ACCELERATED 7
7949 +#define CONF_CM_CMASK 7
7950 +#define CONF_CU (_ULCAST_(1) << 3)
7951 +#define CONF_DB (_ULCAST_(1) << 4)
7952 +#define CONF_IB (_ULCAST_(1) << 5)
7953 +#define CONF_SE (_ULCAST_(1) << 12)
7954 +#define CONF_SC (_ULCAST_(1) << 17)
7955 +#define CONF_AC (_ULCAST_(1) << 23)
7956 +#define CONF_HALT (_ULCAST_(1) << 25)
7957 +
7958 +
7959 +/*
7960 + * Bits in the cp0 config register select 1.
7961 + */
7962 +#define CONF1_FP 0x00000001 /* FPU present */
7963 +#define CONF1_EP 0x00000002 /* EJTAG present */
7964 +#define CONF1_CA 0x00000004 /* mips16 implemented */
7965 +#define CONF1_WR 0x00000008 /* Watch registers present */
7966 +#define CONF1_PC 0x00000010 /* Performance counters present */
7967 +#define CONF1_DA_SHIFT 7 /* D$ associativity */
7968 +#define CONF1_DA_MASK 0x00000380
7969 +#define CONF1_DA_BASE 1
7970 +#define CONF1_DL_SHIFT 10 /* D$ line size */
7971 +#define CONF1_DL_MASK 0x00001c00
7972 +#define CONF1_DL_BASE 2
7973 +#define CONF1_DS_SHIFT 13 /* D$ sets/way */
7974 +#define CONF1_DS_MASK 0x0000e000
7975 +#define CONF1_DS_BASE 64
7976 +#define CONF1_IA_SHIFT 16 /* I$ associativity */
7977 +#define CONF1_IA_MASK 0x00070000
7978 +#define CONF1_IA_BASE 1
7979 +#define CONF1_IL_SHIFT 19 /* I$ line size */
7980 +#define CONF1_IL_MASK 0x00380000
7981 +#define CONF1_IL_BASE 2
7982 +#define CONF1_IS_SHIFT 22 /* Instruction cache sets/way */
7983 +#define CONF1_IS_MASK 0x01c00000
7984 +#define CONF1_IS_BASE 64
7985 +#define CONF1_MS_MASK 0x7e000000 /* Number of tlb entries */
7986 +#define CONF1_MS_SHIFT 25
7987 +
7988 +/* PRID register */
7989 +#define PRID_COPT_MASK 0xff000000
7990 +#define PRID_COMP_MASK 0x00ff0000
7991 +#define PRID_IMP_MASK 0x0000ff00
7992 +#define PRID_REV_MASK 0x000000ff
7993 +
7994 +#define PRID_COMP_LEGACY 0x000000
7995 +#define PRID_COMP_MIPS 0x010000
7996 +#define PRID_COMP_BROADCOM 0x020000
7997 +#define PRID_COMP_ALCHEMY 0x030000
7998 +#define PRID_COMP_SIBYTE 0x040000
7999 +#define PRID_IMP_BCM4710 0x4000
8000 +#define PRID_IMP_BCM3302 0x9000
8001 +#define PRID_IMP_BCM3303 0x9100
8002 +
8003 +#define PRID_IMP_UNKNOWN 0xff00
8004 +
8005 +#define BCM330X(id) \
8006 + (((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3302)) \
8007 + || ((id & (PRID_COMP_MASK | PRID_IMP_MASK)) == (PRID_COMP_BROADCOM | PRID_IMP_BCM3303)))
8008 +
8009 +/* Bits in C0_BROADCOM */
8010 +#define BRCM_PFC_AVAIL 0x20000000 /* PFC is available */
8011 +#define BRCM_DC_ENABLE 0x40000000 /* Enable Data $ */
8012 +#define BRCM_IC_ENABLE 0x80000000 /* Enable Instruction $ */
8013 +#define BRCM_PFC_ENABLE 0x00400000 /* Obsolete? Enable PFC (at least on 4310) */
8014 +
8015 +/* PreFetch Cache aka Read Ahead Cache */
8016 +
8017 +#define PFC_CR0 0xff400000 /* control reg 0 */
8018 +#define PFC_CR1 0xff400004 /* control reg 1 */
8019 +
8020 +/* PFC operations */
8021 +#define PFC_I 0x00000001 /* Enable PFC use for instructions */
8022 +#define PFC_D 0x00000002 /* Enable PFC use for data */
8023 +#define PFC_PFI 0x00000004 /* Enable seq. prefetch for instructions */
8024 +#define PFC_PFD 0x00000008 /* Enable seq. prefetch for data */
8025 +#define PFC_CINV 0x00000010 /* Enable selective (i/d) cacheop flushing */
8026 +#define PFC_NCH 0x00000020 /* Disable flushing based on cacheops */
8027 +#define PFC_DPF 0x00000040 /* Enable directional prefetching */
8028 +#define PFC_FLUSH 0x00000100 /* Flush the PFC */
8029 +#define PFC_BRR 0x40000000 /* Bus error indication */
8030 +#define PFC_PWR 0x80000000 /* Disable power saving (clock gating) */
8031 +
8032 +/* Handy defaults */
8033 +#define PFC_DISABLED 0
8034 +#define PFC_AUTO 0xffffffff /* auto select the default mode */
8035 +#define PFC_INST (PFC_I | PFC_PFI | PFC_CINV)
8036 +#define PFC_INST_NOPF (PFC_I | PFC_CINV)
8037 +#define PFC_DATA (PFC_D | PFC_PFD | PFC_CINV)
8038 +#define PFC_DATA_NOPF (PFC_D | PFC_CINV)
8039 +#define PFC_I_AND_D (PFC_INST | PFC_DATA)
8040 +#define PFC_I_AND_D_NOPF (PFC_INST_NOPF | PFC_DATA_NOPF)
8041 +
8042 +
8043 +/*
8044 + * These are the UART port assignments, expressed as offsets from the base
8045 + * register. These assignments should hold for any serial port based on
8046 + * a 8250, 16450, or 16550(A).
8047 + */
8048 +
8049 +#define UART_RX 0 /* In: Receive buffer (DLAB=0) */
8050 +#define UART_TX 0 /* Out: Transmit buffer (DLAB=0) */
8051 +#define UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */
8052 +#define UART_DLM 1 /* Out: Divisor Latch High (DLAB=1) */
8053 +#define UART_LCR 3 /* Out: Line Control Register */
8054 +#define UART_MCR 4 /* Out: Modem Control Register */
8055 +#define UART_LSR 5 /* In: Line Status Register */
8056 +#define UART_MSR 6 /* In: Modem Status Register */
8057 +#define UART_SCR 7 /* I/O: Scratch Register */
8058 +#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
8059 +#define UART_LCR_WLEN8 0x03 /* Wordlength: 8 bits */
8060 +#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
8061 +#define UART_LSR_THRE 0x20 /* Transmit-hold-register empty */
8062 +#define UART_LSR_RXRDY 0x01 /* Receiver ready */
8063 +
8064 +
8065 +#ifndef _LANGUAGE_ASSEMBLY
8066 +
8067 +/*
8068 + * Macros to access the system control coprocessor
8069 + */
8070 +
8071 +#define MFC0(source, sel) \
8072 +({ \
8073 + int __res; \
8074 + __asm__ __volatile__( \
8075 + ".set\tnoreorder\n\t" \
8076 + ".set\tnoat\n\t" \
8077 + ".word\t"STR(0x40010000 | ((source)<<11) | (sel))"\n\t" \
8078 + "move\t%0,$1\n\t" \
8079 + ".set\tat\n\t" \
8080 + ".set\treorder" \
8081 + :"=r" (__res) \
8082 + : \
8083 + :"$1"); \
8084 + __res; \
8085 +})
8086 +
8087 +#define MTC0(source, sel, value) \
8088 +do { \
8089 + __asm__ __volatile__( \
8090 + ".set\tnoreorder\n\t" \
8091 + ".set\tnoat\n\t" \
8092 + "move\t$1,%z0\n\t" \
8093 + ".word\t"STR(0x40810000 | ((source)<<11) | (sel))"\n\t" \
8094 + ".set\tat\n\t" \
8095 + ".set\treorder" \
8096 + : \
8097 + :"jr" (value) \
8098 + :"$1"); \
8099 +} while (0)
8100 +
8101 +#define get_c0_count() \
8102 +({ \
8103 + int __res; \
8104 + __asm__ __volatile__( \
8105 + ".set\tnoreorder\n\t" \
8106 + ".set\tnoat\n\t" \
8107 + "mfc0\t%0,$9\n\t" \
8108 + ".set\tat\n\t" \
8109 + ".set\treorder" \
8110 + :"=r" (__res)); \
8111 + __res; \
8112 +})
8113 +
8114 +static INLINE void icache_probe(uint32 config1, uint *size, uint *lsize)
8115 +{
8116 + uint lsz, sets, ways;
8117 +
8118 + /* Instruction Cache Size = Associativity * Line Size * Sets Per Way */
8119 + if ((lsz = ((config1 & CONF1_IL_MASK) >> CONF1_IL_SHIFT)))
8120 + lsz = CONF1_IL_BASE << lsz;
8121 + sets = CONF1_IS_BASE << ((config1 & CONF1_IS_MASK) >> CONF1_IS_SHIFT);
8122 + ways = CONF1_IA_BASE + ((config1 & CONF1_IA_MASK) >> CONF1_IA_SHIFT);
8123 + *size = lsz * sets * ways;
8124 + *lsize = lsz;
8125 +}
8126 +
8127 +static INLINE void dcache_probe(uint32 config1, uint *size, uint *lsize)
8128 +{
8129 + uint lsz, sets, ways;
8130 +
8131 + /* Data Cache Size = Associativity * Line Size * Sets Per Way */
8132 + if ((lsz = ((config1 & CONF1_DL_MASK) >> CONF1_DL_SHIFT)))
8133 + lsz = CONF1_DL_BASE << lsz;
8134 + sets = CONF1_DS_BASE << ((config1 & CONF1_DS_MASK) >> CONF1_DS_SHIFT);
8135 + ways = CONF1_DA_BASE + ((config1 & CONF1_DA_MASK) >> CONF1_DA_SHIFT);
8136 + *size = lsz * sets * ways;
8137 + *lsize = lsz;
8138 +}
8139 +
8140 +#define cache_op(base, op) \
8141 + __asm__ __volatile__(" \
8142 + .set noreorder; \
8143 + .set mips3; \
8144 + cache %1, (%0); \
8145 + .set mips0; \
8146 + .set reorder" \
8147 + : \
8148 + : "r" (base), \
8149 + "i" (op));
8150 +
8151 +#define cache_unroll4(base, delta, op) \
8152 + __asm__ __volatile__(" \
8153 + .set noreorder; \
8154 + .set mips3; \
8155 + cache %1,0(%0); \
8156 + cache %1,delta(%0); \
8157 + cache %1,(2 * delta)(%0); \
8158 + cache %1,(3 * delta)(%0); \
8159 + .set mips0; \
8160 + .set reorder" \
8161 + : \
8162 + : "r" (base), \
8163 + "i" (op));
8164 +
8165 +#endif /* !_LANGUAGE_ASSEMBLY */
8166 +
8167 +#endif /* _MISPINC_H */
8168 diff -urN linux.old/arch/mips/bcm947xx/include/osl.h linux.dev/arch/mips/bcm947xx/include/osl.h
8169 --- linux.old/arch/mips/bcm947xx/include/osl.h 1970-01-01 01:00:00.000000000 +0100
8170 +++ linux.dev/arch/mips/bcm947xx/include/osl.h 2005-12-15 15:35:08.321801750 +0100
8171 @@ -0,0 +1,42 @@
8172 +/*
8173 + * OS Abstraction Layer
8174 + *
8175 + * Copyright 2005, Broadcom Corporation
8176 + * All Rights Reserved.
8177 + *
8178 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8179 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8180 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8181 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8182 + * $Id$
8183 + */
8184 +
8185 +#ifndef _osl_h_
8186 +#define _osl_h_
8187 +
8188 +/* osl handle type forward declaration */
8189 +typedef struct os_handle osl_t;
8190 +
8191 +#if defined(linux)
8192 +#include <linux_osl.h>
8193 +#elif defined(NDIS)
8194 +#include <ndis_osl.h>
8195 +#elif defined(_CFE_)
8196 +#include <cfe_osl.h>
8197 +#elif defined(_HNDRTE_)
8198 +#include <hndrte_osl.h>
8199 +#elif defined(_MINOSL_)
8200 +#include <min_osl.h>
8201 +#elif PMON
8202 +#include <pmon_osl.h>
8203 +#elif defined(MACOSX)
8204 +#include <macosx_osl.h>
8205 +#else
8206 +#error "Unsupported OSL requested"
8207 +#endif
8208 +
8209 +/* handy */
8210 +#define SET_REG(r, mask, val) W_REG((r), ((R_REG(r) & ~(mask)) | (val)))
8211 +#define MAXPRIO 7 /* 0-7 */
8212 +
8213 +#endif /* _osl_h_ */
8214 diff -urN linux.old/arch/mips/bcm947xx/include/pcicfg.h linux.dev/arch/mips/bcm947xx/include/pcicfg.h
8215 --- linux.old/arch/mips/bcm947xx/include/pcicfg.h 1970-01-01 01:00:00.000000000 +0100
8216 +++ linux.dev/arch/mips/bcm947xx/include/pcicfg.h 2005-12-15 15:36:31.719013750 +0100
8217 @@ -0,0 +1,398 @@
8218 +/*
8219 + * pcicfg.h: PCI configuration constants and structures.
8220 + *
8221 + * Copyright 2005, Broadcom Corporation
8222 + * All Rights Reserved.
8223 + *
8224 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8225 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8226 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8227 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8228 + *
8229 + * $Id$
8230 + */
8231 +
8232 +#ifndef _h_pci_
8233 +#define _h_pci_
8234 +
8235 +/* The following inside ifndef's so we don't collide with NTDDK.H */
8236 +#ifndef PCI_MAX_BUS
8237 +#define PCI_MAX_BUS 0x100
8238 +#endif
8239 +#ifndef PCI_MAX_DEVICES
8240 +#define PCI_MAX_DEVICES 0x20
8241 +#endif
8242 +#ifndef PCI_MAX_FUNCTION
8243 +#define PCI_MAX_FUNCTION 0x8
8244 +#endif
8245 +
8246 +#ifndef PCI_INVALID_VENDORID
8247 +#define PCI_INVALID_VENDORID 0xffff
8248 +#endif
8249 +#ifndef PCI_INVALID_DEVICEID
8250 +#define PCI_INVALID_DEVICEID 0xffff
8251 +#endif
8252 +
8253 +
8254 +/* Convert between bus-slot-function-register and config addresses */
8255 +
8256 +#define PCICFG_BUS_SHIFT 16 /* Bus shift */
8257 +#define PCICFG_SLOT_SHIFT 11 /* Slot shift */
8258 +#define PCICFG_FUN_SHIFT 8 /* Function shift */
8259 +#define PCICFG_OFF_SHIFT 0 /* Register shift */
8260 +
8261 +#define PCICFG_BUS_MASK 0xff /* Bus mask */
8262 +#define PCICFG_SLOT_MASK 0x1f /* Slot mask */
8263 +#define PCICFG_FUN_MASK 7 /* Function mask */
8264 +#define PCICFG_OFF_MASK 0xff /* Bus mask */
8265 +
8266 +#define PCI_CONFIG_ADDR(b, s, f, o) \
8267 + ((((b) & PCICFG_BUS_MASK) << PCICFG_BUS_SHIFT) \
8268 + | (((s) & PCICFG_SLOT_MASK) << PCICFG_SLOT_SHIFT) \
8269 + | (((f) & PCICFG_FUN_MASK) << PCICFG_FUN_SHIFT) \
8270 + | (((o) & PCICFG_OFF_MASK) << PCICFG_OFF_SHIFT))
8271 +
8272 +#define PCI_CONFIG_BUS(a) (((a) >> PCICFG_BUS_SHIFT) & PCICFG_BUS_MASK)
8273 +#define PCI_CONFIG_SLOT(a) (((a) >> PCICFG_SLOT_SHIFT) & PCICFG_SLOT_MASK)
8274 +#define PCI_CONFIG_FUN(a) (((a) >> PCICFG_FUN_SHIFT) & PCICFG_FUN_MASK)
8275 +#define PCI_CONFIG_OFF(a) (((a) >> PCICFG_OFF_SHIFT) & PCICFG_OFF_MASK)
8276 +
8277 +/* The actual config space */
8278 +
8279 +#define PCI_BAR_MAX 6
8280 +
8281 +#define PCI_ROM_BAR 8
8282 +
8283 +#define PCR_RSVDA_MAX 2
8284 +
8285 +/* pci config status reg has a bit to indicate that capability ptr is present*/
8286 +
8287 +#define PCI_CAPPTR_PRESENT 0x0010
8288 +
8289 +typedef struct _pci_config_regs {
8290 + unsigned short vendor;
8291 + unsigned short device;
8292 + unsigned short command;
8293 + unsigned short status;
8294 + unsigned char rev_id;
8295 + unsigned char prog_if;
8296 + unsigned char sub_class;
8297 + unsigned char base_class;
8298 + unsigned char cache_line_size;
8299 + unsigned char latency_timer;
8300 + unsigned char header_type;
8301 + unsigned char bist;
8302 + unsigned long base[PCI_BAR_MAX];
8303 + unsigned long cardbus_cis;
8304 + unsigned short subsys_vendor;
8305 + unsigned short subsys_id;
8306 + unsigned long baserom;
8307 + unsigned long rsvd_a[PCR_RSVDA_MAX];
8308 + unsigned char int_line;
8309 + unsigned char int_pin;
8310 + unsigned char min_gnt;
8311 + unsigned char max_lat;
8312 + unsigned char dev_dep[192];
8313 +} pci_config_regs;
8314 +
8315 +#define SZPCR (sizeof (pci_config_regs))
8316 +#define MINSZPCR 64 /* offsetof (dev_dep[0] */
8317 +
8318 +/* A structure for the config registers is nice, but in most
8319 + * systems the config space is not memory mapped, so we need
8320 + * filed offsetts. :-(
8321 + */
8322 +#define PCI_CFG_VID 0
8323 +#define PCI_CFG_DID 2
8324 +#define PCI_CFG_CMD 4
8325 +#define PCI_CFG_STAT 6
8326 +#define PCI_CFG_REV 8
8327 +#define PCI_CFG_PROGIF 9
8328 +#define PCI_CFG_SUBCL 0xa
8329 +#define PCI_CFG_BASECL 0xb
8330 +#define PCI_CFG_CLSZ 0xc
8331 +#define PCI_CFG_LATTIM 0xd
8332 +#define PCI_CFG_HDR 0xe
8333 +#define PCI_CFG_BIST 0xf
8334 +#define PCI_CFG_BAR0 0x10
8335 +#define PCI_CFG_BAR1 0x14
8336 +#define PCI_CFG_BAR2 0x18
8337 +#define PCI_CFG_BAR3 0x1c
8338 +#define PCI_CFG_BAR4 0x20
8339 +#define PCI_CFG_BAR5 0x24
8340 +#define PCI_CFG_CIS 0x28
8341 +#define PCI_CFG_SVID 0x2c
8342 +#define PCI_CFG_SSID 0x2e
8343 +#define PCI_CFG_ROMBAR 0x30
8344 +#define PCI_CFG_CAPPTR 0x34
8345 +#define PCI_CFG_INT 0x3c
8346 +#define PCI_CFG_PIN 0x3d
8347 +#define PCI_CFG_MINGNT 0x3e
8348 +#define PCI_CFG_MAXLAT 0x3f
8349 +
8350 +/* Classes and subclasses */
8351 +
8352 +typedef enum {
8353 + PCI_CLASS_OLD = 0,
8354 + PCI_CLASS_DASDI,
8355 + PCI_CLASS_NET,
8356 + PCI_CLASS_DISPLAY,
8357 + PCI_CLASS_MMEDIA,
8358 + PCI_CLASS_MEMORY,
8359 + PCI_CLASS_BRIDGE,
8360 + PCI_CLASS_COMM,
8361 + PCI_CLASS_BASE,
8362 + PCI_CLASS_INPUT,
8363 + PCI_CLASS_DOCK,
8364 + PCI_CLASS_CPU,
8365 + PCI_CLASS_SERIAL,
8366 + PCI_CLASS_INTELLIGENT = 0xe,
8367 + PCI_CLASS_SATELLITE,
8368 + PCI_CLASS_CRYPT,
8369 + PCI_CLASS_DSP,
8370 + PCI_CLASS_MAX
8371 +} pci_classes;
8372 +
8373 +typedef enum {
8374 + PCI_DASDI_SCSI,
8375 + PCI_DASDI_IDE,
8376 + PCI_DASDI_FLOPPY,
8377 + PCI_DASDI_IPI,
8378 + PCI_DASDI_RAID,
8379 + PCI_DASDI_OTHER = 0x80
8380 +} pci_dasdi_subclasses;
8381 +
8382 +typedef enum {
8383 + PCI_NET_ETHER,
8384 + PCI_NET_TOKEN,
8385 + PCI_NET_FDDI,
8386 + PCI_NET_ATM,
8387 + PCI_NET_OTHER = 0x80
8388 +} pci_net_subclasses;
8389 +
8390 +typedef enum {
8391 + PCI_DISPLAY_VGA,
8392 + PCI_DISPLAY_XGA,
8393 + PCI_DISPLAY_3D,
8394 + PCI_DISPLAY_OTHER = 0x80
8395 +} pci_display_subclasses;
8396 +
8397 +typedef enum {
8398 + PCI_MMEDIA_VIDEO,
8399 + PCI_MMEDIA_AUDIO,
8400 + PCI_MMEDIA_PHONE,
8401 + PCI_MEDIA_OTHER = 0x80
8402 +} pci_mmedia_subclasses;
8403 +
8404 +typedef enum {
8405 + PCI_MEMORY_RAM,
8406 + PCI_MEMORY_FLASH,
8407 + PCI_MEMORY_OTHER = 0x80
8408 +} pci_memory_subclasses;
8409 +
8410 +typedef enum {
8411 + PCI_BRIDGE_HOST,
8412 + PCI_BRIDGE_ISA,
8413 + PCI_BRIDGE_EISA,
8414 + PCI_BRIDGE_MC,
8415 + PCI_BRIDGE_PCI,
8416 + PCI_BRIDGE_PCMCIA,
8417 + PCI_BRIDGE_NUBUS,
8418 + PCI_BRIDGE_CARDBUS,
8419 + PCI_BRIDGE_RACEWAY,
8420 + PCI_BRIDGE_OTHER = 0x80
8421 +} pci_bridge_subclasses;
8422 +
8423 +typedef enum {
8424 + PCI_COMM_UART,
8425 + PCI_COMM_PARALLEL,
8426 + PCI_COMM_MULTIUART,
8427 + PCI_COMM_MODEM,
8428 + PCI_COMM_OTHER = 0x80
8429 +} pci_comm_subclasses;
8430 +
8431 +typedef enum {
8432 + PCI_BASE_PIC,
8433 + PCI_BASE_DMA,
8434 + PCI_BASE_TIMER,
8435 + PCI_BASE_RTC,
8436 + PCI_BASE_PCI_HOTPLUG,
8437 + PCI_BASE_OTHER = 0x80
8438 +} pci_base_subclasses;
8439 +
8440 +typedef enum {
8441 + PCI_INPUT_KBD,
8442 + PCI_INPUT_PEN,
8443 + PCI_INPUT_MOUSE,
8444 + PCI_INPUT_SCANNER,
8445 + PCI_INPUT_GAMEPORT,
8446 + PCI_INPUT_OTHER = 0x80
8447 +} pci_input_subclasses;
8448 +
8449 +typedef enum {
8450 + PCI_DOCK_GENERIC,
8451 + PCI_DOCK_OTHER = 0x80
8452 +} pci_dock_subclasses;
8453 +
8454 +typedef enum {
8455 + PCI_CPU_386,
8456 + PCI_CPU_486,
8457 + PCI_CPU_PENTIUM,
8458 + PCI_CPU_ALPHA = 0x10,
8459 + PCI_CPU_POWERPC = 0x20,
8460 + PCI_CPU_MIPS = 0x30,
8461 + PCI_CPU_COPROC = 0x40,
8462 + PCI_CPU_OTHER = 0x80
8463 +} pci_cpu_subclasses;
8464 +
8465 +typedef enum {
8466 + PCI_SERIAL_IEEE1394,
8467 + PCI_SERIAL_ACCESS,
8468 + PCI_SERIAL_SSA,
8469 + PCI_SERIAL_USB,
8470 + PCI_SERIAL_FIBER,
8471 + PCI_SERIAL_SMBUS,
8472 + PCI_SERIAL_OTHER = 0x80
8473 +} pci_serial_subclasses;
8474 +
8475 +typedef enum {
8476 + PCI_INTELLIGENT_I2O,
8477 +} pci_intelligent_subclasses;
8478 +
8479 +typedef enum {
8480 + PCI_SATELLITE_TV,
8481 + PCI_SATELLITE_AUDIO,
8482 + PCI_SATELLITE_VOICE,
8483 + PCI_SATELLITE_DATA,
8484 + PCI_SATELLITE_OTHER = 0x80
8485 +} pci_satellite_subclasses;
8486 +
8487 +typedef enum {
8488 + PCI_CRYPT_NETWORK,
8489 + PCI_CRYPT_ENTERTAINMENT,
8490 + PCI_CRYPT_OTHER = 0x80
8491 +} pci_crypt_subclasses;
8492 +
8493 +typedef enum {
8494 + PCI_DSP_DPIO,
8495 + PCI_DSP_OTHER = 0x80
8496 +} pci_dsp_subclasses;
8497 +
8498 +/* Header types */
8499 +typedef enum {
8500 + PCI_HEADER_NORMAL,
8501 + PCI_HEADER_BRIDGE,
8502 + PCI_HEADER_CARDBUS
8503 +} pci_header_types;
8504 +
8505 +
8506 +/* Overlay for a PCI-to-PCI bridge */
8507 +
8508 +#define PPB_RSVDA_MAX 2
8509 +#define PPB_RSVDD_MAX 8
8510 +
8511 +typedef struct _ppb_config_regs {
8512 + unsigned short vendor;
8513 + unsigned short device;
8514 + unsigned short command;
8515 + unsigned short status;
8516 + unsigned char rev_id;
8517 + unsigned char prog_if;
8518 + unsigned char sub_class;
8519 + unsigned char base_class;
8520 + unsigned char cache_line_size;
8521 + unsigned char latency_timer;
8522 + unsigned char header_type;
8523 + unsigned char bist;
8524 + unsigned long rsvd_a[PPB_RSVDA_MAX];
8525 + unsigned char prim_bus;
8526 + unsigned char sec_bus;
8527 + unsigned char sub_bus;
8528 + unsigned char sec_lat;
8529 + unsigned char io_base;
8530 + unsigned char io_lim;
8531 + unsigned short sec_status;
8532 + unsigned short mem_base;
8533 + unsigned short mem_lim;
8534 + unsigned short pf_mem_base;
8535 + unsigned short pf_mem_lim;
8536 + unsigned long pf_mem_base_hi;
8537 + unsigned long pf_mem_lim_hi;
8538 + unsigned short io_base_hi;
8539 + unsigned short io_lim_hi;
8540 + unsigned short subsys_vendor;
8541 + unsigned short subsys_id;
8542 + unsigned long rsvd_b;
8543 + unsigned char rsvd_c;
8544 + unsigned char int_pin;
8545 + unsigned short bridge_ctrl;
8546 + unsigned char chip_ctrl;
8547 + unsigned char diag_ctrl;
8548 + unsigned short arb_ctrl;
8549 + unsigned long rsvd_d[PPB_RSVDD_MAX];
8550 + unsigned char dev_dep[192];
8551 +} ppb_config_regs;
8552 +
8553 +
8554 +/* PCI CAPABILITY DEFINES */
8555 +#define PCI_CAP_POWERMGMTCAP_ID 0x01
8556 +#define PCI_CAP_MSICAP_ID 0x05
8557 +
8558 +/* Data structure to define the Message Signalled Interrupt facility
8559 + * Valid for PCI and PCIE configurations */
8560 +typedef struct _pciconfig_cap_msi {
8561 + unsigned char capID;
8562 + unsigned char nextptr;
8563 + unsigned short msgctrl;
8564 + unsigned int msgaddr;
8565 +} pciconfig_cap_msi;
8566 +
8567 +/* Data structure to define the Power managment facility
8568 + * Valid for PCI and PCIE configurations */
8569 +typedef struct _pciconfig_cap_pwrmgmt {
8570 + unsigned char capID;
8571 + unsigned char nextptr;
8572 + unsigned short pme_cap;
8573 + unsigned short pme_sts_ctrl;
8574 + unsigned char pme_bridge_ext;
8575 + unsigned char data;
8576 +} pciconfig_cap_pwrmgmt;
8577 +
8578 +/* Everything below is BRCM HND proprietary */
8579 +
8580 +#define PCI_BAR0_WIN 0x80 /* backplane addres space accessed by BAR0 */
8581 +#define PCI_BAR1_WIN 0x84 /* backplane addres space accessed by BAR1 */
8582 +#define PCI_SPROM_CONTROL 0x88 /* sprom property control */
8583 +#define PCI_BAR1_CONTROL 0x8c /* BAR1 region burst control */
8584 +#define PCI_INT_STATUS 0x90 /* PCI and other cores interrupts */
8585 +#define PCI_INT_MASK 0x94 /* mask of PCI and other cores interrupts */
8586 +#define PCI_TO_SB_MB 0x98 /* signal backplane interrupts */
8587 +#define PCI_BACKPLANE_ADDR 0xA0 /* address an arbitrary location on the system backplane */
8588 +#define PCI_BACKPLANE_DATA 0xA4 /* data at the location specified by above address register */
8589 +#define PCI_GPIO_IN 0xb0 /* pci config space gpio input (>=rev3) */
8590 +#define PCI_GPIO_OUT 0xb4 /* pci config space gpio output (>=rev3) */
8591 +#define PCI_GPIO_OUTEN 0xb8 /* pci config space gpio output enable (>=rev3) */
8592 +
8593 +#define PCI_BAR0_SPROM_OFFSET (4 * 1024) /* bar0 + 4K accesses external sprom */
8594 +#define PCI_BAR0_PCIREGS_OFFSET (6 * 1024) /* bar0 + 6K accesses pci core registers */
8595 +
8596 +/* PCI_INT_STATUS */
8597 +#define PCI_SBIM_STATUS_SERR 0x4 /* backplane SBErr interrupt status */
8598 +
8599 +/* PCI_INT_MASK */
8600 +#define PCI_SBIM_SHIFT 8 /* backplane core interrupt mask bits offset */
8601 +#define PCI_SBIM_MASK 0xff00 /* backplane core interrupt mask */
8602 +#define PCI_SBIM_MASK_SERR 0x4 /* backplane SBErr interrupt mask */
8603 +
8604 +/* PCI_SPROM_CONTROL */
8605 +#define SPROM_BLANK 0x04 /* indicating a blank sprom */
8606 +#define SPROM_WRITEEN 0x10 /* sprom write enable */
8607 +#define SPROM_BOOTROM_WE 0x20 /* external bootrom write enable */
8608 +
8609 +#define SPROM_SIZE 256 /* sprom size in 16-bit */
8610 +#define SPROM_CRC_RANGE 64 /* crc cover range in 16-bit */
8611 +
8612 +/* PCI_CFG_CMD_STAT */
8613 +#define PCI_CFG_CMD_STAT_TA 0x08000000 /* target abort status */
8614 +
8615 +#endif
8616 diff -urN linux.old/arch/mips/bcm947xx/include/proto/ethernet.h linux.dev/arch/mips/bcm947xx/include/proto/ethernet.h
8617 --- linux.old/arch/mips/bcm947xx/include/proto/ethernet.h 1970-01-01 01:00:00.000000000 +0100
8618 +++ linux.dev/arch/mips/bcm947xx/include/proto/ethernet.h 2005-12-15 12:57:27.869191250 +0100
8619 @@ -0,0 +1,145 @@
8620 +/*******************************************************************************
8621 + * $Id$
8622 + * Copyright 2001-2003, Broadcom Corporation
8623 + * All Rights Reserved.
8624 + *
8625 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8626 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8627 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8628 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8629 + * From FreeBSD 2.2.7: Fundamental constants relating to ethernet.
8630 + ******************************************************************************/
8631 +
8632 +#ifndef _NET_ETHERNET_H_ /* use native BSD ethernet.h when available */
8633 +#define _NET_ETHERNET_H_
8634 +
8635 +#ifndef _TYPEDEFS_H_
8636 +#include "typedefs.h"
8637 +#endif
8638 +
8639 +#if defined(__GNUC__)
8640 +#define PACKED __attribute__((packed))
8641 +#else
8642 +#define PACKED
8643 +#endif
8644 +
8645 +/*
8646 + * The number of bytes in an ethernet (MAC) address.
8647 + */
8648 +#define ETHER_ADDR_LEN 6
8649 +
8650 +/*
8651 + * The number of bytes in the type field.
8652 + */
8653 +#define ETHER_TYPE_LEN 2
8654 +
8655 +/*
8656 + * The number of bytes in the trailing CRC field.
8657 + */
8658 +#define ETHER_CRC_LEN 4
8659 +
8660 +/*
8661 + * The length of the combined header.
8662 + */
8663 +#define ETHER_HDR_LEN (ETHER_ADDR_LEN*2+ETHER_TYPE_LEN)
8664 +
8665 +/*
8666 + * The minimum packet length.
8667 + */
8668 +#define ETHER_MIN_LEN 64
8669 +
8670 +/*
8671 + * The minimum packet user data length.
8672 + */
8673 +#define ETHER_MIN_DATA 46
8674 +
8675 +/*
8676 + * The maximum packet length.
8677 + */
8678 +#define ETHER_MAX_LEN 1518
8679 +
8680 +/*
8681 + * The maximum packet user data length.
8682 + */
8683 +#define ETHER_MAX_DATA 1500
8684 +
8685 +/*
8686 + * Used to uniquely identify a 802.1q VLAN-tagged header.
8687 + */
8688 +#define VLAN_TAG 0x8100
8689 +
8690 +/*
8691 + * Located after dest & src address in ether header.
8692 + */
8693 +#define VLAN_FIELDS_OFFSET (ETHER_ADDR_LEN * 2)
8694 +
8695 +/*
8696 + * 4 bytes of vlan field info.
8697 + */
8698 +#define VLAN_FIELDS_SIZE 4
8699 +
8700 +/* location of pri bits in 16-bit vlan fields */
8701 +#define VLAN_PRI_SHIFT 13
8702 +
8703 +/* 3 bits of priority */
8704 +#define VLAN_PRI_MASK 7
8705 +
8706 +/* 802.1X ethertype */
8707 +#define ETHER_TYPE_802_1X 0x888e
8708 +
8709 +/*
8710 + * A macro to validate a length with
8711 + */
8712 +#define ETHER_IS_VALID_LEN(foo) \
8713 + ((foo) >= ETHER_MIN_LEN && (foo) <= ETHER_MAX_LEN)
8714 +
8715 +
8716 +#ifndef __INCif_etherh /* Quick and ugly hack for VxWorks */
8717 +/*
8718 + * Structure of a 10Mb/s Ethernet header.
8719 + */
8720 +struct ether_header {
8721 + uint8 ether_dhost[ETHER_ADDR_LEN];
8722 + uint8 ether_shost[ETHER_ADDR_LEN];
8723 + uint16 ether_type;
8724 +} PACKED ;
8725 +
8726 +/*
8727 + * Structure of a 48-bit Ethernet address.
8728 + */
8729 +struct ether_addr {
8730 + uint8 octet[ETHER_ADDR_LEN];
8731 +} PACKED ;
8732 +#endif
8733 +
8734 +/*
8735 + * Takes a pointer, returns true if a 48-bit multicast address
8736 + * (including broadcast, since it is all ones)
8737 + */
8738 +#define ETHER_ISMULTI(ea) (((uint8 *)(ea))[0] & 1)
8739 +
8740 +/*
8741 + * Takes a pointer, returns true if a 48-bit broadcast (all ones)
8742 + */
8743 +#define ETHER_ISBCAST(ea) ((((uint8 *)(ea))[0] & \
8744 + ((uint8 *)(ea))[1] & \
8745 + ((uint8 *)(ea))[2] & \
8746 + ((uint8 *)(ea))[3] & \
8747 + ((uint8 *)(ea))[4] & \
8748 + ((uint8 *)(ea))[5]) == 0xff)
8749 +
8750 +static const struct ether_addr ether_bcast = {{255, 255, 255, 255, 255, 255}};
8751 +
8752 +/*
8753 + * Takes a pointer, returns true if a 48-bit null address (all zeros)
8754 + */
8755 +#define ETHER_ISNULLADDR(ea) ((((uint8 *)(ea))[0] | \
8756 + ((uint8 *)(ea))[1] | \
8757 + ((uint8 *)(ea))[2] | \
8758 + ((uint8 *)(ea))[3] | \
8759 + ((uint8 *)(ea))[4] | \
8760 + ((uint8 *)(ea))[5]) == 0)
8761 +
8762 +#undef PACKED
8763 +
8764 +#endif /* _NET_ETHERNET_H_ */
8765 diff -urN linux.old/arch/mips/bcm947xx/include/s5.h linux.dev/arch/mips/bcm947xx/include/s5.h
8766 --- linux.old/arch/mips/bcm947xx/include/s5.h 1970-01-01 01:00:00.000000000 +0100
8767 +++ linux.dev/arch/mips/bcm947xx/include/s5.h 2005-12-15 12:57:27.869191250 +0100
8768 @@ -0,0 +1,103 @@
8769 +#ifndef _S5_H_
8770 +#define _S5_H_
8771 +/*
8772 + * Copyright 2003, Broadcom Corporation
8773 + * All Rights Reserved.
8774 + *
8775 + * Broadcom Sentry5 (S5) BCM5365, 53xx, BCM58xx SOC Internal Core
8776 + * and MIPS3301 (R4K) System Address Space
8777 + *
8778 + * This program is free software; you can redistribute it and/or
8779 + * modify it under the terms of the GNU General Public License as
8780 + * published by the Free Software Foundation, located in the file
8781 + * LICENSE.
8782 + *
8783 + * $Id: s5.h,v 1.3 2003/06/10 18:54:51 jfd Exp $
8784 + *
8785 + */
8786 +
8787 +/* BCM5365 Address map */
8788 +#define KSEG1ADDR(x) ( (x) | 0xa0000000)
8789 +#define BCM5365_SDRAM 0x00000000 /* 0-128MB Physical SDRAM */
8790 +#define BCM5365_PCI_MEM 0x08000000 /* Host Mode PCI mem space (64MB) */
8791 +#define BCM5365_PCI_CFG 0x0c000000 /* Host Mode PCI cfg space (64MB) */
8792 +#define BCM5365_PCI_DMA 0x40000000 /* Client Mode PCI mem space (1GB)*/
8793 +#define BCM5365_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
8794 +#define BCM5365_ENUM 0x18000000 /* Beginning of core enum space */
8795 +
8796 +/* BCM5365 Core register space */
8797 +#define BCM5365_REG_CHIPC 0x18000000 /* Chipcommon registers */
8798 +#define BCM5365_REG_EMAC0 0x18001000 /* Ethernet MAC0 core registers */
8799 +#define BCM5365_REG_IPSEC 0x18002000 /* BCM582x CryptoCore registers */
8800 +#define BCM5365_REG_USB 0x18003000 /* USB core registers */
8801 +#define BCM5365_REG_PCI 0x18004000 /* PCI core registers */
8802 +#define BCM5365_REG_MIPS33 0x18005000 /* MIPS core registers */
8803 +#define BCM5365_REG_MEMC 0x18006000 /* MEMC core registers */
8804 +#define BCM5365_REG_UARTS (BCM5365_REG_CHIPC + 0x300) /* UART regs */
8805 +#define BCM5365_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
8806 +
8807 +/* COM Ports 1/2 */
8808 +#define BCM5365_UART (BCM5365_REG_UARTS)
8809 +#define BCM5365_UART_COM2 (BCM5365_REG_UARTS + 0x00000100)
8810 +
8811 +/* Registers common to MIPS33 Core used in 5365 */
8812 +#define MIPS33_FLASH_REGION 0x1fc00000 /* Boot FLASH Region */
8813 +#define MIPS33_EXTIF_REGION 0x1a000000 /* Chipcommon EXTIF region*/
8814 +#define BCM5365_EXTIF 0x1b000000 /* MISC_CS */
8815 +#define MIPS33_FLASH_REGION_AUX 0x1c000000 /* FLASH Region 2*/
8816 +
8817 +/* Internal Core Sonics Backplane Devices */
8818 +#define INTERNAL_UART_COM1 BCM5365_UART
8819 +#define INTERNAL_UART_COM2 BCM5365_UART_COM2
8820 +#define SB_REG_CHIPC BCM5365_REG_CHIPC
8821 +#define SB_REG_ENET0 BCM5365_REG_EMAC0
8822 +#define SB_REG_IPSEC BCM5365_REG_IPSEC
8823 +#define SB_REG_USB BCM5365_REG_USB
8824 +#define SB_REG_PCI BCM5365_REG_PCI
8825 +#define SB_REG_MIPS BCM5365_REG_MIPS33
8826 +#define SB_REG_MEMC BCM5365_REG_MEMC
8827 +#define SB_REG_MEMC_OFF 0x6000
8828 +#define SB_EXTIF_SPACE MIPS33_EXTIF_REGION
8829 +#define SB_FLASH_SPACE MIPS33_FLASH_REGION
8830 +
8831 +/*
8832 + * XXX
8833 + * 5365-specific backplane interrupt flag numbers. This should be done
8834 + * dynamically instead.
8835 + */
8836 +#define SBFLAG_PCI 0
8837 +#define SBFLAG_ENET0 1
8838 +#define SBFLAG_ILINE20 2
8839 +#define SBFLAG_CODEC 3
8840 +#define SBFLAG_USB 4
8841 +#define SBFLAG_EXTIF 5
8842 +#define SBFLAG_ENET1 6
8843 +
8844 +/* BCM95365 Local Bus devices */
8845 +#define BCM95365K_RESET_ADDR BCM5365_EXTIF
8846 +#define BCM95365K_BOARDID_ADDR (BCM5365_EXTIF | 0x4000)
8847 +#define BCM95365K_DOC_ADDR (BCM5365_EXTIF | 0x6000)
8848 +#define BCM95365K_LED_ADDR (BCM5365_EXTIF | 0xc000)
8849 +#define BCM95365K_TOD_REG_BASE (BCM95365K_NVRAM_ADDR | 0x1ff0)
8850 +#define BCM95365K_NVRAM_ADDR (BCM5365_EXTIF | 0xe000)
8851 +#define BCM95365K_NVRAM_SIZE 0x1ff0 /* 8K NVRAM : DS1743/STM48txx*/
8852 +
8853 +/* Write to DLR2416 VFD Display character RAM */
8854 +#define LED_REG(x) \
8855 + (*(volatile unsigned char *) (KSEG1ADDR(BCM95365K_LED_ADDR) + (x)))
8856 +
8857 +#ifdef CONFIG_VSIM
8858 +#define BCM5365_TRACE(trval) do { *((int *)0xa0002ff8) = (trval); \
8859 + } while (0)
8860 +#else
8861 +#define BCM5365_TRACE(trval) do { *((unsigned char *)\
8862 + KSEG1ADDR(BCM5365K_LED_ADDR)) = (trval); \
8863 + *((int *)0xa0002ff8) = (trval); } while (0)
8864 +#endif
8865 +
8866 +/* BCM9536R Local Bus devices */
8867 +#define BCM95365R_DOC_ADDR BCM5365_EXTIF
8868 +
8869 +
8870 +
8871 +#endif /*!_S5_H_ */
8872 diff -urN linux.old/arch/mips/bcm947xx/include/sbchipc.h linux.dev/arch/mips/bcm947xx/include/sbchipc.h
8873 --- linux.old/arch/mips/bcm947xx/include/sbchipc.h 1970-01-01 01:00:00.000000000 +0100
8874 +++ linux.dev/arch/mips/bcm947xx/include/sbchipc.h 2005-12-15 15:35:20.458560250 +0100
8875 @@ -0,0 +1,440 @@
8876 +/*
8877 + * SiliconBackplane Chipcommon core hardware definitions.
8878 + *
8879 + * The chipcommon core provides chip identification, SB control,
8880 + * jtag, 0/1/2 uarts, clock frequency control, a watchdog interrupt timer,
8881 + * gpio interface, extbus, and support for serial and parallel flashes.
8882 + *
8883 + * $Id$
8884 + * Copyright 2005, Broadcom Corporation
8885 + * All Rights Reserved.
8886 + *
8887 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
8888 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
8889 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
8890 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
8891 + *
8892 + */
8893 +
8894 +#ifndef _SBCHIPC_H
8895 +#define _SBCHIPC_H
8896 +
8897 +
8898 +#ifndef _LANGUAGE_ASSEMBLY
8899 +
8900 +/* cpp contortions to concatenate w/arg prescan */
8901 +#ifndef PAD
8902 +#define _PADLINE(line) pad ## line
8903 +#define _XSTR(line) _PADLINE(line)
8904 +#define PAD _XSTR(__LINE__)
8905 +#endif /* PAD */
8906 +
8907 +typedef volatile struct {
8908 + uint32 chipid; /* 0x0 */
8909 + uint32 capabilities;
8910 + uint32 corecontrol; /* corerev >= 1 */
8911 + uint32 bist;
8912 +
8913 + /* OTP */
8914 + uint32 otpstatus; /* 0x10, corerev >= 10 */
8915 + uint32 otpcontrol;
8916 + uint32 otpprog;
8917 + uint32 PAD;
8918 +
8919 + /* Interrupt control */
8920 + uint32 intstatus; /* 0x20 */
8921 + uint32 intmask;
8922 + uint32 chipcontrol; /* 0x28, rev >= 11 */
8923 + uint32 chipstatus; /* 0x2c, rev >= 11 */
8924 +
8925 + /* Jtag Master */
8926 + uint32 jtagcmd; /* 0x30, rev >= 10 */
8927 + uint32 jtagir;
8928 + uint32 jtagdr;
8929 + uint32 jtagctrl;
8930 +
8931 + /* serial flash interface registers */
8932 + uint32 flashcontrol; /* 0x40 */
8933 + uint32 flashaddress;
8934 + uint32 flashdata;
8935 + uint32 PAD[1];
8936 +
8937 + /* Silicon backplane configuration broadcast control */
8938 + uint32 broadcastaddress; /* 0x50 */
8939 + uint32 broadcastdata;
8940 + uint32 PAD[2];
8941 +
8942 + /* gpio - cleared only by power-on-reset */
8943 + uint32 gpioin; /* 0x60 */
8944 + uint32 gpioout;
8945 + uint32 gpioouten;
8946 + uint32 gpiocontrol;
8947 + uint32 gpiointpolarity;
8948 + uint32 gpiointmask;
8949 + uint32 PAD[2];
8950 +
8951 + /* Watchdog timer */
8952 + uint32 watchdog; /* 0x80 */
8953 + uint32 PAD[1];
8954 +
8955 + /*GPIO based LED powersave registers corerev >= 16*/
8956 + uint32 gpiotimerval; /*0x88 */
8957 + uint32 gpiotimeroutmask;
8958 +
8959 + /* clock control */
8960 + uint32 clockcontrol_n; /* 0x90 */
8961 + uint32 clockcontrol_sb; /* aka m0 */
8962 + uint32 clockcontrol_pci; /* aka m1 */
8963 + uint32 clockcontrol_m2; /* mii/uart/mipsref */
8964 + uint32 clockcontrol_mips; /* aka m3 */
8965 + uint32 clkdiv; /* corerev >= 3 */
8966 + uint32 PAD[2];
8967 +
8968 + /* pll delay registers (corerev >= 4) */
8969 + uint32 pll_on_delay; /* 0xb0 */
8970 + uint32 fref_sel_delay;
8971 + uint32 slow_clk_ctl; /* 5 < corerev < 10 */
8972 + uint32 PAD[1];
8973 +
8974 + /* Instaclock registers (corerev >= 10) */
8975 + uint32 system_clk_ctl; /* 0xc0 */
8976 + uint32 clkstatestretch;
8977 + uint32 PAD[14];
8978 +
8979 + /* ExtBus control registers (corerev >= 3) */
8980 + uint32 pcmcia_config; /* 0x100 */
8981 + uint32 pcmcia_memwait;
8982 + uint32 pcmcia_attrwait;
8983 + uint32 pcmcia_iowait;
8984 + uint32 ide_config;
8985 + uint32 ide_memwait;
8986 + uint32 ide_attrwait;
8987 + uint32 ide_iowait;
8988 + uint32 prog_config;
8989 + uint32 prog_waitcount;
8990 + uint32 flash_config;
8991 + uint32 flash_waitcount;
8992 + uint32 PAD[116];
8993 +
8994 + /* uarts */
8995 + uint8 uart0data; /* 0x300 */
8996 + uint8 uart0imr;
8997 + uint8 uart0fcr;
8998 + uint8 uart0lcr;
8999 + uint8 uart0mcr;
9000 + uint8 uart0lsr;
9001 + uint8 uart0msr;
9002 + uint8 uart0scratch;
9003 + uint8 PAD[248]; /* corerev >= 1 */
9004 +
9005 + uint8 uart1data; /* 0x400 */
9006 + uint8 uart1imr;
9007 + uint8 uart1fcr;
9008 + uint8 uart1lcr;
9009 + uint8 uart1mcr;
9010 + uint8 uart1lsr;
9011 + uint8 uart1msr;
9012 + uint8 uart1scratch;
9013 +} chipcregs_t;
9014 +
9015 +#endif /* _LANGUAGE_ASSEMBLY */
9016 +
9017 +#define CC_CHIPID 0
9018 +#define CC_CAPABILITIES 4
9019 +#define CC_JTAGCMD 0x30
9020 +#define CC_JTAGIR 0x34
9021 +#define CC_JTAGDR 0x38
9022 +#define CC_JTAGCTRL 0x3c
9023 +#define CC_WATCHDOG 0x80
9024 +#define CC_CLKC_N 0x90
9025 +#define CC_CLKC_M0 0x94
9026 +#define CC_CLKC_M1 0x98
9027 +#define CC_CLKC_M2 0x9c
9028 +#define CC_CLKC_M3 0xa0
9029 +#define CC_CLKDIV 0xa4
9030 +#define CC_SYS_CLK_CTL 0xc0
9031 +#define CC_OTP 0x800
9032 +
9033 +/* chipid */
9034 +#define CID_ID_MASK 0x0000ffff /* Chip Id mask */
9035 +#define CID_REV_MASK 0x000f0000 /* Chip Revision mask */
9036 +#define CID_REV_SHIFT 16 /* Chip Revision shift */
9037 +#define CID_PKG_MASK 0x00f00000 /* Package Option mask */
9038 +#define CID_PKG_SHIFT 20 /* Package Option shift */
9039 +#define CID_CC_MASK 0x0f000000 /* CoreCount (corerev >= 4) */
9040 +#define CID_CC_SHIFT 24
9041 +
9042 +/* capabilities */
9043 +#define CAP_UARTS_MASK 0x00000003 /* Number of uarts */
9044 +#define CAP_MIPSEB 0x00000004 /* MIPS is in big-endian mode */
9045 +#define CAP_UCLKSEL 0x00000018 /* UARTs clock select */
9046 +#define CAP_UINTCLK 0x00000008 /* UARTs are driven by internal divided clock */
9047 +#define CAP_UARTGPIO 0x00000020 /* UARTs own Gpio's 15:12 */
9048 +#define CAP_EXTBUS 0x00000040 /* External bus present */
9049 +#define CAP_FLASH_MASK 0x00000700 /* Type of flash */
9050 +#define CAP_PLL_MASK 0x00038000 /* Type of PLL */
9051 +#define CAP_PWR_CTL 0x00040000 /* Power control */
9052 +#define CAP_OTPSIZE 0x00380000 /* OTP Size (0 = none) */
9053 +#define CAP_OTPSIZE_SHIFT 19 /* OTP Size shift */
9054 +#define CAP_OTPSIZE_BASE 5 /* OTP Size base */
9055 +#define CAP_JTAGP 0x00400000 /* JTAG Master Present */
9056 +#define CAP_ROM 0x00800000 /* Internal boot rom active */
9057 +
9058 +/* PLL type */
9059 +#define PLL_NONE 0x00000000
9060 +#define PLL_TYPE1 0x00010000 /* 48Mhz base, 3 dividers */
9061 +#define PLL_TYPE2 0x00020000 /* 48Mhz, 4 dividers */
9062 +#define PLL_TYPE3 0x00030000 /* 25Mhz, 2 dividers */
9063 +#define PLL_TYPE4 0x00008000 /* 48Mhz, 4 dividers */
9064 +#define PLL_TYPE5 0x00018000 /* 25Mhz, 4 dividers */
9065 +#define PLL_TYPE6 0x00028000 /* 100/200 or 120/240 only */
9066 +#define PLL_TYPE7 0x00038000 /* 25Mhz, 4 dividers */
9067 +
9068 +/* corecontrol */
9069 +#define CC_UARTCLKO 0x00000001 /* Drive UART with internal clock */
9070 +#define CC_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
9071 +
9072 +/* Fields in the otpstatus register */
9073 +#define OTPS_PROGFAIL 0x80000000
9074 +#define OTPS_PROTECT 0x00000007
9075 +#define OTPS_HW_PROTECT 0x00000001
9076 +#define OTPS_SW_PROTECT 0x00000002
9077 +#define OTPS_CID_PROTECT 0x00000004
9078 +
9079 +/* Fields in the otpcontrol register */
9080 +#define OTPC_RECWAIT 0xff000000
9081 +#define OTPC_PROGWAIT 0x00ffff00
9082 +#define OTPC_PRW_SHIFT 8
9083 +#define OTPC_MAXFAIL 0x00000038
9084 +#define OTPC_VSEL 0x00000006
9085 +#define OTPC_SELVL 0x00000001
9086 +
9087 +/* Fields in otpprog */
9088 +#define OTPP_COL_MASK 0x000000ff
9089 +#define OTPP_ROW_MASK 0x0000ff00
9090 +#define OTPP_ROW_SHIFT 8
9091 +#define OTPP_READERR 0x10000000
9092 +#define OTPP_VALUE 0x20000000
9093 +#define OTPP_VALUE_SHIFT 29
9094 +#define OTPP_READ 0x40000000
9095 +#define OTPP_START 0x80000000
9096 +#define OTPP_BUSY 0x80000000
9097 +
9098 +/* jtagcmd */
9099 +#define JCMD_START 0x80000000
9100 +#define JCMD_BUSY 0x80000000
9101 +#define JCMD_PAUSE 0x40000000
9102 +#define JCMD0_ACC_MASK 0x0000f000
9103 +#define JCMD0_ACC_IRDR 0x00000000
9104 +#define JCMD0_ACC_DR 0x00001000
9105 +#define JCMD0_ACC_IR 0x00002000
9106 +#define JCMD0_ACC_RESET 0x00003000
9107 +#define JCMD0_ACC_IRPDR 0x00004000
9108 +#define JCMD0_ACC_PDR 0x00005000
9109 +#define JCMD0_IRW_MASK 0x00000f00
9110 +#define JCMD_ACC_MASK 0x000f0000 /* Changes for corerev 11 */
9111 +#define JCMD_ACC_IRDR 0x00000000
9112 +#define JCMD_ACC_DR 0x00010000
9113 +#define JCMD_ACC_IR 0x00020000
9114 +#define JCMD_ACC_RESET 0x00030000
9115 +#define JCMD_ACC_IRPDR 0x00040000
9116 +#define JCMD_ACC_PDR 0x00050000
9117 +#define JCMD_IRW_MASK 0x00001f00
9118 +#define JCMD_IRW_SHIFT 8
9119 +#define JCMD_DRW_MASK 0x0000003f
9120 +
9121 +/* jtagctrl */
9122 +#define JCTRL_FORCE_CLK 4 /* Force clock */
9123 +#define JCTRL_EXT_EN 2 /* Enable external targets */
9124 +#define JCTRL_EN 1 /* Enable Jtag master */
9125 +
9126 +/* Fields in clkdiv */
9127 +#define CLKD_SFLASH 0x0f000000
9128 +#define CLKD_SFLASH_SHIFT 24
9129 +#define CLKD_OTP 0x000f0000
9130 +#define CLKD_OTP_SHIFT 16
9131 +#define CLKD_JTAG 0x00000f00
9132 +#define CLKD_JTAG_SHIFT 8
9133 +#define CLKD_UART 0x000000ff
9134 +
9135 +/* intstatus/intmask */
9136 +#define CI_GPIO 0x00000001 /* gpio intr */
9137 +#define CI_EI 0x00000002 /* ro: ext intr pin (corerev >= 3) */
9138 +#define CI_WDRESET 0x80000000 /* watchdog reset occurred */
9139 +
9140 +/* slow_clk_ctl */
9141 +#define SCC_SS_MASK 0x00000007 /* slow clock source mask */
9142 +#define SCC_SS_LPO 0x00000000 /* source of slow clock is LPO */
9143 +#define SCC_SS_XTAL 0x00000001 /* source of slow clock is crystal */
9144 +#define SCC_SS_PCI 0x00000002 /* source of slow clock is PCI */
9145 +#define SCC_LF 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */
9146 +#define SCC_LP 0x00000400 /* LPOPowerDown, 1: LPO is disabled, 0: LPO is enabled */
9147 +#define SCC_FS 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock, 0: power logic control */
9148 +#define SCC_IP 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors PLL clock disable requests from core */
9149 +#define SCC_XC 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't disable crystal when appropriate */
9150 +#define SCC_XP 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */
9151 +#define SCC_CD_MASK 0xffff0000 /* ClockDivider (SlowClk = 1/(4+divisor)) */
9152 +#define SCC_CD_SHIFT 16
9153 +
9154 +/* system_clk_ctl */
9155 +#define SYCC_IE 0x00000001 /* ILPen: Enable Idle Low Power */
9156 +#define SYCC_AE 0x00000002 /* ALPen: Enable Active Low Power */
9157 +#define SYCC_FP 0x00000004 /* ForcePLLOn */
9158 +#define SYCC_AR 0x00000008 /* Force ALP (or HT if ALPen is not set */
9159 +#define SYCC_HR 0x00000010 /* Force HT */
9160 +#define SYCC_CD_MASK 0xffff0000 /* ClkDiv (ILP = 1/(4+divisor)) */
9161 +#define SYCC_CD_SHIFT 16
9162 +
9163 +/* gpiotimerval*/
9164 +#define GPIO_ONTIME_SHIFT 16
9165 +
9166 +/* clockcontrol_n */
9167 +#define CN_N1_MASK 0x3f /* n1 control */
9168 +#define CN_N2_MASK 0x3f00 /* n2 control */
9169 +#define CN_N2_SHIFT 8
9170 +#define CN_PLLC_MASK 0xf0000 /* pll control */
9171 +#define CN_PLLC_SHIFT 16
9172 +
9173 +/* clockcontrol_sb/pci/uart */
9174 +#define CC_M1_MASK 0x3f /* m1 control */
9175 +#define CC_M2_MASK 0x3f00 /* m2 control */
9176 +#define CC_M2_SHIFT 8
9177 +#define CC_M3_MASK 0x3f0000 /* m3 control */
9178 +#define CC_M3_SHIFT 16
9179 +#define CC_MC_MASK 0x1f000000 /* mux control */
9180 +#define CC_MC_SHIFT 24
9181 +
9182 +/* N3M Clock control magic field values */
9183 +#define CC_F6_2 0x02 /* A factor of 2 in */
9184 +#define CC_F6_3 0x03 /* 6-bit fields like */
9185 +#define CC_F6_4 0x05 /* N1, M1 or M3 */
9186 +#define CC_F6_5 0x09
9187 +#define CC_F6_6 0x11
9188 +#define CC_F6_7 0x21
9189 +
9190 +#define CC_F5_BIAS 5 /* 5-bit fields get this added */
9191 +
9192 +#define CC_MC_BYPASS 0x08
9193 +#define CC_MC_M1 0x04
9194 +#define CC_MC_M1M2 0x02
9195 +#define CC_MC_M1M2M3 0x01
9196 +#define CC_MC_M1M3 0x11
9197 +
9198 +/* Type 2 Clock control magic field values */
9199 +#define CC_T2_BIAS 2 /* n1, n2, m1 & m3 bias */
9200 +#define CC_T2M2_BIAS 3 /* m2 bias */
9201 +
9202 +#define CC_T2MC_M1BYP 1
9203 +#define CC_T2MC_M2BYP 2
9204 +#define CC_T2MC_M3BYP 4
9205 +
9206 +/* Type 6 Clock control magic field values */
9207 +#define CC_T6_MMASK 1 /* bits of interest in m */
9208 +#define CC_T6_M0 120000000 /* sb clock for m = 0 */
9209 +#define CC_T6_M1 100000000 /* sb clock for m = 1 */
9210 +#define SB2MIPS_T6(sb) (2 * (sb))
9211 +
9212 +/* Common clock base */
9213 +#define CC_CLOCK_BASE1 24000000 /* Half the clock freq */
9214 +#define CC_CLOCK_BASE2 12500000 /* Alternate crystal on some PLL's */
9215 +
9216 +/* Clock control values for 200Mhz in 5350 */
9217 +#define CLKC_5350_N 0x0311
9218 +#define CLKC_5350_M 0x04020009
9219 +
9220 +/* Flash types in the chipcommon capabilities register */
9221 +#define FLASH_NONE 0x000 /* No flash */
9222 +#define SFLASH_ST 0x100 /* ST serial flash */
9223 +#define SFLASH_AT 0x200 /* Atmel serial flash */
9224 +#define PFLASH 0x700 /* Parallel flash */
9225 +
9226 +/* Bits in the config registers */
9227 +#define CC_CFG_EN 0x0001 /* Enable */
9228 +#define CC_CFG_EM_MASK 0x000e /* Extif Mode */
9229 +#define CC_CFG_EM_ASYNC 0x0002 /* Async/Parallel flash */
9230 +#define CC_CFG_EM_SYNC 0x0004 /* Synchronous */
9231 +#define CC_CFG_EM_PCMCIA 0x0008 /* PCMCIA */
9232 +#define CC_CFG_EM_IDE 0x000a /* IDE */
9233 +#define CC_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */
9234 +#define CC_CFG_CD_MASK 0x0060 /* Sync: Clock divisor */
9235 +#define CC_CFG_CE 0x0080 /* Sync: Clock enable */
9236 +#define CC_CFG_SB 0x0100 /* Sync: Size/Bytestrobe */
9237 +
9238 +/* Start/busy bit in flashcontrol */
9239 +#define SFLASH_START 0x80000000
9240 +#define SFLASH_BUSY SFLASH_START
9241 +
9242 +/* flashcontrol opcodes for ST flashes */
9243 +#define SFLASH_ST_WREN 0x0006 /* Write Enable */
9244 +#define SFLASH_ST_WRDIS 0x0004 /* Write Disable */
9245 +#define SFLASH_ST_RDSR 0x0105 /* Read Status Register */
9246 +#define SFLASH_ST_WRSR 0x0101 /* Write Status Register */
9247 +#define SFLASH_ST_READ 0x0303 /* Read Data Bytes */
9248 +#define SFLASH_ST_PP 0x0302 /* Page Program */
9249 +#define SFLASH_ST_SE 0x02d8 /* Sector Erase */
9250 +#define SFLASH_ST_BE 0x00c7 /* Bulk Erase */
9251 +#define SFLASH_ST_DP 0x00b9 /* Deep Power-down */
9252 +#define SFLASH_ST_RES 0x03ab /* Read Electronic Signature */
9253 +
9254 +/* Status register bits for ST flashes */
9255 +#define SFLASH_ST_WIP 0x01 /* Write In Progress */
9256 +#define SFLASH_ST_WEL 0x02 /* Write Enable Latch */
9257 +#define SFLASH_ST_BP_MASK 0x1c /* Block Protect */
9258 +#define SFLASH_ST_BP_SHIFT 2
9259 +#define SFLASH_ST_SRWD 0x80 /* Status Register Write Disable */
9260 +
9261 +/* flashcontrol opcodes for Atmel flashes */
9262 +#define SFLASH_AT_READ 0x07e8
9263 +#define SFLASH_AT_PAGE_READ 0x07d2
9264 +#define SFLASH_AT_BUF1_READ
9265 +#define SFLASH_AT_BUF2_READ
9266 +#define SFLASH_AT_STATUS 0x01d7
9267 +#define SFLASH_AT_BUF1_WRITE 0x0384
9268 +#define SFLASH_AT_BUF2_WRITE 0x0387
9269 +#define SFLASH_AT_BUF1_ERASE_PROGRAM 0x0283
9270 +#define SFLASH_AT_BUF2_ERASE_PROGRAM 0x0286
9271 +#define SFLASH_AT_BUF1_PROGRAM 0x0288
9272 +#define SFLASH_AT_BUF2_PROGRAM 0x0289
9273 +#define SFLASH_AT_PAGE_ERASE 0x0281
9274 +#define SFLASH_AT_BLOCK_ERASE 0x0250
9275 +#define SFLASH_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382
9276 +#define SFLASH_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385
9277 +#define SFLASH_AT_BUF1_LOAD 0x0253
9278 +#define SFLASH_AT_BUF2_LOAD 0x0255
9279 +#define SFLASH_AT_BUF1_COMPARE 0x0260
9280 +#define SFLASH_AT_BUF2_COMPARE 0x0261
9281 +#define SFLASH_AT_BUF1_REPROGRAM 0x0258
9282 +#define SFLASH_AT_BUF2_REPROGRAM 0x0259
9283 +
9284 +/* Status register bits for Atmel flashes */
9285 +#define SFLASH_AT_READY 0x80
9286 +#define SFLASH_AT_MISMATCH 0x40
9287 +#define SFLASH_AT_ID_MASK 0x38
9288 +#define SFLASH_AT_ID_SHIFT 3
9289 +
9290 +/* OTP regions */
9291 +#define OTP_HW_REGION OTPS_HW_PROTECT
9292 +#define OTP_SW_REGION OTPS_SW_PROTECT
9293 +#define OTP_CID_REGION OTPS_CID_PROTECT
9294 +
9295 +/* OTP regions (Byte offsets from otp size) */
9296 +#define OTP_SWLIM_OFF (-8)
9297 +#define OTP_CIDBASE_OFF 0
9298 +#define OTP_CIDLIM_OFF 8
9299 +
9300 +/* Predefined OTP words (Word offset from otp size) */
9301 +#define OTP_BOUNDARY_OFF (-4)
9302 +#define OTP_HWSIGN_OFF (-3)
9303 +#define OTP_SWSIGN_OFF (-2)
9304 +#define OTP_CIDSIGN_OFF (-1)
9305 +
9306 +#define OTP_CID_OFF 0
9307 +#define OTP_PKG_OFF 1
9308 +#define OTP_FID_OFF 2
9309 +#define OTP_RSV_OFF 3
9310 +#define OTP_LIM_OFF 4
9311 +
9312 +#define OTP_SIGNATURE 0x578a
9313 +#define OTP_MAGIC 0x4e56
9314 +
9315 +#endif /* _SBCHIPC_H */
9316 diff -urN linux.old/arch/mips/bcm947xx/include/sbconfig.h linux.dev/arch/mips/bcm947xx/include/sbconfig.h
9317 --- linux.old/arch/mips/bcm947xx/include/sbconfig.h 1970-01-01 01:00:00.000000000 +0100
9318 +++ linux.dev/arch/mips/bcm947xx/include/sbconfig.h 2005-12-15 15:35:24.538815250 +0100
9319 @@ -0,0 +1,342 @@
9320 +/*
9321 + * Broadcom SiliconBackplane hardware register definitions.
9322 + *
9323 + * Copyright 2005, Broadcom Corporation
9324 + * All Rights Reserved.
9325 + *
9326 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
9327 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9328 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
9329 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
9330 + * $Id$
9331 + */
9332 +
9333 +#ifndef _SBCONFIG_H
9334 +#define _SBCONFIG_H
9335 +
9336 +/* cpp contortions to concatenate w/arg prescan */
9337 +#ifndef PAD
9338 +#define _PADLINE(line) pad ## line
9339 +#define _XSTR(line) _PADLINE(line)
9340 +#define PAD _XSTR(__LINE__)
9341 +#endif
9342 +
9343 +/*
9344 + * SiliconBackplane Address Map.
9345 + * All regions may not exist on all chips.
9346 + */
9347 +#define SB_SDRAM_BASE 0x00000000 /* Physical SDRAM */
9348 +#define SB_PCI_MEM 0x08000000 /* Host Mode sb2pcitranslation0 (64 MB) */
9349 +#define SB_PCI_CFG 0x0c000000 /* Host Mode sb2pcitranslation1 (64 MB) */
9350 +#define SB_SDRAM_SWAPPED 0x10000000 /* Byteswapped Physical SDRAM */
9351 +#define SB_ENUM_BASE 0x18000000 /* Enumeration space base */
9352 +#define SB_ENUM_LIM 0x18010000 /* Enumeration space limit */
9353 +
9354 +#define SB_FLASH2 0x1c000000 /* Flash Region 2 (region 1 shadowed here) */
9355 +#define SB_FLASH2_SZ 0x02000000 /* Size of Flash Region 2 */
9356 +
9357 +#define SB_EXTIF_BASE 0x1f000000 /* External Interface region base address */
9358 +#define SB_FLASH1 0x1fc00000 /* Flash Region 1 */
9359 +#define SB_FLASH1_SZ 0x00400000 /* Size of Flash Region 1 */
9360 +
9361 +#define SB_PCI_DMA 0x40000000 /* Client Mode sb2pcitranslation2 (1 GB) */
9362 +#define SB_PCI_DMA_SZ 0x40000000 /* Client Mode sb2pcitranslation2 size in bytes */
9363 +#define SB_PCIE_DMA_L32 0x00000000 /* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), low 32 bits */
9364 +#define SB_PCIE_DMA_H32 0x80000000 /* PCIE Client Mode sb2pcitranslation2 (2 ZettaBytes), high 32 bits */
9365 +#define SB_EUART (SB_EXTIF_BASE + 0x00800000)
9366 +#define SB_LED (SB_EXTIF_BASE + 0x00900000)
9367 +
9368 +
9369 +/* enumeration space related defs */
9370 +#define SB_CORE_SIZE 0x1000 /* each core gets 4Kbytes for registers */
9371 +#define SB_MAXCORES ((SB_ENUM_LIM - SB_ENUM_BASE)/SB_CORE_SIZE)
9372 +#define SBCONFIGOFF 0xf00 /* core sbconfig regs are top 256bytes of regs */
9373 +#define SBCONFIGSIZE 256 /* sizeof (sbconfig_t) */
9374 +
9375 +/* mips address */
9376 +#define SB_EJTAG 0xff200000 /* MIPS EJTAG space (2M) */
9377 +
9378 +/*
9379 + * Sonics Configuration Space Registers.
9380 + */
9381 +#define SBIPSFLAG 0x08
9382 +#define SBTPSFLAG 0x18
9383 +#define SBTMERRLOGA 0x48 /* sonics >= 2.3 */
9384 +#define SBTMERRLOG 0x50 /* sonics >= 2.3 */
9385 +#define SBADMATCH3 0x60
9386 +#define SBADMATCH2 0x68
9387 +#define SBADMATCH1 0x70
9388 +#define SBIMSTATE 0x90
9389 +#define SBINTVEC 0x94
9390 +#define SBTMSTATELOW 0x98
9391 +#define SBTMSTATEHIGH 0x9c
9392 +#define SBBWA0 0xa0
9393 +#define SBIMCONFIGLOW 0xa8
9394 +#define SBIMCONFIGHIGH 0xac
9395 +#define SBADMATCH0 0xb0
9396 +#define SBTMCONFIGLOW 0xb8
9397 +#define SBTMCONFIGHIGH 0xbc
9398 +#define SBBCONFIG 0xc0
9399 +#define SBBSTATE 0xc8
9400 +#define SBACTCNFG 0xd8
9401 +#define SBFLAGST 0xe8
9402 +#define SBIDLOW 0xf8
9403 +#define SBIDHIGH 0xfc
9404 +
9405 +#ifndef _LANGUAGE_ASSEMBLY
9406 +
9407 +typedef volatile struct _sbconfig {
9408 + uint32 PAD[2];
9409 + uint32 sbipsflag; /* initiator port ocp slave flag */
9410 + uint32 PAD[3];
9411 + uint32 sbtpsflag; /* target port ocp slave flag */
9412 + uint32 PAD[11];
9413 + uint32 sbtmerrloga; /* (sonics >= 2.3) */
9414 + uint32 PAD;
9415 + uint32 sbtmerrlog; /* (sonics >= 2.3) */
9416 + uint32 PAD[3];
9417 + uint32 sbadmatch3; /* address match3 */
9418 + uint32 PAD;
9419 + uint32 sbadmatch2; /* address match2 */
9420 + uint32 PAD;
9421 + uint32 sbadmatch1; /* address match1 */
9422 + uint32 PAD[7];
9423 + uint32 sbimstate; /* initiator agent state */
9424 + uint32 sbintvec; /* interrupt mask */
9425 + uint32 sbtmstatelow; /* target state */
9426 + uint32 sbtmstatehigh; /* target state */
9427 + uint32 sbbwa0; /* bandwidth allocation table0 */
9428 + uint32 PAD;
9429 + uint32 sbimconfiglow; /* initiator configuration */
9430 + uint32 sbimconfighigh; /* initiator configuration */
9431 + uint32 sbadmatch0; /* address match0 */
9432 + uint32 PAD;
9433 + uint32 sbtmconfiglow; /* target configuration */
9434 + uint32 sbtmconfighigh; /* target configuration */
9435 + uint32 sbbconfig; /* broadcast configuration */
9436 + uint32 PAD;
9437 + uint32 sbbstate; /* broadcast state */
9438 + uint32 PAD[3];
9439 + uint32 sbactcnfg; /* activate configuration */
9440 + uint32 PAD[3];
9441 + uint32 sbflagst; /* current sbflags */
9442 + uint32 PAD[3];
9443 + uint32 sbidlow; /* identification */
9444 + uint32 sbidhigh; /* identification */
9445 +} sbconfig_t;
9446 +
9447 +#endif /* _LANGUAGE_ASSEMBLY */
9448 +
9449 +/* sbipsflag */
9450 +#define SBIPS_INT1_MASK 0x3f /* which sbflags get routed to mips interrupt 1 */
9451 +#define SBIPS_INT1_SHIFT 0
9452 +#define SBIPS_INT2_MASK 0x3f00 /* which sbflags get routed to mips interrupt 2 */
9453 +#define SBIPS_INT2_SHIFT 8
9454 +#define SBIPS_INT3_MASK 0x3f0000 /* which sbflags get routed to mips interrupt 3 */
9455 +#define SBIPS_INT3_SHIFT 16
9456 +#define SBIPS_INT4_MASK 0x3f000000 /* which sbflags get routed to mips interrupt 4 */
9457 +#define SBIPS_INT4_SHIFT 24
9458 +
9459 +/* sbtpsflag */
9460 +#define SBTPS_NUM0_MASK 0x3f /* interrupt sbFlag # generated by this core */
9461 +#define SBTPS_F0EN0 0x40 /* interrupt is always sent on the backplane */
9462 +
9463 +/* sbtmerrlog */
9464 +#define SBTMEL_CM 0x00000007 /* command */
9465 +#define SBTMEL_CI 0x0000ff00 /* connection id */
9466 +#define SBTMEL_EC 0x0f000000 /* error code */
9467 +#define SBTMEL_ME 0x80000000 /* multiple error */
9468 +
9469 +/* sbimstate */
9470 +#define SBIM_PC 0xf /* pipecount */
9471 +#define SBIM_AP_MASK 0x30 /* arbitration policy */
9472 +#define SBIM_AP_BOTH 0x00 /* use both timeslaces and token */
9473 +#define SBIM_AP_TS 0x10 /* use timesliaces only */
9474 +#define SBIM_AP_TK 0x20 /* use token only */
9475 +#define SBIM_AP_RSV 0x30 /* reserved */
9476 +#define SBIM_IBE 0x20000 /* inbanderror */
9477 +#define SBIM_TO 0x40000 /* timeout */
9478 +#define SBIM_BY 0x01800000 /* busy (sonics >= 2.3) */
9479 +#define SBIM_RJ 0x02000000 /* reject (sonics >= 2.3) */
9480 +
9481 +/* sbtmstatelow */
9482 +#define SBTML_RESET 0x1 /* reset */
9483 +#define SBTML_REJ_MASK 0x6 /* reject */
9484 +#define SBTML_REJ_SHIFT 1
9485 +#define SBTML_CLK 0x10000 /* clock enable */
9486 +#define SBTML_FGC 0x20000 /* force gated clocks on */
9487 +#define SBTML_FL_MASK 0x3ffc0000 /* core-specific flags */
9488 +#define SBTML_PE 0x40000000 /* pme enable */
9489 +#define SBTML_BE 0x80000000 /* bist enable */
9490 +
9491 +/* sbtmstatehigh */
9492 +#define SBTMH_SERR 0x1 /* serror */
9493 +#define SBTMH_INT 0x2 /* interrupt */
9494 +#define SBTMH_BUSY 0x4 /* busy */
9495 +#define SBTMH_TO 0x00000020 /* timeout (sonics >= 2.3) */
9496 +#define SBTMH_FL_MASK 0x1fff0000 /* core-specific flags */
9497 +#define SBTMH_DMA64 0x10000000 /* supports DMA with 64-bit addresses */
9498 +#define SBTMH_GCR 0x20000000 /* gated clock request */
9499 +#define SBTMH_BISTF 0x40000000 /* bist failed */
9500 +#define SBTMH_BISTD 0x80000000 /* bist done */
9501 +
9502 +
9503 +/* sbbwa0 */
9504 +#define SBBWA_TAB0_MASK 0xffff /* lookup table 0 */
9505 +#define SBBWA_TAB1_MASK 0xffff /* lookup table 1 */
9506 +#define SBBWA_TAB1_SHIFT 16
9507 +
9508 +/* sbimconfiglow */
9509 +#define SBIMCL_STO_MASK 0x7 /* service timeout */
9510 +#define SBIMCL_RTO_MASK 0x70 /* request timeout */
9511 +#define SBIMCL_RTO_SHIFT 4
9512 +#define SBIMCL_CID_MASK 0xff0000 /* connection id */
9513 +#define SBIMCL_CID_SHIFT 16
9514 +
9515 +/* sbimconfighigh */
9516 +#define SBIMCH_IEM_MASK 0xc /* inband error mode */
9517 +#define SBIMCH_TEM_MASK 0x30 /* timeout error mode */
9518 +#define SBIMCH_TEM_SHIFT 4
9519 +#define SBIMCH_BEM_MASK 0xc0 /* bus error mode */
9520 +#define SBIMCH_BEM_SHIFT 6
9521 +
9522 +/* sbadmatch0 */
9523 +#define SBAM_TYPE_MASK 0x3 /* address type */
9524 +#define SBAM_AD64 0x4 /* reserved */
9525 +#define SBAM_ADINT0_MASK 0xf8 /* type0 size */
9526 +#define SBAM_ADINT0_SHIFT 3
9527 +#define SBAM_ADINT1_MASK 0x1f8 /* type1 size */
9528 +#define SBAM_ADINT1_SHIFT 3
9529 +#define SBAM_ADINT2_MASK 0x1f8 /* type2 size */
9530 +#define SBAM_ADINT2_SHIFT 3
9531 +#define SBAM_ADEN 0x400 /* enable */
9532 +#define SBAM_ADNEG 0x800 /* negative decode */
9533 +#define SBAM_BASE0_MASK 0xffffff00 /* type0 base address */
9534 +#define SBAM_BASE0_SHIFT 8
9535 +#define SBAM_BASE1_MASK 0xfffff000 /* type1 base address for the core */
9536 +#define SBAM_BASE1_SHIFT 12
9537 +#define SBAM_BASE2_MASK 0xffff0000 /* type2 base address for the core */
9538 +#define SBAM_BASE2_SHIFT 16
9539 +
9540 +/* sbtmconfiglow */
9541 +#define SBTMCL_CD_MASK 0xff /* clock divide */
9542 +#define SBTMCL_CO_MASK 0xf800 /* clock offset */
9543 +#define SBTMCL_CO_SHIFT 11
9544 +#define SBTMCL_IF_MASK 0xfc0000 /* interrupt flags */
9545 +#define SBTMCL_IF_SHIFT 18
9546 +#define SBTMCL_IM_MASK 0x3000000 /* interrupt mode */
9547 +#define SBTMCL_IM_SHIFT 24
9548 +
9549 +/* sbtmconfighigh */
9550 +#define SBTMCH_BM_MASK 0x3 /* busy mode */
9551 +#define SBTMCH_RM_MASK 0x3 /* retry mode */
9552 +#define SBTMCH_RM_SHIFT 2
9553 +#define SBTMCH_SM_MASK 0x30 /* stop mode */
9554 +#define SBTMCH_SM_SHIFT 4
9555 +#define SBTMCH_EM_MASK 0x300 /* sb error mode */
9556 +#define SBTMCH_EM_SHIFT 8
9557 +#define SBTMCH_IM_MASK 0xc00 /* int mode */
9558 +#define SBTMCH_IM_SHIFT 10
9559 +
9560 +/* sbbconfig */
9561 +#define SBBC_LAT_MASK 0x3 /* sb latency */
9562 +#define SBBC_MAX0_MASK 0xf0000 /* maxccntr0 */
9563 +#define SBBC_MAX0_SHIFT 16
9564 +#define SBBC_MAX1_MASK 0xf00000 /* maxccntr1 */
9565 +#define SBBC_MAX1_SHIFT 20
9566 +
9567 +/* sbbstate */
9568 +#define SBBS_SRD 0x1 /* st reg disable */
9569 +#define SBBS_HRD 0x2 /* hold reg disable */
9570 +
9571 +/* sbidlow */
9572 +#define SBIDL_CS_MASK 0x3 /* config space */
9573 +#define SBIDL_AR_MASK 0x38 /* # address ranges supported */
9574 +#define SBIDL_AR_SHIFT 3
9575 +#define SBIDL_SYNCH 0x40 /* sync */
9576 +#define SBIDL_INIT 0x80 /* initiator */
9577 +#define SBIDL_MINLAT_MASK 0xf00 /* minimum backplane latency */
9578 +#define SBIDL_MINLAT_SHIFT 8
9579 +#define SBIDL_MAXLAT 0xf000 /* maximum backplane latency */
9580 +#define SBIDL_MAXLAT_SHIFT 12
9581 +#define SBIDL_FIRST 0x10000 /* this initiator is first */
9582 +#define SBIDL_CW_MASK 0xc0000 /* cycle counter width */
9583 +#define SBIDL_CW_SHIFT 18
9584 +#define SBIDL_TP_MASK 0xf00000 /* target ports */
9585 +#define SBIDL_TP_SHIFT 20
9586 +#define SBIDL_IP_MASK 0xf000000 /* initiator ports */
9587 +#define SBIDL_IP_SHIFT 24
9588 +#define SBIDL_RV_MASK 0xf0000000 /* sonics backplane revision code */
9589 +#define SBIDL_RV_SHIFT 28
9590 +#define SBIDL_RV_2_2 0x00000000 /* version 2.2 or earlier */
9591 +#define SBIDL_RV_2_3 0x10000000 /* version 2.3 */
9592 +
9593 +/* sbidhigh */
9594 +#define SBIDH_RC_MASK 0x000f /* revision code */
9595 +#define SBIDH_RCE_MASK 0x7000 /* revision code extension field */
9596 +#define SBIDH_RCE_SHIFT 8
9597 +#define SBCOREREV(sbidh) \
9598 + ((((sbidh) & SBIDH_RCE_MASK) >> SBIDH_RCE_SHIFT) | ((sbidh) & SBIDH_RC_MASK))
9599 +#define SBIDH_CC_MASK 0x8ff0 /* core code */
9600 +#define SBIDH_CC_SHIFT 4
9601 +#define SBIDH_VC_MASK 0xffff0000 /* vendor code */
9602 +#define SBIDH_VC_SHIFT 16
9603 +
9604 +#define SB_COMMIT 0xfd8 /* update buffered registers value */
9605 +
9606 +/* vendor codes */
9607 +#define SB_VEND_BCM 0x4243 /* Broadcom's SB vendor code */
9608 +
9609 +/* core codes */
9610 +#define SB_CC 0x800 /* chipcommon core */
9611 +#define SB_ILINE20 0x801 /* iline20 core */
9612 +#define SB_SDRAM 0x803 /* sdram core */
9613 +#define SB_PCI 0x804 /* pci core */
9614 +#define SB_MIPS 0x805 /* mips core */
9615 +#define SB_ENET 0x806 /* enet mac core */
9616 +#define SB_CODEC 0x807 /* v90 codec core */
9617 +#define SB_USB 0x808 /* usb 1.1 host/device core */
9618 +#define SB_ADSL 0x809 /* ADSL core */
9619 +#define SB_ILINE100 0x80a /* iline100 core */
9620 +#define SB_IPSEC 0x80b /* ipsec core */
9621 +#define SB_PCMCIA 0x80d /* pcmcia core */
9622 +#define SB_SOCRAM 0x80e /* internal memory core */
9623 +#define SB_MEMC 0x80f /* memc sdram core */
9624 +#define SB_EXTIF 0x811 /* external interface core */
9625 +#define SB_D11 0x812 /* 802.11 MAC core */
9626 +#define SB_MIPS33 0x816 /* mips3302 core */
9627 +#define SB_USB11H 0x817 /* usb 1.1 host core */
9628 +#define SB_USB11D 0x818 /* usb 1.1 device core */
9629 +#define SB_USB20H 0x819 /* usb 2.0 host core */
9630 +#define SB_USB20D 0x81a /* usb 2.0 device core */
9631 +#define SB_SDIOH 0x81b /* sdio host core */
9632 +#define SB_ROBO 0x81c /* roboswitch core */
9633 +#define SB_ATA100 0x81d /* parallel ATA core */
9634 +#define SB_SATAXOR 0x81e /* serial ATA & XOR DMA core */
9635 +#define SB_GIGETH 0x81f /* gigabit ethernet core */
9636 +#define SB_PCIE 0x820 /* pci express core */
9637 +#define SB_SRAMC 0x822 /* SRAM controller core */
9638 +#define SB_MINIMAC 0x823 /* MINI MAC/phy core */
9639 +
9640 +#define SB_CC_IDX 0 /* chipc, when present, is always core 0 */
9641 +
9642 +/* Not really related to Silicon Backplane, but a couple of software
9643 + * conventions for the use the flash space:
9644 + */
9645 +
9646 +/* Minumum amount of flash we support */
9647 +#define FLASH_MIN 0x00020000 /* Minimum flash size */
9648 +
9649 +/* A boot/binary may have an embedded block that describes its size */
9650 +#define BISZ_OFFSET 0x3e0 /* At this offset into the binary */
9651 +#define BISZ_MAGIC 0x4249535a /* Marked with this value: 'BISZ' */
9652 +#define BISZ_MAGIC_IDX 0 /* Word 0: magic */
9653 +#define BISZ_TXTST_IDX 1 /* 1: text start */
9654 +#define BISZ_TXTEND_IDX 2 /* 2: text start */
9655 +#define BISZ_DATAST_IDX 3 /* 3: text start */
9656 +#define BISZ_DATAEND_IDX 4 /* 4: text start */
9657 +#define BISZ_BSSST_IDX 5 /* 5: text start */
9658 +#define BISZ_BSSEND_IDX 6 /* 6: text start */
9659 +#define BISZ_SIZE 7 /* descriptor size in 32-bit intergers */
9660 +
9661 +#endif /* _SBCONFIG_H */
9662 diff -urN linux.old/arch/mips/bcm947xx/include/sbextif.h linux.dev/arch/mips/bcm947xx/include/sbextif.h
9663 --- linux.old/arch/mips/bcm947xx/include/sbextif.h 1970-01-01 01:00:00.000000000 +0100
9664 +++ linux.dev/arch/mips/bcm947xx/include/sbextif.h 2005-12-15 16:48:55.651993750 +0100
9665 @@ -0,0 +1,242 @@
9666 +/*
9667 + * Hardware-specific External Interface I/O core definitions
9668 + * for the BCM47xx family of SiliconBackplane-based chips.
9669 + *
9670 + * The External Interface core supports a total of three external chip selects
9671 + * supporting external interfaces. One of the external chip selects is
9672 + * used for Flash, one is used for PCMCIA, and the other may be
9673 + * programmed to support either a synchronous interface or an
9674 + * asynchronous interface. The asynchronous interface can be used to
9675 + * support external devices such as UARTs and the BCM2019 Bluetooth
9676 + * baseband processor.
9677 + * The external interface core also contains 2 on-chip 16550 UARTs, clock
9678 + * frequency control, a watchdog interrupt timer, and a GPIO interface.
9679 + *
9680 + * Copyright 2005, Broadcom Corporation
9681 + * All Rights Reserved.
9682 + *
9683 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
9684 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9685 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
9686 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
9687 + * $Id$
9688 + */
9689 +
9690 +#ifndef _SBEXTIF_H
9691 +#define _SBEXTIF_H
9692 +
9693 +/* external interface address space */
9694 +#define EXTIF_PCMCIA_MEMBASE(x) (x)
9695 +#define EXTIF_PCMCIA_IOBASE(x) ((x) + 0x100000)
9696 +#define EXTIF_PCMCIA_CFGBASE(x) ((x) + 0x200000)
9697 +#define EXTIF_CFGIF_BASE(x) ((x) + 0x800000)
9698 +#define EXTIF_FLASH_BASE(x) ((x) + 0xc00000)
9699 +
9700 +/* cpp contortions to concatenate w/arg prescan */
9701 +#ifndef PAD
9702 +#define _PADLINE(line) pad ## line
9703 +#define _XSTR(line) _PADLINE(line)
9704 +#define PAD _XSTR(__LINE__)
9705 +#endif /* PAD */
9706 +
9707 +/*
9708 + * The multiple instances of output and output enable registers
9709 + * are present to allow driver software for multiple cores to control
9710 + * gpio outputs without needing to share a single register pair.
9711 + */
9712 +struct gpiouser {
9713 + uint32 out;
9714 + uint32 outen;
9715 +};
9716 +#define NGPIOUSER 5
9717 +
9718 +typedef volatile struct {
9719 + uint32 corecontrol;
9720 + uint32 extstatus;
9721 + uint32 PAD[2];
9722 +
9723 + /* pcmcia control registers */
9724 + uint32 pcmcia_config;
9725 + uint32 pcmcia_memwait;
9726 + uint32 pcmcia_attrwait;
9727 + uint32 pcmcia_iowait;
9728 +
9729 + /* programmable interface control registers */
9730 + uint32 prog_config;
9731 + uint32 prog_waitcount;
9732 +
9733 + /* flash control registers */
9734 + uint32 flash_config;
9735 + uint32 flash_waitcount;
9736 + uint32 PAD[4];
9737 +
9738 + uint32 watchdog;
9739 +
9740 + /* clock control */
9741 + uint32 clockcontrol_n;
9742 + uint32 clockcontrol_sb;
9743 + uint32 clockcontrol_pci;
9744 + uint32 clockcontrol_mii;
9745 + uint32 PAD[3];
9746 +
9747 + /* gpio */
9748 + uint32 gpioin;
9749 + struct gpiouser gpio[NGPIOUSER];
9750 + uint32 PAD;
9751 + uint32 ejtagouten;
9752 + uint32 gpiointpolarity;
9753 + uint32 gpiointmask;
9754 + uint32 PAD[153];
9755 +
9756 + uint8 uartdata;
9757 + uint8 PAD[3];
9758 + uint8 uartimer;
9759 + uint8 PAD[3];
9760 + uint8 uartfcr;
9761 + uint8 PAD[3];
9762 + uint8 uartlcr;
9763 + uint8 PAD[3];
9764 + uint8 uartmcr;
9765 + uint8 PAD[3];
9766 + uint8 uartlsr;
9767 + uint8 PAD[3];
9768 + uint8 uartmsr;
9769 + uint8 PAD[3];
9770 + uint8 uartscratch;
9771 + uint8 PAD[3];
9772 +} extifregs_t;
9773 +
9774 +/* corecontrol */
9775 +#define CC_UE (1 << 0) /* uart enable */
9776 +
9777 +/* extstatus */
9778 +#define ES_EM (1 << 0) /* endian mode (ro) */
9779 +#define ES_EI (1 << 1) /* external interrupt pin (ro) */
9780 +#define ES_GI (1 << 2) /* gpio interrupt pin (ro) */
9781 +
9782 +/* gpio bit mask */
9783 +#define GPIO_BIT0 (1 << 0)
9784 +#define GPIO_BIT1 (1 << 1)
9785 +#define GPIO_BIT2 (1 << 2)
9786 +#define GPIO_BIT3 (1 << 3)
9787 +#define GPIO_BIT4 (1 << 4)
9788 +#define GPIO_BIT5 (1 << 5)
9789 +#define GPIO_BIT6 (1 << 6)
9790 +#define GPIO_BIT7 (1 << 7)
9791 +
9792 +
9793 +/* pcmcia/prog/flash_config */
9794 +#define CF_EN (1 << 0) /* enable */
9795 +#define CF_EM_MASK 0xe /* mode */
9796 +#define CF_EM_SHIFT 1
9797 +#define CF_EM_FLASH 0x0 /* flash/asynchronous mode */
9798 +#define CF_EM_SYNC 0x2 /* synchronous mode */
9799 +#define CF_EM_PCMCIA 0x4 /* pcmcia mode */
9800 +#define CF_DS (1 << 4) /* destsize: 0=8bit, 1=16bit */
9801 +#define CF_BS (1 << 5) /* byteswap */
9802 +#define CF_CD_MASK 0xc0 /* clock divider */
9803 +#define CF_CD_SHIFT 6
9804 +#define CF_CD_DIV2 0x0 /* backplane/2 */
9805 +#define CF_CD_DIV3 0x40 /* backplane/3 */
9806 +#define CF_CD_DIV4 0x80 /* backplane/4 */
9807 +#define CF_CE (1 << 8) /* clock enable */
9808 +#define CF_SB (1 << 9) /* size/bytestrobe (synch only) */
9809 +
9810 +/* pcmcia_memwait */
9811 +#define PM_W0_MASK 0x3f /* waitcount0 */
9812 +#define PM_W1_MASK 0x1f00 /* waitcount1 */
9813 +#define PM_W1_SHIFT 8
9814 +#define PM_W2_MASK 0x1f0000 /* waitcount2 */
9815 +#define PM_W2_SHIFT 16
9816 +#define PM_W3_MASK 0x1f000000 /* waitcount3 */
9817 +#define PM_W3_SHIFT 24
9818 +
9819 +/* pcmcia_attrwait */
9820 +#define PA_W0_MASK 0x3f /* waitcount0 */
9821 +#define PA_W1_MASK 0x1f00 /* waitcount1 */
9822 +#define PA_W1_SHIFT 8
9823 +#define PA_W2_MASK 0x1f0000 /* waitcount2 */
9824 +#define PA_W2_SHIFT 16
9825 +#define PA_W3_MASK 0x1f000000 /* waitcount3 */
9826 +#define PA_W3_SHIFT 24
9827 +
9828 +/* pcmcia_iowait */
9829 +#define PI_W0_MASK 0x3f /* waitcount0 */
9830 +#define PI_W1_MASK 0x1f00 /* waitcount1 */
9831 +#define PI_W1_SHIFT 8
9832 +#define PI_W2_MASK 0x1f0000 /* waitcount2 */
9833 +#define PI_W2_SHIFT 16
9834 +#define PI_W3_MASK 0x1f000000 /* waitcount3 */
9835 +#define PI_W3_SHIFT 24
9836 +
9837 +/* prog_waitcount */
9838 +#define PW_W0_MASK 0x0000001f /* waitcount0 */
9839 +#define PW_W1_MASK 0x00001f00 /* waitcount1 */
9840 +#define PW_W1_SHIFT 8
9841 +#define PW_W2_MASK 0x001f0000 /* waitcount2 */
9842 +#define PW_W2_SHIFT 16
9843 +#define PW_W3_MASK 0x1f000000 /* waitcount3 */
9844 +#define PW_W3_SHIFT 24
9845 +
9846 +#define PW_W0 0x0000000c
9847 +#define PW_W1 0x00000a00
9848 +#define PW_W2 0x00020000
9849 +#define PW_W3 0x01000000
9850 +
9851 +/* flash_waitcount */
9852 +#define FW_W0_MASK 0x1f /* waitcount0 */
9853 +#define FW_W1_MASK 0x1f00 /* waitcount1 */
9854 +#define FW_W1_SHIFT 8
9855 +#define FW_W2_MASK 0x1f0000 /* waitcount2 */
9856 +#define FW_W2_SHIFT 16
9857 +#define FW_W3_MASK 0x1f000000 /* waitcount3 */
9858 +#define FW_W3_SHIFT 24
9859 +
9860 +/* watchdog */
9861 +#define WATCHDOG_CLOCK 48000000 /* Hz */
9862 +
9863 +/* clockcontrol_n */
9864 +#define CN_N1_MASK 0x3f /* n1 control */
9865 +#define CN_N2_MASK 0x3f00 /* n2 control */
9866 +#define CN_N2_SHIFT 8
9867 +
9868 +/* clockcontrol_sb/pci/mii */
9869 +#define CC_M1_MASK 0x3f /* m1 control */
9870 +#define CC_M2_MASK 0x3f00 /* m2 control */
9871 +#define CC_M2_SHIFT 8
9872 +#define CC_M3_MASK 0x3f0000 /* m3 control */
9873 +#define CC_M3_SHIFT 16
9874 +#define CC_MC_MASK 0x1f000000 /* mux control */
9875 +#define CC_MC_SHIFT 24
9876 +
9877 +/* Clock control default values */
9878 +#define CC_DEF_N 0x0009 /* Default values for bcm4710 */
9879 +#define CC_DEF_100 0x04020011
9880 +#define CC_DEF_33 0x11030011
9881 +#define CC_DEF_25 0x11050011
9882 +
9883 +/* Clock control values for 125Mhz */
9884 +#define CC_125_N 0x0802
9885 +#define CC_125_M 0x04020009
9886 +#define CC_125_M25 0x11090009
9887 +#define CC_125_M33 0x11090005
9888 +
9889 +/* Clock control magic field values */
9890 +#define CC_F6_2 0x02 /* A factor of 2 in */
9891 +#define CC_F6_3 0x03 /* 6-bit fields like */
9892 +#define CC_F6_4 0x05 /* N1, M1 or M3 */
9893 +#define CC_F6_5 0x09
9894 +#define CC_F6_6 0x11
9895 +#define CC_F6_7 0x21
9896 +
9897 +#define CC_F5_BIAS 5 /* 5-bit fields get this added */
9898 +
9899 +#define CC_MC_BYPASS 0x08
9900 +#define CC_MC_M1 0x04
9901 +#define CC_MC_M1M2 0x02
9902 +#define CC_MC_M1M2M3 0x01
9903 +#define CC_MC_M1M3 0x11
9904 +
9905 +#define CC_CLOCK_BASE 24000000 /* Half the clock freq. in the 4710 */
9906 +
9907 +#endif /* _SBEXTIF_H */
9908 diff -urN linux.old/arch/mips/bcm947xx/include/sbmemc.h linux.dev/arch/mips/bcm947xx/include/sbmemc.h
9909 --- linux.old/arch/mips/bcm947xx/include/sbmemc.h 1970-01-01 01:00:00.000000000 +0100
9910 +++ linux.dev/arch/mips/bcm947xx/include/sbmemc.h 2005-12-15 15:35:31.567254500 +0100
9911 @@ -0,0 +1,148 @@
9912 +/*
9913 + * BCM47XX Sonics SiliconBackplane DDR/SDRAM controller core hardware definitions.
9914 + *
9915 + * Copyright 2005, Broadcom Corporation
9916 + * All Rights Reserved.
9917 + *
9918 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
9919 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
9920 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
9921 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
9922 + *
9923 + * $Id$
9924 + */
9925 +
9926 +#ifndef _SBMEMC_H
9927 +#define _SBMEMC_H
9928 +
9929 +#ifdef _LANGUAGE_ASSEMBLY
9930 +
9931 +#define MEMC_CONTROL 0x00
9932 +#define MEMC_CONFIG 0x04
9933 +#define MEMC_REFRESH 0x08
9934 +#define MEMC_BISTSTAT 0x0c
9935 +#define MEMC_MODEBUF 0x10
9936 +#define MEMC_BKCLS 0x14
9937 +#define MEMC_PRIORINV 0x18
9938 +#define MEMC_DRAMTIM 0x1c
9939 +#define MEMC_INTSTAT 0x20
9940 +#define MEMC_INTMASK 0x24
9941 +#define MEMC_INTINFO 0x28
9942 +#define MEMC_NCDLCTL 0x30
9943 +#define MEMC_RDNCDLCOR 0x34
9944 +#define MEMC_WRNCDLCOR 0x38
9945 +#define MEMC_MISCDLYCTL 0x3c
9946 +#define MEMC_DQSGATENCDL 0x40
9947 +#define MEMC_SPARE 0x44
9948 +#define MEMC_TPADDR 0x48
9949 +#define MEMC_TPDATA 0x4c
9950 +#define MEMC_BARRIER 0x50
9951 +#define MEMC_CORE 0x54
9952 +
9953 +
9954 +#else
9955 +
9956 +/* Sonics side: MEMC core registers */
9957 +typedef volatile struct sbmemcregs {
9958 + uint32 control;
9959 + uint32 config;
9960 + uint32 refresh;
9961 + uint32 biststat;
9962 + uint32 modebuf;
9963 + uint32 bkcls;
9964 + uint32 priorinv;
9965 + uint32 dramtim;
9966 + uint32 intstat;
9967 + uint32 intmask;
9968 + uint32 intinfo;
9969 + uint32 reserved1;
9970 + uint32 ncdlctl;
9971 + uint32 rdncdlcor;
9972 + uint32 wrncdlcor;
9973 + uint32 miscdlyctl;
9974 + uint32 dqsgatencdl;
9975 + uint32 spare;
9976 + uint32 tpaddr;
9977 + uint32 tpdata;
9978 + uint32 barrier;
9979 + uint32 core;
9980 +} sbmemcregs_t;
9981 +
9982 +#endif
9983 +
9984 +/* MEMC Core Init values (OCP ID 0x80f) */
9985 +
9986 +/* For sdr: */
9987 +#define MEMC_SD_CONFIG_INIT 0x00048000
9988 +#define MEMC_SD_DRAMTIM2_INIT 0x000754d8
9989 +#define MEMC_SD_DRAMTIM3_INIT 0x000754da
9990 +#define MEMC_SD_RDNCDLCOR_INIT 0x00000000
9991 +#define MEMC_SD_WRNCDLCOR_INIT 0x49351200
9992 +#define MEMC_SD1_WRNCDLCOR_INIT 0x14500200 /* For corerev 1 (4712) */
9993 +#define MEMC_SD_MISCDLYCTL_INIT 0x00061c1b
9994 +#define MEMC_SD1_MISCDLYCTL_INIT 0x00021416 /* For corerev 1 (4712) */
9995 +#define MEMC_SD_CONTROL_INIT0 0x00000002
9996 +#define MEMC_SD_CONTROL_INIT1 0x00000008
9997 +#define MEMC_SD_CONTROL_INIT2 0x00000004
9998 +#define MEMC_SD_CONTROL_INIT3 0x00000010
9999 +#define MEMC_SD_CONTROL_INIT4 0x00000001
10000 +#define MEMC_SD_MODEBUF_INIT 0x00000000
10001 +#define MEMC_SD_REFRESH_INIT 0x0000840f
10002 +
10003 +
10004 +/* This is for SDRM8X8X4 */
10005 +#define MEMC_SDR_INIT 0x0008
10006 +#define MEMC_SDR_MODE 0x32
10007 +#define MEMC_SDR_NCDL 0x00020032
10008 +#define MEMC_SDR1_NCDL 0x0002020f /* For corerev 1 (4712) */
10009 +
10010 +/* For ddr: */
10011 +#define MEMC_CONFIG_INIT 0x00048000
10012 +#define MEMC_DRAMTIM2_INIT 0x000754d8
10013 +#define MEMC_DRAMTIM25_INIT 0x000754d9
10014 +#define MEMC_RDNCDLCOR_INIT 0x00000000
10015 +#define MEMC_RDNCDLCOR_SIMINIT 0xf6f6f6f6 /* For hdl sim */
10016 +#define MEMC_WRNCDLCOR_INIT 0x49351200
10017 +#define MEMC_1_WRNCDLCOR_INIT 0x14500200
10018 +#define MEMC_DQSGATENCDL_INIT 0x00030000
10019 +#define MEMC_MISCDLYCTL_INIT 0x21061c1b
10020 +#define MEMC_1_MISCDLYCTL_INIT 0x21021400
10021 +#define MEMC_NCDLCTL_INIT 0x00002001
10022 +#define MEMC_CONTROL_INIT0 0x00000002
10023 +#define MEMC_CONTROL_INIT1 0x00000008
10024 +#define MEMC_MODEBUF_INIT0 0x00004000
10025 +#define MEMC_CONTROL_INIT2 0x00000010
10026 +#define MEMC_MODEBUF_INIT1 0x00000100
10027 +#define MEMC_CONTROL_INIT3 0x00000010
10028 +#define MEMC_CONTROL_INIT4 0x00000008
10029 +#define MEMC_REFRESH_INIT 0x0000840f
10030 +#define MEMC_CONTROL_INIT5 0x00000004
10031 +#define MEMC_MODEBUF_INIT2 0x00000000
10032 +#define MEMC_CONTROL_INIT6 0x00000010
10033 +#define MEMC_CONTROL_INIT7 0x00000001
10034 +
10035 +
10036 +/* This is for DDRM16X16X2 */
10037 +#define MEMC_DDR_INIT 0x0009
10038 +#define MEMC_DDR_MODE 0x62
10039 +#define MEMC_DDR_NCDL 0x0005050a
10040 +#define MEMC_DDR1_NCDL 0x00000a0a /* For corerev 1 (4712) */
10041 +
10042 +/* mask for sdr/ddr calibration registers */
10043 +#define MEMC_RDNCDLCOR_RD_MASK 0x000000ff
10044 +#define MEMC_WRNCDLCOR_WR_MASK 0x000000ff
10045 +#define MEMC_DQSGATENCDL_G_MASK 0x000000ff
10046 +
10047 +/* masks for miscdlyctl registers */
10048 +#define MEMC_MISC_SM_MASK 0x30000000
10049 +#define MEMC_MISC_SM_SHIFT 28
10050 +#define MEMC_MISC_SD_MASK 0x0f000000
10051 +#define MEMC_MISC_SD_SHIFT 24
10052 +
10053 +/* hw threshhold for calculating wr/rd for sdr memc */
10054 +#define MEMC_CD_THRESHOLD 128
10055 +
10056 +/* Low bit of init register says if memc is ddr or sdr */
10057 +#define MEMC_CONFIG_DDR 0x00000001
10058 +
10059 +#endif /* _SBMEMC_H */
10060 diff -urN linux.old/arch/mips/bcm947xx/include/sbmips.h linux.dev/arch/mips/bcm947xx/include/sbmips.h
10061 --- linux.old/arch/mips/bcm947xx/include/sbmips.h 1970-01-01 01:00:00.000000000 +0100
10062 +++ linux.dev/arch/mips/bcm947xx/include/sbmips.h 2005-12-15 16:46:57.616617000 +0100
10063 @@ -0,0 +1,62 @@
10064 +/*
10065 + * Broadcom SiliconBackplane MIPS definitions
10066 + *
10067 + * SB MIPS cores are custom MIPS32 processors with SiliconBackplane
10068 + * OCP interfaces. The CP0 processor ID is 0x00024000, where bits
10069 + * 23:16 mean Broadcom and bits 15:8 mean a MIPS core with an OCP
10070 + * interface. The core revision is stored in the SB ID register in SB
10071 + * configuration space.
10072 + *
10073 + * Copyright 2005, Broadcom Corporation
10074 + * All Rights Reserved.
10075 + *
10076 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10077 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10078 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10079 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10080 + *
10081 + * $Id$
10082 + */
10083 +
10084 +#ifndef _SBMIPS_H
10085 +#define _SBMIPS_H
10086 +
10087 +#include <mipsinc.h>
10088 +
10089 +#ifndef _LANGUAGE_ASSEMBLY
10090 +
10091 +/* cpp contortions to concatenate w/arg prescan */
10092 +#ifndef PAD
10093 +#define _PADLINE(line) pad ## line
10094 +#define _XSTR(line) _PADLINE(line)
10095 +#define PAD _XSTR(__LINE__)
10096 +#endif /* PAD */
10097 +
10098 +typedef volatile struct {
10099 + uint32 corecontrol;
10100 + uint32 PAD[2];
10101 + uint32 biststatus;
10102 + uint32 PAD[4];
10103 + uint32 intstatus;
10104 + uint32 intmask;
10105 + uint32 timer;
10106 +} mipsregs_t;
10107 +
10108 +extern uint32 sb_flag(sb_t *sbh);
10109 +extern uint sb_irq(sb_t *sbh);
10110 +
10111 +extern void BCMINIT(sb_serial_init)(sb_t *sbh, void (*add)(void *regs, uint irq, uint baud_base, uint reg_shift));
10112 +
10113 +extern void *sb_jtagm_init(sb_t *sbh, uint clkd, bool exttap);
10114 +extern void sb_jtagm_disable(void *h);
10115 +extern uint32 jtag_rwreg(void *h, uint32 ir, uint32 dr);
10116 +extern void BCMINIT(sb_mips_init)(sb_t *sbh);
10117 +extern uint32 BCMINIT(sb_mips_clock)(sb_t *sbh);
10118 +extern bool BCMINIT(sb_mips_setclock)(sb_t *sbh, uint32 mipsclock, uint32 sbclock, uint32 pciclock);
10119 +extern void BCMINIT(enable_pfc)(uint32 mode);
10120 +extern uint32 BCMINIT(sb_memc_get_ncdl)(sb_t *sbh);
10121 +
10122 +
10123 +#endif /* _LANGUAGE_ASSEMBLY */
10124 +
10125 +#endif /* _SBMIPS_H */
10126 diff -urN linux.old/arch/mips/bcm947xx/include/sbpci.h linux.dev/arch/mips/bcm947xx/include/sbpci.h
10127 --- linux.old/arch/mips/bcm947xx/include/sbpci.h 1970-01-01 01:00:00.000000000 +0100
10128 +++ linux.dev/arch/mips/bcm947xx/include/sbpci.h 2005-12-15 15:35:36.795581250 +0100
10129 @@ -0,0 +1,122 @@
10130 +/*
10131 + * BCM47XX Sonics SiliconBackplane PCI core hardware definitions.
10132 + *
10133 + * $Id$
10134 + * Copyright 2005, Broadcom Corporation
10135 + * All Rights Reserved.
10136 + *
10137 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10138 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10139 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10140 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10141 + */
10142 +
10143 +#ifndef _SBPCI_H
10144 +#define _SBPCI_H
10145 +
10146 +/* cpp contortions to concatenate w/arg prescan */
10147 +#ifndef PAD
10148 +#define _PADLINE(line) pad ## line
10149 +#define _XSTR(line) _PADLINE(line)
10150 +#define PAD _XSTR(__LINE__)
10151 +#endif
10152 +
10153 +/* Sonics side: PCI core and host control registers */
10154 +typedef struct sbpciregs {
10155 + uint32 control; /* PCI control */
10156 + uint32 PAD[3];
10157 + uint32 arbcontrol; /* PCI arbiter control */
10158 + uint32 PAD[3];
10159 + uint32 intstatus; /* Interrupt status */
10160 + uint32 intmask; /* Interrupt mask */
10161 + uint32 sbtopcimailbox; /* Sonics to PCI mailbox */
10162 + uint32 PAD[9];
10163 + uint32 bcastaddr; /* Sonics broadcast address */
10164 + uint32 bcastdata; /* Sonics broadcast data */
10165 + uint32 PAD[2];
10166 + uint32 gpioin; /* ro: gpio input (>=rev2) */
10167 + uint32 gpioout; /* rw: gpio output (>=rev2) */
10168 + uint32 gpioouten; /* rw: gpio output enable (>= rev2) */
10169 + uint32 gpiocontrol; /* rw: gpio control (>= rev2) */
10170 + uint32 PAD[36];
10171 + uint32 sbtopci0; /* Sonics to PCI translation 0 */
10172 + uint32 sbtopci1; /* Sonics to PCI translation 1 */
10173 + uint32 sbtopci2; /* Sonics to PCI translation 2 */
10174 + uint32 PAD[445];
10175 + uint16 sprom[36]; /* SPROM shadow Area */
10176 + uint32 PAD[46];
10177 +} sbpciregs_t;
10178 +
10179 +/* PCI control */
10180 +#define PCI_RST_OE 0x01 /* When set, drives PCI_RESET out to pin */
10181 +#define PCI_RST 0x02 /* Value driven out to pin */
10182 +#define PCI_CLK_OE 0x04 /* When set, drives clock as gated by PCI_CLK out to pin */
10183 +#define PCI_CLK 0x08 /* Gate for clock driven out to pin */
10184 +
10185 +/* PCI arbiter control */
10186 +#define PCI_INT_ARB 0x01 /* When set, use an internal arbiter */
10187 +#define PCI_EXT_ARB 0x02 /* When set, use an external arbiter */
10188 +#define PCI_PARKID_MASK 0x06 /* Selects which agent is parked on an idle bus */
10189 +#define PCI_PARKID_SHIFT 1
10190 +#define PCI_PARKID_LAST 0 /* Last requestor */
10191 +#define PCI_PARKID_4710 1 /* 4710 */
10192 +#define PCI_PARKID_EXTREQ0 2 /* External requestor 0 */
10193 +#define PCI_PARKID_EXTREQ1 3 /* External requestor 1 */
10194 +
10195 +/* Interrupt status/mask */
10196 +#define PCI_INTA 0x01 /* PCI INTA# is asserted */
10197 +#define PCI_INTB 0x02 /* PCI INTB# is asserted */
10198 +#define PCI_SERR 0x04 /* PCI SERR# has been asserted (write one to clear) */
10199 +#define PCI_PERR 0x08 /* PCI PERR# has been asserted (write one to clear) */
10200 +#define PCI_PME 0x10 /* PCI PME# is asserted */
10201 +
10202 +/* (General) PCI/SB mailbox interrupts, two bits per pci function */
10203 +#define MAILBOX_F0_0 0x100 /* function 0, int 0 */
10204 +#define MAILBOX_F0_1 0x200 /* function 0, int 1 */
10205 +#define MAILBOX_F1_0 0x400 /* function 1, int 0 */
10206 +#define MAILBOX_F1_1 0x800 /* function 1, int 1 */
10207 +#define MAILBOX_F2_0 0x1000 /* function 2, int 0 */
10208 +#define MAILBOX_F2_1 0x2000 /* function 2, int 1 */
10209 +#define MAILBOX_F3_0 0x4000 /* function 3, int 0 */
10210 +#define MAILBOX_F3_1 0x8000 /* function 3, int 1 */
10211 +
10212 +/* Sonics broadcast address */
10213 +#define BCAST_ADDR_MASK 0xff /* Broadcast register address */
10214 +
10215 +/* Sonics to PCI translation types */
10216 +#define SBTOPCI0_MASK 0xfc000000
10217 +#define SBTOPCI1_MASK 0xfc000000
10218 +#define SBTOPCI2_MASK 0xc0000000
10219 +#define SBTOPCI_MEM 0
10220 +#define SBTOPCI_IO 1
10221 +#define SBTOPCI_CFG0 2
10222 +#define SBTOPCI_CFG1 3
10223 +#define SBTOPCI_PREF 0x4 /* prefetch enable */
10224 +#define SBTOPCI_BURST 0x8 /* burst enable */
10225 +#define SBTOPCI_RC_MASK 0x30 /* read command (>= rev11) */
10226 +#define SBTOPCI_RC_READ 0x00 /* memory read */
10227 +#define SBTOPCI_RC_READLINE 0x10 /* memory read line */
10228 +#define SBTOPCI_RC_READMULTI 0x20 /* memory read multiple */
10229 +
10230 +/* PCI core index in SROM shadow area */
10231 +#define SRSH_PI_OFFSET 0 /* first word */
10232 +#define SRSH_PI_MASK 0xf000 /* bit 15:12 */
10233 +#define SRSH_PI_SHIFT 12 /* bit 15:12 */
10234 +
10235 +/* PCI side: Reserved PCI configuration registers (see pcicfg.h) */
10236 +#define cap_list rsvd_a[0]
10237 +#define bar0_window dev_dep[0x80 - 0x40]
10238 +#define bar1_window dev_dep[0x84 - 0x40]
10239 +#define sprom_control dev_dep[0x88 - 0x40]
10240 +
10241 +#ifndef _LANGUAGE_ASSEMBLY
10242 +
10243 +extern int sbpci_read_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len);
10244 +extern int sbpci_write_config(sb_t *sbh, uint bus, uint dev, uint func, uint off, void *buf, int len);
10245 +extern void sbpci_ban(uint16 core);
10246 +extern int sbpci_init(sb_t *sbh);
10247 +extern void sbpci_check(sb_t *sbh);
10248 +
10249 +#endif /* !_LANGUAGE_ASSEMBLY */
10250 +
10251 +#endif /* _SBPCI_H */
10252 diff -urN linux.old/arch/mips/bcm947xx/include/sbsdram.h linux.dev/arch/mips/bcm947xx/include/sbsdram.h
10253 --- linux.old/arch/mips/bcm947xx/include/sbsdram.h 1970-01-01 01:00:00.000000000 +0100
10254 +++ linux.dev/arch/mips/bcm947xx/include/sbsdram.h 2005-12-15 15:35:40.175792500 +0100
10255 @@ -0,0 +1,75 @@
10256 +/*
10257 + * BCM47XX Sonics SiliconBackplane SDRAM controller core hardware definitions.
10258 + *
10259 + * Copyright 2005, Broadcom Corporation
10260 + * All Rights Reserved.
10261 + *
10262 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10263 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10264 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10265 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10266 + * $Id$
10267 + */
10268 +
10269 +#ifndef _SBSDRAM_H
10270 +#define _SBSDRAM_H
10271 +
10272 +#ifndef _LANGUAGE_ASSEMBLY
10273 +
10274 +/* Sonics side: SDRAM core registers */
10275 +typedef volatile struct sbsdramregs {
10276 + uint32 initcontrol; /* Generates external SDRAM initialization sequence */
10277 + uint32 config; /* Initializes external SDRAM mode register */
10278 + uint32 refresh; /* Controls external SDRAM refresh rate */
10279 + uint32 pad1;
10280 + uint32 pad2;
10281 +} sbsdramregs_t;
10282 +
10283 +#endif
10284 +
10285 +/* SDRAM initialization control (initcontrol) register bits */
10286 +#define SDRAM_CBR 0x0001 /* Writing 1 generates refresh cycle and toggles bit */
10287 +#define SDRAM_PRE 0x0002 /* Writing 1 generates precharge cycle and toggles bit */
10288 +#define SDRAM_MRS 0x0004 /* Writing 1 generates mode register select cycle and toggles bit */
10289 +#define SDRAM_EN 0x0008 /* When set, enables access to SDRAM */
10290 +#define SDRAM_16Mb 0x0000 /* Use 16 Megabit SDRAM */
10291 +#define SDRAM_64Mb 0x0010 /* Use 64 Megabit SDRAM */
10292 +#define SDRAM_128Mb 0x0020 /* Use 128 Megabit SDRAM */
10293 +#define SDRAM_RSVMb 0x0030 /* Use special SDRAM */
10294 +#define SDRAM_RST 0x0080 /* Writing 1 causes soft reset of controller */
10295 +#define SDRAM_SELFREF 0x0100 /* Writing 1 enables self refresh mode */
10296 +#define SDRAM_PWRDOWN 0x0200 /* Writing 1 causes controller to power down */
10297 +#define SDRAM_32BIT 0x0400 /* When set, indicates 32 bit SDRAM interface */
10298 +#define SDRAM_9BITCOL 0x0800 /* When set, indicates 9 bit column */
10299 +
10300 +/* SDRAM configuration (config) register bits */
10301 +#define SDRAM_BURSTFULL 0x0000 /* Use full page bursts */
10302 +#define SDRAM_BURST8 0x0001 /* Use burst of 8 */
10303 +#define SDRAM_BURST4 0x0002 /* Use burst of 4 */
10304 +#define SDRAM_BURST2 0x0003 /* Use burst of 2 */
10305 +#define SDRAM_CAS3 0x0000 /* Use CAS latency of 3 */
10306 +#define SDRAM_CAS2 0x0004 /* Use CAS latency of 2 */
10307 +
10308 +/* SDRAM refresh control (refresh) register bits */
10309 +#define SDRAM_REF(p) (((p)&0xff) | SDRAM_REF_EN) /* Refresh period */
10310 +#define SDRAM_REF_EN 0x8000 /* Writing 1 enables periodic refresh */
10311 +
10312 +/* SDRAM Core default Init values (OCP ID 0x803) */
10313 +#define SDRAM_INIT MEM4MX16X2
10314 +#define SDRAM_CONFIG SDRAM_BURSTFULL
10315 +#define SDRAM_REFRESH SDRAM_REF(0x40)
10316 +
10317 +#define MEM1MX16 0x009 /* 2 MB */
10318 +#define MEM1MX16X2 0x409 /* 4 MB */
10319 +#define MEM2MX8X2 0x809 /* 4 MB */
10320 +#define MEM2MX8X4 0xc09 /* 8 MB */
10321 +#define MEM2MX32 0x439 /* 8 MB */
10322 +#define MEM4MX16 0x019 /* 8 MB */
10323 +#define MEM4MX16X2 0x419 /* 16 MB */
10324 +#define MEM8MX8X2 0x819 /* 16 MB */
10325 +#define MEM8MX16 0x829 /* 16 MB */
10326 +#define MEM4MX32 0x429 /* 16 MB */
10327 +#define MEM8MX8X4 0xc19 /* 32 MB */
10328 +#define MEM8MX16X2 0xc29 /* 32 MB */
10329 +
10330 +#endif /* _SBSDRAM_H */
10331 diff -urN linux.old/arch/mips/bcm947xx/include/sbutils.h linux.dev/arch/mips/bcm947xx/include/sbutils.h
10332 --- linux.old/arch/mips/bcm947xx/include/sbutils.h 1970-01-01 01:00:00.000000000 +0100
10333 +++ linux.dev/arch/mips/bcm947xx/include/sbutils.h 2005-12-15 16:00:47.404550500 +0100
10334 @@ -0,0 +1,136 @@
10335 +/*
10336 + * Misc utility routines for accessing chip-specific features
10337 + * of Broadcom HNBU SiliconBackplane-based chips.
10338 + *
10339 + * Copyright 2005, Broadcom Corporation
10340 + * All Rights Reserved.
10341 + *
10342 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10343 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10344 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10345 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10346 + *
10347 + * $Id$
10348 + */
10349 +
10350 +#ifndef _sbutils_h_
10351 +#define _sbutils_h_
10352 +
10353 +/*
10354 + * Datastructure to export all chip specific common variables
10355 + * public (read-only) portion of sbutils handle returned by
10356 + * sb_attach()/sb_kattach()
10357 +*/
10358 +
10359 +struct sb_pub {
10360 +
10361 + uint bustype; /* SB_BUS, PCI_BUS */
10362 + uint buscoretype; /* SB_PCI, SB_PCMCIA, SB_PCIE*/
10363 + uint buscorerev; /* buscore rev */
10364 + uint buscoreidx; /* buscore index */
10365 + int ccrev; /* chip common core rev */
10366 + uint boardtype; /* board type */
10367 + uint boardvendor; /* board vendor */
10368 + uint chip; /* chip number */
10369 + uint chiprev; /* chip revision */
10370 + uint chippkg; /* chip package option */
10371 + uint sonicsrev; /* sonics backplane rev */
10372 +};
10373 +
10374 +typedef const struct sb_pub sb_t;
10375 +
10376 +/*
10377 + * Many of the routines below take an 'sbh' handle as their first arg.
10378 + * Allocate this by calling sb_attach(). Free it by calling sb_detach().
10379 + * At any one time, the sbh is logically focused on one particular sb core
10380 + * (the "current core").
10381 + * Use sb_setcore() or sb_setcoreidx() to change the association to another core.
10382 + */
10383 +
10384 +/* exported externs */
10385 +extern sb_t * BCMINIT(sb_attach)(uint pcidev, osl_t *osh, void *regs, uint bustype, void *sdh, char **vars, int *varsz);
10386 +extern sb_t * BCMINIT(sb_kattach)(void);
10387 +extern void sb_detach(sb_t *sbh);
10388 +extern uint BCMINIT(sb_chip)(sb_t *sbh);
10389 +extern uint BCMINIT(sb_chiprev)(sb_t *sbh);
10390 +extern uint BCMINIT(sb_chipcrev)(sb_t *sbh);
10391 +extern uint BCMINIT(sb_chippkg)(sb_t *sbh);
10392 +extern uint BCMINIT(sb_pcirev)(sb_t *sbh);
10393 +extern bool BCMINIT(sb_war16165)(sb_t *sbh);
10394 +extern uint BCMINIT(sb_boardvendor)(sb_t *sbh);
10395 +extern uint BCMINIT(sb_boardtype)(sb_t *sbh);
10396 +extern uint sb_bus(sb_t *sbh);
10397 +extern uint sb_buscoretype(sb_t *sbh);
10398 +extern uint sb_buscorerev(sb_t *sbh);
10399 +extern uint sb_corelist(sb_t *sbh, uint coreid[]);
10400 +extern uint sb_coreid(sb_t *sbh);
10401 +extern uint sb_coreidx(sb_t *sbh);
10402 +extern uint sb_coreunit(sb_t *sbh);
10403 +extern uint sb_corevendor(sb_t *sbh);
10404 +extern uint sb_corerev(sb_t *sbh);
10405 +extern void *sb_osh(sb_t *sbh);
10406 +extern void *sb_coreregs(sb_t *sbh);
10407 +extern uint32 sb_coreflags(sb_t *sbh, uint32 mask, uint32 val);
10408 +extern uint32 sb_coreflagshi(sb_t *sbh, uint32 mask, uint32 val);
10409 +extern bool sb_iscoreup(sb_t *sbh);
10410 +extern void *sb_setcoreidx(sb_t *sbh, uint coreidx);
10411 +extern void *sb_setcore(sb_t *sbh, uint coreid, uint coreunit);
10412 +extern int sb_corebist(sb_t *sbh, uint coreid, uint coreunit);
10413 +extern void sb_commit(sb_t *sbh);
10414 +extern uint32 sb_base(uint32 admatch);
10415 +extern uint32 sb_size(uint32 admatch);
10416 +extern void sb_core_reset(sb_t *sbh, uint32 bits);
10417 +extern void sb_core_tofixup(sb_t *sbh);
10418 +extern void sb_core_disable(sb_t *sbh, uint32 bits);
10419 +extern uint32 sb_clock_rate(uint32 pll_type, uint32 n, uint32 m);
10420 +extern uint32 sb_clock(sb_t *sbh);
10421 +extern void sb_pci_setup(sb_t *sbh, uint coremask);
10422 +extern void sb_watchdog(sb_t *sbh, uint ticks);
10423 +extern void *sb_gpiosetcore(sb_t *sbh);
10424 +extern uint32 sb_gpiocontrol(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
10425 +extern uint32 sb_gpioouten(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
10426 +extern uint32 sb_gpioout(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
10427 +extern uint32 sb_gpioin(sb_t *sbh);
10428 +extern uint32 sb_gpiointpolarity(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
10429 +extern uint32 sb_gpiointmask(sb_t *sbh, uint32 mask, uint32 val, uint8 priority);
10430 +extern uint32 sb_gpioled(sb_t *sbh, uint32 mask, uint32 val);
10431 +extern uint32 sb_gpioreserve(sb_t *sbh, uint32 gpio_num, uint8 priority);
10432 +extern uint32 sb_gpiorelease(sb_t *sbh, uint32 gpio_num, uint8 priority);
10433 +
10434 +extern void sb_clkctl_init(sb_t *sbh);
10435 +extern uint16 sb_clkctl_fast_pwrup_delay(sb_t *sbh);
10436 +extern bool sb_clkctl_clk(sb_t *sbh, uint mode);
10437 +extern int sb_clkctl_xtal(sb_t *sbh, uint what, bool on);
10438 +extern void sb_register_intr_callback(sb_t *sbh, void *intrsoff_fn,
10439 + void *intrsrestore_fn, void *intrsenabled_fn, void *intr_arg);
10440 +extern uint32 sb_set_initiator_to(sb_t *sbh, uint32 to);
10441 +extern void sb_corepciid(sb_t *sbh, uint16 *pcivendor, uint16 *pcidevice,
10442 + uint8 *pciclass, uint8 *pcisubclass, uint8 *pciprogif);
10443 +extern uint32 sb_gpiotimerval(sb_t *sbh, uint32 mask, uint32 val);
10444 +
10445 +
10446 +
10447 +/*
10448 +* Build device path. Path size must be >= SB_DEVPATH_BUFSZ.
10449 +* The returned path is NULL terminated and has trailing '/'.
10450 +* Return 0 on success, nonzero otherwise.
10451 +*/
10452 +extern int sb_devpath(sb_t *sbh, char *path, int size);
10453 +
10454 +/* clkctl xtal what flags */
10455 +#define XTAL 0x1 /* primary crystal oscillator (2050) */
10456 +#define PLL 0x2 /* main chip pll */
10457 +
10458 +/* clkctl clk mode */
10459 +#define CLK_FAST 0 /* force fast (pll) clock */
10460 +#define CLK_DYNAMIC 2 /* enable dynamic clock control */
10461 +
10462 +
10463 +/* GPIO usage priorities */
10464 +#define GPIO_DRV_PRIORITY 0
10465 +#define GPIO_APP_PRIORITY 1
10466 +
10467 +/* device path */
10468 +#define SB_DEVPATH_BUFSZ 16 /* min buffer size in bytes */
10469 +
10470 +#endif /* _sbutils_h_ */
10471 diff -urN linux.old/arch/mips/bcm947xx/include/sflash.h linux.dev/arch/mips/bcm947xx/include/sflash.h
10472 --- linux.old/arch/mips/bcm947xx/include/sflash.h 1970-01-01 01:00:00.000000000 +0100
10473 +++ linux.dev/arch/mips/bcm947xx/include/sflash.h 2005-12-15 16:49:23.001703000 +0100
10474 @@ -0,0 +1,36 @@
10475 +/*
10476 + * Broadcom SiliconBackplane chipcommon serial flash interface
10477 + *
10478 + * Copyright 2005, Broadcom Corporation
10479 + * All Rights Reserved.
10480 + *
10481 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10482 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10483 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10484 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10485 + *
10486 + * $Id$
10487 + */
10488 +
10489 +#ifndef _sflash_h_
10490 +#define _sflash_h_
10491 +
10492 +#include <typedefs.h>
10493 +#include <sbchipc.h>
10494 +
10495 +struct sflash {
10496 + uint blocksize; /* Block size */
10497 + uint numblocks; /* Number of blocks */
10498 + uint32 type; /* Type */
10499 + uint size; /* Total size in bytes */
10500 +};
10501 +
10502 +/* Utility functions */
10503 +extern int sflash_poll(chipcregs_t *cc, uint offset);
10504 +extern int sflash_read(chipcregs_t *cc, uint offset, uint len, uchar *buf);
10505 +extern int sflash_write(chipcregs_t *cc, uint offset, uint len, const uchar *buf);
10506 +extern int sflash_erase(chipcregs_t *cc, uint offset);
10507 +extern int sflash_commit(chipcregs_t *cc, uint offset, uint len, const uchar *buf);
10508 +extern struct sflash * sflash_init(chipcregs_t *cc);
10509 +
10510 +#endif /* _sflash_h_ */
10511 diff -urN linux.old/arch/mips/bcm947xx/include/trxhdr.h linux.dev/arch/mips/bcm947xx/include/trxhdr.h
10512 --- linux.old/arch/mips/bcm947xx/include/trxhdr.h 1970-01-01 01:00:00.000000000 +0100
10513 +++ linux.dev/arch/mips/bcm947xx/include/trxhdr.h 2005-12-15 15:35:49.220357750 +0100
10514 @@ -0,0 +1,33 @@
10515 +/*
10516 + * TRX image file header format.
10517 + *
10518 + * Copyright 2005, Broadcom Corporation
10519 + * All Rights Reserved.
10520 + *
10521 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10522 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10523 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10524 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10525 + *
10526 + * $Id$
10527 + */
10528 +
10529 +#include <typedefs.h>
10530 +
10531 +#define TRX_MAGIC 0x30524448 /* "HDR0" */
10532 +#define TRX_VERSION 1
10533 +#define TRX_MAX_LEN 0x3A0000
10534 +#define TRX_NO_HEADER 1 /* Do not write TRX header */
10535 +#define TRX_GZ_FILES 0x2 /* Contains up to TRX_MAX_OFFSET individual gzip files */
10536 +#define TRX_MAX_OFFSET 3
10537 +
10538 +struct trx_header {
10539 + uint32 magic; /* "HDR0" */
10540 + uint32 len; /* Length of file including header */
10541 + uint32 crc32; /* 32-bit CRC from flag_version to end of file */
10542 + uint32 flag_version; /* 0:15 flags, 16:31 version */
10543 + uint32 offsets[TRX_MAX_OFFSET]; /* Offsets of partitions from start of header */
10544 +};
10545 +
10546 +/* Compatibility */
10547 +typedef struct trx_header TRXHDR, *PTRXHDR;
10548 diff -urN linux.old/arch/mips/bcm947xx/include/typedefs.h linux.dev/arch/mips/bcm947xx/include/typedefs.h
10549 --- linux.old/arch/mips/bcm947xx/include/typedefs.h 1970-01-01 01:00:00.000000000 +0100
10550 +++ linux.dev/arch/mips/bcm947xx/include/typedefs.h 2005-12-15 15:35:52.436558750 +0100
10551 @@ -0,0 +1,326 @@
10552 +/*
10553 + * Copyright 2005, Broadcom Corporation
10554 + * All Rights Reserved.
10555 + *
10556 + * THIS SOFTWARE IS OFFERED "AS IS", AND BROADCOM GRANTS NO WARRANTIES OF ANY
10557 + * KIND, EXPRESS OR IMPLIED, BY STATUTE, COMMUNICATION OR OTHERWISE. BROADCOM
10558 + * SPECIFICALLY DISCLAIMS ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS
10559 + * FOR A SPECIFIC PURPOSE OR NONINFRINGEMENT CONCERNING THIS SOFTWARE.
10560 + * $Id$
10561 + */
10562 +
10563 +#ifndef _TYPEDEFS_H_
10564 +#define _TYPEDEFS_H_
10565 +
10566 +
10567 +/* Define 'SITE_TYPEDEFS' in the compile to include a site specific
10568 + * typedef file "site_typedefs.h".
10569 + *
10570 + * If 'SITE_TYPEDEFS' is not defined, then the "Inferred Typedefs"
10571 + * section of this file makes inferences about the compile environment
10572 + * based on defined symbols and possibly compiler pragmas.
10573 + *
10574 + * Following these two sections is the "Default Typedefs"
10575 + * section. This section is only prcessed if 'USE_TYPEDEF_DEFAULTS' is
10576 + * defined. This section has a default set of typedefs and a few
10577 + * proprocessor symbols (TRUE, FALSE, NULL, ...).
10578 + */
10579 +
10580 +#ifdef SITE_TYPEDEFS
10581 +
10582 +/*******************************************************************************
10583 + * Site Specific Typedefs
10584 + *******************************************************************************/
10585 +
10586 +#include "site_typedefs.h"
10587 +
10588 +#else
10589 +
10590 +/*******************************************************************************
10591 + * Inferred Typedefs
10592 + *******************************************************************************/
10593 +
10594 +/* Infer the compile environment based on preprocessor symbols and pramas.
10595 + * Override type definitions as needed, and include configuration dependent
10596 + * header files to define types.
10597 + */
10598 +
10599 +#ifdef __cplusplus
10600 +
10601 +#define TYPEDEF_BOOL
10602 +#ifndef FALSE
10603 +#define FALSE false
10604 +#endif
10605 +#ifndef TRUE
10606 +#define TRUE true
10607 +#endif
10608 +
10609 +#else /* ! __cplusplus */
10610 +
10611 +#if defined(_WIN32)
10612 +
10613 +#define TYPEDEF_BOOL
10614 +typedef unsigned char bool; /* consistent w/BOOL */
10615 +
10616 +#endif /* _WIN32 */
10617 +
10618 +#endif /* ! __cplusplus */
10619 +
10620 +/* use the Windows ULONG_PTR type when compiling for 64 bit */
10621 +#if defined(_WIN64)
10622 +#include <basetsd.h>
10623 +#define TYPEDEF_UINTPTR
10624 +typedef ULONG_PTR uintptr;
10625 +#endif
10626 +
10627 +#ifdef _HNDRTE_
10628 +typedef long unsigned int size_t;
10629 +#endif
10630 +
10631 +#ifdef _MSC_VER /* Microsoft C */
10632 +#define TYPEDEF_INT64
10633 +#define TYPEDEF_UINT64
10634 +typedef signed __int64 int64;
10635 +typedef unsigned __int64 uint64;
10636 +#endif
10637 +
10638 +#if defined(MACOSX) && defined(KERNEL)
10639 +#define TYPEDEF_BOOL
10640 +#endif
10641 +
10642 +
10643 +#if defined(linux)
10644 +#define TYPEDEF_UINT
10645 +#define TYPEDEF_USHORT
10646 +#define TYPEDEF_ULONG
10647 +#endif
10648 +
10649 +#if !defined(linux) && !defined(_WIN32) && !defined(PMON) && !defined(_CFE_) && !defined(_HNDRTE_) && !defined(_MINOSL_)
10650 +#define TYPEDEF_UINT
10651 +#define TYPEDEF_USHORT
10652 +#endif
10653 +
10654 +
10655 +/* Do not support the (u)int64 types with strict ansi for GNU C */
10656 +#if defined(__GNUC__) && defined(__STRICT_ANSI__)
10657 +#define TYPEDEF_INT64
10658 +#define TYPEDEF_UINT64
10659 +#endif
10660 +
10661 +/* ICL accepts unsigned 64 bit type only, and complains in ANSI mode
10662 + * for singned or unsigned */
10663 +#if defined(__ICL)
10664 +
10665 +#define TYPEDEF_INT64
10666 +
10667 +#if defined(__STDC__)
10668 +#define TYPEDEF_UINT64
10669 +#endif
10670 +
10671 +#endif /* __ICL */
10672 +
10673 +
10674 +#if !defined(_WIN32) && !defined(PMON) && !defined(_CFE_) && !defined(_HNDRTE_) && !defined(_MINOSL_)
10675 +
10676 +/* pick up ushort & uint from standard types.h */
10677 +#if defined(linux) && defined(__KERNEL__)
10678 +
10679 +#include <linux/types.h> /* sys/types.h and linux/types.h are oil and water */
10680 +
10681 +#else
10682 +
10683 +#include <sys/types.h>
10684 +
10685 +#endif
10686 +
10687 +#endif /* !_WIN32 && !PMON && !_CFE_ && !_HNDRTE_ && !_MINOSL_ */
10688 +
10689 +#if defined(MACOSX) && defined(KERNEL)
10690 +#include <IOKit/IOTypes.h>
10691 +#endif
10692 +
10693 +
10694 +/* use the default typedefs in the next section of this file */
10695 +#define USE_TYPEDEF_DEFAULTS
10696 +
10697 +#endif /* SITE_TYPEDEFS */
10698 +
10699 +
10700 +/*******************************************************************************
10701 + * Default Typedefs
10702 + *******************************************************************************/
10703 +
10704 +#ifdef USE_TYPEDEF_DEFAULTS
10705 +#undef USE_TYPEDEF_DEFAULTS
10706 +
10707 +#ifndef TYPEDEF_BOOL
10708 +typedef /*@abstract@*/ unsigned char bool;
10709 +#endif
10710 +
10711 +/*----------------------- define uchar, ushort, uint, ulong ------------------*/
10712 +
10713 +#ifndef TYPEDEF_UCHAR
10714 +typedef unsigned char uchar;
10715 +#endif
10716 +
10717 +#ifndef TYPEDEF_USHORT
10718 +typedef unsigned short ushort;
10719 +#endif
10720 +
10721 +#ifndef TYPEDEF_UINT
10722 +typedef unsigned int uint;
10723 +#endif
10724 +
10725 +#ifndef TYPEDEF_ULONG
10726 +typedef unsigned long ulong;
10727 +#endif
10728 +
10729 +/*----------------------- define [u]int8/16/32/64, uintptr --------------------*/
10730 +
10731 +#ifndef TYPEDEF_UINT8
10732 +typedef unsigned char uint8;
10733 +#endif
10734 +
10735 +#ifndef TYPEDEF_UINT16
10736 +typedef unsigned short uint16;
10737 +#endif
10738 +
10739 +#ifndef TYPEDEF_UINT32
10740 +typedef unsigned int uint32;
10741 +#endif
10742 +
10743 +#ifndef TYPEDEF_UINT64
10744 +typedef unsigned long long uint64;
10745 +#endif
10746 +
10747 +#ifndef TYPEDEF_UINTPTR
10748 +typedef unsigned int uintptr;
10749 +#endif
10750 +
10751 +#ifndef TYPEDEF_INT8
10752 +typedef signed char int8;
10753 +#endif
10754 +
10755 +#ifndef TYPEDEF_INT16
10756 +typedef signed short int16;
10757 +#endif
10758 +
10759 +#ifndef TYPEDEF_INT32
10760 +typedef signed int int32;
10761 +#endif
10762 +
10763 +#ifndef TYPEDEF_INT64
10764 +typedef signed long long int64;
10765 +#endif
10766 +
10767 +/*----------------------- define float32/64, float_t -----------------------*/
10768 +
10769 +#ifndef TYPEDEF_FLOAT32
10770 +typedef float float32;
10771 +#endif
10772 +
10773 +#ifndef TYPEDEF_FLOAT64
10774 +typedef double float64;
10775 +#endif
10776 +
10777 +/*
10778 + * abstracted floating point type allows for compile time selection of
10779 + * single or double precision arithmetic. Compiling with -DFLOAT32
10780 + * selects single precision; the default is double precision.
10781 + */
10782 +
10783 +#ifndef TYPEDEF_FLOAT_T
10784 +
10785 +#if defined(FLOAT32)
10786 +typedef float32 float_t;
10787 +#else /* default to double precision floating point */
10788 +typedef float64 float_t;
10789 +#endif
10790 +
10791 +#endif /* TYPEDEF_FLOAT_T */
10792 +
10793 +/*----------------------- define macro values -----------------------------*/
10794 +
10795 +#ifndef FALSE
10796 +#define FALSE 0
10797 +#endif
10798 +
10799 +#ifndef TRUE
10800 +#define TRUE 1
10801 +#endif
10802 +
10803 +#ifndef NULL
10804 +#define NULL 0
10805 +#endif
10806 +
10807 +#ifndef OFF
10808 +#define OFF 0
10809 +#endif
10810 +
10811 +#ifndef ON
10812 +#define ON 1
10813 +#endif
10814 +
10815 +#define AUTO (-1)
10816 +
10817 +/* Reclaiming text and data :
10818 + The following macros specify special linker sections that can be reclaimed
10819 + after a system is considered 'up'.
10820 + */
10821 +#if defined(__GNUC__) && defined(BCMRECLAIM)
10822 +extern bool bcmreclaimed;
10823 +#define BCMINITDATA(_data) __attribute__ ((__section__ (".dataini." #_data))) _data##_ini
10824 +#define BCMINITFN(_fn) __attribute__ ((__section__ (".textini." #_fn))) _fn##_ini
10825 +#define BCMINIT(_id) _id##_ini
10826 +#else
10827 +#define BCMINITDATA(_data) _data
10828 +#define BCMINITFN(_fn) _fn
10829 +#define BCMINIT(_id) _id
10830 +#define bcmreclaimed 0
10831 +#endif
10832 +
10833 +/*----------------------- define PTRSZ, INLINE ----------------------------*/
10834 +
10835 +#ifndef PTRSZ
10836 +#define PTRSZ sizeof (char*)
10837 +#endif
10838 +
10839 +#ifndef INLINE
10840 +
10841 +#ifdef _MSC_VER
10842 +
10843 +#define INLINE __inline
10844 +
10845 +#elif __GNUC__
10846 +
10847 +#define INLINE __inline__
10848 +
10849 +#else
10850 +
10851 +#define INLINE
10852 +
10853 +#endif /* _MSC_VER */
10854 +
10855 +#endif /* INLINE */
10856 +
10857 +#undef TYPEDEF_BOOL
10858 +#undef TYPEDEF_UCHAR
10859 +#undef TYPEDEF_USHORT
10860 +#undef TYPEDEF_UINT
10861 +#undef TYPEDEF_ULONG
10862 +#undef TYPEDEF_UINT8
10863 +#undef TYPEDEF_UINT16
10864 +#undef TYPEDEF_UINT32
10865 +#undef TYPEDEF_UINT64
10866 +#undef TYPEDEF_UINTPTR
10867 +#undef TYPEDEF_INT8
10868 +#undef TYPEDEF_INT16
10869 +#undef TYPEDEF_INT32
10870 +#undef TYPEDEF_INT64
10871 +#undef TYPEDEF_FLOAT32
10872 +#undef TYPEDEF_FLOAT64
10873 +#undef TYPEDEF_FLOAT_T
10874 +
10875 +#endif /* USE_TYPEDEF_DEFAULTS */
10876 +
10877 +#endif /* _TYPEDEFS_H_ */
10878 diff -urN linux.old/arch/mips/bcm947xx/int-handler.S linux.dev/arch/mips/bcm947xx/int-handler.S
10879 --- linux.old/arch/mips/bcm947xx/int-handler.S 1970-01-01 01:00:00.000000000 +0100
10880 +++ linux.dev/arch/mips/bcm947xx/int-handler.S 2005-12-15 12:57:27.877187750 +0100
10881 @@ -0,0 +1,48 @@
10882 +/*
10883 + * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
10884 + *
10885 + * This program is free software; you can redistribute it and/or modify it
10886 + * under the terms of the GNU General Public License as published by the
10887 + * Free Software Foundation; either version 2 of the License, or (at your
10888 + * option) any later version.
10889 + *
10890 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
10891 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
10892 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
10893 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
10894 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
10895 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
10896 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
10897 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
10898 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
10899 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
10900 + *
10901 + * You should have received a copy of the GNU General Public License along
10902 + * with this program; if not, write to the Free Software Foundation, Inc.,
10903 + * 675 Mass Ave, Cambridge, MA 02139, USA.
10904 + */
10905 +
10906 +#include <asm/asm.h>
10907 +#include <asm/mipsregs.h>
10908 +#include <asm/regdef.h>
10909 +#include <asm/stackframe.h>
10910 +
10911 + .text
10912 + .set noreorder
10913 + .set noat
10914 + .align 5
10915 +
10916 + NESTED(bcm47xx_irq_handler, PT_SIZE, sp)
10917 + SAVE_ALL
10918 + CLI
10919 +
10920 + .set at
10921 + .set noreorder
10922 +
10923 + jal bcm47xx_irq_dispatch
10924 + move a0, sp
10925 +
10926 + j ret_from_irq
10927 + nop
10928 +
10929 + END(bcm47xx_irq_handler)
10930 diff -urN linux.old/arch/mips/bcm947xx/irq.c linux.dev/arch/mips/bcm947xx/irq.c
10931 --- linux.old/arch/mips/bcm947xx/irq.c 1970-01-01 01:00:00.000000000 +0100
10932 +++ linux.dev/arch/mips/bcm947xx/irq.c 2005-12-15 12:57:27.877187750 +0100
10933 @@ -0,0 +1,67 @@
10934 +/*
10935 + * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
10936 + *
10937 + * This program is free software; you can redistribute it and/or modify it
10938 + * under the terms of the GNU General Public License as published by the
10939 + * Free Software Foundation; either version 2 of the License, or (at your
10940 + * option) any later version.
10941 + *
10942 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
10943 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
10944 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
10945 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
10946 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
10947 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
10948 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
10949 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
10950 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
10951 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
10952 + *
10953 + * You should have received a copy of the GNU General Public License along
10954 + * with this program; if not, write to the Free Software Foundation, Inc.,
10955 + * 675 Mass Ave, Cambridge, MA 02139, USA.
10956 + */
10957 +
10958 +#include <linux/config.h>
10959 +#include <linux/errno.h>
10960 +#include <linux/init.h>
10961 +#include <linux/interrupt.h>
10962 +#include <linux/irq.h>
10963 +#include <linux/module.h>
10964 +#include <linux/smp.h>
10965 +#include <linux/types.h>
10966 +
10967 +#include <asm/cpu.h>
10968 +#include <asm/io.h>
10969 +#include <asm/irq.h>
10970 +#include <asm/irq_cpu.h>
10971 +
10972 +extern asmlinkage void bcm47xx_irq_handler(void);
10973 +
10974 +void bcm47xx_irq_dispatch(struct pt_regs *regs)
10975 +{
10976 + u32 cause;
10977 +
10978 + cause = read_c0_cause() & read_c0_status() & CAUSEF_IP;
10979 +
10980 + clear_c0_status(cause);
10981 +
10982 + if (cause & CAUSEF_IP7)
10983 + do_IRQ(7, regs);
10984 + if (cause & CAUSEF_IP2)
10985 + do_IRQ(2, regs);
10986 + if (cause & CAUSEF_IP3)
10987 + do_IRQ(3, regs);
10988 + if (cause & CAUSEF_IP4)
10989 + do_IRQ(4, regs);
10990 + if (cause & CAUSEF_IP5)
10991 + do_IRQ(5, regs);
10992 + if (cause & CAUSEF_IP6)
10993 + do_IRQ(6, regs);
10994 +}
10995 +
10996 +void __init arch_init_irq(void)
10997 +{
10998 + set_except_vector(0, bcm47xx_irq_handler);
10999 + mips_cpu_irq_init(0);
11000 +}
11001 diff -urN linux.old/arch/mips/bcm947xx/pci.c linux.dev/arch/mips/bcm947xx/pci.c
11002 --- linux.old/arch/mips/bcm947xx/pci.c 1970-01-01 01:00:00.000000000 +0100
11003 +++ linux.dev/arch/mips/bcm947xx/pci.c 2005-12-15 23:25:48.489984500 +0100
11004 @@ -0,0 +1,92 @@
11005 +#include <linux/kernel.h>
11006 +#include <linux/init.h>
11007 +#include <linux/pci.h>
11008 +#include <linux/types.h>
11009 +
11010 +#include <asm/cpu.h>
11011 +#include <asm/io.h>
11012 +
11013 +#include <typedefs.h>
11014 +#include <osl.h>
11015 +#include <sbutils.h>
11016 +#include <sbmips.h>
11017 +#include <sbconfig.h>
11018 +#include <sbpci.h>
11019 +
11020 +extern sb_t *sbh;
11021 +
11022 +
11023 +static int
11024 +sb_pci_read_config(struct pci_bus *bus, unsigned int devfn,
11025 + int reg, int size, u32 *val)
11026 +{
11027 + int ret;
11028 + ret = sbpci_read_config(sbh, bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), reg, val, size);
11029 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
11030 +}
11031 +
11032 +static int
11033 +sb_pci_write_config(struct pci_bus *bus, unsigned int devfn,
11034 + int reg, int size, u32 val)
11035 +{
11036 + int ret;
11037 + ret = sbpci_write_config(sbh, bus->number, PCI_SLOT(devfn), PCI_FUNC(devfn), reg, &val, size);
11038 + return ret ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL;
11039 +}
11040 +
11041 +
11042 +static struct pci_ops sb_pci_ops = {
11043 + .read = sb_pci_read_config,
11044 + .write = sb_pci_write_config,
11045 +};
11046 +
11047 +
11048 +static struct resource sb_pci_mem_resource = {
11049 + .name = "SB PCI Memory resources",
11050 + .start = SB_ENUM_BASE,
11051 + .end = SB_ENUM_LIM - 1,
11052 + .flags = IORESOURCE_MEM,
11053 +};
11054 +
11055 +static struct resource sb_pci_io_resource = {
11056 + .name = "SB PCI I/O resources",
11057 + .start = 0x100,
11058 + .end = 0x1FF,
11059 + .flags = IORESOURCE_IO,
11060 +};
11061 +
11062 +static struct pci_controller bcm47xx_sb_pci_controller = {
11063 + .pci_ops = &sb_pci_ops,
11064 + .mem_resource = &sb_pci_mem_resource,
11065 + .io_resource = &sb_pci_io_resource,
11066 +};
11067 +
11068 +static struct resource ext_pci_mem_resource = {
11069 + .name = "Ext PCI Memory resources",
11070 + .start = 0x40000000,
11071 + .end = 0x7fffffff,
11072 + .flags = IORESOURCE_MEM,
11073 +};
11074 +
11075 +static struct resource ext_pci_io_resource = {
11076 + .name = "Ext PCI I/O resources",
11077 + .start = 0x200,
11078 + .end = 0x2FF,
11079 + .flags = IORESOURCE_IO,
11080 +};
11081 +
11082 +static struct pci_controller bcm47xx_ext_pci_controller = {
11083 + .pci_ops = &sb_pci_ops,
11084 + .mem_resource = &ext_pci_mem_resource,
11085 + .io_resource = &ext_pci_io_resource,
11086 +};
11087 +
11088 +void bcm47xx_pci_init(void)
11089 +{
11090 + sbpci_init(sbh);
11091 +
11092 + set_io_port_base((unsigned long) ioremap_nocache(SB_PCI_MEM, 0x04000000));
11093 +
11094 + register_pci_controller(&bcm47xx_sb_pci_controller);
11095 + register_pci_controller(&bcm47xx_ext_pci_controller);
11096 +}
11097 diff -urN linux.old/arch/mips/bcm947xx/prom.c linux.dev/arch/mips/bcm947xx/prom.c
11098 --- linux.old/arch/mips/bcm947xx/prom.c 1970-01-01 01:00:00.000000000 +0100
11099 +++ linux.dev/arch/mips/bcm947xx/prom.c 2005-12-15 12:57:27.877187750 +0100
11100 @@ -0,0 +1,59 @@
11101 +/*
11102 + * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
11103 + *
11104 + * This program is free software; you can redistribute it and/or modify it
11105 + * under the terms of the GNU General Public License as published by the
11106 + * Free Software Foundation; either version 2 of the License, or (at your
11107 + * option) any later version.
11108 + *
11109 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11110 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
11111 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
11112 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
11113 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
11114 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
11115 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
11116 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
11117 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
11118 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
11119 + *
11120 + * You should have received a copy of the GNU General Public License along
11121 + * with this program; if not, write to the Free Software Foundation, Inc.,
11122 + * 675 Mass Ave, Cambridge, MA 02139, USA.
11123 + */
11124 +
11125 +#include <linux/init.h>
11126 +#include <linux/mm.h>
11127 +#include <linux/sched.h>
11128 +#include <linux/bootmem.h>
11129 +
11130 +#include <asm/addrspace.h>
11131 +#include <asm/bootinfo.h>
11132 +#include <asm/pmon.h>
11133 +
11134 +const char *get_system_type(void)
11135 +{
11136 + return "Broadcom BCM47xx";
11137 +}
11138 +
11139 +void __init prom_init(void)
11140 +{
11141 + unsigned long mem;
11142 +
11143 + mips_machgroup = MACH_GROUP_BRCM;
11144 + mips_machtype = MACH_BCM47XX;
11145 +
11146 + /* Figure out memory size by finding aliases */
11147 + for (mem = (1 << 20); mem < (128 << 20); mem += (1 << 20)) {
11148 + if (*(unsigned long *)((unsigned long)(prom_init) + mem) ==
11149 + *(unsigned long *)(prom_init))
11150 + break;
11151 + }
11152 +
11153 + add_memory_region(0, mem, BOOT_MEM_RAM);
11154 +}
11155 +
11156 +unsigned long __init prom_free_prom_memory(void)
11157 +{
11158 + return 0;
11159 +}
11160 diff -urN linux.old/arch/mips/bcm947xx/setup.c linux.dev/arch/mips/bcm947xx/setup.c
11161 --- linux.old/arch/mips/bcm947xx/setup.c 1970-01-01 01:00:00.000000000 +0100
11162 +++ linux.dev/arch/mips/bcm947xx/setup.c 2005-12-15 19:17:21.508844000 +0100
11163 @@ -0,0 +1,107 @@
11164 +/*
11165 + * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
11166 + * Copyright (C) 2005 Waldemar Brodkorb <wbx@openwrt.org>
11167 + *
11168 + * This program is free software; you can redistribute it and/or modify it
11169 + * under the terms of the GNU General Public License as published by the
11170 + * Free Software Foundation; either version 2 of the License, or (at your
11171 + * option) any later version.
11172 + *
11173 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11174 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
11175 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
11176 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
11177 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
11178 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
11179 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
11180 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
11181 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
11182 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
11183 + *
11184 + * You should have received a copy of the GNU General Public License along
11185 + * with this program; if not, write to the Free Software Foundation, Inc.,
11186 + * 675 Mass Ave, Cambridge, MA 02139, USA.
11187 + */
11188 +
11189 +#include <linux/init.h>
11190 +#include <linux/types.h>
11191 +#include <linux/tty.h>
11192 +#include <linux/serial.h>
11193 +#include <linux/serial_core.h>
11194 +#include <linux/serial_reg.h>
11195 +#include <asm/bootinfo.h>
11196 +#include <asm/time.h>
11197 +#include <asm/reboot.h>
11198 +
11199 +#include <typedefs.h>
11200 +#include <osl.h>
11201 +#include <sbutils.h>
11202 +#include <sbmips.h>
11203 +#include <sbpci.h>
11204 +#include <sbconfig.h>
11205 +#include <bcmdevs.h>
11206 +
11207 +extern void bcm47xx_pci_init(void);
11208 +extern void bcm47xx_time_init(void);
11209 +extern void bcm47xx_timer_setup(struct irqaction *irq);
11210 +void *sbh;
11211 +
11212 +static int ser_line = 0;
11213 +
11214 +static void
11215 +serial_add(void *regs, uint irq, uint baud_base, uint reg_shift)
11216 +{
11217 + struct uart_port s;
11218 +
11219 + memset(&s, 0, sizeof(s));
11220 +
11221 + s.line = ser_line++;
11222 + s.membase = regs;
11223 + s.irq = irq + 2;
11224 + s.uartclk = baud_base;
11225 + s.flags = ASYNC_BOOT_AUTOCONF;
11226 + s.iotype = SERIAL_IO_MEM;
11227 + s.regshift = reg_shift;
11228 +
11229 + if (early_serial_setup(&s) != 0) {
11230 + printk(KERN_ERR "Serial setup failed!\n");
11231 + }
11232 +}
11233 +
11234 +static void bcm47xx_machine_restart(char *command)
11235 +{
11236 + printk("Please stand by while rebooting the system...\n");
11237 +
11238 + /* Set the watchdog timer to reset immediately */
11239 + local_irq_disable();
11240 + sb_watchdog(sbh, 1);
11241 + while (1);
11242 +}
11243 +
11244 +static void bcm47xx_machine_halt(void)
11245 +{
11246 + /* Disable interrupts and watchdog and spin forever */
11247 + local_irq_disable();
11248 + sb_watchdog(sbh, 0);
11249 + while (1);
11250 +}
11251 +
11252 +void __init plat_setup(void)
11253 +{
11254 +
11255 + sbh = sb_kattach();
11256 + sb_mips_init(sbh);
11257 +
11258 + bcm47xx_pci_init();
11259 +
11260 + set_io_port_base((unsigned long) ioremap_nocache(SB_PCI_MEM, 0x04000000));
11261 +
11262 + sb_serial_init(sbh, serial_add);
11263 +
11264 + _machine_restart = bcm47xx_machine_restart;
11265 + _machine_halt = bcm47xx_machine_halt;
11266 + _machine_power_off = bcm47xx_machine_halt;
11267 +
11268 + board_time_init = bcm47xx_time_init;
11269 + board_timer_setup = bcm47xx_timer_setup;
11270 +}
11271 diff -urN linux.old/arch/mips/bcm947xx/time.c linux.dev/arch/mips/bcm947xx/time.c
11272 --- linux.old/arch/mips/bcm947xx/time.c 1970-01-01 01:00:00.000000000 +0100
11273 +++ linux.dev/arch/mips/bcm947xx/time.c 2005-12-15 12:57:27.877187750 +0100
11274 @@ -0,0 +1,59 @@
11275 +/*
11276 + * Copyright (C) 2004 Florian Schirmer (jolt@tuxbox.org)
11277 + *
11278 + * This program is free software; you can redistribute it and/or modify it
11279 + * under the terms of the GNU General Public License as published by the
11280 + * Free Software Foundation; either version 2 of the License, or (at your
11281 + * option) any later version.
11282 + *
11283 + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11284 + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
11285 + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
11286 + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
11287 + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
11288 + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
11289 + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
11290 + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
11291 + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
11292 + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
11293 + *
11294 + * You should have received a copy of the GNU General Public License along
11295 + * with this program; if not, write to the Free Software Foundation, Inc.,
11296 + * 675 Mass Ave, Cambridge, MA 02139, USA.
11297 + */
11298 +
11299 +#include <linux/config.h>
11300 +#include <linux/init.h>
11301 +#include <linux/kernel.h>
11302 +#include <linux/sched.h>
11303 +#include <linux/serial_reg.h>
11304 +#include <linux/interrupt.h>
11305 +#include <asm/addrspace.h>
11306 +#include <asm/io.h>
11307 +#include <asm/time.h>
11308 +
11309 +void __init
11310 +bcm47xx_time_init(void)
11311 +{
11312 + unsigned int hz;
11313 +
11314 + /*
11315 + * Use deterministic values for initial counter interrupt
11316 + * so that calibrate delay avoids encountering a counter wrap.
11317 + */
11318 + write_c0_count(0);
11319 + write_c0_compare(0xffff);
11320 +
11321 + hz = 200 * 1000 * 1000;
11322 +
11323 + /* Set MIPS counter frequency for fixed_rate_gettimeoffset() */
11324 + mips_hpt_frequency = hz / 2;
11325 +
11326 +}
11327 +
11328 +void __init
11329 +bcm47xx_timer_setup(struct irqaction *irq)
11330 +{
11331 + /* Enable the timer interrupt */
11332 + setup_irq(7, irq);
11333 +}
11334 diff -urN linux.old/arch/mips/kernel/cpu-probe.c linux.dev/arch/mips/kernel/cpu-probe.c
11335 --- linux.old/arch/mips/kernel/cpu-probe.c 2005-12-15 13:26:49.766024000 +0100
11336 +++ linux.dev/arch/mips/kernel/cpu-probe.c 2005-12-15 12:57:27.901177250 +0100
11337 @@ -656,6 +656,28 @@
11338 }
11339
11340
11341 +static inline void cpu_probe_broadcom(struct cpuinfo_mips *c)
11342 +{
11343 + decode_config1(c);
11344 + switch (c->processor_id & 0xff00) {
11345 + case PRID_IMP_BCM3302:
11346 + c->cputype = CPU_BCM3302;
11347 + c->isa_level = MIPS_CPU_ISA_M32;
11348 + c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
11349 + MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER;
11350 + break;
11351 + case PRID_IMP_BCM4710:
11352 + c->cputype = CPU_BCM4710;
11353 + c->isa_level = MIPS_CPU_ISA_M32;
11354 + c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
11355 + MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER;
11356 + break;
11357 + default:
11358 + c->cputype = CPU_UNKNOWN;
11359 + break;
11360 + }
11361 +}
11362 +
11363 __init void cpu_probe(void)
11364 {
11365 struct cpuinfo_mips *c = &current_cpu_data;
11366 @@ -678,6 +700,9 @@
11367 case PRID_COMP_SIBYTE:
11368 cpu_probe_sibyte(c);
11369 break;
11370 + case PRID_COMP_BROADCOM:
11371 + cpu_probe_broadcom(c);
11372 + break;
11373 case PRID_COMP_SANDCRAFT:
11374 cpu_probe_sandcraft(c);
11375 break;
11376 diff -urN linux.old/arch/mips/kernel/head.S linux.dev/arch/mips/kernel/head.S
11377 --- linux.old/arch/mips/kernel/head.S 2005-12-15 13:26:49.766024000 +0100
11378 +++ linux.dev/arch/mips/kernel/head.S 2005-12-15 12:57:27.901177250 +0100
11379 @@ -107,6 +107,14 @@
11380 #endif
11381 .endm
11382
11383 +#ifdef CONFIG_BCM4710
11384 +#undef eret
11385 +#define eret nop; nop; eret
11386 +#endif
11387 +
11388 + j kernel_entry
11389 + nop
11390 +
11391 /*
11392 * Reserved space for exception handlers.
11393 * Necessary for machines which link their kernels at KSEG0.
11394 diff -urN linux.old/arch/mips/kernel/proc.c linux.dev/arch/mips/kernel/proc.c
11395 --- linux.old/arch/mips/kernel/proc.c 2005-12-15 13:26:49.766024000 +0100
11396 +++ linux.dev/arch/mips/kernel/proc.c 2005-12-15 12:57:27.921168500 +0100
11397 @@ -82,6 +82,8 @@
11398 [CPU_VR4181] = "NEC VR4181",
11399 [CPU_VR4181A] = "NEC VR4181A",
11400 [CPU_SR71000] = "Sandcraft SR71000",
11401 + [CPU_BCM3302] = "Broadcom BCM3302",
11402 + [CPU_BCM4710] = "Broadcom BCM4710",
11403 [CPU_PR4450] = "Philips PR4450",
11404 };
11405
11406 diff -urN linux.old/arch/mips/mm/tlbex.c linux.dev/arch/mips/mm/tlbex.c
11407 --- linux.old/arch/mips/mm/tlbex.c 2005-12-15 13:26:49.794011750 +0100
11408 +++ linux.dev/arch/mips/mm/tlbex.c 2005-12-15 12:57:27.945158000 +0100
11409 @@ -858,6 +858,8 @@
11410 case CPU_4KSC:
11411 case CPU_20KC:
11412 case CPU_25KF:
11413 + case CPU_BCM3302:
11414 + case CPU_BCM4710:
11415 tlbw(p);
11416 break;
11417
11418 diff -urN linux.old/arch/mips/pci/Makefile linux.dev/arch/mips/pci/Makefile
11419 --- linux.old/arch/mips/pci/Makefile 2005-12-15 13:26:49.814003000 +0100
11420 +++ linux.dev/arch/mips/pci/Makefile 2005-12-15 14:27:26.439319250 +0100
11421 @@ -18,6 +18,7 @@
11422 obj-$(CONFIG_MIPS_TX3927) += ops-tx3927.o
11423 obj-$(CONFIG_PCI_VR41XX) += ops-vr41xx.o pci-vr41xx.o
11424 obj-$(CONFIG_NEC_CMBVR4133) += fixup-vr4133.o
11425 +obj-$(CONFIG_BCM947XX) += fixup-bcm47xx.o
11426
11427 #
11428 # These are still pretty much in the old state, watch, go blind.
11429 diff -urN linux.old/arch/mips/pci/fixup-bcm47xx.c linux.dev/arch/mips/pci/fixup-bcm47xx.c
11430 --- linux.old/arch/mips/pci/fixup-bcm47xx.c 1970-01-01 01:00:00.000000000 +0100
11431 +++ linux.dev/arch/mips/pci/fixup-bcm47xx.c 2005-12-15 12:57:27.945158000 +0100
11432 @@ -0,0 +1,23 @@
11433 +#include <linux/init.h>
11434 +#include <linux/pci.h>
11435 +
11436 +/* Do platform specific device initialization at pci_enable_device() time */
11437 +int pcibios_plat_dev_init(struct pci_dev *dev)
11438 +{
11439 + return 0;
11440 +}
11441 +
11442 +int __init pcibios_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
11443 +{
11444 + u8 irq;
11445 +
11446 + if (dev->bus->number == 1)
11447 + return 2;
11448 +
11449 + pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
11450 + return irq + 2;
11451 +}
11452 +
11453 +struct pci_fixup pcibios_fixups[] = {
11454 + { 0 }
11455 +};
11456 diff -urN linux.old/include/asm-mips/bootinfo.h linux.dev/include/asm-mips/bootinfo.h
11457 --- linux.old/include/asm-mips/bootinfo.h 2005-12-15 13:26:49.818001250 +0100
11458 +++ linux.dev/include/asm-mips/bootinfo.h 2005-12-15 12:57:27.969147500 +0100
11459 @@ -218,6 +218,12 @@
11460 #define MACH_GROUP_TITAN 22 /* PMC-Sierra Titan */
11461 #define MACH_TITAN_YOSEMITE 1 /* PMC-Sierra Yosemite */
11462
11463 +/*
11464 + * Valid machtype for group Broadcom
11465 + */
11466 +#define MACH_GROUP_BRCM 23 /* Broadcom */
11467 +#define MACH_BCM47XX 1 /* Broadcom BCM47xx */
11468 +
11469 #define CL_SIZE COMMAND_LINE_SIZE
11470
11471 const char *get_system_type(void);
11472 diff -urN linux.old/include/asm-mips/cpu.h linux.dev/include/asm-mips/cpu.h
11473 --- linux.old/include/asm-mips/cpu.h 2005-12-15 13:26:49.818001250 +0100
11474 +++ linux.dev/include/asm-mips/cpu.h 2005-12-15 12:57:27.969147500 +0100
11475 @@ -102,6 +102,13 @@
11476 #define PRID_IMP_SR71000 0x0400
11477
11478 /*
11479 + * These are the PRID's for when 23:16 == PRID_COMP_BROADCOM
11480 + */
11481 +
11482 +#define PRID_IMP_BCM4710 0x4000
11483 +#define PRID_IMP_BCM3302 0x9000
11484 +
11485 +/*
11486 * Definitions for 7:0 on legacy processors
11487 */
11488
11489 @@ -196,7 +203,9 @@
11490 #define CPU_34K 60
11491 #define CPU_PR4450 61
11492 #define CPU_SB1A 62
11493 -#define CPU_LAST 62
11494 +#define CPU_BCM3302 63
11495 +#define CPU_BCM4710 64
11496 +#define CPU_LAST 64
11497
11498 /*
11499 * ISA Level encodings
11500 diff -urN linux.old/include/linux/init.h linux.dev/include/linux/init.h
11501 --- linux.old/include/linux/init.h 2005-12-15 13:26:49.818001250 +0100
11502 +++ linux.dev/include/linux/init.h 2005-12-15 12:57:27.973145750 +0100
11503 @@ -86,6 +86,8 @@
11504 static initcall_t __initcall_##fn __attribute_used__ \
11505 __attribute__((__section__(".initcall" level ".init"))) = fn
11506
11507 +#define early_initcall(fn) __define_initcall(".early1",fn)
11508 +
11509 #define core_initcall(fn) __define_initcall("1",fn)
11510 #define postcore_initcall(fn) __define_initcall("2",fn)
11511 #define arch_initcall(fn) __define_initcall("3",fn)
11512 diff -urN linux.old/include/linux/pci_ids.h linux.dev/include/linux/pci_ids.h
11513 --- linux.old/include/linux/pci_ids.h 2005-12-15 13:26:49.818001250 +0100
11514 +++ linux.dev/include/linux/pci_ids.h 2005-12-15 12:57:27.977144000 +0100
11515 @@ -1835,6 +1835,7 @@
11516 #define PCI_DEVICE_ID_TIGON3_5901_2 0x170e
11517 #define PCI_DEVICE_ID_BCM4401 0x4401
11518 #define PCI_DEVICE_ID_BCM4401B0 0x4402
11519 +#define PCI_DEVICE_ID_BCM4713 0x4713
11520
11521 #define PCI_VENDOR_ID_TOPIC 0x151f
11522 #define PCI_DEVICE_ID_TOPIC_TP560 0x0000
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