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[openwrt/svn-archive/archive.git] / package / ath9k / src / drivers / net / wireless / ath9k / hw.c
1 /*
2 * Copyright (c) 2008 Atheros Communications Inc.
3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
17 #include <linux/io.h>
18
19 #include "ath9k.h"
20 #include "hw.h"
21 #include "reg.h"
22 #include "phy.h"
23 #include "initvals.h"
24
25 static void ath9k_hw_iqcal_collect(struct ath_hal *ah);
26 static void ath9k_hw_iqcalibrate(struct ath_hal *ah, u_int8_t numChains);
27 static void ath9k_hw_adc_gaincal_collect(struct ath_hal *ah);
28 static void ath9k_hw_adc_gaincal_calibrate(struct ath_hal *ah,
29 u_int8_t numChains);
30 static void ath9k_hw_adc_dccal_collect(struct ath_hal *ah);
31 static void ath9k_hw_adc_dccal_calibrate(struct ath_hal *ah,
32 u_int8_t numChains);
33
34 static const u_int8_t CLOCK_RATE[] = { 40, 80, 22, 44, 88, 40 };
35 static const int16_t NOISE_FLOOR[] = { -96, -93, -98, -96, -93, -96 };
36
37 static const struct hal_percal_data iq_cal_multi_sample = {
38 IQ_MISMATCH_CAL,
39 MAX_CAL_SAMPLES,
40 PER_MIN_LOG_COUNT,
41 ath9k_hw_iqcal_collect,
42 ath9k_hw_iqcalibrate
43 };
44 static const struct hal_percal_data iq_cal_single_sample = {
45 IQ_MISMATCH_CAL,
46 MIN_CAL_SAMPLES,
47 PER_MAX_LOG_COUNT,
48 ath9k_hw_iqcal_collect,
49 ath9k_hw_iqcalibrate
50 };
51 static const struct hal_percal_data adc_gain_cal_multi_sample = {
52 ADC_GAIN_CAL,
53 MAX_CAL_SAMPLES,
54 PER_MIN_LOG_COUNT,
55 ath9k_hw_adc_gaincal_collect,
56 ath9k_hw_adc_gaincal_calibrate
57 };
58 static const struct hal_percal_data adc_gain_cal_single_sample = {
59 ADC_GAIN_CAL,
60 MIN_CAL_SAMPLES,
61 PER_MAX_LOG_COUNT,
62 ath9k_hw_adc_gaincal_collect,
63 ath9k_hw_adc_gaincal_calibrate
64 };
65 static const struct hal_percal_data adc_dc_cal_multi_sample = {
66 ADC_DC_CAL,
67 MAX_CAL_SAMPLES,
68 PER_MIN_LOG_COUNT,
69 ath9k_hw_adc_dccal_collect,
70 ath9k_hw_adc_dccal_calibrate
71 };
72 static const struct hal_percal_data adc_dc_cal_single_sample = {
73 ADC_DC_CAL,
74 MIN_CAL_SAMPLES,
75 PER_MAX_LOG_COUNT,
76 ath9k_hw_adc_dccal_collect,
77 ath9k_hw_adc_dccal_calibrate
78 };
79 static const struct hal_percal_data adc_init_dc_cal = {
80 ADC_DC_INIT_CAL,
81 MIN_CAL_SAMPLES,
82 INIT_LOG_COUNT,
83 ath9k_hw_adc_dccal_collect,
84 ath9k_hw_adc_dccal_calibrate
85 };
86
87 static const struct ath_hal ar5416hal = {
88 AR5416_MAGIC,
89 0,
90 0,
91 NULL,
92 NULL,
93 CTRY_DEFAULT,
94 0,
95 0,
96 0,
97 0,
98 0,
99 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
100 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
101 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
102 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
103 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
104 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
105 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
106 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
107 },
108 };
109
110 static struct hal_rate_table ar5416_11a_table = {
111 8,
112 {0},
113 {
114 {AH_TRUE, PHY_OFDM, 6000, 0x0b, 0x00, (0x80 | 12), 0},
115 {AH_TRUE, PHY_OFDM, 9000, 0x0f, 0x00, 18, 0},
116 {AH_TRUE, PHY_OFDM, 12000, 0x0a, 0x00, (0x80 | 24), 2},
117 {AH_TRUE, PHY_OFDM, 18000, 0x0e, 0x00, 36, 2},
118 {AH_TRUE, PHY_OFDM, 24000, 0x09, 0x00, (0x80 | 48), 4},
119 {AH_TRUE, PHY_OFDM, 36000, 0x0d, 0x00, 72, 4},
120 {AH_TRUE, PHY_OFDM, 48000, 0x08, 0x00, 96, 4},
121 {AH_TRUE, PHY_OFDM, 54000, 0x0c, 0x00, 108, 4}
122 },
123 };
124
125 static struct hal_rate_table ar5416_11b_table = {
126 4,
127 {0},
128 {
129 {AH_TRUE, PHY_CCK, 1000, 0x1b, 0x00, (0x80 | 2), 0},
130 {AH_TRUE, PHY_CCK, 2000, 0x1a, 0x04, (0x80 | 4), 1},
131 {AH_TRUE, PHY_CCK, 5500, 0x19, 0x04, (0x80 | 11), 1},
132 {AH_TRUE, PHY_CCK, 11000, 0x18, 0x04, (0x80 | 22), 1}
133 },
134 };
135
136 static struct hal_rate_table ar5416_11g_table = {
137 12,
138 {0},
139 {
140 {AH_TRUE, PHY_CCK, 1000, 0x1b, 0x00, (0x80 | 2), 0},
141 {AH_TRUE, PHY_CCK, 2000, 0x1a, 0x04, (0x80 | 4), 1},
142 {AH_TRUE, PHY_CCK, 5500, 0x19, 0x04, (0x80 | 11), 2},
143 {AH_TRUE, PHY_CCK, 11000, 0x18, 0x04, (0x80 | 22), 3},
144
145 {AH_FALSE, PHY_OFDM, 6000, 0x0b, 0x00, 12, 4},
146 {AH_FALSE, PHY_OFDM, 9000, 0x0f, 0x00, 18, 4},
147 {AH_TRUE, PHY_OFDM, 12000, 0x0a, 0x00, 24, 6},
148 {AH_TRUE, PHY_OFDM, 18000, 0x0e, 0x00, 36, 6},
149 {AH_TRUE, PHY_OFDM, 24000, 0x09, 0x00, 48, 8},
150 {AH_TRUE, PHY_OFDM, 36000, 0x0d, 0x00, 72, 8},
151 {AH_TRUE, PHY_OFDM, 48000, 0x08, 0x00, 96, 8},
152 {AH_TRUE, PHY_OFDM, 54000, 0x0c, 0x00, 108, 8}
153 },
154 };
155
156 static struct hal_rate_table ar5416_11ng_table = {
157 28,
158 {0},
159 {
160 {AH_TRUE, PHY_CCK, 1000, 0x1b, 0x00, (0x80 | 2), 0},
161 {AH_TRUE, PHY_CCK, 2000, 0x1a, 0x04, (0x80 | 4), 1},
162 {AH_TRUE, PHY_CCK, 5500, 0x19, 0x04, (0x80 | 11), 2},
163 {AH_TRUE, PHY_CCK, 11000, 0x18, 0x04, (0x80 | 22), 3},
164
165 {AH_FALSE, PHY_OFDM, 6000, 0x0b, 0x00, 12, 4},
166 {AH_FALSE, PHY_OFDM, 9000, 0x0f, 0x00, 18, 4},
167 {AH_TRUE, PHY_OFDM, 12000, 0x0a, 0x00, 24, 6},
168 {AH_TRUE, PHY_OFDM, 18000, 0x0e, 0x00, 36, 6},
169 {AH_TRUE, PHY_OFDM, 24000, 0x09, 0x00, 48, 8},
170 {AH_TRUE, PHY_OFDM, 36000, 0x0d, 0x00, 72, 8},
171 {AH_TRUE, PHY_OFDM, 48000, 0x08, 0x00, 96, 8},
172 {AH_TRUE, PHY_OFDM, 54000, 0x0c, 0x00, 108, 8},
173 {AH_TRUE, PHY_HT, 6500, 0x80, 0x00, 0, 4},
174 {AH_TRUE, PHY_HT, 13000, 0x81, 0x00, 1, 6},
175 {AH_TRUE, PHY_HT, 19500, 0x82, 0x00, 2, 6},
176 {AH_TRUE, PHY_HT, 26000, 0x83, 0x00, 3, 8},
177 {AH_TRUE, PHY_HT, 39000, 0x84, 0x00, 4, 8},
178 {AH_TRUE, PHY_HT, 52000, 0x85, 0x00, 5, 8},
179 {AH_TRUE, PHY_HT, 58500, 0x86, 0x00, 6, 8},
180 {AH_TRUE, PHY_HT, 65000, 0x87, 0x00, 7, 8},
181 {AH_TRUE, PHY_HT, 13000, 0x88, 0x00, 8, 4},
182 {AH_TRUE, PHY_HT, 26000, 0x89, 0x00, 9, 6},
183 {AH_TRUE, PHY_HT, 39000, 0x8a, 0x00, 10, 6},
184 {AH_TRUE, PHY_HT, 52000, 0x8b, 0x00, 11, 8},
185 {AH_TRUE, PHY_HT, 78000, 0x8c, 0x00, 12, 8},
186 {AH_TRUE, PHY_HT, 104000, 0x8d, 0x00, 13, 8},
187 {AH_TRUE, PHY_HT, 117000, 0x8e, 0x00, 14, 8},
188 {AH_TRUE, PHY_HT, 130000, 0x8f, 0x00, 15, 8},
189 },
190 };
191
192 static struct hal_rate_table ar5416_11na_table = {
193 24,
194 {0},
195 {
196 {AH_TRUE, PHY_OFDM, 6000, 0x0b, 0x00, (0x80 | 12), 0},
197 {AH_TRUE, PHY_OFDM, 9000, 0x0f, 0x00, 18, 0},
198 {AH_TRUE, PHY_OFDM, 12000, 0x0a, 0x00, (0x80 | 24), 2},
199 {AH_TRUE, PHY_OFDM, 18000, 0x0e, 0x00, 36, 2},
200 {AH_TRUE, PHY_OFDM, 24000, 0x09, 0x00, (0x80 | 48), 4},
201 {AH_TRUE, PHY_OFDM, 36000, 0x0d, 0x00, 72, 4},
202 {AH_TRUE, PHY_OFDM, 48000, 0x08, 0x00, 96, 4},
203 {AH_TRUE, PHY_OFDM, 54000, 0x0c, 0x00, 108, 4},
204 {AH_TRUE, PHY_HT, 6500, 0x80, 0x00, 0, 0},
205 {AH_TRUE, PHY_HT, 13000, 0x81, 0x00, 1, 2},
206 {AH_TRUE, PHY_HT, 19500, 0x82, 0x00, 2, 2},
207 {AH_TRUE, PHY_HT, 26000, 0x83, 0x00, 3, 4},
208 {AH_TRUE, PHY_HT, 39000, 0x84, 0x00, 4, 4},
209 {AH_TRUE, PHY_HT, 52000, 0x85, 0x00, 5, 4},
210 {AH_TRUE, PHY_HT, 58500, 0x86, 0x00, 6, 4},
211 {AH_TRUE, PHY_HT, 65000, 0x87, 0x00, 7, 4},
212 {AH_TRUE, PHY_HT, 13000, 0x88, 0x00, 8, 0},
213 {AH_TRUE, PHY_HT, 26000, 0x89, 0x00, 9, 2},
214 {AH_TRUE, PHY_HT, 39000, 0x8a, 0x00, 10, 2},
215 {AH_TRUE, PHY_HT, 52000, 0x8b, 0x00, 11, 4},
216 {AH_TRUE, PHY_HT, 78000, 0x8c, 0x00, 12, 4},
217 {AH_TRUE, PHY_HT, 104000, 0x8d, 0x00, 13, 4},
218 {AH_TRUE, PHY_HT, 117000, 0x8e, 0x00, 14, 4},
219 {AH_TRUE, PHY_HT, 130000, 0x8f, 0x00, 15, 4},
220 },
221 };
222
223 static enum wireless_mode ath9k_hw_chan2wmode(struct ath_hal *ah,
224 const struct hal_channel *chan)
225 {
226 if (IS_CHAN_CCK(chan))
227 return WIRELESS_MODE_11b;
228 if (IS_CHAN_G(chan))
229 return WIRELESS_MODE_11g;
230 return WIRELESS_MODE_11a;
231 }
232
233 static enum hal_bool ath9k_hw_wait(struct ath_hal *ah,
234 u_int reg,
235 u_int32_t mask,
236 u_int32_t val)
237 {
238 int i;
239
240 for (i = 0; i < (AH_TIMEOUT / AH_TIME_QUANTUM); i++) {
241 if ((REG_READ(ah, reg) & mask) == val)
242 return AH_TRUE;
243
244 udelay(AH_TIME_QUANTUM);
245 }
246 HDPRINTF(ah, HAL_DBG_PHY_IO,
247 "%s: timeout on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
248 __func__, reg, REG_READ(ah, reg), mask, val);
249 return AH_FALSE;
250 }
251
252 static enum hal_bool ath9k_hw_eeprom_read(struct ath_hal *ah, u_int off,
253 u_int16_t *data)
254 {
255 (void) REG_READ(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S));
256
257 if (!ath9k_hw_wait(ah,
258 AR_EEPROM_STATUS_DATA,
259 AR_EEPROM_STATUS_DATA_BUSY |
260 AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0)) {
261 return AH_FALSE;
262 }
263
264 *data = MS(REG_READ(ah, AR_EEPROM_STATUS_DATA),
265 AR_EEPROM_STATUS_DATA_VAL);
266
267 return AH_TRUE;
268 }
269
270 static enum hal_status ath9k_hw_flash_map(struct ath_hal *ah)
271 {
272 struct ath_hal_5416 *ahp = AH5416(ah);
273
274 ahp->ah_cal_mem = ioremap(AR5416_EEPROM_START_ADDR, AR5416_EEPROM_MAX);
275
276 if (!ahp->ah_cal_mem) {
277 HDPRINTF(ah, HAL_DBG_EEPROM,
278 "%s: cannot remap eeprom region \n", __func__);
279 return HAL_EIO;
280 }
281
282 return HAL_OK;
283 }
284
285 static enum hal_bool ath9k_hw_flash_read(struct ath_hal *ah, u_int off,
286 u_int16_t *data)
287 {
288 struct ath_hal_5416 *ahp = AH5416(ah);
289
290 *data = ioread16(ahp->ah_cal_mem + off);
291 return AH_TRUE;
292 }
293
294 static void ath9k_hw_read_revisions(struct ath_hal *ah)
295 {
296 u_int32_t val;
297
298 val = REG_READ(ah, AR_SREV) & AR_SREV_ID;
299
300 if (val == 0xFF) {
301 val = REG_READ(ah, AR_SREV);
302
303 ah->ah_macVersion =
304 (val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
305
306 ah->ah_macRev = MS(val, AR_SREV_REVISION2);
307 ah->ah_isPciExpress =
308 (val & AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
309
310 } else {
311 if (!AR_SREV_9100(ah))
312 ah->ah_macVersion = MS(val, AR_SREV_VERSION);
313
314 ah->ah_macRev = val & AR_SREV_REVISION;
315
316 if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE)
317 ah->ah_isPciExpress = AH_TRUE;
318 }
319 }
320
321 u_int32_t ath9k_hw_reverse_bits(u_int32_t val, u_int32_t n)
322 {
323 u_int32_t retval;
324 int i;
325
326 for (i = 0, retval = 0; i < n; i++) {
327 retval = (retval << 1) | (val & 1);
328 val >>= 1;
329 }
330 return retval;
331 }
332
333 static void ath9k_hw_set_defaults(struct ath_hal *ah)
334 {
335 int i;
336
337 ah->ah_config.ath_hal_dma_beacon_response_time = 2;
338 ah->ah_config.ath_hal_sw_beacon_response_time = 10;
339 ah->ah_config.ath_hal_additional_swba_backoff = 0;
340 ah->ah_config.ath_hal_6mb_ack = 0x0;
341 ah->ah_config.ath_hal_cwmIgnoreExtCCA = 0;
342 ah->ah_config.ath_hal_pciePowerSaveEnable = 0;
343 ah->ah_config.ath_hal_pcieL1SKPEnable = 0;
344 ah->ah_config.ath_hal_pcieClockReq = 0;
345 ah->ah_config.ath_hal_pciePowerReset = 0x100;
346 ah->ah_config.ath_hal_pcieRestore = 0;
347 ah->ah_config.ath_hal_pcieWaen = 0;
348 ah->ah_config.ath_hal_analogShiftReg = 1;
349 ah->ah_config.ath_hal_htEnable = 1;
350 ah->ah_config.ath_hal_ofdmTrigLow = 200;
351 ah->ah_config.ath_hal_ofdmTrigHigh = 500;
352 ah->ah_config.ath_hal_cckTrigHigh = 200;
353 ah->ah_config.ath_hal_cckTrigLow = 100;
354 ah->ah_config.ath_hal_enableANI = 0;
355 ah->ah_config.ath_hal_noiseImmunityLvl = 4;
356 ah->ah_config.ath_hal_ofdmWeakSigDet = 1;
357 ah->ah_config.ath_hal_cckWeakSigThr = 0;
358 ah->ah_config.ath_hal_spurImmunityLvl = 2;
359 ah->ah_config.ath_hal_firStepLvl = 0;
360 ah->ah_config.ath_hal_rssiThrHigh = 40;
361 ah->ah_config.ath_hal_rssiThrLow = 7;
362 ah->ah_config.ath_hal_diversityControl = 0;
363 ah->ah_config.ath_hal_antennaSwitchSwap = 0;
364
365 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
366 ah->ah_config.ath_hal_spurChans[i][0] = AR_NO_SPUR;
367 ah->ah_config.ath_hal_spurChans[i][1] = AR_NO_SPUR;
368 }
369
370 ah->ah_config.ath_hal_intrMitigation = 0;
371 ah->ah_config.ath_hal_debug = 0;
372 }
373
374 static inline void ath9k_hw_override_ini(struct ath_hal *ah,
375 struct hal_channel *chan)
376 {
377 if (!AR_SREV_5416_V20_OR_LATER(ah)
378 || AR_SREV_9280_10_OR_LATER(ah))
379 return;
380
381 REG_WRITE(ah, 0x9800 + (651 << 2), 0x11);
382 }
383
384 static inline void ath9k_hw_init_bb(struct ath_hal *ah,
385 struct hal_channel *chan)
386 {
387 u_int32_t synthDelay;
388
389 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
390 if (IS_CHAN_CCK(chan))
391 synthDelay = (4 * synthDelay) / 22;
392 else
393 synthDelay /= 10;
394
395 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN);
396
397 udelay(synthDelay + BASE_ACTIVATE_DELAY);
398 }
399
400 static inline void ath9k_hw_init_interrupt_masks(struct ath_hal *ah,
401 enum hal_opmode opmode)
402 {
403 struct ath_hal_5416 *ahp = AH5416(ah);
404
405 ahp->ah_maskReg = AR_IMR_TXERR |
406 AR_IMR_TXURN |
407 AR_IMR_RXERR |
408 AR_IMR_RXORN |
409 AR_IMR_BCNMISC;
410
411 if (ahp->ah_intrMitigation)
412 ahp->ah_maskReg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
413 else
414 ahp->ah_maskReg |= AR_IMR_RXOK;
415
416 ahp->ah_maskReg |= AR_IMR_TXOK;
417
418 if (opmode == HAL_M_HOSTAP)
419 ahp->ah_maskReg |= AR_IMR_MIB;
420
421 REG_WRITE(ah, AR_IMR, ahp->ah_maskReg);
422 REG_WRITE(ah, AR_IMR_S2, REG_READ(ah, AR_IMR_S2) | AR_IMR_S2_GTT);
423
424 if (!AR_SREV_9100(ah)) {
425 REG_WRITE(ah, AR_INTR_SYNC_CAUSE, 0xFFFFFFFF);
426 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, AR_INTR_SYNC_DEFAULT);
427 REG_WRITE(ah, AR_INTR_SYNC_MASK, 0);
428 }
429 }
430
431 static inline void ath9k_hw_init_qos(struct ath_hal *ah)
432 {
433 REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
434 REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
435
436 REG_WRITE(ah, AR_QOS_NO_ACK,
437 SM(2, AR_QOS_NO_ACK_TWO_BIT) |
438 SM(5, AR_QOS_NO_ACK_BIT_OFF) |
439 SM(0, AR_QOS_NO_ACK_BYTE_OFF));
440
441 REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
442 REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
443 REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
444 REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
445 REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
446 }
447
448 static void ath9k_hw_analog_shift_rmw(struct ath_hal *ah,
449 u_int reg,
450 u_int32_t mask,
451 u_int32_t shift,
452 u_int32_t val)
453 {
454 u_int32_t regVal;
455
456 regVal = REG_READ(ah, reg) & ~mask;
457 regVal |= (val << shift) & mask;
458
459 REG_WRITE(ah, reg, regVal);
460
461 if (ah->ah_config.ath_hal_analogShiftReg)
462 udelay(100);
463
464 return;
465 }
466
467 static u_int8_t ath9k_hw_get_num_ant_config(struct ath_hal_5416 *ahp,
468 enum hal_freq_band freq_band)
469 {
470 struct ar5416_eeprom *eep = &ahp->ah_eeprom;
471 struct modal_eep_header *pModal =
472 &(eep->modalHeader[HAL_FREQ_BAND_2GHZ == freq_band]);
473 struct base_eep_header *pBase = &eep->baseEepHeader;
474 u_int8_t num_ant_config;
475
476 num_ant_config = 1;
477
478 if (pBase->version >= 0x0E0D)
479 if (pModal->useAnt1)
480 num_ant_config += 1;
481
482 return num_ant_config;
483 }
484
485 static enum hal_status
486 ath9k_hw_get_eeprom_antenna_cfg(struct ath_hal_5416 *ahp,
487 struct hal_channel_internal *chan,
488 u_int8_t index,
489 u_int16_t *config)
490 {
491 struct ar5416_eeprom *eep = &ahp->ah_eeprom;
492 struct modal_eep_header *pModal =
493 &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
494 struct base_eep_header *pBase = &eep->baseEepHeader;
495
496 switch (index) {
497 case 0:
498 *config = pModal->antCtrlCommon & 0xFFFF;
499 return HAL_OK;
500 case 1:
501 if (pBase->version >= 0x0E0D) {
502 if (pModal->useAnt1) {
503 *config =
504 ((pModal->antCtrlCommon & 0xFFFF0000) >> 16);
505 return HAL_OK;
506 }
507 }
508 break;
509 default:
510 break;
511 }
512
513 return HAL_EINVAL;
514 }
515
516 static inline enum hal_bool ath9k_hw_nvram_read(struct ath_hal *ah,
517 u_int off,
518 u_int16_t *data)
519 {
520 if (ath9k_hw_use_flash(ah))
521 return ath9k_hw_flash_read(ah, off, data);
522 else
523 return ath9k_hw_eeprom_read(ah, off, data);
524 }
525
526 static inline enum hal_bool ath9k_hw_fill_eeprom(struct ath_hal *ah)
527 {
528 struct ath_hal_5416 *ahp = AH5416(ah);
529 struct ar5416_eeprom *eep = &ahp->ah_eeprom;
530 u_int16_t *eep_data;
531 int addr, ar5416_eep_start_loc = 0;
532
533 if (!ath9k_hw_use_flash(ah)) {
534 HDPRINTF(ah, HAL_DBG_EEPROM,
535 "%s: Reading from EEPROM, not flash\n", __func__);
536 ar5416_eep_start_loc = 256;
537 }
538 if (AR_SREV_9100(ah))
539 ar5416_eep_start_loc = 256;
540
541 eep_data = (u_int16_t *) eep;
542 for (addr = 0;
543 addr < sizeof(struct ar5416_eeprom) / sizeof(u_int16_t);
544 addr++) {
545 if (!ath9k_hw_nvram_read(ah, addr + ar5416_eep_start_loc,
546 eep_data)) {
547 HDPRINTF(ah, HAL_DBG_EEPROM,
548 "%s: Unable to read eeprom region \n",
549 __func__);
550 return AH_FALSE;
551 }
552 eep_data++;
553 }
554 return AH_TRUE;
555 }
556
557 /* XXX: Clean me up, make me more legible */
558 static enum hal_bool
559 ath9k_hw_eeprom_set_board_values(struct ath_hal *ah,
560 struct hal_channel_internal *chan)
561 {
562 struct modal_eep_header *pModal;
563 int i, regChainOffset;
564 struct ath_hal_5416 *ahp = AH5416(ah);
565 struct ar5416_eeprom *eep = &ahp->ah_eeprom;
566 u_int8_t txRxAttenLocal;
567 u_int16_t ant_config;
568
569 pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
570
571 txRxAttenLocal = IS_CHAN_2GHZ(chan) ? 23 : 44;
572
573 ath9k_hw_get_eeprom_antenna_cfg(ahp, chan, 1, &ant_config);
574 REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config);
575
576 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
577 if (AR_SREV_9280(ah)) {
578 if (i >= 2)
579 break;
580 }
581
582 if (AR_SREV_5416_V20_OR_LATER(ah) &&
583 (ahp->ah_rxchainmask == 5 || ahp->ah_txchainmask == 5)
584 && (i != 0))
585 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
586 else
587 regChainOffset = i * 0x1000;
588
589 REG_WRITE(ah, AR_PHY_SWITCH_CHAIN_0 + regChainOffset,
590 pModal->antCtrlChain[i]);
591
592 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0) + regChainOffset,
593 (REG_READ(ah,
594 AR_PHY_TIMING_CTRL4(0) +
595 regChainOffset) &
596 ~(AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF |
597 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF)) |
598 SM(pModal->iqCalICh[i],
599 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF) |
600 SM(pModal->iqCalQCh[i],
601 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF));
602
603 if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) {
604 if ((eep->baseEepHeader.version &
605 AR5416_EEP_VER_MINOR_MASK) >= AR5416_EEP_MINOR_VER_3) {
606 txRxAttenLocal = pModal->txRxAttenCh[i];
607 if (AR_SREV_9280_10_OR_LATER(ah)) {
608 OS_REG_RMW_FIELD(ah,
609 AR_PHY_GAIN_2GHZ +
610 regChainOffset,
611 AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN,
612 pModal->
613 bswMargin[i]);
614 OS_REG_RMW_FIELD(ah,
615 AR_PHY_GAIN_2GHZ +
616 regChainOffset,
617 AR_PHY_GAIN_2GHZ_XATTEN1_DB,
618 pModal->
619 bswAtten[i]);
620 OS_REG_RMW_FIELD(ah,
621 AR_PHY_GAIN_2GHZ +
622 regChainOffset,
623 AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN,
624 pModal->
625 xatten2Margin[i]);
626 OS_REG_RMW_FIELD(ah,
627 AR_PHY_GAIN_2GHZ +
628 regChainOffset,
629 AR_PHY_GAIN_2GHZ_XATTEN2_DB,
630 pModal->
631 xatten2Db[i]);
632 } else {
633 REG_WRITE(ah,
634 AR_PHY_GAIN_2GHZ +
635 regChainOffset,
636 (REG_READ(ah,
637 AR_PHY_GAIN_2GHZ +
638 regChainOffset) &
639 ~AR_PHY_GAIN_2GHZ_BSW_MARGIN)
640 | SM(pModal->
641 bswMargin[i],
642 AR_PHY_GAIN_2GHZ_BSW_MARGIN));
643 REG_WRITE(ah,
644 AR_PHY_GAIN_2GHZ +
645 regChainOffset,
646 (REG_READ(ah,
647 AR_PHY_GAIN_2GHZ +
648 regChainOffset) &
649 ~AR_PHY_GAIN_2GHZ_BSW_ATTEN)
650 | SM(pModal->bswAtten[i],
651 AR_PHY_GAIN_2GHZ_BSW_ATTEN));
652 }
653 }
654 if (AR_SREV_9280_10_OR_LATER(ah)) {
655 OS_REG_RMW_FIELD(ah,
656 AR_PHY_RXGAIN +
657 regChainOffset,
658 AR9280_PHY_RXGAIN_TXRX_ATTEN,
659 txRxAttenLocal);
660 OS_REG_RMW_FIELD(ah,
661 AR_PHY_RXGAIN +
662 regChainOffset,
663 AR9280_PHY_RXGAIN_TXRX_MARGIN,
664 pModal->rxTxMarginCh[i]);
665 } else {
666 REG_WRITE(ah,
667 AR_PHY_RXGAIN + regChainOffset,
668 (REG_READ(ah,
669 AR_PHY_RXGAIN +
670 regChainOffset) &
671 ~AR_PHY_RXGAIN_TXRX_ATTEN) |
672 SM(txRxAttenLocal,
673 AR_PHY_RXGAIN_TXRX_ATTEN));
674 REG_WRITE(ah,
675 AR_PHY_GAIN_2GHZ +
676 regChainOffset,
677 (REG_READ(ah,
678 AR_PHY_GAIN_2GHZ +
679 regChainOffset) &
680 ~AR_PHY_GAIN_2GHZ_RXTX_MARGIN) |
681 SM(pModal->rxTxMarginCh[i],
682 AR_PHY_GAIN_2GHZ_RXTX_MARGIN));
683 }
684 }
685 }
686
687 if (AR_SREV_9280_10_OR_LATER(ah)) {
688 if (IS_CHAN_2GHZ(chan)) {
689 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
690 AR_AN_RF2G1_CH0_OB,
691 AR_AN_RF2G1_CH0_OB_S,
692 pModal->ob);
693 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH0,
694 AR_AN_RF2G1_CH0_DB,
695 AR_AN_RF2G1_CH0_DB_S,
696 pModal->db);
697 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
698 AR_AN_RF2G1_CH1_OB,
699 AR_AN_RF2G1_CH1_OB_S,
700 pModal->ob_ch1);
701 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF2G1_CH1,
702 AR_AN_RF2G1_CH1_DB,
703 AR_AN_RF2G1_CH1_DB_S,
704 pModal->db_ch1);
705 } else {
706 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
707 AR_AN_RF5G1_CH0_OB5,
708 AR_AN_RF5G1_CH0_OB5_S,
709 pModal->ob);
710 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH0,
711 AR_AN_RF5G1_CH0_DB5,
712 AR_AN_RF5G1_CH0_DB5_S,
713 pModal->db);
714 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
715 AR_AN_RF5G1_CH1_OB5,
716 AR_AN_RF5G1_CH1_OB5_S,
717 pModal->ob_ch1);
718 ath9k_hw_analog_shift_rmw(ah, AR_AN_RF5G1_CH1,
719 AR_AN_RF5G1_CH1_DB5,
720 AR_AN_RF5G1_CH1_DB5_S,
721 pModal->db_ch1);
722 }
723 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
724 AR_AN_TOP2_XPABIAS_LVL,
725 AR_AN_TOP2_XPABIAS_LVL_S,
726 pModal->xpaBiasLvl);
727 ath9k_hw_analog_shift_rmw(ah, AR_AN_TOP2,
728 AR_AN_TOP2_LOCALBIAS,
729 AR_AN_TOP2_LOCALBIAS_S,
730 pModal->local_bias);
731 HDPRINTF(NULL, HAL_DBG_UNMASKABLE, "ForceXPAon: %d\n",
732 pModal->force_xpaon);
733 OS_REG_RMW_FIELD(ah, AR_PHY_XPA_CFG, AR_PHY_FORCE_XPA_CFG,
734 pModal->force_xpaon);
735 }
736
737 OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING, AR_PHY_SETTLING_SWITCH,
738 pModal->switchSettling);
739 OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ, AR_PHY_DESIRED_SZ_ADC,
740 pModal->adcDesiredSize);
741
742 if (!AR_SREV_9280_10_OR_LATER(ah))
743 OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
744 AR_PHY_DESIRED_SZ_PGA,
745 pModal->pgaDesiredSize);
746
747 REG_WRITE(ah, AR_PHY_RF_CTL4,
748 SM(pModal->txEndToXpaOff, AR_PHY_RF_CTL4_TX_END_XPAA_OFF)
749 | SM(pModal->txEndToXpaOff,
750 AR_PHY_RF_CTL4_TX_END_XPAB_OFF)
751 | SM(pModal->txFrameToXpaOn,
752 AR_PHY_RF_CTL4_FRAME_XPAA_ON)
753 | SM(pModal->txFrameToXpaOn,
754 AR_PHY_RF_CTL4_FRAME_XPAB_ON));
755
756 OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL3, AR_PHY_TX_END_TO_A2_RX_ON,
757 pModal->txEndToRxOn);
758 if (AR_SREV_9280_10_OR_LATER(ah)) {
759 OS_REG_RMW_FIELD(ah, AR_PHY_CCA, AR9280_PHY_CCA_THRESH62,
760 pModal->thresh62);
761 OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA0,
762 AR_PHY_EXT_CCA0_THRESH62,
763 pModal->thresh62);
764 } else {
765 OS_REG_RMW_FIELD(ah, AR_PHY_CCA, AR_PHY_CCA_THRESH62,
766 pModal->thresh62);
767 OS_REG_RMW_FIELD(ah, AR_PHY_EXT_CCA,
768 AR_PHY_EXT_CCA_THRESH62,
769 pModal->thresh62);
770 }
771
772 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
773 AR5416_EEP_MINOR_VER_2) {
774 OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2,
775 AR_PHY_TX_END_DATA_START,
776 pModal->txFrameToDataStart);
777 OS_REG_RMW_FIELD(ah, AR_PHY_RF_CTL2, AR_PHY_TX_END_PA_ON,
778 pModal->txFrameToPaOn);
779 }
780
781 if ((eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) >=
782 AR5416_EEP_MINOR_VER_3) {
783 if (IS_CHAN_HT40(chan))
784 OS_REG_RMW_FIELD(ah, AR_PHY_SETTLING,
785 AR_PHY_SETTLING_SWITCH,
786 pModal->swSettleHt40);
787 }
788
789 return AH_TRUE;
790 }
791
792 static inline enum hal_status ath9k_hw_check_eeprom(struct ath_hal *ah)
793 {
794 u_int32_t sum = 0, el;
795 u_int16_t *eepdata;
796 int i;
797 struct ath_hal_5416 *ahp = AH5416(ah);
798 enum hal_bool need_swap = AH_FALSE;
799 struct ar5416_eeprom *eep =
800 (struct ar5416_eeprom *) &ahp->ah_eeprom;
801
802 if (!ath9k_hw_use_flash(ah)) {
803 u_int16_t magic, magic2;
804 int addr;
805
806 if (ath9k_hw_nvram_read(ah, AR5416_EEPROM_MAGIC_OFFSET,
807 &magic)) {
808 HDPRINTF(ah, HAL_DBG_EEPROM,
809 "%s: Reading Magic # failed\n", __func__);
810 return AH_FALSE;
811 }
812 HDPRINTF(ah, HAL_DBG_EEPROM, "%s: Read Magic = 0x%04X\n",
813 __func__, magic);
814
815 if (magic != AR5416_EEPROM_MAGIC) {
816 magic2 = swab16(magic);
817
818 if (magic2 == AR5416_EEPROM_MAGIC) {
819 need_swap = AH_TRUE;
820 eepdata = (u_int16_t *) (&ahp->ah_eeprom);
821
822 for (addr = 0;
823 addr <
824 sizeof(struct ar5416_eeprom) /
825 sizeof(u_int16_t); addr++) {
826 u_int16_t temp;
827
828 temp = swab16(*eepdata);
829 *eepdata = temp;
830 eepdata++;
831
832 HDPRINTF(ah, HAL_DBG_EEPROM_DUMP,
833 "0x%04X ", *eepdata);
834 if (((addr + 1) % 6) == 0)
835 HDPRINTF(ah,
836 HAL_DBG_EEPROM_DUMP,
837 "\n");
838 }
839 } else {
840 HDPRINTF(ah, HAL_DBG_EEPROM,
841 "Invalid EEPROM Magic. "
842 "endianness missmatch.\n");
843 return HAL_EEBADSUM;
844 }
845 }
846 }
847 HDPRINTF(ah, HAL_DBG_EEPROM, "need_swap = %s.\n",
848 need_swap ? "True" : "False");
849
850 if (need_swap)
851 el = swab16(ahp->ah_eeprom.baseEepHeader.length);
852 else
853 el = ahp->ah_eeprom.baseEepHeader.length;
854
855 eepdata = (u_int16_t *) (&ahp->ah_eeprom);
856 for (i = 0; i <
857 min(el, sizeof(struct ar5416_eeprom)) / sizeof(u_int16_t); i++)
858 sum ^= *eepdata++;
859
860 if (need_swap) {
861 u_int32_t integer, j;
862 u_int16_t word;
863
864 HDPRINTF(ah, HAL_DBG_EEPROM,
865 "EEPROM Endianness is not native.. Changing \n");
866
867 word = swab16(eep->baseEepHeader.length);
868 eep->baseEepHeader.length = word;
869
870 word = swab16(eep->baseEepHeader.checksum);
871 eep->baseEepHeader.checksum = word;
872
873 word = swab16(eep->baseEepHeader.version);
874 eep->baseEepHeader.version = word;
875
876 word = swab16(eep->baseEepHeader.regDmn[0]);
877 eep->baseEepHeader.regDmn[0] = word;
878
879 word = swab16(eep->baseEepHeader.regDmn[1]);
880 eep->baseEepHeader.regDmn[1] = word;
881
882 word = swab16(eep->baseEepHeader.rfSilent);
883 eep->baseEepHeader.rfSilent = word;
884
885 word = swab16(eep->baseEepHeader.blueToothOptions);
886 eep->baseEepHeader.blueToothOptions = word;
887
888 word = swab16(eep->baseEepHeader.deviceCap);
889 eep->baseEepHeader.deviceCap = word;
890
891 for (j = 0; j < ARRAY_SIZE(eep->modalHeader); j++) {
892 struct modal_eep_header *pModal =
893 &eep->modalHeader[j];
894 integer = swab32(pModal->antCtrlCommon);
895 pModal->antCtrlCommon = integer;
896
897 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
898 integer = swab32(pModal->antCtrlChain[i]);
899 pModal->antCtrlChain[i] = integer;
900 }
901
902 for (i = 0; i < AR5416_EEPROM_MODAL_SPURS; i++) {
903 word = swab16(pModal->spurChans[i].spurChan);
904 pModal->spurChans[i].spurChan = word;
905 }
906 }
907 }
908
909 if (sum != 0xffff || ar5416_get_eep_ver(ahp) != AR5416_EEP_VER ||
910 ar5416_get_eep_rev(ahp) < AR5416_EEP_NO_BACK_VER) {
911 HDPRINTF(ah, HAL_DBG_EEPROM,
912 "Bad EEPROM checksum 0x%x or revision 0x%04x\n",
913 sum, ar5416_get_eep_ver(ahp));
914 return HAL_EEBADSUM;
915 }
916
917 return HAL_OK;
918 }
919
920 static enum hal_bool ath9k_hw_chip_test(struct ath_hal *ah)
921 {
922 u_int32_t regAddr[2] = { AR_STA_ID0, AR_PHY_BASE + (8 << 2) };
923 u_int32_t regHold[2];
924 u_int32_t patternData[4] = { 0x55555555,
925 0xaaaaaaaa,
926 0x66666666,
927 0x99999999 };
928 int i, j;
929
930 for (i = 0; i < 2; i++) {
931 u_int32_t addr = regAddr[i];
932 u_int32_t wrData, rdData;
933
934 regHold[i] = REG_READ(ah, addr);
935 for (j = 0; j < 0x100; j++) {
936 wrData = (j << 16) | j;
937 REG_WRITE(ah, addr, wrData);
938 rdData = REG_READ(ah, addr);
939 if (rdData != wrData) {
940 HDPRINTF(ah, HAL_DBG_REG_IO,
941 "%s: address test failed "
942 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
943 __func__, addr, wrData, rdData);
944 return AH_FALSE;
945 }
946 }
947 for (j = 0; j < 4; j++) {
948 wrData = patternData[j];
949 REG_WRITE(ah, addr, wrData);
950 rdData = REG_READ(ah, addr);
951 if (wrData != rdData) {
952 HDPRINTF(ah, HAL_DBG_REG_IO,
953 "%s: address test failed "
954 "addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
955 __func__, addr, wrData, rdData);
956 return AH_FALSE;
957 }
958 }
959 REG_WRITE(ah, regAddr[i], regHold[i]);
960 }
961 udelay(100);
962 return AH_TRUE;
963 }
964
965 u_int32_t ath9k_hw_getrxfilter(struct ath_hal *ah)
966 {
967 u_int32_t bits = REG_READ(ah, AR_RX_FILTER);
968 u_int32_t phybits = REG_READ(ah, AR_PHY_ERR);
969
970 if (phybits & AR_PHY_ERR_RADAR)
971 bits |= HAL_RX_FILTER_PHYRADAR;
972 if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
973 bits |= HAL_RX_FILTER_PHYERR;
974 return bits;
975 }
976
977 void ath9k_hw_setrxfilter(struct ath_hal *ah, u_int32_t bits)
978 {
979 u_int32_t phybits;
980
981 REG_WRITE(ah, AR_RX_FILTER, (bits & 0xffff) | AR_RX_COMPR_BAR);
982 phybits = 0;
983 if (bits & HAL_RX_FILTER_PHYRADAR)
984 phybits |= AR_PHY_ERR_RADAR;
985 if (bits & HAL_RX_FILTER_PHYERR)
986 phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
987 REG_WRITE(ah, AR_PHY_ERR, phybits);
988
989 if (phybits)
990 REG_WRITE(ah, AR_RXCFG,
991 REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
992 else
993 REG_WRITE(ah, AR_RXCFG,
994 REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_ZLFDMA);
995 }
996
997 enum hal_bool ath9k_hw_setcapability(struct ath_hal *ah,
998 enum hal_capability_type type,
999 u_int32_t capability,
1000 u_int32_t setting,
1001 enum hal_status *status)
1002 {
1003 struct ath_hal_5416 *ahp = AH5416(ah);
1004 u_int32_t v;
1005
1006 switch (type) {
1007 case HAL_CAP_TKIP_MIC:
1008 if (setting)
1009 ahp->ah_staId1Defaults |=
1010 AR_STA_ID1_CRPT_MIC_ENABLE;
1011 else
1012 ahp->ah_staId1Defaults &=
1013 ~AR_STA_ID1_CRPT_MIC_ENABLE;
1014 return AH_TRUE;
1015 case HAL_CAP_DIVERSITY:
1016 v = REG_READ(ah, AR_PHY_CCK_DETECT);
1017 if (setting)
1018 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
1019 else
1020 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
1021 REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
1022 return AH_TRUE;
1023 case HAL_CAP_MCAST_KEYSRCH:
1024 if (setting)
1025 ahp->ah_staId1Defaults |= AR_STA_ID1_MCAST_KSRCH;
1026 else
1027 ahp->ah_staId1Defaults &= ~AR_STA_ID1_MCAST_KSRCH;
1028 return AH_TRUE;
1029 case HAL_CAP_TSF_ADJUST:
1030 if (setting)
1031 ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF;
1032 else
1033 ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF;
1034 return AH_TRUE;
1035 default:
1036 return AH_FALSE;
1037 }
1038 }
1039
1040 void ath9k_hw_dmaRegDump(struct ath_hal *ah)
1041 {
1042 u_int32_t val[ATH9K_NUM_DMA_DEBUG_REGS];
1043 int qcuOffset = 0, dcuOffset = 0;
1044 u_int32_t *qcuBase = &val[0], *dcuBase = &val[4];
1045 int i;
1046
1047 REG_WRITE(ah, AR_MACMISC,
1048 ((AR_MACMISC_DMA_OBS_LINE_8 << AR_MACMISC_DMA_OBS_S) |
1049 (AR_MACMISC_MISC_OBS_BUS_1 <<
1050 AR_MACMISC_MISC_OBS_BUS_MSB_S)));
1051
1052 HDPRINTF(ah, HAL_DBG_REG_IO, "Raw DMA Debug values:\n");
1053 for (i = 0; i < ATH9K_NUM_DMA_DEBUG_REGS; i++) {
1054 if (i % 4 == 0)
1055 HDPRINTF(ah, HAL_DBG_REG_IO, "\n");
1056
1057 val[i] = REG_READ(ah, AR_DMADBG_0 + (i * sizeof(u_int32_t)));
1058 HDPRINTF(ah, HAL_DBG_REG_IO, "%d: %08x ", i, val[i]);
1059 }
1060
1061 HDPRINTF(ah, HAL_DBG_REG_IO, "\n\n");
1062 HDPRINTF(ah, HAL_DBG_REG_IO,
1063 "Num QCU: chain_st fsp_ok fsp_st DCU: chain_st\n");
1064
1065 for (i = 0; i < ATH9K_NUM_QUEUES;
1066 i++, qcuOffset += 4, dcuOffset += 5) {
1067 if (i == 8) {
1068 qcuOffset = 0;
1069 qcuBase++;
1070 }
1071
1072 if (i == 6) {
1073 dcuOffset = 0;
1074 dcuBase++;
1075 }
1076
1077 HDPRINTF(ah, HAL_DBG_REG_IO,
1078 "%2d %2x %1x %2x %2x\n",
1079 i, (*qcuBase & (0x7 << qcuOffset)) >> qcuOffset,
1080 (*qcuBase & (0x8 << qcuOffset)) >> (qcuOffset +
1081 3),
1082 val[2] & (0x7 << (i * 3)) >> (i * 3),
1083 (*dcuBase & (0x1f << dcuOffset)) >> dcuOffset);
1084 }
1085
1086 HDPRINTF(ah, HAL_DBG_REG_IO, "\n");
1087 HDPRINTF(ah, HAL_DBG_REG_IO,
1088 "qcu_stitch state: %2x qcu_fetch state: %2x\n",
1089 (val[3] & 0x003c0000) >> 18, (val[3] & 0x03c00000) >> 22);
1090 HDPRINTF(ah, HAL_DBG_REG_IO,
1091 "qcu_complete state: %2x dcu_complete state: %2x\n",
1092 (val[3] & 0x1c000000) >> 26, (val[6] & 0x3));
1093 HDPRINTF(ah, HAL_DBG_REG_IO,
1094 "dcu_arb state: %2x dcu_fp state: %2x\n",
1095 (val[5] & 0x06000000) >> 25, (val[5] & 0x38000000) >> 27);
1096 HDPRINTF(ah, HAL_DBG_REG_IO,
1097 "chan_idle_dur: %3d chan_idle_dur_valid: %1d\n",
1098 (val[6] & 0x000003fc) >> 2, (val[6] & 0x00000400) >> 10);
1099 HDPRINTF(ah, HAL_DBG_REG_IO,
1100 "txfifo_valid_0: %1d txfifo_valid_1: %1d\n",
1101 (val[6] & 0x00000800) >> 11, (val[6] & 0x00001000) >> 12);
1102 HDPRINTF(ah, HAL_DBG_REG_IO,
1103 "txfifo_dcu_num_0: %2d txfifo_dcu_num_1: %2d\n",
1104 (val[6] & 0x0001e000) >> 13, (val[6] & 0x001e0000) >> 17);
1105
1106 HDPRINTF(ah, HAL_DBG_REG_IO, "pcu observe 0x%x \n",
1107 REG_READ(ah, AR_OBS_BUS_1));
1108 HDPRINTF(ah, HAL_DBG_REG_IO, "AR_CR 0x%x \n", REG_READ(ah, AR_CR));
1109 }
1110
1111 u_int32_t ath9k_hw_GetMibCycleCountsPct(struct ath_hal *ah,
1112 u_int32_t *rxc_pcnt,
1113 u_int32_t *rxf_pcnt,
1114 u_int32_t *txf_pcnt)
1115 {
1116 static u_int32_t cycles, rx_clear, rx_frame, tx_frame;
1117 u_int32_t good = 1;
1118
1119 u_int32_t rc = REG_READ(ah, AR_RCCNT);
1120 u_int32_t rf = REG_READ(ah, AR_RFCNT);
1121 u_int32_t tf = REG_READ(ah, AR_TFCNT);
1122 u_int32_t cc = REG_READ(ah, AR_CCCNT);
1123
1124 if (cycles == 0 || cycles > cc) {
1125 HDPRINTF(ah, HAL_DBG_CHANNEL,
1126 "%s: cycle counter wrap. ExtBusy = 0\n",
1127 __func__);
1128 good = 0;
1129 } else {
1130 u_int32_t cc_d = cc - cycles;
1131 u_int32_t rc_d = rc - rx_clear;
1132 u_int32_t rf_d = rf - rx_frame;
1133 u_int32_t tf_d = tf - tx_frame;
1134
1135 if (cc_d != 0) {
1136 *rxc_pcnt = rc_d * 100 / cc_d;
1137 *rxf_pcnt = rf_d * 100 / cc_d;
1138 *txf_pcnt = tf_d * 100 / cc_d;
1139 } else {
1140 good = 0;
1141 }
1142 }
1143
1144 cycles = cc;
1145 rx_frame = rf;
1146 rx_clear = rc;
1147 tx_frame = tf;
1148
1149 return good;
1150 }
1151
1152 void ath9k_hw_set11nmac2040(struct ath_hal *ah, enum hal_ht_macmode mode)
1153 {
1154 u_int32_t macmode;
1155
1156 if (mode == HAL_HT_MACMODE_2040 &&
1157 !ah->ah_config.ath_hal_cwmIgnoreExtCCA)
1158 macmode = AR_2040_JOINED_RX_CLEAR;
1159 else
1160 macmode = 0;
1161
1162 REG_WRITE(ah, AR_2040_MODE, macmode);
1163 }
1164
1165 static void ath9k_hw_mark_phy_inactive(struct ath_hal *ah)
1166 {
1167 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS);
1168 }
1169
1170
1171 static struct ath_hal_5416 *ath9k_hw_newstate(u_int16_t devid, void *sc,
1172 void __iomem *mem,
1173 enum hal_status *status)
1174 {
1175 static const u_int8_t defbssidmask[ETH_ALEN] =
1176 { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1177 struct ath_hal_5416 *ahp;
1178 struct ath_hal *ah;
1179
1180 ahp = kzalloc(sizeof(struct ath_hal_5416), GFP_KERNEL);
1181 if (ahp == NULL) {
1182 HDPRINTF(NULL, HAL_DBG_UNMASKABLE,
1183 "%s: cannot allocate memory for state block\n",
1184 __func__);
1185 *status = HAL_ENOMEM;
1186 return NULL;
1187 }
1188
1189 ah = &ahp->ah;
1190
1191 memcpy(&ahp->ah, &ar5416hal, sizeof(struct ath_hal));
1192
1193 ah->ah_sc = sc;
1194 ah->ah_sh = mem;
1195
1196 ah->ah_devid = devid;
1197 ah->ah_subvendorid = 0;
1198
1199 ah->ah_flags = 0;
1200 if ((devid == AR5416_AR9100_DEVID))
1201 ah->ah_macVersion = AR_SREV_VERSION_9100;
1202 if (!AR_SREV_9100(ah))
1203 ah->ah_flags = AH_USE_EEPROM;
1204
1205 ah->ah_powerLimit = MAX_RATE_POWER;
1206 ah->ah_tpScale = HAL_TP_SCALE_MAX;
1207
1208 ahp->ah_atimWindow = 0;
1209 ahp->ah_diversityControl = ah->ah_config.ath_hal_diversityControl;
1210 ahp->ah_antennaSwitchSwap =
1211 ah->ah_config.ath_hal_antennaSwitchSwap;
1212
1213 ahp->ah_staId1Defaults = AR_STA_ID1_CRPT_MIC_ENABLE;
1214 ahp->ah_beaconInterval = 100;
1215 ahp->ah_enable32kHzClock = DONT_USE_32KHZ;
1216 ahp->ah_slottime = (u_int) -1;
1217 ahp->ah_acktimeout = (u_int) -1;
1218 ahp->ah_ctstimeout = (u_int) -1;
1219 ahp->ah_globaltxtimeout = (u_int) -1;
1220 memcpy(&ahp->ah_bssidmask, defbssidmask, ETH_ALEN);
1221
1222 ahp->ah_gBeaconRate = 0;
1223
1224 return ahp;
1225 }
1226
1227 static enum hal_status ath9k_hw_eeprom_attach(struct ath_hal *ah)
1228 {
1229 enum hal_status status;
1230
1231 if (ath9k_hw_use_flash(ah))
1232 ath9k_hw_flash_map(ah);
1233
1234 if (!ath9k_hw_fill_eeprom(ah))
1235 return HAL_EIO;
1236
1237 status = ath9k_hw_check_eeprom(ah);
1238
1239 return status;
1240 }
1241
1242 u_int32_t ath9k_hw_get_eeprom(struct ath_hal_5416 *ahp,
1243 enum eeprom_param param)
1244 {
1245 struct ar5416_eeprom *eep = &ahp->ah_eeprom;
1246 struct modal_eep_header *pModal = eep->modalHeader;
1247 struct base_eep_header *pBase = &eep->baseEepHeader;
1248
1249 switch (param) {
1250 case EEP_NFTHRESH_5:
1251 return -pModal[0].noiseFloorThreshCh[0];
1252 case EEP_NFTHRESH_2:
1253 return -pModal[1].noiseFloorThreshCh[0];
1254 case AR_EEPROM_MAC(0):
1255 return pBase->macAddr[0] << 8 | pBase->macAddr[1];
1256 case AR_EEPROM_MAC(1):
1257 return pBase->macAddr[2] << 8 | pBase->macAddr[3];
1258 case AR_EEPROM_MAC(2):
1259 return pBase->macAddr[4] << 8 | pBase->macAddr[5];
1260 case EEP_REG_0:
1261 return pBase->regDmn[0];
1262 case EEP_REG_1:
1263 return pBase->regDmn[1];
1264 case EEP_OP_CAP:
1265 return pBase->deviceCap;
1266 case EEP_OP_MODE:
1267 return pBase->opCapFlags;
1268 case EEP_RF_SILENT:
1269 return pBase->rfSilent;
1270 case EEP_OB_5:
1271 return pModal[0].ob;
1272 case EEP_DB_5:
1273 return pModal[0].db;
1274 case EEP_OB_2:
1275 return pModal[1].ob;
1276 case EEP_DB_2:
1277 return pModal[1].db;
1278 case EEP_MINOR_REV:
1279 return pBase->version & AR5416_EEP_VER_MINOR_MASK;
1280 case EEP_TX_MASK:
1281 return pBase->txMask;
1282 case EEP_RX_MASK:
1283 return pBase->rxMask;
1284 default:
1285 return 0;
1286 }
1287 }
1288
1289 static inline int ath9k_hw_get_radiorev(struct ath_hal *ah)
1290 {
1291 u_int32_t val;
1292 int i;
1293
1294 REG_WRITE(ah, AR_PHY(0x36), 0x00007058);
1295 for (i = 0; i < 8; i++)
1296 REG_WRITE(ah, AR_PHY(0x20), 0x00010000);
1297 val = (REG_READ(ah, AR_PHY(256)) >> 24) & 0xff;
1298 val = ((val & 0xf0) >> 4) | ((val & 0x0f) << 4);
1299 return ath9k_hw_reverse_bits(val, 8);
1300 }
1301
1302 static inline enum hal_status ath9k_hw_init_macaddr(struct ath_hal *ah)
1303 {
1304 u_int32_t sum;
1305 int i;
1306 u_int16_t eeval;
1307 struct ath_hal_5416 *ahp = AH5416(ah);
1308 DECLARE_MAC_BUF(mac);
1309
1310 sum = 0;
1311 for (i = 0; i < 3; i++) {
1312 eeval = ath9k_hw_get_eeprom(ahp, AR_EEPROM_MAC(i));
1313 sum += eeval;
1314 ahp->ah_macaddr[2 * i] = eeval >> 8;
1315 ahp->ah_macaddr[2 * i + 1] = eeval & 0xff;
1316 }
1317 if (sum == 0 || sum == 0xffff * 3) {
1318 HDPRINTF(ah, HAL_DBG_EEPROM,
1319 "%s: mac address read failed: %s\n", __func__,
1320 print_mac(mac, ahp->ah_macaddr));
1321 return HAL_EEBADMAC;
1322 }
1323
1324 return HAL_OK;
1325 }
1326
1327 static inline int16_t ath9k_hw_interpolate(u_int16_t target,
1328 u_int16_t srcLeft,
1329 u_int16_t srcRight,
1330 int16_t targetLeft,
1331 int16_t targetRight)
1332 {
1333 int16_t rv;
1334
1335 if (srcRight == srcLeft) {
1336 rv = targetLeft;
1337 } else {
1338 rv = (int16_t) (((target - srcLeft) * targetRight +
1339 (srcRight - target) * targetLeft) /
1340 (srcRight - srcLeft));
1341 }
1342 return rv;
1343 }
1344
1345 static inline u_int16_t ath9k_hw_fbin2freq(u_int8_t fbin,
1346 enum hal_bool is2GHz)
1347 {
1348
1349 if (fbin == AR5416_BCHAN_UNUSED)
1350 return fbin;
1351
1352 return (u_int16_t) ((is2GHz) ? (2300 + fbin) : (4800 + 5 * fbin));
1353 }
1354
1355 static u_int16_t ath9k_hw_eeprom_get_spur_chan(struct ath_hal *ah,
1356 u_int16_t i,
1357 enum hal_bool is2GHz)
1358 {
1359 struct ath_hal_5416 *ahp = AH5416(ah);
1360 struct ar5416_eeprom *eep =
1361 (struct ar5416_eeprom *) &ahp->ah_eeprom;
1362 u_int16_t spur_val = AR_NO_SPUR;
1363
1364 HDPRINTF(ah, HAL_DBG_ANI,
1365 "Getting spur idx %d is2Ghz. %d val %x\n",
1366 i, is2GHz, ah->ah_config.ath_hal_spurChans[i][is2GHz]);
1367
1368 switch (ah->ah_config.ath_hal_spurMode) {
1369 case SPUR_DISABLE:
1370 break;
1371 case SPUR_ENABLE_IOCTL:
1372 spur_val = ah->ah_config.ath_hal_spurChans[i][is2GHz];
1373 HDPRINTF(ah, HAL_DBG_ANI,
1374 "Getting spur val from new loc. %d\n", spur_val);
1375 break;
1376 case SPUR_ENABLE_EEPROM:
1377 spur_val = eep->modalHeader[is2GHz].spurChans[i].spurChan;
1378 break;
1379
1380 }
1381 return spur_val;
1382 }
1383
1384 static inline enum hal_status ath9k_hw_rfattach(struct ath_hal *ah)
1385 {
1386 enum hal_bool rfStatus = AH_FALSE;
1387 enum hal_status ecode = HAL_OK;
1388
1389 rfStatus = ath9k_hw_init_rf(ah, &ecode);
1390 if (!rfStatus) {
1391 HDPRINTF(ah, HAL_DBG_RESET,
1392 "%s: RF setup failed, status %u\n", __func__,
1393 ecode);
1394 return ecode;
1395 }
1396
1397 return HAL_OK;
1398 }
1399
1400 static enum hal_status ath9k_hw_rf_claim(struct ath_hal *ah)
1401 {
1402 u_int32_t val;
1403
1404 REG_WRITE(ah, AR_PHY(0), 0x00000007);
1405
1406 val = ath9k_hw_get_radiorev(ah);
1407 switch (val & AR_RADIO_SREV_MAJOR) {
1408 case 0:
1409 val = AR_RAD5133_SREV_MAJOR;
1410 break;
1411 case AR_RAD5133_SREV_MAJOR:
1412 case AR_RAD5122_SREV_MAJOR:
1413 case AR_RAD2133_SREV_MAJOR:
1414 case AR_RAD2122_SREV_MAJOR:
1415 break;
1416 default:
1417 HDPRINTF(ah, HAL_DBG_CHANNEL,
1418 "%s: 5G Radio Chip Rev 0x%02X is not "
1419 "supported by this driver\n",
1420 __func__, ah->ah_analog5GhzRev);
1421 return HAL_ENOTSUPP;
1422 }
1423
1424 ah->ah_analog5GhzRev = val;
1425
1426 return HAL_OK;
1427 }
1428
1429 static inline void ath9k_hw_init_pll(struct ath_hal *ah,
1430 struct hal_channel *chan)
1431 {
1432 u_int32_t pll;
1433
1434 if (AR_SREV_9100(ah)) {
1435 if (chan && IS_CHAN_5GHZ(chan))
1436 pll = 0x1450;
1437 else
1438 pll = 0x1458;
1439 } else {
1440 if (AR_SREV_9280_10_OR_LATER(ah)) {
1441 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1442
1443 if (chan && IS_CHAN_HALF_RATE(chan))
1444 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1445 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1446 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1447
1448 if (chan && IS_CHAN_5GHZ(chan)) {
1449 pll |= SM(0x28, AR_RTC_9160_PLL_DIV);
1450
1451
1452 if (AR_SREV_9280_20(ah)) {
1453 if (((chan->channel % 20) == 0)
1454 || ((chan->channel % 10) == 0))
1455 pll = 0x2850;
1456 else
1457 pll = 0x142c;
1458 }
1459 } else {
1460 pll |= SM(0x2c, AR_RTC_9160_PLL_DIV);
1461 }
1462
1463 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
1464
1465 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV);
1466
1467 if (chan && IS_CHAN_HALF_RATE(chan))
1468 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL);
1469 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1470 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL);
1471
1472 if (chan && IS_CHAN_5GHZ(chan))
1473 pll |= SM(0x50, AR_RTC_9160_PLL_DIV);
1474 else
1475 pll |= SM(0x58, AR_RTC_9160_PLL_DIV);
1476 } else {
1477 pll = AR_RTC_PLL_REFDIV_5 | AR_RTC_PLL_DIV2;
1478
1479 if (chan && IS_CHAN_HALF_RATE(chan))
1480 pll |= SM(0x1, AR_RTC_PLL_CLKSEL);
1481 else if (chan && IS_CHAN_QUARTER_RATE(chan))
1482 pll |= SM(0x2, AR_RTC_PLL_CLKSEL);
1483
1484 if (chan && IS_CHAN_5GHZ(chan))
1485 pll |= SM(0xa, AR_RTC_PLL_DIV);
1486 else
1487 pll |= SM(0xb, AR_RTC_PLL_DIV);
1488 }
1489 }
1490 REG_WRITE(ah, (u_int16_t) (AR_RTC_PLL_CONTROL), pll);
1491
1492 udelay(RTC_PLL_SETTLE_DELAY);
1493
1494 REG_WRITE(ah, AR_RTC_SLEEP_CLK, AR_RTC_FORCE_DERIVED_CLK);
1495 }
1496
1497 static void ath9k_hw_set_regs(struct ath_hal *ah, struct hal_channel *chan,
1498 enum hal_ht_macmode macmode)
1499 {
1500 u_int32_t phymode;
1501 struct ath_hal_5416 *ahp = AH5416(ah);
1502
1503 phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40
1504 | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH;
1505
1506 if (IS_CHAN_HT40(chan)) {
1507 phymode |= AR_PHY_FC_DYN2040_EN;
1508
1509 if (chan->channelFlags & CHANNEL_HT40PLUS)
1510 phymode |= AR_PHY_FC_DYN2040_PRI_CH;
1511
1512 if (ahp->ah_extprotspacing == HAL_HT_EXTPROTSPACING_25)
1513 phymode |= AR_PHY_FC_DYN2040_EXT_CH;
1514 }
1515 REG_WRITE(ah, AR_PHY_TURBO, phymode);
1516
1517 ath9k_hw_set11nmac2040(ah, macmode);
1518
1519 REG_WRITE(ah, AR_GTXTO, 25 << AR_GTXTO_TIMEOUT_LIMIT_S);
1520 REG_WRITE(ah, AR_CST, 0xF << AR_CST_TIMEOUT_LIMIT_S);
1521 }
1522
1523 static void ath9k_hw_set_operating_mode(struct ath_hal *ah, int opmode)
1524 {
1525 u_int32_t val;
1526
1527 val = REG_READ(ah, AR_STA_ID1);
1528 val &= ~(AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC);
1529 switch (opmode) {
1530 case HAL_M_HOSTAP:
1531 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_STA_AP
1532 | AR_STA_ID1_KSRCH_MODE);
1533 OS_REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1534 break;
1535 case HAL_M_IBSS:
1536 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_ADHOC
1537 | AR_STA_ID1_KSRCH_MODE);
1538 OS_REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1539 break;
1540 case HAL_M_STA:
1541 case HAL_M_MONITOR:
1542 REG_WRITE(ah, AR_STA_ID1, val | AR_STA_ID1_KSRCH_MODE);
1543 break;
1544 }
1545 }
1546
1547 static inline void
1548 ath9k_hw_set_rfmode(struct ath_hal *ah, struct hal_channel *chan)
1549 {
1550 u_int32_t rfMode = 0;
1551
1552 if (chan == NULL)
1553 return;
1554
1555 rfMode |= (IS_CHAN_B(chan) || IS_CHAN_G(chan))
1556 ? AR_PHY_MODE_DYNAMIC : AR_PHY_MODE_OFDM;
1557
1558 if (!AR_SREV_9280_10_OR_LATER(ah))
1559 rfMode |= (IS_CHAN_5GHZ(chan)) ? AR_PHY_MODE_RF5GHZ :
1560 AR_PHY_MODE_RF2GHZ;
1561
1562 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan))
1563 rfMode |= (AR_PHY_MODE_DYNAMIC | AR_PHY_MODE_DYN_CCK_DISABLE);
1564
1565 REG_WRITE(ah, AR_PHY_MODE, rfMode);
1566 }
1567
1568 static enum hal_bool ath9k_hw_set_reset(struct ath_hal *ah, int type)
1569 {
1570 u_int32_t rst_flags;
1571 u_int32_t tmpReg;
1572
1573 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1574 AR_RTC_FORCE_WAKE_ON_INT);
1575
1576 if (AR_SREV_9100(ah)) {
1577 rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1578 AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1579 } else {
1580 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
1581 if (tmpReg &
1582 (AR_INTR_SYNC_LOCAL_TIMEOUT |
1583 AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
1584 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
1585 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
1586 } else {
1587 REG_WRITE(ah, AR_RC, AR_RC_AHB);
1588 }
1589
1590 rst_flags = AR_RTC_RC_MAC_WARM;
1591 if (type == HAL_RESET_COLD)
1592 rst_flags |= AR_RTC_RC_MAC_COLD;
1593 }
1594
1595 REG_WRITE(ah, (u_int16_t) (AR_RTC_RC), rst_flags);
1596 udelay(50);
1597
1598 REG_WRITE(ah, (u_int16_t) (AR_RTC_RC), 0);
1599 if (!ath9k_hw_wait(ah, (u_int16_t) (AR_RTC_RC), AR_RTC_RC_M, 0)) {
1600 HDPRINTF(ah, HAL_DBG_RESET, "%s: RTC stuck in MAC reset\n",
1601 __func__);
1602 return AH_FALSE;
1603 }
1604
1605 if (!AR_SREV_9100(ah))
1606 REG_WRITE(ah, AR_RC, 0);
1607
1608 ath9k_hw_init_pll(ah, NULL);
1609
1610 if (AR_SREV_9100(ah))
1611 udelay(50);
1612
1613 return AH_TRUE;
1614 }
1615
1616 static inline enum hal_bool ath9k_hw_set_reset_power_on(struct ath_hal *ah)
1617 {
1618 REG_WRITE(ah, AR_RTC_FORCE_WAKE, AR_RTC_FORCE_WAKE_EN |
1619 AR_RTC_FORCE_WAKE_ON_INT);
1620
1621 REG_WRITE(ah, (u_int16_t) (AR_RTC_RESET), 0);
1622 REG_WRITE(ah, (u_int16_t) (AR_RTC_RESET), 1);
1623
1624 if (!ath9k_hw_wait(ah,
1625 AR_RTC_STATUS,
1626 AR_RTC_STATUS_M,
1627 AR_RTC_STATUS_ON)) {
1628 HDPRINTF(ah, HAL_DBG_RESET, "%s: RTC not waking up\n",
1629 __func__);
1630 return AH_FALSE;
1631 }
1632
1633 ath9k_hw_read_revisions(ah);
1634
1635 return ath9k_hw_set_reset(ah, HAL_RESET_WARM);
1636 }
1637
1638 static enum hal_bool ath9k_hw_set_reset_reg(struct ath_hal *ah,
1639 u_int32_t type)
1640 {
1641 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
1642 AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1643
1644 switch (type) {
1645 case HAL_RESET_POWER_ON:
1646 return ath9k_hw_set_reset_power_on(ah);
1647 break;
1648 case HAL_RESET_WARM:
1649 case HAL_RESET_COLD:
1650 return ath9k_hw_set_reset(ah, type);
1651 break;
1652 default:
1653 return AH_FALSE;
1654 }
1655 }
1656
1657 static inline struct hal_channel_internal *ath9k_hw_check_chan(
1658 struct ath_hal *ah, struct hal_channel *chan)
1659 {
1660 if ((IS(chan, CHANNEL_2GHZ) ^ IS(chan, CHANNEL_5GHZ)) == 0) {
1661 HDPRINTF(ah, HAL_DBG_CHANNEL,
1662 "%s: invalid channel %u/0x%x; not marked as "
1663 "2GHz or 5GHz\n", __func__, chan->channel,
1664 chan->channelFlags);
1665 return NULL;
1666 }
1667
1668 if ((IS(chan, CHANNEL_OFDM)
1669 ^ IS(chan, CHANNEL_CCK)
1670 ^ IS(chan, CHANNEL_HT20)
1671 ^ IS(chan, CHANNEL_HT40PLUS)
1672 ^ IS(chan, CHANNEL_HT40MINUS)) == 0) {
1673 HDPRINTF(ah, HAL_DBG_CHANNEL,
1674 "%s: invalid channel %u/0x%x; not marked as "
1675 "OFDM or CCK or HT20 or HT40PLUS or HT40MINUS\n",
1676 __func__, chan->channel, chan->channelFlags);
1677 return NULL;
1678 }
1679
1680 return ath9k_regd_check_channel(ah, chan);
1681 }
1682
1683 static inline enum hal_bool
1684 ath9k_hw_get_lower_upper_index(u_int8_t target,
1685 u_int8_t *pList,
1686 u_int16_t listSize,
1687 u_int16_t *indexL,
1688 u_int16_t *indexR)
1689 {
1690 u_int16_t i;
1691
1692 if (target <= pList[0]) {
1693 *indexL = *indexR = 0;
1694 return AH_TRUE;
1695 }
1696 if (target >= pList[listSize - 1]) {
1697 *indexL = *indexR = (u_int16_t) (listSize - 1);
1698 return AH_TRUE;
1699 }
1700
1701 for (i = 0; i < listSize - 1; i++) {
1702 if (pList[i] == target) {
1703 *indexL = *indexR = i;
1704 return AH_TRUE;
1705 }
1706 if (target < pList[i + 1]) {
1707 *indexL = i;
1708 *indexR = (u_int16_t) (i + 1);
1709 return AH_FALSE;
1710 }
1711 }
1712 return AH_FALSE;
1713 }
1714
1715 static int16_t ath9k_hw_get_nf_hist_mid(int16_t *nfCalBuffer)
1716 {
1717 int16_t nfval;
1718 int16_t sort[HAL_NF_CAL_HIST_MAX];
1719 int i, j;
1720
1721 for (i = 0; i < HAL_NF_CAL_HIST_MAX; i++)
1722 sort[i] = nfCalBuffer[i];
1723
1724 for (i = 0; i < HAL_NF_CAL_HIST_MAX - 1; i++) {
1725 for (j = 1; j < HAL_NF_CAL_HIST_MAX - i; j++) {
1726 if (sort[j] > sort[j - 1]) {
1727 nfval = sort[j];
1728 sort[j] = sort[j - 1];
1729 sort[j - 1] = nfval;
1730 }
1731 }
1732 }
1733 nfval = sort[(HAL_NF_CAL_HIST_MAX - 1) >> 1];
1734
1735 return nfval;
1736 }
1737
1738 static void ath9k_hw_update_nfcal_hist_buffer(struct hal_nfcal_hist *h,
1739 int16_t *nfarray)
1740 {
1741 int i;
1742
1743 for (i = 0; i < NUM_NF_READINGS; i++) {
1744 h[i].nfCalBuffer[h[i].currIndex] = nfarray[i];
1745
1746 if (++h[i].currIndex >= HAL_NF_CAL_HIST_MAX)
1747 h[i].currIndex = 0;
1748
1749 if (h[i].invalidNFcount > 0) {
1750 if (nfarray[i] < AR_PHY_CCA_MIN_BAD_VALUE
1751 || nfarray[i] > AR_PHY_CCA_MAX_HIGH_VALUE) {
1752 h[i].invalidNFcount = HAL_NF_CAL_HIST_MAX;
1753 } else {
1754 h[i].invalidNFcount--;
1755 h[i].privNF = nfarray[i];
1756 }
1757 } else {
1758 h[i].privNF =
1759 ath9k_hw_get_nf_hist_mid(h[i].nfCalBuffer);
1760 }
1761 }
1762 return;
1763 }
1764
1765 static void ar5416GetNoiseFloor(struct ath_hal *ah,
1766 int16_t nfarray[NUM_NF_READINGS])
1767 {
1768 int16_t nf;
1769
1770 if (AR_SREV_9280_10_OR_LATER(ah))
1771 nf = MS(REG_READ(ah, AR_PHY_CCA), AR9280_PHY_MINCCA_PWR);
1772 else
1773 nf = MS(REG_READ(ah, AR_PHY_CCA), AR_PHY_MINCCA_PWR);
1774
1775 if (nf & 0x100)
1776 nf = 0 - ((nf ^ 0x1ff) + 1);
1777 HDPRINTF(ah, HAL_DBG_CALIBRATE,
1778 "NF calibrated [ctl] [chain 0] is %d\n", nf);
1779 nfarray[0] = nf;
1780
1781 if (AR_SREV_9280_10_OR_LATER(ah))
1782 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA),
1783 AR9280_PHY_CH1_MINCCA_PWR);
1784 else
1785 nf = MS(REG_READ(ah, AR_PHY_CH1_CCA),
1786 AR_PHY_CH1_MINCCA_PWR);
1787
1788 if (nf & 0x100)
1789 nf = 0 - ((nf ^ 0x1ff) + 1);
1790 HDPRINTF(ah, HAL_DBG_NF_CAL,
1791 "NF calibrated [ctl] [chain 1] is %d\n", nf);
1792 nfarray[1] = nf;
1793
1794 if (!AR_SREV_9280(ah)) {
1795 nf = MS(REG_READ(ah, AR_PHY_CH2_CCA),
1796 AR_PHY_CH2_MINCCA_PWR);
1797 if (nf & 0x100)
1798 nf = 0 - ((nf ^ 0x1ff) + 1);
1799 HDPRINTF(ah, HAL_DBG_NF_CAL,
1800 "NF calibrated [ctl] [chain 2] is %d\n", nf);
1801 nfarray[2] = nf;
1802 }
1803
1804 if (AR_SREV_9280_10_OR_LATER(ah))
1805 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA),
1806 AR9280_PHY_EXT_MINCCA_PWR);
1807 else
1808 nf = MS(REG_READ(ah, AR_PHY_EXT_CCA),
1809 AR_PHY_EXT_MINCCA_PWR);
1810
1811 if (nf & 0x100)
1812 nf = 0 - ((nf ^ 0x1ff) + 1);
1813 HDPRINTF(ah, HAL_DBG_NF_CAL,
1814 "NF calibrated [ext] [chain 0] is %d\n", nf);
1815 nfarray[3] = nf;
1816
1817 if (AR_SREV_9280_10_OR_LATER(ah))
1818 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA),
1819 AR9280_PHY_CH1_EXT_MINCCA_PWR);
1820 else
1821 nf = MS(REG_READ(ah, AR_PHY_CH1_EXT_CCA),
1822 AR_PHY_CH1_EXT_MINCCA_PWR);
1823
1824 if (nf & 0x100)
1825 nf = 0 - ((nf ^ 0x1ff) + 1);
1826 HDPRINTF(ah, HAL_DBG_CALIBRATE,
1827 "NF calibrated [ext] [chain 1] is %d\n", nf);
1828 nfarray[4] = nf;
1829
1830 if (!AR_SREV_9280(ah)) {
1831 nf = MS(REG_READ(ah, AR_PHY_CH2_EXT_CCA),
1832 AR_PHY_CH2_EXT_MINCCA_PWR);
1833 if (nf & 0x100)
1834 nf = 0 - ((nf ^ 0x1ff) + 1);
1835 HDPRINTF(ah, HAL_DBG_NF_CAL,
1836 "NF calibrated [ext] [chain 2] is %d\n", nf);
1837 nfarray[5] = nf;
1838 }
1839 }
1840
1841 static enum hal_bool
1842 getNoiseFloorThresh(struct ath_hal *ah,
1843 const struct hal_channel_internal *chan,
1844 int16_t *nft)
1845 {
1846 struct ath_hal_5416 *ahp = AH5416(ah);
1847
1848 switch (chan->channelFlags & CHANNEL_ALL) {
1849 case CHANNEL_A:
1850 case CHANNEL_A_HT20:
1851 case CHANNEL_A_HT40PLUS:
1852 case CHANNEL_A_HT40MINUS:
1853 *nft = (int16_t) ath9k_hw_get_eeprom(ahp, EEP_NFTHRESH_5);
1854 break;
1855 case CHANNEL_B:
1856 case CHANNEL_G:
1857 case CHANNEL_G_HT20:
1858 case CHANNEL_G_HT40PLUS:
1859 case CHANNEL_G_HT40MINUS:
1860 *nft = (int16_t) ath9k_hw_get_eeprom(ahp, EEP_NFTHRESH_2);
1861 break;
1862 default:
1863 HDPRINTF(ah, HAL_DBG_CHANNEL,
1864 "%s: invalid channel flags 0x%x\n", __func__,
1865 chan->channelFlags);
1866 return AH_FALSE;
1867 }
1868 return AH_TRUE;
1869 }
1870
1871 static void ath9k_hw_start_nfcal(struct ath_hal *ah)
1872 {
1873 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
1874 AR_PHY_AGC_CONTROL_ENABLE_NF);
1875 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL,
1876 AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
1877 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
1878 }
1879
1880 static void
1881 ath9k_hw_loadnf(struct ath_hal *ah, struct hal_channel_internal *chan)
1882 {
1883 struct hal_nfcal_hist *h;
1884 int i, j;
1885 int32_t val;
1886 const u_int32_t ar5416_cca_regs[6] = {
1887 AR_PHY_CCA,
1888 AR_PHY_CH1_CCA,
1889 AR_PHY_CH2_CCA,
1890 AR_PHY_EXT_CCA,
1891 AR_PHY_CH1_EXT_CCA,
1892 AR_PHY_CH2_EXT_CCA
1893 };
1894 u_int8_t chainmask;
1895
1896 if (AR_SREV_9280(ah))
1897 chainmask = 0x1B;
1898 else
1899 chainmask = 0x3F;
1900
1901 #ifdef ATH_NF_PER_CHAN
1902 h = chan->nfCalHist;
1903 #else
1904 h = ah->nfCalHist;
1905 #endif
1906
1907 for (i = 0; i < NUM_NF_READINGS; i++) {
1908 if (chainmask & (1 << i)) {
1909 val = REG_READ(ah, ar5416_cca_regs[i]);
1910 val &= 0xFFFFFE00;
1911 val |= (((u_int32_t) (h[i].privNF) << 1) & 0x1ff);
1912 REG_WRITE(ah, ar5416_cca_regs[i], val);
1913 }
1914 }
1915
1916 OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
1917 AR_PHY_AGC_CONTROL_ENABLE_NF);
1918 OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL,
1919 AR_PHY_AGC_CONTROL_NO_UPDATE_NF);
1920 OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_NF);
1921
1922 for (j = 0; j < 1000; j++) {
1923 if ((REG_READ(ah, AR_PHY_AGC_CONTROL) &
1924 AR_PHY_AGC_CONTROL_NF) == 0)
1925 break;
1926 udelay(10);
1927 }
1928
1929 for (i = 0; i < NUM_NF_READINGS; i++) {
1930 if (chainmask & (1 << i)) {
1931 val = REG_READ(ah, ar5416_cca_regs[i]);
1932 val &= 0xFFFFFE00;
1933 val |= (((u_int32_t) (-50) << 1) & 0x1ff);
1934 REG_WRITE(ah, ar5416_cca_regs[i], val);
1935 }
1936 }
1937 }
1938
1939 static int16_t ath9k_hw_getnf(struct ath_hal *ah,
1940 struct hal_channel_internal *chan)
1941 {
1942 int16_t nf, nfThresh;
1943 int16_t nfarray[NUM_NF_READINGS] = { 0 };
1944 struct hal_nfcal_hist *h;
1945 u_int8_t chainmask;
1946
1947 if (AR_SREV_9280(ah))
1948 chainmask = 0x1B;
1949 else
1950 chainmask = 0x3F;
1951
1952 chan->channelFlags &= (~CHANNEL_CW_INT);
1953 if (REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF) {
1954 HDPRINTF(ah, HAL_DBG_CALIBRATE,
1955 "%s: NF did not complete in calibration window\n",
1956 __func__);
1957 nf = 0;
1958 chan->rawNoiseFloor = nf;
1959 return chan->rawNoiseFloor;
1960 } else {
1961 ar5416GetNoiseFloor(ah, nfarray);
1962 nf = nfarray[0];
1963 if (getNoiseFloorThresh(ah, chan, &nfThresh)
1964 && nf > nfThresh) {
1965 HDPRINTF(ah, HAL_DBG_CALIBRATE,
1966 "%s: noise floor failed detected; "
1967 "detected %d, threshold %d\n", __func__,
1968 nf, nfThresh);
1969 chan->channelFlags |= CHANNEL_CW_INT;
1970 }
1971 }
1972
1973 #ifdef ATH_NF_PER_CHAN
1974 h = chan->nfCalHist;
1975 #else
1976 h = ah->nfCalHist;
1977 #endif
1978
1979 ath9k_hw_update_nfcal_hist_buffer(h, nfarray);
1980 chan->rawNoiseFloor = h[0].privNF;
1981
1982 return chan->rawNoiseFloor;
1983 }
1984
1985 static void ath9k_hw_update_mibstats(struct ath_hal *ah,
1986 struct hal_mib_stats *stats)
1987 {
1988 stats->ackrcv_bad += REG_READ(ah, AR_ACK_FAIL);
1989 stats->rts_bad += REG_READ(ah, AR_RTS_FAIL);
1990 stats->fcs_bad += REG_READ(ah, AR_FCS_FAIL);
1991 stats->rts_good += REG_READ(ah, AR_RTS_OK);
1992 stats->beacons += REG_READ(ah, AR_BEACON_CNT);
1993 }
1994
1995 static void ath9k_enable_mib_counters(struct ath_hal *ah)
1996 {
1997 struct ath_hal_5416 *ahp = AH5416(ah);
1998
1999 HDPRINTF(ah, HAL_DBG_ANI, "Enable mib counters\n");
2000
2001 ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats);
2002
2003 REG_WRITE(ah, AR_FILT_OFDM, 0);
2004 REG_WRITE(ah, AR_FILT_CCK, 0);
2005 REG_WRITE(ah, AR_MIBC,
2006 ~(AR_MIBC_COW | AR_MIBC_FMC | AR_MIBC_CMC | AR_MIBC_MCS)
2007 & 0x0f);
2008 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
2009 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
2010 }
2011
2012 static void ath9k_hw_disable_mib_counters(struct ath_hal *ah)
2013 {
2014 struct ath_hal_5416 *ahp = AH5416(ah);
2015
2016 HDPRINTF(ah, HAL_DBG_ANI, "Disabling MIB counters\n");
2017
2018 REG_WRITE(ah, AR_MIBC, AR_MIBC_FMC | AR_MIBC_CMC);
2019
2020 ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats);
2021
2022 REG_WRITE(ah, AR_FILT_OFDM, 0);
2023 REG_WRITE(ah, AR_FILT_CCK, 0);
2024 }
2025
2026 static int ath9k_hw_get_ani_channel_idx(struct ath_hal *ah,
2027 struct hal_channel_internal *chan)
2028 {
2029 struct ath_hal_5416 *ahp = AH5416(ah);
2030 int i;
2031
2032 for (i = 0; i < ARRAY_SIZE(ahp->ah_ani); i++) {
2033 if (ahp->ah_ani[i].c.channel == chan->channel)
2034 return i;
2035 if (ahp->ah_ani[i].c.channel == 0) {
2036 ahp->ah_ani[i].c.channel = chan->channel;
2037 ahp->ah_ani[i].c.channelFlags = chan->channelFlags;
2038 return i;
2039 }
2040 }
2041
2042 HDPRINTF(ah, HAL_DBG_ANI,
2043 "No more channel states left. Using channel 0\n");
2044 return 0;
2045 }
2046
2047 static void ath9k_hw_ani_attach(struct ath_hal *ah)
2048 {
2049 struct ath_hal_5416 *ahp = AH5416(ah);
2050 int i;
2051
2052 ahp->ah_hasHwPhyCounters = 1;
2053
2054 memset(ahp->ah_ani, 0, sizeof(ahp->ah_ani));
2055 for (i = 0; i < ARRAY_SIZE(ahp->ah_ani); i++) {
2056 ahp->ah_ani[i].ofdmTrigHigh = HAL_ANI_OFDM_TRIG_HIGH;
2057 ahp->ah_ani[i].ofdmTrigLow = HAL_ANI_OFDM_TRIG_LOW;
2058 ahp->ah_ani[i].cckTrigHigh = HAL_ANI_CCK_TRIG_HIGH;
2059 ahp->ah_ani[i].cckTrigLow = HAL_ANI_CCK_TRIG_LOW;
2060 ahp->ah_ani[i].rssiThrHigh = HAL_ANI_RSSI_THR_HIGH;
2061 ahp->ah_ani[i].rssiThrLow = HAL_ANI_RSSI_THR_LOW;
2062 ahp->ah_ani[i].ofdmWeakSigDetectOff =
2063 !HAL_ANI_USE_OFDM_WEAK_SIG;
2064 ahp->ah_ani[i].cckWeakSigThreshold =
2065 HAL_ANI_CCK_WEAK_SIG_THR;
2066 ahp->ah_ani[i].spurImmunityLevel = HAL_ANI_SPUR_IMMUNE_LVL;
2067 ahp->ah_ani[i].firstepLevel = HAL_ANI_FIRSTEP_LVL;
2068 if (ahp->ah_hasHwPhyCounters) {
2069 ahp->ah_ani[i].ofdmPhyErrBase =
2070 AR_PHY_COUNTMAX - HAL_ANI_OFDM_TRIG_HIGH;
2071 ahp->ah_ani[i].cckPhyErrBase =
2072 AR_PHY_COUNTMAX - HAL_ANI_CCK_TRIG_HIGH;
2073 }
2074 }
2075 if (ahp->ah_hasHwPhyCounters) {
2076 HDPRINTF(ah, HAL_DBG_ANI, "Setting OfdmErrBase = 0x%08x\n",
2077 ahp->ah_ani[0].ofdmPhyErrBase);
2078 HDPRINTF(ah, HAL_DBG_ANI, "Setting cckErrBase = 0x%08x\n",
2079 ahp->ah_ani[0].cckPhyErrBase);
2080
2081 REG_WRITE(ah, AR_PHY_ERR_1, ahp->ah_ani[0].ofdmPhyErrBase);
2082 REG_WRITE(ah, AR_PHY_ERR_2, ahp->ah_ani[0].cckPhyErrBase);
2083 ath9k_enable_mib_counters(ah);
2084 }
2085 ahp->ah_aniPeriod = HAL_ANI_PERIOD;
2086 if (ah->ah_config.ath_hal_enableANI)
2087 ahp->ah_procPhyErr |= HAL_PROCESS_ANI;
2088 }
2089
2090 static inline void ath9k_hw_ani_setup(struct ath_hal *ah)
2091 {
2092 struct ath_hal_5416 *ahp = AH5416(ah);
2093 int i;
2094
2095 const int totalSizeDesired[] = { -55, -55, -55, -55, -62 };
2096 const int coarseHigh[] = { -14, -14, -14, -14, -12 };
2097 const int coarseLow[] = { -64, -64, -64, -64, -70 };
2098 const int firpwr[] = { -78, -78, -78, -78, -80 };
2099
2100 for (i = 0; i < 5; i++) {
2101 ahp->ah_totalSizeDesired[i] = totalSizeDesired[i];
2102 ahp->ah_coarseHigh[i] = coarseHigh[i];
2103 ahp->ah_coarseLow[i] = coarseLow[i];
2104 ahp->ah_firpwr[i] = firpwr[i];
2105 }
2106 }
2107
2108 static void ath9k_hw_ani_detach(struct ath_hal *ah)
2109 {
2110 struct ath_hal_5416 *ahp = AH5416(ah);
2111
2112 HDPRINTF(ah, HAL_DBG_ANI, "Detaching Ani\n");
2113 if (ahp->ah_hasHwPhyCounters) {
2114 ath9k_hw_disable_mib_counters(ah);
2115 REG_WRITE(ah, AR_PHY_ERR_1, 0);
2116 REG_WRITE(ah, AR_PHY_ERR_2, 0);
2117 }
2118 }
2119
2120
2121 static enum hal_bool ath9k_hw_ani_control(struct ath_hal *ah,
2122 enum hal_ani_cmd cmd, int param)
2123 {
2124 struct ath_hal_5416 *ahp = AH5416(ah);
2125 struct ar5416AniState *aniState = ahp->ah_curani;
2126
2127 switch (cmd & ahp->ah_ani_function) {
2128 case HAL_ANI_NOISE_IMMUNITY_LEVEL:{
2129 u_int level = param;
2130
2131 if (level >= ARRAY_SIZE(ahp->ah_totalSizeDesired)) {
2132 HDPRINTF(ah, HAL_DBG_ANI,
2133 "%s: level out of range (%u > %u)\n",
2134 __func__, level,
2135 (unsigned) ARRAY_SIZE(ahp->
2136 ah_totalSizeDesired));
2137 return AH_FALSE;
2138 }
2139
2140 OS_REG_RMW_FIELD(ah, AR_PHY_DESIRED_SZ,
2141 AR_PHY_DESIRED_SZ_TOT_DES,
2142 ahp->ah_totalSizeDesired[level]);
2143 OS_REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
2144 AR_PHY_AGC_CTL1_COARSE_LOW,
2145 ahp->ah_coarseLow[level]);
2146 OS_REG_RMW_FIELD(ah, AR_PHY_AGC_CTL1,
2147 AR_PHY_AGC_CTL1_COARSE_HIGH,
2148 ahp->ah_coarseHigh[level]);
2149 OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
2150 AR_PHY_FIND_SIG_FIRPWR,
2151 ahp->ah_firpwr[level]);
2152
2153 if (level > aniState->noiseImmunityLevel)
2154 ahp->ah_stats.ast_ani_niup++;
2155 else if (level < aniState->noiseImmunityLevel)
2156 ahp->ah_stats.ast_ani_nidown++;
2157 aniState->noiseImmunityLevel = level;
2158 break;
2159 }
2160 case HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION:{
2161 const int m1ThreshLow[] = { 127, 50 };
2162 const int m2ThreshLow[] = { 127, 40 };
2163 const int m1Thresh[] = { 127, 0x4d };
2164 const int m2Thresh[] = { 127, 0x40 };
2165 const int m2CountThr[] = { 31, 16 };
2166 const int m2CountThrLow[] = { 63, 48 };
2167 u_int on = param ? 1 : 0;
2168
2169 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
2170 AR_PHY_SFCORR_LOW_M1_THRESH_LOW,
2171 m1ThreshLow[on]);
2172 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
2173 AR_PHY_SFCORR_LOW_M2_THRESH_LOW,
2174 m2ThreshLow[on]);
2175 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR,
2176 AR_PHY_SFCORR_M1_THRESH,
2177 m1Thresh[on]);
2178 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR,
2179 AR_PHY_SFCORR_M2_THRESH,
2180 m2Thresh[on]);
2181 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR,
2182 AR_PHY_SFCORR_M2COUNT_THR,
2183 m2CountThr[on]);
2184 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_LOW,
2185 AR_PHY_SFCORR_LOW_M2COUNT_THR_LOW,
2186 m2CountThrLow[on]);
2187
2188 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
2189 AR_PHY_SFCORR_EXT_M1_THRESH_LOW,
2190 m1ThreshLow[on]);
2191 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
2192 AR_PHY_SFCORR_EXT_M2_THRESH_LOW,
2193 m2ThreshLow[on]);
2194 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
2195 AR_PHY_SFCORR_EXT_M1_THRESH,
2196 m1Thresh[on]);
2197 OS_REG_RMW_FIELD(ah, AR_PHY_SFCORR_EXT,
2198 AR_PHY_SFCORR_EXT_M2_THRESH,
2199 m2Thresh[on]);
2200
2201 if (on)
2202 OS_REG_SET_BIT(ah, AR_PHY_SFCORR_LOW,
2203 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
2204 else
2205 OS_REG_CLR_BIT(ah, AR_PHY_SFCORR_LOW,
2206 AR_PHY_SFCORR_LOW_USE_SELF_CORR_LOW);
2207
2208 if (!on != aniState->ofdmWeakSigDetectOff) {
2209 if (on)
2210 ahp->ah_stats.ast_ani_ofdmon++;
2211 else
2212 ahp->ah_stats.ast_ani_ofdmoff++;
2213 aniState->ofdmWeakSigDetectOff = !on;
2214 }
2215 break;
2216 }
2217 case HAL_ANI_CCK_WEAK_SIGNAL_THR:{
2218 const int weakSigThrCck[] = { 8, 6 };
2219 u_int high = param ? 1 : 0;
2220
2221 OS_REG_RMW_FIELD(ah, AR_PHY_CCK_DETECT,
2222 AR_PHY_CCK_DETECT_WEAK_SIG_THR_CCK,
2223 weakSigThrCck[high]);
2224 if (high != aniState->cckWeakSigThreshold) {
2225 if (high)
2226 ahp->ah_stats.ast_ani_cckhigh++;
2227 else
2228 ahp->ah_stats.ast_ani_ccklow++;
2229 aniState->cckWeakSigThreshold = high;
2230 }
2231 break;
2232 }
2233 case HAL_ANI_FIRSTEP_LEVEL:{
2234 const int firstep[] = { 0, 4, 8 };
2235 u_int level = param;
2236
2237 if (level >= ARRAY_SIZE(firstep)) {
2238 HDPRINTF(ah, HAL_DBG_ANI,
2239 "%s: level out of range (%u > %u)\n",
2240 __func__, level,
2241 (unsigned) ARRAY_SIZE(firstep));
2242 return AH_FALSE;
2243 }
2244 OS_REG_RMW_FIELD(ah, AR_PHY_FIND_SIG,
2245 AR_PHY_FIND_SIG_FIRSTEP,
2246 firstep[level]);
2247 if (level > aniState->firstepLevel)
2248 ahp->ah_stats.ast_ani_stepup++;
2249 else if (level < aniState->firstepLevel)
2250 ahp->ah_stats.ast_ani_stepdown++;
2251 aniState->firstepLevel = level;
2252 break;
2253 }
2254 case HAL_ANI_SPUR_IMMUNITY_LEVEL:{
2255 const int cycpwrThr1[] =
2256 { 2, 4, 6, 8, 10, 12, 14, 16 };
2257 u_int level = param;
2258
2259 if (level >= ARRAY_SIZE(cycpwrThr1)) {
2260 HDPRINTF(ah, HAL_DBG_ANI,
2261 "%s: level out of range (%u > %u)\n",
2262 __func__, level,
2263 (unsigned)
2264 ARRAY_SIZE(cycpwrThr1));
2265 return AH_FALSE;
2266 }
2267 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING5,
2268 AR_PHY_TIMING5_CYCPWR_THR1,
2269 cycpwrThr1[level]);
2270 if (level > aniState->spurImmunityLevel)
2271 ahp->ah_stats.ast_ani_spurup++;
2272 else if (level < aniState->spurImmunityLevel)
2273 ahp->ah_stats.ast_ani_spurdown++;
2274 aniState->spurImmunityLevel = level;
2275 break;
2276 }
2277 case HAL_ANI_PRESENT:
2278 break;
2279 default:
2280 HDPRINTF(ah, HAL_DBG_ANI, "%s: invalid cmd %u\n", __func__,
2281 cmd);
2282 return AH_FALSE;
2283 }
2284
2285 HDPRINTF(ah, HAL_DBG_ANI, "%s: ANI parameters:\n", __func__);
2286 HDPRINTF(ah, HAL_DBG_ANI,
2287 "noiseImmunityLevel=%d, spurImmunityLevel=%d, "
2288 "ofdmWeakSigDetectOff=%d\n",
2289 aniState->noiseImmunityLevel, aniState->spurImmunityLevel,
2290 !aniState->ofdmWeakSigDetectOff);
2291 HDPRINTF(ah, HAL_DBG_ANI,
2292 "cckWeakSigThreshold=%d, "
2293 "firstepLevel=%d, listenTime=%d\n",
2294 aniState->cckWeakSigThreshold, aniState->firstepLevel,
2295 aniState->listenTime);
2296 HDPRINTF(ah, HAL_DBG_ANI,
2297 "cycleCount=%d, ofdmPhyErrCount=%d, cckPhyErrCount=%d\n\n",
2298 aniState->cycleCount, aniState->ofdmPhyErrCount,
2299 aniState->cckPhyErrCount);
2300 return AH_TRUE;
2301 }
2302
2303 static void ath9k_ani_restart(struct ath_hal *ah)
2304 {
2305 struct ath_hal_5416 *ahp = AH5416(ah);
2306 struct ar5416AniState *aniState;
2307
2308 if (!DO_ANI(ah))
2309 return;
2310
2311 aniState = ahp->ah_curani;
2312
2313 aniState->listenTime = 0;
2314 if (ahp->ah_hasHwPhyCounters) {
2315 if (aniState->ofdmTrigHigh > AR_PHY_COUNTMAX) {
2316 aniState->ofdmPhyErrBase = 0;
2317 HDPRINTF(ah, HAL_DBG_ANI,
2318 "OFDM Trigger is too high for hw counters\n");
2319 } else {
2320 aniState->ofdmPhyErrBase =
2321 AR_PHY_COUNTMAX - aniState->ofdmTrigHigh;
2322 }
2323 if (aniState->cckTrigHigh > AR_PHY_COUNTMAX) {
2324 aniState->cckPhyErrBase = 0;
2325 HDPRINTF(ah, HAL_DBG_ANI,
2326 "CCK Trigger is too high for hw counters\n");
2327 } else {
2328 aniState->cckPhyErrBase =
2329 AR_PHY_COUNTMAX - aniState->cckTrigHigh;
2330 }
2331 HDPRINTF(ah, HAL_DBG_ANI,
2332 "%s: Writing ofdmbase=%u cckbase=%u\n",
2333 __func__, aniState->ofdmPhyErrBase,
2334 aniState->cckPhyErrBase);
2335 REG_WRITE(ah, AR_PHY_ERR_1, aniState->ofdmPhyErrBase);
2336 REG_WRITE(ah, AR_PHY_ERR_2, aniState->cckPhyErrBase);
2337 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
2338 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
2339
2340 ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats);
2341 }
2342 aniState->ofdmPhyErrCount = 0;
2343 aniState->cckPhyErrCount = 0;
2344 }
2345
2346 static void ath9k_hw_ani_ofdm_err_trigger(struct ath_hal *ah)
2347 {
2348 struct ath_hal_5416 *ahp = AH5416(ah);
2349 struct hal_channel_internal *chan = ah->ah_curchan;
2350 struct ar5416AniState *aniState;
2351 enum wireless_mode mode;
2352 int32_t rssi;
2353
2354 if (!DO_ANI(ah))
2355 return;
2356
2357 aniState = ahp->ah_curani;
2358
2359 if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) {
2360 if (ath9k_hw_ani_control(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL,
2361 aniState->noiseImmunityLevel +
2362 1) == AH_TRUE) {
2363 return;
2364 }
2365 }
2366
2367 if (aniState->spurImmunityLevel < HAL_SPUR_IMMUNE_MAX) {
2368 if (ath9k_hw_ani_control(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL,
2369 aniState->spurImmunityLevel +
2370 1) == AH_TRUE) {
2371 return;
2372 }
2373 }
2374
2375 if (ah->ah_opmode == HAL_M_HOSTAP) {
2376 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) {
2377 ath9k_hw_ani_control(ah, HAL_ANI_FIRSTEP_LEVEL,
2378 aniState->firstepLevel + 1);
2379 }
2380 return;
2381 }
2382 rssi = BEACON_RSSI(ahp);
2383 if (rssi > aniState->rssiThrHigh) {
2384 if (!aniState->ofdmWeakSigDetectOff) {
2385 if (ath9k_hw_ani_control(ah,
2386 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
2387 AH_FALSE) == AH_TRUE) {
2388 ath9k_hw_ani_control(ah,
2389 HAL_ANI_SPUR_IMMUNITY_LEVEL,
2390 0);
2391 return;
2392 }
2393 }
2394 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) {
2395 ath9k_hw_ani_control(ah, HAL_ANI_FIRSTEP_LEVEL,
2396 aniState->firstepLevel + 1);
2397 return;
2398 }
2399 } else if (rssi > aniState->rssiThrLow) {
2400 if (aniState->ofdmWeakSigDetectOff)
2401 ath9k_hw_ani_control(ah,
2402 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
2403 AH_TRUE);
2404 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX)
2405 ath9k_hw_ani_control(ah, HAL_ANI_FIRSTEP_LEVEL,
2406 aniState->firstepLevel + 1);
2407 return;
2408 } else {
2409 mode = ath9k_hw_chan2wmode(ah, (struct hal_channel *) chan);
2410 if (mode == WIRELESS_MODE_11g || mode == WIRELESS_MODE_11b) {
2411 if (!aniState->ofdmWeakSigDetectOff)
2412 ath9k_hw_ani_control(ah,
2413 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
2414 AH_FALSE);
2415 if (aniState->firstepLevel > 0)
2416 ath9k_hw_ani_control(ah,
2417 HAL_ANI_FIRSTEP_LEVEL,
2418 0);
2419 return;
2420 }
2421 }
2422 }
2423
2424 static void ath9k_hw_ani_cck_err_trigger(struct ath_hal *ah)
2425 {
2426 struct ath_hal_5416 *ahp = AH5416(ah);
2427 struct hal_channel_internal *chan = ah->ah_curchan;
2428 struct ar5416AniState *aniState;
2429 enum wireless_mode mode;
2430 int32_t rssi;
2431
2432 if (!DO_ANI(ah))
2433 return;
2434
2435 aniState = ahp->ah_curani;
2436 if (aniState->noiseImmunityLevel < HAL_NOISE_IMMUNE_MAX) {
2437 if (ath9k_hw_ani_control(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL,
2438 aniState->noiseImmunityLevel +
2439 1) == AH_TRUE) {
2440 return;
2441 }
2442 }
2443 if (ah->ah_opmode == HAL_M_HOSTAP) {
2444 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX) {
2445 ath9k_hw_ani_control(ah, HAL_ANI_FIRSTEP_LEVEL,
2446 aniState->firstepLevel + 1);
2447 }
2448 return;
2449 }
2450 rssi = BEACON_RSSI(ahp);
2451 if (rssi > aniState->rssiThrLow) {
2452 if (aniState->firstepLevel < HAL_FIRST_STEP_MAX)
2453 ath9k_hw_ani_control(ah, HAL_ANI_FIRSTEP_LEVEL,
2454 aniState->firstepLevel + 1);
2455 } else {
2456 mode = ath9k_hw_chan2wmode(ah, (struct hal_channel *) chan);
2457 if (mode == WIRELESS_MODE_11g || mode == WIRELESS_MODE_11b) {
2458 if (aniState->firstepLevel > 0)
2459 ath9k_hw_ani_control(ah,
2460 HAL_ANI_FIRSTEP_LEVEL,
2461 0);
2462 }
2463 }
2464 }
2465
2466 static void ath9k_ani_reset(struct ath_hal *ah)
2467 {
2468 struct ath_hal_5416 *ahp = AH5416(ah);
2469 struct ar5416AniState *aniState;
2470 struct hal_channel_internal *chan = ah->ah_curchan;
2471 int index;
2472
2473 if (!DO_ANI(ah))
2474 return;
2475
2476 index = ath9k_hw_get_ani_channel_idx(ah, chan);
2477 aniState = &ahp->ah_ani[index];
2478 ahp->ah_curani = aniState;
2479
2480 if (DO_ANI(ah) && ah->ah_opmode != HAL_M_STA
2481 && ah->ah_opmode != HAL_M_IBSS) {
2482 HDPRINTF(ah, HAL_DBG_ANI,
2483 "%s: Reset ANI state opmode %u\n", __func__,
2484 ah->ah_opmode);
2485 ahp->ah_stats.ast_ani_reset++;
2486 ath9k_hw_ani_control(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL, 0);
2487 ath9k_hw_ani_control(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL, 0);
2488 ath9k_hw_ani_control(ah, HAL_ANI_FIRSTEP_LEVEL, 0);
2489 ath9k_hw_ani_control(ah,
2490 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
2491 !HAL_ANI_USE_OFDM_WEAK_SIG);
2492 ath9k_hw_ani_control(ah, HAL_ANI_CCK_WEAK_SIGNAL_THR,
2493 HAL_ANI_CCK_WEAK_SIG_THR);
2494 ath9k_hw_setrxfilter(ah,
2495 ath9k_hw_getrxfilter(ah) |
2496 HAL_RX_FILTER_PHYERR);
2497 if (ah->ah_opmode == HAL_M_HOSTAP) {
2498 ahp->ah_curani->ofdmTrigHigh =
2499 ah->ah_config.ath_hal_ofdmTrigHigh;
2500 ahp->ah_curani->ofdmTrigLow =
2501 ah->ah_config.ath_hal_ofdmTrigLow;
2502 ahp->ah_curani->cckTrigHigh =
2503 ah->ah_config.ath_hal_cckTrigHigh;
2504 ahp->ah_curani->cckTrigLow =
2505 ah->ah_config.ath_hal_cckTrigLow;
2506 }
2507 ath9k_ani_restart(ah);
2508 return;
2509 }
2510
2511 if (aniState->noiseImmunityLevel != 0)
2512 ath9k_hw_ani_control(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL,
2513 aniState->noiseImmunityLevel);
2514 if (aniState->spurImmunityLevel != 0)
2515 ath9k_hw_ani_control(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL,
2516 aniState->spurImmunityLevel);
2517 if (aniState->ofdmWeakSigDetectOff)
2518 ath9k_hw_ani_control(ah,
2519 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
2520 !aniState->ofdmWeakSigDetectOff);
2521 if (aniState->cckWeakSigThreshold)
2522 ath9k_hw_ani_control(ah, HAL_ANI_CCK_WEAK_SIGNAL_THR,
2523 aniState->cckWeakSigThreshold);
2524 if (aniState->firstepLevel != 0)
2525 ath9k_hw_ani_control(ah, HAL_ANI_FIRSTEP_LEVEL,
2526 aniState->firstepLevel);
2527 if (ahp->ah_hasHwPhyCounters) {
2528 ath9k_hw_setrxfilter(ah,
2529 ath9k_hw_getrxfilter(ah) &
2530 ~HAL_RX_FILTER_PHYERR);
2531 ath9k_ani_restart(ah);
2532 REG_WRITE(ah, AR_PHY_ERR_MASK_1, AR_PHY_ERR_OFDM_TIMING);
2533 REG_WRITE(ah, AR_PHY_ERR_MASK_2, AR_PHY_ERR_CCK_TIMING);
2534
2535 } else {
2536 ath9k_ani_restart(ah);
2537 ath9k_hw_setrxfilter(ah,
2538 ath9k_hw_getrxfilter(ah) |
2539 HAL_RX_FILTER_PHYERR);
2540 }
2541 }
2542
2543 void ath9k_hw_procmibevent(struct ath_hal *ah,
2544 const struct hal_node_stats *stats)
2545 {
2546 struct ath_hal_5416 *ahp = AH5416(ah);
2547 u_int32_t phyCnt1, phyCnt2;
2548
2549 HDPRINTF(ah, HAL_DBG_ANI, "Processing Mib Intr\n");
2550
2551 REG_WRITE(ah, AR_FILT_OFDM, 0);
2552 REG_WRITE(ah, AR_FILT_CCK, 0);
2553 if (!(REG_READ(ah, AR_SLP_MIB_CTRL) & AR_SLP_MIB_PENDING))
2554 REG_WRITE(ah, AR_SLP_MIB_CTRL, AR_SLP_MIB_CLEAR);
2555
2556 ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats);
2557 ahp->ah_stats.ast_nodestats = *stats;
2558
2559 if (!DO_ANI(ah))
2560 return;
2561
2562 phyCnt1 = REG_READ(ah, AR_PHY_ERR_1);
2563 phyCnt2 = REG_READ(ah, AR_PHY_ERR_2);
2564 if (((phyCnt1 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK) ||
2565 ((phyCnt2 & AR_MIBCNT_INTRMASK) == AR_MIBCNT_INTRMASK)) {
2566 struct ar5416AniState *aniState = ahp->ah_curani;
2567 u_int32_t ofdmPhyErrCnt, cckPhyErrCnt;
2568
2569 ofdmPhyErrCnt = phyCnt1 - aniState->ofdmPhyErrBase;
2570 ahp->ah_stats.ast_ani_ofdmerrs +=
2571 ofdmPhyErrCnt - aniState->ofdmPhyErrCount;
2572 aniState->ofdmPhyErrCount = ofdmPhyErrCnt;
2573
2574 cckPhyErrCnt = phyCnt2 - aniState->cckPhyErrBase;
2575 ahp->ah_stats.ast_ani_cckerrs +=
2576 cckPhyErrCnt - aniState->cckPhyErrCount;
2577 aniState->cckPhyErrCount = cckPhyErrCnt;
2578
2579 if (aniState->ofdmPhyErrCount > aniState->ofdmTrigHigh)
2580 ath9k_hw_ani_ofdm_err_trigger(ah);
2581 if (aniState->cckPhyErrCount > aniState->cckTrigHigh)
2582 ath9k_hw_ani_cck_err_trigger(ah);
2583
2584 ath9k_ani_restart(ah);
2585 }
2586 }
2587
2588 static void ath9k_hw_ani_lower_immunity(struct ath_hal *ah)
2589 {
2590 struct ath_hal_5416 *ahp = AH5416(ah);
2591 struct ar5416AniState *aniState;
2592 int32_t rssi;
2593
2594 aniState = ahp->ah_curani;
2595
2596 if (ah->ah_opmode == HAL_M_HOSTAP) {
2597 if (aniState->firstepLevel > 0) {
2598 if (ath9k_hw_ani_control(ah, HAL_ANI_FIRSTEP_LEVEL,
2599 aniState->firstepLevel -
2600 1) == AH_TRUE) {
2601 return;
2602 }
2603 }
2604 } else {
2605 rssi = BEACON_RSSI(ahp);
2606 if (rssi > aniState->rssiThrHigh) {
2607
2608 } else if (rssi > aniState->rssiThrLow) {
2609 if (aniState->ofdmWeakSigDetectOff) {
2610 if (ath9k_hw_ani_control(ah,
2611 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
2612 AH_TRUE) ==
2613 AH_TRUE) {
2614 return;
2615 }
2616 }
2617 if (aniState->firstepLevel > 0) {
2618 if (ath9k_hw_ani_control
2619 (ah, HAL_ANI_FIRSTEP_LEVEL,
2620 aniState->firstepLevel - 1) ==
2621 AH_TRUE) {
2622 return;
2623 }
2624 }
2625 } else {
2626 if (aniState->firstepLevel > 0) {
2627 if (ath9k_hw_ani_control
2628 (ah, HAL_ANI_FIRSTEP_LEVEL,
2629 aniState->firstepLevel - 1) ==
2630 AH_TRUE) {
2631 return;
2632 }
2633 }
2634 }
2635 }
2636
2637 if (aniState->spurImmunityLevel > 0) {
2638 if (ath9k_hw_ani_control(ah, HAL_ANI_SPUR_IMMUNITY_LEVEL,
2639 aniState->spurImmunityLevel -
2640 1) == AH_TRUE) {
2641 return;
2642 }
2643 }
2644
2645 if (aniState->noiseImmunityLevel > 0) {
2646 ath9k_hw_ani_control(ah, HAL_ANI_NOISE_IMMUNITY_LEVEL,
2647 aniState->noiseImmunityLevel - 1);
2648 return;
2649 }
2650 }
2651
2652 static int32_t ath9k_hw_ani_get_listen_time(struct ath_hal *ah)
2653 {
2654 struct ath_hal_5416 *ahp = AH5416(ah);
2655 struct ar5416AniState *aniState;
2656 u_int32_t txFrameCount, rxFrameCount, cycleCount;
2657 int32_t listenTime;
2658
2659 txFrameCount = REG_READ(ah, AR_TFCNT);
2660 rxFrameCount = REG_READ(ah, AR_RFCNT);
2661 cycleCount = REG_READ(ah, AR_CCCNT);
2662
2663 aniState = ahp->ah_curani;
2664 if (aniState->cycleCount == 0 || aniState->cycleCount > cycleCount) {
2665
2666 listenTime = 0;
2667 ahp->ah_stats.ast_ani_lzero++;
2668 } else {
2669 int32_t ccdelta = cycleCount - aniState->cycleCount;
2670 int32_t rfdelta = rxFrameCount - aniState->rxFrameCount;
2671 int32_t tfdelta = txFrameCount - aniState->txFrameCount;
2672 listenTime = (ccdelta - rfdelta - tfdelta) / 44000;
2673 }
2674 aniState->cycleCount = cycleCount;
2675 aniState->txFrameCount = txFrameCount;
2676 aniState->rxFrameCount = rxFrameCount;
2677
2678 return listenTime;
2679 }
2680
2681 void ath9k_hw_ani_monitor(struct ath_hal *ah,
2682 const struct hal_node_stats *stats,
2683 struct hal_channel *chan)
2684 {
2685 struct ath_hal_5416 *ahp = AH5416(ah);
2686 struct ar5416AniState *aniState;
2687 int32_t listenTime;
2688
2689 aniState = ahp->ah_curani;
2690 ahp->ah_stats.ast_nodestats = *stats;
2691
2692 listenTime = ath9k_hw_ani_get_listen_time(ah);
2693 if (listenTime < 0) {
2694 ahp->ah_stats.ast_ani_lneg++;
2695 ath9k_ani_restart(ah);
2696 return;
2697 }
2698
2699 aniState->listenTime += listenTime;
2700
2701 if (ahp->ah_hasHwPhyCounters) {
2702 u_int32_t phyCnt1, phyCnt2;
2703 u_int32_t ofdmPhyErrCnt, cckPhyErrCnt;
2704
2705 ath9k_hw_update_mibstats(ah, &ahp->ah_mibStats);
2706
2707 phyCnt1 = REG_READ(ah, AR_PHY_ERR_1);
2708 phyCnt2 = REG_READ(ah, AR_PHY_ERR_2);
2709
2710 if (phyCnt1 < aniState->ofdmPhyErrBase ||
2711 phyCnt2 < aniState->cckPhyErrBase) {
2712 if (phyCnt1 < aniState->ofdmPhyErrBase) {
2713 HDPRINTF(ah, HAL_DBG_ANI,
2714 "%s: phyCnt1 0x%x, resetting "
2715 "counter value to 0x%x\n",
2716 __func__, phyCnt1,
2717 aniState->ofdmPhyErrBase);
2718 REG_WRITE(ah, AR_PHY_ERR_1,
2719 aniState->ofdmPhyErrBase);
2720 REG_WRITE(ah, AR_PHY_ERR_MASK_1,
2721 AR_PHY_ERR_OFDM_TIMING);
2722 }
2723 if (phyCnt2 < aniState->cckPhyErrBase) {
2724 HDPRINTF(ah, HAL_DBG_ANI,
2725 "%s: phyCnt2 0x%x, resetting "
2726 "counter value to 0x%x\n",
2727 __func__, phyCnt2,
2728 aniState->cckPhyErrBase);
2729 REG_WRITE(ah, AR_PHY_ERR_2,
2730 aniState->cckPhyErrBase);
2731 REG_WRITE(ah, AR_PHY_ERR_MASK_2,
2732 AR_PHY_ERR_CCK_TIMING);
2733 }
2734 return;
2735 }
2736
2737 ofdmPhyErrCnt = phyCnt1 - aniState->ofdmPhyErrBase;
2738 ahp->ah_stats.ast_ani_ofdmerrs +=
2739 ofdmPhyErrCnt - aniState->ofdmPhyErrCount;
2740 aniState->ofdmPhyErrCount = ofdmPhyErrCnt;
2741
2742 cckPhyErrCnt = phyCnt2 - aniState->cckPhyErrBase;
2743 ahp->ah_stats.ast_ani_cckerrs +=
2744 cckPhyErrCnt - aniState->cckPhyErrCount;
2745 aniState->cckPhyErrCount = cckPhyErrCnt;
2746 }
2747
2748 if (!DO_ANI(ah))
2749 return;
2750
2751 if (aniState->listenTime > 5 * ahp->ah_aniPeriod) {
2752 if (aniState->ofdmPhyErrCount <= aniState->listenTime *
2753 aniState->ofdmTrigLow / 1000 &&
2754 aniState->cckPhyErrCount <= aniState->listenTime *
2755 aniState->cckTrigLow / 1000)
2756 ath9k_hw_ani_lower_immunity(ah);
2757 ath9k_ani_restart(ah);
2758 } else if (aniState->listenTime > ahp->ah_aniPeriod) {
2759 if (aniState->ofdmPhyErrCount > aniState->listenTime *
2760 aniState->ofdmTrigHigh / 1000) {
2761 ath9k_hw_ani_ofdm_err_trigger(ah);
2762 ath9k_ani_restart(ah);
2763 } else if (aniState->cckPhyErrCount >
2764 aniState->listenTime * aniState->cckTrigHigh /
2765 1000) {
2766 ath9k_hw_ani_cck_err_trigger(ah);
2767 ath9k_ani_restart(ah);
2768 }
2769 }
2770 }
2771
2772 #ifndef ATH_NF_PER_CHAN
2773 static void ath9k_init_nfcal_hist_buffer(struct ath_hal *ah)
2774 {
2775 int i, j;
2776
2777 for (i = 0; i < NUM_NF_READINGS; i++) {
2778 ah->nfCalHist[i].currIndex = 0;
2779 ah->nfCalHist[i].privNF = AR_PHY_CCA_MAX_GOOD_VALUE;
2780 ah->nfCalHist[i].invalidNFcount =
2781 AR_PHY_CCA_FILTERWINDOW_LENGTH;
2782 for (j = 0; j < HAL_NF_CAL_HIST_MAX; j++) {
2783 ah->nfCalHist[i].nfCalBuffer[j] =
2784 AR_PHY_CCA_MAX_GOOD_VALUE;
2785 }
2786 }
2787 return;
2788 }
2789 #endif
2790
2791 static void ath9k_hw_gpio_cfg_output_mux(struct ath_hal *ah,
2792 u_int32_t gpio, u_int32_t type)
2793 {
2794 int addr;
2795 u_int32_t gpio_shift, tmp;
2796
2797 if (gpio > 11)
2798 addr = AR_GPIO_OUTPUT_MUX3;
2799 else if (gpio > 5)
2800 addr = AR_GPIO_OUTPUT_MUX2;
2801 else
2802 addr = AR_GPIO_OUTPUT_MUX1;
2803
2804 gpio_shift = (gpio % 6) * 5;
2805
2806 if (AR_SREV_9280_20_OR_LATER(ah)
2807 || (addr != AR_GPIO_OUTPUT_MUX1)) {
2808 OS_REG_RMW(ah, addr, (type << gpio_shift),
2809 (0x1f << gpio_shift));
2810 } else {
2811 tmp = REG_READ(ah, addr);
2812 tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2813 tmp &= ~(0x1f << gpio_shift);
2814 tmp |= (type << gpio_shift);
2815 REG_WRITE(ah, addr, tmp);
2816 }
2817 }
2818
2819 static enum hal_bool ath9k_hw_cfg_output(struct ath_hal *ah, u_int32_t gpio,
2820 enum hal_gpio_output_mux_type
2821 halSignalType)
2822 {
2823 u_int32_t ah_signal_type;
2824 u_int32_t gpio_shift;
2825
2826 static u_int32_t MuxSignalConversionTable[] = {
2827
2828 AR_GPIO_OUTPUT_MUX_AS_OUTPUT,
2829
2830 AR_GPIO_OUTPUT_MUX_AS_PCIE_ATTENTION_LED,
2831
2832 AR_GPIO_OUTPUT_MUX_AS_PCIE_POWER_LED,
2833
2834 AR_GPIO_OUTPUT_MUX_AS_MAC_NETWORK_LED,
2835
2836 AR_GPIO_OUTPUT_MUX_AS_MAC_POWER_LED,
2837 };
2838
2839 if ((halSignalType >= 0)
2840 && (halSignalType < ARRAY_SIZE(MuxSignalConversionTable)))
2841 ah_signal_type = MuxSignalConversionTable[halSignalType];
2842 else
2843 return AH_FALSE;
2844
2845 ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
2846
2847 gpio_shift = 2 * gpio;
2848
2849 OS_REG_RMW(ah,
2850 AR_GPIO_OE_OUT,
2851 (AR_GPIO_OE_OUT_DRV_ALL << gpio_shift),
2852 (AR_GPIO_OE_OUT_DRV << gpio_shift));
2853
2854 return AH_TRUE;
2855 }
2856
2857 static enum hal_bool ath9k_hw_set_gpio(struct ath_hal *ah, u_int32_t gpio,
2858 u_int32_t val)
2859 {
2860 OS_REG_RMW(ah, AR_GPIO_IN_OUT, ((val & 1) << gpio),
2861 AR_GPIO_BIT(gpio));
2862 return AH_TRUE;
2863 }
2864
2865 static u_int32_t ath9k_hw_gpio_get(struct ath_hal *ah, u_int32_t gpio)
2866 {
2867 if (gpio >= ah->ah_caps.halNumGpioPins)
2868 return 0xffffffff;
2869
2870 if (AR_SREV_9280_10_OR_LATER(ah)) {
2871 return (MS
2872 (REG_READ(ah, AR_GPIO_IN_OUT),
2873 AR928X_GPIO_IN_VAL) & AR_GPIO_BIT(gpio)) != 0;
2874 } else {
2875 return (MS(REG_READ(ah, AR_GPIO_IN_OUT), AR_GPIO_IN_VAL) &
2876 AR_GPIO_BIT(gpio)) != 0;
2877 }
2878 }
2879
2880 static inline enum hal_status ath9k_hw_post_attach(struct ath_hal *ah)
2881 {
2882 enum hal_status ecode;
2883
2884 if (!ath9k_hw_chip_test(ah)) {
2885 HDPRINTF(ah, HAL_DBG_REG_IO,
2886 "%s: hardware self-test failed\n", __func__);
2887 return HAL_ESELFTEST;
2888 }
2889
2890 ecode = ath9k_hw_rf_claim(ah);
2891 if (ecode != HAL_OK)
2892 return ecode;
2893
2894 ecode = ath9k_hw_eeprom_attach(ah);
2895 if (ecode != HAL_OK)
2896 return ecode;
2897 ecode = ath9k_hw_rfattach(ah);
2898 if (ecode != HAL_OK)
2899 return ecode;
2900
2901 if (!AR_SREV_9100(ah)) {
2902 ath9k_hw_ani_setup(ah);
2903 ath9k_hw_ani_attach(ah);
2904 }
2905 return HAL_OK;
2906 }
2907
2908 static u_int32_t ath9k_hw_ini_fixup(struct ath_hal *ah,
2909 struct ar5416_eeprom *pEepData,
2910 u_int32_t reg, u_int32_t value)
2911 {
2912 struct base_eep_header *pBase = &(pEepData->baseEepHeader);
2913
2914 switch (ah->ah_devid) {
2915 case AR9280_DEVID_PCI:
2916 if (reg == 0x7894) {
2917 HDPRINTF(NULL, HAL_DBG_UNMASKABLE,
2918 "ini VAL: %x EEPROM: %x\n", value,
2919 (pBase->version & 0xff));
2920
2921 if ((pBase->version & 0xff) > 0x0a) {
2922 HDPRINTF(NULL, HAL_DBG_UNMASKABLE,
2923 "PWDCLKIND: %d\n",
2924 pBase->pwdclkind);
2925 value &= ~AR_AN_TOP2_PWDCLKIND;
2926 value |= AR_AN_TOP2_PWDCLKIND & (pBase->
2927 pwdclkind << AR_AN_TOP2_PWDCLKIND_S);
2928 } else {
2929 HDPRINTF(NULL, HAL_DBG_UNMASKABLE,
2930 "PWDCLKIND Earlier Rev\n");
2931 }
2932
2933 HDPRINTF(NULL, HAL_DBG_UNMASKABLE,
2934 "final ini VAL: %x\n", value);
2935 }
2936 break;
2937 }
2938 return value;
2939 }
2940
2941 static enum hal_bool ath9k_hw_fill_cap_info(struct ath_hal *ah)
2942 {
2943 struct ath_hal_5416 *ahp = AH5416(ah);
2944 struct hal_capabilities *pCap = &ah->ah_caps;
2945 u_int16_t capField = 0, eeval;
2946
2947 eeval = ath9k_hw_get_eeprom(ahp, EEP_REG_0);
2948
2949 ah->ah_currentRD = eeval;
2950
2951 eeval = ath9k_hw_get_eeprom(ahp, EEP_REG_1);
2952 ah->ah_currentRDExt = eeval;
2953
2954 capField = ath9k_hw_get_eeprom(ahp, EEP_OP_CAP);
2955
2956 if (ah->ah_opmode != HAL_M_HOSTAP &&
2957 ah->ah_subvendorid == AR_SUBVENDOR_ID_NEW_A) {
2958 if (ah->ah_currentRD == 0x64 || ah->ah_currentRD == 0x65)
2959 ah->ah_currentRD += 5;
2960 else if (ah->ah_currentRD == 0x41)
2961 ah->ah_currentRD = 0x43;
2962 HDPRINTF(ah, HAL_DBG_REGULATORY,
2963 "%s: regdomain mapped to 0x%x\n", __func__,
2964 ah->ah_currentRD);
2965 }
2966
2967 pCap->halWirelessModes = 0;
2968 eeval = ath9k_hw_get_eeprom(ahp, EEP_OP_MODE);
2969
2970 if (eeval & AR5416_OPFLAGS_11A) {
2971 pCap->halWirelessModes |= ATH9K_MODE_SEL_11A |
2972 ((!ah->ah_config.ath_hal_htEnable
2973 || (eeval & AR5416_OPFLAGS_N_5G_HT20)) ? 0
2974 : (ATH9K_MODE_SEL_11NA_HT20 |
2975 ((eeval & AR5416_OPFLAGS_N_5G_HT40) ? 0
2976 : (ATH9K_MODE_SEL_11NA_HT40PLUS |
2977 ATH9K_MODE_SEL_11NA_HT40MINUS))));
2978 }
2979 if (eeval & AR5416_OPFLAGS_11G) {
2980 pCap->halWirelessModes |=
2981 ATH9K_MODE_SEL_11B | ATH9K_MODE_SEL_11G |
2982 ((!ah->ah_config.ath_hal_htEnable
2983 || (eeval & AR5416_OPFLAGS_N_2G_HT20)) ? 0
2984 : (ATH9K_MODE_SEL_11NG_HT20 |
2985 ((eeval & AR5416_OPFLAGS_N_2G_HT40) ? 0
2986 : (ATH9K_MODE_SEL_11NG_HT40PLUS |
2987 ATH9K_MODE_SEL_11NG_HT40MINUS))));
2988
2989 }
2990 pCap->halTxChainMask = ath9k_hw_get_eeprom(ahp, EEP_TX_MASK);
2991 if ((ah->ah_isPciExpress)
2992 || (eeval & AR5416_OPFLAGS_11A)) {
2993 pCap->halRxChainMask =
2994 ath9k_hw_get_eeprom(ahp, EEP_RX_MASK);
2995 } else {
2996 pCap->halRxChainMask =
2997 (ath9k_hw_gpio_get(ah, 0)) ? 0x5 : 0x7;
2998 }
2999
3000 if (!(AR_SREV_9280(ah) && (ah->ah_macRev == 0)))
3001 ahp->ah_miscMode |= AR_PCU_MIC_NEW_LOC_ENA;
3002
3003 pCap->halLow2GhzChan = 2312;
3004 pCap->halHigh2GhzChan = 2732;
3005
3006 pCap->halLow5GhzChan = 4920;
3007 pCap->halHigh5GhzChan = 6100;
3008
3009 pCap->halCipherCkipSupport = AH_FALSE;
3010 pCap->halCipherTkipSupport = AH_TRUE;
3011 pCap->halCipherAesCcmSupport = AH_TRUE;
3012
3013 pCap->halMicCkipSupport = AH_FALSE;
3014 pCap->halMicTkipSupport = AH_TRUE;
3015 pCap->halMicAesCcmSupport = AH_TRUE;
3016
3017 pCap->halChanSpreadSupport = AH_TRUE;
3018
3019 pCap->halHTSupport =
3020 ah->ah_config.ath_hal_htEnable ? AH_TRUE : AH_FALSE;
3021 pCap->halGTTSupport = AH_TRUE;
3022 pCap->halVEOLSupport = AH_TRUE;
3023 pCap->halBssIdMaskSupport = AH_TRUE;
3024 pCap->halMcastKeySrchSupport = AH_FALSE;
3025
3026 if (capField & AR_EEPROM_EEPCAP_MAXQCU)
3027 pCap->halTotalQueues =
3028 MS(capField, AR_EEPROM_EEPCAP_MAXQCU);
3029 else
3030 pCap->halTotalQueues = HAL_NUM_TX_QUEUES;
3031
3032 if (capField & AR_EEPROM_EEPCAP_KC_ENTRIES)
3033 pCap->halKeyCacheSize =
3034 1 << MS(capField, AR_EEPROM_EEPCAP_KC_ENTRIES);
3035 else
3036 pCap->halKeyCacheSize = AR_KEYTABLE_SIZE;
3037
3038 pCap->halFastCCSupport = AH_TRUE;
3039 pCap->halNumMRRetries = 4;
3040 pCap->halTxTrigLevelMax = MAX_TX_FIFO_THRESHOLD;
3041
3042 if (AR_SREV_9280_10_OR_LATER(ah))
3043 pCap->halNumGpioPins = AR928X_NUM_GPIO;
3044 else
3045 pCap->halNumGpioPins = AR_NUM_GPIO;
3046
3047 if (AR_SREV_9280_10_OR_LATER(ah)) {
3048 pCap->halWowSupport = AH_TRUE;
3049 pCap->halWowMatchPatternExact = AH_TRUE;
3050 } else {
3051 pCap->halWowSupport = AH_FALSE;
3052 pCap->halWowMatchPatternExact = AH_FALSE;
3053 }
3054
3055 if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah)) {
3056 pCap->halCSTSupport = AH_TRUE;
3057 pCap->halRtsAggrLimit = ATH_AMPDU_LIMIT_MAX;
3058 } else {
3059 pCap->halRtsAggrLimit = (8 * 1024);
3060 }
3061
3062 pCap->halEnhancedPmSupport = AH_TRUE;
3063
3064 ah->ah_rfsilent = ath9k_hw_get_eeprom(ahp, EEP_RF_SILENT);
3065 if (ah->ah_rfsilent & EEP_RFSILENT_ENABLED) {
3066 ahp->ah_gpioSelect =
3067 MS(ah->ah_rfsilent, EEP_RFSILENT_GPIO_SEL);
3068 ahp->ah_polarity =
3069 MS(ah->ah_rfsilent, EEP_RFSILENT_POLARITY);
3070
3071 ath9k_hw_setcapability(ah, HAL_CAP_RFSILENT, 1, AH_TRUE,
3072 NULL);
3073 pCap->halRfSilentSupport = AH_TRUE;
3074 }
3075
3076 if ((ah->ah_macVersion == AR_SREV_VERSION_5416_PCI) ||
3077 (ah->ah_macVersion == AR_SREV_VERSION_5416_PCIE) ||
3078 (ah->ah_macVersion == AR_SREV_VERSION_9160) ||
3079 (ah->ah_macVersion == AR_SREV_VERSION_9100) ||
3080 (ah->ah_macVersion == AR_SREV_VERSION_9280))
3081 pCap->halAutoSleepSupport = AH_FALSE;
3082 else
3083 pCap->halAutoSleepSupport = AH_TRUE;
3084
3085 if (AR_SREV_9280(ah))
3086 pCap->hal4kbSplitTransSupport = AH_FALSE;
3087 else
3088 pCap->hal4kbSplitTransSupport = AH_TRUE;
3089
3090 if (ah->ah_currentRDExt & (1 << REG_EXT_JAPAN_MIDBAND)) {
3091 pCap->halRegCap =
3092 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3093 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN |
3094 AR_EEPROM_EEREGCAP_EN_KK_U2 |
3095 AR_EEPROM_EEREGCAP_EN_KK_MIDBAND;
3096 } else {
3097 pCap->halRegCap =
3098 AR_EEPROM_EEREGCAP_EN_KK_NEW_11A |
3099 AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN;
3100 }
3101
3102 pCap->halRegCap |= AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND;
3103
3104 pCap->halNumAntCfg5GHz =
3105 ath9k_hw_get_num_ant_config(ahp, HAL_FREQ_BAND_5GHZ);
3106 pCap->halNumAntCfg2GHz =
3107 ath9k_hw_get_num_ant_config(ahp, HAL_FREQ_BAND_2GHZ);
3108
3109 return AH_TRUE;
3110 }
3111
3112 static void ar5416DisablePciePhy(struct ath_hal *ah)
3113 {
3114 if (!AR_SREV_9100(ah))
3115 return;
3116
3117 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
3118 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
3119 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
3120 REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
3121 REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
3122 REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
3123 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
3124 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
3125 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
3126
3127 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
3128 }
3129
3130 static void ath9k_set_power_sleep(struct ath_hal *ah, int setChip)
3131 {
3132 OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
3133 if (setChip) {
3134 OS_REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
3135 AR_RTC_FORCE_WAKE_EN);
3136 if (!AR_SREV_9100(ah))
3137 REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
3138
3139 OS_REG_CLR_BIT(ah, (u_int16_t) (AR_RTC_RESET),
3140 AR_RTC_RESET_EN);
3141 }
3142 }
3143
3144 static void ath9k_set_power_network_sleep(struct ath_hal *ah, int setChip)
3145 {
3146 OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
3147 if (setChip) {
3148 struct hal_capabilities *pCap = &ah->ah_caps;
3149
3150 if (!pCap->halAutoSleepSupport) {
3151 REG_WRITE(ah, AR_RTC_FORCE_WAKE,
3152 AR_RTC_FORCE_WAKE_ON_INT);
3153 } else {
3154 OS_REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE,
3155 AR_RTC_FORCE_WAKE_EN);
3156 }
3157 }
3158 }
3159
3160 static enum hal_bool ath9k_hw_set_power_awake(struct ath_hal *ah,
3161 int setChip)
3162 {
3163 u_int32_t val;
3164 int i;
3165
3166 if (setChip) {
3167 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M) ==
3168 AR_RTC_STATUS_SHUTDOWN) {
3169 if (ath9k_hw_set_reset_reg(ah, HAL_RESET_POWER_ON)
3170 != AH_TRUE) {
3171 return AH_FALSE;
3172 }
3173 }
3174 if (AR_SREV_9100(ah))
3175 OS_REG_SET_BIT(ah, AR_RTC_RESET,
3176 AR_RTC_RESET_EN);
3177
3178 OS_REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
3179 AR_RTC_FORCE_WAKE_EN);
3180 udelay(50);
3181
3182 for (i = POWER_UP_TIME / 50; i > 0; i--) {
3183 val = REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M;
3184 if (val == AR_RTC_STATUS_ON)
3185 break;
3186 udelay(50);
3187 OS_REG_SET_BIT(ah, AR_RTC_FORCE_WAKE,
3188 AR_RTC_FORCE_WAKE_EN);
3189 }
3190 if (i == 0) {
3191 HDPRINTF(ah, HAL_DBG_POWER_MGMT,
3192 "%s: Failed to wakeup in %uus\n",
3193 __func__, POWER_UP_TIME / 20);
3194 return AH_FALSE;
3195 }
3196 }
3197
3198 OS_REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
3199 return AH_TRUE;
3200 }
3201
3202 enum hal_bool ath9k_hw_setpower(struct ath_hal *ah,
3203 enum hal_power_mode mode)
3204 {
3205 struct ath_hal_5416 *ahp = AH5416(ah);
3206 static const char *modes[] = {
3207 "AWAKE",
3208 "FULL-SLEEP",
3209 "NETWORK SLEEP",
3210 "UNDEFINED"
3211 };
3212 int status = AH_TRUE, setChip = AH_TRUE;
3213
3214 HDPRINTF(ah, HAL_DBG_POWER_MGMT, "%s: %s -> %s (%s)\n", __func__,
3215 modes[ahp->ah_powerMode], modes[mode],
3216 setChip ? "set chip " : "");
3217
3218 switch (mode) {
3219 case HAL_PM_AWAKE:
3220 status = ath9k_hw_set_power_awake(ah, setChip);
3221 break;
3222 case HAL_PM_FULL_SLEEP:
3223 ath9k_set_power_sleep(ah, setChip);
3224 ahp->ah_chipFullSleep = AH_TRUE;
3225 break;
3226 case HAL_PM_NETWORK_SLEEP:
3227 ath9k_set_power_network_sleep(ah, setChip);
3228 break;
3229 default:
3230 HDPRINTF(ah, HAL_DBG_POWER_MGMT,
3231 "%s: unknown power mode %u\n", __func__, mode);
3232 return AH_FALSE;
3233 }
3234 ahp->ah_powerMode = mode;
3235 return status;
3236 }
3237
3238 static struct ath_hal *ath9k_hw_do_attach(u_int16_t devid, void *sc,
3239 void __iomem *mem,
3240 enum hal_status *status)
3241 {
3242 struct ath_hal_5416 *ahp;
3243 struct ath_hal *ah;
3244 enum hal_status ecode;
3245 #ifndef CONFIG_SLOW_ANT_DIV
3246 u_int32_t i;
3247 u_int32_t j;
3248 #endif
3249
3250 ahp = ath9k_hw_newstate(devid, sc, mem, status);
3251 if (ahp == NULL)
3252 return NULL;
3253
3254 ah = &ahp->ah;
3255
3256 ath9k_hw_set_defaults(ah);
3257
3258 if (ah->ah_config.ath_hal_intrMitigation != 0)
3259 ahp->ah_intrMitigation = AH_TRUE;
3260
3261 if (!ath9k_hw_set_reset_reg(ah, HAL_RESET_POWER_ON)) {
3262 HDPRINTF(ah, HAL_DBG_RESET, "%s: couldn't reset chip\n",
3263 __func__);
3264 ecode = HAL_EIO;
3265 goto bad;
3266 }
3267
3268 if (!ath9k_hw_setpower(ah, HAL_PM_AWAKE)) {
3269 HDPRINTF(ah, HAL_DBG_RESET, "%s: couldn't wakeup chip\n",
3270 __func__);
3271 ecode = HAL_EIO;
3272 goto bad;
3273 }
3274
3275 if (ah->ah_config.ath_hal_serializeRegMode == SER_REG_MODE_AUTO) {
3276 if (ah->ah_macVersion == AR_SREV_VERSION_5416_PCI) {
3277 ah->ah_config.ath_hal_serializeRegMode =
3278 SER_REG_MODE_ON;
3279 } else {
3280 ah->ah_config.ath_hal_serializeRegMode =
3281 SER_REG_MODE_OFF;
3282 }
3283 }
3284 HDPRINTF(ah, HAL_DBG_RESET, "%s: ath_hal_serializeRegMode is %d\n",
3285 __func__, ah->ah_config.ath_hal_serializeRegMode);
3286
3287 if ((ah->ah_macVersion != AR_SREV_VERSION_5416_PCI) &&
3288 (ah->ah_macVersion != AR_SREV_VERSION_5416_PCIE) &&
3289 (ah->ah_macVersion != AR_SREV_VERSION_9160) &&
3290 (!AR_SREV_9100(ah)) && (!AR_SREV_9280(ah))) {
3291 HDPRINTF(ah, HAL_DBG_RESET,
3292 "%s: Mac Chip Rev 0x%02x.%x is not supported by "
3293 "this driver\n", __func__,
3294 ah->ah_macVersion, ah->ah_macRev);
3295 ecode = HAL_ENOTSUPP;
3296 goto bad;
3297 }
3298
3299 if (AR_SREV_9100(ah)) {
3300 ahp->ah_iqCalData.calData = &iq_cal_multi_sample;
3301 ahp->ah_suppCals = IQ_MISMATCH_CAL;
3302 ah->ah_isPciExpress = AH_FALSE;
3303 }
3304 ah->ah_phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
3305
3306 if (AR_SREV_9160_10_OR_LATER(ah)) {
3307 if (AR_SREV_9280_10_OR_LATER(ah)) {
3308 ahp->ah_iqCalData.calData = &iq_cal_single_sample;
3309 ahp->ah_adcGainCalData.calData =
3310 &adc_gain_cal_single_sample;
3311 ahp->ah_adcDcCalData.calData =
3312 &adc_dc_cal_single_sample;
3313 ahp->ah_adcDcCalInitData.calData =
3314 &adc_init_dc_cal;
3315 } else {
3316 ahp->ah_iqCalData.calData = &iq_cal_multi_sample;
3317 ahp->ah_adcGainCalData.calData =
3318 &adc_gain_cal_multi_sample;
3319 ahp->ah_adcDcCalData.calData =
3320 &adc_dc_cal_multi_sample;
3321 ahp->ah_adcDcCalInitData.calData =
3322 &adc_init_dc_cal;
3323 }
3324 ahp->ah_suppCals =
3325 ADC_GAIN_CAL | ADC_DC_CAL | IQ_MISMATCH_CAL;
3326 }
3327
3328 if (AR_SREV_9160(ah)) {
3329 ah->ah_config.ath_hal_enableANI = 1;
3330 ahp->ah_ani_function = (HAL_ANI_SPUR_IMMUNITY_LEVEL |
3331 HAL_ANI_FIRSTEP_LEVEL);
3332 } else {
3333 ahp->ah_ani_function = HAL_ANI_ALL;
3334 if (AR_SREV_9280_10_OR_LATER(ah)) {
3335 ahp->ah_ani_function &=
3336 ~HAL_ANI_NOISE_IMMUNITY_LEVEL;
3337 }
3338 }
3339
3340 HDPRINTF(ah, HAL_DBG_RESET,
3341 "%s: This Mac Chip Rev 0x%02x.%x is \n", __func__,
3342 ah->ah_macVersion, ah->ah_macRev);
3343
3344 if (AR_SREV_9280_20_OR_LATER(ah)) {
3345 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280_2,
3346 ARRAY_SIZE(ar9280Modes_9280_2), 6);
3347 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280_2,
3348 ARRAY_SIZE(ar9280Common_9280_2), 2);
3349
3350 if (ah->ah_config.ath_hal_pcieClockReq) {
3351 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
3352 ar9280PciePhy_clkreq_off_L1_9280,
3353 ARRAY_SIZE
3354 (ar9280PciePhy_clkreq_off_L1_9280),
3355 2);
3356 } else {
3357 INIT_INI_ARRAY(&ahp->ah_iniPcieSerdes,
3358 ar9280PciePhy_clkreq_always_on_L1_9280,
3359 ARRAY_SIZE
3360 (ar9280PciePhy_clkreq_always_on_L1_9280),
3361 2);
3362 }
3363 INIT_INI_ARRAY(&ahp->ah_iniModesAdditional,
3364 ar9280Modes_fast_clock_9280_2,
3365 ARRAY_SIZE(ar9280Modes_fast_clock_9280_2),
3366 3);
3367 } else if (AR_SREV_9280_10_OR_LATER(ah)) {
3368 INIT_INI_ARRAY(&ahp->ah_iniModes, ar9280Modes_9280,
3369 ARRAY_SIZE(ar9280Modes_9280), 6);
3370 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar9280Common_9280,
3371 ARRAY_SIZE(ar9280Common_9280), 2);
3372 } else if (AR_SREV_9160_10_OR_LATER(ah)) {
3373 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes_9160,
3374 ARRAY_SIZE(ar5416Modes_9160), 6);
3375 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common_9160,
3376 ARRAY_SIZE(ar5416Common_9160), 2);
3377 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0_9160,
3378 ARRAY_SIZE(ar5416Bank0_9160), 2);
3379 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain_9160,
3380 ARRAY_SIZE(ar5416BB_RfGain_9160), 3);
3381 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1_9160,
3382 ARRAY_SIZE(ar5416Bank1_9160), 2);
3383 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2_9160,
3384 ARRAY_SIZE(ar5416Bank2_9160), 2);
3385 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3_9160,
3386 ARRAY_SIZE(ar5416Bank3_9160), 3);
3387 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6_9160,
3388 ARRAY_SIZE(ar5416Bank6_9160), 3);
3389 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC_9160,
3390 ARRAY_SIZE(ar5416Bank6TPC_9160), 3);
3391 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7_9160,
3392 ARRAY_SIZE(ar5416Bank7_9160), 2);
3393 if (AR_SREV_9160_11(ah)) {
3394 INIT_INI_ARRAY(&ahp->ah_iniAddac,
3395 ar5416Addac_91601_1,
3396 ARRAY_SIZE(ar5416Addac_91601_1), 2);
3397 } else {
3398 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac_9160,
3399 ARRAY_SIZE(ar5416Addac_9160), 2);
3400 }
3401 } else if (AR_SREV_9100_OR_LATER(ah)) {
3402 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes_9100,
3403 ARRAY_SIZE(ar5416Modes_9100), 6);
3404 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common_9100,
3405 ARRAY_SIZE(ar5416Common_9100), 2);
3406 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0_9100,
3407 ARRAY_SIZE(ar5416Bank0_9100), 2);
3408 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain_9100,
3409 ARRAY_SIZE(ar5416BB_RfGain_9100), 3);
3410 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1_9100,
3411 ARRAY_SIZE(ar5416Bank1_9100), 2);
3412 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2_9100,
3413 ARRAY_SIZE(ar5416Bank2_9100), 2);
3414 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3_9100,
3415 ARRAY_SIZE(ar5416Bank3_9100), 3);
3416 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6_9100,
3417 ARRAY_SIZE(ar5416Bank6_9100), 3);
3418 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC_9100,
3419 ARRAY_SIZE(ar5416Bank6TPC_9100), 3);
3420 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7_9100,
3421 ARRAY_SIZE(ar5416Bank7_9100), 2);
3422 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac_9100,
3423 ARRAY_SIZE(ar5416Addac_9100), 2);
3424 } else {
3425 INIT_INI_ARRAY(&ahp->ah_iniModes, ar5416Modes,
3426 ARRAY_SIZE(ar5416Modes), 6);
3427 INIT_INI_ARRAY(&ahp->ah_iniCommon, ar5416Common,
3428 ARRAY_SIZE(ar5416Common), 2);
3429 INIT_INI_ARRAY(&ahp->ah_iniBank0, ar5416Bank0,
3430 ARRAY_SIZE(ar5416Bank0), 2);
3431 INIT_INI_ARRAY(&ahp->ah_iniBB_RfGain, ar5416BB_RfGain,
3432 ARRAY_SIZE(ar5416BB_RfGain), 3);
3433 INIT_INI_ARRAY(&ahp->ah_iniBank1, ar5416Bank1,
3434 ARRAY_SIZE(ar5416Bank1), 2);
3435 INIT_INI_ARRAY(&ahp->ah_iniBank2, ar5416Bank2,
3436 ARRAY_SIZE(ar5416Bank2), 2);
3437 INIT_INI_ARRAY(&ahp->ah_iniBank3, ar5416Bank3,
3438 ARRAY_SIZE(ar5416Bank3), 3);
3439 INIT_INI_ARRAY(&ahp->ah_iniBank6, ar5416Bank6,
3440 ARRAY_SIZE(ar5416Bank6), 3);
3441 INIT_INI_ARRAY(&ahp->ah_iniBank6TPC, ar5416Bank6TPC,
3442 ARRAY_SIZE(ar5416Bank6TPC), 3);
3443 INIT_INI_ARRAY(&ahp->ah_iniBank7, ar5416Bank7,
3444 ARRAY_SIZE(ar5416Bank7), 2);
3445 INIT_INI_ARRAY(&ahp->ah_iniAddac, ar5416Addac,
3446 ARRAY_SIZE(ar5416Addac), 2);
3447 }
3448
3449 if (ah->ah_isPciExpress)
3450 ath9k_hw_configpcipowersave(ah, 0);
3451 else
3452 ar5416DisablePciePhy(ah);
3453
3454 ecode = ath9k_hw_post_attach(ah);
3455 if (ecode != HAL_OK)
3456 goto bad;
3457
3458 #ifndef CONFIG_SLOW_ANT_DIV
3459 if (ah->ah_devid == AR9280_DEVID_PCI) {
3460 for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) {
3461 u_int32_t reg = INI_RA(&ahp->ah_iniModes, i, 0);
3462
3463 for (j = 1; j < ahp->ah_iniModes.ia_columns; j++) {
3464 u_int32_t val = INI_RA(&ahp->ah_iniModes, i, j);
3465
3466 INI_RA(&ahp->ah_iniModes, i, j) =
3467 ath9k_hw_ini_fixup(ah, &ahp->ah_eeprom,
3468 reg, val);
3469 }
3470 }
3471 }
3472 #endif
3473
3474 if (!ath9k_hw_fill_cap_info(ah)) {
3475 HDPRINTF(ah, HAL_DBG_RESET,
3476 "%s:failed ath9k_hw_fill_cap_info\n", __func__);
3477 ecode = HAL_EEREAD;
3478 goto bad;
3479 }
3480
3481 ecode = ath9k_hw_init_macaddr(ah);
3482 if (ecode != HAL_OK) {
3483 HDPRINTF(ah, HAL_DBG_RESET,
3484 "%s: failed initializing mac address\n",
3485 __func__);
3486 goto bad;
3487 }
3488
3489 if (AR_SREV_9285(ah))
3490 ah->ah_txTrigLevel = (AR_FTRIG_256B >> AR_FTRIG_S);
3491 else
3492 ah->ah_txTrigLevel = (AR_FTRIG_512B >> AR_FTRIG_S);
3493
3494 #ifndef ATH_NF_PER_CHAN
3495
3496 ath9k_init_nfcal_hist_buffer(ah);
3497 #endif
3498
3499 return ah;
3500
3501 bad:
3502 if (ahp)
3503 ath9k_hw_detach((struct ath_hal *) ahp);
3504 if (status)
3505 *status = ecode;
3506 return NULL;
3507 }
3508
3509 void ath9k_hw_detach(struct ath_hal *ah)
3510 {
3511 if (!AR_SREV_9100(ah))
3512 ath9k_hw_ani_detach(ah);
3513 ath9k_hw_rfdetach(ah);
3514
3515 ath9k_hw_setpower(ah, HAL_PM_FULL_SLEEP);
3516 kfree(ah);
3517 }
3518
3519 enum hal_bool ath9k_get_channel_edges(struct ath_hal *ah,
3520 u_int16_t flags, u_int16_t *low,
3521 u_int16_t *high)
3522 {
3523 struct hal_capabilities *pCap = &ah->ah_caps;
3524
3525 if (flags & CHANNEL_5GHZ) {
3526 *low = pCap->halLow5GhzChan;
3527 *high = pCap->halHigh5GhzChan;
3528 return AH_TRUE;
3529 }
3530 if ((flags & CHANNEL_2GHZ)) {
3531 *low = pCap->halLow2GhzChan;
3532 *high = pCap->halHigh2GhzChan;
3533
3534 return AH_TRUE;
3535 }
3536 return AH_FALSE;
3537 }
3538
3539 static inline enum hal_bool ath9k_hw_fill_vpd_table(u_int8_t pwrMin,
3540 u_int8_t pwrMax,
3541 u_int8_t *pPwrList,
3542 u_int8_t *pVpdList,
3543 u_int16_t
3544 numIntercepts,
3545 u_int8_t *pRetVpdList)
3546 {
3547 u_int16_t i, k;
3548 u_int8_t currPwr = pwrMin;
3549 u_int16_t idxL = 0, idxR = 0;
3550
3551 for (i = 0; i <= (pwrMax - pwrMin) / 2; i++) {
3552 ath9k_hw_get_lower_upper_index(currPwr, pPwrList,
3553 numIntercepts, &(idxL),
3554 &(idxR));
3555 if (idxR < 1)
3556 idxR = 1;
3557 if (idxL == numIntercepts - 1)
3558 idxL = (u_int16_t) (numIntercepts - 2);
3559 if (pPwrList[idxL] == pPwrList[idxR])
3560 k = pVpdList[idxL];
3561 else
3562 k = (u_int16_t) (((currPwr -
3563 pPwrList[idxL]) *
3564 pVpdList[idxR] +
3565 (pPwrList[idxR] -
3566 currPwr) * pVpdList[idxL]) /
3567 (pPwrList[idxR] -
3568 pPwrList[idxL]));
3569 pRetVpdList[i] = (u_int8_t) k;
3570 currPwr += 2;
3571 }
3572
3573 return AH_TRUE;
3574 }
3575
3576 static inline void
3577 ath9k_hw_get_gain_boundaries_pdadcs(struct ath_hal *ah,
3578 struct hal_channel_internal *chan,
3579 struct cal_data_per_freq *pRawDataSet,
3580 u_int8_t *bChans,
3581 u_int16_t availPiers,
3582 u_int16_t tPdGainOverlap,
3583 int16_t *pMinCalPower,
3584 u_int16_t *pPdGainBoundaries,
3585 u_int8_t *pPDADCValues,
3586 u_int16_t numXpdGains)
3587 {
3588 int i, j, k;
3589 int16_t ss;
3590 u_int16_t idxL = 0, idxR = 0, numPiers;
3591 static u_int8_t vpdTableL[AR5416_NUM_PD_GAINS]
3592 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
3593 static u_int8_t vpdTableR[AR5416_NUM_PD_GAINS]
3594 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
3595 static u_int8_t vpdTableI[AR5416_NUM_PD_GAINS]
3596 [AR5416_MAX_PWR_RANGE_IN_HALF_DB];
3597
3598 u_int8_t *pVpdL, *pVpdR, *pPwrL, *pPwrR;
3599 u_int8_t minPwrT4[AR5416_NUM_PD_GAINS];
3600 u_int8_t maxPwrT4[AR5416_NUM_PD_GAINS];
3601 int16_t vpdStep;
3602 int16_t tmpVal;
3603 u_int16_t sizeCurrVpdTable, maxIndex, tgtIndex;
3604 enum hal_bool match;
3605 int16_t minDelta = 0;
3606 struct chan_centers centers;
3607
3608 ath9k_hw_get_channel_centers(ah, chan, &centers);
3609
3610 for (numPiers = 0; numPiers < availPiers; numPiers++) {
3611 if (bChans[numPiers] == AR5416_BCHAN_UNUSED)
3612 break;
3613 }
3614
3615 match = ath9k_hw_get_lower_upper_index((u_int8_t)
3616 FREQ2FBIN(centers.
3617 synth_center,
3618 IS_CHAN_2GHZ
3619 (chan)), bChans,
3620 numPiers, &idxL, &idxR);
3621
3622 if (match) {
3623 for (i = 0; i < numXpdGains; i++) {
3624 minPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][0];
3625 maxPwrT4[i] = pRawDataSet[idxL].pwrPdg[i][4];
3626 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
3627 pRawDataSet[idxL].
3628 pwrPdg[i],
3629 pRawDataSet[idxL].
3630 vpdPdg[i],
3631 AR5416_PD_GAIN_ICEPTS,
3632 vpdTableI[i]);
3633 }
3634 } else {
3635 for (i = 0; i < numXpdGains; i++) {
3636 pVpdL = pRawDataSet[idxL].vpdPdg[i];
3637 pPwrL = pRawDataSet[idxL].pwrPdg[i];
3638 pVpdR = pRawDataSet[idxR].vpdPdg[i];
3639 pPwrR = pRawDataSet[idxR].pwrPdg[i];
3640
3641 minPwrT4[i] = max(pPwrL[0], pPwrR[0]);
3642
3643 maxPwrT4[i] =
3644 min(pPwrL[AR5416_PD_GAIN_ICEPTS - 1],
3645 pPwrR[AR5416_PD_GAIN_ICEPTS - 1]);
3646
3647
3648 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
3649 pPwrL, pVpdL,
3650 AR5416_PD_GAIN_ICEPTS,
3651 vpdTableL[i]);
3652 ath9k_hw_fill_vpd_table(minPwrT4[i], maxPwrT4[i],
3653 pPwrR, pVpdR,
3654 AR5416_PD_GAIN_ICEPTS,
3655 vpdTableR[i]);
3656
3657 for (j = 0; j <= (maxPwrT4[i] - minPwrT4[i]) / 2; j++) {
3658 vpdTableI[i][j] =
3659 (u_int8_t) (ath9k_hw_interpolate
3660 ((u_int16_t)
3661 FREQ2FBIN(centers.
3662 synth_center,
3663 IS_CHAN_2GHZ
3664 (chan)),
3665 bChans[idxL],
3666 bChans[idxR], vpdTableL[i]
3667 [j], vpdTableR[i]
3668 [j]));
3669 }
3670 }
3671 }
3672
3673 *pMinCalPower = (int16_t) (minPwrT4[0] / 2);
3674
3675 k = 0;
3676 for (i = 0; i < numXpdGains; i++) {
3677 if (i == (numXpdGains - 1))
3678 pPdGainBoundaries[i] =
3679 (u_int16_t) (maxPwrT4[i] / 2);
3680 else
3681 pPdGainBoundaries[i] =
3682 (u_int16_t) ((maxPwrT4[i] +
3683 minPwrT4[i + 1]) / 4);
3684
3685 pPdGainBoundaries[i] =
3686 min((u_int16_t) AR5416_MAX_RATE_POWER,
3687 pPdGainBoundaries[i]);
3688
3689 if ((i == 0) && !AR_SREV_5416_V20_OR_LATER(ah)) {
3690 minDelta = pPdGainBoundaries[0] - 23;
3691 pPdGainBoundaries[0] = 23;
3692 } else {
3693 minDelta = 0;
3694 }
3695
3696 if (i == 0) {
3697 if (AR_SREV_9280_10_OR_LATER(ah))
3698 ss = (int16_t) (0 - (minPwrT4[i] / 2));
3699 else
3700 ss = 0;
3701 } else {
3702 ss = (int16_t) ((pPdGainBoundaries[i - 1] -
3703 (minPwrT4[i] / 2)) -
3704 tPdGainOverlap + 1 + minDelta);
3705 }
3706 vpdStep = (int16_t) (vpdTableI[i][1] - vpdTableI[i][0]);
3707 vpdStep = (int16_t) ((vpdStep < 1) ? 1 : vpdStep);
3708
3709 while ((ss < 0) && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
3710 tmpVal = (int16_t) (vpdTableI[i][0] + ss * vpdStep);
3711 pPDADCValues[k++] =
3712 (u_int8_t) ((tmpVal < 0) ? 0 : tmpVal);
3713 ss++;
3714 }
3715
3716 sizeCurrVpdTable =
3717 (u_int8_t) ((maxPwrT4[i] - minPwrT4[i]) / 2 + 1);
3718 tgtIndex = (u_int8_t) (pPdGainBoundaries[i] + tPdGainOverlap -
3719 (minPwrT4[i] / 2));
3720 maxIndex = (tgtIndex <
3721 sizeCurrVpdTable) ? tgtIndex : sizeCurrVpdTable;
3722
3723 while ((ss < maxIndex)
3724 && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
3725 pPDADCValues[k++] = vpdTableI[i][ss++];
3726 }
3727
3728 vpdStep = (int16_t) (vpdTableI[i][sizeCurrVpdTable - 1] -
3729 vpdTableI[i][sizeCurrVpdTable - 2]);
3730 vpdStep = (int16_t) ((vpdStep < 1) ? 1 : vpdStep);
3731
3732 if (tgtIndex > maxIndex) {
3733 while ((ss <= tgtIndex)
3734 && (k < (AR5416_NUM_PDADC_VALUES - 1))) {
3735 tmpVal = (int16_t) ((vpdTableI[i]
3736 [sizeCurrVpdTable -
3737 1] + (ss - maxIndex +
3738 1) * vpdStep));
3739 pPDADCValues[k++] = (u_int8_t) ((tmpVal >
3740 255) ? 255 : tmpVal);
3741 ss++;
3742 }
3743 }
3744 }
3745
3746 while (i < AR5416_PD_GAINS_IN_MASK) {
3747 pPdGainBoundaries[i] = pPdGainBoundaries[i - 1];
3748 i++;
3749 }
3750
3751 while (k < AR5416_NUM_PDADC_VALUES) {
3752 pPDADCValues[k] = pPDADCValues[k - 1];
3753 k++;
3754 }
3755 return;
3756 }
3757
3758 static inline enum hal_bool
3759 ath9k_hw_set_power_cal_table(struct ath_hal *ah,
3760 struct ar5416_eeprom *pEepData,
3761 struct hal_channel_internal *chan,
3762 int16_t *pTxPowerIndexOffset)
3763 {
3764 struct cal_data_per_freq *pRawDataset;
3765 u_int8_t *pCalBChans = NULL;
3766 u_int16_t pdGainOverlap_t2;
3767 static u_int8_t pdadcValues[AR5416_NUM_PDADC_VALUES];
3768 u_int16_t gainBoundaries[AR5416_PD_GAINS_IN_MASK];
3769 u_int16_t numPiers, i, j;
3770 int16_t tMinCalPower;
3771 u_int16_t numXpdGain, xpdMask;
3772 u_int16_t xpdGainValues[AR5416_NUM_PD_GAINS] = { 0, 0, 0, 0 };
3773 u_int32_t reg32, regOffset, regChainOffset;
3774 int16_t modalIdx;
3775 struct ath_hal_5416 *ahp = AH5416(ah);
3776
3777 modalIdx = IS_CHAN_2GHZ(chan) ? 1 : 0;
3778 xpdMask = pEepData->modalHeader[modalIdx].xpdGain;
3779
3780 if ((pEepData->baseEepHeader.
3781 version & AR5416_EEP_VER_MINOR_MASK) >=
3782 AR5416_EEP_MINOR_VER_2) {
3783 pdGainOverlap_t2 =
3784 pEepData->modalHeader[modalIdx].pdGainOverlap;
3785 } else {
3786 pdGainOverlap_t2 =
3787 (u_int16_t) (MS
3788 (REG_READ(ah, AR_PHY_TPCRG5),
3789 AR_PHY_TPCRG5_PD_GAIN_OVERLAP));
3790 }
3791
3792 if (IS_CHAN_2GHZ(chan)) {
3793 pCalBChans = pEepData->calFreqPier2G;
3794 numPiers = AR5416_NUM_2G_CAL_PIERS;
3795 } else {
3796 pCalBChans = pEepData->calFreqPier5G;
3797 numPiers = AR5416_NUM_5G_CAL_PIERS;
3798 }
3799
3800 numXpdGain = 0;
3801
3802 for (i = 1; i <= AR5416_PD_GAINS_IN_MASK; i++) {
3803 if ((xpdMask >> (AR5416_PD_GAINS_IN_MASK - i)) & 1) {
3804 if (numXpdGain >= AR5416_NUM_PD_GAINS)
3805 break;
3806 xpdGainValues[numXpdGain] =
3807 (u_int16_t) (AR5416_PD_GAINS_IN_MASK - i);
3808 numXpdGain++;
3809 }
3810 }
3811
3812 OS_REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_NUM_PD_GAIN,
3813 (numXpdGain - 1) & 0x3);
3814 OS_REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_1,
3815 xpdGainValues[0]);
3816 OS_REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_2,
3817 xpdGainValues[1]);
3818 OS_REG_RMW_FIELD(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_GAIN_3,
3819 xpdGainValues[2]);
3820
3821 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
3822 if (AR_SREV_5416_V20_OR_LATER(ah) &&
3823 (ahp->ah_rxchainmask == 5 || ahp->ah_txchainmask == 5)
3824 && (i != 0)) {
3825 regChainOffset = (i == 1) ? 0x2000 : 0x1000;
3826 } else
3827 regChainOffset = i * 0x1000;
3828 if (pEepData->baseEepHeader.txMask & (1 << i)) {
3829 if (IS_CHAN_2GHZ(chan))
3830 pRawDataset = pEepData->calPierData2G[i];
3831 else
3832 pRawDataset = pEepData->calPierData5G[i];
3833
3834 ath9k_hw_get_gain_boundaries_pdadcs(ah, chan,
3835 pRawDataset,
3836 pCalBChans,
3837 numPiers,
3838 pdGainOverlap_t2,
3839 &tMinCalPower,
3840 gainBoundaries,
3841 pdadcValues,
3842 numXpdGain);
3843
3844 if ((i == 0) || AR_SREV_5416_V20_OR_LATER(ah)) {
3845
3846 REG_WRITE(ah,
3847 AR_PHY_TPCRG5 + regChainOffset,
3848 SM(pdGainOverlap_t2,
3849 AR_PHY_TPCRG5_PD_GAIN_OVERLAP)
3850 | SM(gainBoundaries[0],
3851 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1)
3852 | SM(gainBoundaries[1],
3853 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_2)
3854 | SM(gainBoundaries[2],
3855 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_3)
3856 | SM(gainBoundaries[3],
3857 AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_4));
3858 }
3859
3860 regOffset =
3861 AR_PHY_BASE + (672 << 2) + regChainOffset;
3862 for (j = 0; j < 32; j++) {
3863 reg32 =
3864 ((pdadcValues[4 * j + 0] & 0xFF) << 0)
3865 | ((pdadcValues[4 * j + 1] & 0xFF) <<
3866 8) | ((pdadcValues[4 * j + 2] &
3867 0xFF) << 16) |
3868 ((pdadcValues[4 * j + 3] & 0xFF) <<
3869 24);
3870 REG_WRITE(ah, regOffset, reg32);
3871
3872 HDPRINTF(ah, HAL_DBG_PHY_IO,
3873 "PDADC (%d,%4x): %4.4x %8.8x\n",
3874 i, regChainOffset, regOffset,
3875 reg32);
3876 HDPRINTF(ah, HAL_DBG_PHY_IO,
3877 "PDADC: Chain %d | PDADC %3d Value %3d | "
3878 "PDADC %3d Value %3d | PDADC %3d Value %3d | "
3879 "PDADC %3d Value %3d |\n",
3880 i, 4 * j, pdadcValues[4 * j],
3881 4 * j + 1, pdadcValues[4 * j + 1],
3882 4 * j + 2, pdadcValues[4 * j + 2],
3883 4 * j + 3,
3884 pdadcValues[4 * j + 3]);
3885
3886 regOffset += 4;
3887 }
3888 }
3889 }
3890 *pTxPowerIndexOffset = 0;
3891
3892 return AH_TRUE;
3893 }
3894
3895 void ath9k_hw_configpcipowersave(struct ath_hal *ah, int restore)
3896 {
3897 struct ath_hal_5416 *ahp = AH5416(ah);
3898 u_int8_t i;
3899
3900 if (ah->ah_isPciExpress != AH_TRUE)
3901 return;
3902
3903 if (ah->ah_config.ath_hal_pciePowerSaveEnable == 2)
3904 return;
3905
3906 if (restore)
3907 return;
3908
3909 if (AR_SREV_9280_20_OR_LATER(ah)) {
3910 for (i = 0; i < ahp->ah_iniPcieSerdes.ia_rows; i++) {
3911 REG_WRITE(ah, INI_RA(&ahp->ah_iniPcieSerdes, i, 0),
3912 INI_RA(&ahp->ah_iniPcieSerdes, i, 1));
3913 }
3914 udelay(1000);
3915 } else if (AR_SREV_9280(ah)
3916 && (ah->ah_macRev == AR_SREV_REVISION_9280_10)) {
3917 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fd00);
3918 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
3919
3920 REG_WRITE(ah, AR_PCIE_SERDES, 0xa8000019);
3921 REG_WRITE(ah, AR_PCIE_SERDES, 0x13160820);
3922 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980560);
3923
3924 if (ah->ah_config.ath_hal_pcieClockReq)
3925 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffc);
3926 else
3927 REG_WRITE(ah, AR_PCIE_SERDES, 0x401deffd);
3928
3929 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
3930 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
3931 REG_WRITE(ah, AR_PCIE_SERDES, 0x00043007);
3932
3933 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
3934
3935 udelay(1000);
3936 } else {
3937 REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
3938 REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
3939 REG_WRITE(ah, AR_PCIE_SERDES, 0x28000039);
3940 REG_WRITE(ah, AR_PCIE_SERDES, 0x53160824);
3941 REG_WRITE(ah, AR_PCIE_SERDES, 0xe5980579);
3942 REG_WRITE(ah, AR_PCIE_SERDES, 0x001defff);
3943 REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
3944 REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
3945 REG_WRITE(ah, AR_PCIE_SERDES, 0x000e3007);
3946 REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
3947 }
3948
3949 OS_REG_SET_BIT(ah, AR_PCIE_PM_CTRL, AR_PCIE_PM_CTRL_ENA);
3950
3951 if (ah->ah_config.ath_hal_pcieWaen) {
3952 REG_WRITE(ah, AR_WA, ah->ah_config.ath_hal_pcieWaen);
3953 } else {
3954 if (AR_SREV_9280(ah))
3955 REG_WRITE(ah, AR_WA, 0x0040073f);
3956 else
3957 REG_WRITE(ah, AR_WA, 0x0000073f);
3958 }
3959 }
3960
3961 static inline void
3962 ath9k_hw_get_legacy_target_powers(struct ath_hal *ah,
3963 struct hal_channel_internal *chan,
3964 struct cal_target_power_leg *powInfo,
3965 u_int16_t numChannels,
3966 struct cal_target_power_leg *pNewPower,
3967 u_int16_t numRates,
3968 enum hal_bool isExtTarget)
3969 {
3970 u_int16_t clo, chi;
3971 int i;
3972 int matchIndex = -1, lowIndex = -1;
3973 u_int16_t freq;
3974 struct chan_centers centers;
3975
3976 ath9k_hw_get_channel_centers(ah, chan, &centers);
3977 freq = (isExtTarget) ? centers.ext_center : centers.ctl_center;
3978
3979 if (freq <= ath9k_hw_fbin2freq(powInfo[0].bChannel,
3980 IS_CHAN_2GHZ(chan))) {
3981 matchIndex = 0;
3982 } else {
3983 for (i = 0; (i < numChannels)
3984 && (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
3985 if (freq ==
3986 ath9k_hw_fbin2freq(powInfo[i].bChannel,
3987 IS_CHAN_2GHZ(chan))) {
3988 matchIndex = i;
3989 break;
3990 } else if ((freq <
3991 ath9k_hw_fbin2freq(powInfo[i].bChannel,
3992 IS_CHAN_2GHZ(chan)))
3993 && (freq >
3994 ath9k_hw_fbin2freq(powInfo[i - 1].
3995 bChannel,
3996 IS_CHAN_2GHZ
3997 (chan)))) {
3998 lowIndex = i - 1;
3999 break;
4000 }
4001 }
4002 if ((matchIndex == -1) && (lowIndex == -1))
4003 matchIndex = i - 1;
4004 }
4005
4006 if (matchIndex != -1) {
4007 *pNewPower = powInfo[matchIndex];
4008 } else {
4009 clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel,
4010 IS_CHAN_2GHZ(chan));
4011 chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel,
4012 IS_CHAN_2GHZ(chan));
4013
4014 for (i = 0; i < numRates; i++) {
4015 pNewPower->tPow2x[i] =
4016 (u_int8_t) ath9k_hw_interpolate(freq, clo, chi,
4017 powInfo
4018 [lowIndex].
4019 tPow2x[i],
4020 powInfo
4021 [lowIndex +
4022 1].tPow2x[i]);
4023 }
4024 }
4025 }
4026
4027 static inline void
4028 ath9k_hw_get_target_powers(struct ath_hal *ah,
4029 struct hal_channel_internal *chan,
4030 struct cal_target_power_ht *powInfo,
4031 u_int16_t numChannels,
4032 struct cal_target_power_ht *pNewPower,
4033 u_int16_t numRates,
4034 enum hal_bool isHt40Target)
4035 {
4036 u_int16_t clo, chi;
4037 int i;
4038 int matchIndex = -1, lowIndex = -1;
4039 u_int16_t freq;
4040 struct chan_centers centers;
4041
4042 ath9k_hw_get_channel_centers(ah, chan, &centers);
4043 freq = isHt40Target ? centers.synth_center : centers.ctl_center;
4044
4045 if (freq <=
4046 ath9k_hw_fbin2freq(powInfo[0].bChannel, IS_CHAN_2GHZ(chan))) {
4047 matchIndex = 0;
4048 } else {
4049 for (i = 0; (i < numChannels)
4050 && (powInfo[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
4051 if (freq ==
4052 ath9k_hw_fbin2freq(powInfo[i].bChannel,
4053 IS_CHAN_2GHZ(chan))) {
4054 matchIndex = i;
4055 break;
4056 } else
4057 if ((freq <
4058 ath9k_hw_fbin2freq(powInfo[i].bChannel,
4059 IS_CHAN_2GHZ(chan)))
4060 && (freq >
4061 ath9k_hw_fbin2freq(powInfo[i - 1].
4062 bChannel,
4063 IS_CHAN_2GHZ
4064 (chan)))) {
4065 lowIndex = i - 1;
4066 break;
4067 }
4068 }
4069 if ((matchIndex == -1) && (lowIndex == -1))
4070 matchIndex = i - 1;
4071 }
4072
4073 if (matchIndex != -1) {
4074 *pNewPower = powInfo[matchIndex];
4075 } else {
4076 clo = ath9k_hw_fbin2freq(powInfo[lowIndex].bChannel,
4077 IS_CHAN_2GHZ(chan));
4078 chi = ath9k_hw_fbin2freq(powInfo[lowIndex + 1].bChannel,
4079 IS_CHAN_2GHZ(chan));
4080
4081 for (i = 0; i < numRates; i++) {
4082 pNewPower->tPow2x[i] =
4083 (u_int8_t) ath9k_hw_interpolate(freq, clo, chi,
4084 powInfo
4085 [lowIndex].
4086 tPow2x[i],
4087 powInfo
4088 [lowIndex +
4089 1].tPow2x[i]);
4090 }
4091 }
4092 }
4093
4094 static inline u_int16_t
4095 ath9k_hw_get_max_edge_power(u_int16_t freq,
4096 struct cal_ctl_edges *pRdEdgesPower,
4097 enum hal_bool is2GHz)
4098 {
4099 u_int16_t twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
4100 int i;
4101
4102 for (i = 0; (i < AR5416_NUM_BAND_EDGES)
4103 && (pRdEdgesPower[i].bChannel != AR5416_BCHAN_UNUSED); i++) {
4104 if (freq == ath9k_hw_fbin2freq(pRdEdgesPower[i].bChannel,
4105 is2GHz)) {
4106 twiceMaxEdgePower = pRdEdgesPower[i].tPower;
4107 break;
4108 } else if ((i > 0)
4109 && (freq <
4110 ath9k_hw_fbin2freq(pRdEdgesPower[i].
4111 bChannel, is2GHz))) {
4112 if (ath9k_hw_fbin2freq
4113 (pRdEdgesPower[i - 1].bChannel, is2GHz) < freq
4114 && pRdEdgesPower[i - 1].flag) {
4115 twiceMaxEdgePower =
4116 pRdEdgesPower[i - 1].tPower;
4117 }
4118 break;
4119 }
4120 }
4121 return twiceMaxEdgePower;
4122 }
4123
4124 static inline enum hal_bool
4125 ath9k_hw_set_power_per_rate_table(struct ath_hal *ah,
4126 struct ar5416_eeprom *pEepData,
4127 struct hal_channel_internal *chan,
4128 int16_t *ratesArray,
4129 u_int16_t cfgCtl,
4130 u_int8_t AntennaReduction,
4131 u_int8_t twiceMaxRegulatoryPower,
4132 u_int8_t powerLimit)
4133 {
4134 u_int8_t twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
4135 static const u_int16_t tpScaleReductionTable[5] =
4136 { 0, 3, 6, 9, AR5416_MAX_RATE_POWER };
4137
4138 int i;
4139 int8_t twiceLargestAntenna;
4140 struct cal_ctl_data *rep;
4141 struct cal_target_power_leg targetPowerOfdm, targetPowerCck = {
4142 0, { 0, 0, 0, 0}
4143 };
4144 struct cal_target_power_leg targetPowerOfdmExt = {
4145 0, { 0, 0, 0, 0} }, targetPowerCckExt = {
4146 0, { 0, 0, 0, 0 }
4147 };
4148 struct cal_target_power_ht targetPowerHt20, targetPowerHt40 = {
4149 0, {0, 0, 0, 0}
4150 };
4151 u_int8_t scaledPower = 0, minCtlPower, maxRegAllowedPower;
4152 u_int16_t ctlModesFor11a[] =
4153 { CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40 };
4154 u_int16_t ctlModesFor11g[] =
4155 { CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT, CTL_11G_EXT,
4156 CTL_2GHT40
4157 };
4158 u_int16_t numCtlModes, *pCtlMode, ctlMode, freq;
4159 struct chan_centers centers;
4160 int tx_chainmask;
4161 u_int8_t twiceMinEdgePower;
4162 struct ath_hal_5416 *ahp = AH5416(ah);
4163
4164 tx_chainmask = ahp->ah_txchainmask;
4165
4166 ath9k_hw_get_channel_centers(ah, chan, &centers);
4167
4168 twiceLargestAntenna = max(
4169 pEepData->modalHeader
4170 [IS_CHAN_2GHZ(chan)].antennaGainCh[0],
4171 pEepData->modalHeader
4172 [IS_CHAN_2GHZ(chan)].antennaGainCh[1]);
4173
4174 twiceLargestAntenna = max((u_int8_t) twiceLargestAntenna,
4175 pEepData->modalHeader
4176 [IS_CHAN_2GHZ(chan)].antennaGainCh[2]);
4177
4178 twiceLargestAntenna =
4179 (int8_t) min(AntennaReduction - twiceLargestAntenna, 0);
4180
4181 maxRegAllowedPower = twiceMaxRegulatoryPower + twiceLargestAntenna;
4182
4183 if (ah->ah_tpScale != HAL_TP_SCALE_MAX) {
4184 maxRegAllowedPower -=
4185 (tpScaleReductionTable[(ah->ah_tpScale)] * 2);
4186 }
4187
4188 scaledPower = min(powerLimit, maxRegAllowedPower);
4189
4190 switch (ar5416_get_ntxchains(tx_chainmask)) {
4191 case 1:
4192 break;
4193 case 2:
4194 scaledPower -=
4195 pEepData->modalHeader[IS_CHAN_2GHZ(chan)].
4196 pwrDecreaseFor2Chain;
4197 break;
4198 case 3:
4199 scaledPower -=
4200 pEepData->modalHeader[IS_CHAN_2GHZ(chan)].
4201 pwrDecreaseFor3Chain;
4202 break;
4203 }
4204
4205 scaledPower = max(0, (int32_t) scaledPower);
4206
4207 if (IS_CHAN_2GHZ(chan)) {
4208 numCtlModes =
4209 ARRAY_SIZE(ctlModesFor11g) -
4210 SUB_NUM_CTL_MODES_AT_2G_40;
4211 pCtlMode = ctlModesFor11g;
4212
4213 ath9k_hw_get_legacy_target_powers(ah, chan,
4214 pEepData->
4215 calTargetPowerCck,
4216 AR5416_NUM_2G_CCK_TARGET_POWERS,
4217 &targetPowerCck, 4,
4218 AH_FALSE);
4219 ath9k_hw_get_legacy_target_powers(ah, chan,
4220 pEepData->
4221 calTargetPower2G,
4222 AR5416_NUM_2G_20_TARGET_POWERS,
4223 &targetPowerOfdm, 4,
4224 AH_FALSE);
4225 ath9k_hw_get_target_powers(ah, chan,
4226 pEepData->calTargetPower2GHT20,
4227 AR5416_NUM_2G_20_TARGET_POWERS,
4228 &targetPowerHt20, 8, AH_FALSE);
4229
4230 if (IS_CHAN_HT40(chan)) {
4231 numCtlModes = ARRAY_SIZE(ctlModesFor11g);
4232 ath9k_hw_get_target_powers(ah, chan,
4233 pEepData->
4234 calTargetPower2GHT40,
4235 AR5416_NUM_2G_40_TARGET_POWERS,
4236 &targetPowerHt40, 8,
4237 AH_TRUE);
4238 ath9k_hw_get_legacy_target_powers(ah, chan,
4239 pEepData->
4240 calTargetPowerCck,
4241 AR5416_NUM_2G_CCK_TARGET_POWERS,
4242 &targetPowerCckExt,
4243 4, AH_TRUE);
4244 ath9k_hw_get_legacy_target_powers(ah, chan,
4245 pEepData->
4246 calTargetPower2G,
4247 AR5416_NUM_2G_20_TARGET_POWERS,
4248 &targetPowerOfdmExt,
4249 4, AH_TRUE);
4250 }
4251 } else {
4252
4253 numCtlModes =
4254 ARRAY_SIZE(ctlModesFor11a) -
4255 SUB_NUM_CTL_MODES_AT_5G_40;
4256 pCtlMode = ctlModesFor11a;
4257
4258 ath9k_hw_get_legacy_target_powers(ah, chan,
4259 pEepData->
4260 calTargetPower5G,
4261 AR5416_NUM_5G_20_TARGET_POWERS,
4262 &targetPowerOfdm, 4,
4263 AH_FALSE);
4264 ath9k_hw_get_target_powers(ah, chan,
4265 pEepData->calTargetPower5GHT20,
4266 AR5416_NUM_5G_20_TARGET_POWERS,
4267 &targetPowerHt20, 8, AH_FALSE);
4268
4269 if (IS_CHAN_HT40(chan)) {
4270 numCtlModes = ARRAY_SIZE(ctlModesFor11a);
4271 ath9k_hw_get_target_powers(ah, chan,
4272 pEepData->
4273 calTargetPower5GHT40,
4274 AR5416_NUM_5G_40_TARGET_POWERS,
4275 &targetPowerHt40, 8,
4276 AH_TRUE);
4277 ath9k_hw_get_legacy_target_powers(ah, chan,
4278 pEepData->
4279 calTargetPower5G,
4280 AR5416_NUM_5G_20_TARGET_POWERS,
4281 &targetPowerOfdmExt,
4282 4, AH_TRUE);
4283 }
4284 }
4285
4286 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
4287 enum hal_bool isHt40CtlMode =
4288 (pCtlMode[ctlMode] == CTL_5GHT40)
4289 || (pCtlMode[ctlMode] == CTL_2GHT40);
4290 if (isHt40CtlMode)
4291 freq = centers.synth_center;
4292 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
4293 freq = centers.ext_center;
4294 else
4295 freq = centers.ctl_center;
4296
4297 if (ar5416_get_eep_ver(ahp) == 14
4298 && ar5416_get_eep_rev(ahp) <= 2)
4299 twiceMaxEdgePower = AR5416_MAX_RATE_POWER;
4300
4301 HDPRINTF(ah, HAL_DBG_POWER_MGMT,
4302 "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, "
4303 "EXT_ADDITIVE %d\n",
4304 ctlMode, numCtlModes, isHt40CtlMode,
4305 (pCtlMode[ctlMode] & EXT_ADDITIVE));
4306
4307 for (i = 0; (i < AR5416_NUM_CTLS) && pEepData->ctlIndex[i];
4308 i++) {
4309 HDPRINTF(ah, HAL_DBG_POWER_MGMT,
4310 " LOOP-Ctlidx %d: cfgCtl 0x%2.2x "
4311 "pCtlMode 0x%2.2x ctlIndex 0x%2.2x "
4312 "chan %d chanctl 0x%x\n",
4313 i, cfgCtl, pCtlMode[ctlMode],
4314 pEepData->ctlIndex[i], chan->channel,
4315 chan->conformanceTestLimit);
4316
4317 if ((((cfgCtl & ~CTL_MODE_M) |
4318 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
4319 pEepData->ctlIndex[i])
4320 ||
4321 (((cfgCtl & ~CTL_MODE_M) |
4322 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
4323 ((pEepData->
4324 ctlIndex[i] & CTL_MODE_M) | SD_NO_CTL))) {
4325 rep = &(pEepData->ctlData[i]);
4326
4327 twiceMinEdgePower =
4328 ath9k_hw_get_max_edge_power(freq,
4329 rep->
4330 ctlEdges
4331 [ar5416_get_ntxchains
4332 (tx_chainmask)
4333 - 1],
4334 IS_CHAN_2GHZ
4335 (chan));
4336
4337 HDPRINTF(ah, HAL_DBG_POWER_MGMT,
4338 " MATCH-EE_IDX %d: ch %d is2 %d "
4339 "2xMinEdge %d chainmask %d chains %d\n",
4340 i, freq, IS_CHAN_2GHZ(chan),
4341 twiceMinEdgePower, tx_chainmask,
4342 ar5416_get_ntxchains
4343 (tx_chainmask));
4344 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL) {
4345 twiceMaxEdgePower =
4346 min(twiceMaxEdgePower,
4347 twiceMinEdgePower);
4348 } else {
4349 twiceMaxEdgePower =
4350 twiceMinEdgePower;
4351 break;
4352 }
4353 }
4354 }
4355
4356 minCtlPower = min(twiceMaxEdgePower, scaledPower);
4357
4358 HDPRINTF(ah, HAL_DBG_POWER_MGMT,
4359 " SEL-Min ctlMode %d pCtlMode %d "
4360 "2xMaxEdge %d sP %d minCtlPwr %d\n",
4361 ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
4362 scaledPower, minCtlPower);
4363
4364 switch (pCtlMode[ctlMode]) {
4365 case CTL_11B:
4366 for (i = 0; i < ARRAY_SIZE(targetPowerCck.tPow2x);
4367 i++) {
4368 targetPowerCck.tPow2x[i] =
4369 min(targetPowerCck.tPow2x[i],
4370 minCtlPower);
4371 }
4372 break;
4373 case CTL_11A:
4374 case CTL_11G:
4375 for (i = 0; i < ARRAY_SIZE(targetPowerOfdm.tPow2x);
4376 i++) {
4377 targetPowerOfdm.tPow2x[i] =
4378 min(targetPowerOfdm.tPow2x[i],
4379 minCtlPower);
4380 }
4381 break;
4382 case CTL_5GHT20:
4383 case CTL_2GHT20:
4384 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x);
4385 i++) {
4386 targetPowerHt20.tPow2x[i] =
4387 min(targetPowerHt20.tPow2x[i],
4388 minCtlPower);
4389 }
4390 break;
4391 case CTL_11B_EXT:
4392 targetPowerCckExt.tPow2x[0] =
4393 min(targetPowerCckExt.tPow2x[0], minCtlPower);
4394 break;
4395 case CTL_11A_EXT:
4396 case CTL_11G_EXT:
4397 targetPowerOfdmExt.tPow2x[0] =
4398 min(targetPowerOfdmExt.tPow2x[0], minCtlPower);
4399 break;
4400 case CTL_5GHT40:
4401 case CTL_2GHT40:
4402 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x);
4403 i++) {
4404 targetPowerHt40.tPow2x[i] =
4405 min(targetPowerHt40.tPow2x[i],
4406 minCtlPower);
4407 }
4408 break;
4409 default:
4410 break;
4411 }
4412 }
4413
4414 ratesArray[rate6mb] = ratesArray[rate9mb] = ratesArray[rate12mb] =
4415 ratesArray[rate18mb] = ratesArray[rate24mb] =
4416 targetPowerOfdm.tPow2x[0];
4417 ratesArray[rate36mb] = targetPowerOfdm.tPow2x[1];
4418 ratesArray[rate48mb] = targetPowerOfdm.tPow2x[2];
4419 ratesArray[rate54mb] = targetPowerOfdm.tPow2x[3];
4420 ratesArray[rateXr] = targetPowerOfdm.tPow2x[0];
4421
4422 for (i = 0; i < ARRAY_SIZE(targetPowerHt20.tPow2x); i++)
4423 ratesArray[rateHt20_0 + i] = targetPowerHt20.tPow2x[i];
4424
4425 if (IS_CHAN_2GHZ(chan)) {
4426 ratesArray[rate1l] = targetPowerCck.tPow2x[0];
4427 ratesArray[rate2s] = ratesArray[rate2l] =
4428 targetPowerCck.tPow2x[1];
4429 ratesArray[rate5_5s] = ratesArray[rate5_5l] =
4430 targetPowerCck.tPow2x[2];
4431 ;
4432 ratesArray[rate11s] = ratesArray[rate11l] =
4433 targetPowerCck.tPow2x[3];
4434 ;
4435 }
4436 if (IS_CHAN_HT40(chan)) {
4437 for (i = 0; i < ARRAY_SIZE(targetPowerHt40.tPow2x); i++) {
4438 ratesArray[rateHt40_0 + i] =
4439 targetPowerHt40.tPow2x[i];
4440 }
4441 ratesArray[rateDupOfdm] = targetPowerHt40.tPow2x[0];
4442 ratesArray[rateDupCck] = targetPowerHt40.tPow2x[0];
4443 ratesArray[rateExtOfdm] = targetPowerOfdmExt.tPow2x[0];
4444 if (IS_CHAN_2GHZ(chan)) {
4445 ratesArray[rateExtCck] =
4446 targetPowerCckExt.tPow2x[0];
4447 }
4448 }
4449 return AH_TRUE;
4450 }
4451
4452 static enum hal_status
4453 ath9k_hw_set_txpower(struct ath_hal *ah,
4454 struct ar5416_eeprom *pEepData,
4455 struct hal_channel_internal *chan,
4456 u_int16_t cfgCtl,
4457 u_int8_t twiceAntennaReduction,
4458 u_int8_t twiceMaxRegulatoryPower,
4459 u_int8_t powerLimit)
4460 {
4461 struct modal_eep_header *pModal =
4462 &(pEepData->modalHeader[IS_CHAN_2GHZ(chan)]);
4463 int16_t ratesArray[Ar5416RateSize];
4464 int16_t txPowerIndexOffset = 0;
4465 u_int8_t ht40PowerIncForPdadc = 2;
4466 int i;
4467
4468 memset(ratesArray, 0, sizeof(ratesArray));
4469
4470 if ((pEepData->baseEepHeader.
4471 version & AR5416_EEP_VER_MINOR_MASK) >=
4472 AR5416_EEP_MINOR_VER_2) {
4473 ht40PowerIncForPdadc = pModal->ht40PowerIncForPdadc;
4474 }
4475
4476 if (!ath9k_hw_set_power_per_rate_table(ah, pEepData, chan,
4477 &ratesArray[0], cfgCtl,
4478 twiceAntennaReduction,
4479 twiceMaxRegulatoryPower,
4480 powerLimit)) {
4481 HDPRINTF(ah, HAL_DBG_EEPROM,
4482 "ath9k_hw_set_txpower: unable to set "
4483 "tx power per rate table\n");
4484 return HAL_EIO;
4485 }
4486
4487 if (!ath9k_hw_set_power_cal_table
4488 (ah, pEepData, chan, &txPowerIndexOffset)) {
4489 HDPRINTF(ah, HAL_DBG_EEPROM,
4490 "ath9k_hw_set_txpower: unable to set power table\n");
4491 return HAL_EIO;
4492 }
4493
4494 for (i = 0; i < ARRAY_SIZE(ratesArray); i++) {
4495 ratesArray[i] =
4496 (int16_t) (txPowerIndexOffset + ratesArray[i]);
4497 if (ratesArray[i] > AR5416_MAX_RATE_POWER)
4498 ratesArray[i] = AR5416_MAX_RATE_POWER;
4499 }
4500
4501 if (AR_SREV_9280_10_OR_LATER(ah)) {
4502 for (i = 0; i < Ar5416RateSize; i++)
4503 ratesArray[i] -= AR5416_PWR_TABLE_OFFSET * 2;
4504 }
4505
4506 REG_WRITE(ah, AR_PHY_POWER_TX_RATE1,
4507 ATH9K_POW_SM(ratesArray[rate18mb], 24)
4508 | ATH9K_POW_SM(ratesArray[rate12mb], 16)
4509 | ATH9K_POW_SM(ratesArray[rate9mb], 8)
4510 | ATH9K_POW_SM(ratesArray[rate6mb], 0)
4511 );
4512 REG_WRITE(ah, AR_PHY_POWER_TX_RATE2,
4513 ATH9K_POW_SM(ratesArray[rate54mb], 24)
4514 | ATH9K_POW_SM(ratesArray[rate48mb], 16)
4515 | ATH9K_POW_SM(ratesArray[rate36mb], 8)
4516 | ATH9K_POW_SM(ratesArray[rate24mb], 0)
4517 );
4518
4519 if (IS_CHAN_2GHZ(chan)) {
4520 REG_WRITE(ah, AR_PHY_POWER_TX_RATE3,
4521 ATH9K_POW_SM(ratesArray[rate2s], 24)
4522 | ATH9K_POW_SM(ratesArray[rate2l], 16)
4523 | ATH9K_POW_SM(ratesArray[rateXr], 8)
4524 | ATH9K_POW_SM(ratesArray[rate1l], 0)
4525 );
4526 REG_WRITE(ah, AR_PHY_POWER_TX_RATE4,
4527 ATH9K_POW_SM(ratesArray[rate11s], 24)
4528 | ATH9K_POW_SM(ratesArray[rate11l], 16)
4529 | ATH9K_POW_SM(ratesArray[rate5_5s], 8)
4530 | ATH9K_POW_SM(ratesArray[rate5_5l], 0)
4531 );
4532 }
4533
4534 REG_WRITE(ah, AR_PHY_POWER_TX_RATE5,
4535 ATH9K_POW_SM(ratesArray[rateHt20_3], 24)
4536 | ATH9K_POW_SM(ratesArray[rateHt20_2], 16)
4537 | ATH9K_POW_SM(ratesArray[rateHt20_1], 8)
4538 | ATH9K_POW_SM(ratesArray[rateHt20_0], 0)
4539 );
4540 REG_WRITE(ah, AR_PHY_POWER_TX_RATE6,
4541 ATH9K_POW_SM(ratesArray[rateHt20_7], 24)
4542 | ATH9K_POW_SM(ratesArray[rateHt20_6], 16)
4543 | ATH9K_POW_SM(ratesArray[rateHt20_5], 8)
4544 | ATH9K_POW_SM(ratesArray[rateHt20_4], 0)
4545 );
4546
4547 if (IS_CHAN_HT40(chan)) {
4548 REG_WRITE(ah, AR_PHY_POWER_TX_RATE7,
4549 ATH9K_POW_SM(ratesArray[rateHt40_3] +
4550 ht40PowerIncForPdadc, 24)
4551 | ATH9K_POW_SM(ratesArray[rateHt40_2] +
4552 ht40PowerIncForPdadc, 16)
4553 | ATH9K_POW_SM(ratesArray[rateHt40_1] +
4554 ht40PowerIncForPdadc, 8)
4555 | ATH9K_POW_SM(ratesArray[rateHt40_0] +
4556 ht40PowerIncForPdadc, 0)
4557 );
4558 REG_WRITE(ah, AR_PHY_POWER_TX_RATE8,
4559 ATH9K_POW_SM(ratesArray[rateHt40_7] +
4560 ht40PowerIncForPdadc, 24)
4561 | ATH9K_POW_SM(ratesArray[rateHt40_6] +
4562 ht40PowerIncForPdadc, 16)
4563 | ATH9K_POW_SM(ratesArray[rateHt40_5] +
4564 ht40PowerIncForPdadc, 8)
4565 | ATH9K_POW_SM(ratesArray[rateHt40_4] +
4566 ht40PowerIncForPdadc, 0)
4567 );
4568
4569 REG_WRITE(ah, AR_PHY_POWER_TX_RATE9,
4570 ATH9K_POW_SM(ratesArray[rateExtOfdm], 24)
4571 | ATH9K_POW_SM(ratesArray[rateExtCck], 16)
4572 | ATH9K_POW_SM(ratesArray[rateDupOfdm], 8)
4573 | ATH9K_POW_SM(ratesArray[rateDupCck], 0)
4574 );
4575 }
4576
4577 REG_WRITE(ah, AR_PHY_POWER_TX_SUB,
4578 ATH9K_POW_SM(pModal->pwrDecreaseFor3Chain, 6)
4579 | ATH9K_POW_SM(pModal->pwrDecreaseFor2Chain, 0)
4580 );
4581
4582 i = rate6mb;
4583 if (IS_CHAN_HT40(chan))
4584 i = rateHt40_0;
4585 else if (IS_CHAN_HT20(chan))
4586 i = rateHt20_0;
4587
4588 if (AR_SREV_9280_10_OR_LATER(ah))
4589 ah->ah_maxPowerLevel =
4590 ratesArray[i] + AR5416_PWR_TABLE_OFFSET * 2;
4591 else
4592 ah->ah_maxPowerLevel = ratesArray[i];
4593
4594 return HAL_OK;
4595 }
4596
4597 static inline void ath9k_hw_get_delta_slope_vals(struct ath_hal *ah,
4598 u_int32_t coef_scaled,
4599 u_int32_t *coef_mantissa,
4600 u_int32_t *coef_exponent)
4601 {
4602 u_int32_t coef_exp, coef_man;
4603
4604 for (coef_exp = 31; coef_exp > 0; coef_exp--)
4605 if ((coef_scaled >> coef_exp) & 0x1)
4606 break;
4607
4608 coef_exp = 14 - (coef_exp - COEF_SCALE_S);
4609
4610 coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
4611
4612 *coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
4613 *coef_exponent = coef_exp - 16;
4614 }
4615
4616 static void
4617 ath9k_hw_set_delta_slope(struct ath_hal *ah,
4618 struct hal_channel_internal *chan)
4619 {
4620 u_int32_t coef_scaled, ds_coef_exp, ds_coef_man;
4621 u_int32_t clockMhzScaled = 0x64000000;
4622 struct chan_centers centers;
4623
4624 if (IS_CHAN_HALF_RATE(chan))
4625 clockMhzScaled = clockMhzScaled >> 1;
4626 else if (IS_CHAN_QUARTER_RATE(chan))
4627 clockMhzScaled = clockMhzScaled >> 2;
4628
4629 ath9k_hw_get_channel_centers(ah, chan, &centers);
4630 coef_scaled = clockMhzScaled / centers.synth_center;
4631
4632 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
4633 &ds_coef_exp);
4634
4635 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING3,
4636 AR_PHY_TIMING3_DSC_MAN, ds_coef_man);
4637 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING3,
4638 AR_PHY_TIMING3_DSC_EXP, ds_coef_exp);
4639
4640 coef_scaled = (9 * coef_scaled) / 10;
4641
4642 ath9k_hw_get_delta_slope_vals(ah, coef_scaled, &ds_coef_man,
4643 &ds_coef_exp);
4644
4645 OS_REG_RMW_FIELD(ah, AR_PHY_HALFGI,
4646 AR_PHY_HALFGI_DSC_MAN, ds_coef_man);
4647 OS_REG_RMW_FIELD(ah, AR_PHY_HALFGI,
4648 AR_PHY_HALFGI_DSC_EXP, ds_coef_exp);
4649 }
4650
4651 static void ath9k_hw_9280_spur_mitigate(struct ath_hal *ah,
4652 struct hal_channel *chan,
4653 struct hal_channel_internal *ichan)
4654 {
4655 int bb_spur = AR_NO_SPUR;
4656 int freq;
4657 int bin, cur_bin;
4658 int bb_spur_off, spur_subchannel_sd;
4659 int spur_freq_sd;
4660 int spur_delta_phase;
4661 int denominator;
4662 int upper, lower, cur_vit_mask;
4663 int tmp, newVal;
4664 int i;
4665 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
4666 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
4667 };
4668 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
4669 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
4670 };
4671 int inc[4] = { 0, 100, 0, 0 };
4672 struct chan_centers centers;
4673
4674 int8_t mask_m[123];
4675 int8_t mask_p[123];
4676 int8_t mask_amt;
4677 int tmp_mask;
4678 int cur_bb_spur;
4679 enum hal_bool is2GHz = IS_CHAN_2GHZ(chan);
4680
4681 memset(&mask_m, 0, sizeof(int8_t) * 123);
4682 memset(&mask_p, 0, sizeof(int8_t) * 123);
4683
4684 ath9k_hw_get_channel_centers(ah, ichan, &centers);
4685 freq = centers.synth_center;
4686
4687 ah->ah_config.ath_hal_spurMode = SPUR_ENABLE_EEPROM;
4688 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
4689 cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz);
4690
4691 if (is2GHz)
4692 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_2GHZ;
4693 else
4694 cur_bb_spur = (cur_bb_spur / 10) + AR_BASE_FREQ_5GHZ;
4695
4696 if (AR_NO_SPUR == cur_bb_spur)
4697 break;
4698 cur_bb_spur = cur_bb_spur - freq;
4699
4700 if (IS_CHAN_HT40(chan)) {
4701 if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT40) &&
4702 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT40)) {
4703 bb_spur = cur_bb_spur;
4704 break;
4705 }
4706 } else if ((cur_bb_spur > -AR_SPUR_FEEQ_BOUND_HT20) &&
4707 (cur_bb_spur < AR_SPUR_FEEQ_BOUND_HT20)) {
4708 bb_spur = cur_bb_spur;
4709 break;
4710 }
4711 }
4712
4713 if (AR_NO_SPUR == bb_spur) {
4714 OS_REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
4715 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
4716 return;
4717 } else {
4718 OS_REG_CLR_BIT(ah, AR_PHY_FORCE_CLKEN_CCK,
4719 AR_PHY_FORCE_CLKEN_CCK_MRC_MUX);
4720 }
4721
4722 bin = bb_spur * 320;
4723
4724 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
4725
4726 newVal = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
4727 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
4728 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
4729 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
4730 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), newVal);
4731
4732 newVal = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
4733 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
4734 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
4735 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
4736 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
4737 REG_WRITE(ah, AR_PHY_SPUR_REG, newVal);
4738
4739 if (IS_CHAN_HT40(chan)) {
4740 if (bb_spur < 0) {
4741 spur_subchannel_sd = 1;
4742 bb_spur_off = bb_spur + 10;
4743 } else {
4744 spur_subchannel_sd = 0;
4745 bb_spur_off = bb_spur - 10;
4746 }
4747 } else {
4748 spur_subchannel_sd = 0;
4749 bb_spur_off = bb_spur;
4750 }
4751
4752 if (IS_CHAN_HT40(chan))
4753 spur_delta_phase =
4754 ((bb_spur * 262144) /
4755 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
4756 else
4757 spur_delta_phase =
4758 ((bb_spur * 524288) /
4759 10) & AR_PHY_TIMING11_SPUR_DELTA_PHASE;
4760
4761 denominator = IS_CHAN_2GHZ(chan) ? 44 : 40;
4762 spur_freq_sd = ((bb_spur_off * 2048) / denominator) & 0x3ff;
4763
4764 newVal = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
4765 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
4766 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
4767 REG_WRITE(ah, AR_PHY_TIMING11, newVal);
4768
4769 newVal = spur_subchannel_sd << AR_PHY_SFCORR_SPUR_SUBCHNL_SD_S;
4770 REG_WRITE(ah, AR_PHY_SFCORR_EXT, newVal);
4771
4772 cur_bin = -6000;
4773 upper = bin + 100;
4774 lower = bin - 100;
4775
4776 for (i = 0; i < 4; i++) {
4777 int pilot_mask = 0;
4778 int chan_mask = 0;
4779 int bp = 0;
4780 for (bp = 0; bp < 30; bp++) {
4781 if ((cur_bin > lower) && (cur_bin < upper)) {
4782 pilot_mask = pilot_mask | 0x1 << bp;
4783 chan_mask = chan_mask | 0x1 << bp;
4784 }
4785 cur_bin += 100;
4786 }
4787 cur_bin += inc[i];
4788 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
4789 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
4790 }
4791
4792 cur_vit_mask = 6100;
4793 upper = bin + 120;
4794 lower = bin - 120;
4795
4796 for (i = 0; i < 123; i++) {
4797 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
4798 if ((abs(cur_vit_mask - bin)) < 75)
4799 mask_amt = 1;
4800 else
4801 mask_amt = 0;
4802 if (cur_vit_mask < 0)
4803 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
4804 else
4805 mask_p[cur_vit_mask / 100] = mask_amt;
4806 }
4807 cur_vit_mask -= 100;
4808 }
4809
4810 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
4811 | (mask_m[48] << 26) | (mask_m[49] << 24)
4812 | (mask_m[50] << 22) | (mask_m[51] << 20)
4813 | (mask_m[52] << 18) | (mask_m[53] << 16)
4814 | (mask_m[54] << 14) | (mask_m[55] << 12)
4815 | (mask_m[56] << 10) | (mask_m[57] << 8)
4816 | (mask_m[58] << 6) | (mask_m[59] << 4)
4817 | (mask_m[60] << 2) | (mask_m[61] << 0);
4818 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
4819 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
4820
4821 tmp_mask = (mask_m[31] << 28)
4822 | (mask_m[32] << 26) | (mask_m[33] << 24)
4823 | (mask_m[34] << 22) | (mask_m[35] << 20)
4824 | (mask_m[36] << 18) | (mask_m[37] << 16)
4825 | (mask_m[48] << 14) | (mask_m[39] << 12)
4826 | (mask_m[40] << 10) | (mask_m[41] << 8)
4827 | (mask_m[42] << 6) | (mask_m[43] << 4)
4828 | (mask_m[44] << 2) | (mask_m[45] << 0);
4829 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
4830 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
4831
4832 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
4833 | (mask_m[18] << 26) | (mask_m[18] << 24)
4834 | (mask_m[20] << 22) | (mask_m[20] << 20)
4835 | (mask_m[22] << 18) | (mask_m[22] << 16)
4836 | (mask_m[24] << 14) | (mask_m[24] << 12)
4837 | (mask_m[25] << 10) | (mask_m[26] << 8)
4838 | (mask_m[27] << 6) | (mask_m[28] << 4)
4839 | (mask_m[29] << 2) | (mask_m[30] << 0);
4840 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
4841 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
4842
4843 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
4844 | (mask_m[2] << 26) | (mask_m[3] << 24)
4845 | (mask_m[4] << 22) | (mask_m[5] << 20)
4846 | (mask_m[6] << 18) | (mask_m[7] << 16)
4847 | (mask_m[8] << 14) | (mask_m[9] << 12)
4848 | (mask_m[10] << 10) | (mask_m[11] << 8)
4849 | (mask_m[12] << 6) | (mask_m[13] << 4)
4850 | (mask_m[14] << 2) | (mask_m[15] << 0);
4851 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
4852 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
4853
4854 tmp_mask = (mask_p[15] << 28)
4855 | (mask_p[14] << 26) | (mask_p[13] << 24)
4856 | (mask_p[12] << 22) | (mask_p[11] << 20)
4857 | (mask_p[10] << 18) | (mask_p[9] << 16)
4858 | (mask_p[8] << 14) | (mask_p[7] << 12)
4859 | (mask_p[6] << 10) | (mask_p[5] << 8)
4860 | (mask_p[4] << 6) | (mask_p[3] << 4)
4861 | (mask_p[2] << 2) | (mask_p[1] << 0);
4862 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
4863 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
4864
4865 tmp_mask = (mask_p[30] << 28)
4866 | (mask_p[29] << 26) | (mask_p[28] << 24)
4867 | (mask_p[27] << 22) | (mask_p[26] << 20)
4868 | (mask_p[25] << 18) | (mask_p[24] << 16)
4869 | (mask_p[23] << 14) | (mask_p[22] << 12)
4870 | (mask_p[21] << 10) | (mask_p[20] << 8)
4871 | (mask_p[19] << 6) | (mask_p[18] << 4)
4872 | (mask_p[17] << 2) | (mask_p[16] << 0);
4873 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
4874 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
4875
4876 tmp_mask = (mask_p[45] << 28)
4877 | (mask_p[44] << 26) | (mask_p[43] << 24)
4878 | (mask_p[42] << 22) | (mask_p[41] << 20)
4879 | (mask_p[40] << 18) | (mask_p[39] << 16)
4880 | (mask_p[38] << 14) | (mask_p[37] << 12)
4881 | (mask_p[36] << 10) | (mask_p[35] << 8)
4882 | (mask_p[34] << 6) | (mask_p[33] << 4)
4883 | (mask_p[32] << 2) | (mask_p[31] << 0);
4884 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
4885 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
4886
4887 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
4888 | (mask_p[59] << 26) | (mask_p[58] << 24)
4889 | (mask_p[57] << 22) | (mask_p[56] << 20)
4890 | (mask_p[55] << 18) | (mask_p[54] << 16)
4891 | (mask_p[53] << 14) | (mask_p[52] << 12)
4892 | (mask_p[51] << 10) | (mask_p[50] << 8)
4893 | (mask_p[49] << 6) | (mask_p[48] << 4)
4894 | (mask_p[47] << 2) | (mask_p[46] << 0);
4895 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
4896 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
4897 }
4898
4899 static void ath9k_hw_spur_mitigate(struct ath_hal *ah,
4900 struct hal_channel *chan)
4901 {
4902 int bb_spur = AR_NO_SPUR;
4903 int bin, cur_bin;
4904 int spur_freq_sd;
4905 int spur_delta_phase;
4906 int denominator;
4907 int upper, lower, cur_vit_mask;
4908 int tmp, new;
4909 int i;
4910 int pilot_mask_reg[4] = { AR_PHY_TIMING7, AR_PHY_TIMING8,
4911 AR_PHY_PILOT_MASK_01_30, AR_PHY_PILOT_MASK_31_60
4912 };
4913 int chan_mask_reg[4] = { AR_PHY_TIMING9, AR_PHY_TIMING10,
4914 AR_PHY_CHANNEL_MASK_01_30, AR_PHY_CHANNEL_MASK_31_60
4915 };
4916 int inc[4] = { 0, 100, 0, 0 };
4917
4918 int8_t mask_m[123];
4919 int8_t mask_p[123];
4920 int8_t mask_amt;
4921 int tmp_mask;
4922 int cur_bb_spur;
4923 enum hal_bool is2GHz = IS_CHAN_2GHZ(chan);
4924
4925 memset(&mask_m, 0, sizeof(int8_t) * 123);
4926 memset(&mask_p, 0, sizeof(int8_t) * 123);
4927
4928 for (i = 0; i < AR_EEPROM_MODAL_SPURS; i++) {
4929 cur_bb_spur = ath9k_hw_eeprom_get_spur_chan(ah, i, is2GHz);
4930 if (AR_NO_SPUR == cur_bb_spur)
4931 break;
4932 cur_bb_spur = cur_bb_spur - (chan->channel * 10);
4933 if ((cur_bb_spur > -95) && (cur_bb_spur < 95)) {
4934 bb_spur = cur_bb_spur;
4935 break;
4936 }
4937 }
4938
4939 if (AR_NO_SPUR == bb_spur)
4940 return;
4941
4942 bin = bb_spur * 32;
4943
4944 tmp = REG_READ(ah, AR_PHY_TIMING_CTRL4(0));
4945 new = tmp | (AR_PHY_TIMING_CTRL4_ENABLE_SPUR_RSSI |
4946 AR_PHY_TIMING_CTRL4_ENABLE_SPUR_FILTER |
4947 AR_PHY_TIMING_CTRL4_ENABLE_CHAN_MASK |
4948 AR_PHY_TIMING_CTRL4_ENABLE_PILOT_MASK);
4949
4950 REG_WRITE(ah, AR_PHY_TIMING_CTRL4(0), new);
4951
4952 new = (AR_PHY_SPUR_REG_MASK_RATE_CNTL |
4953 AR_PHY_SPUR_REG_ENABLE_MASK_PPM |
4954 AR_PHY_SPUR_REG_MASK_RATE_SELECT |
4955 AR_PHY_SPUR_REG_ENABLE_VIT_SPUR_RSSI |
4956 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH));
4957 REG_WRITE(ah, AR_PHY_SPUR_REG, new);
4958
4959 spur_delta_phase = ((bb_spur * 524288) / 100) &
4960 AR_PHY_TIMING11_SPUR_DELTA_PHASE;
4961
4962 denominator = IS_CHAN_2GHZ(chan) ? 440 : 400;
4963 spur_freq_sd = ((bb_spur * 2048) / denominator) & 0x3ff;
4964
4965 new = (AR_PHY_TIMING11_USE_SPUR_IN_AGC |
4966 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) |
4967 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE));
4968 REG_WRITE(ah, AR_PHY_TIMING11, new);
4969
4970 cur_bin = -6000;
4971 upper = bin + 100;
4972 lower = bin - 100;
4973
4974 for (i = 0; i < 4; i++) {
4975 int pilot_mask = 0;
4976 int chan_mask = 0;
4977 int bp = 0;
4978 for (bp = 0; bp < 30; bp++) {
4979 if ((cur_bin > lower) && (cur_bin < upper)) {
4980 pilot_mask = pilot_mask | 0x1 << bp;
4981 chan_mask = chan_mask | 0x1 << bp;
4982 }
4983 cur_bin += 100;
4984 }
4985 cur_bin += inc[i];
4986 REG_WRITE(ah, pilot_mask_reg[i], pilot_mask);
4987 REG_WRITE(ah, chan_mask_reg[i], chan_mask);
4988 }
4989
4990 cur_vit_mask = 6100;
4991 upper = bin + 120;
4992 lower = bin - 120;
4993
4994 for (i = 0; i < 123; i++) {
4995 if ((cur_vit_mask > lower) && (cur_vit_mask < upper)) {
4996 if ((abs(cur_vit_mask - bin)) < 75)
4997 mask_amt = 1;
4998 else
4999 mask_amt = 0;
5000 if (cur_vit_mask < 0)
5001 mask_m[abs(cur_vit_mask / 100)] = mask_amt;
5002 else
5003 mask_p[cur_vit_mask / 100] = mask_amt;
5004 }
5005 cur_vit_mask -= 100;
5006 }
5007
5008 tmp_mask = (mask_m[46] << 30) | (mask_m[47] << 28)
5009 | (mask_m[48] << 26) | (mask_m[49] << 24)
5010 | (mask_m[50] << 22) | (mask_m[51] << 20)
5011 | (mask_m[52] << 18) | (mask_m[53] << 16)
5012 | (mask_m[54] << 14) | (mask_m[55] << 12)
5013 | (mask_m[56] << 10) | (mask_m[57] << 8)
5014 | (mask_m[58] << 6) | (mask_m[59] << 4)
5015 | (mask_m[60] << 2) | (mask_m[61] << 0);
5016 REG_WRITE(ah, AR_PHY_BIN_MASK_1, tmp_mask);
5017 REG_WRITE(ah, AR_PHY_VIT_MASK2_M_46_61, tmp_mask);
5018
5019 tmp_mask = (mask_m[31] << 28)
5020 | (mask_m[32] << 26) | (mask_m[33] << 24)
5021 | (mask_m[34] << 22) | (mask_m[35] << 20)
5022 | (mask_m[36] << 18) | (mask_m[37] << 16)
5023 | (mask_m[48] << 14) | (mask_m[39] << 12)
5024 | (mask_m[40] << 10) | (mask_m[41] << 8)
5025 | (mask_m[42] << 6) | (mask_m[43] << 4)
5026 | (mask_m[44] << 2) | (mask_m[45] << 0);
5027 REG_WRITE(ah, AR_PHY_BIN_MASK_2, tmp_mask);
5028 REG_WRITE(ah, AR_PHY_MASK2_M_31_45, tmp_mask);
5029
5030 tmp_mask = (mask_m[16] << 30) | (mask_m[16] << 28)
5031 | (mask_m[18] << 26) | (mask_m[18] << 24)
5032 | (mask_m[20] << 22) | (mask_m[20] << 20)
5033 | (mask_m[22] << 18) | (mask_m[22] << 16)
5034 | (mask_m[24] << 14) | (mask_m[24] << 12)
5035 | (mask_m[25] << 10) | (mask_m[26] << 8)
5036 | (mask_m[27] << 6) | (mask_m[28] << 4)
5037 | (mask_m[29] << 2) | (mask_m[30] << 0);
5038 REG_WRITE(ah, AR_PHY_BIN_MASK_3, tmp_mask);
5039 REG_WRITE(ah, AR_PHY_MASK2_M_16_30, tmp_mask);
5040
5041 tmp_mask = (mask_m[0] << 30) | (mask_m[1] << 28)
5042 | (mask_m[2] << 26) | (mask_m[3] << 24)
5043 | (mask_m[4] << 22) | (mask_m[5] << 20)
5044 | (mask_m[6] << 18) | (mask_m[7] << 16)
5045 | (mask_m[8] << 14) | (mask_m[9] << 12)
5046 | (mask_m[10] << 10) | (mask_m[11] << 8)
5047 | (mask_m[12] << 6) | (mask_m[13] << 4)
5048 | (mask_m[14] << 2) | (mask_m[15] << 0);
5049 REG_WRITE(ah, AR_PHY_MASK_CTL, tmp_mask);
5050 REG_WRITE(ah, AR_PHY_MASK2_M_00_15, tmp_mask);
5051
5052 tmp_mask = (mask_p[15] << 28)
5053 | (mask_p[14] << 26) | (mask_p[13] << 24)
5054 | (mask_p[12] << 22) | (mask_p[11] << 20)
5055 | (mask_p[10] << 18) | (mask_p[9] << 16)
5056 | (mask_p[8] << 14) | (mask_p[7] << 12)
5057 | (mask_p[6] << 10) | (mask_p[5] << 8)
5058 | (mask_p[4] << 6) | (mask_p[3] << 4)
5059 | (mask_p[2] << 2) | (mask_p[1] << 0);
5060 REG_WRITE(ah, AR_PHY_BIN_MASK2_1, tmp_mask);
5061 REG_WRITE(ah, AR_PHY_MASK2_P_15_01, tmp_mask);
5062
5063 tmp_mask = (mask_p[30] << 28)
5064 | (mask_p[29] << 26) | (mask_p[28] << 24)
5065 | (mask_p[27] << 22) | (mask_p[26] << 20)
5066 | (mask_p[25] << 18) | (mask_p[24] << 16)
5067 | (mask_p[23] << 14) | (mask_p[22] << 12)
5068 | (mask_p[21] << 10) | (mask_p[20] << 8)
5069 | (mask_p[19] << 6) | (mask_p[18] << 4)
5070 | (mask_p[17] << 2) | (mask_p[16] << 0);
5071 REG_WRITE(ah, AR_PHY_BIN_MASK2_2, tmp_mask);
5072 REG_WRITE(ah, AR_PHY_MASK2_P_30_16, tmp_mask);
5073
5074 tmp_mask = (mask_p[45] << 28)
5075 | (mask_p[44] << 26) | (mask_p[43] << 24)
5076 | (mask_p[42] << 22) | (mask_p[41] << 20)
5077 | (mask_p[40] << 18) | (mask_p[39] << 16)
5078 | (mask_p[38] << 14) | (mask_p[37] << 12)
5079 | (mask_p[36] << 10) | (mask_p[35] << 8)
5080 | (mask_p[34] << 6) | (mask_p[33] << 4)
5081 | (mask_p[32] << 2) | (mask_p[31] << 0);
5082 REG_WRITE(ah, AR_PHY_BIN_MASK2_3, tmp_mask);
5083 REG_WRITE(ah, AR_PHY_MASK2_P_45_31, tmp_mask);
5084
5085 tmp_mask = (mask_p[61] << 30) | (mask_p[60] << 28)
5086 | (mask_p[59] << 26) | (mask_p[58] << 24)
5087 | (mask_p[57] << 22) | (mask_p[56] << 20)
5088 | (mask_p[55] << 18) | (mask_p[54] << 16)
5089 | (mask_p[53] << 14) | (mask_p[52] << 12)
5090 | (mask_p[51] << 10) | (mask_p[50] << 8)
5091 | (mask_p[49] << 6) | (mask_p[48] << 4)
5092 | (mask_p[47] << 2) | (mask_p[46] << 0);
5093 REG_WRITE(ah, AR_PHY_BIN_MASK2_4, tmp_mask);
5094 REG_WRITE(ah, AR_PHY_MASK2_P_61_45, tmp_mask);
5095 }
5096
5097 static inline void ath9k_hw_init_chain_masks(struct ath_hal *ah)
5098 {
5099 struct ath_hal_5416 *ahp = AH5416(ah);
5100 int rx_chainmask, tx_chainmask;
5101
5102 rx_chainmask = ahp->ah_rxchainmask;
5103 tx_chainmask = ahp->ah_txchainmask;
5104
5105 switch (rx_chainmask) {
5106 case 0x5:
5107 OS_REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
5108 AR_PHY_SWAP_ALT_CHAIN);
5109 case 0x3:
5110 if (((ah)->ah_macVersion <= AR_SREV_VERSION_9160)) {
5111 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, 0x7);
5112 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, 0x7);
5113 break;
5114 }
5115 case 0x1:
5116 case 0x2:
5117 if (!AR_SREV_9280(ah))
5118 break;
5119 case 0x7:
5120 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
5121 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
5122 break;
5123 default:
5124 break;
5125 }
5126
5127 REG_WRITE(ah, AR_SELFGEN_MASK, tx_chainmask);
5128 if (tx_chainmask == 0x5) {
5129 OS_REG_SET_BIT(ah, AR_PHY_ANALOG_SWAP,
5130 AR_PHY_SWAP_ALT_CHAIN);
5131 }
5132 if (AR_SREV_9100(ah))
5133 REG_WRITE(ah, AR_PHY_ANALOG_SWAP,
5134 REG_READ(ah, AR_PHY_ANALOG_SWAP) | 0x00000001);
5135 }
5136
5137 static void ath9k_hw_set_addac(struct ath_hal *ah,
5138 struct hal_channel_internal *chan)
5139 {
5140 struct modal_eep_header *pModal;
5141 struct ath_hal_5416 *ahp = AH5416(ah);
5142 struct ar5416_eeprom *eep = &ahp->ah_eeprom;
5143 u_int8_t biaslevel;
5144
5145 if (ah->ah_macVersion != AR_SREV_VERSION_9160)
5146 return;
5147
5148 if (ar5416_get_eep_rev(ahp) < AR5416_EEP_MINOR_VER_7)
5149 return;
5150
5151 pModal = &(eep->modalHeader[IS_CHAN_2GHZ(chan)]);
5152
5153 if (pModal->xpaBiasLvl != 0xff) {
5154 biaslevel = pModal->xpaBiasLvl;
5155 } else {
5156
5157 u_int16_t resetFreqBin, freqBin, freqCount = 0;
5158 struct chan_centers centers;
5159
5160 ath9k_hw_get_channel_centers(ah, chan, &centers);
5161
5162 resetFreqBin =
5163 FREQ2FBIN(centers.synth_center, IS_CHAN_2GHZ(chan));
5164 freqBin = pModal->xpaBiasLvlFreq[0] & 0xff;
5165 biaslevel = (u_int8_t) (pModal->xpaBiasLvlFreq[0] >> 14);
5166
5167 freqCount++;
5168
5169 while (freqCount < 3) {
5170 if (pModal->xpaBiasLvlFreq[freqCount] == 0x0)
5171 break;
5172
5173 freqBin = pModal->xpaBiasLvlFreq[freqCount] & 0xff;
5174 if (resetFreqBin >= freqBin) {
5175 biaslevel =
5176 (u_int8_t) (pModal->
5177 xpaBiasLvlFreq[freqCount]
5178 >> 14);
5179 } else {
5180 break;
5181 }
5182 freqCount++;
5183 }
5184 }
5185
5186 if (IS_CHAN_2GHZ(chan)) {
5187 INI_RA(&ahp->ah_iniAddac, 7, 1) =
5188 (INI_RA(&ahp->ah_iniAddac, 7, 1) & (~0x18)) | biaslevel
5189 << 3;
5190 } else {
5191 INI_RA(&ahp->ah_iniAddac, 6, 1) =
5192 (INI_RA(&ahp->ah_iniAddac, 6, 1) & (~0xc0)) | biaslevel
5193 << 6;
5194 }
5195 }
5196
5197 static u_int ath9k_hw_mac_usec(struct ath_hal *ah, u_int clks)
5198 {
5199 const struct hal_channel *c =
5200 (const struct hal_channel *) ah->ah_curchan;
5201
5202 if (c != NULL)
5203 return clks / CLOCK_RATE[ath9k_hw_chan2wmode(ah, c)];
5204 else
5205 return clks / CLOCK_RATE[WIRELESS_MODE_11b];
5206 }
5207
5208 static u_int ath9k_hw_mac_to_usec(struct ath_hal *ah, u_int clks)
5209 {
5210 struct hal_channel_internal *chan = ah->ah_curchan;
5211
5212 if (chan && IS_CHAN_HT40(chan))
5213 return ath9k_hw_mac_usec(ah, clks) / 2;
5214 else
5215 return ath9k_hw_mac_usec(ah, clks);
5216 }
5217
5218 static u_int ath9k_hw_mac_clks(struct ath_hal *ah, u_int usecs)
5219 {
5220 const struct hal_channel *c =
5221 (const struct hal_channel *) ah->ah_curchan;
5222
5223 if (c != NULL)
5224 return usecs * CLOCK_RATE[ath9k_hw_chan2wmode(ah, c)];
5225 else
5226 return usecs * CLOCK_RATE[WIRELESS_MODE_11b];
5227 }
5228
5229 static u_int ath9k_hw_mac_to_clks(struct ath_hal *ah, u_int usecs)
5230 {
5231 struct hal_channel_internal *chan = ah->ah_curchan;
5232
5233 if (chan && IS_CHAN_HT40(chan))
5234 return ath9k_hw_mac_clks(ah, usecs) * 2;
5235 else
5236 return ath9k_hw_mac_clks(ah, usecs);
5237 }
5238
5239 static enum hal_bool ath9k_hw_set_ack_timeout(struct ath_hal *ah, u_int us)
5240 {
5241 struct ath_hal_5416 *ahp = AH5416(ah);
5242
5243 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
5244 HDPRINTF(ah, HAL_DBG_RESET, "%s: bad ack timeout %u\n",
5245 __func__, us);
5246 ahp->ah_acktimeout = (u_int) -1;
5247 return AH_FALSE;
5248 } else {
5249 OS_REG_RMW_FIELD(ah, AR_TIME_OUT,
5250 AR_TIME_OUT_ACK, ath9k_hw_mac_to_clks(ah, us));
5251 ahp->ah_acktimeout = us;
5252 return AH_TRUE;
5253 }
5254 }
5255
5256 static enum hal_bool ath9k_hw_set_cts_timeout(struct ath_hal *ah, u_int us)
5257 {
5258 struct ath_hal_5416 *ahp = AH5416(ah);
5259
5260 if (us > ath9k_hw_mac_to_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
5261 HDPRINTF(ah, HAL_DBG_RESET, "%s: bad cts timeout %u\n",
5262 __func__, us);
5263 ahp->ah_ctstimeout = (u_int) -1;
5264 return AH_FALSE;
5265 } else {
5266 OS_REG_RMW_FIELD(ah, AR_TIME_OUT,
5267 AR_TIME_OUT_CTS, ath9k_hw_mac_to_clks(ah, us));
5268 ahp->ah_ctstimeout = us;
5269 return AH_TRUE;
5270 }
5271 }
5272 static enum hal_bool ath9k_hw_set_global_txtimeout(struct ath_hal *ah,
5273 u_int tu)
5274 {
5275 struct ath_hal_5416 *ahp = AH5416(ah);
5276
5277 if (tu > 0xFFFF) {
5278 HDPRINTF(ah, HAL_DBG_TX, "%s: bad global tx timeout %u\n",
5279 __func__, tu);
5280 ahp->ah_globaltxtimeout = (u_int) -1;
5281 return AH_FALSE;
5282 } else {
5283 OS_REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
5284 ahp->ah_globaltxtimeout = tu;
5285 return AH_TRUE;
5286 }
5287 }
5288
5289 enum hal_bool ath9k_hw_setslottime(struct ath_hal *ah, u_int us)
5290 {
5291 struct ath_hal_5416 *ahp = AH5416(ah);
5292
5293 if (us < HAL_SLOT_TIME_9 || us > ath9k_hw_mac_to_usec(ah, 0xffff)) {
5294 HDPRINTF(ah, HAL_DBG_RESET, "%s: bad slot time %u\n",
5295 __func__, us);
5296 ahp->ah_slottime = (u_int) -1;
5297 return AH_FALSE;
5298 } else {
5299 REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath9k_hw_mac_to_clks(ah, us));
5300 ahp->ah_slottime = us;
5301 return AH_TRUE;
5302 }
5303 }
5304
5305 static inline void ath9k_hw_init_user_settings(struct ath_hal *ah)
5306 {
5307 struct ath_hal_5416 *ahp = AH5416(ah);
5308
5309 HDPRINTF(ah, HAL_DBG_RESET, "--AP %s ahp->ah_miscMode 0x%x\n",
5310 __func__, ahp->ah_miscMode);
5311 if (ahp->ah_miscMode != 0)
5312 REG_WRITE(ah, AR_PCU_MISC,
5313 REG_READ(ah, AR_PCU_MISC) | ahp->ah_miscMode);
5314 if (ahp->ah_slottime != (u_int) -1)
5315 ath9k_hw_setslottime(ah, ahp->ah_slottime);
5316 if (ahp->ah_acktimeout != (u_int) -1)
5317 ath9k_hw_set_ack_timeout(ah, ahp->ah_acktimeout);
5318 if (ahp->ah_ctstimeout != (u_int) -1)
5319 ath9k_hw_set_cts_timeout(ah, ahp->ah_ctstimeout);
5320 if (ahp->ah_globaltxtimeout != (u_int) -1)
5321 ath9k_hw_set_global_txtimeout(ah, ahp->ah_globaltxtimeout);
5322 }
5323
5324 static inline enum hal_status
5325 ath9k_hw_process_ini(struct ath_hal *ah,
5326 struct hal_channel *chan,
5327 struct hal_channel_internal *ichan,
5328 enum hal_ht_macmode macmode)
5329 {
5330 int i, regWrites = 0;
5331 struct ath_hal_5416 *ahp = AH5416(ah);
5332 u_int modesIndex, freqIndex;
5333 enum hal_status status;
5334
5335 switch (chan->channelFlags & CHANNEL_ALL) {
5336 case CHANNEL_A:
5337 case CHANNEL_A_HT20:
5338 modesIndex = 1;
5339 freqIndex = 1;
5340 break;
5341 case CHANNEL_A_HT40PLUS:
5342 case CHANNEL_A_HT40MINUS:
5343 modesIndex = 2;
5344 freqIndex = 1;
5345 break;
5346 case CHANNEL_PUREG:
5347 case CHANNEL_G_HT20:
5348 case CHANNEL_B:
5349 modesIndex = 4;
5350 freqIndex = 2;
5351 break;
5352 case CHANNEL_G_HT40PLUS:
5353 case CHANNEL_G_HT40MINUS:
5354 modesIndex = 3;
5355 freqIndex = 2;
5356 break;
5357
5358 default:
5359 return HAL_EINVAL;
5360 }
5361
5362 REG_WRITE(ah, AR_PHY(0), 0x00000007);
5363
5364 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_EXTERNAL_RADIO);
5365
5366 ath9k_hw_set_addac(ah, ichan);
5367
5368 if (AR_SREV_5416_V22_OR_LATER(ah)) {
5369 REG_WRITE_ARRAY(&ahp->ah_iniAddac, 1, regWrites);
5370 } else {
5371 struct ar5416IniArray temp;
5372 u_int32_t addacSize =
5373 sizeof(u_int32_t) * ahp->ah_iniAddac.ia_rows *
5374 ahp->ah_iniAddac.ia_columns;
5375
5376 memcpy(ahp->ah_addac5416_21,
5377 ahp->ah_iniAddac.ia_array, addacSize);
5378
5379 (ahp->ah_addac5416_21)[31 *
5380 ahp->ah_iniAddac.ia_columns + 1] = 0;
5381
5382 temp.ia_array = ahp->ah_addac5416_21;
5383 temp.ia_columns = ahp->ah_iniAddac.ia_columns;
5384 temp.ia_rows = ahp->ah_iniAddac.ia_rows;
5385 REG_WRITE_ARRAY(&temp, 1, regWrites);
5386 }
5387 REG_WRITE(ah, AR_PHY_ADC_SERIAL_CTL, AR_PHY_SEL_INTERNAL_ADDAC);
5388
5389 for (i = 0; i < ahp->ah_iniModes.ia_rows; i++) {
5390 u_int32_t reg = INI_RA(&ahp->ah_iniModes, i, 0);
5391 u_int32_t val = INI_RA(&ahp->ah_iniModes, i, modesIndex);
5392
5393 #ifdef CONFIG_SLOW_ANT_DIV
5394 if (ah->ah_devid == AR9280_DEVID_PCI)
5395 val = ath9k_hw_ini_fixup(ah, &ahp->ah_eeprom, reg,
5396 val);
5397 #endif
5398
5399 REG_WRITE(ah, reg, val);
5400
5401 if (reg >= 0x7800 && reg < 0x78a0
5402 && ah->ah_config.ath_hal_analogShiftReg) {
5403 udelay(100);
5404 }
5405
5406 DO_DELAY(regWrites);
5407 }
5408
5409 for (i = 0; i < ahp->ah_iniCommon.ia_rows; i++) {
5410 u_int32_t reg = INI_RA(&ahp->ah_iniCommon, i, 0);
5411 u_int32_t val = INI_RA(&ahp->ah_iniCommon, i, 1);
5412
5413 REG_WRITE(ah, reg, val);
5414
5415 if (reg >= 0x7800 && reg < 0x78a0
5416 && ah->ah_config.ath_hal_analogShiftReg) {
5417 udelay(100);
5418 }
5419
5420 DO_DELAY(regWrites);
5421 }
5422
5423 ath9k_hw_write_regs(ah, modesIndex, freqIndex, regWrites);
5424
5425 if (AR_SREV_9280_20(ah) && IS_CHAN_A_5MHZ_SPACED(chan)) {
5426 REG_WRITE_ARRAY(&ahp->ah_iniModesAdditional, modesIndex,
5427 regWrites);
5428 }
5429
5430 ath9k_hw_override_ini(ah, chan);
5431 ath9k_hw_set_regs(ah, chan, macmode);
5432 ath9k_hw_init_chain_masks(ah);
5433
5434 status = ath9k_hw_set_txpower(ah, &ahp->ah_eeprom, ichan,
5435 ath9k_regd_get_ctl(ah, chan),
5436 ath9k_regd_get_antenna_allowed(ah,
5437 chan),
5438 ichan->maxRegTxPower * 2,
5439 min((u_int32_t) MAX_RATE_POWER,
5440 (u_int32_t) ah->ah_powerLimit));
5441 if (status != HAL_OK) {
5442 HDPRINTF(ah, HAL_DBG_POWER_MGMT,
5443 "%s: error init'ing transmit power\n", __func__);
5444 return HAL_EIO;
5445 }
5446
5447 if (!ath9k_hw_set_rf_regs(ah, ichan, freqIndex)) {
5448 HDPRINTF(ah, HAL_DBG_REG_IO,
5449 "%s: ar5416SetRfRegs failed\n", __func__);
5450 return HAL_EIO;
5451 }
5452
5453 return HAL_OK;
5454 }
5455
5456 static inline void ath9k_hw_setup_calibration(struct ath_hal *ah,
5457 struct hal_cal_list *currCal)
5458 {
5459 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(0),
5460 AR_PHY_TIMING_CTRL4_IQCAL_LOG_COUNT_MAX,
5461 currCal->calData->calCountMax);
5462
5463 switch (currCal->calData->calType) {
5464 case IQ_MISMATCH_CAL:
5465 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ);
5466 HDPRINTF(ah, HAL_DBG_CALIBRATE,
5467 "%s: starting IQ Mismatch Calibration\n",
5468 __func__);
5469 break;
5470 case ADC_GAIN_CAL:
5471 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_GAIN);
5472 HDPRINTF(ah, HAL_DBG_CALIBRATE,
5473 "%s: starting ADC Gain Calibration\n", __func__);
5474 break;
5475 case ADC_DC_CAL:
5476 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_PER);
5477 HDPRINTF(ah, HAL_DBG_CALIBRATE,
5478 "%s: starting ADC DC Calibration\n", __func__);
5479 break;
5480 case ADC_DC_INIT_CAL:
5481 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_ADC_DC_INIT);
5482 HDPRINTF(ah, HAL_DBG_CALIBRATE,
5483 "%s: starting Init ADC DC Calibration\n",
5484 __func__);
5485 break;
5486 }
5487
5488 OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
5489 AR_PHY_TIMING_CTRL4_DO_CAL);
5490 }
5491
5492 static inline void ath9k_hw_reset_calibration(struct ath_hal *ah,
5493 struct hal_cal_list *currCal)
5494 {
5495 struct ath_hal_5416 *ahp = AH5416(ah);
5496 int i;
5497
5498 ath9k_hw_setup_calibration(ah, currCal);
5499
5500 currCal->calState = CAL_RUNNING;
5501
5502 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
5503 ahp->ah_Meas0.sign[i] = 0;
5504 ahp->ah_Meas1.sign[i] = 0;
5505 ahp->ah_Meas2.sign[i] = 0;
5506 ahp->ah_Meas3.sign[i] = 0;
5507 }
5508
5509 ahp->ah_CalSamples = 0;
5510 }
5511
5512 static inline void
5513 ath9k_hw_per_calibration(struct ath_hal *ah,
5514 struct hal_channel_internal *ichan,
5515 u_int8_t rxchainmask,
5516 struct hal_cal_list *currCal,
5517 enum hal_bool *isCalDone)
5518 {
5519 struct ath_hal_5416 *ahp = AH5416(ah);
5520
5521 *isCalDone = AH_FALSE;
5522
5523 if (currCal->calState == CAL_RUNNING) {
5524 if (!(REG_READ(ah,
5525 AR_PHY_TIMING_CTRL4(0)) &
5526 AR_PHY_TIMING_CTRL4_DO_CAL)) {
5527
5528 currCal->calData->calCollect(ah);
5529
5530 ahp->ah_CalSamples++;
5531
5532 if (ahp->ah_CalSamples >=
5533 currCal->calData->calNumSamples) {
5534 int i, numChains = 0;
5535 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
5536 if (rxchainmask & (1 << i))
5537 numChains++;
5538 }
5539
5540 currCal->calData->calPostProc(ah,
5541 numChains);
5542
5543 ichan->CalValid |=
5544 currCal->calData->calType;
5545 currCal->calState = CAL_DONE;
5546 *isCalDone = AH_TRUE;
5547 } else {
5548 ath9k_hw_setup_calibration(ah, currCal);
5549 }
5550 }
5551 } else if (!(ichan->CalValid & currCal->calData->calType)) {
5552 ath9k_hw_reset_calibration(ah, currCal);
5553 }
5554 }
5555
5556 static inline enum hal_bool ath9k_hw_run_init_cals(struct ath_hal *ah,
5557 int init_cal_count)
5558 {
5559 struct ath_hal_5416 *ahp = AH5416(ah);
5560 struct hal_channel_internal ichan;
5561 enum hal_bool isCalDone;
5562 struct hal_cal_list *currCal = ahp->ah_cal_list_curr;
5563 const struct hal_percal_data *calData = currCal->calData;
5564 int i;
5565
5566 if (currCal == NULL)
5567 return AH_FALSE;
5568
5569 ichan.CalValid = 0;
5570
5571 for (i = 0; i < init_cal_count; i++) {
5572 ath9k_hw_reset_calibration(ah, currCal);
5573
5574 if (!ath9k_hw_wait(ah, AR_PHY_TIMING_CTRL4(0),
5575 AR_PHY_TIMING_CTRL4_DO_CAL, 0)) {
5576 HDPRINTF(ah, HAL_DBG_CALIBRATE,
5577 "%s: Cal %d failed to complete in 100ms.\n",
5578 __func__, calData->calType);
5579
5580 ahp->ah_cal_list = ahp->ah_cal_list_last =
5581 ahp->ah_cal_list_curr = NULL;
5582 return AH_FALSE;
5583 }
5584
5585 ath9k_hw_per_calibration(ah, &ichan, ahp->ah_rxchainmask,
5586 currCal, &isCalDone);
5587 if (isCalDone == AH_FALSE) {
5588 HDPRINTF(ah, HAL_DBG_CALIBRATE,
5589 "%s: Not able to run Init Cal %d.\n",
5590 __func__, calData->calType);
5591 }
5592 if (currCal->calNext) {
5593 currCal = currCal->calNext;
5594 calData = currCal->calData;
5595 }
5596 }
5597
5598 ahp->ah_cal_list = ahp->ah_cal_list_last = ahp->ah_cal_list_curr = NULL;
5599 return AH_TRUE;
5600 }
5601
5602 static inline enum hal_bool
5603 ath9k_hw_channel_change(struct ath_hal *ah,
5604 struct hal_channel *chan,
5605 struct hal_channel_internal *ichan,
5606 enum hal_ht_macmode macmode)
5607 {
5608 u_int32_t synthDelay, qnum;
5609 struct ath_hal_5416 *ahp = AH5416(ah);
5610
5611 for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
5612 if (ath9k_hw_numtxpending(ah, qnum)) {
5613 HDPRINTF(ah, HAL_DBG_QUEUE,
5614 "%s: Transmit frames pending on queue %d\n",
5615 __func__, qnum);
5616 return AH_FALSE;
5617 }
5618 }
5619
5620 REG_WRITE(ah, AR_PHY_RFBUS_REQ, AR_PHY_RFBUS_REQ_EN);
5621 if (!ath9k_hw_wait(ah, AR_PHY_RFBUS_GRANT, AR_PHY_RFBUS_GRANT_EN,
5622 AR_PHY_RFBUS_GRANT_EN)) {
5623 HDPRINTF(ah, HAL_DBG_PHY_IO,
5624 "%s: Could not kill baseband RX\n", __func__);
5625 return AH_FALSE;
5626 }
5627
5628 ath9k_hw_set_regs(ah, chan, macmode);
5629
5630 if (AR_SREV_9280_10_OR_LATER(ah)) {
5631 if (!(ath9k_hw_ar9280_set_channel(ah, ichan))) {
5632 HDPRINTF(ah, HAL_DBG_CHANNEL,
5633 "%s: failed to set channel\n", __func__);
5634 return AH_FALSE;
5635 }
5636 } else {
5637 if (!(ath9k_hw_set_channel(ah, ichan))) {
5638 HDPRINTF(ah, HAL_DBG_CHANNEL,
5639 "%s: failed to set channel\n", __func__);
5640 return AH_FALSE;
5641 }
5642 }
5643
5644 if (ath9k_hw_set_txpower(ah, &ahp->ah_eeprom, ichan,
5645 ath9k_regd_get_ctl(ah, chan),
5646 ath9k_regd_get_antenna_allowed(ah, chan),
5647 ichan->maxRegTxPower * 2,
5648 min((u_int32_t) MAX_RATE_POWER,
5649 (u_int32_t) ah->ah_powerLimit))
5650 != HAL_OK) {
5651 HDPRINTF(ah, HAL_DBG_EEPROM,
5652 "%s: error init'ing transmit power\n", __func__);
5653 return AH_FALSE;
5654 }
5655
5656 synthDelay = REG_READ(ah, AR_PHY_RX_DELAY) & AR_PHY_RX_DELAY_DELAY;
5657 if (IS_CHAN_CCK(chan))
5658 synthDelay = (4 * synthDelay) / 22;
5659 else
5660 synthDelay /= 10;
5661
5662 udelay(synthDelay + BASE_ACTIVATE_DELAY);
5663
5664 REG_WRITE(ah, AR_PHY_RFBUS_REQ, 0);
5665
5666 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
5667 ath9k_hw_set_delta_slope(ah, ichan);
5668
5669 if (AR_SREV_9280_10_OR_LATER(ah))
5670 ath9k_hw_9280_spur_mitigate(ah, chan, ichan);
5671 else
5672 ath9k_hw_spur_mitigate(ah, chan);
5673
5674 if (!ichan->oneTimeCalsDone)
5675 ichan->oneTimeCalsDone = AH_TRUE;
5676
5677 return AH_TRUE;
5678 }
5679
5680 static enum hal_bool ath9k_hw_chip_reset(struct ath_hal *ah,
5681 struct hal_channel *chan)
5682 {
5683 struct ath_hal_5416 *ahp = AH5416(ah);
5684
5685 if (!ath9k_hw_set_reset_reg(ah, HAL_RESET_WARM))
5686 return AH_FALSE;
5687
5688 if (!ath9k_hw_setpower(ah, HAL_PM_AWAKE))
5689 return AH_FALSE;
5690
5691 ahp->ah_chipFullSleep = AH_FALSE;
5692
5693 ath9k_hw_init_pll(ah, chan);
5694
5695 ath9k_hw_set_rfmode(ah, chan);
5696
5697 return AH_TRUE;
5698 }
5699
5700 static inline void ath9k_hw_set_dma(struct ath_hal *ah)
5701 {
5702 u_int32_t regval;
5703
5704 regval = REG_READ(ah, AR_AHB_MODE);
5705 REG_WRITE(ah, AR_AHB_MODE, regval | AR_AHB_PREFETCH_RD_EN);
5706
5707 regval = REG_READ(ah, AR_TXCFG) & ~AR_TXCFG_DMASZ_MASK;
5708 REG_WRITE(ah, AR_TXCFG, regval | AR_TXCFG_DMASZ_128B);
5709
5710 OS_REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->ah_txTrigLevel);
5711
5712 regval = REG_READ(ah, AR_RXCFG) & ~AR_RXCFG_DMASZ_MASK;
5713 REG_WRITE(ah, AR_RXCFG, regval | AR_RXCFG_DMASZ_128B);
5714
5715 REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
5716
5717 if (AR_SREV_9285(ah)) {
5718 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
5719 AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
5720 } else {
5721 REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
5722 AR_PCU_TXBUF_CTRL_USABLE_SIZE);
5723 }
5724 }
5725
5726 enum hal_bool ath9k_hw_stopdmarecv(struct ath_hal *ah)
5727 {
5728 REG_WRITE(ah, AR_CR, AR_CR_RXD);
5729 if (!ath9k_hw_wait(ah, AR_CR, AR_CR_RXE, 0)) {
5730 HDPRINTF(ah, HAL_DBG_RX, "%s: dma failed to stop in 10ms\n"
5731 "AR_CR=0x%08x\nAR_DIAG_SW=0x%08x\n",
5732 __func__,
5733 REG_READ(ah, AR_CR), REG_READ(ah, AR_DIAG_SW));
5734 return AH_FALSE;
5735 } else {
5736 return AH_TRUE;
5737 }
5738 }
5739
5740 void ath9k_hw_startpcureceive(struct ath_hal *ah)
5741 {
5742 OS_REG_CLR_BIT(ah, AR_DIAG_SW,
5743 (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
5744
5745 ath9k_enable_mib_counters(ah);
5746
5747 ath9k_ani_reset(ah);
5748 }
5749
5750 void ath9k_hw_stoppcurecv(struct ath_hal *ah)
5751 {
5752 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_RX_DIS);
5753
5754 ath9k_hw_disable_mib_counters(ah);
5755 }
5756
5757 static enum hal_bool ath9k_hw_iscal_supported(struct ath_hal *ah,
5758 struct hal_channel *chan,
5759 enum hal_cal_types calType)
5760 {
5761 struct ath_hal_5416 *ahp = AH5416(ah);
5762 enum hal_bool retval = AH_FALSE;
5763
5764 switch (calType & ahp->ah_suppCals) {
5765 case IQ_MISMATCH_CAL:
5766 if (!IS_CHAN_B(chan))
5767 retval = AH_TRUE;
5768 break;
5769 case ADC_GAIN_CAL:
5770 case ADC_DC_CAL:
5771 if (!IS_CHAN_B(chan)
5772 && !(IS_CHAN_2GHZ(chan) && IS_CHAN_HT20(chan)))
5773 retval = AH_TRUE;
5774 break;
5775 }
5776
5777 return retval;
5778 }
5779
5780 static inline enum hal_bool ath9k_hw_init_cal(struct ath_hal *ah,
5781 struct hal_channel *chan)
5782 {
5783 struct ath_hal_5416 *ahp = AH5416(ah);
5784 struct hal_channel_internal *ichan =
5785 ath9k_regd_check_channel(ah, chan);
5786
5787 REG_WRITE(ah, AR_PHY_AGC_CONTROL,
5788 REG_READ(ah, AR_PHY_AGC_CONTROL) |
5789 AR_PHY_AGC_CONTROL_CAL);
5790
5791 if (!ath9k_hw_wait
5792 (ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0)) {
5793 HDPRINTF(ah, HAL_DBG_CALIBRATE,
5794 "%s: offset calibration failed to complete in 1ms; "
5795 "noisy environment?\n", __func__);
5796 return AH_FALSE;
5797 }
5798
5799 REG_WRITE(ah, AR_PHY_AGC_CONTROL,
5800 REG_READ(ah, AR_PHY_AGC_CONTROL) |
5801 AR_PHY_AGC_CONTROL_NF);
5802
5803 ahp->ah_cal_list = ahp->ah_cal_list_last = ahp->ah_cal_list_curr =
5804 NULL;
5805
5806 if (AR_SREV_9100(ah) || AR_SREV_9160_10_OR_LATER(ah)) {
5807 if (AH_TRUE ==
5808 ath9k_hw_iscal_supported(ah, chan, ADC_GAIN_CAL)) {
5809 INIT_CAL(&ahp->ah_adcGainCalData);
5810 INSERT_CAL(ahp, &ahp->ah_adcGainCalData);
5811 HDPRINTF(ah, HAL_DBG_CALIBRATE,
5812 "%s: enabling ADC Gain Calibration.\n",
5813 __func__);
5814 }
5815 if (AH_TRUE ==
5816 ath9k_hw_iscal_supported(ah, chan, ADC_DC_CAL)) {
5817 INIT_CAL(&ahp->ah_adcDcCalData);
5818 INSERT_CAL(ahp, &ahp->ah_adcDcCalData);
5819 HDPRINTF(ah, HAL_DBG_CALIBRATE,
5820 "%s: enabling ADC DC Calibration.\n",
5821 __func__);
5822 }
5823 if (AH_TRUE ==
5824 ath9k_hw_iscal_supported(ah, chan, IQ_MISMATCH_CAL)) {
5825 INIT_CAL(&ahp->ah_iqCalData);
5826 INSERT_CAL(ahp, &ahp->ah_iqCalData);
5827 HDPRINTF(ah, HAL_DBG_CALIBRATE,
5828 "%s: enabling IQ Calibration.\n",
5829 __func__);
5830 }
5831
5832 ahp->ah_cal_list_curr = ahp->ah_cal_list;
5833
5834 if (ahp->ah_cal_list_curr)
5835 ath9k_hw_reset_calibration(ah,
5836 ahp->ah_cal_list_curr);
5837 }
5838
5839 ichan->CalValid = 0;
5840
5841 return AH_TRUE;
5842 }
5843
5844
5845 enum hal_bool ath9k_hw_reset(struct ath_hal *ah, enum hal_opmode opmode,
5846 struct hal_channel *chan,
5847 enum hal_ht_macmode macmode,
5848 u_int8_t txchainmask, u_int8_t rxchainmask,
5849 enum hal_ht_extprotspacing extprotspacing,
5850 enum hal_bool bChannelChange,
5851 enum hal_status *status)
5852 {
5853 #define FAIL(_code) do { ecode = _code; goto bad; } while (0)
5854 u_int32_t saveLedState;
5855 struct ath_hal_5416 *ahp = AH5416(ah);
5856 struct hal_channel_internal *ichan;
5857 struct hal_channel_internal *curchan = ah->ah_curchan;
5858 u_int32_t saveDefAntenna;
5859 u_int32_t macStaId1;
5860 enum hal_status ecode;
5861 int i, rx_chainmask;
5862
5863 ahp->ah_extprotspacing = extprotspacing;
5864 ahp->ah_txchainmask = txchainmask;
5865 ahp->ah_rxchainmask = rxchainmask;
5866
5867 if (AR_SREV_9280(ah)) {
5868 ahp->ah_txchainmask &= 0x3;
5869 ahp->ah_rxchainmask &= 0x3;
5870 }
5871
5872 ichan = ath9k_hw_check_chan(ah, chan);
5873 if (ichan == NULL) {
5874 HDPRINTF(ah, HAL_DBG_CHANNEL,
5875 "%s: invalid channel %u/0x%x; no mapping\n",
5876 __func__, chan->channel, chan->channelFlags);
5877 FAIL(HAL_EINVAL);
5878 }
5879
5880 if (!ath9k_hw_setpower(ah, HAL_PM_AWAKE))
5881 return AH_FALSE;
5882
5883 if (curchan)
5884 ath9k_hw_getnf(ah, curchan);
5885
5886 if (bChannelChange &&
5887 (ahp->ah_chipFullSleep != AH_TRUE) &&
5888 (ah->ah_curchan != NULL) &&
5889 (chan->channel != ah->ah_curchan->channel) &&
5890 ((chan->channelFlags & CHANNEL_ALL) ==
5891 (ah->ah_curchan->channelFlags & CHANNEL_ALL)) &&
5892 (!AR_SREV_9280(ah) || (!IS_CHAN_A_5MHZ_SPACED(chan) &&
5893 !IS_CHAN_A_5MHZ_SPACED(ah->
5894 ah_curchan)))) {
5895
5896 if (ath9k_hw_channel_change(ah, chan, ichan, macmode)) {
5897 chan->channelFlags = ichan->channelFlags;
5898 chan->privFlags = ichan->privFlags;
5899
5900 ath9k_hw_loadnf(ah, ah->ah_curchan);
5901
5902 ath9k_hw_start_nfcal(ah);
5903
5904 return AH_TRUE;
5905 }
5906 }
5907
5908 saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
5909 if (saveDefAntenna == 0)
5910 saveDefAntenna = 1;
5911
5912 macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
5913
5914 saveLedState = REG_READ(ah, AR_CFG_LED) &
5915 (AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
5916 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
5917
5918 ath9k_hw_mark_phy_inactive(ah);
5919
5920 if (!ath9k_hw_chip_reset(ah, chan)) {
5921 HDPRINTF(ah, HAL_DBG_RESET, "%s: chip reset failed\n",
5922 __func__);
5923 FAIL(HAL_EIO);
5924 }
5925
5926 if (AR_SREV_9280(ah)) {
5927 OS_REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
5928 AR_GPIO_JTAG_DISABLE);
5929
5930 if (ah->ah_caps.halWirelessModes & ATH9K_MODE_SEL_11A) {
5931 if (IS_CHAN_5GHZ(chan))
5932 ath9k_hw_set_gpio(ah, 9, 0);
5933 else
5934 ath9k_hw_set_gpio(ah, 9, 1);
5935 }
5936 ath9k_hw_cfg_output(ah, 9, HAL_GPIO_OUTPUT_MUX_AS_OUTPUT);
5937 }
5938
5939 ecode = ath9k_hw_process_ini(ah, chan, ichan, macmode);
5940 if (ecode != HAL_OK)
5941 goto bad;
5942
5943 if (IS_CHAN_OFDM(chan) || IS_CHAN_HT(chan))
5944 ath9k_hw_set_delta_slope(ah, ichan);
5945
5946 if (AR_SREV_9280_10_OR_LATER(ah))
5947 ath9k_hw_9280_spur_mitigate(ah, chan, ichan);
5948 else
5949 ath9k_hw_spur_mitigate(ah, chan);
5950
5951 if (!ath9k_hw_eeprom_set_board_values(ah, ichan)) {
5952 HDPRINTF(ah, HAL_DBG_EEPROM,
5953 "%s: error setting board options\n", __func__);
5954 FAIL(HAL_EIO);
5955 }
5956
5957 ath9k_hw_decrease_chain_power(ah, chan);
5958
5959 REG_WRITE(ah, AR_STA_ID0, LE_READ_4(ahp->ah_macaddr));
5960 REG_WRITE(ah, AR_STA_ID1, LE_READ_2(ahp->ah_macaddr + 4)
5961 | macStaId1
5962 | AR_STA_ID1_RTS_USE_DEF
5963 | (ah->ah_config.
5964 ath_hal_6mb_ack ? AR_STA_ID1_ACKCTS_6MB : 0)
5965 | ahp->ah_staId1Defaults);
5966 ath9k_hw_set_operating_mode(ah, opmode);
5967
5968 REG_WRITE(ah, AR_BSSMSKL, LE_READ_4(ahp->ah_bssidmask));
5969 REG_WRITE(ah, AR_BSSMSKU, LE_READ_2(ahp->ah_bssidmask + 4));
5970
5971 REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
5972
5973 REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid));
5974 REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid + 4) |
5975 ((ahp->ah_assocId & 0x3fff) << AR_BSS_ID1_AID_S));
5976
5977 REG_WRITE(ah, AR_ISR, ~0);
5978
5979 REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
5980
5981 if (AR_SREV_9280_10_OR_LATER(ah)) {
5982 if (!(ath9k_hw_ar9280_set_channel(ah, ichan)))
5983 FAIL(HAL_EIO);
5984 } else {
5985 if (!(ath9k_hw_set_channel(ah, ichan)))
5986 FAIL(HAL_EIO);
5987 }
5988
5989 for (i = 0; i < AR_NUM_DCU; i++)
5990 REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
5991
5992 ahp->ah_intrTxqs = 0;
5993 for (i = 0; i < ah->ah_caps.halTotalQueues; i++)
5994 ath9k_hw_resettxqueue(ah, i);
5995
5996 ath9k_hw_init_interrupt_masks(ah, opmode);
5997 ath9k_hw_init_qos(ah);
5998
5999 ath9k_hw_init_user_settings(ah);
6000
6001 ah->ah_opmode = opmode;
6002
6003 REG_WRITE(ah, AR_STA_ID1,
6004 REG_READ(ah, AR_STA_ID1) | AR_STA_ID1_PRESERVE_SEQNUM);
6005
6006 ath9k_hw_set_dma(ah);
6007
6008 REG_WRITE(ah, AR_OBS, 8);
6009
6010 if (ahp->ah_intrMitigation) {
6011
6012 OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, 500);
6013 OS_REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, 2000);
6014 }
6015
6016 ath9k_hw_init_bb(ah, chan);
6017
6018 if (!ath9k_hw_init_cal(ah, chan))
6019 FAIL(HAL_ESELFTEST);
6020
6021 rx_chainmask = ahp->ah_rxchainmask;
6022 if ((rx_chainmask == 0x5) || (rx_chainmask == 0x3)) {
6023 REG_WRITE(ah, AR_PHY_RX_CHAINMASK, rx_chainmask);
6024 REG_WRITE(ah, AR_PHY_CAL_CHAINMASK, rx_chainmask);
6025 }
6026
6027 REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
6028
6029 if (AR_SREV_9100(ah)) {
6030 u_int32_t mask;
6031 mask = REG_READ(ah, AR_CFG);
6032 if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
6033 HDPRINTF(ah, HAL_DBG_RESET,
6034 "%s CFG Byte Swap Set 0x%x\n", __func__,
6035 mask);
6036 } else {
6037 mask =
6038 INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
6039 REG_WRITE(ah, AR_CFG, mask);
6040 HDPRINTF(ah, HAL_DBG_RESET,
6041 "%s Setting CFG 0x%x\n", __func__,
6042 REG_READ(ah, AR_CFG));
6043 }
6044 } else {
6045 #ifdef __BIG_ENDIAN
6046 REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
6047 #endif
6048 }
6049 chan->channelFlags = ichan->channelFlags;
6050 chan->privFlags = ichan->privFlags;
6051 return AH_TRUE;
6052 bad:
6053 if (status)
6054 *status = ecode;
6055 return AH_FALSE;
6056 #undef FAIL
6057 }
6058
6059 enum hal_bool ath9k_hw_phy_disable(struct ath_hal *ah)
6060 {
6061 return ath9k_hw_set_reset_reg(ah, HAL_RESET_WARM);
6062 }
6063
6064 enum hal_bool ath9k_hw_disable(struct ath_hal *ah)
6065 {
6066 if (!ath9k_hw_setpower(ah, HAL_PM_AWAKE))
6067 return AH_FALSE;
6068
6069 return ath9k_hw_set_reset_reg(ah, HAL_RESET_COLD);
6070 }
6071
6072 enum hal_bool
6073 ath9k_hw_calibrate(struct ath_hal *ah, struct hal_channel *chan,
6074 u_int8_t rxchainmask, enum hal_bool longcal,
6075 enum hal_bool *isCalDone)
6076 {
6077 struct ath_hal_5416 *ahp = AH5416(ah);
6078 struct hal_cal_list *currCal = ahp->ah_cal_list_curr;
6079 struct hal_channel_internal *ichan =
6080 ath9k_regd_check_channel(ah, chan);
6081
6082 *isCalDone = AH_TRUE;
6083
6084 if (ichan == NULL) {
6085 HDPRINTF(ah, HAL_DBG_CHANNEL,
6086 "%s: invalid channel %u/0x%x; no mapping\n",
6087 __func__, chan->channel, chan->channelFlags);
6088 return AH_FALSE;
6089 }
6090
6091 if (currCal &&
6092 (currCal->calState == CAL_RUNNING ||
6093 currCal->calState == CAL_WAITING)) {
6094 ath9k_hw_per_calibration(ah, ichan, rxchainmask, currCal,
6095 isCalDone);
6096 if (*isCalDone == AH_TRUE) {
6097 ahp->ah_cal_list_curr = currCal = currCal->calNext;
6098
6099 if (currCal->calState == CAL_WAITING) {
6100 *isCalDone = AH_FALSE;
6101 ath9k_hw_reset_calibration(ah, currCal);
6102 }
6103 }
6104 }
6105
6106 if (longcal) {
6107 ath9k_hw_getnf(ah, ichan);
6108 ath9k_hw_loadnf(ah, ah->ah_curchan);
6109 ath9k_hw_start_nfcal(ah);
6110
6111 if ((ichan->channelFlags & CHANNEL_CW_INT) != 0) {
6112
6113 chan->channelFlags |= CHANNEL_CW_INT;
6114 ichan->channelFlags &= ~CHANNEL_CW_INT;
6115 }
6116 }
6117
6118 return AH_TRUE;
6119 }
6120
6121 static void ath9k_hw_iqcal_collect(struct ath_hal *ah)
6122 {
6123 struct ath_hal_5416 *ahp = AH5416(ah);
6124 int i;
6125
6126 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
6127 ahp->ah_totalPowerMeasI[i] +=
6128 REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
6129 ahp->ah_totalPowerMeasQ[i] +=
6130 REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
6131 ahp->ah_totalIqCorrMeas[i] +=
6132 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
6133 HDPRINTF(ah, HAL_DBG_CALIBRATE,
6134 "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n",
6135 ahp->ah_CalSamples, i, ahp->ah_totalPowerMeasI[i],
6136 ahp->ah_totalPowerMeasQ[i],
6137 ahp->ah_totalIqCorrMeas[i]);
6138 }
6139 }
6140
6141 static void ath9k_hw_adc_gaincal_collect(struct ath_hal *ah)
6142 {
6143 struct ath_hal_5416 *ahp = AH5416(ah);
6144 int i;
6145
6146 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
6147 ahp->ah_totalAdcIOddPhase[i] +=
6148 REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
6149 ahp->ah_totalAdcIEvenPhase[i] +=
6150 REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
6151 ahp->ah_totalAdcQOddPhase[i] +=
6152 REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
6153 ahp->ah_totalAdcQEvenPhase[i] +=
6154 REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
6155
6156 HDPRINTF(ah, HAL_DBG_CALIBRATE,
6157 "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
6158 "oddq=0x%08x; evenq=0x%08x;\n",
6159 ahp->ah_CalSamples, i,
6160 ahp->ah_totalAdcIOddPhase[i],
6161 ahp->ah_totalAdcIEvenPhase[i],
6162 ahp->ah_totalAdcQOddPhase[i],
6163 ahp->ah_totalAdcQEvenPhase[i]);
6164 }
6165 }
6166
6167 static void ath9k_hw_adc_dccal_collect(struct ath_hal *ah)
6168 {
6169 struct ath_hal_5416 *ahp = AH5416(ah);
6170 int i;
6171
6172 for (i = 0; i < AR5416_MAX_CHAINS; i++) {
6173 ahp->ah_totalAdcDcOffsetIOddPhase[i] +=
6174 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_0(i));
6175 ahp->ah_totalAdcDcOffsetIEvenPhase[i] +=
6176 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_1(i));
6177 ahp->ah_totalAdcDcOffsetQOddPhase[i] +=
6178 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i));
6179 ahp->ah_totalAdcDcOffsetQEvenPhase[i] +=
6180 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_3(i));
6181
6182 HDPRINTF(ah, HAL_DBG_CALIBRATE,
6183 "%d: Chn %d oddi=0x%08x; eveni=0x%08x; "
6184 "oddq=0x%08x; evenq=0x%08x;\n",
6185 ahp->ah_CalSamples, i,
6186 ahp->ah_totalAdcDcOffsetIOddPhase[i],
6187 ahp->ah_totalAdcDcOffsetIEvenPhase[i],
6188 ahp->ah_totalAdcDcOffsetQOddPhase[i],
6189 ahp->ah_totalAdcDcOffsetQEvenPhase[i]);
6190 }
6191 }
6192
6193 static void ath9k_hw_iqcalibrate(struct ath_hal *ah, u_int8_t numChains)
6194 {
6195 struct ath_hal_5416 *ahp = AH5416(ah);
6196 u_int32_t powerMeasQ, powerMeasI, iqCorrMeas;
6197 u_int32_t qCoffDenom, iCoffDenom;
6198 int32_t qCoff, iCoff;
6199 int iqCorrNeg, i;
6200
6201 for (i = 0; i < numChains; i++) {
6202 powerMeasI = ahp->ah_totalPowerMeasI[i];
6203 powerMeasQ = ahp->ah_totalPowerMeasQ[i];
6204 iqCorrMeas = ahp->ah_totalIqCorrMeas[i];
6205
6206 HDPRINTF(ah, HAL_DBG_CALIBRATE,
6207 "Starting IQ Cal and Correction for Chain %d\n",
6208 i);
6209
6210 HDPRINTF(ah, HAL_DBG_CALIBRATE,
6211 "Orignal: Chn %diq_corr_meas = 0x%08x\n",
6212 i, ahp->ah_totalIqCorrMeas[i]);
6213
6214 iqCorrNeg = 0;
6215
6216
6217 if (iqCorrMeas > 0x80000000) {
6218 iqCorrMeas = (0xffffffff - iqCorrMeas) + 1;
6219 iqCorrNeg = 1;
6220 }
6221
6222 HDPRINTF(ah, HAL_DBG_CALIBRATE,
6223 "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI);
6224 HDPRINTF(ah, HAL_DBG_CALIBRATE,
6225 "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ);
6226 HDPRINTF(ah, HAL_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n",
6227 iqCorrNeg);
6228
6229 iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 128;
6230 qCoffDenom = powerMeasQ / 64;
6231
6232 if (powerMeasQ != 0) {
6233
6234 iCoff = iqCorrMeas / iCoffDenom;
6235 qCoff = powerMeasI / qCoffDenom - 64;
6236 HDPRINTF(ah, HAL_DBG_CALIBRATE,
6237 "Chn %d iCoff = 0x%08x\n", i, iCoff);
6238 HDPRINTF(ah, HAL_DBG_CALIBRATE,
6239 "Chn %d qCoff = 0x%08x\n", i, qCoff);
6240
6241
6242 iCoff = iCoff & 0x3f;
6243 HDPRINTF(ah, HAL_DBG_CALIBRATE,
6244 "New: Chn %d iCoff = 0x%08x\n", i, iCoff);
6245 if (iqCorrNeg == 0x0)
6246 iCoff = 0x40 - iCoff;
6247
6248 if (qCoff > 15)
6249 qCoff = 15;
6250 else if (qCoff <= -16)
6251 qCoff = 16;
6252
6253 HDPRINTF(ah, HAL_DBG_CALIBRATE,
6254 "Chn %d : iCoff = 0x%x qCoff = 0x%x\n",
6255 i, iCoff, qCoff);
6256
6257 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
6258 AR_PHY_TIMING_CTRL4_IQCORR_Q_I_COFF,
6259 iCoff);
6260 OS_REG_RMW_FIELD(ah, AR_PHY_TIMING_CTRL4(i),
6261 AR_PHY_TIMING_CTRL4_IQCORR_Q_Q_COFF,
6262 qCoff);
6263 HDPRINTF(ah, HAL_DBG_CALIBRATE,
6264 "IQ Cal and Correction done for Chain %d\n",
6265 i);
6266 }
6267 }
6268
6269 OS_REG_SET_BIT(ah, AR_PHY_TIMING_CTRL4(0),
6270 AR_PHY_TIMING_CTRL4_IQCORR_ENABLE);
6271 }
6272
6273 static void
6274 ath9k_hw_adc_gaincal_calibrate(struct ath_hal *ah, u_int8_t numChains)
6275 {
6276 struct ath_hal_5416 *ahp = AH5416(ah);
6277 u_int32_t iOddMeasOffset, iEvenMeasOffset, qOddMeasOffset,
6278 qEvenMeasOffset;
6279 u_int32_t qGainMismatch, iGainMismatch, val, i;
6280
6281 for (i = 0; i < numChains; i++) {
6282 iOddMeasOffset = ahp->ah_totalAdcIOddPhase[i];
6283 iEvenMeasOffset = ahp->ah_totalAdcIEvenPhase[i];
6284 qOddMeasOffset = ahp->ah_totalAdcQOddPhase[i];
6285 qEvenMeasOffset = ahp->ah_totalAdcQEvenPhase[i];
6286
6287 HDPRINTF(ah, HAL_DBG_CALIBRATE,
6288 "Starting ADC Gain Cal for Chain %d\n", i);
6289
6290 HDPRINTF(ah, HAL_DBG_CALIBRATE,
6291 "Chn %d pwr_meas_odd_i = 0x%08x\n", i,
6292 iOddMeasOffset);
6293 HDPRINTF(ah, HAL_DBG_CALIBRATE,
6294 "Chn %d pwr_meas_even_i = 0x%08x\n", i,
6295 iEvenMeasOffset);
6296 HDPRINTF(ah, HAL_DBG_CALIBRATE,
6297 "Chn %d pwr_meas_odd_q = 0x%08x\n", i,
6298 qOddMeasOffset);
6299 HDPRINTF(ah, HAL_DBG_CALIBRATE,
6300 "Chn %d pwr_meas_even_q = 0x%08x\n", i,
6301 qEvenMeasOffset);
6302
6303 if (iOddMeasOffset != 0 && qEvenMeasOffset != 0) {
6304 iGainMismatch =
6305 ((iEvenMeasOffset * 32) /
6306 iOddMeasOffset) & 0x3f;
6307 qGainMismatch =
6308 ((qOddMeasOffset * 32) /
6309 qEvenMeasOffset) & 0x3f;
6310
6311 HDPRINTF(ah, HAL_DBG_CALIBRATE,
6312 "Chn %d gain_mismatch_i = 0x%08x\n", i,
6313 iGainMismatch);
6314 HDPRINTF(ah, HAL_DBG_CALIBRATE,
6315 "Chn %d gain_mismatch_q = 0x%08x\n", i,
6316 qGainMismatch);
6317
6318 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
6319 val &= 0xfffff000;
6320 val |= (qGainMismatch) | (iGainMismatch << 6);
6321 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
6322
6323 HDPRINTF(ah, HAL_DBG_CALIBRATE,
6324 "ADC Gain Cal done for Chain %d\n", i);
6325 }
6326 }
6327
6328 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
6329 REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
6330 AR_PHY_NEW_ADC_GAIN_CORR_ENABLE);
6331 }
6332
6333 static void
6334 ath9k_hw_adc_dccal_calibrate(struct ath_hal *ah, u_int8_t numChains)
6335 {
6336 struct ath_hal_5416 *ahp = AH5416(ah);
6337 u_int32_t iOddMeasOffset, iEvenMeasOffset, val, i;
6338 int32_t qOddMeasOffset, qEvenMeasOffset, qDcMismatch, iDcMismatch;
6339 const struct hal_percal_data *calData =
6340 ahp->ah_cal_list_curr->calData;
6341 u_int32_t numSamples =
6342 (1 << (calData->calCountMax + 5)) * calData->calNumSamples;
6343
6344 for (i = 0; i < numChains; i++) {
6345 iOddMeasOffset = ahp->ah_totalAdcDcOffsetIOddPhase[i];
6346 iEvenMeasOffset = ahp->ah_totalAdcDcOffsetIEvenPhase[i];
6347 qOddMeasOffset = ahp->ah_totalAdcDcOffsetQOddPhase[i];
6348 qEvenMeasOffset = ahp->ah_totalAdcDcOffsetQEvenPhase[i];
6349
6350 HDPRINTF(ah, HAL_DBG_CALIBRATE,
6351 "Starting ADC DC Offset Cal for Chain %d\n", i);
6352
6353 HDPRINTF(ah, HAL_DBG_CALIBRATE,
6354 "Chn %d pwr_meas_odd_i = %d\n", i,
6355 iOddMeasOffset);
6356 HDPRINTF(ah, HAL_DBG_CALIBRATE,
6357 "Chn %d pwr_meas_even_i = %d\n", i,
6358 iEvenMeasOffset);
6359 HDPRINTF(ah, HAL_DBG_CALIBRATE,
6360 "Chn %d pwr_meas_odd_q = %d\n", i,
6361 qOddMeasOffset);
6362 HDPRINTF(ah, HAL_DBG_CALIBRATE,
6363 "Chn %d pwr_meas_even_q = %d\n", i,
6364 qEvenMeasOffset);
6365
6366 iDcMismatch = (((iEvenMeasOffset - iOddMeasOffset) * 2) /
6367 numSamples) & 0x1ff;
6368 qDcMismatch = (((qOddMeasOffset - qEvenMeasOffset) * 2) /
6369 numSamples) & 0x1ff;
6370
6371 HDPRINTF(ah, HAL_DBG_CALIBRATE,
6372 "Chn %d dc_offset_mismatch_i = 0x%08x\n", i,
6373 iDcMismatch);
6374 HDPRINTF(ah, HAL_DBG_CALIBRATE,
6375 "Chn %d dc_offset_mismatch_q = 0x%08x\n", i,
6376 qDcMismatch);
6377
6378 val = REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i));
6379 val &= 0xc0000fff;
6380 val |= (qDcMismatch << 12) | (iDcMismatch << 21);
6381 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(i), val);
6382
6383 HDPRINTF(ah, HAL_DBG_CALIBRATE,
6384 "ADC DC Offset Cal done for Chain %d\n", i);
6385 }
6386
6387 REG_WRITE(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0),
6388 REG_READ(ah, AR_PHY_NEW_ADC_DC_GAIN_CORR(0)) |
6389 AR_PHY_NEW_ADC_DC_OFFSET_CORR_ENABLE);
6390 }
6391
6392 enum hal_bool
6393 ath9k_hw_SetTxPowerLimit(struct ath_hal *ah, u_int32_t limit,
6394 u_int16_t tpcInDb)
6395 {
6396 struct ath_hal_5416 *ahp = AH5416(ah);
6397 struct hal_channel_internal *ichan = ah->ah_curchan;
6398 struct hal_channel *chan = (struct hal_channel *) ichan;
6399
6400 ah->ah_powerLimit = min(limit, (u_int32_t) MAX_RATE_POWER);
6401
6402 if (ath9k_hw_set_txpower(ah, &ahp->ah_eeprom, ichan,
6403 ath9k_regd_get_ctl(ah, chan),
6404 ath9k_regd_get_antenna_allowed(ah,
6405 chan),
6406 chan->maxRegTxPower * 2,
6407 min((u_int32_t) MAX_RATE_POWER,
6408 (u_int32_t) ah->ah_powerLimit))
6409 != HAL_OK)
6410 return AH_FALSE;
6411
6412 return AH_TRUE;
6413 }
6414
6415 void
6416 ath9k_hw_get_channel_centers(struct ath_hal *ah,
6417 struct hal_channel_internal *chan,
6418 struct chan_centers *centers)
6419 {
6420 int8_t extoff;
6421 struct ath_hal_5416 *ahp = AH5416(ah);
6422
6423 if (!IS_CHAN_HT40(chan)) {
6424 centers->ctl_center = centers->ext_center =
6425 centers->synth_center = chan->channel;
6426 return;
6427 }
6428
6429 if (chan->channelFlags & CHANNEL_HT40PLUS) {
6430 centers->synth_center =
6431 chan->channel + HT40_CHANNEL_CENTER_SHIFT;
6432 extoff = 1;
6433 } else {
6434 centers->synth_center =
6435 chan->channel - HT40_CHANNEL_CENTER_SHIFT;
6436 extoff = -1;
6437 }
6438
6439 centers->ctl_center = centers->synth_center - (extoff *
6440 HT40_CHANNEL_CENTER_SHIFT);
6441 centers->ext_center = centers->synth_center + (extoff *
6442 ((ahp->
6443 ah_extprotspacing
6444 ==
6445 HAL_HT_EXTPROTSPACING_20)
6446 ?
6447 HT40_CHANNEL_CENTER_SHIFT
6448 : 15));
6449
6450 }
6451
6452 void
6453 ath9k_hw_reset_calvalid(struct ath_hal *ah, struct hal_channel *chan,
6454 enum hal_bool *isCalDone)
6455 {
6456 struct ath_hal_5416 *ahp = AH5416(ah);
6457 struct hal_channel_internal *ichan =
6458 ath9k_regd_check_channel(ah, chan);
6459 struct hal_cal_list *currCal = ahp->ah_cal_list_curr;
6460
6461 *isCalDone = AH_TRUE;
6462
6463 if (!AR_SREV_9100(ah) && !AR_SREV_9160_10_OR_LATER(ah))
6464 return;
6465
6466 if (currCal == NULL)
6467 return;
6468
6469 if (ichan == NULL) {
6470 HDPRINTF(ah, HAL_DBG_CALIBRATE,
6471 "%s: invalid channel %u/0x%x; no mapping\n",
6472 __func__, chan->channel, chan->channelFlags);
6473 return;
6474 }
6475
6476
6477 if (currCal->calState != CAL_DONE) {
6478 HDPRINTF(ah, HAL_DBG_CALIBRATE,
6479 "%s: Calibration state incorrect, %d\n",
6480 __func__, currCal->calState);
6481 return;
6482 }
6483
6484
6485 if (ath9k_hw_iscal_supported(ah, chan, currCal->calData->calType)
6486 == AH_FALSE) {
6487 return;
6488 }
6489
6490 HDPRINTF(ah, HAL_DBG_CALIBRATE,
6491 "%s: Resetting Cal %d state for channel %u/0x%x\n",
6492 __func__, currCal->calData->calType, chan->channel,
6493 chan->channelFlags);
6494
6495 ichan->CalValid &= ~currCal->calData->calType;
6496 currCal->calState = CAL_WAITING;
6497
6498 *isCalDone = AH_FALSE;
6499 }
6500
6501 void ath9k_hw_getmac(struct ath_hal *ah, u_int8_t *mac)
6502 {
6503 struct ath_hal_5416 *ahp = AH5416(ah);
6504
6505 memcpy(mac, ahp->ah_macaddr, ETH_ALEN);
6506 }
6507
6508 enum hal_bool ath9k_hw_setmac(struct ath_hal *ah, const u_int8_t *mac)
6509 {
6510 struct ath_hal_5416 *ahp = AH5416(ah);
6511
6512 memcpy(ahp->ah_macaddr, mac, ETH_ALEN);
6513 return AH_TRUE;
6514 }
6515
6516 void ath9k_hw_getbssidmask(struct ath_hal *ah, u_int8_t *mask)
6517 {
6518 struct ath_hal_5416 *ahp = AH5416(ah);
6519
6520 memcpy(mask, ahp->ah_bssidmask, ETH_ALEN);
6521 }
6522
6523 enum hal_bool
6524 ath9k_hw_setbssidmask(struct ath_hal *ah, const u_int8_t *mask)
6525 {
6526 struct ath_hal_5416 *ahp = AH5416(ah);
6527
6528 memcpy(ahp->ah_bssidmask, mask, ETH_ALEN);
6529
6530 REG_WRITE(ah, AR_BSSMSKL, LE_READ_4(ahp->ah_bssidmask));
6531 REG_WRITE(ah, AR_BSSMSKU, LE_READ_2(ahp->ah_bssidmask + 4));
6532
6533 return AH_TRUE;
6534 }
6535
6536 #ifdef CONFIG_ATH9K_RFKILL
6537 static void ath9k_enable_rfkill(struct ath_hal *ah)
6538 {
6539 struct ath_hal_5416 *ahp = AH5416(ah);
6540
6541 OS_REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL,
6542 AR_GPIO_INPUT_EN_VAL_RFSILENT_BB);
6543
6544 OS_REG_CLR_BIT(ah, AR_GPIO_INPUT_MUX2,
6545 AR_GPIO_INPUT_MUX2_RFSILENT);
6546
6547 ath9k_hw_cfg_gpio_input(ah, ahp->ah_gpioSelect);
6548 OS_REG_SET_BIT(ah, AR_PHY_TEST, RFSILENT_BB);
6549
6550 if (ahp->ah_gpioBit == ath9k_hw_gpio_get(ah, ahp->ah_gpioSelect)) {
6551
6552 ath9k_hw_set_gpio_intr(ah, ahp->ah_gpioSelect,
6553 !ahp->ah_gpioBit);
6554 } else {
6555 ath9k_hw_set_gpio_intr(ah, ahp->ah_gpioSelect,
6556 ahp->ah_gpioBit);
6557 }
6558 }
6559 #endif
6560
6561 void
6562 ath9k_hw_write_associd(struct ath_hal *ah, const u_int8_t *bssid,
6563 u_int16_t assocId)
6564 {
6565 struct ath_hal_5416 *ahp = AH5416(ah);
6566
6567 memcpy(ahp->ah_bssid, bssid, ETH_ALEN);
6568 ahp->ah_assocId = assocId;
6569
6570 REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid));
6571 REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid + 4) |
6572 ((assocId & 0x3fff) << AR_BSS_ID1_AID_S));
6573 }
6574
6575 u_int64_t ath9k_hw_gettsf64(struct ath_hal *ah)
6576 {
6577 u_int64_t tsf;
6578
6579 tsf = REG_READ(ah, AR_TSF_U32);
6580 tsf = (tsf << 32) | REG_READ(ah, AR_TSF_L32);
6581 return tsf;
6582 }
6583
6584 void ath9k_hw_reset_tsf(struct ath_hal *ah)
6585 {
6586 int count;
6587
6588 count = 0;
6589 while (REG_READ(ah, AR_SLP32_MODE) & AR_SLP32_TSF_WRITE_STATUS) {
6590 count++;
6591 if (count > 10) {
6592 HDPRINTF(ah, HAL_DBG_RESET,
6593 "%s: AR_SLP32_TSF_WRITE_STATUS limit exceeded\n",
6594 __func__);
6595 break;
6596 }
6597 udelay(10);
6598 }
6599 REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
6600 }
6601
6602 u_int ath9k_hw_getdefantenna(struct ath_hal *ah)
6603 {
6604 return REG_READ(ah, AR_DEF_ANTENNA) & 0x7;
6605 }
6606
6607 void ath9k_hw_setantenna(struct ath_hal *ah, u_int antenna)
6608 {
6609 REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
6610 }
6611
6612 enum hal_bool
6613 ath9k_hw_setantennaswitch(struct ath_hal *ah,
6614 enum hal_ant_setting settings,
6615 struct hal_channel *chan,
6616 u_int8_t *tx_chainmask,
6617 u_int8_t *rx_chainmask,
6618 u_int8_t *antenna_cfgd)
6619 {
6620 struct ath_hal_5416 *ahp = AH5416(ah);
6621 static u_int8_t tx_chainmask_cfg, rx_chainmask_cfg;
6622
6623 if (AR_SREV_9280(ah)) {
6624 if (!tx_chainmask_cfg) {
6625
6626 tx_chainmask_cfg = *tx_chainmask;
6627 rx_chainmask_cfg = *rx_chainmask;
6628 }
6629
6630 switch (settings) {
6631 case HAL_ANT_FIXED_A:
6632 *tx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
6633 *rx_chainmask = ATH9K_ANTENNA0_CHAINMASK;
6634 *antenna_cfgd = AH_TRUE;
6635 break;
6636 case HAL_ANT_FIXED_B:
6637 if (ah->ah_caps.halTxChainMask >
6638 ATH9K_ANTENNA1_CHAINMASK) {
6639 *tx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
6640 }
6641 *rx_chainmask = ATH9K_ANTENNA1_CHAINMASK;
6642 *antenna_cfgd = AH_TRUE;
6643 break;
6644 case HAL_ANT_VARIABLE:
6645 *tx_chainmask = tx_chainmask_cfg;
6646 *rx_chainmask = rx_chainmask_cfg;
6647 *antenna_cfgd = AH_TRUE;
6648 break;
6649 default:
6650 break;
6651 }
6652 } else {
6653 ahp->ah_diversityControl = settings;
6654 }
6655
6656 return AH_TRUE;
6657 }
6658
6659 void ath9k_hw_setopmode(struct ath_hal *ah)
6660 {
6661 ath9k_hw_set_operating_mode(ah, ah->ah_opmode);
6662 }
6663
6664 enum hal_bool
6665 ath9k_hw_getcapability(struct ath_hal *ah, enum hal_capability_type type,
6666 u_int32_t capability, u_int32_t *result)
6667 {
6668 struct ath_hal_5416 *ahp = AH5416(ah);
6669 const struct hal_capabilities *pCap = &ah->ah_caps;
6670
6671 switch (type) {
6672 case HAL_CAP_CIPHER:
6673 switch (capability) {
6674 case HAL_CIPHER_AES_CCM:
6675 case HAL_CIPHER_AES_OCB:
6676 case HAL_CIPHER_TKIP:
6677 case HAL_CIPHER_WEP:
6678 case HAL_CIPHER_MIC:
6679 case HAL_CIPHER_CLR:
6680 return AH_TRUE;
6681 default:
6682 return AH_FALSE;
6683 }
6684 case HAL_CAP_TKIP_MIC:
6685 switch (capability) {
6686 case 0:
6687 return AH_TRUE;
6688 case 1:
6689 return (ahp->ah_staId1Defaults &
6690 AR_STA_ID1_CRPT_MIC_ENABLE) ? AH_TRUE :
6691 AH_FALSE;
6692 }
6693 case HAL_CAP_TKIP_SPLIT:
6694 return (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) ?
6695 AH_FALSE : AH_TRUE;
6696 case HAL_CAP_WME_TKIPMIC:
6697 return HAL_OK;
6698 case HAL_CAP_PHYCOUNTERS:
6699 return ahp->ah_hasHwPhyCounters ? HAL_OK : HAL_ENXIO;
6700 case HAL_CAP_DIVERSITY:
6701 switch (capability) {
6702 case 0:
6703 return AH_TRUE;
6704 case 1:
6705 return (REG_READ(ah, AR_PHY_CCK_DETECT) &
6706 AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV) ?
6707 AH_TRUE : AH_FALSE;
6708 }
6709 return AH_FALSE;
6710 case HAL_CAP_PHYDIAG:
6711 return AH_TRUE;
6712 case HAL_CAP_MCAST_KEYSRCH:
6713 switch (capability) {
6714 case 0:
6715 return AH_TRUE;
6716 case 1:
6717 if (REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_ADHOC) {
6718 return AH_FALSE;
6719 } else {
6720 return (ahp->ah_staId1Defaults &
6721 AR_STA_ID1_MCAST_KSRCH) ? AH_TRUE :
6722 AH_FALSE;
6723 }
6724 }
6725 return AH_FALSE;
6726 case HAL_CAP_TSF_ADJUST:
6727 switch (capability) {
6728 case 0:
6729 return AH_TRUE;
6730 case 1:
6731 return (ahp->ah_miscMode & AR_PCU_TX_ADD_TSF) ?
6732 AH_TRUE : AH_FALSE;
6733 }
6734 return AH_FALSE;
6735 case HAL_CAP_RFSILENT:
6736 if (capability == 3)
6737 return AH_FALSE;
6738 case HAL_CAP_ANT_CFG_2GHZ:
6739 *result = pCap->halNumAntCfg2GHz;
6740 return AH_TRUE;
6741 case HAL_CAP_ANT_CFG_5GHZ:
6742 *result = pCap->halNumAntCfg5GHz;
6743 return AH_TRUE;
6744 case HAL_CAP_TXPOW:
6745 switch (capability) {
6746 case 0:
6747 return HAL_OK;
6748 case 1:
6749 *result = ah->ah_powerLimit;
6750 return HAL_OK;
6751 case 2:
6752 *result = ah->ah_maxPowerLevel;
6753 return HAL_OK;
6754 case 3:
6755 *result = ah->ah_tpScale;
6756 return HAL_OK;
6757 }
6758 return AH_FALSE;
6759 default:
6760 return AH_FALSE;
6761 }
6762 }
6763
6764 enum hal_status
6765 ath9k_hw_select_antconfig(struct ath_hal *ah, u_int32_t cfg)
6766 {
6767 struct ath_hal_5416 *ahp = AH5416(ah);
6768 struct hal_channel_internal *chan = ah->ah_curchan;
6769 const struct hal_capabilities *pCap = &ah->ah_caps;
6770 u_int16_t ant_config;
6771 u_int32_t halNumAntConfig;
6772
6773 halNumAntConfig =
6774 IS_CHAN_2GHZ(chan) ? pCap->halNumAntCfg2GHz : pCap->
6775 halNumAntCfg5GHz;
6776
6777 if (cfg < halNumAntConfig) {
6778 if (HAL_OK ==
6779 ath9k_hw_get_eeprom_antenna_cfg(ahp, chan, cfg,
6780 &ant_config)) {
6781 REG_WRITE(ah, AR_PHY_SWITCH_COM, ant_config);
6782 return HAL_OK;
6783 }
6784 }
6785
6786 return HAL_EINVAL;
6787 }
6788
6789 enum hal_bool ath9k_hw_intrpend(struct ath_hal *ah)
6790 {
6791 u_int32_t host_isr;
6792
6793 if (AR_SREV_9100(ah))
6794 return AH_TRUE;
6795
6796 host_isr = REG_READ(ah, AR_INTR_ASYNC_CAUSE);
6797 if ((host_isr & AR_INTR_MAC_IRQ) && (host_isr != AR_INTR_SPURIOUS))
6798 return AH_TRUE;
6799
6800 host_isr = REG_READ(ah, AR_INTR_SYNC_CAUSE);
6801 if ((host_isr & AR_INTR_SYNC_DEFAULT)
6802 && (host_isr != AR_INTR_SPURIOUS))
6803 return AH_TRUE;
6804
6805 return AH_FALSE;
6806 }
6807
6808 enum hal_bool ath9k_hw_getisr(struct ath_hal *ah, enum hal_int *masked)
6809 {
6810 u_int32_t isr = 0;
6811 u_int32_t mask2 = 0;
6812 struct hal_capabilities *pCap = &ah->ah_caps;
6813 u_int32_t sync_cause = 0;
6814 enum hal_bool fatal_int = AH_FALSE;
6815
6816 if (!AR_SREV_9100(ah)) {
6817 if (REG_READ(ah, AR_INTR_ASYNC_CAUSE) & AR_INTR_MAC_IRQ) {
6818 if ((REG_READ(ah, AR_RTC_STATUS) & AR_RTC_STATUS_M)
6819 == AR_RTC_STATUS_ON) {
6820 isr = REG_READ(ah, AR_ISR);
6821 }
6822 }
6823
6824 sync_cause =
6825 REG_READ(ah,
6826 AR_INTR_SYNC_CAUSE) & AR_INTR_SYNC_DEFAULT;
6827
6828 *masked = 0;
6829
6830 if (!isr && !sync_cause)
6831 return AH_FALSE;
6832 } else {
6833 *masked = 0;
6834 isr = REG_READ(ah, AR_ISR);
6835 }
6836
6837 if (isr) {
6838 struct ath_hal_5416 *ahp = AH5416(ah);
6839
6840 if (isr & AR_ISR_BCNMISC) {
6841 u_int32_t isr2;
6842 isr2 = REG_READ(ah, AR_ISR_S2);
6843 if (isr2 & AR_ISR_S2_TIM)
6844 mask2 |= HAL_INT_TIM;
6845 if (isr2 & AR_ISR_S2_DTIM)
6846 mask2 |= HAL_INT_DTIM;
6847 if (isr2 & AR_ISR_S2_DTIMSYNC)
6848 mask2 |= HAL_INT_DTIMSYNC;
6849 if (isr2 & (AR_ISR_S2_CABEND))
6850 mask2 |= HAL_INT_CABEND;
6851 if (isr2 & AR_ISR_S2_GTT)
6852 mask2 |= HAL_INT_GTT;
6853 if (isr2 & AR_ISR_S2_CST)
6854 mask2 |= HAL_INT_CST;
6855 }
6856
6857 isr = REG_READ(ah, AR_ISR_RAC);
6858 if (isr == 0xffffffff) {
6859 *masked = 0;
6860 return AH_FALSE;
6861 }
6862
6863 *masked = isr & HAL_INT_COMMON;
6864
6865 if (ahp->ah_intrMitigation) {
6866
6867 if (isr & (AR_ISR_RXMINTR | AR_ISR_RXINTM))
6868 *masked |= HAL_INT_RX;
6869 }
6870
6871 if (isr & (AR_ISR_RXOK | AR_ISR_RXERR))
6872 *masked |= HAL_INT_RX;
6873 if (isr &
6874 (AR_ISR_TXOK | AR_ISR_TXDESC | AR_ISR_TXERR |
6875 AR_ISR_TXEOL)) {
6876 u_int32_t s0_s, s1_s;
6877
6878 *masked |= HAL_INT_TX;
6879
6880 s0_s = REG_READ(ah, AR_ISR_S0_S);
6881 ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXOK);
6882 ahp->ah_intrTxqs |= MS(s0_s, AR_ISR_S0_QCU_TXDESC);
6883
6884 s1_s = REG_READ(ah, AR_ISR_S1_S);
6885 ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXERR);
6886 ahp->ah_intrTxqs |= MS(s1_s, AR_ISR_S1_QCU_TXEOL);
6887 }
6888
6889 if (isr & AR_ISR_RXORN) {
6890 HDPRINTF(ah, HAL_DBG_INTERRUPT,
6891 "%s: receive FIFO overrun interrupt\n",
6892 __func__);
6893 }
6894
6895 if (!AR_SREV_9100(ah)) {
6896 if (!pCap->halAutoSleepSupport) {
6897 u_int32_t isr5 = REG_READ(ah, AR_ISR_S5_S);
6898 if (isr5 & AR_ISR_S5_TIM_TIMER)
6899 *masked |= HAL_INT_TIM_TIMER;
6900 }
6901 }
6902
6903 *masked |= mask2;
6904 }
6905 if (AR_SREV_9100(ah))
6906 return AH_TRUE;
6907 if (sync_cause) {
6908 fatal_int =
6909 (sync_cause &
6910 (AR_INTR_SYNC_HOST1_FATAL | AR_INTR_SYNC_HOST1_PERR))
6911 ? AH_TRUE : AH_FALSE;
6912
6913 if (AH_TRUE == fatal_int) {
6914 if (sync_cause & AR_INTR_SYNC_HOST1_FATAL) {
6915 HDPRINTF(ah, HAL_DBG_UNMASKABLE,
6916 "%s: received PCI FATAL interrupt\n",
6917 __func__);
6918 }
6919 if (sync_cause & AR_INTR_SYNC_HOST1_PERR) {
6920 HDPRINTF(ah, HAL_DBG_UNMASKABLE,
6921 "%s: received PCI PERR interrupt\n",
6922 __func__);
6923 }
6924 }
6925 if (sync_cause & AR_INTR_SYNC_RADM_CPL_TIMEOUT) {
6926 HDPRINTF(ah, HAL_DBG_INTERRUPT,
6927 "%s: AR_INTR_SYNC_RADM_CPL_TIMEOUT\n",
6928 __func__);
6929 REG_WRITE(ah, AR_RC, AR_RC_HOSTIF);
6930 REG_WRITE(ah, AR_RC, 0);
6931 *masked |= HAL_INT_FATAL;
6932 }
6933 if (sync_cause & AR_INTR_SYNC_LOCAL_TIMEOUT) {
6934 HDPRINTF(ah, HAL_DBG_INTERRUPT,
6935 "%s: AR_INTR_SYNC_LOCAL_TIMEOUT\n",
6936 __func__);
6937 }
6938
6939 REG_WRITE(ah, AR_INTR_SYNC_CAUSE_CLR, sync_cause);
6940 (void) REG_READ(ah, AR_INTR_SYNC_CAUSE_CLR);
6941 }
6942 return AH_TRUE;
6943 }
6944
6945 enum hal_int ath9k_hw_intrget(struct ath_hal *ah)
6946 {
6947 return AH5416(ah)->ah_maskReg;
6948 }
6949
6950 enum hal_int ath9k_hw_set_interrupts(struct ath_hal *ah, enum hal_int ints)
6951 {
6952 struct ath_hal_5416 *ahp = AH5416(ah);
6953 u_int32_t omask = ahp->ah_maskReg;
6954 u_int32_t mask, mask2;
6955 struct hal_capabilities *pCap = &ah->ah_caps;
6956
6957 HDPRINTF(ah, HAL_DBG_INTERRUPT, "%s: 0x%x => 0x%x\n", __func__,
6958 omask, ints);
6959
6960 if (omask & HAL_INT_GLOBAL) {
6961 HDPRINTF(ah, HAL_DBG_INTERRUPT, "%s: disable IER\n",
6962 __func__);
6963 REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
6964 (void) REG_READ(ah, AR_IER);
6965 if (!AR_SREV_9100(ah)) {
6966 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE, 0);
6967 (void) REG_READ(ah, AR_INTR_ASYNC_ENABLE);
6968
6969 REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
6970 (void) REG_READ(ah, AR_INTR_SYNC_ENABLE);
6971 }
6972 }
6973
6974 mask = ints & HAL_INT_COMMON;
6975 mask2 = 0;
6976
6977 if (ints & HAL_INT_TX) {
6978 if (ahp->ah_txOkInterruptMask)
6979 mask |= AR_IMR_TXOK;
6980 if (ahp->ah_txDescInterruptMask)
6981 mask |= AR_IMR_TXDESC;
6982 if (ahp->ah_txErrInterruptMask)
6983 mask |= AR_IMR_TXERR;
6984 if (ahp->ah_txEolInterruptMask)
6985 mask |= AR_IMR_TXEOL;
6986 }
6987 if (ints & HAL_INT_RX) {
6988 mask |= AR_IMR_RXERR;
6989 if (ahp->ah_intrMitigation)
6990 mask |= AR_IMR_RXMINTR | AR_IMR_RXINTM;
6991 else
6992 mask |= AR_IMR_RXOK | AR_IMR_RXDESC;
6993 if (!pCap->halAutoSleepSupport)
6994 mask |= AR_IMR_GENTMR;
6995 }
6996
6997 if (ints & (HAL_INT_BMISC)) {
6998 mask |= AR_IMR_BCNMISC;
6999 if (ints & HAL_INT_TIM)
7000 mask2 |= AR_IMR_S2_TIM;
7001 if (ints & HAL_INT_DTIM)
7002 mask2 |= AR_IMR_S2_DTIM;
7003 if (ints & HAL_INT_DTIMSYNC)
7004 mask2 |= AR_IMR_S2_DTIMSYNC;
7005 if (ints & HAL_INT_CABEND)
7006 mask2 |= (AR_IMR_S2_CABEND);
7007 }
7008
7009 if (ints & (HAL_INT_GTT | HAL_INT_CST)) {
7010 mask |= AR_IMR_BCNMISC;
7011 if (ints & HAL_INT_GTT)
7012 mask2 |= AR_IMR_S2_GTT;
7013 if (ints & HAL_INT_CST)
7014 mask2 |= AR_IMR_S2_CST;
7015 }
7016
7017 HDPRINTF(ah, HAL_DBG_INTERRUPT, "%s: new IMR 0x%x\n", __func__,
7018 mask);
7019 REG_WRITE(ah, AR_IMR, mask);
7020 mask = REG_READ(ah, AR_IMR_S2) & ~(AR_IMR_S2_TIM |
7021 AR_IMR_S2_DTIM |
7022 AR_IMR_S2_DTIMSYNC |
7023 AR_IMR_S2_CABEND |
7024 AR_IMR_S2_CABTO |
7025 AR_IMR_S2_TSFOOR |
7026 AR_IMR_S2_GTT | AR_IMR_S2_CST);
7027 REG_WRITE(ah, AR_IMR_S2, mask | mask2);
7028 ahp->ah_maskReg = ints;
7029
7030 if (!pCap->halAutoSleepSupport) {
7031 if (ints & HAL_INT_TIM_TIMER)
7032 OS_REG_SET_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
7033 else
7034 OS_REG_CLR_BIT(ah, AR_IMR_S5, AR_IMR_S5_TIM_TIMER);
7035 }
7036
7037 if (ints & HAL_INT_GLOBAL) {
7038 HDPRINTF(ah, HAL_DBG_INTERRUPT, "%s: enable IER\n",
7039 __func__);
7040 REG_WRITE(ah, AR_IER, AR_IER_ENABLE);
7041 if (!AR_SREV_9100(ah)) {
7042 REG_WRITE(ah, AR_INTR_ASYNC_ENABLE,
7043 AR_INTR_MAC_IRQ);
7044 REG_WRITE(ah, AR_INTR_ASYNC_MASK, AR_INTR_MAC_IRQ);
7045
7046
7047 REG_WRITE(ah, AR_INTR_SYNC_ENABLE,
7048 AR_INTR_SYNC_DEFAULT);
7049 REG_WRITE(ah, AR_INTR_SYNC_MASK,
7050 AR_INTR_SYNC_DEFAULT);
7051 }
7052 HDPRINTF(ah, HAL_DBG_INTERRUPT, "AR_IMR 0x%x IER 0x%x\n",
7053 REG_READ(ah, AR_IMR), REG_READ(ah, AR_IER));
7054 }
7055
7056 return omask;
7057 }
7058
7059 void
7060 ath9k_hw_beaconinit(struct ath_hal *ah,
7061 u_int32_t next_beacon, u_int32_t beacon_period)
7062 {
7063 struct ath_hal_5416 *ahp = AH5416(ah);
7064 int flags = 0;
7065
7066 ahp->ah_beaconInterval = beacon_period;
7067
7068 switch (ah->ah_opmode) {
7069 case HAL_M_STA:
7070 case HAL_M_MONITOR:
7071 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
7072 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, 0xffff);
7073 REG_WRITE(ah, AR_NEXT_SWBA, 0x7ffff);
7074 flags |= AR_TBTT_TIMER_EN;
7075 break;
7076 case HAL_M_IBSS:
7077 OS_REG_SET_BIT(ah, AR_TXCFG,
7078 AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
7079 REG_WRITE(ah, AR_NEXT_NDP_TIMER,
7080 TU_TO_USEC(next_beacon +
7081 (ahp->ah_atimWindow ? ahp->
7082 ah_atimWindow : 1)));
7083 flags |= AR_NDP_TIMER_EN;
7084 case HAL_M_HOSTAP:
7085 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(next_beacon));
7086 REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT,
7087 TU_TO_USEC(next_beacon -
7088 ah->ah_config.
7089 ath_hal_dma_beacon_response_time));
7090 REG_WRITE(ah, AR_NEXT_SWBA,
7091 TU_TO_USEC(next_beacon -
7092 ah->ah_config.
7093 ath_hal_sw_beacon_response_time));
7094 flags |=
7095 AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
7096 break;
7097 }
7098
7099 REG_WRITE(ah, AR_BEACON_PERIOD, TU_TO_USEC(beacon_period));
7100 REG_WRITE(ah, AR_DMA_BEACON_PERIOD, TU_TO_USEC(beacon_period));
7101 REG_WRITE(ah, AR_SWBA_PERIOD, TU_TO_USEC(beacon_period));
7102 REG_WRITE(ah, AR_NDP_PERIOD, TU_TO_USEC(beacon_period));
7103
7104 beacon_period &= ~HAL_BEACON_ENA;
7105 if (beacon_period & HAL_BEACON_RESET_TSF) {
7106 beacon_period &= ~HAL_BEACON_RESET_TSF;
7107 ath9k_hw_reset_tsf(ah);
7108 }
7109
7110 OS_REG_SET_BIT(ah, AR_TIMER_MODE, flags);
7111 }
7112
7113 void
7114 ath9k_hw_set_sta_beacon_timers(struct ath_hal *ah,
7115 const struct hal_beacon_state *bs)
7116 {
7117 u_int32_t nextTbtt, beaconintval, dtimperiod, beacontimeout;
7118 struct hal_capabilities *pCap = &ah->ah_caps;
7119
7120 REG_WRITE(ah, AR_NEXT_TBTT_TIMER, TU_TO_USEC(bs->bs_nexttbtt));
7121
7122 REG_WRITE(ah, AR_BEACON_PERIOD,
7123 TU_TO_USEC(bs->bs_intval & HAL_BEACON_PERIOD));
7124 REG_WRITE(ah, AR_DMA_BEACON_PERIOD,
7125 TU_TO_USEC(bs->bs_intval & HAL_BEACON_PERIOD));
7126
7127 OS_REG_RMW_FIELD(ah, AR_RSSI_THR,
7128 AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
7129
7130 beaconintval = bs->bs_intval & HAL_BEACON_PERIOD;
7131
7132 if (bs->bs_sleepduration > beaconintval)
7133 beaconintval = bs->bs_sleepduration;
7134
7135 dtimperiod = bs->bs_dtimperiod;
7136 if (bs->bs_sleepduration > dtimperiod)
7137 dtimperiod = bs->bs_sleepduration;
7138
7139 if (beaconintval == dtimperiod)
7140 nextTbtt = bs->bs_nextdtim;
7141 else
7142 nextTbtt = bs->bs_nexttbtt;
7143
7144 HDPRINTF(ah, HAL_DBG_BEACON, "%s: next DTIM %d\n", __func__,
7145 bs->bs_nextdtim);
7146 HDPRINTF(ah, HAL_DBG_BEACON, "%s: next beacon %d\n", __func__,
7147 nextTbtt);
7148 HDPRINTF(ah, HAL_DBG_BEACON, "%s: beacon period %d\n", __func__,
7149 beaconintval);
7150 HDPRINTF(ah, HAL_DBG_BEACON, "%s: DTIM period %d\n", __func__,
7151 dtimperiod);
7152
7153 REG_WRITE(ah, AR_NEXT_DTIM,
7154 TU_TO_USEC(bs->bs_nextdtim - SLEEP_SLOP));
7155 REG_WRITE(ah, AR_NEXT_TIM, TU_TO_USEC(nextTbtt - SLEEP_SLOP));
7156
7157 REG_WRITE(ah, AR_SLEEP1,
7158 SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
7159 | AR_SLEEP1_ASSUME_DTIM);
7160
7161 if (pCap->halAutoSleepSupport)
7162 beacontimeout = (BEACON_TIMEOUT_VAL << 3);
7163 else
7164 beacontimeout = MIN_BEACON_TIMEOUT_VAL;
7165
7166 REG_WRITE(ah, AR_SLEEP2,
7167 SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
7168
7169 REG_WRITE(ah, AR_TIM_PERIOD, TU_TO_USEC(beaconintval));
7170 REG_WRITE(ah, AR_DTIM_PERIOD, TU_TO_USEC(dtimperiod));
7171
7172 OS_REG_SET_BIT(ah, AR_TIMER_MODE,
7173 AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
7174 AR_DTIM_TIMER_EN);
7175
7176 }
7177
7178 enum hal_bool ath9k_hw_keyisvalid(struct ath_hal *ah, u_int16_t entry)
7179 {
7180 if (entry < ah->ah_caps.halKeyCacheSize) {
7181 u_int32_t val = REG_READ(ah, AR_KEYTABLE_MAC1(entry));
7182 if (val & AR_KEYTABLE_VALID)
7183 return AH_TRUE;
7184 }
7185 return AH_FALSE;
7186 }
7187
7188 enum hal_bool ath9k_hw_keyreset(struct ath_hal *ah, u_int16_t entry)
7189 {
7190 u_int32_t keyType;
7191
7192 if (entry >= ah->ah_caps.halKeyCacheSize) {
7193 HDPRINTF(ah, HAL_DBG_KEYCACHE,
7194 "%s: entry %u out of range\n", __func__, entry);
7195 return AH_FALSE;
7196 }
7197 keyType = REG_READ(ah, AR_KEYTABLE_TYPE(entry));
7198
7199 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), 0);
7200 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), 0);
7201 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), 0);
7202 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), 0);
7203 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), 0);
7204 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), AR_KEYTABLE_TYPE_CLR);
7205 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), 0);
7206 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), 0);
7207
7208 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
7209 u_int16_t micentry = entry + 64;
7210
7211 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), 0);
7212 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
7213 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), 0);
7214 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
7215
7216 }
7217
7218 if (ah->ah_curchan == NULL)
7219 return AH_TRUE;
7220
7221 return AH_TRUE;
7222 }
7223
7224 enum hal_bool
7225 ath9k_hw_keysetmac(struct ath_hal *ah, u_int16_t entry,
7226 const u_int8_t *mac)
7227 {
7228 u_int32_t macHi, macLo;
7229
7230 if (entry >= ah->ah_caps.halKeyCacheSize) {
7231 HDPRINTF(ah, HAL_DBG_KEYCACHE,
7232 "%s: entry %u out of range\n", __func__, entry);
7233 return AH_FALSE;
7234 }
7235
7236 if (mac != NULL) {
7237 macHi = (mac[5] << 8) | mac[4];
7238 macLo = (mac[3] << 24) | (mac[2] << 16)
7239 | (mac[1] << 8) | mac[0];
7240 macLo >>= 1;
7241 macLo |= (macHi & 1) << 31;
7242 macHi >>= 1;
7243 } else {
7244 macLo = macHi = 0;
7245 }
7246 REG_WRITE(ah, AR_KEYTABLE_MAC0(entry), macLo);
7247 REG_WRITE(ah, AR_KEYTABLE_MAC1(entry), macHi | AR_KEYTABLE_VALID);
7248
7249 return AH_TRUE;
7250 }
7251
7252 enum hal_bool
7253 ath9k_hw_set_keycache_entry(struct ath_hal *ah, u_int16_t entry,
7254 const struct hal_keyval *k,
7255 const u_int8_t *mac, int xorKey)
7256 {
7257 const struct hal_capabilities *pCap = &ah->ah_caps;
7258 u_int32_t key0, key1, key2, key3, key4;
7259 u_int32_t keyType;
7260 u_int32_t xorMask = xorKey ?
7261 (ATH9K_KEY_XOR << 24 | ATH9K_KEY_XOR << 16 | ATH9K_KEY_XOR << 8
7262 | ATH9K_KEY_XOR) : 0;
7263 struct ath_hal_5416 *ahp = AH5416(ah);
7264
7265 if (entry >= pCap->halKeyCacheSize) {
7266 HDPRINTF(ah, HAL_DBG_KEYCACHE,
7267 "%s: entry %u out of range\n", __func__, entry);
7268 return AH_FALSE;
7269 }
7270 switch (k->kv_type) {
7271 case HAL_CIPHER_AES_OCB:
7272 keyType = AR_KEYTABLE_TYPE_AES;
7273 break;
7274 case HAL_CIPHER_AES_CCM:
7275 if (!pCap->halCipherAesCcmSupport) {
7276 HDPRINTF(ah, HAL_DBG_KEYCACHE,
7277 "%s: AES-CCM not supported by "
7278 "mac rev 0x%x\n", __func__,
7279 ah->ah_macRev);
7280 return AH_FALSE;
7281 }
7282 keyType = AR_KEYTABLE_TYPE_CCM;
7283 break;
7284 case HAL_CIPHER_TKIP:
7285 keyType = AR_KEYTABLE_TYPE_TKIP;
7286 if (ATH9K_IS_MIC_ENABLED(ah)
7287 && entry + 64 >= pCap->halKeyCacheSize) {
7288 HDPRINTF(ah, HAL_DBG_KEYCACHE,
7289 "%s: entry %u inappropriate for TKIP\n",
7290 __func__, entry);
7291 return AH_FALSE;
7292 }
7293 break;
7294 case HAL_CIPHER_WEP:
7295 if (k->kv_len < 40 / NBBY) {
7296 HDPRINTF(ah, HAL_DBG_KEYCACHE,
7297 "%s: WEP key length %u too small\n",
7298 __func__, k->kv_len);
7299 return AH_FALSE;
7300 }
7301 if (k->kv_len <= 40 / NBBY)
7302 keyType = AR_KEYTABLE_TYPE_40;
7303 else if (k->kv_len <= 104 / NBBY)
7304 keyType = AR_KEYTABLE_TYPE_104;
7305 else
7306 keyType = AR_KEYTABLE_TYPE_128;
7307 break;
7308 case HAL_CIPHER_CLR:
7309 keyType = AR_KEYTABLE_TYPE_CLR;
7310 break;
7311 default:
7312 HDPRINTF(ah, HAL_DBG_KEYCACHE,
7313 "%s: cipher %u not supported\n", __func__,
7314 k->kv_type);
7315 return AH_FALSE;
7316 }
7317
7318 key0 = LE_READ_4(k->kv_val + 0) ^ xorMask;
7319 key1 = (LE_READ_2(k->kv_val + 4) ^ xorMask) & 0xffff;
7320 key2 = LE_READ_4(k->kv_val + 6) ^ xorMask;
7321 key3 = (LE_READ_2(k->kv_val + 10) ^ xorMask) & 0xffff;
7322 key4 = LE_READ_4(k->kv_val + 12) ^ xorMask;
7323 if (k->kv_len <= 104 / NBBY)
7324 key4 &= 0xff;
7325
7326 if (keyType == AR_KEYTABLE_TYPE_TKIP && ATH9K_IS_MIC_ENABLED(ah)) {
7327 u_int16_t micentry = entry + 64;
7328
7329 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), ~key0);
7330 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), ~key1);
7331 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
7332 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
7333 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
7334 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
7335 (void) ath9k_hw_keysetmac(ah, entry, mac);
7336
7337 if (ahp->ah_miscMode & AR_PCU_MIC_NEW_LOC_ENA) {
7338 u_int32_t mic0, mic1, mic2, mic3, mic4;
7339
7340 mic0 = LE_READ_4(k->kv_mic + 0);
7341 mic2 = LE_READ_4(k->kv_mic + 4);
7342 mic1 = LE_READ_2(k->kv_txmic + 2) & 0xffff;
7343 mic3 = LE_READ_2(k->kv_txmic + 0) & 0xffff;
7344 mic4 = LE_READ_4(k->kv_txmic + 4);
7345 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
7346 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), mic1);
7347 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
7348 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), mic3);
7349 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), mic4);
7350 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
7351 AR_KEYTABLE_TYPE_CLR);
7352
7353 } else {
7354 u_int32_t mic0, mic2;
7355
7356 mic0 = LE_READ_4(k->kv_mic + 0);
7357 mic2 = LE_READ_4(k->kv_mic + 4);
7358 REG_WRITE(ah, AR_KEYTABLE_KEY0(micentry), mic0);
7359 REG_WRITE(ah, AR_KEYTABLE_KEY1(micentry), 0);
7360 REG_WRITE(ah, AR_KEYTABLE_KEY2(micentry), mic2);
7361 REG_WRITE(ah, AR_KEYTABLE_KEY3(micentry), 0);
7362 REG_WRITE(ah, AR_KEYTABLE_KEY4(micentry), 0);
7363 REG_WRITE(ah, AR_KEYTABLE_TYPE(micentry),
7364 AR_KEYTABLE_TYPE_CLR);
7365 }
7366 REG_WRITE(ah, AR_KEYTABLE_MAC0(micentry), 0);
7367 REG_WRITE(ah, AR_KEYTABLE_MAC1(micentry), 0);
7368 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
7369 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
7370 } else {
7371 REG_WRITE(ah, AR_KEYTABLE_KEY0(entry), key0);
7372 REG_WRITE(ah, AR_KEYTABLE_KEY1(entry), key1);
7373 REG_WRITE(ah, AR_KEYTABLE_KEY2(entry), key2);
7374 REG_WRITE(ah, AR_KEYTABLE_KEY3(entry), key3);
7375 REG_WRITE(ah, AR_KEYTABLE_KEY4(entry), key4);
7376 REG_WRITE(ah, AR_KEYTABLE_TYPE(entry), keyType);
7377
7378 (void) ath9k_hw_keysetmac(ah, entry, mac);
7379 }
7380
7381 if (ah->ah_curchan == NULL)
7382 return AH_TRUE;
7383
7384 return AH_TRUE;
7385 }
7386
7387 enum hal_bool
7388 ath9k_hw_updatetxtriglevel(struct ath_hal *ah, enum hal_bool bIncTrigLevel)
7389 {
7390 struct ath_hal_5416 *ahp = AH5416(ah);
7391 u_int32_t txcfg, curLevel, newLevel;
7392 enum hal_int omask;
7393
7394 if (ah->ah_txTrigLevel >= MAX_TX_FIFO_THRESHOLD)
7395 return AH_FALSE;
7396
7397 omask = ath9k_hw_set_interrupts(ah, ahp->ah_maskReg & ~HAL_INT_GLOBAL);
7398
7399 txcfg = REG_READ(ah, AR_TXCFG);
7400 curLevel = MS(txcfg, AR_FTRIG);
7401 newLevel = curLevel;
7402 if (bIncTrigLevel) {
7403 if (curLevel < MAX_TX_FIFO_THRESHOLD)
7404 newLevel++;
7405 } else if (curLevel > MIN_TX_FIFO_THRESHOLD)
7406 newLevel--;
7407 if (newLevel != curLevel)
7408 REG_WRITE(ah, AR_TXCFG,
7409 (txcfg & ~AR_FTRIG) | SM(newLevel, AR_FTRIG));
7410
7411 ath9k_hw_set_interrupts(ah, omask);
7412
7413 ah->ah_txTrigLevel = newLevel;
7414
7415 return newLevel != curLevel;
7416 }
7417
7418 static enum hal_bool ath9k_hw_set_txq_props(struct ath_hal *ah,
7419 struct hal_tx_queue_info *qi,
7420 const struct hal_txq_info *qInfo)
7421 {
7422 u_int32_t cw;
7423
7424 if (qi->tqi_type == HAL_TX_QUEUE_INACTIVE) {
7425 HDPRINTF(ah, HAL_DBG_QUEUE, "%s: inactive queue\n",
7426 __func__);
7427 return AH_FALSE;
7428 }
7429
7430 HDPRINTF(ah, HAL_DBG_QUEUE, "%s: queue %p\n", __func__, qi);
7431
7432 qi->tqi_ver = qInfo->tqi_ver;
7433 qi->tqi_subtype = qInfo->tqi_subtype;
7434 qi->tqi_qflags = qInfo->tqi_qflags;
7435 qi->tqi_priority = qInfo->tqi_priority;
7436 if (qInfo->tqi_aifs != HAL_TXQ_USEDEFAULT)
7437 qi->tqi_aifs = min(qInfo->tqi_aifs, 255U);
7438 else
7439 qi->tqi_aifs = INIT_AIFS;
7440 if (qInfo->tqi_cwmin != HAL_TXQ_USEDEFAULT) {
7441 cw = min(qInfo->tqi_cwmin, 1024U);
7442 qi->tqi_cwmin = 1;
7443 while (qi->tqi_cwmin < cw)
7444 qi->tqi_cwmin = (qi->tqi_cwmin << 1) | 1;
7445 } else
7446 qi->tqi_cwmin = qInfo->tqi_cwmin;
7447 if (qInfo->tqi_cwmax != HAL_TXQ_USEDEFAULT) {
7448 cw = min(qInfo->tqi_cwmax, 1024U);
7449 qi->tqi_cwmax = 1;
7450 while (qi->tqi_cwmax < cw)
7451 qi->tqi_cwmax = (qi->tqi_cwmax << 1) | 1;
7452 } else
7453 qi->tqi_cwmax = INIT_CWMAX;
7454
7455 if (qInfo->tqi_shretry != 0)
7456 qi->tqi_shretry = min((u_int32_t) qInfo->tqi_shretry, 15U);
7457 else
7458 qi->tqi_shretry = INIT_SH_RETRY;
7459 if (qInfo->tqi_lgretry != 0)
7460 qi->tqi_lgretry = min((u_int32_t) qInfo->tqi_lgretry, 15U);
7461 else
7462 qi->tqi_lgretry = INIT_LG_RETRY;
7463 qi->tqi_cbrPeriod = qInfo->tqi_cbrPeriod;
7464 qi->tqi_cbrOverflowLimit = qInfo->tqi_cbrOverflowLimit;
7465 qi->tqi_burstTime = qInfo->tqi_burstTime;
7466 qi->tqi_readyTime = qInfo->tqi_readyTime;
7467
7468 switch (qInfo->tqi_subtype) {
7469 case HAL_WME_UPSD:
7470 if (qi->tqi_type == HAL_TX_QUEUE_DATA)
7471 qi->tqi_intFlags = HAL_TXQ_USE_LOCKOUT_BKOFF_DIS;
7472 break;
7473 default:
7474 break;
7475 }
7476 return AH_TRUE;
7477 }
7478
7479 enum hal_bool ath9k_hw_settxqueueprops(struct ath_hal *ah, int q,
7480 const struct hal_txq_info *qInfo)
7481 {
7482 struct ath_hal_5416 *ahp = AH5416(ah);
7483 struct hal_capabilities *pCap = &ah->ah_caps;
7484
7485 if (q >= pCap->halTotalQueues) {
7486 HDPRINTF(ah, HAL_DBG_QUEUE, "%s: invalid queue num %u\n",
7487 __func__, q);
7488 return AH_FALSE;
7489 }
7490 return ath9k_hw_set_txq_props(ah, &ahp->ah_txq[q], qInfo);
7491 }
7492
7493 static enum hal_bool ath9k_hw_get_txq_props(struct ath_hal *ah,
7494 struct hal_txq_info *qInfo,
7495 const struct hal_tx_queue_info *qi)
7496 {
7497 if (qi->tqi_type == HAL_TX_QUEUE_INACTIVE) {
7498 HDPRINTF(ah, HAL_DBG_QUEUE, "%s: inactive queue\n",
7499 __func__);
7500 return AH_FALSE;
7501 }
7502
7503 qInfo->tqi_qflags = qi->tqi_qflags;
7504 qInfo->tqi_ver = qi->tqi_ver;
7505 qInfo->tqi_subtype = qi->tqi_subtype;
7506 qInfo->tqi_qflags = qi->tqi_qflags;
7507 qInfo->tqi_priority = qi->tqi_priority;
7508 qInfo->tqi_aifs = qi->tqi_aifs;
7509 qInfo->tqi_cwmin = qi->tqi_cwmin;
7510 qInfo->tqi_cwmax = qi->tqi_cwmax;
7511 qInfo->tqi_shretry = qi->tqi_shretry;
7512 qInfo->tqi_lgretry = qi->tqi_lgretry;
7513 qInfo->tqi_cbrPeriod = qi->tqi_cbrPeriod;
7514 qInfo->tqi_cbrOverflowLimit = qi->tqi_cbrOverflowLimit;
7515 qInfo->tqi_burstTime = qi->tqi_burstTime;
7516 qInfo->tqi_readyTime = qi->tqi_readyTime;
7517
7518 return AH_TRUE;
7519 }
7520
7521 enum hal_bool
7522 ath9k_hw_gettxqueueprops(struct ath_hal *ah, int q,
7523 struct hal_txq_info *qInfo)
7524 {
7525 struct ath_hal_5416 *ahp = AH5416(ah);
7526 struct hal_capabilities *pCap = &ah->ah_caps;
7527
7528 if (q >= pCap->halTotalQueues) {
7529 HDPRINTF(ah, HAL_DBG_QUEUE, "%s: invalid queue num %u\n",
7530 __func__, q);
7531 return AH_FALSE;
7532 }
7533 return ath9k_hw_get_txq_props(ah, qInfo, &ahp->ah_txq[q]);
7534 }
7535
7536 int
7537 ath9k_hw_setuptxqueue(struct ath_hal *ah, enum hal_tx_queue type,
7538 const struct hal_txq_info *qInfo)
7539 {
7540 struct ath_hal_5416 *ahp = AH5416(ah);
7541 struct hal_tx_queue_info *qi;
7542 struct hal_capabilities *pCap = &ah->ah_caps;
7543 int q;
7544
7545 switch (type) {
7546 case HAL_TX_QUEUE_BEACON:
7547 q = pCap->halTotalQueues - 1;
7548 break;
7549 case HAL_TX_QUEUE_CAB:
7550 q = pCap->halTotalQueues - 2;
7551 break;
7552 case HAL_TX_QUEUE_PSPOLL:
7553 q = 1;
7554 break;
7555 case HAL_TX_QUEUE_UAPSD:
7556 q = pCap->halTotalQueues - 3;
7557 break;
7558 case HAL_TX_QUEUE_DATA:
7559 for (q = 0; q < pCap->halTotalQueues; q++)
7560 if (ahp->ah_txq[q].tqi_type ==
7561 HAL_TX_QUEUE_INACTIVE)
7562 break;
7563 if (q == pCap->halTotalQueues) {
7564 HDPRINTF(ah, HAL_DBG_QUEUE,
7565 "%s: no available tx queue\n", __func__);
7566 return -1;
7567 }
7568 break;
7569 default:
7570 HDPRINTF(ah, HAL_DBG_QUEUE, "%s: bad tx queue type %u\n",
7571 __func__, type);
7572 return -1;
7573 }
7574
7575 HDPRINTF(ah, HAL_DBG_QUEUE, "%s: queue %u\n", __func__, q);
7576
7577 qi = &ahp->ah_txq[q];
7578 if (qi->tqi_type != HAL_TX_QUEUE_INACTIVE) {
7579 HDPRINTF(ah, HAL_DBG_QUEUE,
7580 "%s: tx queue %u already active\n", __func__, q);
7581 return -1;
7582 }
7583 memset(qi, 0, sizeof(struct hal_tx_queue_info));
7584 qi->tqi_type = type;
7585 if (qInfo == NULL) {
7586 qi->tqi_qflags =
7587 TXQ_FLAG_TXOKINT_ENABLE
7588 | TXQ_FLAG_TXERRINT_ENABLE
7589 | TXQ_FLAG_TXDESCINT_ENABLE | TXQ_FLAG_TXURNINT_ENABLE;
7590 qi->tqi_aifs = INIT_AIFS;
7591 qi->tqi_cwmin = HAL_TXQ_USEDEFAULT;
7592 qi->tqi_cwmax = INIT_CWMAX;
7593 qi->tqi_shretry = INIT_SH_RETRY;
7594 qi->tqi_lgretry = INIT_LG_RETRY;
7595 qi->tqi_physCompBuf = 0;
7596 } else {
7597 qi->tqi_physCompBuf = qInfo->tqi_compBuf;
7598 (void) ath9k_hw_settxqueueprops(ah, q, qInfo);
7599 }
7600
7601 return q;
7602 }
7603
7604 static void
7605 ath9k_hw_set_txq_interrupts(struct ath_hal *ah,
7606 struct hal_tx_queue_info *qi)
7607 {
7608 struct ath_hal_5416 *ahp = AH5416(ah);
7609
7610 HDPRINTF(ah, HAL_DBG_INTERRUPT,
7611 "%s: tx ok 0x%x err 0x%x desc 0x%x eol 0x%x urn 0x%x\n",
7612 __func__, ahp->ah_txOkInterruptMask,
7613 ahp->ah_txErrInterruptMask, ahp->ah_txDescInterruptMask,
7614 ahp->ah_txEolInterruptMask, ahp->ah_txUrnInterruptMask);
7615
7616 REG_WRITE(ah, AR_IMR_S0,
7617 SM(ahp->ah_txOkInterruptMask, AR_IMR_S0_QCU_TXOK)
7618 | SM(ahp->ah_txDescInterruptMask, AR_IMR_S0_QCU_TXDESC)
7619 );
7620 REG_WRITE(ah, AR_IMR_S1,
7621 SM(ahp->ah_txErrInterruptMask, AR_IMR_S1_QCU_TXERR)
7622 | SM(ahp->ah_txEolInterruptMask, AR_IMR_S1_QCU_TXEOL)
7623 );
7624 OS_REG_RMW_FIELD(ah, AR_IMR_S2,
7625 AR_IMR_S2_QCU_TXURN, ahp->ah_txUrnInterruptMask);
7626 }
7627
7628 enum hal_bool ath9k_hw_releasetxqueue(struct ath_hal *ah, u_int q)
7629 {
7630 struct ath_hal_5416 *ahp = AH5416(ah);
7631 struct hal_capabilities *pCap = &ah->ah_caps;
7632 struct hal_tx_queue_info *qi;
7633
7634 if (q >= pCap->halTotalQueues) {
7635 HDPRINTF(ah, HAL_DBG_QUEUE, "%s: invalid queue num %u\n",
7636 __func__, q);
7637 return AH_FALSE;
7638 }
7639 qi = &ahp->ah_txq[q];
7640 if (qi->tqi_type == HAL_TX_QUEUE_INACTIVE) {
7641 HDPRINTF(ah, HAL_DBG_QUEUE, "%s: inactive queue %u\n",
7642 __func__, q);
7643 return AH_FALSE;
7644 }
7645
7646 HDPRINTF(ah, HAL_DBG_QUEUE, "%s: release queue %u\n", __func__, q);
7647
7648 qi->tqi_type = HAL_TX_QUEUE_INACTIVE;
7649 ahp->ah_txOkInterruptMask &= ~(1 << q);
7650 ahp->ah_txErrInterruptMask &= ~(1 << q);
7651 ahp->ah_txDescInterruptMask &= ~(1 << q);
7652 ahp->ah_txEolInterruptMask &= ~(1 << q);
7653 ahp->ah_txUrnInterruptMask &= ~(1 << q);
7654 ath9k_hw_set_txq_interrupts(ah, qi);
7655
7656 return AH_TRUE;
7657 }
7658
7659 enum hal_bool ath9k_hw_resettxqueue(struct ath_hal *ah, u_int q)
7660 {
7661 struct ath_hal_5416 *ahp = AH5416(ah);
7662 struct hal_capabilities *pCap = &ah->ah_caps;
7663 struct hal_channel_internal *chan = ah->ah_curchan;
7664 struct hal_tx_queue_info *qi;
7665 u_int32_t cwMin, chanCwMin, value;
7666
7667 if (q >= pCap->halTotalQueues) {
7668 HDPRINTF(ah, HAL_DBG_QUEUE, "%s: invalid queue num %u\n",
7669 __func__, q);
7670 return AH_FALSE;
7671 }
7672 qi = &ahp->ah_txq[q];
7673 if (qi->tqi_type == HAL_TX_QUEUE_INACTIVE) {
7674 HDPRINTF(ah, HAL_DBG_QUEUE, "%s: inactive queue %u\n",
7675 __func__, q);
7676 return AH_TRUE;
7677 }
7678
7679 HDPRINTF(ah, HAL_DBG_QUEUE, "%s: reset queue %u\n", __func__, q);
7680
7681 if (qi->tqi_cwmin == HAL_TXQ_USEDEFAULT) {
7682 if (chan && IS_CHAN_B(chan))
7683 chanCwMin = INIT_CWMIN_11B;
7684 else
7685 chanCwMin = INIT_CWMIN;
7686
7687 for (cwMin = 1; cwMin < chanCwMin;
7688 cwMin = (cwMin << 1) | 1);
7689 } else
7690 cwMin = qi->tqi_cwmin;
7691
7692 REG_WRITE(ah, AR_DLCL_IFS(q), SM(cwMin, AR_D_LCL_IFS_CWMIN)
7693 | SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX)
7694 | SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS));
7695
7696 REG_WRITE(ah, AR_DRETRY_LIMIT(q),
7697 SM(INIT_SSH_RETRY, AR_D_RETRY_LIMIT_STA_SH)
7698 | SM(INIT_SLG_RETRY, AR_D_RETRY_LIMIT_STA_LG)
7699 | SM(qi->tqi_shretry, AR_D_RETRY_LIMIT_FR_SH)
7700 );
7701
7702 REG_WRITE(ah, AR_QMISC(q), AR_Q_MISC_DCU_EARLY_TERM_REQ);
7703 REG_WRITE(ah, AR_DMISC(q),
7704 AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x2);
7705
7706 if (qi->tqi_cbrPeriod) {
7707 REG_WRITE(ah, AR_QCBRCFG(q),
7708 SM(qi->tqi_cbrPeriod, AR_Q_CBRCFG_INTERVAL)
7709 | SM(qi->tqi_cbrOverflowLimit,
7710 AR_Q_CBRCFG_OVF_THRESH));
7711 REG_WRITE(ah, AR_QMISC(q),
7712 REG_READ(ah,
7713 AR_QMISC(q)) | AR_Q_MISC_FSP_CBR | (qi->
7714 tqi_cbrOverflowLimit
7715 ?
7716 AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN
7717 :
7718 0));
7719 }
7720 if (qi->tqi_readyTime && (qi->tqi_type != HAL_TX_QUEUE_CAB)) {
7721 REG_WRITE(ah, AR_QRDYTIMECFG(q),
7722 SM(qi->tqi_readyTime, AR_Q_RDYTIMECFG_DURATION) |
7723 AR_Q_RDYTIMECFG_EN);
7724 }
7725
7726 REG_WRITE(ah, AR_DCHNTIME(q),
7727 SM(qi->tqi_burstTime, AR_D_CHNTIME_DUR) |
7728 (qi->tqi_burstTime ? AR_D_CHNTIME_EN : 0));
7729
7730 if (qi->tqi_burstTime
7731 && (qi->tqi_qflags & TXQ_FLAG_RDYTIME_EXP_POLICY_ENABLE)) {
7732 REG_WRITE(ah, AR_QMISC(q),
7733 REG_READ(ah,
7734 AR_QMISC(q)) |
7735 AR_Q_MISC_RDYTIME_EXP_POLICY);
7736
7737 }
7738
7739 if (qi->tqi_qflags & TXQ_FLAG_BACKOFF_DISABLE) {
7740 REG_WRITE(ah, AR_DMISC(q),
7741 REG_READ(ah, AR_DMISC(q)) |
7742 AR_D_MISC_POST_FR_BKOFF_DIS);
7743 }
7744 if (qi->tqi_qflags & TXQ_FLAG_FRAG_BURST_BACKOFF_ENABLE) {
7745 REG_WRITE(ah, AR_DMISC(q),
7746 REG_READ(ah, AR_DMISC(q)) |
7747 AR_D_MISC_FRAG_BKOFF_EN);
7748 }
7749 switch (qi->tqi_type) {
7750 case HAL_TX_QUEUE_BEACON:
7751 REG_WRITE(ah, AR_QMISC(q), REG_READ(ah, AR_QMISC(q))
7752 | AR_Q_MISC_FSP_DBA_GATED
7753 | AR_Q_MISC_BEACON_USE
7754 | AR_Q_MISC_CBR_INCR_DIS1);
7755
7756 REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q))
7757 | (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
7758 AR_D_MISC_ARB_LOCKOUT_CNTRL_S)
7759 | AR_D_MISC_BEACON_USE
7760 | AR_D_MISC_POST_FR_BKOFF_DIS);
7761 break;
7762 case HAL_TX_QUEUE_CAB:
7763 REG_WRITE(ah, AR_QMISC(q), REG_READ(ah, AR_QMISC(q))
7764 | AR_Q_MISC_FSP_DBA_GATED
7765 | AR_Q_MISC_CBR_INCR_DIS1
7766 | AR_Q_MISC_CBR_INCR_DIS0);
7767 value = (qi->tqi_readyTime
7768 - (ah->ah_config.ath_hal_sw_beacon_response_time -
7769 ah->ah_config.ath_hal_dma_beacon_response_time)
7770 -
7771 ah->ah_config.ath_hal_additional_swba_backoff) *
7772 1024;
7773 REG_WRITE(ah, AR_QRDYTIMECFG(q),
7774 value | AR_Q_RDYTIMECFG_EN);
7775 REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q))
7776 | (AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL <<
7777 AR_D_MISC_ARB_LOCKOUT_CNTRL_S));
7778 break;
7779 case HAL_TX_QUEUE_PSPOLL:
7780 REG_WRITE(ah, AR_QMISC(q),
7781 REG_READ(ah,
7782 AR_QMISC(q)) | AR_Q_MISC_CBR_INCR_DIS1);
7783 break;
7784 case HAL_TX_QUEUE_UAPSD:
7785 REG_WRITE(ah, AR_DMISC(q), REG_READ(ah, AR_DMISC(q))
7786 | AR_D_MISC_POST_FR_BKOFF_DIS);
7787 break;
7788 default:
7789 break;
7790 }
7791
7792 if (qi->tqi_intFlags & HAL_TXQ_USE_LOCKOUT_BKOFF_DIS) {
7793 REG_WRITE(ah, AR_DMISC(q),
7794 REG_READ(ah, AR_DMISC(q)) |
7795 SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL,
7796 AR_D_MISC_ARB_LOCKOUT_CNTRL) |
7797 AR_D_MISC_POST_FR_BKOFF_DIS);
7798 }
7799
7800 if (qi->tqi_qflags & TXQ_FLAG_TXOKINT_ENABLE)
7801 ahp->ah_txOkInterruptMask |= 1 << q;
7802 else
7803 ahp->ah_txOkInterruptMask &= ~(1 << q);
7804 if (qi->tqi_qflags & TXQ_FLAG_TXERRINT_ENABLE)
7805 ahp->ah_txErrInterruptMask |= 1 << q;
7806 else
7807 ahp->ah_txErrInterruptMask &= ~(1 << q);
7808 if (qi->tqi_qflags & TXQ_FLAG_TXDESCINT_ENABLE)
7809 ahp->ah_txDescInterruptMask |= 1 << q;
7810 else
7811 ahp->ah_txDescInterruptMask &= ~(1 << q);
7812 if (qi->tqi_qflags & TXQ_FLAG_TXEOLINT_ENABLE)
7813 ahp->ah_txEolInterruptMask |= 1 << q;
7814 else
7815 ahp->ah_txEolInterruptMask &= ~(1 << q);
7816 if (qi->tqi_qflags & TXQ_FLAG_TXURNINT_ENABLE)
7817 ahp->ah_txUrnInterruptMask |= 1 << q;
7818 else
7819 ahp->ah_txUrnInterruptMask &= ~(1 << q);
7820 ath9k_hw_set_txq_interrupts(ah, qi);
7821
7822 return AH_TRUE;
7823 }
7824
7825 void ath9k_hw_gettxintrtxqs(struct ath_hal *ah, u_int32_t *txqs)
7826 {
7827 struct ath_hal_5416 *ahp = AH5416(ah);
7828 *txqs &= ahp->ah_intrTxqs;
7829 ahp->ah_intrTxqs &= ~(*txqs);
7830 }
7831
7832 enum hal_bool
7833 ath9k_hw_setupxtxdesc(struct ath_hal *ah, struct ath_desc *ds,
7834 u_int txRate1, u_int txTries1,
7835 u_int txRate2, u_int txTries2,
7836 u_int txRate3, u_int txTries3)
7837 {
7838 struct ar5416_desc *ads = AR5416DESC(ds);
7839
7840 if (txTries1) {
7841 ads->ds_ctl2 |= AR_DurUpdateEna;
7842 ads->ds_ctl2 |= SM(txTries1, AR_XmitDataTries1);
7843 ads->ds_ctl3 |= (txRate1 << AR_XmitRate1_S);
7844 }
7845 if (txTries2) {
7846 ads->ds_ctl2 |= SM(txTries2, AR_XmitDataTries2);
7847 ads->ds_ctl3 |= (txRate2 << AR_XmitRate2_S);
7848 }
7849 if (txTries3) {
7850 ads->ds_ctl2 |= SM(txTries3, AR_XmitDataTries3);
7851 ads->ds_ctl3 |= (txRate3 << AR_XmitRate3_S);
7852 }
7853 return AH_TRUE;
7854 }
7855
7856 enum hal_bool
7857 ath9k_hw_filltxdesc(struct ath_hal *ah, struct ath_desc *ds,
7858 u_int segLen, enum hal_bool firstSeg,
7859 enum hal_bool lastSeg, const struct ath_desc *ds0)
7860 {
7861 struct ar5416_desc *ads = AR5416DESC(ds);
7862
7863 if (firstSeg) {
7864 ads->ds_ctl1 |= segLen | (lastSeg ? 0 : AR_TxMore);
7865 } else if (lastSeg) {
7866 ads->ds_ctl0 = 0;
7867 ads->ds_ctl1 = segLen;
7868 ads->ds_ctl2 = AR5416DESC_CONST(ds0)->ds_ctl2;
7869 ads->ds_ctl3 = AR5416DESC_CONST(ds0)->ds_ctl3;
7870 } else {
7871 ads->ds_ctl0 = 0;
7872 ads->ds_ctl1 = segLen | AR_TxMore;
7873 ads->ds_ctl2 = 0;
7874 ads->ds_ctl3 = 0;
7875 }
7876 ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
7877 ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
7878 ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
7879 ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
7880 ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
7881 return AH_TRUE;
7882 }
7883
7884 void ath9k_hw_cleartxdesc(struct ath_hal *ah, struct ath_desc *ds)
7885 {
7886 struct ar5416_desc *ads = AR5416DESC(ds);
7887
7888 ads->ds_txstatus0 = ads->ds_txstatus1 = 0;
7889 ads->ds_txstatus2 = ads->ds_txstatus3 = 0;
7890 ads->ds_txstatus4 = ads->ds_txstatus5 = 0;
7891 ads->ds_txstatus6 = ads->ds_txstatus7 = 0;
7892 ads->ds_txstatus8 = ads->ds_txstatus9 = 0;
7893 }
7894
7895 enum hal_status
7896 ath9k_hw_txprocdesc(struct ath_hal *ah, struct ath_desc *ds)
7897 {
7898 struct ar5416_desc *ads = AR5416DESC(ds);
7899
7900 if ((ads->ds_txstatus9 & AR_TxDone) == 0)
7901 return HAL_EINPROGRESS;
7902
7903 ds->ds_txstat.ts_seqnum = MS(ads->ds_txstatus9, AR_SeqNum);
7904 ds->ds_txstat.ts_tstamp = ads->AR_SendTimestamp;
7905 ds->ds_txstat.ts_status = 0;
7906 ds->ds_txstat.ts_flags = 0;
7907
7908 if (ads->ds_txstatus1 & AR_ExcessiveRetries)
7909 ds->ds_txstat.ts_status |= HAL_TXERR_XRETRY;
7910 if (ads->ds_txstatus1 & AR_Filtered)
7911 ds->ds_txstat.ts_status |= HAL_TXERR_FILT;
7912 if (ads->ds_txstatus1 & AR_FIFOUnderrun)
7913 ds->ds_txstat.ts_status |= HAL_TXERR_FIFO;
7914 if (ads->ds_txstatus9 & AR_TxOpExceeded)
7915 ds->ds_txstat.ts_status |= HAL_TXERR_XTXOP;
7916 if (ads->ds_txstatus1 & AR_TxTimerExpired)
7917 ds->ds_txstat.ts_status |= HAL_TXERR_TIMER_EXPIRED;
7918
7919 if (ads->ds_txstatus1 & AR_DescCfgErr)
7920 ds->ds_txstat.ts_flags |= HAL_TX_DESC_CFG_ERR;
7921 if (ads->ds_txstatus1 & AR_TxDataUnderrun) {
7922 ds->ds_txstat.ts_flags |= HAL_TX_DATA_UNDERRUN;
7923 ath9k_hw_updatetxtriglevel(ah, AH_TRUE);
7924 }
7925 if (ads->ds_txstatus1 & AR_TxDelimUnderrun) {
7926 ds->ds_txstat.ts_flags |= HAL_TX_DELIM_UNDERRUN;
7927 ath9k_hw_updatetxtriglevel(ah, AH_TRUE);
7928 }
7929 if (ads->ds_txstatus0 & AR_TxBaStatus) {
7930 ds->ds_txstat.ts_flags |= HAL_TX_BA;
7931 ds->ds_txstat.ba_low = ads->AR_BaBitmapLow;
7932 ds->ds_txstat.ba_high = ads->AR_BaBitmapHigh;
7933 }
7934
7935 ds->ds_txstat.ts_rateindex = MS(ads->ds_txstatus9, AR_FinalTxIdx);
7936 switch (ds->ds_txstat.ts_rateindex) {
7937 case 0:
7938 ds->ds_txstat.ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate0);
7939 break;
7940 case 1:
7941 ds->ds_txstat.ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate1);
7942 break;
7943 case 2:
7944 ds->ds_txstat.ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate2);
7945 break;
7946 case 3:
7947 ds->ds_txstat.ts_ratecode = MS(ads->ds_ctl3, AR_XmitRate3);
7948 break;
7949 }
7950
7951 ds->ds_txstat.ts_rssi = MS(ads->ds_txstatus5, AR_TxRSSICombined);
7952 ds->ds_txstat.ts_rssi_ctl0 = MS(ads->ds_txstatus0, AR_TxRSSIAnt00);
7953 ds->ds_txstat.ts_rssi_ctl1 = MS(ads->ds_txstatus0, AR_TxRSSIAnt01);
7954 ds->ds_txstat.ts_rssi_ctl2 = MS(ads->ds_txstatus0, AR_TxRSSIAnt02);
7955 ds->ds_txstat.ts_rssi_ext0 = MS(ads->ds_txstatus5, AR_TxRSSIAnt10);
7956 ds->ds_txstat.ts_rssi_ext1 = MS(ads->ds_txstatus5, AR_TxRSSIAnt11);
7957 ds->ds_txstat.ts_rssi_ext2 = MS(ads->ds_txstatus5, AR_TxRSSIAnt12);
7958 ds->ds_txstat.evm0 = ads->AR_TxEVM0;
7959 ds->ds_txstat.evm1 = ads->AR_TxEVM1;
7960 ds->ds_txstat.evm2 = ads->AR_TxEVM2;
7961 ds->ds_txstat.ts_shortretry = MS(ads->ds_txstatus1, AR_RTSFailCnt);
7962 ds->ds_txstat.ts_longretry = MS(ads->ds_txstatus1, AR_DataFailCnt);
7963 ds->ds_txstat.ts_virtcol = MS(ads->ds_txstatus1, AR_VirtRetryCnt);
7964 ds->ds_txstat.ts_antenna = 1;
7965
7966 return HAL_OK;
7967 }
7968
7969 void
7970 ath9k_hw_set11n_txdesc(struct ath_hal *ah, struct ath_desc *ds,
7971 u_int pktLen, enum hal_pkt_type type, u_int txPower,
7972 u_int keyIx, enum hal_key_type keyType, u_int flags)
7973 {
7974 struct ar5416_desc *ads = AR5416DESC(ds);
7975 struct ath_hal_5416 *ahp = AH5416(ah);
7976
7977 txPower += ahp->ah_txPowerIndexOffset;
7978 if (txPower > 63)
7979 txPower = 63;
7980
7981 ads->ds_ctl0 = (pktLen & AR_FrameLen)
7982 | (flags & HAL_TXDESC_VMF ? AR_VirtMoreFrag : 0)
7983 | SM(txPower, AR_XmitPower)
7984 | (flags & HAL_TXDESC_VEOL ? AR_VEOL : 0)
7985 | (flags & HAL_TXDESC_CLRDMASK ? AR_ClrDestMask : 0)
7986 | (flags & HAL_TXDESC_INTREQ ? AR_TxIntrReq : 0)
7987 | (keyIx != HAL_TXKEYIX_INVALID ? AR_DestIdxValid : 0);
7988
7989 ads->ds_ctl1 =
7990 (keyIx != HAL_TXKEYIX_INVALID ? SM(keyIx, AR_DestIdx) : 0)
7991 | SM(type, AR_FrameType)
7992 | (flags & HAL_TXDESC_NOACK ? AR_NoAck : 0)
7993 | (flags & HAL_TXDESC_EXT_ONLY ? AR_ExtOnly : 0)
7994 | (flags & HAL_TXDESC_EXT_AND_CTL ? AR_ExtAndCtl : 0);
7995
7996 ads->ds_ctl6 = SM(keyType, AR_EncrType);
7997
7998 if (AR_SREV_9285(ah)) {
7999
8000 ads->ds_ctl8 = 0;
8001 ads->ds_ctl9 = 0;
8002 ads->ds_ctl10 = 0;
8003 ads->ds_ctl11 = 0;
8004 }
8005 }
8006
8007 void
8008 ath9k_hw_set11n_ratescenario(struct ath_hal *ah, struct ath_desc *ds,
8009 struct ath_desc *lastds,
8010 u_int durUpdateEn, u_int rtsctsRate,
8011 u_int rtsctsDuration,
8012 struct hal_11n_rate_series series[],
8013 u_int nseries, u_int flags)
8014 {
8015 struct ar5416_desc *ads = AR5416DESC(ds);
8016 struct ar5416_desc *last_ads = AR5416DESC(lastds);
8017 u_int32_t ds_ctl0;
8018
8019 (void) nseries;
8020 (void) rtsctsDuration;
8021
8022 if (flags & (HAL_TXDESC_RTSENA | HAL_TXDESC_CTSENA)) {
8023 ds_ctl0 = ads->ds_ctl0;
8024
8025 if (flags & HAL_TXDESC_RTSENA) {
8026 ds_ctl0 &= ~AR_CTSEnable;
8027 ds_ctl0 |= AR_RTSEnable;
8028 } else {
8029 ds_ctl0 &= ~AR_RTSEnable;
8030 ds_ctl0 |= AR_CTSEnable;
8031 }
8032
8033 ads->ds_ctl0 = ds_ctl0;
8034 } else {
8035 ads->ds_ctl0 =
8036 (ads->ds_ctl0 & ~(AR_RTSEnable | AR_CTSEnable));
8037 }
8038
8039 ads->ds_ctl2 = set11nTries(series, 0)
8040 | set11nTries(series, 1)
8041 | set11nTries(series, 2)
8042 | set11nTries(series, 3)
8043 | (durUpdateEn ? AR_DurUpdateEna : 0)
8044 | SM(0, AR_BurstDur);
8045
8046 ads->ds_ctl3 = set11nRate(series, 0)
8047 | set11nRate(series, 1)
8048 | set11nRate(series, 2)
8049 | set11nRate(series, 3);
8050
8051 ads->ds_ctl4 = set11nPktDurRTSCTS(series, 0)
8052 | set11nPktDurRTSCTS(series, 1);
8053
8054 ads->ds_ctl5 = set11nPktDurRTSCTS(series, 2)
8055 | set11nPktDurRTSCTS(series, 3);
8056
8057 ads->ds_ctl7 = set11nRateFlags(series, 0)
8058 | set11nRateFlags(series, 1)
8059 | set11nRateFlags(series, 2)
8060 | set11nRateFlags(series, 3)
8061 | SM(rtsctsRate, AR_RTSCTSRate);
8062 last_ads->ds_ctl2 = ads->ds_ctl2;
8063 last_ads->ds_ctl3 = ads->ds_ctl3;
8064 }
8065
8066 void
8067 ath9k_hw_set11n_aggr_first(struct ath_hal *ah, struct ath_desc *ds,
8068 u_int aggrLen)
8069 {
8070 struct ar5416_desc *ads = AR5416DESC(ds);
8071
8072 ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
8073
8074 ads->ds_ctl6 &= ~AR_AggrLen;
8075 ads->ds_ctl6 |= SM(aggrLen, AR_AggrLen);
8076 }
8077
8078 void
8079 ath9k_hw_set11n_aggr_middle(struct ath_hal *ah, struct ath_desc *ds,
8080 u_int numDelims)
8081 {
8082 struct ar5416_desc *ads = AR5416DESC(ds);
8083 unsigned int ctl6;
8084
8085 ads->ds_ctl1 |= (AR_IsAggr | AR_MoreAggr);
8086
8087 ctl6 = ads->ds_ctl6;
8088 ctl6 &= ~AR_PadDelim;
8089 ctl6 |= SM(numDelims, AR_PadDelim);
8090 ads->ds_ctl6 = ctl6;
8091 }
8092
8093 void ath9k_hw_set11n_aggr_last(struct ath_hal *ah, struct ath_desc *ds)
8094 {
8095 struct ar5416_desc *ads = AR5416DESC(ds);
8096
8097 ads->ds_ctl1 |= AR_IsAggr;
8098 ads->ds_ctl1 &= ~AR_MoreAggr;
8099 ads->ds_ctl6 &= ~AR_PadDelim;
8100 }
8101
8102 void ath9k_hw_clr11n_aggr(struct ath_hal *ah, struct ath_desc *ds)
8103 {
8104 struct ar5416_desc *ads = AR5416DESC(ds);
8105
8106 ads->ds_ctl1 &= (~AR_IsAggr & ~AR_MoreAggr);
8107 }
8108
8109 void
8110 ath9k_hw_set11n_burstduration(struct ath_hal *ah, struct ath_desc *ds,
8111 u_int burstDuration)
8112 {
8113 struct ar5416_desc *ads = AR5416DESC(ds);
8114
8115 ads->ds_ctl2 &= ~AR_BurstDur;
8116 ads->ds_ctl2 |= SM(burstDuration, AR_BurstDur);
8117 }
8118
8119 void
8120 ath9k_hw_set11n_virtualmorefrag(struct ath_hal *ah, struct ath_desc *ds,
8121 u_int vmf)
8122 {
8123 struct ar5416_desc *ads = AR5416DESC(ds);
8124
8125 if (vmf)
8126 ads->ds_ctl0 |= AR_VirtMoreFrag;
8127 else
8128 ads->ds_ctl0 &= ~AR_VirtMoreFrag;
8129 }
8130
8131 void ath9k_hw_putrxbuf(struct ath_hal *ah, u_int32_t rxdp)
8132 {
8133 REG_WRITE(ah, AR_RXDP, rxdp);
8134 }
8135
8136 void ath9k_hw_rxena(struct ath_hal *ah)
8137 {
8138 REG_WRITE(ah, AR_CR, AR_CR_RXE);
8139 }
8140
8141 enum hal_bool ath9k_hw_setrxabort(struct ath_hal *ah, enum hal_bool set)
8142 {
8143 if (set) {
8144
8145 OS_REG_SET_BIT(ah, AR_DIAG_SW,
8146 (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
8147
8148 if (!ath9k_hw_wait
8149 (ah, AR_OBS_BUS_1, AR_OBS_BUS_1_RX_STATE, 0)) {
8150 u_int32_t reg;
8151
8152 OS_REG_CLR_BIT(ah, AR_DIAG_SW,
8153 (AR_DIAG_RX_DIS |
8154 AR_DIAG_RX_ABORT));
8155
8156 reg = REG_READ(ah, AR_OBS_BUS_1);
8157 HDPRINTF(ah, HAL_DBG_RX,
8158 "%s: rx failed to go idle in 10 ms RXSM=0x%x\n",
8159 __func__, reg);
8160
8161 return AH_FALSE;
8162 }
8163 } else {
8164 OS_REG_CLR_BIT(ah, AR_DIAG_SW,
8165 (AR_DIAG_RX_DIS | AR_DIAG_RX_ABORT));
8166 }
8167
8168 return AH_TRUE;
8169 }
8170
8171 void
8172 ath9k_hw_setmcastfilter(struct ath_hal *ah, u_int32_t filter0,
8173 u_int32_t filter1)
8174 {
8175 REG_WRITE(ah, AR_MCAST_FIL0, filter0);
8176 REG_WRITE(ah, AR_MCAST_FIL1, filter1);
8177 }
8178
8179 enum hal_bool
8180 ath9k_hw_setuprxdesc(struct ath_hal *ah, struct ath_desc *ds,
8181 u_int32_t size, u_int flags)
8182 {
8183 struct ar5416_desc *ads = AR5416DESC(ds);
8184 struct hal_capabilities *pCap = &ah->ah_caps;
8185
8186 ads->ds_ctl1 = size & AR_BufLen;
8187 if (flags & HAL_RXDESC_INTREQ)
8188 ads->ds_ctl1 |= AR_RxIntrReq;
8189
8190 ads->ds_rxstatus8 &= ~AR_RxDone;
8191 if (!pCap->halAutoSleepSupport)
8192 memset(&(ads->u), 0, sizeof(ads->u));
8193 return AH_TRUE;
8194 }
8195
8196 enum hal_status
8197 ath9k_hw_rxprocdesc(struct ath_hal *ah, struct ath_desc *ds,
8198 u_int32_t pa, struct ath_desc *nds, u_int64_t tsf)
8199 {
8200 struct ar5416_desc ads;
8201 struct ar5416_desc *adsp = AR5416DESC(ds);
8202
8203 if ((adsp->ds_rxstatus8 & AR_RxDone) == 0)
8204 return HAL_EINPROGRESS;
8205
8206 ads.u.rx = adsp->u.rx;
8207
8208 ds->ds_rxstat.rs_status = 0;
8209 ds->ds_rxstat.rs_flags = 0;
8210
8211 ds->ds_rxstat.rs_datalen = ads.ds_rxstatus1 & AR_DataLen;
8212 ds->ds_rxstat.rs_tstamp = ads.AR_RcvTimestamp;
8213
8214 ds->ds_rxstat.rs_rssi = MS(ads.ds_rxstatus4, AR_RxRSSICombined);
8215 ds->ds_rxstat.rs_rssi_ctl0 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt00);
8216 ds->ds_rxstat.rs_rssi_ctl1 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt01);
8217 ds->ds_rxstat.rs_rssi_ctl2 = MS(ads.ds_rxstatus0, AR_RxRSSIAnt02);
8218 ds->ds_rxstat.rs_rssi_ext0 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt10);
8219 ds->ds_rxstat.rs_rssi_ext1 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt11);
8220 ds->ds_rxstat.rs_rssi_ext2 = MS(ads.ds_rxstatus4, AR_RxRSSIAnt12);
8221 if (ads.ds_rxstatus8 & AR_RxKeyIdxValid)
8222 ds->ds_rxstat.rs_keyix = MS(ads.ds_rxstatus8, AR_KeyIdx);
8223 else
8224 ds->ds_rxstat.rs_keyix = HAL_RXKEYIX_INVALID;
8225
8226 ds->ds_rxstat.rs_rate = RXSTATUS_RATE(ah, (&ads));
8227 ds->ds_rxstat.rs_more = (ads.ds_rxstatus1 & AR_RxMore) ? 1 : 0;
8228
8229 ds->ds_rxstat.rs_isaggr = (ads.ds_rxstatus8 & AR_RxAggr) ? 1 : 0;
8230 ds->ds_rxstat.rs_moreaggr =
8231 (ads.ds_rxstatus8 & AR_RxMoreAggr) ? 1 : 0;
8232 ds->ds_rxstat.rs_antenna = MS(ads.ds_rxstatus3, AR_RxAntenna);
8233 ds->ds_rxstat.rs_flags =
8234 (ads.ds_rxstatus3 & AR_GI) ? HAL_RX_GI : 0;
8235 ds->ds_rxstat.rs_flags |=
8236 (ads.ds_rxstatus3 & AR_2040) ? HAL_RX_2040 : 0;
8237
8238 if (ads.ds_rxstatus8 & AR_PreDelimCRCErr)
8239 ds->ds_rxstat.rs_flags |= HAL_RX_DELIM_CRC_PRE;
8240 if (ads.ds_rxstatus8 & AR_PostDelimCRCErr)
8241 ds->ds_rxstat.rs_flags |= HAL_RX_DELIM_CRC_POST;
8242 if (ads.ds_rxstatus8 & AR_DecryptBusyErr)
8243 ds->ds_rxstat.rs_flags |= HAL_RX_DECRYPT_BUSY;
8244
8245 if ((ads.ds_rxstatus8 & AR_RxFrameOK) == 0) {
8246
8247 if (ads.ds_rxstatus8 & AR_CRCErr)
8248 ds->ds_rxstat.rs_status |= HAL_RXERR_CRC;
8249 else if (ads.ds_rxstatus8 & AR_PHYErr) {
8250 u_int phyerr;
8251
8252 ds->ds_rxstat.rs_status |= HAL_RXERR_PHY;
8253 phyerr = MS(ads.ds_rxstatus8, AR_PHYErrCode);
8254 ds->ds_rxstat.rs_phyerr = phyerr;
8255 } else if (ads.ds_rxstatus8 & AR_DecryptCRCErr)
8256 ds->ds_rxstat.rs_status |= HAL_RXERR_DECRYPT;
8257 else if (ads.ds_rxstatus8 & AR_MichaelErr)
8258 ds->ds_rxstat.rs_status |= HAL_RXERR_MIC;
8259 }
8260
8261 return HAL_OK;
8262 }
8263
8264 static void ath9k_hw_setup_rate_table(struct ath_hal *ah,
8265 struct hal_rate_table *rt)
8266 {
8267 int i;
8268
8269 if (rt->rateCodeToIndex[0] != 0)
8270 return;
8271 for (i = 0; i < 256; i++)
8272 rt->rateCodeToIndex[i] = (u_int8_t) -1;
8273 for (i = 0; i < rt->rateCount; i++) {
8274 u_int8_t code = rt->info[i].rateCode;
8275 u_int8_t cix = rt->info[i].controlRate;
8276
8277 rt->rateCodeToIndex[code] = i;
8278 rt->rateCodeToIndex[code | rt->info[i].shortPreamble] = i;
8279
8280 rt->info[i].lpAckDuration =
8281 ath9k_hw_computetxtime(ah, rt,
8282 WLAN_CTRL_FRAME_SIZE,
8283 cix,
8284 AH_FALSE);
8285 rt->info[i].spAckDuration =
8286 ath9k_hw_computetxtime(ah, rt,
8287 WLAN_CTRL_FRAME_SIZE,
8288 cix,
8289 AH_TRUE);
8290 }
8291 }
8292
8293 const struct hal_rate_table *ath9k_hw_getratetable(struct ath_hal *ah,
8294 u_int mode)
8295 {
8296 struct hal_rate_table *rt;
8297 switch (mode) {
8298 case ATH9K_MODE_SEL_11A:
8299 rt = &ar5416_11a_table;
8300 break;
8301 case ATH9K_MODE_SEL_11B:
8302 rt = &ar5416_11b_table;
8303 break;
8304 case ATH9K_MODE_SEL_11G:
8305 rt = &ar5416_11g_table;
8306 break;
8307 case ATH9K_MODE_SEL_11NG_HT20:
8308 case ATH9K_MODE_SEL_11NG_HT40PLUS:
8309 case ATH9K_MODE_SEL_11NG_HT40MINUS:
8310 rt = &ar5416_11ng_table;
8311 break;
8312 case ATH9K_MODE_SEL_11NA_HT20:
8313 case ATH9K_MODE_SEL_11NA_HT40PLUS:
8314 case ATH9K_MODE_SEL_11NA_HT40MINUS:
8315 rt = &ar5416_11na_table;
8316 break;
8317 default:
8318 HDPRINTF(ah, HAL_DBG_CHANNEL, "%s: invalid mode 0x%x\n",
8319 __func__, mode);
8320 return NULL;
8321 }
8322 ath9k_hw_setup_rate_table(ah, rt);
8323 return rt;
8324 }
8325
8326 static const char *ath9k_hw_devname(u_int16_t devid)
8327 {
8328 switch (devid) {
8329 case AR5416_DEVID_PCI:
8330 case AR5416_DEVID_PCIE:
8331 return "Atheros 5416";
8332 case AR9280_DEVID_PCI:
8333 case AR9280_DEVID_PCIE:
8334 return "Atheros 9280";
8335 }
8336 return NULL;
8337 }
8338
8339 const char *ath9k_hw_probe(u_int16_t vendorid, u_int16_t devid)
8340 {
8341 return vendorid == ATHEROS_VENDOR_ID ?
8342 ath9k_hw_devname(devid) : NULL;
8343 }
8344
8345 struct ath_hal *ath9k_hw_attach(u_int16_t devid, void *sc, void __iomem *mem,
8346 enum hal_status *error)
8347 {
8348 struct ath_hal *ah = NULL;
8349
8350 switch (devid) {
8351 case AR5416_DEVID_PCI:
8352 case AR5416_DEVID_PCIE:
8353 case AR9280_DEVID_PCI:
8354 case AR9280_DEVID_PCIE:
8355 ah = ath9k_hw_do_attach(devid, sc, mem, error);
8356 break;
8357 default:
8358 HDPRINTF(ah, HAL_DBG_UNMASKABLE,
8359 "devid=0x%x not supported.\n", devid);
8360 ah = NULL;
8361 *error = HAL_ENXIO;
8362 break;
8363 }
8364 if (ah != NULL) {
8365 ah->ah_devid = ah->ah_devid;
8366 ah->ah_subvendorid = ah->ah_subvendorid;
8367 ah->ah_macVersion = ah->ah_macVersion;
8368 ah->ah_macRev = ah->ah_macRev;
8369 ah->ah_phyRev = ah->ah_phyRev;
8370 ah->ah_analog5GhzRev = ah->ah_analog5GhzRev;
8371 ah->ah_analog2GhzRev = ah->ah_analog2GhzRev;
8372 }
8373 return ah;
8374 }
8375
8376 u_int16_t
8377 ath9k_hw_computetxtime(struct ath_hal *ah,
8378 const struct hal_rate_table *rates,
8379 u_int32_t frameLen, u_int16_t rateix,
8380 enum hal_bool shortPreamble)
8381 {
8382 u_int32_t bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
8383 u_int32_t kbps;
8384
8385 kbps = rates->info[rateix].rateKbps;
8386
8387 if (kbps == 0)
8388 return 0;
8389 switch (rates->info[rateix].phy) {
8390
8391 case PHY_CCK:
8392 phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
8393 if (shortPreamble && rates->info[rateix].shortPreamble)
8394 phyTime >>= 1;
8395 numBits = frameLen << 3;
8396 txTime = CCK_SIFS_TIME + phyTime
8397 + ((numBits * 1000) / kbps);
8398 break;
8399 case PHY_OFDM:
8400 if (ah->ah_curchan && IS_CHAN_QUARTER_RATE(ah->ah_curchan)) {
8401 bitsPerSymbol =
8402 (kbps * OFDM_SYMBOL_TIME_QUARTER) / 1000;
8403
8404 numBits = OFDM_PLCP_BITS + (frameLen << 3);
8405 numSymbols = howmany(numBits, bitsPerSymbol);
8406 txTime = OFDM_SIFS_TIME_QUARTER
8407 + OFDM_PREAMBLE_TIME_QUARTER
8408 + (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
8409 } else if (ah->ah_curchan &&
8410 IS_CHAN_HALF_RATE(ah->ah_curchan)) {
8411 bitsPerSymbol =
8412 (kbps * OFDM_SYMBOL_TIME_HALF) / 1000;
8413
8414 numBits = OFDM_PLCP_BITS + (frameLen << 3);
8415 numSymbols = howmany(numBits, bitsPerSymbol);
8416 txTime = OFDM_SIFS_TIME_HALF +
8417 OFDM_PREAMBLE_TIME_HALF
8418 + (numSymbols * OFDM_SYMBOL_TIME_HALF);
8419 } else {
8420 bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
8421
8422 numBits = OFDM_PLCP_BITS + (frameLen << 3);
8423 numSymbols = howmany(numBits, bitsPerSymbol);
8424 txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
8425 + (numSymbols * OFDM_SYMBOL_TIME);
8426 }
8427 break;
8428
8429 default:
8430 HDPRINTF(ah, HAL_DBG_PHY_IO,
8431 "%s: unknown phy %u (rate ix %u)\n", __func__,
8432 rates->info[rateix].phy, rateix);
8433 txTime = 0;
8434 break;
8435 }
8436 return txTime;
8437 }
8438
8439 u_int ath9k_hw_mhz2ieee(struct ath_hal *ah, u_int freq, u_int flags)
8440 {
8441 if (flags & CHANNEL_2GHZ) {
8442 if (freq == 2484)
8443 return 14;
8444 if (freq < 2484)
8445 return (freq - 2407) / 5;
8446 else
8447 return 15 + ((freq - 2512) / 20);
8448 } else if (flags & CHANNEL_5GHZ) {
8449 if (ath9k_regd_is_public_safety_sku(ah) &&
8450 IS_CHAN_IN_PUBLIC_SAFETY_BAND(freq)) {
8451 return ((freq * 10) +
8452 (((freq % 5) == 2) ? 5 : 0) - 49400) / 5;
8453 } else if ((flags & CHANNEL_A) && (freq <= 5000)) {
8454 return (freq - 4000) / 5;
8455 } else {
8456 return (freq - 5000) / 5;
8457 }
8458 } else {
8459 if (freq == 2484)
8460 return 14;
8461 if (freq < 2484)
8462 return (freq - 2407) / 5;
8463 if (freq < 5000) {
8464 if (ath9k_regd_is_public_safety_sku(ah)
8465 && IS_CHAN_IN_PUBLIC_SAFETY_BAND(freq)) {
8466 return ((freq * 10) +
8467 (((freq % 5) ==
8468 2) ? 5 : 0) - 49400) / 5;
8469 } else if (freq > 4900) {
8470 return (freq - 4000) / 5;
8471 } else {
8472 return 15 + ((freq - 2512) / 20);
8473 }
8474 }
8475 return (freq - 5000) / 5;
8476 }
8477 }
8478
8479 int16_t
8480 ath9k_hw_getchan_noise(struct ath_hal *ah, struct hal_channel *chan)
8481 {
8482 struct hal_channel_internal *ichan;
8483
8484 ichan = ath9k_regd_check_channel(ah, chan);
8485 if (ichan == NULL) {
8486 HDPRINTF(ah, HAL_DBG_NF_CAL,
8487 "%s: invalid channel %u/0x%x; no mapping\n",
8488 __func__, chan->channel, chan->channelFlags);
8489 return 0;
8490 }
8491 if (ichan->rawNoiseFloor == 0) {
8492 enum wireless_mode mode = ath9k_hw_chan2wmode(ah, chan);
8493 return NOISE_FLOOR[mode];
8494 } else
8495 return ichan->rawNoiseFloor;
8496 }
8497
8498 enum hal_bool ath9k_hw_set_tsfadjust(struct ath_hal *ah, u_int32_t setting)
8499 {
8500 struct ath_hal_5416 *ahp = AH5416(ah);
8501
8502 if (setting)
8503 ahp->ah_miscMode |= AR_PCU_TX_ADD_TSF;
8504 else
8505 ahp->ah_miscMode &= ~AR_PCU_TX_ADD_TSF;
8506 return AH_TRUE;
8507 }
8508
8509 enum hal_bool ath9k_hw_phycounters(struct ath_hal *ah)
8510 {
8511 struct ath_hal_5416 *ahp = AH5416(ah);
8512
8513 return ahp->ah_hasHwPhyCounters ? AH_TRUE : AH_FALSE;
8514 }
8515
8516 u_int32_t ath9k_hw_gettxbuf(struct ath_hal *ah, u_int q)
8517 {
8518 return REG_READ(ah, AR_QTXDP(q));
8519 }
8520
8521 enum hal_bool ath9k_hw_puttxbuf(struct ath_hal *ah, u_int q,
8522 u_int32_t txdp)
8523 {
8524 REG_WRITE(ah, AR_QTXDP(q), txdp);
8525
8526 return AH_TRUE;
8527 }
8528
8529 enum hal_bool ath9k_hw_txstart(struct ath_hal *ah, u_int q)
8530 {
8531 HDPRINTF(ah, HAL_DBG_QUEUE, "%s: queue %u\n", __func__, q);
8532
8533 REG_WRITE(ah, AR_Q_TXE, 1 << q);
8534
8535 return AH_TRUE;
8536 }
8537
8538 u_int32_t ath9k_hw_numtxpending(struct ath_hal *ah, u_int q)
8539 {
8540 u_int32_t npend;
8541
8542 npend = REG_READ(ah, AR_QSTS(q)) & AR_Q_STS_PEND_FR_CNT;
8543 if (npend == 0) {
8544
8545 if (REG_READ(ah, AR_Q_TXE) & (1 << q))
8546 npend = 1;
8547 }
8548 return npend;
8549 }
8550
8551 enum hal_bool ath9k_hw_stoptxdma(struct ath_hal *ah, u_int q)
8552 {
8553 u_int wait;
8554
8555 REG_WRITE(ah, AR_Q_TXD, 1 << q);
8556
8557 for (wait = 1000; wait != 0; wait--) {
8558 if (ath9k_hw_numtxpending(ah, q) == 0)
8559 break;
8560 udelay(100);
8561 }
8562
8563 if (ath9k_hw_numtxpending(ah, q)) {
8564 u_int32_t tsfLow, j;
8565
8566 HDPRINTF(ah, HAL_DBG_QUEUE,
8567 "%s: Num of pending TX Frames %d on Q %d\n",
8568 __func__, ath9k_hw_numtxpending(ah, q), q);
8569
8570 for (j = 0; j < 2; j++) {
8571 tsfLow = REG_READ(ah, AR_TSF_L32);
8572 REG_WRITE(ah, AR_QUIET2,
8573 SM(10, AR_QUIET2_QUIET_DUR));
8574 REG_WRITE(ah, AR_QUIET_PERIOD, 100);
8575 REG_WRITE(ah, AR_NEXT_QUIET_TIMER, tsfLow >> 10);
8576 OS_REG_SET_BIT(ah, AR_TIMER_MODE,
8577 AR_QUIET_TIMER_EN);
8578
8579 if ((REG_READ(ah, AR_TSF_L32) >> 10) ==
8580 (tsfLow >> 10)) {
8581 break;
8582 }
8583 HDPRINTF(ah, HAL_DBG_QUEUE,
8584 "%s: TSF have moved while trying to set "
8585 "quiet time TSF: 0x%08x\n",
8586 __func__, tsfLow);
8587 }
8588
8589 OS_REG_SET_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
8590
8591 udelay(200);
8592 OS_REG_CLR_BIT(ah, AR_TIMER_MODE, AR_QUIET_TIMER_EN);
8593
8594 wait = 1000;
8595
8596 while (ath9k_hw_numtxpending(ah, q)) {
8597 if ((--wait) == 0) {
8598 HDPRINTF(ah, HAL_DBG_TX,
8599 "%s: Failed to stop Tx DMA in 100 "
8600 "msec after killing last frame\n",
8601 __func__);
8602 break;
8603 }
8604 udelay(100);
8605 }
8606
8607 OS_REG_CLR_BIT(ah, AR_DIAG_SW, AR_DIAG_FORCE_CH_IDLE_HIGH);
8608 }
8609
8610 REG_WRITE(ah, AR_Q_TXD, 0);
8611 return wait != 0;
8612 }
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