package/boot/arm-trusted-firmware-mvebu/patches/100-fix-plat-marvell-a3720-uart-fix-UART-clock-rate-valu.patch

   1 From 66a7752834382595d26214783ae4698fd1f00bd6 Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
   3 Date: Thu, 13 May 2021 14:53:44 +0200
   4 Subject: [PATCH] fix(plat/marvell/a3720/uart): fix UART clock rate value and
   5  divisor calculation
   6 MIME-Version: 1.0
   7 Content-Type: text/plain; charset=UTF-8
   8 Content-Transfer-Encoding: 8bit
   9
  10 UART parent clock is by default the platform's xtal clock, which is
  11 25 MHz.
  12
  13 The value defined in the driver, though, is 25.8048 MHz. This is a hack
  14 for the suboptimal divisor calculation
  15   Divisor = UART clock / (16 * baudrate)
  16 which does not use rounding division, resulting in a suboptimal value
  17 for divisor if the correct parent clock rate was used.
  18
  19 Change the code for divisor calculation to
  20   Divisor = Round(UART clock / (16 * baudrate))
  21 and change the parent clock rate value to 25 MHz.
  22
  23 The final UART divisor for default baudrate 115200 is not affected by
  24 this change.
  25
  26 (Note that the parent clock rate should not be defined via a macro,
  27 since the xtal clock can also be 40 MHz. This is outside of the scope of
  28 this fix, though.)
  29
  30 Signed-off-by: Pali Rohár <pali@kernel.org>
  31 Change-Id: Iaa401173df87aec94f2dd1b38a90fb6ed0bf0ec6
  32 ---
  33  drivers/marvell/uart/a3700_console.S                  | 3 ++-
  34  plat/marvell/armada/a3k/common/include/platform_def.h | 2 +-
  35  2 files changed, 3 insertions(+), 2 deletions(-)
  36
  37 --- a/drivers/marvell/uart/a3700_console.S
  38 +++ b/drivers/marvell/uart/a3700_console.S
  39 @@ -45,8 +45,9 @@ func console_a3700_core_init
  40         cbz     w2, init_fail
  41
  42         /* Program the baudrate */
  43 -       /* Divisor =  Uart clock / (16 * baudrate) */
  44 +       /* Divisor = Round(Uartclock / (16 * baudrate)) */
  45         lsl     w2, w2, #4
  46 +       add     w1, w1, w2, lsr #1
  47         udiv    w2, w1, w2
  48         and     w2, w2, #0x3ff
  49
  50 --- a/plat/marvell/armada/a3k/common/include/platform_def.h
  51 +++ b/plat/marvell/armada/a3k/common/include/platform_def.h
  52 @@ -164,7 +164,7 @@
  53   * PL011 related constants
  54   */
  55  #define PLAT_MARVELL_BOOT_UART_BASE            (MVEBU_REGS_BASE + 0x12000)
  56 -#define PLAT_MARVELL_BOOT_UART_CLK_IN_HZ       25804800
  57 +#define PLAT_MARVELL_BOOT_UART_CLK_IN_HZ       25000000
  58
  59  #define PLAT_MARVELL_CRASH_UART_BASE           PLAT_MARVELL_BOOT_UART_BASE
  60  #define PLAT_MARVELL_CRASH_UART_CLK_IN_HZ      PLAT_MARVELL_BOOT_UART_CLK_IN_HZ