1 /******************************************************************************
3 ** FILE NAME : ifxmips_ptm_vr9.c
9 ** DESCRIPTION : PTM driver common source file (core functions)
10 ** COPYRIGHT : Copyright (c) 2006
11 ** Infineon Technologies AG
12 ** Am Campeon 1-12, 85579 Neubiberg, Germany
14 ** This program is free software; you can redistribute it and/or modify
15 ** it under the terms of the GNU General Public License as published by
16 ** the Free Software Foundation; either version 2 of the License, or
17 ** (at your option) any later version.
20 ** $Date $Author $Comment
21 ** 07 JUL 2009 Xu Liang Init Version
22 *******************************************************************************/
27 * ####################################
29 * ####################################
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/version.h>
38 #include <linux/types.h>
39 #include <linux/errno.h>
40 #include <linux/proc_fs.h>
41 #include <linux/init.h>
42 #include <linux/ioctl.h>
43 #include <linux/platform_device.h>
44 #include <linux/reset.h>
45 #include <asm/delay.h>
48 * Chip Specific Head File
50 #include "ifxmips_ptm_vdsl.h"
51 #include "ifxmips_ptm_fw_vr9.h"
53 #include <lantiq_soc.h>
55 static inline void init_pmu(void);
56 static inline void uninit_pmu(void);
57 static inline void reset_ppe(struct platform_device
*pdev
);
58 static inline void init_pdma(void);
59 static inline void init_mailbox(void);
60 static inline void init_atm_tc(void);
61 static inline void clear_share_buffer(void);
63 #define IFX_PMU_MODULE_PPE_SLL01 BIT(19)
64 #define IFX_PMU_MODULE_PPE_TC BIT(21)
65 #define IFX_PMU_MODULE_PPE_EMA BIT(22)
66 #define IFX_PMU_MODULE_PPE_QSB BIT(18)
67 #define IFX_PMU_MODULE_AHBS BIT(13)
68 #define IFX_PMU_MODULE_DSL_DFE BIT(9)
71 static inline void init_pmu(void)
73 ltq_pmu_enable(IFX_PMU_MODULE_PPE_SLL01
|
74 IFX_PMU_MODULE_PPE_TC
|
75 IFX_PMU_MODULE_PPE_EMA
|
77 IFX_PMU_MODULE_DSL_DFE
);
81 static inline void uninit_pmu(void)
85 static inline void reset_ppe(struct platform_device
*pdev
)
87 struct device
*dev
= &pdev
->dev
;
88 struct reset_control
*dsp
;
89 struct reset_control
*dfe
;
90 struct reset_control
*tc
;
92 dsp
= devm_reset_control_get(dev
, "dsp");
94 if (PTR_ERR(dsp
) != -EPROBE_DEFER
)
95 dev_err(dev
, "Failed to lookup dsp reset\n");
96 // return PTR_ERR(dsp);
99 dfe
= devm_reset_control_get(dev
, "dfe");
101 if (PTR_ERR(dfe
) != -EPROBE_DEFER
)
102 dev_err(dev
, "Failed to lookup dfe reset\n");
103 // return PTR_ERR(dfe);
106 tc
= devm_reset_control_get(dev
, "tc");
108 if (PTR_ERR(tc
) != -EPROBE_DEFER
)
109 dev_err(dev
, "Failed to lookup tc reset\n");
110 // return PTR_ERR(tc);
113 reset_control_assert(dsp
);
115 reset_control_assert(dfe
);
117 reset_control_assert(tc
);
119 *PP32_SRST
&= ~0x000303CF;
121 *PP32_SRST
|= 0x000303CF;
125 static inline void init_pdma(void)
127 IFX_REG_W32(0x00000001, PDMA_CFG
);
128 IFX_REG_W32(0x00082C00, PDMA_RX_CTX_CFG
);
129 IFX_REG_W32(0x00081B00, PDMA_TX_CTX_CFG
);
130 IFX_REG_W32(0x02040604, PDMA_RX_MAX_LEN_REG
);
131 IFX_REG_W32(0x000F003F, PDMA_RX_DELAY_CFG
);
133 IFX_REG_W32(0x00000011, SAR_MODE_CFG
);
134 IFX_REG_W32(0x00082A00, SAR_RX_CTX_CFG
);
135 IFX_REG_W32(0x00082E00, SAR_TX_CTX_CFG
);
136 IFX_REG_W32(0x00001021, SAR_POLY_CFG_SET0
);
137 IFX_REG_W32(0x1EDC6F41, SAR_POLY_CFG_SET1
);
138 IFX_REG_W32(0x04C11DB7, SAR_POLY_CFG_SET2
);
139 IFX_REG_W32(0x00000F3E, SAR_CRC_SIZE_CFG
);
141 IFX_REG_W32(0x01001900, SAR_PDMA_RX_CMDBUF_CFG
);
142 IFX_REG_W32(0x01001A00, SAR_PDMA_TX_CMDBUF_CFG
);
145 static inline void init_mailbox(void)
147 IFX_REG_W32(0xFFFFFFFF, MBOX_IGU1_ISRC
);
148 IFX_REG_W32(0x00000000, MBOX_IGU1_IER
);
149 IFX_REG_W32(0xFFFFFFFF, MBOX_IGU3_ISRC
);
150 IFX_REG_W32(0x00000000, MBOX_IGU3_IER
);
153 static inline void init_atm_tc(void)
155 IFX_REG_W32(0x00010040, SFSM_CFG0
);
156 IFX_REG_W32(0x00010040, SFSM_CFG1
);
157 IFX_REG_W32(0x00020000, SFSM_PGCNT0
);
158 IFX_REG_W32(0x00020000, SFSM_PGCNT1
);
159 IFX_REG_W32(0x00000000, DREG_AT_IDLE0
);
160 IFX_REG_W32(0x00000000, DREG_AT_IDLE1
);
161 IFX_REG_W32(0x00000000, DREG_AR_IDLE0
);
162 IFX_REG_W32(0x00000000, DREG_AR_IDLE1
);
163 IFX_REG_W32(0x0000080C, DREG_B0_LADR
);
164 IFX_REG_W32(0x0000080C, DREG_B1_LADR
);
166 IFX_REG_W32(0x000001F0, DREG_AR_CFG0
);
167 IFX_REG_W32(0x000001F0, DREG_AR_CFG1
);
168 IFX_REG_W32(0x000001E0, DREG_AT_CFG0
);
169 IFX_REG_W32(0x000001E0, DREG_AT_CFG1
);
171 /* clear sync state */
172 //IFX_REG_W32(0, SFSM_STATE0);
173 //IFX_REG_W32(0, SFSM_STATE1);
175 IFX_REG_W32_MASK(0, 1 << 14, SFSM_CFG0
); // enable SFSM storing
176 IFX_REG_W32_MASK(0, 1 << 14, SFSM_CFG1
);
178 IFX_REG_W32_MASK(0, 1 << 15, SFSM_CFG0
); // HW keep the IDLE cells in RTHA buffer
179 IFX_REG_W32_MASK(0, 1 << 15, SFSM_CFG1
);
181 IFX_REG_W32(0xF0D10000, FFSM_IDLE_HEAD_BC0
);
182 IFX_REG_W32(0xF0D10000, FFSM_IDLE_HEAD_BC1
);
183 IFX_REG_W32(0x00030028, FFSM_CFG0
); // Force_idle
184 IFX_REG_W32(0x00030028, FFSM_CFG1
);
187 static inline void clear_share_buffer(void)
193 for ( i
= 0; i
< SB_RAM0_DWLEN
+ SB_RAM1_DWLEN
+ SB_RAM2_DWLEN
+ SB_RAM3_DWLEN
; i
++ )
197 for ( i
= 0; i
< SB_RAM6_DWLEN
; i
++ )
203 * Download PPE firmware binary code.
205 * pp32 --- int, which pp32 core
206 * src --- u32 *, binary code buffer
207 * dword_len --- unsigned int, binary code length in DWORD (32-bit)
212 static inline int pp32_download_code(int pp32
, u32
*code_src
, unsigned int code_dword_len
, u32
*data_src
, unsigned int data_dword_len
)
214 unsigned int clr
, set
;
217 if ( code_src
== 0 || ((unsigned long)code_src
& 0x03) != 0
218 || data_src
== 0 || ((unsigned long)data_src
& 0x03) != 0 )
221 clr
= pp32
? 0xF0 : 0x0F;
222 if ( code_dword_len
<= CDM_CODE_MEMORYn_DWLEN(0) )
223 set
= pp32
? (3 << 6): (2 << 2);
226 IFX_REG_W32_MASK(clr
, set
, CDM_CFG
);
229 dest
= CDM_CODE_MEMORY(pp32
, 0);
230 while ( code_dword_len
-- > 0 )
231 IFX_REG_W32(*code_src
++, dest
++);
234 dest
= CDM_DATA_MEMORY(pp32
, 0);
235 while ( data_dword_len
-- > 0 )
236 IFX_REG_W32(*data_src
++, dest
++);
244 * ####################################
246 * ####################################
249 void ifx_ptm_get_fw_ver(unsigned int *major
, unsigned int *mid
, unsigned int *minor
)
251 ASSERT(major
!= NULL
, "pointer is NULL");
252 ASSERT(minor
!= NULL
, "pointer is NULL");
254 if ( *(volatile unsigned int *)FW_VER_ID_NEW
== 0 ) {
255 *major
= FW_VER_ID
->major
;
257 *minor
= FW_VER_ID
->minor
;
260 *major
= FW_VER_ID_NEW
->major
;
261 *mid
= FW_VER_ID_NEW
->middle
;
262 *minor
= FW_VER_ID_NEW
->minor
;
266 void ifx_ptm_init_chip(struct platform_device
*pdev
)
278 clear_share_buffer();
281 void ifx_ptm_uninit_chip(void)
288 * Initialize and start up PP32.
295 int ifx_pp32_start(int pp32
)
297 unsigned int mask
= 1 << (pp32
<< 4);
300 /* download firmware */
301 ret
= pp32_download_code(pp32
, firmware_binary_code
, sizeof(firmware_binary_code
) / sizeof(*firmware_binary_code
), firmware_binary_data
, sizeof(firmware_binary_data
) / sizeof(*firmware_binary_data
));
306 IFX_REG_W32_MASK(mask
, 0, PP32_FREEZE
);
308 /* idle for a while to let PP32 init itself */
322 void ifx_pp32_stop(int pp32
)
324 unsigned int mask
= 1 << (pp32
<< 4);
327 IFX_REG_W32_MASK(0, mask
, PP32_FREEZE
);