package/kernel/lantiq/vrx518_ep/src/aca.h

   1 /*******************************************************************************
   2
   3   Intel SmartPHY DSL PCIe Endpoint/ACA Linux driver
   4   Copyright(c) 2016 Intel Corporation.
   5
   6   This program is free software; you can redistribute it and/or modify it
   7   under the terms and conditions of the GNU General Public License,
   8   version 2, as published by the Free Software Foundation.
   9
  10   This program is distributed in the hope it will be useful, but WITHOUT
  11   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12   FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13   more details.
  14
  15   You should have received a copy of the GNU General Public License along with
  16   this program; if not, write to the Free Software Foundation, Inc.,
  17   51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  18
  19   The full GNU General Public License is included in this distribution in
  20   the file called "COPYING".
  21
  22 *******************************************************************************/
  23
  24 #ifndef ACA_H
  25 #define ACA_H
  26
  27 #define HOST_IF_BASE            0x50000
  28 #define ACA_CORE_BASE           0x50800
  29 #define GENRISC_IRAM_BASE       0x58000
  30 #define GENRISC_SPRAM_BASE      0x5C000
  31 #define GENRISC_BASE            0x5D000
  32 #define MAC_HT_EXT_BASE         0x5D400
  33 #define ACA_SRAM_BASE           0x100000
  34 #define ACA_SRAM_SIZE           0x2000 /* Project specific */
  35 #define ACA_HOSTIF_ADDR_SHIFT   2
  36
  37 #define ACA_HOSTIF_ADDR(addr)   ((addr) >> ACA_HOSTIF_ADDR_SHIFT)
  38
  39 #define ACA_HIF_LOC_POS         0x100060
  40 #define ACA_HIF_PARAM_ADDR      0x100064
  41 #define ACA_ACC_FW_SIZE         0x400
  42 #define ACA_LOOP_CNT            1000
  43
  44 /* TODO: change name after karthik explained */
  45 #define TXIN_DST_OWNBIT         0xC4
  46 #define TXOUT_DST_OWNBIT        0x1C4
  47 #define RXOUT_SRC_OWNBIT        0x3C4
  48 #define RXIN_DST_OWNBIT         0x2C4
  49
  50 /* Genrisc Internal Host Descriptor(Ping/Pong) decided by ACA fw header */
  51 /* ACA Core */
  52 #define ACA_CORE_REG(X) (ACA_CORE_BASE + (X))
  53 #define TXIN_CFG1       ACA_CORE_REG(0x0)
  54 #define TXIN_CFG2       ACA_CORE_REG(0x4)
  55 #define TXIN_CFG3       ACA_CORE_REG(0x8)
  56 #define TXIN_DST_OWWBIT_CFG4    ACA_CORE_REG(TXIN_DST_OWNBIT)
  57
  58 #define TXOUT_CFG1      ACA_CORE_REG(0x100)
  59 #define TXOUT_CFG2      ACA_CORE_REG(0x104)
  60 #define TXOUT_CFG3      ACA_CORE_REG(0x108)
  61 #define TXOUT_DST_OWWBIT_CFG4   ACA_CORE_REG(TXOUT_DST_OWNBIT)
  62
  63 #define RXOUT_CFG1      ACA_CORE_REG(0x300)
  64 #define RXOUT_CFG2      ACA_CORE_REG(0x304)
  65 #define RXOUT_CFG3      ACA_CORE_REG(0x308)
  66 #define RXOUT_SRC_OWNBIT_CFG3   ACA_CORE_REG(RXOUT_SRC_OWNBIT)
  67
  68 #define RXIN_CFG1       ACA_CORE_REG(0x200)
  69 #define RXIN_CFG2       ACA_CORE_REG(0x204)
  70 #define RXIN_CFG3       ACA_CORE_REG(0x208)
  71 #define RXIN_SRC_OWNBIT_CFG3    ACA_CORE_REG(RXIN_DST_OWNBIT)
  72
  73 /* Genrisc */
  74 #define GNRC_REG(X)             (GENRISC_BASE + (X))
  75 #define GNRC_STOP_OP            GNRC_REG(0x60)
  76 #define GNRC_CONTINUE_OP        GNRC_REG(0x64)
  77 #define GNRC_START_OP           GNRC_REG(0x90)
  78
  79 /* HOST Interface Register */
  80 #define HOST_IF_REG(X)          (HOST_IF_BASE + (X))
  81 #define HD_DESC_IN_DW           0x7u
  82 #define HD_DESC_IN_DW_S         0
  83 #define PD_DESC_IN_DW           0x70u
  84 #define PD_DESC_IN_DW_S         4
  85 #define BYTE_SWAP_EN            BIT(28)
  86
  87 #define TXIN_CONV_CFG           HOST_IF_REG(0x14)
  88 #define TXOUT_CONV_CFG          HOST_IF_REG(0x18)
  89 #define RXIN_CONV_CFG           HOST_IF_REG(0x1C)
  90 #define RXOUT_CONV_CFG          HOST_IF_REG(0x20)
  91
  92 #define TXIN_COUNTERS           HOST_IF_REG(0x44)
  93 #define TXOUT_COUNTERS          HOST_IF_REG(0x48)
  94 #define RXIN_COUNTERS           HOST_IF_REG(0x4c)
  95 #define RXOUT_COUNTERS          HOST_IF_REG(0x50)
  96
  97 #define TXOUT_RING_CFG          HOST_IF_REG(0x98)
  98 #define RXOUT_RING_CFG          HOST_IF_REG(0x9C)
  99
 100 #define ACA_PENDING_JOB         0x00000300
 101 #define ACA_PENDING_JOB_S       8
 102 #define ACA_AVAIL_BUF           0x00030000
 103 #define ACA_AVAIL_BUF_S         16
 104 #define ACA_PP_BUFS             2
 105
 106 #define HOST_TYPE               HOST_IF_REG(0xA0)
 107 #define TXOUT_COUNTERS_UPDATE   HOST_IF_REG(0xAC)
 108 #define RXOUT_COUNTERS_UPDATE   HOST_IF_REG(0xB4)
 109 #define RXIN_HD_ACCUM_ADD       HOST_IF_REG(0xC8) /* UMT Message trigger */
 110 #define TXIN_HD_ACCUM_ADD       HOST_IF_REG(0xCC) /* UMT Message trigger */
 111 #define RXOUT_HD_ACCUM_ADD      HOST_IF_REG(0xD0)
 112 #define TXOUT_HD_ACCUM_ADD      HOST_IF_REG(0xD4)
 113 #define RXOUT_ACA_ACCUM_ADD     HOST_IF_REG(0xE0) /* PPE FW tigger */
 114 #define TXOUT_ACA_ACCUM_ADD     HOST_IF_REG(0xE4) /* PPE FW tigger */
 115 #define RXOUT_HD_ACCUM_SUB      HOST_IF_REG(0xF8)
 116 #define TXOUT_HD_ACCUM_SUB      HOST_IF_REG(0xFC)
 117 #define RXIN_ACA_ACCUM_SUB      HOST_IF_REG(0x100)
 118 #define TXIN_ACA_ACCUM_SUB      HOST_IF_REG(0x104)
 119 #define TXIN_ACA_HD_ACC_CNT     HOST_IF_REG(0x11C)
 120 #define UMT_ORDER_CFG           HOST_IF_REG(0x234)
 121 #define RXIN_HD_ACCUM_ADD_BE    HOST_IF_REG(0x250)
 122 #define TXIN_HD_ACCUM_ADD_BE    HOST_IF_REG(0x254)
 123 #define RXOUT_HD_ACCUM_SUB_BE   HOST_IF_REG(0x268)
 124 #define TXOUT_HD_ACCUM_SUB_BE   HOST_IF_REG(0x26c)
 125
 126 /* MAC_HT_EXTENSION Register */
 127 #define MAC_HT_EXT_REG(X)       (MAC_HT_EXT_BASE + (X))
 128
 129 #define HT_GCLK_ENABLE          MAC_HT_EXT_REG(0)
 130 #define HT_SW_RST_RELEASE       MAC_HT_EXT_REG(0x4)
 131 #define HT_SW_RST_ASSRT         MAC_HT_EXT_REG(0x1C)
 132 #define SW_RST_GENRISC          BIT(14)
 133 #define SW_RST_RXOUT            BIT(26)
 134 #define SW_RST_RXIN             BIT(27)
 135 #define SW_RST_TXOUT            BIT(28)
 136 #define SW_RST_TXIN             BIT(29)
 137 #define SW_RST_HOSTIF_REG       BIT(30)
 138 #define OCP_ARB_ACC_PAGE_REG    MAC_HT_EXT_REG(0x1C4)
 139 #define AHB_ARB_HP_REG          MAC_HT_EXT_REG(0x1C8)
 140
 141 /* Genrisc FW Configuration */
 142 #define GNRC_SPRAM_REG(X)       (GENRISC_SPRAM_BASE + (X))
 143
 144 /* TX IN */
 145 #define GNRC_TXIN_TGT_STAT              GNRC_SPRAM_REG(0x04)
 146 #define GNRC_TXIN_TGT_PD_OFF            GNRC_SPRAM_REG(0x08)
 147 #define GNRC_TXIN_TGT_ACCM_CNT          GNRC_SPRAM_REG(0x0C)
 148
 149 /* TX OUT */
 150 #define GNRC_TXOUT_TGT_STAT             GNRC_SPRAM_REG(0x10)
 151 #define GNRC_TXOUT_TGT_PD_OFF           GNRC_SPRAM_REG(0x14)
 152 #define GNRC_TXOUT_TGT_ACCM_CNT         GNRC_SPRAM_REG(0x18)
 153
 154 /* RX IN */
 155 #define GNRC_RXIN_TGT_STAT              GNRC_SPRAM_REG(0x1C)
 156 #define GNRC_RXIN_TGT_PD_OFF            GNRC_SPRAM_REG(0x20)
 157 #define GNRC_RXIN_TGT_ACCM_CNT          GNRC_SPRAM_REG(0x24)
 158
 159 /* RX OUT XXX not consistent */
 160 #define GNRC_RXOUT_TGT_STAT             GNRC_SPRAM_REG(0x28)
 161 #define GNRC_RXOUT_TGT_PD_OFF           GNRC_SPRAM_REG(0x2C)
 162 #define GNRC_RXOUT_TGT_ACCM_CNT         GNRC_SPRAM_REG(0x30)
 163
 164 /* 4 Ring 8 UMT case SoC cumulative counter address configuration */
 165 #define GNRC_TXIN_CMLT_CNT_ADDR         GNRC_SPRAM_REG(0x34)
 166 #define GNRC_TXOUT_CMLT_CNT_ADDR        GNRC_SPRAM_REG(0x38)
 167 #define GNRC_RXOUT_CMLT_CNT_ADDR        GNRC_SPRAM_REG(0x3C)
 168 #define GNRC_RXIN_CMLT_CNT_ADDR         GNRC_SPRAM_REG(0x40)
 169
 170
 171 #define GNRC_SOURCE_TXIN_CMLT_CNT_ADDR  GNRC_SPRAM_REG(0x54)
 172 #define GNRC_SOURCE_TXOUT_CMLT_CNT_ADDR GNRC_SPRAM_REG(0x58)
 173 #define GNRC_SOURCE_RXOUT_CMLT_CNT_ADDR GNRC_SPRAM_REG(0x5c)
 174 #define GNRC_SOURCE_RXIN_CMLT_CNT_ADDR  GNRC_SPRAM_REG(0x60)
 175
 176 /* Txin index prefill */
 177 #define GNRC_TXIN_BUF_PREFILL           GNRC_SPRAM_REG(0x44)
 178 /* Task enable bitmap */
 179 #define GNRC_EN_TASK_BITMAP             GNRC_SPRAM_REG(0x64)
 180
 181 #define ACA_SRAM_REG(X) (ACA_SRAM_BASE + (X))
 182 #define ACA_TXOUT_PING_BUFFER_START ACA_SRAM_REG(0x1528)
 183
 184
 185 /* XBAR SSX0 */
 186 #define ACA_SSX0_BASE                   0x180000
 187 #define ACA_SSX0_IA_BASE(id)            (ACA_SSX0_BASE + (((id) - 1) << 10))
 188 #define ACA_AGENT_CTRL(id)              (ACA_SSX0_IA_BASE(id) + 0x20)
 189 #define ACA_AGENT_STATUS(id)            (ACA_SSX0_IA_BASE(id) + 0x28)
 190
 191 #define XBAR_CTRL_CORE_RESET            BIT(0)
 192 #define XBAR_CTRL_REJECT                BIT(4)
 193
 194 #define XBAR_STAT_CORE_RESET            BIT(0)
 195 #define XBAR_STAT_REQ_ACTIVE            BIT(4)
 196 #define XBAR_STAT_RESP_WAITING          BIT(5)
 197 #define XBAR_STAT_BURST                 BIT(6)
 198 #define XBAR_STAT_READEX                BIT(7)
 199
 200 enum {
 201         ACA_ACC_IA04 = 4,
 202         ACA_M_IA06 = 6,
 203 };
 204
 205 /* Should be passed from ACA FW header */
 206 #define DESC_NUM_PER_CH         1
 207
 208 /* ACA DMA REG */
 209 #define ACA_DMA_BASE            0x60000
 210
 211 #define ACA_DMA_REG(X)          (ACA_DMA_BASE + (X))
 212 #define ADMA_CLC                ACA_DMA_REG(0x0)
 213 #define ADMA_ID                 ACA_DMA_REG(0x8)
 214 #define ADMA_CTRL               ACA_DMA_REG(0x10)
 215 #define ADMA_CPOLL              ACA_DMA_REG(0x14)
 216
 217 #define ADMA_ID_REV             0x1Fu
 218 #define ADMA_ID_REV_S           0
 219 #define ADMA_ID_ID              0xFF00u
 220 #define ADMA_ID_ID_S            8
 221 #define ADMA_ID_PRTNR           0xF0000u
 222 #define ADMA_ID_PRTNR_S         16
 223 #define ADMA_ID_CHNR            0x7F00000u
 224 #define ADMA_ID_CHNR_S          20
 225
 226 #define ADMA_CPOLL_EN           BIT(31)
 227
 228 #define ADMA_CPOLL_CNT          0xFFF0u
 229 #define ADMA_CPOLL_CNT_S        4
 230 #define ADMA_DEFAULT_POLL       24
 231 #define ADMA_CS                 ACA_DMA_REG(0x18)
 232 #define ADMA_CCTRL              ACA_DMA_REG(0x1C)
 233 #define ADMA_CDBA               ACA_DMA_REG(0x20)
 234 #define ADMA_CDLEN              ACA_DMA_REG(0x24)
 235 #define ADMA_CIS                ACA_DMA_REG(0x28)
 236 #define ADMA_CIE                ACA_DMA_REG(0x2C)
 237
 238 #define ADMA_CI_EOP             BIT(1)
 239 #define ADMA_CI_DUR             BIT(2)
 240 #define ADMA_CI_DESCPT          BIT(3)
 241 #define ADMA_CI_CHOFF           BIT(4)
 242 #define ADMA_CI_RDERR           BIT(5)
 243 #define ADMA_CI_ALL             (ADMA_CI_EOP | ADMA_CI_DUR | ADMA_CI_DESCPT\
 244                                 | ADMA_CI_CHOFF | ADMA_CI_RDERR)
 245
 246 #define ADMA_CDPTNRD            ACA_DMA_REG(0x34)
 247 #define ADMA_PS                 ACA_DMA_REG(0x40)
 248 #define ADMA_PCTRL              ACA_DMA_REG(0x44)
 249
 250 /* DMA CCTRL BIT */
 251 #define CCTRL_RST               1 /* Channel Reset */
 252 #define CCTRL_ONOFF             0 /* Channel On/Off */
 253
 254 /* DMA CTRL BIT */
 255 #define CTRL_PKTARB             31 /* Packet Arbitration */
 256 #define CTRL_MDC                15 /* Meta data copy */
 257 #define CTRL_DDBR               14 /* Dynamic Burst */
 258 #define CTRL_DCNF               13 /* Descriptor Length CFG*/
 259 #define CTRL_ENBE               9 /* Byte Enable */
 260 #define CTRL_DRB                8 /* Descriptor read back */
 261 #define CTRL_DSRAM              1 /* Dedicated Descriptor Access port Enable */
 262 #define CTRL_RST                0 /* Global Reset */
 263
 264 /* DMA PORT BIT */
 265 #define PCTRL_FLUSH             16
 266 #define PCTRL_TXENDI            10 /* TX DIR Endianess */
 267 #define PCTRL_RXENDI            8 /* RX DIR Endianess */
 268 #define PCTRL_TXBL              4 /* TX burst 2/4/8 */
 269 #define PCTRL_RXBL              2 /* RX burst 2/4/8 */
 270 #define PCTRL_TXBL16            1 /* TX burst of 16 */
 271 #define PCTRL_RXBL16            0 /* RX burst of 16 */
 272
 273 /*DMA ID BIT */
 274 #define ID_CHNR                 20 /* Channel Number */
 275
 276 /*DMA POLLING BIT */
 277 #define POLL_EN                 31 /* Polling Enable */
 278 #define POLL_CNT                4 /* Polling Counter */
 279
 280 #define ACA_DMA_CHAN_MAX        12
 281
 282 enum aca_sec_id {
 283         ACA_SEC_HIF = 0x1,
 284         ACA_SEC_GNR = 0x2,
 285         ACA_SEC_MAC_HT = 0x3,
 286         ACA_SEC_MEM_TXIN = 0x4,
 287         ACA_SEC_MEM_TXIN_PDRING = 0x5,
 288         ACA_SEC_MEM_TXOUT = 0x6,
 289         ACA_SEC_MEM_TXOUT_PDRING = 0x7,
 290         ACA_SEC_MEM_RXOUT = 0x8,
 291         ACA_SEC_MEM_RXOUT_PDRING = 0x9,
 292         ACA_SEC_MEM_RXIN = 0xa,
 293         ACA_SEC_MEM_RXIN_PDRING = 0xb,
 294         ACA_SEC_DMA = 0xc,
 295         ACA_SEC_FW_INIT = 0xd,
 296         ACA_SEC_FW = 0x88,
 297 };
 298
 299 enum aca_fw_id {
 300         ACA_FW_TXIN = 1,
 301         ACA_FW_TXOUT = 2,
 302         ACA_FW_RXIN = 3,
 303         ACA_FW_RXOUT = 4,
 304         ACA_FW_GNRC = 5,
 305         ACA_FW_MAX = 5,
 306 };
 307
 308 enum aca_img_type {
 309         ACA_VRX518_IMG,
 310         ACA_VRX618_IMG,
 311         ACA_FALCON_IMG,
 312         ACA_PUMA_IMG,
 313         ACA_IMG_MAX,
 314 };
 315
 316 enum aca_soc_type {
 317         ACA_SOC_XRX300 = 1,
 318         ACA_SOC_XRX500 = 2,
 319         ACA_SOC_PUMA   = 4,
 320         ACA_SOC_3RD_PARTY = 8,
 321 };
 322
 323 #define ACA_SOC_MASK    0xf
 324
 325 /* Common information element, len has different variants */
 326 struct aca_fw_ie {
 327         __be32 id;
 328         __be32 len;
 329 } __packed;
 330
 331 struct aca_fw_reg {
 332         __be32 offset;
 333         __be32 value;
 334 } __packed;
 335
 336 struct aca_sram_desc {
 337         __be32 dnum;
 338         __be32 dbase;
 339 } __packed;
 340
 341 struct aca_fw_dma {
 342         __be32 cid;
 343         __be32 base;
 344 } __packed;
 345
 346 /* ACA internal header part */
 347 struct aca_int_hdr {
 348         __be32 id;
 349         __be32 offset;
 350         __be32 size;
 351         __be32 load_addr;
 352 } __packed;
 353
 354 struct aca_fw_param {
 355         __be32 st_sz;
 356         __be32 init_addr;
 357 } __packed;
 358
 359 struct aca_mem_layout {
 360         u32 txin_host_desc_base;
 361         u32 txin_host_dnum;
 362         u32 txout_host_desc_base;
 363         u32 txout_host_dnum;
 364         u32 rxin_host_desc_base;
 365         u32 rxin_host_dnum;
 366         u32 rxout_host_desc_base;
 367         u32 rxout_host_dnum;
 368 };
 369
 370 struct aca_pdmem_layout {
 371         u32 txin_pd_desc_base;
 372         u32 txin_pd_dnum;
 373         u32 txout_pd_desc_base;
 374         u32 txout_pd_dnum;
 375         u32 rxin_pd_desc_base;
 376         u32 rxin_pd_dnum;
 377         u32 rxout_pd_desc_base;
 378         u32 rxout_pd_dnum;
 379 };
 380
 381 struct aca_fw_addr_tuple {
 382         u32 fw_id;
 383         u32 fw_load_addr;
 384         size_t fw_size;
 385         const char *fw_base;
 386 };
 387
 388 struct aca_fw_dl_addr {
 389         u32 fw_num;
 390         struct aca_fw_addr_tuple fw_addr[ACA_FW_MAX];
 391 };
 392
 393 struct aca_fw_info {
 394         const struct firmware *fw;
 395         const void *fw_data;
 396         size_t fw_len;
 397         struct aca_mem_layout mem_layout;
 398         struct aca_pdmem_layout pdmem_layout;
 399         struct aca_fw_param fw_param;
 400         struct aca_fw_dl_addr fw_dl;
 401         u32 chan_num;
 402         u32 adma_desc_base[ACA_DMA_CHAN_MAX];
 403 };
 404
 405 union fw_ver {
 406 #ifdef CONFIG_CPU_BIG_ENDIAN
 407         struct {
 408                 u32 build:4;
 409                 u32 branch:4;
 410                 u32 major:8;
 411                 u32 minor:16;
 412         } __packed field;
 413 #else
 414         struct {
 415                 u32 minor:16;
 416                 u32 major:8;
 417                 u32 branch:4;
 418                 u32 build:4;
 419         } __packed field;
 420 #endif /* CONFIG_CPU_BIG_ENDIAN */
 421         u32 all;
 422 } __packed;
 423
 424 union img_soc_type {
 425 #ifdef CONFIG_CPU_BIG_ENDIAN
 426         struct {
 427                 u32 img_type:16;
 428                 u32 soc_type:16;
 429         } __packed field;
 430 #else
 431         struct {
 432                 u32 soc_type:16;
 433                 u32 img_type:16;
 434         } __packed field;
 435 #endif /* CONFIG_CPU_BIG_ENDIAN */
 436         u32 all;
 437 } __packed;
 438
 439 /* Fixed header part */
 440 struct aca_fw_f_hdr {
 441         __be32 ver;
 442         __be32 type;
 443         __be32 hdr_size;
 444         __be32 fw_size;
 445         __be32 num_section;
 446 } __packed;
 447
 448 struct aca_hif_param {
 449         u32 soc_desc_base;
 450         u32 soc_desc_num;
 451         u32 pp_buf_base;
 452         u32 pp_buf_num;
 453         u32 pd_desc_base;
 454         u32 pd_desc_num;
 455         u32 pd_desc_threshold;
 456 } __packed;
 457
 458 struct aca_hif_params {
 459         u32 task_mask;
 460         struct aca_hif_param txin;
 461         struct aca_hif_param txout;
 462         struct aca_hif_param rxin;
 463         struct aca_hif_param rxout;
 464         u32 dbg_base;
 465         u32 dbg_size;
 466         u32 magic;
 467 } __packed;
 468
 469 #define ACA_MAGIC       0x25062016
 470
 471 struct dc_aca {
 472         bool initialized;
 473         spinlock_t      clk_lock;
 474         spinlock_t      rcu_lock;
 475         struct mutex    pin_lock;
 476         struct aca_fw_info fw_info;
 477         struct aca_hif_params *hif_params;
 478         u32 max_gpio;
 479         u32 adma_chans;
 480 };
 481 #endif /* ACA_H */