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uboot-envtools: add kirkwood board support
[openwrt/staging/chunkeey.git] / package / mac80211 / patches / 840-brcmsmac-backport.patch
1 --- a/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
2 +++ b/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
3 @@ -320,10 +320,6 @@
4 #define IS_SIM(chippkg) \
5 ((chippkg == HDLSIM_PKG_ID) || (chippkg == HWSIM_PKG_ID))
6
7 -#define PCIE(sih) (ai_get_buscoretype(sih) == PCIE_CORE_ID)
8 -
9 -#define PCI_FORCEHT(sih) (PCIE(sih) && (ai_get_chip_id(sih) == BCM4716_CHIP_ID))
10 -
11 #ifdef DEBUG
12 #define SI_MSG(fmt, ...) pr_debug(fmt, ##__VA_ARGS__)
13 #else
14 @@ -475,9 +471,6 @@ ai_buscore_setup(struct si_info *sii, st
15 sii->pub.pmurev = sii->pub.pmucaps & PCAP_REV_MASK;
16 }
17
18 - /* figure out buscore */
19 - sii->buscore = ai_findcore(&sii->pub, PCIE_CORE_ID, 0);
20 -
21 return true;
22 }
23
24 @@ -485,11 +478,7 @@ static struct si_info *ai_doattach(struc
25 struct bcma_bus *pbus)
26 {
27 struct si_pub *sih = &sii->pub;
28 - u32 w, savewin;
29 struct bcma_device *cc;
30 - struct ssb_sprom *sprom = &pbus->sprom;
31 -
32 - savewin = 0;
33
34 sii->icbus = pbus;
35 sii->pcibus = pbus->host_pci;
36 @@ -512,47 +501,7 @@ static struct si_info *ai_doattach(struc
37
38 /* PMU specific initializations */
39 if (ai_get_cccaps(sih) & CC_CAP_PMU) {
40 - si_pmu_init(sih);
41 (void)si_pmu_measure_alpclk(sih);
42 - si_pmu_res_init(sih);
43 - }
44 -
45 - /* setup the GPIO based LED powersave register */
46 - w = (sprom->leddc_on_time << BCMA_CC_GPIOTIMER_ONTIME_SHIFT) |
47 - (sprom->leddc_off_time << BCMA_CC_GPIOTIMER_OFFTIME_SHIFT);
48 - if (w == 0)
49 - w = DEFAULT_GPIOTIMERVAL;
50 - ai_cc_reg(sih, offsetof(struct chipcregs, gpiotimerval),
51 - ~0, w);
52 -
53 - if (ai_get_chip_id(sih) == BCM43224_CHIP_ID) {
54 - /*
55 - * enable 12 mA drive strenth for 43224 and
56 - * set chipControl register bit 15
57 - */
58 - if (ai_get_chiprev(sih) == 0) {
59 - SI_MSG("Applying 43224A0 WARs\n");
60 - ai_cc_reg(sih, offsetof(struct chipcregs, chipcontrol),
61 - CCTRL43224_GPIO_TOGGLE,
62 - CCTRL43224_GPIO_TOGGLE);
63 - si_pmu_chipcontrol(sih, 0, CCTRL_43224A0_12MA_LED_DRIVE,
64 - CCTRL_43224A0_12MA_LED_DRIVE);
65 - }
66 - if (ai_get_chiprev(sih) >= 1) {
67 - SI_MSG("Applying 43224B0+ WARs\n");
68 - si_pmu_chipcontrol(sih, 0, CCTRL_43224B0_12MA_LED_DRIVE,
69 - CCTRL_43224B0_12MA_LED_DRIVE);
70 - }
71 - }
72 -
73 - if (ai_get_chip_id(sih) == BCM4313_CHIP_ID) {
74 - /*
75 - * enable 12 mA drive strenth for 4313 and
76 - * set chipControl register bit 1
77 - */
78 - SI_MSG("Applying 4313 WARs\n");
79 - si_pmu_chipcontrol(sih, 0, CCTRL_4313_12MA_LED_DRIVE,
80 - CCTRL_4313_12MA_LED_DRIVE);
81 }
82
83 return sii;
84 @@ -591,7 +540,7 @@ void ai_detach(struct si_pub *sih)
85 struct si_pub *si_local = NULL;
86 memcpy(&si_local, &sih, sizeof(struct si_pub **));
87
88 - sii = (struct si_info *)sih;
89 + sii = container_of(sih, struct si_info, pub);
90
91 if (sii == NULL)
92 return;
93 @@ -599,27 +548,6 @@ void ai_detach(struct si_pub *sih)
94 kfree(sii);
95 }
96
97 -/* return index of coreid or BADIDX if not found */
98 -struct bcma_device *ai_findcore(struct si_pub *sih, u16 coreid, u16 coreunit)
99 -{
100 - struct bcma_device *core;
101 - struct si_info *sii;
102 - uint found;
103 -
104 - sii = (struct si_info *)sih;
105 -
106 - found = 0;
107 -
108 - list_for_each_entry(core, &sii->icbus->cores, list)
109 - if (core->id.id == coreid) {
110 - if (found == coreunit)
111 - return core;
112 - found++;
113 - }
114 -
115 - return NULL;
116 -}
117 -
118 /*
119 * read/modify chipcommon core register.
120 */
121 @@ -629,7 +557,7 @@ uint ai_cc_reg(struct si_pub *sih, uint
122 u32 w;
123 struct si_info *sii;
124
125 - sii = (struct si_info *)sih;
126 + sii = container_of(sih, struct si_info, pub);
127 cc = sii->icbus->drv_cc.core;
128
129 /* mask and set */
130 @@ -695,12 +623,13 @@ ai_clkctl_setdelay(struct si_pub *sih, s
131 /* initialize power control delay registers */
132 void ai_clkctl_init(struct si_pub *sih)
133 {
134 + struct si_info *sii = container_of(sih, struct si_info, pub);
135 struct bcma_device *cc;
136
137 if (!(ai_get_cccaps(sih) & CC_CAP_PWR_CTL))
138 return;
139
140 - cc = ai_findcore(sih, BCMA_CORE_CHIPCOMMON, 0);
141 + cc = sii->icbus->drv_cc.core;
142 if (cc == NULL)
143 return;
144
145 @@ -722,7 +651,7 @@ u16 ai_clkctl_fast_pwrup_delay(struct si
146 uint slowminfreq;
147 u16 fpdelay;
148
149 - sii = (struct si_info *)sih;
150 + sii = container_of(sih, struct si_info, pub);
151 if (ai_get_cccaps(sih) & CC_CAP_PMU) {
152 fpdelay = si_pmu_fast_pwrup_delay(sih);
153 return fpdelay;
154 @@ -732,7 +661,7 @@ u16 ai_clkctl_fast_pwrup_delay(struct si
155 return 0;
156
157 fpdelay = 0;
158 - cc = ai_findcore(sih, CC_CORE_ID, 0);
159 + cc = sii->icbus->drv_cc.core;
160 if (cc) {
161 slowminfreq = ai_slowclk_freq(sih, false, cc);
162 fpdelay = (((bcma_read32(cc, CHIPCREGOFFS(pll_on_delay)) + 2)
163 @@ -754,12 +683,9 @@ bool ai_clkctl_cc(struct si_pub *sih, en
164 struct si_info *sii;
165 struct bcma_device *cc;
166
167 - sii = (struct si_info *)sih;
168 -
169 - if (PCI_FORCEHT(sih))
170 - return mode == BCMA_CLKMODE_FAST;
171 + sii = container_of(sih, struct si_info, pub);
172
173 - cc = ai_findcore(&sii->pub, BCMA_CORE_CHIPCOMMON, 0);
174 + cc = sii->icbus->drv_cc.core;
175 bcma_core_set_clockmode(cc, mode);
176 return mode == BCMA_CLKMODE_FAST;
177 }
178 @@ -767,16 +693,10 @@ bool ai_clkctl_cc(struct si_pub *sih, en
179 void ai_pci_up(struct si_pub *sih)
180 {
181 struct si_info *sii;
182 - struct bcma_device *cc;
183
184 - sii = (struct si_info *)sih;
185 + sii = container_of(sih, struct si_info, pub);
186
187 - if (PCI_FORCEHT(sih)) {
188 - cc = ai_findcore(&sii->pub, BCMA_CORE_CHIPCOMMON, 0);
189 - bcma_core_set_clockmode(cc, BCMA_CLKMODE_FAST);
190 - }
191 -
192 - if (PCIE(sih))
193 + if (sii->icbus->hosttype == BCMA_HOSTTYPE_PCI)
194 bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci, true);
195 }
196
197 @@ -784,26 +704,20 @@ void ai_pci_up(struct si_pub *sih)
198 void ai_pci_down(struct si_pub *sih)
199 {
200 struct si_info *sii;
201 - struct bcma_device *cc;
202
203 - sii = (struct si_info *)sih;
204 + sii = container_of(sih, struct si_info, pub);
205
206 - /* release FORCEHT since chip is going to "down" state */
207 - if (PCI_FORCEHT(sih)) {
208 - cc = ai_findcore(&sii->pub, BCMA_CORE_CHIPCOMMON, 0);
209 - bcma_core_set_clockmode(cc, BCMA_CLKMODE_DYNAMIC);
210 - }
211 -
212 - if (PCIE(sih))
213 + if (sii->icbus->hosttype == BCMA_HOSTTYPE_PCI)
214 bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci, false);
215 }
216
217 /* Enable BT-COEX & Ex-PA for 4313 */
218 void ai_epa_4313war(struct si_pub *sih)
219 {
220 + struct si_info *sii = container_of(sih, struct si_info, pub);
221 struct bcma_device *cc;
222
223 - cc = ai_findcore(sih, CC_CORE_ID, 0);
224 + cc = sii->icbus->drv_cc.core;
225
226 /* EPA Fix */
227 bcma_set32(cc, CHIPCREGOFFS(gpiocontrol), GPIO_CTRL_EPA_EN_MASK);
228 @@ -815,7 +729,7 @@ bool ai_deviceremoved(struct si_pub *sih
229 u32 w;
230 struct si_info *sii;
231
232 - sii = (struct si_info *)sih;
233 + sii = container_of(sih, struct si_info, pub);
234
235 if (sii->icbus->hosttype != BCMA_HOSTTYPE_PCI)
236 return false;
237 @@ -826,15 +740,3 @@ bool ai_deviceremoved(struct si_pub *sih
238
239 return false;
240 }
241 -
242 -uint ai_get_buscoretype(struct si_pub *sih)
243 -{
244 - struct si_info *sii = (struct si_info *)sih;
245 - return sii->buscore->id.id;
246 -}
247 -
248 -uint ai_get_buscorerev(struct si_pub *sih)
249 -{
250 - struct si_info *sii = (struct si_info *)sih;
251 - return sii->buscore->id.rev;
252 -}
253 --- a/drivers/net/wireless/brcm80211/brcmsmac/aiutils.h
254 +++ b/drivers/net/wireless/brcm80211/brcmsmac/aiutils.h
255 @@ -88,16 +88,6 @@
256 #define CLKD_OTP 0x000f0000
257 #define CLKD_OTP_SHIFT 16
258
259 -/* Package IDs */
260 -#define BCM4717_PKG_ID 9 /* 4717 package id */
261 -#define BCM4718_PKG_ID 10 /* 4718 package id */
262 -#define BCM43224_FAB_SMIC 0xa /* the chip is manufactured by SMIC */
263 -
264 -/* these are router chips */
265 -#define BCM4716_CHIP_ID 0x4716 /* 4716 chipcommon chipid */
266 -#define BCM47162_CHIP_ID 47162 /* 47162 chipcommon chipid */
267 -#define BCM4748_CHIP_ID 0x4748 /* 4716 chipcommon chipid (OTP, RBBU) */
268 -
269 /* dynamic clock control defines */
270 #define LPOMINFREQ 25000 /* low power oscillator min */
271 #define LPOMAXFREQ 43000 /* low power oscillator max */
272 @@ -168,7 +158,6 @@ struct si_info {
273 struct si_pub pub; /* back plane public state (must be first) */
274 struct bcma_bus *icbus; /* handle to soc interconnect bus */
275 struct pci_dev *pcibus; /* handle to pci bus */
276 - struct bcma_device *buscore;
277
278 u32 chipst; /* chip status */
279 };
280 @@ -183,8 +172,6 @@ struct si_info {
281
282
283 /* AMBA Interconnect exported externs */
284 -extern struct bcma_device *ai_findcore(struct si_pub *sih,
285 - u16 coreid, u16 coreunit);
286 extern u32 ai_core_cflags(struct bcma_device *core, u32 mask, u32 val);
287
288 /* === exported functions === */
289 @@ -202,9 +189,6 @@ extern void ai_pci_up(struct si_pub *sih
290 /* Enable Ex-PA for 4313 */
291 extern void ai_epa_4313war(struct si_pub *sih);
292
293 -extern uint ai_get_buscoretype(struct si_pub *sih);
294 -extern uint ai_get_buscorerev(struct si_pub *sih);
295 -
296 static inline u32 ai_get_cccaps(struct si_pub *sih)
297 {
298 return sih->cccaps;
299 --- a/drivers/net/wireless/brcm80211/brcmsmac/dma.c
300 +++ b/drivers/net/wireless/brcm80211/brcmsmac/dma.c
301 @@ -574,6 +574,7 @@ struct dma_pub *dma_attach(char *name, s
302 struct dma_info *di;
303 u8 rev = core->id.rev;
304 uint size;
305 + struct si_info *sii = container_of(sih, struct si_info, pub);
306
307 /* allocate private info structure */
308 di = kzalloc(sizeof(struct dma_info), GFP_ATOMIC);
309 @@ -634,16 +635,20 @@ struct dma_pub *dma_attach(char *name, s
310 */
311 di->ddoffsetlow = 0;
312 di->dataoffsetlow = 0;
313 - /* add offset for pcie with DMA64 bus */
314 - di->ddoffsetlow = 0;
315 - di->ddoffsethigh = SI_PCIE_DMA_H32;
316 + /* for pci bus, add offset */
317 + if (sii->icbus->hosttype == BCMA_HOSTTYPE_PCI) {
318 + /* add offset for pcie with DMA64 bus */
319 + di->ddoffsetlow = 0;
320 + di->ddoffsethigh = SI_PCIE_DMA_H32;
321 + }
322 di->dataoffsetlow = di->ddoffsetlow;
323 di->dataoffsethigh = di->ddoffsethigh;
324 +
325 /* WAR64450 : DMACtl.Addr ext fields are not supported in SDIOD core. */
326 - if ((core->id.id == SDIOD_CORE_ID)
327 + if ((core->id.id == BCMA_CORE_SDIO_DEV)
328 && ((rev > 0) && (rev <= 2)))
329 di->addrext = false;
330 - else if ((core->id.id == I2S_CORE_ID) &&
331 + else if ((core->id.id == BCMA_CORE_I2S) &&
332 ((rev == 0) || (rev == 1)))
333 di->addrext = false;
334 else
335 --- a/drivers/net/wireless/brcm80211/brcmsmac/mac80211_if.c
336 +++ b/drivers/net/wireless/brcm80211/brcmsmac/mac80211_if.c
337 @@ -321,8 +321,7 @@ static void brcms_ops_stop(struct ieee80
338 return;
339
340 spin_lock_bh(&wl->lock);
341 - status = brcms_c_chipmatch(wl->wlc->hw->vendorid,
342 - wl->wlc->hw->deviceid);
343 + status = brcms_c_chipmatch(wl->wlc->hw->d11core);
344 spin_unlock_bh(&wl->lock);
345 if (!status) {
346 wiphy_err(wl->wiphy,
347 --- a/drivers/net/wireless/brcm80211/brcmsmac/main.c
348 +++ b/drivers/net/wireless/brcm80211/brcmsmac/main.c
349 @@ -271,7 +271,7 @@ struct brcms_c_bit_desc {
350 */
351
352 /* Starting corerev for the fifo size table */
353 -#define XMTFIFOTBL_STARTREV 20
354 +#define XMTFIFOTBL_STARTREV 17
355
356 struct d11init {
357 __le16 addr;
358 @@ -335,6 +335,12 @@ const u8 wlc_prio2prec_map[] = {
359 };
360
361 static const u16 xmtfifo_sz[][NFIFO] = {
362 + /* corerev 17: 5120, 49152, 49152, 5376, 4352, 1280 */
363 + {20, 192, 192, 21, 17, 5},
364 + /* corerev 18: */
365 + {0, 0, 0, 0, 0, 0},
366 + /* corerev 19: */
367 + {0, 0, 0, 0, 0, 0},
368 /* corerev 20: 5120, 49152, 49152, 5376, 4352, 1280 */
369 {20, 192, 192, 21, 17, 5},
370 /* corerev 21: 2304, 14848, 5632, 3584, 3584, 1280 */
371 @@ -345,6 +351,14 @@ static const u16 xmtfifo_sz[][NFIFO] = {
372 {20, 192, 192, 21, 17, 5},
373 /* corerev 24: 2304, 14848, 5632, 3584, 3584, 1280 */
374 {9, 58, 22, 14, 14, 5},
375 + /* corerev 25: */
376 + {0, 0, 0, 0, 0, 0},
377 + /* corerev 26: */
378 + {0, 0, 0, 0, 0, 0},
379 + /* corerev 27: */
380 + {0, 0, 0, 0, 0, 0},
381 + /* corerev 28: 2304, 14848, 5632, 3584, 3584, 1280 */
382 + {9, 58, 22, 14, 14, 5},
383 };
384
385 #ifdef DEBUG
386 @@ -1944,7 +1958,8 @@ static bool brcms_b_radio_read_hwdisable
387 * accesses phyreg throughput mac. This can be skipped since
388 * only mac reg is accessed below
389 */
390 - flags |= SICF_PCLKE;
391 + if (D11REV_GE(wlc_hw->corerev, 18))
392 + flags |= SICF_PCLKE;
393
394 /*
395 * TODO: test suspend/resume
396 @@ -2025,7 +2040,8 @@ void brcms_b_corereset(struct brcms_hard
397 * phyreg throughput mac, AND phy_reset is skipped at early stage when
398 * band->pi is invalid. need to enable PHY CLK
399 */
400 - flags |= SICF_PCLKE;
401 + if (D11REV_GE(wlc_hw->corerev, 18))
402 + flags |= SICF_PCLKE;
403
404 /*
405 * reset the core
406 @@ -2128,8 +2144,8 @@ void brcms_b_switch_macfreq(struct brcms
407 {
408 struct bcma_device *core = wlc_hw->d11core;
409
410 - if ((ai_get_chip_id(wlc_hw->sih) == BCM43224_CHIP_ID) ||
411 - (ai_get_chip_id(wlc_hw->sih) == BCM43225_CHIP_ID)) {
412 + if ((ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM43224) ||
413 + (ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM43225)) {
414 if (spurmode == WL_SPURAVOID_ON2) { /* 126Mhz */
415 bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x2082);
416 bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8);
417 @@ -2793,7 +2809,7 @@ void brcms_b_core_phypll_ctl(struct brcm
418 tmp = 0;
419
420 if (on) {
421 - if ((ai_get_chip_id(wlc_hw->sih) == BCM4313_CHIP_ID)) {
422 + if ((ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM4313)) {
423 bcma_set32(core, D11REGOFFS(clk_ctl_st),
424 CCS_ERSRC_REQ_HT |
425 CCS_ERSRC_REQ_D11PLL |
426 @@ -4220,9 +4236,8 @@ static void brcms_c_radio_timer(void *ar
427 }
428
429 /* common low-level watchdog code */
430 -static void brcms_b_watchdog(void *arg)
431 +static void brcms_b_watchdog(struct brcms_c_info *wlc)
432 {
433 - struct brcms_c_info *wlc = (struct brcms_c_info *) arg;
434 struct brcms_hardware *wlc_hw = wlc->hw;
435
436 BCMMSG(wlc->wiphy, "wl%d\n", wlc_hw->unit);
437 @@ -4243,10 +4258,8 @@ static void brcms_b_watchdog(void *arg)
438 }
439
440 /* common watchdog code */
441 -static void brcms_c_watchdog(void *arg)
442 +static void brcms_c_watchdog(struct brcms_c_info *wlc)
443 {
444 - struct brcms_c_info *wlc = (struct brcms_c_info *) arg;
445 -
446 BCMMSG(wlc->wiphy, "wl%d\n", wlc->pub->unit);
447
448 if (!wlc->pub->up)
449 @@ -4286,7 +4299,9 @@ static void brcms_c_watchdog(void *arg)
450
451 static void brcms_c_watchdog_by_timer(void *arg)
452 {
453 - brcms_c_watchdog(arg);
454 + struct brcms_c_info *wlc = (struct brcms_c_info *) arg;
455 +
456 + brcms_c_watchdog(wlc);
457 }
458
459 static bool brcms_c_timers_init(struct brcms_c_info *wlc, int unit)
460 @@ -4456,11 +4471,9 @@ static int brcms_b_attach(struct brcms_c
461 }
462
463 /* verify again the device is supported */
464 - if (core->bus->hosttype == BCMA_HOSTTYPE_PCI &&
465 - !brcms_c_chipmatch(pcidev->vendor, pcidev->device)) {
466 - wiphy_err(wiphy, "wl%d: brcms_b_attach: Unsupported "
467 - "vendor/device (0x%x/0x%x)\n",
468 - unit, pcidev->vendor, pcidev->device);
469 + if (!brcms_c_chipmatch(core)) {
470 + wiphy_err(wiphy, "wl%d: brcms_b_attach: Unsupported device\n",
471 + unit);
472 err = 12;
473 goto fail;
474 }
475 @@ -4530,7 +4543,7 @@ static int brcms_b_attach(struct brcms_c
476 else
477 wlc_hw->_nbands = 1;
478
479 - if ((ai_get_chip_id(wlc_hw->sih) == BCM43225_CHIP_ID))
480 + if ((ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM43225))
481 wlc_hw->_nbands = 1;
482
483 /* BMAC_NOTE: remove init of pub values when brcms_c_attach()
484 @@ -4597,8 +4610,12 @@ static int brcms_b_attach(struct brcms_c
485 wlc_hw->machwcap_backup = wlc_hw->machwcap;
486
487 /* init tx fifo size */
488 + WARN_ON((wlc_hw->corerev - XMTFIFOTBL_STARTREV) < 0 ||
489 + (wlc_hw->corerev - XMTFIFOTBL_STARTREV) >
490 + ARRAY_SIZE(xmtfifo_sz));
491 wlc_hw->xmtfifo_sz =
492 xmtfifo_sz[(wlc_hw->corerev - XMTFIFOTBL_STARTREV)];
493 + WARN_ON(!wlc_hw->xmtfifo_sz[0]);
494
495 /* Get a phy for this band */
496 wlc_hw->band->pi =
497 @@ -5038,7 +5055,7 @@ static void brcms_b_hw_up(struct brcms_h
498 wlc_hw->wlc->pub->hw_up = true;
499
500 if ((wlc_hw->boardflags & BFL_FEM)
501 - && (ai_get_chip_id(wlc_hw->sih) == BCM4313_CHIP_ID)) {
502 + && (ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM4313)) {
503 if (!
504 (wlc_hw->boardrev >= 0x1250
505 && (wlc_hw->boardflags & BFL_FEM_BT)))
506 @@ -5132,7 +5149,7 @@ int brcms_c_up(struct brcms_c_info *wlc)
507 }
508
509 if ((wlc->pub->boardflags & BFL_FEM)
510 - && (ai_get_chip_id(wlc->hw->sih) == BCM4313_CHIP_ID)) {
511 + && (ai_get_chip_id(wlc->hw->sih) == BCMA_CHIP_ID_BCM4313)) {
512 if (wlc->pub->boardrev >= 0x1250
513 && (wlc->pub->boardflags & BFL_FEM_BT))
514 brcms_b_mhf(wlc->hw, MHF5, MHF5_4313_GPIOCTRL,
515 @@ -5769,8 +5786,12 @@ void brcms_c_print_txstatus(struct tx_st
516 (txs->ackphyrxsh & PRXS1_SQ_MASK) >> PRXS1_SQ_SHIFT);
517 }
518
519 -bool brcms_c_chipmatch(u16 vendor, u16 device)
520 +static bool brcms_c_chipmatch_pci(struct bcma_device *core)
521 {
522 + struct pci_dev *pcidev = core->bus->host_pci;
523 + u16 vendor = pcidev->vendor;
524 + u16 device = pcidev->device;
525 +
526 if (vendor != PCI_VENDOR_ID_BROADCOM) {
527 pr_err("unknown vendor id %04x\n", vendor);
528 return false;
529 @@ -5789,6 +5810,30 @@ bool brcms_c_chipmatch(u16 vendor, u16 d
530 return false;
531 }
532
533 +static bool brcms_c_chipmatch_soc(struct bcma_device *core)
534 +{
535 + struct bcma_chipinfo *chipinfo = &core->bus->chipinfo;
536 +
537 + if (chipinfo->id == BCMA_CHIP_ID_BCM4716)
538 + return true;
539 +
540 + pr_err("unknown chip id %04x\n", chipinfo->id);
541 + return false;
542 +}
543 +
544 +bool brcms_c_chipmatch(struct bcma_device *core)
545 +{
546 + switch (core->bus->hosttype) {
547 + case BCMA_HOSTTYPE_PCI:
548 + return brcms_c_chipmatch_pci(core);
549 + case BCMA_HOSTTYPE_SOC:
550 + return brcms_c_chipmatch_soc(core);
551 + default:
552 + pr_err("unknown host type: %i\n", core->bus->hosttype);
553 + return false;
554 + }
555 +}
556 +
557 #if defined(DEBUG)
558 void brcms_c_print_txdesc(struct d11txh *txh)
559 {
560 --- a/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_cmn.c
561 +++ b/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_cmn.c
562 @@ -198,6 +198,8 @@ u16 read_radio_reg(struct brcms_phy *pi,
563
564 void write_radio_reg(struct brcms_phy *pi, u16 addr, u16 val)
565 {
566 + struct si_info *sii = container_of(pi->sh->sih, struct si_info, pub);
567 +
568 if ((D11REV_GE(pi->sh->corerev, 24)) ||
569 (D11REV_IS(pi->sh->corerev, 22)
570 && (pi->pubpi.phy_type != PHY_TYPE_SSN))) {
571 @@ -209,7 +211,8 @@ void write_radio_reg(struct brcms_phy *p
572 bcma_write16(pi->d11core, D11REGOFFS(phy4wdatalo), val);
573 }
574
575 - if (++pi->phy_wreg >= pi->phy_wreg_limit) {
576 + if ((sii->icbus->hosttype == BCMA_HOSTTYPE_PCI) &&
577 + (++pi->phy_wreg >= pi->phy_wreg_limit)) {
578 (void)bcma_read32(pi->d11core, D11REGOFFS(maccontrol));
579 pi->phy_wreg = 0;
580 }
581 @@ -292,10 +295,13 @@ void write_phy_reg(struct brcms_phy *pi,
582 bcma_wflush16(pi->d11core, D11REGOFFS(phyregaddr), addr);
583 bcma_write16(pi->d11core, D11REGOFFS(phyregdata), val);
584 if (addr == 0x72)
585 - (void)bcma_read16(pi->d11core, D11REGOFFS(phyversion));
586 + (void)bcma_read16(pi->d11core, D11REGOFFS(phyregdata));
587 #else
588 + struct si_info *sii = container_of(pi->sh->sih, struct si_info, pub);
589 +
590 bcma_write32(pi->d11core, D11REGOFFS(phyregaddr), addr | (val << 16));
591 - if (++pi->phy_wreg >= pi->phy_wreg_limit) {
592 + if ((sii->icbus->hosttype == BCMA_HOSTTYPE_PCI) &&
593 + (++pi->phy_wreg >= pi->phy_wreg_limit)) {
594 pi->phy_wreg = 0;
595 (void)bcma_read16(pi->d11core, D11REGOFFS(phyversion));
596 }
597 @@ -837,7 +843,7 @@ wlc_phy_table_addr(struct brcms_phy *pi,
598 pi->tbl_data_hi = tblDataHi;
599 pi->tbl_data_lo = tblDataLo;
600
601 - if (pi->sh->chip == BCM43224_CHIP_ID &&
602 + if (pi->sh->chip == BCMA_CHIP_ID_BCM43224 &&
603 pi->sh->chiprev == 1) {
604 pi->tbl_addr = tblAddr;
605 pi->tbl_save_id = tbl_id;
606 @@ -847,7 +853,7 @@ wlc_phy_table_addr(struct brcms_phy *pi,
607
608 void wlc_phy_table_data_write(struct brcms_phy *pi, uint width, u32 val)
609 {
610 - if ((pi->sh->chip == BCM43224_CHIP_ID) &&
611 + if ((pi->sh->chip == BCMA_CHIP_ID_BCM43224) &&
612 (pi->sh->chiprev == 1) &&
613 (pi->tbl_save_id == NPHY_TBL_ID_ANTSWCTRLLUT)) {
614 read_phy_reg(pi, pi->tbl_data_lo);
615 @@ -881,7 +887,7 @@ wlc_phy_write_table(struct brcms_phy *pi
616
617 for (idx = 0; idx < ptbl_info->tbl_len; idx++) {
618
619 - if ((pi->sh->chip == BCM43224_CHIP_ID) &&
620 + if ((pi->sh->chip == BCMA_CHIP_ID_BCM43224) &&
621 (pi->sh->chiprev == 1) &&
622 (tbl_id == NPHY_TBL_ID_ANTSWCTRLLUT)) {
623 read_phy_reg(pi, tblDataLo);
624 @@ -918,7 +924,7 @@ wlc_phy_read_table(struct brcms_phy *pi,
625
626 for (idx = 0; idx < ptbl_info->tbl_len; idx++) {
627
628 - if ((pi->sh->chip == BCM43224_CHIP_ID) &&
629 + if ((pi->sh->chip == BCMA_CHIP_ID_BCM43224) &&
630 (pi->sh->chiprev == 1)) {
631 (void)read_phy_reg(pi, tblDataLo);
632
633 @@ -2894,7 +2900,7 @@ const u8 *wlc_phy_get_ofdm_rate_lookup(v
634
635 void wlc_lcnphy_epa_switch(struct brcms_phy *pi, bool mode)
636 {
637 - if ((pi->sh->chip == BCM4313_CHIP_ID) &&
638 + if ((pi->sh->chip == BCMA_CHIP_ID_BCM4313) &&
639 (pi->sh->boardflags & BFL_FEM)) {
640 if (mode) {
641 u16 txant = 0;
642 --- a/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_n.c
643 +++ b/drivers/net/wireless/brcm80211/brcmsmac/phy/phy_n.c
644 @@ -17895,6 +17895,8 @@ static u32 *wlc_phy_get_ipa_gaintbl_nphy
645 nphy_tpc_txgain_ipa_2g_2057rev7;
646 } else if (NREV_IS(pi->pubpi.phy_rev, 6)) {
647 tx_pwrctrl_tbl = nphy_tpc_txgain_ipa_rev6;
648 + if (pi->sh->chip == BCMA_CHIP_ID_BCM47162)
649 + tx_pwrctrl_tbl = nphy_tpc_txgain_ipa_rev5;
650 } else if (NREV_IS(pi->pubpi.phy_rev, 5)) {
651 tx_pwrctrl_tbl = nphy_tpc_txgain_ipa_rev5;
652 } else {
653 @@ -19256,8 +19258,14 @@ static void wlc_phy_spurwar_nphy(struct
654 case 38:
655 case 102:
656 case 118:
657 - nphy_adj_tone_id_buf[0] = 0;
658 - nphy_adj_noise_var_buf[0] = 0x0;
659 + if ((pi->sh->chip == BCMA_CHIP_ID_BCM4716) &&
660 + (pi->sh->chippkg == BCMA_PKG_ID_BCM4717)) {
661 + nphy_adj_tone_id_buf[0] = 32;
662 + nphy_adj_noise_var_buf[0] = 0x21f;
663 + } else {
664 + nphy_adj_tone_id_buf[0] = 0;
665 + nphy_adj_noise_var_buf[0] = 0x0;
666 + }
667 break;
668 case 134:
669 nphy_adj_tone_id_buf[0] = 32;
670 @@ -19311,8 +19319,8 @@ void wlc_phy_init_nphy(struct brcms_phy
671 pi->measure_hold |= PHY_HOLD_FOR_NOT_ASSOC;
672
673 if ((ISNPHY(pi)) && (NREV_GE(pi->pubpi.phy_rev, 5)) &&
674 - ((pi->sh->chippkg == BCM4717_PKG_ID) ||
675 - (pi->sh->chippkg == BCM4718_PKG_ID))) {
676 + ((pi->sh->chippkg == BCMA_PKG_ID_BCM4717) ||
677 + (pi->sh->chippkg == BCMA_PKG_ID_BCM4718))) {
678 if ((pi->sh->boardflags & BFL_EXTLNA) &&
679 (CHSPEC_IS2G(pi->radio_chanspec)))
680 ai_cc_reg(pi->sh->sih,
681 @@ -19320,6 +19328,10 @@ void wlc_phy_init_nphy(struct brcms_phy
682 0x40, 0x40);
683 }
684
685 + if ((!PHY_IPA(pi)) && (pi->sh->chip == BCMA_CHIP_ID_BCM5357))
686 + si_pmu_chipcontrol(pi->sh->sih, 1, CCTRL5357_EXTPA,
687 + CCTRL5357_EXTPA);
688 +
689 if ((pi->nphy_gband_spurwar2_en) && CHSPEC_IS2G(pi->radio_chanspec) &&
690 CHSPEC_IS40(pi->radio_chanspec)) {
691
692 @@ -20697,12 +20709,22 @@ wlc_phy_chanspec_radio2056_setup(struct
693 write_radio_reg(pi, RADIO_2056_SYN_PLL_LOOPFILTER2 |
694 RADIO_2056_SYN, 0x1f);
695
696 - write_radio_reg(pi,
697 - RADIO_2056_SYN_PLL_LOOPFILTER4 |
698 - RADIO_2056_SYN, 0xb);
699 - write_radio_reg(pi,
700 - RADIO_2056_SYN_PLL_CP2 |
701 - RADIO_2056_SYN, 0x14);
702 + if ((pi->sh->chip == BCMA_CHIP_ID_BCM4716) ||
703 + (pi->sh->chip == BCMA_CHIP_ID_BCM47162)) {
704 + write_radio_reg(pi,
705 + RADIO_2056_SYN_PLL_LOOPFILTER4 |
706 + RADIO_2056_SYN, 0x14);
707 + write_radio_reg(pi,
708 + RADIO_2056_SYN_PLL_CP2 |
709 + RADIO_2056_SYN, 0x00);
710 + } else {
711 + write_radio_reg(pi,
712 + RADIO_2056_SYN_PLL_LOOPFILTER4 |
713 + RADIO_2056_SYN, 0xb);
714 + write_radio_reg(pi,
715 + RADIO_2056_SYN_PLL_CP2 |
716 + RADIO_2056_SYN, 0x14);
717 + }
718 }
719 }
720
721 @@ -20749,24 +20771,30 @@ wlc_phy_chanspec_radio2056_setup(struct
722 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
723 PADG_IDAC, 0xcc);
724
725 - bias = 0x25;
726 - cascbias = 0x20;
727 + if ((pi->sh->chip == BCMA_CHIP_ID_BCM4716) ||
728 + (pi->sh->chip == BCMA_CHIP_ID_BCM47162)) {
729 + bias = 0x40;
730 + cascbias = 0x45;
731 + pag_boost_tune = 0x5;
732 + pgag_boost_tune = 0x33;
733 + padg_boost_tune = 0x77;
734 + mixg_boost_tune = 0x55;
735 + } else {
736 + bias = 0x25;
737 + cascbias = 0x20;
738
739 - if ((pi->sh->chip ==
740 - BCM43224_CHIP_ID)
741 - || (pi->sh->chip ==
742 - BCM43225_CHIP_ID)) {
743 - if (pi->sh->chippkg ==
744 - BCM43224_FAB_SMIC) {
745 + if ((pi->sh->chip == BCMA_CHIP_ID_BCM43224 ||
746 + pi->sh->chip == BCMA_CHIP_ID_BCM43225) &&
747 + pi->sh->chippkg == BCMA_PKG_ID_BCM43224_FAB_SMIC) {
748 bias = 0x2a;
749 cascbias = 0x38;
750 }
751 - }
752
753 - pag_boost_tune = 0x4;
754 - pgag_boost_tune = 0x03;
755 - padg_boost_tune = 0x77;
756 - mixg_boost_tune = 0x65;
757 + pag_boost_tune = 0x4;
758 + pgag_boost_tune = 0x03;
759 + padg_boost_tune = 0x77;
760 + mixg_boost_tune = 0x65;
761 + }
762
763 WRITE_RADIO_REG2(pi, RADIO_2056, TX, core,
764 INTPAG_IMAIN_STAT, bias);
765 @@ -20865,11 +20893,10 @@ wlc_phy_chanspec_radio2056_setup(struct
766
767 cascbias = 0x30;
768
769 - if ((pi->sh->chip == BCM43224_CHIP_ID) ||
770 - (pi->sh->chip == BCM43225_CHIP_ID)) {
771 - if (pi->sh->chippkg == BCM43224_FAB_SMIC)
772 - cascbias = 0x35;
773 - }
774 + if ((pi->sh->chip == BCMA_CHIP_ID_BCM43224 ||
775 + pi->sh->chip == BCMA_CHIP_ID_BCM43225) &&
776 + pi->sh->chippkg == BCMA_PKG_ID_BCM43224_FAB_SMIC)
777 + cascbias = 0x35;
778
779 pabias = (pi->phy_pabias == 0) ? 0x30 : pi->phy_pabias;
780
781 @@ -21108,6 +21135,7 @@ wlc_phy_chanspec_nphy_setup(struct brcms
782 const struct nphy_sfo_cfg *ci)
783 {
784 u16 val;
785 + struct si_info *sii = container_of(pi->sh->sih, struct si_info, pub);
786
787 val = read_phy_reg(pi, 0x09) & NPHY_BandControl_currentBand;
788 if (CHSPEC_IS5G(chanspec) && !val) {
789 @@ -21180,22 +21208,32 @@ wlc_phy_chanspec_nphy_setup(struct brcms
790 } else if (NREV_GE(pi->pubpi.phy_rev, 7)) {
791 if (val == 54)
792 spuravoid = 1;
793 - } else {
794 - if (pi->nphy_aband_spurwar_en &&
795 - ((val == 38) || (val == 102)
796 - || (val == 118)))
797 + } else if (pi->nphy_aband_spurwar_en &&
798 + ((val == 38) || (val == 102) || (val == 118))) {
799 + if ((pi->sh->chip == BCMA_CHIP_ID_BCM4716)
800 + && (pi->sh->chippkg == BCMA_PKG_ID_BCM4717)) {
801 + spuravoid = 0;
802 + } else {
803 spuravoid = 1;
804 + }
805 }
806
807 if (pi->phy_spuravoid == SPURAVOID_FORCEON)
808 spuravoid = 1;
809
810 - wlapi_bmac_core_phypll_ctl(pi->sh->physhim, false);
811 - si_pmu_spuravoid_pllupdate(pi->sh->sih, spuravoid);
812 - wlapi_bmac_core_phypll_ctl(pi->sh->physhim, true);
813 + if ((pi->sh->chip == BCMA_CHIP_ID_BCM4716) ||
814 + (pi->sh->chip == BCMA_CHIP_ID_BCM43225)) {
815 + bcma_pmu_spuravoid_pllupdate(&sii->icbus->drv_cc,
816 + spuravoid);
817 + } else {
818 + wlapi_bmac_core_phypll_ctl(pi->sh->physhim, false);
819 + bcma_pmu_spuravoid_pllupdate(&sii->icbus->drv_cc,
820 + spuravoid);
821 + wlapi_bmac_core_phypll_ctl(pi->sh->physhim, true);
822 + }
823
824 - if ((pi->sh->chip == BCM43224_CHIP_ID) ||
825 - (pi->sh->chip == BCM43225_CHIP_ID)) {
826 + if ((pi->sh->chip == BCMA_CHIP_ID_BCM43224) ||
827 + (pi->sh->chip == BCMA_CHIP_ID_BCM43225)) {
828 if (spuravoid == 1) {
829 bcma_write16(pi->d11core,
830 D11REGOFFS(tsf_clk_frac_l),
831 @@ -21211,7 +21249,9 @@ wlc_phy_chanspec_nphy_setup(struct brcms
832 }
833 }
834
835 - wlapi_bmac_core_phypll_reset(pi->sh->physhim);
836 + if (!((pi->sh->chip == BCMA_CHIP_ID_BCM4716) ||
837 + (pi->sh->chip == BCMA_CHIP_ID_BCM47162)))
838 + wlapi_bmac_core_phypll_reset(pi->sh->physhim);
839
840 mod_phy_reg(pi, 0x01, (0x1 << 15),
841 ((spuravoid > 0) ? (0x1 << 15) : 0));
842 @@ -22173,9 +22213,15 @@ s16 wlc_phy_tempsense_nphy(struct brcms_
843 wlc_phy_table_write_nphy(pi, NPHY_TBL_ID_AFECTRL, 1, 0x03, 16,
844 &auxADC_rssi_ctrlH_save);
845
846 - radio_temp[0] = (179 * (radio_temp[1] + radio_temp2[1])
847 - + 82 * (auxADC_Vl) - 28861 +
848 - 128) / 256;
849 + if (pi->sh->chip == BCMA_CHIP_ID_BCM5357) {
850 + radio_temp[0] = (193 * (radio_temp[1] + radio_temp2[1])
851 + + 88 * (auxADC_Vl) - 27111 +
852 + 128) / 256;
853 + } else {
854 + radio_temp[0] = (179 * (radio_temp[1] + radio_temp2[1])
855 + + 82 * (auxADC_Vl) - 28861 +
856 + 128) / 256;
857 + }
858
859 offset = (s16) pi->phy_tempsense_offset;
860
861 @@ -24925,14 +24971,16 @@ wlc_phy_a2_nphy(struct brcms_phy *pi, st
862 if (txgains->useindex) {
863 phy_a4 = 15 - ((txgains->index) >> 3);
864 if (CHSPEC_IS2G(pi->radio_chanspec)) {
865 - if (NREV_GE(pi->pubpi.phy_rev, 6))
866 + if (NREV_GE(pi->pubpi.phy_rev, 6) &&
867 + pi->sh->chip == BCMA_CHIP_ID_BCM47162) {
868 + phy_a5 = 0x10f7 | (phy_a4 << 8);
869 + } else if (NREV_GE(pi->pubpi.phy_rev, 6)) {
870 phy_a5 = 0x00f7 | (phy_a4 << 8);
871 -
872 - else
873 - if (NREV_IS(pi->pubpi.phy_rev, 5))
874 + } else if (NREV_IS(pi->pubpi.phy_rev, 5)) {
875 phy_a5 = 0x10f7 | (phy_a4 << 8);
876 - else
877 + } else {
878 phy_a5 = 0x50f7 | (phy_a4 << 8);
879 + }
880 } else {
881 phy_a5 = 0x70f7 | (phy_a4 << 8);
882 }
883 --- a/drivers/net/wireless/brcm80211/brcmsmac/pmu.c
884 +++ b/drivers/net/wireless/brcm80211/brcmsmac/pmu.c
885 @@ -74,16 +74,6 @@
886 * PMU<rev>_PLL<num>_XX where <rev> is PMU corerev and <num> is an arbitrary
887 * number to differentiate different PLLs controlled by the same PMU rev.
888 */
889 -/* pllcontrol registers:
890 - * ndiv_pwrdn, pwrdn_ch<x>, refcomp_pwrdn, dly_ch<x>,
891 - * p1div, p2div, _bypass_sdmod
892 - */
893 -#define PMU1_PLL0_PLLCTL0 0
894 -#define PMU1_PLL0_PLLCTL1 1
895 -#define PMU1_PLL0_PLLCTL2 2
896 -#define PMU1_PLL0_PLLCTL3 3
897 -#define PMU1_PLL0_PLLCTL4 4
898 -#define PMU1_PLL0_PLLCTL5 5
899
900 /* pmu XtalFreqRatio */
901 #define PMU_XTALFREQ_REG_ILPCTR_MASK 0x00001FFF
902 @@ -108,118 +98,14 @@
903 #define RES4313_HT_AVAIL_RSRC 14
904 #define RES4313_MACPHY_CLK_AVAIL_RSRC 15
905
906 -/* Determine min/max rsrc masks. Value 0 leaves hardware at default. */
907 -static void si_pmu_res_masks(struct si_pub *sih, u32 * pmin, u32 * pmax)
908 -{
909 - u32 min_mask = 0, max_mask = 0;
910 - uint rsrcs;
911 -
912 - /* # resources */
913 - rsrcs = (ai_get_pmucaps(sih) & PCAP_RC_MASK) >> PCAP_RC_SHIFT;
914 -
915 - /* determine min/max rsrc masks */
916 - switch (ai_get_chip_id(sih)) {
917 - case BCM43224_CHIP_ID:
918 - case BCM43225_CHIP_ID:
919 - /* ??? */
920 - break;
921 -
922 - case BCM4313_CHIP_ID:
923 - min_mask = PMURES_BIT(RES4313_BB_PU_RSRC) |
924 - PMURES_BIT(RES4313_XTAL_PU_RSRC) |
925 - PMURES_BIT(RES4313_ALP_AVAIL_RSRC) |
926 - PMURES_BIT(RES4313_BB_PLL_PWRSW_RSRC);
927 - max_mask = 0xffff;
928 - break;
929 - default:
930 - break;
931 - }
932 -
933 - *pmin = min_mask;
934 - *pmax = max_mask;
935 -}
936 -
937 -void si_pmu_spuravoid_pllupdate(struct si_pub *sih, u8 spuravoid)
938 -{
939 - u32 tmp = 0;
940 - struct bcma_device *core;
941 -
942 - /* switch to chipc */
943 - core = ai_findcore(sih, BCMA_CORE_CHIPCOMMON, 0);
944 -
945 - switch (ai_get_chip_id(sih)) {
946 - case BCM43224_CHIP_ID:
947 - case BCM43225_CHIP_ID:
948 - if (spuravoid == 1) {
949 - bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
950 - PMU1_PLL0_PLLCTL0);
951 - bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
952 - 0x11500010);
953 - bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
954 - PMU1_PLL0_PLLCTL1);
955 - bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
956 - 0x000C0C06);
957 - bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
958 - PMU1_PLL0_PLLCTL2);
959 - bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
960 - 0x0F600a08);
961 - bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
962 - PMU1_PLL0_PLLCTL3);
963 - bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
964 - 0x00000000);
965 - bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
966 - PMU1_PLL0_PLLCTL4);
967 - bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
968 - 0x2001E920);
969 - bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
970 - PMU1_PLL0_PLLCTL5);
971 - bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
972 - 0x88888815);
973 - } else {
974 - bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
975 - PMU1_PLL0_PLLCTL0);
976 - bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
977 - 0x11100010);
978 - bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
979 - PMU1_PLL0_PLLCTL1);
980 - bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
981 - 0x000c0c06);
982 - bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
983 - PMU1_PLL0_PLLCTL2);
984 - bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
985 - 0x03000a08);
986 - bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
987 - PMU1_PLL0_PLLCTL3);
988 - bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
989 - 0x00000000);
990 - bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
991 - PMU1_PLL0_PLLCTL4);
992 - bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
993 - 0x200005c0);
994 - bcma_write32(core, CHIPCREGOFFS(pllcontrol_addr),
995 - PMU1_PLL0_PLLCTL5);
996 - bcma_write32(core, CHIPCREGOFFS(pllcontrol_data),
997 - 0x88888815);
998 - }
999 - tmp = 1 << 10;
1000 - break;
1001 -
1002 - default:
1003 - /* bail out */
1004 - return;
1005 - }
1006 -
1007 - bcma_set32(core, CHIPCREGOFFS(pmucontrol), tmp);
1008 -}
1009 -
1010 u16 si_pmu_fast_pwrup_delay(struct si_pub *sih)
1011 {
1012 uint delay = PMU_MAX_TRANSITION_DLY;
1013
1014 switch (ai_get_chip_id(sih)) {
1015 - case BCM43224_CHIP_ID:
1016 - case BCM43225_CHIP_ID:
1017 - case BCM4313_CHIP_ID:
1018 + case BCMA_CHIP_ID_BCM43224:
1019 + case BCMA_CHIP_ID_BCM43225:
1020 + case BCMA_CHIP_ID_BCM4313:
1021 delay = 3700;
1022 break;
1023 default:
1024 @@ -270,9 +156,9 @@ u32 si_pmu_alp_clock(struct si_pub *sih)
1025 return clock;
1026
1027 switch (ai_get_chip_id(sih)) {
1028 - case BCM43224_CHIP_ID:
1029 - case BCM43225_CHIP_ID:
1030 - case BCM4313_CHIP_ID:
1031 + case BCMA_CHIP_ID_BCM43224:
1032 + case BCMA_CHIP_ID_BCM43225:
1033 + case BCMA_CHIP_ID_BCM4313:
1034 /* always 20Mhz */
1035 clock = 20000 * 1000;
1036 break;
1037 @@ -283,51 +169,9 @@ u32 si_pmu_alp_clock(struct si_pub *sih)
1038 return clock;
1039 }
1040
1041 -/* initialize PMU */
1042 -void si_pmu_init(struct si_pub *sih)
1043 -{
1044 - struct bcma_device *core;
1045 -
1046 - /* select chipc */
1047 - core = ai_findcore(sih, BCMA_CORE_CHIPCOMMON, 0);
1048 -
1049 - if (ai_get_pmurev(sih) == 1)
1050 - bcma_mask32(core, CHIPCREGOFFS(pmucontrol),
1051 - ~PCTL_NOILP_ON_WAIT);
1052 - else if (ai_get_pmurev(sih) >= 2)
1053 - bcma_set32(core, CHIPCREGOFFS(pmucontrol), PCTL_NOILP_ON_WAIT);
1054 -}
1055 -
1056 -/* initialize PMU resources */
1057 -void si_pmu_res_init(struct si_pub *sih)
1058 -{
1059 - struct bcma_device *core;
1060 - u32 min_mask = 0, max_mask = 0;
1061 -
1062 - /* select to chipc */
1063 - core = ai_findcore(sih, BCMA_CORE_CHIPCOMMON, 0);
1064 -
1065 - /* Determine min/max rsrc masks */
1066 - si_pmu_res_masks(sih, &min_mask, &max_mask);
1067 -
1068 - /* It is required to program max_mask first and then min_mask */
1069 -
1070 - /* Program max resource mask */
1071 -
1072 - if (max_mask)
1073 - bcma_write32(core, CHIPCREGOFFS(max_res_mask), max_mask);
1074 -
1075 - /* Program min resource mask */
1076 -
1077 - if (min_mask)
1078 - bcma_write32(core, CHIPCREGOFFS(min_res_mask), min_mask);
1079 -
1080 - /* Add some delay; allow resources to come up and settle. */
1081 - mdelay(2);
1082 -}
1083 -
1084 u32 si_pmu_measure_alpclk(struct si_pub *sih)
1085 {
1086 + struct si_info *sii = container_of(sih, struct si_info, pub);
1087 struct bcma_device *core;
1088 u32 alp_khz;
1089
1090 @@ -335,7 +179,7 @@ u32 si_pmu_measure_alpclk(struct si_pub
1091 return 0;
1092
1093 /* Remember original core before switch to chipc */
1094 - core = ai_findcore(sih, BCMA_CORE_CHIPCOMMON, 0);
1095 + core = sii->icbus->drv_cc.core;
1096
1097 if (bcma_read32(core, CHIPCREGOFFS(pmustatus)) & PST_EXTLPOAVAIL) {
1098 u32 ilp_ctr, alp_hz;
1099 --- a/drivers/net/wireless/brcm80211/brcmsmac/pmu.h
1100 +++ b/drivers/net/wireless/brcm80211/brcmsmac/pmu.h
1101 @@ -26,10 +26,7 @@ extern u32 si_pmu_chipcontrol(struct si_
1102 extern u32 si_pmu_regcontrol(struct si_pub *sih, uint reg, u32 mask, u32 val);
1103 extern u32 si_pmu_alp_clock(struct si_pub *sih);
1104 extern void si_pmu_pllupd(struct si_pub *sih);
1105 -extern void si_pmu_spuravoid_pllupdate(struct si_pub *sih, u8 spuravoid);
1106 extern u32 si_pmu_pllcontrol(struct si_pub *sih, uint reg, u32 mask, u32 val);
1107 -extern void si_pmu_init(struct si_pub *sih);
1108 -extern void si_pmu_res_init(struct si_pub *sih);
1109 extern u32 si_pmu_measure_alpclk(struct si_pub *sih);
1110
1111 #endif /* _BRCM_PMU_H_ */
1112 --- a/drivers/net/wireless/brcm80211/brcmsmac/pub.h
1113 +++ b/drivers/net/wireless/brcm80211/brcmsmac/pub.h
1114 @@ -311,7 +311,7 @@ extern uint brcms_c_detach(struct brcms_
1115 extern int brcms_c_up(struct brcms_c_info *wlc);
1116 extern uint brcms_c_down(struct brcms_c_info *wlc);
1117
1118 -extern bool brcms_c_chipmatch(u16 vendor, u16 device);
1119 +extern bool brcms_c_chipmatch(struct bcma_device *core);
1120 extern void brcms_c_init(struct brcms_c_info *wlc, bool mute_tx);
1121 extern void brcms_c_reset(struct brcms_c_info *wlc);
1122
1123 --- a/drivers/net/wireless/brcm80211/include/soc.h
1124 +++ b/drivers/net/wireless/brcm80211/include/soc.h
1125 @@ -19,68 +19,6 @@
1126
1127 #define SI_ENUM_BASE 0x18000000 /* Enumeration space base */
1128
1129 -/* core codes */
1130 -#define NODEV_CORE_ID 0x700 /* Invalid coreid */
1131 -#define CC_CORE_ID 0x800 /* chipcommon core */
1132 -#define ILINE20_CORE_ID 0x801 /* iline20 core */
1133 -#define SRAM_CORE_ID 0x802 /* sram core */
1134 -#define SDRAM_CORE_ID 0x803 /* sdram core */
1135 -#define PCI_CORE_ID 0x804 /* pci core */
1136 -#define MIPS_CORE_ID 0x805 /* mips core */
1137 -#define ENET_CORE_ID 0x806 /* enet mac core */
1138 -#define CODEC_CORE_ID 0x807 /* v90 codec core */
1139 -#define USB_CORE_ID 0x808 /* usb 1.1 host/device core */
1140 -#define ADSL_CORE_ID 0x809 /* ADSL core */
1141 -#define ILINE100_CORE_ID 0x80a /* iline100 core */
1142 -#define IPSEC_CORE_ID 0x80b /* ipsec core */
1143 -#define UTOPIA_CORE_ID 0x80c /* utopia core */
1144 -#define PCMCIA_CORE_ID 0x80d /* pcmcia core */
1145 -#define SOCRAM_CORE_ID 0x80e /* internal memory core */
1146 -#define MEMC_CORE_ID 0x80f /* memc sdram core */
1147 -#define OFDM_CORE_ID 0x810 /* OFDM phy core */
1148 -#define EXTIF_CORE_ID 0x811 /* external interface core */
1149 -#define D11_CORE_ID 0x812 /* 802.11 MAC core */
1150 -#define APHY_CORE_ID 0x813 /* 802.11a phy core */
1151 -#define BPHY_CORE_ID 0x814 /* 802.11b phy core */
1152 -#define GPHY_CORE_ID 0x815 /* 802.11g phy core */
1153 -#define MIPS33_CORE_ID 0x816 /* mips3302 core */
1154 -#define USB11H_CORE_ID 0x817 /* usb 1.1 host core */
1155 -#define USB11D_CORE_ID 0x818 /* usb 1.1 device core */
1156 -#define USB20H_CORE_ID 0x819 /* usb 2.0 host core */
1157 -#define USB20D_CORE_ID 0x81a /* usb 2.0 device core */
1158 -#define SDIOH_CORE_ID 0x81b /* sdio host core */
1159 -#define ROBO_CORE_ID 0x81c /* roboswitch core */
1160 -#define ATA100_CORE_ID 0x81d /* parallel ATA core */
1161 -#define SATAXOR_CORE_ID 0x81e /* serial ATA & XOR DMA core */
1162 -#define GIGETH_CORE_ID 0x81f /* gigabit ethernet core */
1163 -#define PCIE_CORE_ID 0x820 /* pci express core */
1164 -#define NPHY_CORE_ID 0x821 /* 802.11n 2x2 phy core */
1165 -#define SRAMC_CORE_ID 0x822 /* SRAM controller core */
1166 -#define MINIMAC_CORE_ID 0x823 /* MINI MAC/phy core */
1167 -#define ARM11_CORE_ID 0x824 /* ARM 1176 core */
1168 -#define ARM7S_CORE_ID 0x825 /* ARM7tdmi-s core */
1169 -#define LPPHY_CORE_ID 0x826 /* 802.11a/b/g phy core */
1170 -#define PMU_CORE_ID 0x827 /* PMU core */
1171 -#define SSNPHY_CORE_ID 0x828 /* 802.11n single-stream phy core */
1172 -#define SDIOD_CORE_ID 0x829 /* SDIO device core */
1173 -#define ARMCM3_CORE_ID 0x82a /* ARM Cortex M3 core */
1174 -#define HTPHY_CORE_ID 0x82b /* 802.11n 4x4 phy core */
1175 -#define MIPS74K_CORE_ID 0x82c /* mips 74k core */
1176 -#define GMAC_CORE_ID 0x82d /* Gigabit MAC core */
1177 -#define DMEMC_CORE_ID 0x82e /* DDR1/2 memory controller core */
1178 -#define PCIERC_CORE_ID 0x82f /* PCIE Root Complex core */
1179 -#define OCP_CORE_ID 0x830 /* OCP2OCP bridge core */
1180 -#define SC_CORE_ID 0x831 /* shared common core */
1181 -#define AHB_CORE_ID 0x832 /* OCP2AHB bridge core */
1182 -#define SPIH_CORE_ID 0x833 /* SPI host core */
1183 -#define I2S_CORE_ID 0x834 /* I2S core */
1184 -#define DMEMS_CORE_ID 0x835 /* SDR/DDR1 memory controller core */
1185 -#define DEF_SHIM_COMP 0x837 /* SHIM component in ubus/6362 */
1186 -#define OOB_ROUTER_CORE_ID 0x367 /* OOB router core ID */
1187 -#define DEF_AI_COMP 0xfff /* Default component, in ai chips it
1188 - * maps all unused address ranges
1189 - */
1190 -
1191 /* Common core control flags */
1192 #define SICF_BIST_EN 0x8000
1193 #define SICF_PME_EN 0x4000
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