target/linux/ar7/files/include/asm-mips/ar7/ar7.h

   1 /*
   2  * Copyright (C) 2006,2007 Felix Fietkau <nbd@openwrt.org>
   3  * Copyright (C) 2006,2007 Eugene Konev <ejka@openwrt.org>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  18  */
  19
  20 #ifndef __AR7_H__
  21 #define __AR7_H__
  22
  23 #include <linux/delay.h>
  24 #include <asm/addrspace.h>
  25 #include <linux/io.h>
  26
  27 #define AR7_REGS_BASE   0x08610000
  28
  29 #define AR7_REGS_MAC0   (AR7_REGS_BASE + 0x0000)
  30 #define AR7_REGS_GPIO   (AR7_REGS_BASE + 0x0900)
  31 /* 0x08610A00 - 0x08610BFF (512 bytes, 128 bytes / clock) */
  32 #define AR7_REGS_POWER  (AR7_REGS_BASE + 0x0a00)
  33 #define AR7_REGS_UART0  (AR7_REGS_BASE + 0x0e00)
  34 #define AR7_REGS_USB    (AR7_REGS_BASE + 0x1200)
  35 #define AR7_REGS_RESET  (AR7_REGS_BASE + 0x1600)
  36 #define AR7_REGS_VLYNQ0 (AR7_REGS_BASE + 0x1800)
  37 #define AR7_REGS_DCL    (AR7_REGS_BASE + 0x1a00)
  38 #define AR7_REGS_VLYNQ1 (AR7_REGS_BASE + 0x1c00)
  39 #define AR7_REGS_MDIO   (AR7_REGS_BASE + 0x1e00)
  40 #define AR7_REGS_IRQ    (AR7_REGS_BASE + 0x2400)
  41 #define AR7_REGS_MAC1   (AR7_REGS_BASE + 0x2800)
  42
  43 #define AR7_REGS_WDT    (AR7_REGS_BASE + 0x1f00)
  44 #define UR8_REGS_WDT    (AR7_REGS_BASE + 0x0b00)
  45 #define UR8_REGS_UART1  (AR7_REGS_BASE + 0x0f00)
  46
  47 #define TITAN_REGS_MAC0         (0x08640000)
  48 #define TITAN_REGS_MAC1         (TITAN_REGS_MAC0 + 0x0800)
  49 #define TITAN_REGS_VLYNQ0       (AR7_REGS_BASE + 0x1c00)
  50 #define TITAN_REGS_VLYNQ1       (AR7_REGS_BASE + 0x1300)
  51
  52 #define AR7_RESET_PEREPHERIAL   0x0
  53 #define AR7_RESET_SOFTWARE      0x4
  54 #define AR7_RESET_STATUS        0x8
  55
  56 #define AR7_RESET_BIT_CPMAC_LO  17
  57 #define AR7_RESET_BIT_CPMAC_HI  21
  58 #define AR7_RESET_BIT_MDIO      22
  59 #define AR7_RESET_BIT_EPHY      26
  60
  61 #define TITAN_RESET_BIT_EPHY1   28
  62
  63 /* GPIO control registers */
  64 #define AR7_GPIO_INPUT  0x0
  65 #define AR7_GPIO_OUTPUT 0x4
  66 #define AR7_GPIO_DIR    0x8
  67 #define AR7_GPIO_ENABLE 0xc
  68 #define TITAN_GPIO_INPUT_0      0x0
  69 #define TITAN_GPIO_INPUT_1      0x4
  70 #define TITAN_GPIO_OUTPUT_0     0x8
  71 #define TITAN_GPIO_OUTPUT_1     0xc
  72 #define TITAN_GPIO_DIR_0        0x10
  73 #define TITAN_GPIO_DIR_1        0x14
  74 #define TITAN_GPIO_ENBL_0       0x18
  75 #define TITAN_GPIO_ENBL_1       0x1c
  76
  77 #define AR7_CHIP_7100   0x18
  78 #define AR7_CHIP_7200   0x2b
  79 #define AR7_CHIP_7300   0x05
  80 #define AR7_CHIP_TITAN  0x07
  81 #define TITAN_CHIP_1050 0x0f
  82 #define TITAN_CHIP_1055 0x0e
  83 #define TITAN_CHIP_1056 0x0d
  84 #define TITAN_CHIP_1060 0x07
  85
  86 /* Interrupts */
  87 #define AR7_IRQ_UART0   15
  88 #define AR7_IRQ_UART1   16
  89
  90 /* Clocks */
  91 #define AR7_AFE_CLOCK   35328000
  92 #define AR7_REF_CLOCK   25000000
  93 #define AR7_XTAL_CLOCK  24000000
  94
  95 struct plat_cpmac_data {
  96         int reset_bit;
  97         int power_bit;
  98         u32 phy_mask;
  99         char dev_addr[6];
 100 };
 101
 102 struct plat_dsl_data {
 103         int reset_bit_dsl;
 104         int reset_bit_sar;
 105 };
 106
 107 extern int ar7_cpu_clock, ar7_bus_clock, ar7_dsp_clock;
 108
 109 static inline int ar7_is_titan(void)
 110 {
 111         return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + 0x24)) & 0xffff) ==
 112                 AR7_CHIP_TITAN;
 113 }
 114
 115 static inline u16 ar7_chip_id(void)
 116 {
 117         return ar7_is_titan() ? AR7_CHIP_TITAN : (readl((void *)
 118                 KSEG1ADDR(AR7_REGS_GPIO + 0x14)) & 0xffff);
 119 }
 120
 121 static inline u8 ar7_chip_rev(void)
 122 {
 123         return (readl((void *)KSEG1ADDR(AR7_REGS_GPIO + (ar7_is_titan() ? 0x24 :
 124                 0x14))) >> 16) & 0xff;
 125 }
 126
 127 static inline int ar7_cpu_freq(void)
 128 {
 129         return ar7_cpu_clock;
 130 }
 131
 132 static inline int ar7_bus_freq(void)
 133 {
 134         return ar7_bus_clock;
 135 }
 136
 137 static inline int ar7_vbus_freq(void)
 138 {
 139         return ar7_bus_clock / 2;
 140 }
 141 #define ar7_cpmac_freq ar7_vbus_freq
 142
 143 static inline int ar7_dsp_freq(void)
 144 {
 145         return ar7_dsp_clock;
 146 }
 147
 148 static inline int ar7_has_high_cpmac(void)
 149 {
 150         u16 chip_id = ar7_chip_id();
 151         switch (chip_id) {
 152         case AR7_CHIP_7100:
 153         case AR7_CHIP_7200:
 154                 return 0;
 155         default:
 156                 return 1;
 157         }
 158 }
 159 #define ar7_has_high_vlynq ar7_has_high_cpmac
 160 #define ar7_has_second_uart ar7_has_high_cpmac
 161
 162 static inline void ar7_device_enable(u32 bit)
 163 {
 164         void *reset_reg =
 165                 (void *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PEREPHERIAL);
 166         writel(readl(reset_reg) | (1 << bit), reset_reg);
 167         mdelay(20);
 168 }
 169
 170 static inline void ar7_device_disable(u32 bit)
 171 {
 172         void *reset_reg =
 173                 (void *)KSEG1ADDR(AR7_REGS_RESET + AR7_RESET_PEREPHERIAL);
 174         writel(readl(reset_reg) & ~(1 << bit), reset_reg);
 175         mdelay(20);
 176 }
 177
 178 static inline void ar7_device_reset(u32 bit)
 179 {
 180         ar7_device_disable(bit);
 181         ar7_device_enable(bit);
 182 }
 183
 184 static inline void ar7_device_on(u32 bit)
 185 {
 186         void *power_reg = (void *)KSEG1ADDR(AR7_REGS_POWER);
 187         writel(readl(power_reg) | (1 << bit), power_reg);
 188         mdelay(20);
 189 }
 190
 191 static inline void ar7_device_off(u32 bit)
 192 {
 193         void *power_reg = (void *)KSEG1ADDR(AR7_REGS_POWER);
 194         writel(readl(power_reg) & ~(1 << bit), power_reg);
 195         mdelay(20);
 196 }
 197
 198 #endif /* __AR7_H__ */