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ar71xx: allow to register ethernet interfaces for AR934X
[openwrt/openwrt.git] / target / linux / ar71xx / files / arch / mips / ar71xx / devices.c
1 /*
2 * Atheros AR71xx SoC platform devices
3 *
4 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
5 * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
6 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 *
8 * Parts of this file are based on Atheros 2.6.15 BSP
9 * Parts of this file are based on Atheros 2.6.31 BSP
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License version 2 as published
13 * by the Free Software Foundation.
14 */
15
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/delay.h>
19 #include <linux/etherdevice.h>
20 #include <linux/platform_device.h>
21 #include <linux/serial_8250.h>
22
23 #include <asm/mach-ar71xx/ar71xx.h>
24 #include <asm/mach-ar71xx/ar933x_uart_platform.h>
25
26 #include "devices.h"
27
28 unsigned char ar71xx_mac_base[ETH_ALEN] __initdata;
29
30 static struct resource ar71xx_uart_resources[] = {
31 {
32 .start = AR71XX_UART_BASE,
33 .end = AR71XX_UART_BASE + AR71XX_UART_SIZE - 1,
34 .flags = IORESOURCE_MEM,
35 },
36 };
37
38 #define AR71XX_UART_FLAGS (UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP)
39 static struct plat_serial8250_port ar71xx_uart_data[] = {
40 {
41 .mapbase = AR71XX_UART_BASE,
42 .irq = AR71XX_MISC_IRQ_UART,
43 .flags = AR71XX_UART_FLAGS,
44 .iotype = UPIO_MEM32,
45 .regshift = 2,
46 }, {
47 /* terminating entry */
48 }
49 };
50
51 static struct platform_device ar71xx_uart_device = {
52 .name = "serial8250",
53 .id = PLAT8250_DEV_PLATFORM,
54 .resource = ar71xx_uart_resources,
55 .num_resources = ARRAY_SIZE(ar71xx_uart_resources),
56 .dev = {
57 .platform_data = ar71xx_uart_data
58 },
59 };
60
61 static struct resource ar933x_uart_resources[] = {
62 {
63 .start = AR933X_UART_BASE,
64 .end = AR933X_UART_BASE + AR71XX_UART_SIZE - 1,
65 .flags = IORESOURCE_MEM,
66 },
67 {
68 .start = AR71XX_MISC_IRQ_UART,
69 .end = AR71XX_MISC_IRQ_UART,
70 .flags = IORESOURCE_IRQ,
71 },
72 };
73
74 static struct ar933x_uart_platform_data ar933x_uart_data;
75 static struct platform_device ar933x_uart_device = {
76 .name = "ar933x-uart",
77 .id = -1,
78 .resource = ar933x_uart_resources,
79 .num_resources = ARRAY_SIZE(ar933x_uart_resources),
80 .dev = {
81 .platform_data = &ar933x_uart_data,
82 },
83 };
84
85 void __init ar71xx_add_device_uart(void)
86 {
87 struct platform_device *pdev;
88
89 switch (ar71xx_soc) {
90 case AR71XX_SOC_AR7130:
91 case AR71XX_SOC_AR7141:
92 case AR71XX_SOC_AR7161:
93 case AR71XX_SOC_AR7240:
94 case AR71XX_SOC_AR7241:
95 case AR71XX_SOC_AR7242:
96 case AR71XX_SOC_AR9130:
97 case AR71XX_SOC_AR9132:
98 pdev = &ar71xx_uart_device;
99 ar71xx_uart_data[0].uartclk = ar71xx_ahb_freq;
100 break;
101
102 case AR71XX_SOC_AR9330:
103 case AR71XX_SOC_AR9331:
104 pdev = &ar933x_uart_device;
105 ar933x_uart_data.uartclk = ar71xx_ref_freq;
106 break;
107
108 case AR71XX_SOC_AR9341:
109 case AR71XX_SOC_AR9342:
110 case AR71XX_SOC_AR9344:
111 pdev = &ar71xx_uart_device;
112 ar71xx_uart_data[0].uartclk = ar71xx_ref_freq;
113 break;
114
115 default:
116 BUG();
117 }
118
119 platform_device_register(pdev);
120 }
121
122 static struct resource ar71xx_mdio_resources[] = {
123 {
124 .name = "mdio_base",
125 .flags = IORESOURCE_MEM,
126 .start = AR71XX_GE0_BASE,
127 .end = AR71XX_GE0_BASE + 0x200 - 1,
128 }
129 };
130
131 static struct ag71xx_mdio_platform_data ar71xx_mdio_data;
132
133 struct platform_device ar71xx_mdio_device = {
134 .name = "ag71xx-mdio",
135 .id = -1,
136 .resource = ar71xx_mdio_resources,
137 .num_resources = ARRAY_SIZE(ar71xx_mdio_resources),
138 .dev = {
139 .platform_data = &ar71xx_mdio_data,
140 },
141 };
142
143 static void ar71xx_set_pll(u32 cfg_reg, u32 pll_reg, u32 pll_val, u32 shift)
144 {
145 void __iomem *base;
146 u32 t;
147
148 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
149
150 t = __raw_readl(base + cfg_reg);
151 t &= ~(3 << shift);
152 t |= (2 << shift);
153 __raw_writel(t, base + cfg_reg);
154 udelay(100);
155
156 __raw_writel(pll_val, base + pll_reg);
157
158 t |= (3 << shift);
159 __raw_writel(t, base + cfg_reg);
160 udelay(100);
161
162 t &= ~(3 << shift);
163 __raw_writel(t, base + cfg_reg);
164 udelay(100);
165
166 printk(KERN_DEBUG "ar71xx: pll_reg %#x: %#x\n",
167 (unsigned int)(base + pll_reg), __raw_readl(base + pll_reg));
168
169 iounmap(base);
170 }
171
172 void __init ar71xx_add_device_mdio(u32 phy_mask)
173 {
174 switch (ar71xx_soc) {
175 case AR71XX_SOC_AR7240:
176 ar71xx_mdio_data.is_ar7240 = 1;
177 break;
178 case AR71XX_SOC_AR7241:
179 ar71xx_mdio_data.is_ar7240 = 1;
180 ar71xx_mdio_resources[0].start = AR71XX_GE1_BASE;
181 ar71xx_mdio_resources[0].end = AR71XX_GE1_BASE + 0x200 - 1;
182 break;
183 case AR71XX_SOC_AR7242:
184 ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG,
185 AR7242_PLL_REG_ETH0_INT_CLOCK, 0x62000000,
186 AR71XX_ETH0_PLL_SHIFT);
187 break;
188 case AR71XX_SOC_AR9330:
189 case AR71XX_SOC_AR9331:
190 ar71xx_mdio_data.is_ar7240 = 1;
191 ar71xx_mdio_resources[0].start = AR71XX_GE1_BASE;
192 ar71xx_mdio_resources[0].end = AR71XX_GE1_BASE + 0x200 - 1;
193 break;
194 default:
195 break;
196 }
197
198 ar71xx_mdio_data.phy_mask = phy_mask;
199
200 platform_device_register(&ar71xx_mdio_device);
201 }
202
203 struct ar71xx_eth_pll_data ar71xx_eth0_pll_data;
204 struct ar71xx_eth_pll_data ar71xx_eth1_pll_data;
205
206 static u32 ar71xx_get_eth_pll(unsigned int mac, int speed)
207 {
208 struct ar71xx_eth_pll_data *pll_data;
209 u32 pll_val;
210
211 switch (mac) {
212 case 0:
213 pll_data = &ar71xx_eth0_pll_data;
214 break;
215 case 1:
216 pll_data = &ar71xx_eth1_pll_data;
217 break;
218 default:
219 BUG();
220 }
221
222 switch (speed) {
223 case SPEED_10:
224 pll_val = pll_data->pll_10;
225 break;
226 case SPEED_100:
227 pll_val = pll_data->pll_100;
228 break;
229 case SPEED_1000:
230 pll_val = pll_data->pll_1000;
231 break;
232 default:
233 BUG();
234 }
235
236 return pll_val;
237 }
238
239 static void ar71xx_set_pll_ge0(int speed)
240 {
241 u32 val = ar71xx_get_eth_pll(0, speed);
242
243 ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH0_INT_CLOCK,
244 val, AR71XX_ETH0_PLL_SHIFT);
245 }
246
247 static void ar71xx_set_pll_ge1(int speed)
248 {
249 u32 val = ar71xx_get_eth_pll(1, speed);
250
251 ar71xx_set_pll(AR71XX_PLL_REG_SEC_CONFIG, AR71XX_PLL_REG_ETH1_INT_CLOCK,
252 val, AR71XX_ETH1_PLL_SHIFT);
253 }
254
255 static void ar724x_set_pll_ge0(int speed)
256 {
257 /* TODO */
258 }
259
260 static void ar724x_set_pll_ge1(int speed)
261 {
262 /* TODO */
263 }
264
265 static void ar7242_set_pll_ge0(int speed)
266 {
267 u32 val = ar71xx_get_eth_pll(0, speed);
268 void __iomem *base;
269
270 base = ioremap_nocache(AR71XX_PLL_BASE, AR71XX_PLL_SIZE);
271 __raw_writel(val, base + AR7242_PLL_REG_ETH0_INT_CLOCK);
272 iounmap(base);
273 }
274
275 static void ar91xx_set_pll_ge0(int speed)
276 {
277 u32 val = ar71xx_get_eth_pll(0, speed);
278
279 ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH0_INT_CLOCK,
280 val, AR91XX_ETH0_PLL_SHIFT);
281 }
282
283 static void ar91xx_set_pll_ge1(int speed)
284 {
285 u32 val = ar71xx_get_eth_pll(1, speed);
286
287 ar71xx_set_pll(AR91XX_PLL_REG_ETH_CONFIG, AR91XX_PLL_REG_ETH1_INT_CLOCK,
288 val, AR91XX_ETH1_PLL_SHIFT);
289 }
290
291 static void ar933x_set_pll_ge0(int speed)
292 {
293 /* TODO */
294 }
295
296 static void ar933x_set_pll_ge1(int speed)
297 {
298 /* TODO */
299 }
300
301 static void ar934x_set_pll_ge0(int speed)
302 {
303 /* TODO */
304 }
305
306 static void ar934x_set_pll_ge1(int speed)
307 {
308 /* TODO */
309 }
310
311 static void ar71xx_ddr_flush_ge0(void)
312 {
313 ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_GE0);
314 }
315
316 static void ar71xx_ddr_flush_ge1(void)
317 {
318 ar71xx_ddr_flush(AR71XX_DDR_REG_FLUSH_GE1);
319 }
320
321 static void ar724x_ddr_flush_ge0(void)
322 {
323 ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE0);
324 }
325
326 static void ar724x_ddr_flush_ge1(void)
327 {
328 ar71xx_ddr_flush(AR724X_DDR_REG_FLUSH_GE1);
329 }
330
331 static void ar91xx_ddr_flush_ge0(void)
332 {
333 ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE0);
334 }
335
336 static void ar91xx_ddr_flush_ge1(void)
337 {
338 ar71xx_ddr_flush(AR91XX_DDR_REG_FLUSH_GE1);
339 }
340
341 static void ar933x_ddr_flush_ge0(void)
342 {
343 ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_GE0);
344 }
345
346 static void ar933x_ddr_flush_ge1(void)
347 {
348 ar71xx_ddr_flush(AR933X_DDR_REG_FLUSH_GE1);
349 }
350
351 static void ar934x_ddr_flush_ge0(void)
352 {
353 ar71xx_ddr_flush(AR934X_DDR_REG_FLUSH_GE0);
354 }
355
356 static void ar934x_ddr_flush_ge1(void)
357 {
358 ar71xx_ddr_flush(AR934X_DDR_REG_FLUSH_GE1);
359 }
360
361 static struct resource ar71xx_eth0_resources[] = {
362 {
363 .name = "mac_base",
364 .flags = IORESOURCE_MEM,
365 .start = AR71XX_GE0_BASE,
366 .end = AR71XX_GE0_BASE + 0x200 - 1,
367 }, {
368 .name = "mii_ctrl",
369 .flags = IORESOURCE_MEM,
370 .start = AR71XX_MII_BASE + MII_REG_MII0_CTRL,
371 .end = AR71XX_MII_BASE + MII_REG_MII0_CTRL + 3,
372 }, {
373 .name = "mac_irq",
374 .flags = IORESOURCE_IRQ,
375 .start = AR71XX_CPU_IRQ_GE0,
376 .end = AR71XX_CPU_IRQ_GE0,
377 },
378 };
379
380 struct ag71xx_platform_data ar71xx_eth0_data = {
381 .reset_bit = RESET_MODULE_GE0_MAC,
382 };
383
384 struct platform_device ar71xx_eth0_device = {
385 .name = "ag71xx",
386 .id = 0,
387 .resource = ar71xx_eth0_resources,
388 .num_resources = ARRAY_SIZE(ar71xx_eth0_resources),
389 .dev = {
390 .platform_data = &ar71xx_eth0_data,
391 },
392 };
393
394 static struct resource ar71xx_eth1_resources[] = {
395 {
396 .name = "mac_base",
397 .flags = IORESOURCE_MEM,
398 .start = AR71XX_GE1_BASE,
399 .end = AR71XX_GE1_BASE + 0x200 - 1,
400 }, {
401 .name = "mii_ctrl",
402 .flags = IORESOURCE_MEM,
403 .start = AR71XX_MII_BASE + MII_REG_MII1_CTRL,
404 .end = AR71XX_MII_BASE + MII_REG_MII1_CTRL + 3,
405 }, {
406 .name = "mac_irq",
407 .flags = IORESOURCE_IRQ,
408 .start = AR71XX_CPU_IRQ_GE1,
409 .end = AR71XX_CPU_IRQ_GE1,
410 },
411 };
412
413 struct ag71xx_platform_data ar71xx_eth1_data = {
414 .reset_bit = RESET_MODULE_GE1_MAC,
415 };
416
417 struct platform_device ar71xx_eth1_device = {
418 .name = "ag71xx",
419 .id = 1,
420 .resource = ar71xx_eth1_resources,
421 .num_resources = ARRAY_SIZE(ar71xx_eth1_resources),
422 .dev = {
423 .platform_data = &ar71xx_eth1_data,
424 },
425 };
426
427 #define AR71XX_PLL_VAL_1000 0x00110000
428 #define AR71XX_PLL_VAL_100 0x00001099
429 #define AR71XX_PLL_VAL_10 0x00991099
430
431 #define AR724X_PLL_VAL_1000 0x00110000
432 #define AR724X_PLL_VAL_100 0x00001099
433 #define AR724X_PLL_VAL_10 0x00991099
434
435 #define AR7242_PLL_VAL_1000 0x16000000
436 #define AR7242_PLL_VAL_100 0x00000101
437 #define AR7242_PLL_VAL_10 0x00001616
438
439 #define AR91XX_PLL_VAL_1000 0x1a000000
440 #define AR91XX_PLL_VAL_100 0x13000a44
441 #define AR91XX_PLL_VAL_10 0x00441099
442
443 #define AR933X_PLL_VAL_1000 0x00110000
444 #define AR933X_PLL_VAL_100 0x00001099
445 #define AR933X_PLL_VAL_10 0x00991099
446
447 #define AR934X_PLL_VAL_1000 0x00110000
448 #define AR934X_PLL_VAL_100 0x00001099
449 #define AR934X_PLL_VAL_10 0x00991099
450
451 static void __init ar71xx_init_eth_pll_data(unsigned int id)
452 {
453 struct ar71xx_eth_pll_data *pll_data;
454 u32 pll_10, pll_100, pll_1000;
455
456 switch (id) {
457 case 0:
458 pll_data = &ar71xx_eth0_pll_data;
459 break;
460 case 1:
461 pll_data = &ar71xx_eth1_pll_data;
462 break;
463 default:
464 BUG();
465 }
466
467 switch (ar71xx_soc) {
468 case AR71XX_SOC_AR7130:
469 case AR71XX_SOC_AR7141:
470 case AR71XX_SOC_AR7161:
471 pll_10 = AR71XX_PLL_VAL_10;
472 pll_100 = AR71XX_PLL_VAL_100;
473 pll_1000 = AR71XX_PLL_VAL_1000;
474 break;
475
476 case AR71XX_SOC_AR7240:
477 case AR71XX_SOC_AR7241:
478 pll_10 = AR724X_PLL_VAL_10;
479 pll_100 = AR724X_PLL_VAL_100;
480 pll_1000 = AR724X_PLL_VAL_1000;
481 break;
482
483 case AR71XX_SOC_AR7242:
484 pll_10 = AR7242_PLL_VAL_10;
485 pll_100 = AR7242_PLL_VAL_100;
486 pll_1000 = AR7242_PLL_VAL_1000;
487 break;
488
489 case AR71XX_SOC_AR9130:
490 case AR71XX_SOC_AR9132:
491 pll_10 = AR91XX_PLL_VAL_10;
492 pll_100 = AR91XX_PLL_VAL_100;
493 pll_1000 = AR91XX_PLL_VAL_1000;
494 break;
495
496 case AR71XX_SOC_AR9330:
497 case AR71XX_SOC_AR9331:
498 pll_10 = AR933X_PLL_VAL_10;
499 pll_100 = AR933X_PLL_VAL_100;
500 pll_1000 = AR933X_PLL_VAL_1000;
501 break;
502
503 case AR71XX_SOC_AR9341:
504 case AR71XX_SOC_AR9342:
505 case AR71XX_SOC_AR9344:
506 pll_10 = AR934X_PLL_VAL_10;
507 pll_100 = AR934X_PLL_VAL_100;
508 pll_1000 = AR934X_PLL_VAL_1000;
509 break;
510
511 default:
512 BUG();
513 }
514
515 if (!pll_data->pll_10)
516 pll_data->pll_10 = pll_10;
517
518 if (!pll_data->pll_100)
519 pll_data->pll_100 = pll_100;
520
521 if (!pll_data->pll_1000)
522 pll_data->pll_1000 = pll_1000;
523 }
524
525 static int ar71xx_eth_instance __initdata;
526 void __init ar71xx_add_device_eth(unsigned int id)
527 {
528 struct platform_device *pdev;
529 struct ag71xx_platform_data *pdata;
530
531 ar71xx_init_eth_pll_data(id);
532
533 switch (id) {
534 case 0:
535 switch (ar71xx_eth0_data.phy_if_mode) {
536 case PHY_INTERFACE_MODE_MII:
537 ar71xx_eth0_data.mii_if = MII0_CTRL_IF_MII;
538 break;
539 case PHY_INTERFACE_MODE_GMII:
540 ar71xx_eth0_data.mii_if = MII0_CTRL_IF_GMII;
541 break;
542 case PHY_INTERFACE_MODE_RGMII:
543 ar71xx_eth0_data.mii_if = MII0_CTRL_IF_RGMII;
544 break;
545 case PHY_INTERFACE_MODE_RMII:
546 ar71xx_eth0_data.mii_if = MII0_CTRL_IF_RMII;
547 break;
548 default:
549 printk(KERN_ERR "ar71xx: invalid PHY interface mode "
550 "for eth0\n");
551 return;
552 }
553 pdev = &ar71xx_eth0_device;
554 break;
555 case 1:
556 switch (ar71xx_eth1_data.phy_if_mode) {
557 case PHY_INTERFACE_MODE_RMII:
558 ar71xx_eth1_data.mii_if = MII1_CTRL_IF_RMII;
559 break;
560 case PHY_INTERFACE_MODE_RGMII:
561 ar71xx_eth1_data.mii_if = MII1_CTRL_IF_RGMII;
562 break;
563 default:
564 printk(KERN_ERR "ar71xx: invalid PHY interface mode "
565 "for eth1\n");
566 return;
567 }
568 pdev = &ar71xx_eth1_device;
569 break;
570 default:
571 printk(KERN_ERR "ar71xx: invalid ethernet id %d\n", id);
572 return;
573 }
574
575 pdata = pdev->dev.platform_data;
576
577 switch (ar71xx_soc) {
578 case AR71XX_SOC_AR7130:
579 pdata->ddr_flush = id ? ar71xx_ddr_flush_ge1
580 : ar71xx_ddr_flush_ge0;
581 pdata->set_pll = id ? ar71xx_set_pll_ge1
582 : ar71xx_set_pll_ge0;
583 break;
584
585 case AR71XX_SOC_AR7141:
586 case AR71XX_SOC_AR7161:
587 pdata->ddr_flush = id ? ar71xx_ddr_flush_ge1
588 : ar71xx_ddr_flush_ge0;
589 pdata->set_pll = id ? ar71xx_set_pll_ge1
590 : ar71xx_set_pll_ge0;
591 pdata->has_gbit = 1;
592 break;
593
594 case AR71XX_SOC_AR7242:
595 ar71xx_eth0_data.reset_bit |= AR724X_RESET_GE0_MDIO |
596 RESET_MODULE_GE0_PHY;
597 ar71xx_eth1_data.reset_bit |= AR724X_RESET_GE1_MDIO |
598 RESET_MODULE_GE1_PHY;
599 pdata->ddr_flush = id ? ar724x_ddr_flush_ge1
600 : ar724x_ddr_flush_ge0;
601 pdata->set_pll = id ? ar724x_set_pll_ge1
602 : ar7242_set_pll_ge0;
603 pdata->has_gbit = 1;
604 pdata->is_ar724x = 1;
605
606 if (!pdata->fifo_cfg1)
607 pdata->fifo_cfg1 = 0x0010ffff;
608 if (!pdata->fifo_cfg2)
609 pdata->fifo_cfg2 = 0x015500aa;
610 if (!pdata->fifo_cfg3)
611 pdata->fifo_cfg3 = 0x01f00140;
612 break;
613
614 case AR71XX_SOC_AR7241:
615 ar71xx_eth0_data.reset_bit |= AR724X_RESET_GE0_MDIO;
616 ar71xx_eth1_data.reset_bit |= AR724X_RESET_GE1_MDIO;
617 /* fall through */
618 case AR71XX_SOC_AR7240:
619 ar71xx_eth0_data.reset_bit |= RESET_MODULE_GE0_PHY;
620 ar71xx_eth1_data.reset_bit |= RESET_MODULE_GE1_PHY;
621 pdata->ddr_flush = id ? ar724x_ddr_flush_ge1
622 : ar724x_ddr_flush_ge0;
623 pdata->set_pll = id ? ar724x_set_pll_ge1
624 : ar724x_set_pll_ge0;
625 pdata->is_ar724x = 1;
626 if (ar71xx_soc == AR71XX_SOC_AR7240)
627 pdata->is_ar7240 = 1;
628
629 if (!pdata->fifo_cfg1)
630 pdata->fifo_cfg1 = 0x0010ffff;
631 if (!pdata->fifo_cfg2)
632 pdata->fifo_cfg2 = 0x015500aa;
633 if (!pdata->fifo_cfg3)
634 pdata->fifo_cfg3 = 0x01f00140;
635 break;
636
637 case AR71XX_SOC_AR9130:
638 pdata->ddr_flush = id ? ar91xx_ddr_flush_ge1
639 : ar91xx_ddr_flush_ge0;
640 pdata->set_pll = id ? ar91xx_set_pll_ge1
641 : ar91xx_set_pll_ge0;
642 pdata->is_ar91xx = 1;
643 break;
644
645 case AR71XX_SOC_AR9132:
646 pdata->ddr_flush = id ? ar91xx_ddr_flush_ge1
647 : ar91xx_ddr_flush_ge0;
648 pdata->set_pll = id ? ar91xx_set_pll_ge1
649 : ar91xx_set_pll_ge0;
650 pdata->is_ar91xx = 1;
651 pdata->has_gbit = 1;
652 break;
653
654 case AR71XX_SOC_AR9330:
655 case AR71XX_SOC_AR9331:
656 ar71xx_eth0_data.reset_bit = AR933X_RESET_GE0_MAC |
657 AR933X_RESET_GE0_MDIO;
658 ar71xx_eth1_data.reset_bit = AR933X_RESET_GE1_MAC |
659 AR933X_RESET_GE1_MDIO;
660 pdata->ddr_flush = id ? ar933x_ddr_flush_ge1
661 : ar933x_ddr_flush_ge0;
662 pdata->set_pll = id ? ar933x_set_pll_ge1
663 : ar933x_set_pll_ge0;
664 pdata->has_gbit = 1;
665 pdata->is_ar724x = 1;
666
667 if (!pdata->fifo_cfg1)
668 pdata->fifo_cfg1 = 0x0010ffff;
669 if (!pdata->fifo_cfg2)
670 pdata->fifo_cfg2 = 0x015500aa;
671 if (!pdata->fifo_cfg3)
672 pdata->fifo_cfg3 = 0x01f00140;
673 break;
674
675 case AR71XX_SOC_AR9341:
676 case AR71XX_SOC_AR9342:
677 case AR71XX_SOC_AR9344:
678 ar71xx_eth0_data.reset_bit = AR934X_RESET_GE0_MAC |
679 AR934X_RESET_GE0_MDIO;
680 ar71xx_eth1_data.reset_bit = AR934X_RESET_GE1_MAC |
681 AR934X_RESET_GE1_MDIO;
682 pdata->ddr_flush = id ? ar934x_ddr_flush_ge1
683 : ar934x_ddr_flush_ge0;
684 pdata->set_pll = id ? ar934x_set_pll_ge1
685 : ar934x_set_pll_ge0;
686 pdata->has_gbit = 1;
687 pdata->is_ar724x = 1;
688
689 if (!pdata->fifo_cfg1)
690 pdata->fifo_cfg1 = 0x0010ffff;
691 if (!pdata->fifo_cfg2)
692 pdata->fifo_cfg2 = 0x015500aa;
693 if (!pdata->fifo_cfg3)
694 pdata->fifo_cfg3 = 0x01f00140;
695 break;
696
697 default:
698 BUG();
699 }
700
701 switch (pdata->phy_if_mode) {
702 case PHY_INTERFACE_MODE_GMII:
703 case PHY_INTERFACE_MODE_RGMII:
704 if (!pdata->has_gbit) {
705 printk(KERN_ERR "ar71xx: no gbit available on eth%d\n",
706 id);
707 return;
708 }
709 /* fallthrough */
710 default:
711 break;
712 }
713
714 if (!is_valid_ether_addr(pdata->mac_addr)) {
715 random_ether_addr(pdata->mac_addr);
716 printk(KERN_DEBUG
717 "ar71xx: using random MAC address for eth%d\n",
718 ar71xx_eth_instance);
719 }
720
721 if (pdata->mii_bus_dev == NULL)
722 pdata->mii_bus_dev = &ar71xx_mdio_device.dev;
723
724 /* Reset the device */
725 ar71xx_device_stop(pdata->reset_bit);
726 mdelay(100);
727
728 ar71xx_device_start(pdata->reset_bit);
729 mdelay(100);
730
731 platform_device_register(pdev);
732 ar71xx_eth_instance++;
733 }
734
735 static struct resource ar71xx_spi_resources[] = {
736 [0] = {
737 .start = AR71XX_SPI_BASE,
738 .end = AR71XX_SPI_BASE + AR71XX_SPI_SIZE - 1,
739 .flags = IORESOURCE_MEM,
740 },
741 };
742
743 static struct platform_device ar71xx_spi_device = {
744 .name = "ar71xx-spi",
745 .id = -1,
746 .resource = ar71xx_spi_resources,
747 .num_resources = ARRAY_SIZE(ar71xx_spi_resources),
748 };
749
750 void __init ar71xx_add_device_spi(struct ar71xx_spi_platform_data *pdata,
751 struct spi_board_info const *info,
752 unsigned n)
753 {
754 spi_register_board_info(info, n);
755 ar71xx_spi_device.dev.platform_data = pdata;
756 platform_device_register(&ar71xx_spi_device);
757 }
758
759 void __init ar71xx_add_device_wdt(void)
760 {
761 platform_device_register_simple("ar71xx-wdt", -1, NULL, 0);
762 }
763
764 void __init ar71xx_set_mac_base(unsigned char *mac)
765 {
766 memcpy(ar71xx_mac_base, mac, ETH_ALEN);
767 }
768
769 void __init ar71xx_parse_mac_addr(char *mac_str)
770 {
771 u8 tmp[ETH_ALEN];
772 int t;
773
774 t = sscanf(mac_str, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
775 &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]);
776
777 if (t != ETH_ALEN)
778 t = sscanf(mac_str, "%02hhx.%02hhx.%02hhx.%02hhx.%02hhx.%02hhx",
779 &tmp[0], &tmp[1], &tmp[2], &tmp[3], &tmp[4], &tmp[5]);
780
781 if (t == ETH_ALEN)
782 ar71xx_set_mac_base(tmp);
783 else
784 printk(KERN_DEBUG "ar71xx: failed to parse mac address "
785 "\"%s\"\n", mac_str);
786 }
787
788 static int __init ar71xx_ethaddr_setup(char *str)
789 {
790 ar71xx_parse_mac_addr(str);
791 return 1;
792 }
793 __setup("ethaddr=", ar71xx_ethaddr_setup);
794
795 static int __init ar71xx_kmac_setup(char *str)
796 {
797 ar71xx_parse_mac_addr(str);
798 return 1;
799 }
800 __setup("kmac=", ar71xx_kmac_setup);
801
802 void __init ar71xx_init_mac(unsigned char *dst, const unsigned char *src,
803 unsigned offset)
804 {
805 u32 t;
806
807 if (!is_valid_ether_addr(src)) {
808 memset(dst, '\0', ETH_ALEN);
809 return;
810 }
811
812 t = (((u32) src[3]) << 16) + (((u32) src[4]) << 8) + ((u32) src[5]);
813 t += offset;
814
815 dst[0] = src[0];
816 dst[1] = src[1];
817 dst[2] = src[2];
818 dst[3] = (t >> 16) & 0xff;
819 dst[4] = (t >> 8) & 0xff;
820 dst[5] = t & 0xff;
821 }
OpenWrt Source Repository