2 * Atheros AR71xx SoC specific interrupt handling
4 * Copyright (C) 2008-2009 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 * Parts of this file are based on Atheros' 2.6.15 BSP
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/interrupt.h>
17 #include <linux/irq.h>
19 #include <asm/irq_cpu.h>
20 #include <asm/mipsregs.h>
22 #include <asm/mach-ar71xx/ar71xx.h>
25 static void ar71xx_pci_irq_dispatch(void)
29 pending
= ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_STATUS
) &
30 ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE
);
32 if (pending
& PCI_INT_DEV0
)
33 do_IRQ(AR71XX_PCI_IRQ_DEV0
);
35 else if (pending
& PCI_INT_DEV1
)
36 do_IRQ(AR71XX_PCI_IRQ_DEV1
);
38 else if (pending
& PCI_INT_DEV2
)
39 do_IRQ(AR71XX_PCI_IRQ_DEV2
);
41 else if (pending
& PCI_INT_CORE
)
42 do_IRQ(AR71XX_PCI_IRQ_CORE
);
48 static void ar71xx_pci_irq_unmask(unsigned int irq
)
50 irq
-= AR71XX_PCI_IRQ_BASE
;
51 ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE
,
52 ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE
) | (1 << irq
));
55 ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE
);
58 static void ar71xx_pci_irq_mask(unsigned int irq
)
60 irq
-= AR71XX_PCI_IRQ_BASE
;
61 ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE
,
62 ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE
) & ~(1 << irq
));
65 ar71xx_reset_rr(AR71XX_RESET_REG_PCI_INT_ENABLE
);
68 static struct irq_chip ar71xx_pci_irq_chip
= {
69 .name
= "AR71XX PCI ",
70 .mask
= ar71xx_pci_irq_mask
,
71 .unmask
= ar71xx_pci_irq_unmask
,
72 .mask_ack
= ar71xx_pci_irq_mask
,
75 static struct irqaction ar71xx_pci_irqaction
= {
77 .name
= "cascade [AR71XX PCI]",
80 static void __init
ar71xx_pci_irq_init(void)
84 ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_ENABLE
, 0);
85 ar71xx_reset_wr(AR71XX_RESET_REG_PCI_INT_STATUS
, 0);
87 for (i
= AR71XX_PCI_IRQ_BASE
;
88 i
< AR71XX_PCI_IRQ_BASE
+ AR71XX_PCI_IRQ_COUNT
; i
++) {
89 irq_desc
[i
].status
= IRQ_DISABLED
;
90 set_irq_chip_and_handler(i
, &ar71xx_pci_irq_chip
,
94 setup_irq(AR71XX_CPU_IRQ_PCI
, &ar71xx_pci_irqaction
);
96 #endif /* CONFIG_PCI */
98 static void ar71xx_gpio_irq_dispatch(void)
102 pending
= ar71xx_gpio_rr(GPIO_REG_INT_PENDING
)
103 & ar71xx_gpio_rr(GPIO_REG_INT_ENABLE
);
106 do_IRQ(AR71XX_GPIO_IRQ_BASE
+ fls(pending
) - 1);
108 spurious_interrupt();
111 static void ar71xx_gpio_irq_unmask(unsigned int irq
)
113 irq
-= AR71XX_GPIO_IRQ_BASE
;
114 ar71xx_gpio_wr(GPIO_REG_INT_ENABLE
,
115 ar71xx_gpio_rr(GPIO_REG_INT_ENABLE
) | (1 << irq
));
118 static void ar71xx_gpio_irq_mask(unsigned int irq
)
120 irq
-= AR71XX_GPIO_IRQ_BASE
;
121 ar71xx_gpio_wr(GPIO_REG_INT_ENABLE
,
122 ar71xx_gpio_rr(GPIO_REG_INT_ENABLE
) & ~(1 << irq
));
126 static int ar71xx_gpio_irq_set_type(unsigned int irq
, unsigned int flow_type
)
128 /* TODO: implement */
132 #define ar71xx_gpio_irq_set_type NULL
135 struct irq_chip ar71xx_gpio_irq_chip
= {
136 .name
= "AR71XX GPIO",
137 .unmask
= ar71xx_gpio_irq_unmask
,
138 .mask
= ar71xx_gpio_irq_mask
,
139 .mask_ack
= ar71xx_gpio_irq_mask
,
140 .set_type
= ar71xx_gpio_irq_set_type
,
143 static struct irqaction ar71xx_gpio_irqaction
= {
144 .handler
= no_action
,
145 .name
= "cascade [AR71XX GPIO]",
148 #define GPIO_IRQ_INIT_STATUS (IRQ_LEVEL | IRQ_TYPE_LEVEL_HIGH | IRQ_DISABLED)
149 #define GPIO_INT_ALL 0xffff
151 static void __init
ar71xx_gpio_irq_init(void)
155 ar71xx_gpio_wr(GPIO_REG_INT_ENABLE
, 0);
156 ar71xx_gpio_wr(GPIO_REG_INT_PENDING
, 0);
158 /* setup type of all GPIO interrupts to level sensitive */
159 ar71xx_gpio_wr(GPIO_REG_INT_TYPE
, GPIO_INT_ALL
);
161 /* setup polarity of all GPIO interrupts to active high */
162 ar71xx_gpio_wr(GPIO_REG_INT_POLARITY
, GPIO_INT_ALL
);
164 for (i
= AR71XX_GPIO_IRQ_BASE
;
165 i
< AR71XX_GPIO_IRQ_BASE
+ AR71XX_GPIO_IRQ_COUNT
; i
++) {
166 irq_desc
[i
].status
= GPIO_IRQ_INIT_STATUS
;
167 set_irq_chip_and_handler(i
, &ar71xx_gpio_irq_chip
,
171 setup_irq(AR71XX_MISC_IRQ_GPIO
, &ar71xx_gpio_irqaction
);
174 static void ar71xx_misc_irq_dispatch(void)
178 pending
= ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_STATUS
)
179 & ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE
);
181 if (pending
& MISC_INT_UART
)
182 do_IRQ(AR71XX_MISC_IRQ_UART
);
184 else if (pending
& MISC_INT_DMA
)
185 do_IRQ(AR71XX_MISC_IRQ_DMA
);
187 else if (pending
& MISC_INT_PERFC
)
188 do_IRQ(AR71XX_MISC_IRQ_PERFC
);
190 else if (pending
& MISC_INT_TIMER
)
191 do_IRQ(AR71XX_MISC_IRQ_TIMER
);
193 else if (pending
& MISC_INT_OHCI
)
194 do_IRQ(AR71XX_MISC_IRQ_OHCI
);
196 else if (pending
& MISC_INT_ERROR
)
197 do_IRQ(AR71XX_MISC_IRQ_ERROR
);
199 else if (pending
& MISC_INT_GPIO
)
200 ar71xx_gpio_irq_dispatch();
202 else if (pending
& MISC_INT_WDOG
)
203 do_IRQ(AR71XX_MISC_IRQ_WDOG
);
206 spurious_interrupt();
209 static void ar71xx_misc_irq_unmask(unsigned int irq
)
211 irq
-= AR71XX_MISC_IRQ_BASE
;
212 ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE
,
213 ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE
) | (1 << irq
));
216 static void ar71xx_misc_irq_mask(unsigned int irq
)
218 irq
-= AR71XX_MISC_IRQ_BASE
;
219 ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE
,
220 ar71xx_reset_rr(AR71XX_RESET_REG_MISC_INT_ENABLE
) & ~(1 << irq
));
223 struct irq_chip ar71xx_misc_irq_chip
= {
224 .name
= "AR71XX MISC",
225 .unmask
= ar71xx_misc_irq_unmask
,
226 .mask
= ar71xx_misc_irq_mask
,
227 .mask_ack
= ar71xx_misc_irq_mask
,
230 static struct irqaction ar71xx_misc_irqaction
= {
231 .handler
= no_action
,
232 .name
= "cascade [AR71XX MISC]",
235 static void __init
ar71xx_misc_irq_init(void)
239 ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_ENABLE
, 0);
240 ar71xx_reset_wr(AR71XX_RESET_REG_MISC_INT_STATUS
, 0);
242 for (i
= AR71XX_MISC_IRQ_BASE
;
243 i
< AR71XX_MISC_IRQ_BASE
+ AR71XX_MISC_IRQ_COUNT
; i
++) {
244 irq_desc
[i
].status
= IRQ_DISABLED
;
245 set_irq_chip_and_handler(i
, &ar71xx_misc_irq_chip
,
249 setup_irq(AR71XX_CPU_IRQ_MISC
, &ar71xx_misc_irqaction
);
252 static void ar913x_wmac_irq_dispatch(void)
254 do_IRQ(AR71XX_CPU_IRQ_WMAC
);
257 static void (* ar71xx_ip2_irq_handler
)(void) = spurious_interrupt
;
259 asmlinkage
void plat_irq_dispatch(void)
261 unsigned long pending
;
263 pending
= read_c0_status() & read_c0_cause() & ST0_IM
;
265 if (pending
& STATUSF_IP7
)
266 do_IRQ(AR71XX_CPU_IRQ_TIMER
);
268 else if (pending
& STATUSF_IP2
)
269 ar71xx_ip2_irq_handler();
271 else if (pending
& STATUSF_IP4
)
272 do_IRQ(AR71XX_CPU_IRQ_GE0
);
274 else if (pending
& STATUSF_IP5
)
275 do_IRQ(AR71XX_CPU_IRQ_GE1
);
277 else if (pending
& STATUSF_IP3
)
278 do_IRQ(AR71XX_CPU_IRQ_USB
);
280 else if (pending
& STATUSF_IP6
)
281 ar71xx_misc_irq_dispatch();
284 spurious_interrupt();
287 void __init
arch_init_irq(void)
291 ar71xx_misc_irq_init();
293 switch (ar71xx_soc
) {
294 case AR71XX_SOC_AR7130
:
295 case AR71XX_SOC_AR7141
:
296 case AR71XX_SOC_AR7161
:
298 ar71xx_pci_irq_init();
299 ar71xx_ip2_irq_handler
= ar71xx_pci_irq_dispatch
;
302 case AR71XX_SOC_AR9130
:
303 case AR71XX_SOC_AR9132
:
304 ar71xx_ip2_irq_handler
= ar913x_wmac_irq_dispatch
;
310 ar71xx_gpio_irq_init();