ar71xx: WNR2000v3: fix for random WLAN MAC
[openwrt/svn-archive/archive.git] / target / linux / ar71xx / files / arch / mips / ath79 / mach-archer-c7.c
1 /*
2 * TP-LINK Archer C5/C7/TL-WDR4900 v2 board support
3 *
4 * Copyright (c) 2013 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (c) 2014 施康成 <tenninjas@tenninjas.ca>
6 * Copyright (c) 2014 Imre Kaloz <kaloz@openwrt.org>
7 *
8 * Based on the Qualcomm Atheros AP135/AP136 reference board support code
9 * Copyright (c) 2012 Qualcomm Atheros
10 *
11 * Permission to use, copy, modify, and/or distribute this software for any
12 * purpose with or without fee is hereby granted, provided that the above
13 * copyright notice and this permission notice appear in all copies.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
16 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
18 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
19 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
20 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
21 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
22 *
23 */
24
25 #include <linux/pci.h>
26 #include <linux/phy.h>
27 #include <linux/gpio.h>
28 #include <linux/platform_device.h>
29 #include <linux/ath9k_platform.h>
30 #include <linux/ar8216_platform.h>
31
32 #include <asm/mach-ath79/ar71xx_regs.h>
33
34 #include "common.h"
35 #include "dev-ap9x-pci.h"
36 #include "dev-eth.h"
37 #include "dev-gpio-buttons.h"
38 #include "dev-leds-gpio.h"
39 #include "dev-m25p80.h"
40 #include "dev-spi.h"
41 #include "dev-usb.h"
42 #include "dev-wmac.h"
43 #include "machtypes.h"
44 #include "pci.h"
45
46 #define ARCHER_C7_GPIO_LED_WLAN2G 12
47 #define ARCHER_C7_GPIO_LED_SYSTEM 14
48 #define ARCHER_C7_GPIO_LED_QSS 15
49 #define ARCHER_C7_GPIO_LED_WLAN5G 17
50 #define ARCHER_C7_GPIO_LED_USB1 18
51 #define ARCHER_C7_GPIO_LED_USB2 19
52
53 #define ARCHER_C7_GPIO_BTN_RFKILL 13
54 #define ARCHER_C7_GPIO_BTN_RESET 16
55
56 #define ARCHER_C7_GPIO_USB1_POWER 22
57 #define ARCHER_C7_GPIO_USB2_POWER 21
58
59 #define ARCHER_C7_KEYS_POLL_INTERVAL 20 /* msecs */
60 #define ARCHER_C7_KEYS_DEBOUNCE_INTERVAL (3 * ARCHER_C7_KEYS_POLL_INTERVAL)
61
62 #define ARCHER_C7_WMAC_CALDATA_OFFSET 0x1000
63 #define ARCHER_C7_PCIE_CALDATA_OFFSET 0x5000
64
65 static const char *archer_c7_part_probes[] = {
66 "tp-link",
67 NULL,
68 };
69
70 static struct flash_platform_data archer_c7_flash_data = {
71 .part_probes = archer_c7_part_probes,
72 };
73
74 static struct gpio_led archer_c7_leds_gpio[] __initdata = {
75 {
76 .name = "tp-link:blue:qss",
77 .gpio = ARCHER_C7_GPIO_LED_QSS,
78 .active_low = 1,
79 },
80 {
81 .name = "tp-link:blue:system",
82 .gpio = ARCHER_C7_GPIO_LED_SYSTEM,
83 .active_low = 1,
84 },
85 {
86 .name = "tp-link:blue:wlan2g",
87 .gpio = ARCHER_C7_GPIO_LED_WLAN2G,
88 .active_low = 1,
89 },
90 {
91 .name = "tp-link:blue:wlan5g",
92 .gpio = ARCHER_C7_GPIO_LED_WLAN5G,
93 .active_low = 1,
94 },
95 {
96 .name = "tp-link:green:usb1",
97 .gpio = ARCHER_C7_GPIO_LED_USB1,
98 .active_low = 1,
99 },
100 {
101 .name = "tp-link:green:usb2",
102 .gpio = ARCHER_C7_GPIO_LED_USB2,
103 .active_low = 1,
104 },
105 };
106
107 static struct gpio_keys_button archer_c7_gpio_keys[] __initdata = {
108 {
109 .desc = "Reset button",
110 .type = EV_KEY,
111 .code = KEY_WPS_BUTTON,
112 .debounce_interval = ARCHER_C7_KEYS_DEBOUNCE_INTERVAL,
113 .gpio = ARCHER_C7_GPIO_BTN_RESET,
114 .active_low = 1,
115 },
116 {
117 .desc = "RFKILL switch",
118 .type = EV_SW,
119 .code = KEY_RFKILL,
120 .debounce_interval = ARCHER_C7_KEYS_DEBOUNCE_INTERVAL,
121 .gpio = ARCHER_C7_GPIO_BTN_RFKILL,
122 },
123 };
124
125 static const struct ar8327_led_info archer_c7_leds_ar8327[] __initconst = {
126 AR8327_LED_INFO(PHY0_0, HW, "tp-link:blue:wan"),
127 AR8327_LED_INFO(PHY1_0, HW, "tp-link:blue:lan1"),
128 AR8327_LED_INFO(PHY2_0, HW, "tp-link:blue:lan2"),
129 AR8327_LED_INFO(PHY3_0, HW, "tp-link:blue:lan3"),
130 AR8327_LED_INFO(PHY4_0, HW, "tp-link:blue:lan4"),
131 };
132
133 /* GMAC0 of the AR8327 switch is connected to the QCA9558 SoC via SGMII */
134 static struct ar8327_pad_cfg archer_c7_ar8327_pad0_cfg = {
135 .mode = AR8327_PAD_MAC_SGMII,
136 .sgmii_delay_en = true,
137 };
138
139 /* GMAC6 of the AR8327 switch is connected to the QCA9558 SoC via RGMII */
140 static struct ar8327_pad_cfg archer_c7_ar8327_pad6_cfg = {
141 .mode = AR8327_PAD_MAC_RGMII,
142 .txclk_delay_en = true,
143 .rxclk_delay_en = true,
144 .txclk_delay_sel = AR8327_CLK_DELAY_SEL1,
145 .rxclk_delay_sel = AR8327_CLK_DELAY_SEL2,
146 };
147
148 static struct ar8327_led_cfg archer_c7_ar8327_led_cfg = {
149 .led_ctrl0 = 0xc737c737,
150 .led_ctrl1 = 0x00000000,
151 .led_ctrl2 = 0x00000000,
152 .led_ctrl3 = 0x0030c300,
153 .open_drain = false,
154 };
155
156 static struct ar8327_platform_data archer_c7_ar8327_data = {
157 .pad0_cfg = &archer_c7_ar8327_pad0_cfg,
158 .pad6_cfg = &archer_c7_ar8327_pad6_cfg,
159 .port0_cfg = {
160 .force_link = 1,
161 .speed = AR8327_PORT_SPEED_1000,
162 .duplex = 1,
163 .txpause = 1,
164 .rxpause = 1,
165 },
166 .port6_cfg = {
167 .force_link = 1,
168 .speed = AR8327_PORT_SPEED_1000,
169 .duplex = 1,
170 .txpause = 1,
171 .rxpause = 1,
172 },
173 .led_cfg = &archer_c7_ar8327_led_cfg,
174 .num_leds = ARRAY_SIZE(archer_c7_leds_ar8327),
175 .leds = archer_c7_leds_ar8327,
176 };
177
178 static struct mdio_board_info archer_c7_mdio0_info[] = {
179 {
180 .bus_id = "ag71xx-mdio.0",
181 .phy_addr = 0,
182 .platform_data = &archer_c7_ar8327_data,
183 },
184 };
185
186 static void __init common_setup(bool pcie_slot)
187 {
188 u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
189 u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
190 u8 tmpmac[ETH_ALEN];
191
192 ath79_register_m25p80(&archer_c7_flash_data);
193 ath79_register_leds_gpio(-1, ARRAY_SIZE(archer_c7_leds_gpio),
194 archer_c7_leds_gpio);
195 ath79_register_gpio_keys_polled(-1, ARCHER_C7_KEYS_POLL_INTERVAL,
196 ARRAY_SIZE(archer_c7_gpio_keys),
197 archer_c7_gpio_keys);
198
199 ath79_init_mac(tmpmac, mac, -1);
200 ath79_register_wmac(art + ARCHER_C7_WMAC_CALDATA_OFFSET, tmpmac);
201
202 if (pcie_slot) {
203 ath79_register_pci();
204 } else {
205 ath79_init_mac(tmpmac, mac, -1);
206 ap9x_pci_setup_wmac_led_pin(0, 0);
207 ap91_pci_init(art + ARCHER_C7_PCIE_CALDATA_OFFSET, tmpmac);
208 }
209
210 mdiobus_register_board_info(archer_c7_mdio0_info,
211 ARRAY_SIZE(archer_c7_mdio0_info));
212 ath79_register_mdio(0, 0x0);
213
214 ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
215
216 /* GMAC0 is connected to the RMGII interface */
217 ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
218 ath79_eth0_data.phy_mask = BIT(0);
219 ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
220 ath79_eth0_pll_data.pll_1000 = 0x56000000;
221
222 ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1);
223 ath79_register_eth(0);
224
225 /* GMAC1 is connected to the SGMII interface */
226 ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
227 ath79_eth1_data.speed = SPEED_1000;
228 ath79_eth1_data.duplex = DUPLEX_FULL;
229 ath79_eth1_pll_data.pll_1000 = 0x03000101;
230
231 ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0);
232 ath79_register_eth(1);
233
234 gpio_request_one(ARCHER_C7_GPIO_USB1_POWER,
235 GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
236 "USB1 power");
237 gpio_request_one(ARCHER_C7_GPIO_USB2_POWER,
238 GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
239 "USB2 power");
240 ath79_register_usb();
241 }
242
243 static void __init archer_c5_setup(void)
244 {
245 common_setup(true);
246 }
247
248 MIPS_MACHINE(ATH79_MACH_ARCHER_C5, "ARCHER-C5", "TP-LINK Archer C5",
249 archer_c5_setup);
250
251 static void __init archer_c7_setup(void)
252 {
253 common_setup(true);
254 }
255
256 MIPS_MACHINE(ATH79_MACH_ARCHER_C7, "ARCHER-C7", "TP-LINK Archer C7",
257 archer_c7_setup);
258
259 static void __init tl_wdr4900_v2_setup(void)
260 {
261 common_setup(false);
262 }
263
264 MIPS_MACHINE(ATH79_MACH_TL_WDR4900_V2, "TL-WDR4900-v2", "TP-LINK TL-WDR4900 v2",
265 tl_wdr4900_v2_setup)
266