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[openwrt/openwrt.git] / target / linux / ar71xx / files / drivers / net / ag71xx / ag71xx.h
1 /*
2 * Atheros AR71xx built-in ethernet mac driver
3 *
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Based on Atheros' AG7100 driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #ifndef __AG71XX_H
15 #define __AG71XX_H
16
17 #include <linux/kernel.h>
18 #include <linux/version.h>
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/types.h>
22 #include <linux/random.h>
23 #include <linux/spinlock.h>
24 #include <linux/interrupt.h>
25 #include <linux/platform_device.h>
26 #include <linux/ethtool.h>
27 #include <linux/etherdevice.h>
28 #include <linux/if_vlan.h>
29 #include <linux/phy.h>
30 #include <linux/skbuff.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/workqueue.h>
33
34 #include <linux/bitops.h>
35
36 #include <asm/mach-ar71xx/ar71xx.h>
37 #include <asm/mach-ar71xx/platform.h>
38
39 #define AG71XX_DRV_NAME "ag71xx"
40 #define AG71XX_DRV_VERSION "0.5.35"
41
42 #define AG71XX_NAPI_WEIGHT 64
43 #define AG71XX_OOM_REFILL (1 + HZ/10)
44
45 #define AG71XX_INT_ERR (AG71XX_INT_RX_BE | AG71XX_INT_TX_BE)
46 #define AG71XX_INT_TX (AG71XX_INT_TX_PS)
47 #define AG71XX_INT_RX (AG71XX_INT_RX_PR | AG71XX_INT_RX_OF)
48
49 #define AG71XX_INT_POLL (AG71XX_INT_RX | AG71XX_INT_TX)
50 #define AG71XX_INT_INIT (AG71XX_INT_ERR | AG71XX_INT_POLL)
51
52 #define AG71XX_TX_MTU_LEN 1540
53 #define AG71XX_RX_PKT_RESERVE 64
54 #define AG71XX_RX_PKT_SIZE \
55 (AG71XX_RX_PKT_RESERVE + ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
56
57 #define AG71XX_TX_RING_SIZE_DEFAULT 64
58 #define AG71XX_RX_RING_SIZE_DEFAULT 128
59
60 #ifdef CONFIG_AG71XX_DEBUG
61 #define DBG(fmt, args...) printk(KERN_DEBUG fmt, ## args)
62 #else
63 #define DBG(fmt, args...) do {} while (0)
64 #endif
65
66 #define ag71xx_assert(_cond) \
67 do { \
68 if (_cond) \
69 break; \
70 printk("%s,%d: assertion failed\n", __FILE__, __LINE__); \
71 BUG(); \
72 } while (0)
73
74 struct ag71xx_desc {
75 u32 data;
76 u32 ctrl;
77 #define DESC_EMPTY BIT(31)
78 #define DESC_MORE BIT(24)
79 #define DESC_PKTLEN_M 0xfff
80 u32 next;
81 u32 pad;
82 } __attribute__((aligned(4)));
83
84 struct ag71xx_buf {
85 struct sk_buff *skb;
86 struct ag71xx_desc *desc;
87 dma_addr_t dma_addr;
88 unsigned long timestamp;
89 };
90
91 struct ag71xx_ring {
92 struct ag71xx_buf *buf;
93 u8 *descs_cpu;
94 dma_addr_t descs_dma;
95 unsigned int desc_size;
96 unsigned int curr;
97 unsigned int dirty;
98 unsigned int size;
99 };
100
101 struct ag71xx_mdio {
102 struct mii_bus *mii_bus;
103 int mii_irq[PHY_MAX_ADDR];
104 void __iomem *mdio_base;
105 struct ag71xx_mdio_platform_data *pdata;
106 };
107
108 struct ag71xx_int_stats {
109 unsigned long rx_pr;
110 unsigned long rx_be;
111 unsigned long rx_of;
112 unsigned long tx_ps;
113 unsigned long tx_be;
114 unsigned long tx_ur;
115 unsigned long total;
116 };
117
118 struct ag71xx_napi_stats {
119 unsigned long napi_calls;
120 unsigned long rx_count;
121 unsigned long rx_packets;
122 unsigned long rx_packets_max;
123 unsigned long tx_count;
124 unsigned long tx_packets;
125 unsigned long tx_packets_max;
126
127 unsigned long rx[AG71XX_NAPI_WEIGHT + 1];
128 unsigned long tx[AG71XX_NAPI_WEIGHT + 1];
129 };
130
131 struct ag71xx_debug {
132 struct dentry *debugfs_dir;
133
134 struct ag71xx_int_stats int_stats;
135 struct ag71xx_napi_stats napi_stats;
136 };
137
138 struct ag71xx {
139 void __iomem *mac_base;
140 void __iomem *mii_ctrl;
141
142 spinlock_t lock;
143 struct platform_device *pdev;
144 struct net_device *dev;
145 struct napi_struct napi;
146 u32 msg_enable;
147
148 struct ag71xx_ring rx_ring;
149 struct ag71xx_ring tx_ring;
150
151 struct mii_bus *mii_bus;
152 struct phy_device *phy_dev;
153 void *phy_priv;
154
155 unsigned int link;
156 unsigned int speed;
157 int duplex;
158
159 struct work_struct restart_work;
160 struct delayed_work link_work;
161 struct timer_list oom_timer;
162
163 #ifdef CONFIG_AG71XX_DEBUG_FS
164 struct ag71xx_debug debug;
165 #endif
166 };
167
168 extern struct ethtool_ops ag71xx_ethtool_ops;
169 void ag71xx_link_adjust(struct ag71xx *ag);
170
171 int ag71xx_mdio_driver_init(void) __init;
172 void ag71xx_mdio_driver_exit(void);
173
174 int ag71xx_phy_connect(struct ag71xx *ag);
175 void ag71xx_phy_disconnect(struct ag71xx *ag);
176 void ag71xx_phy_start(struct ag71xx *ag);
177 void ag71xx_phy_stop(struct ag71xx *ag);
178
179 static inline struct ag71xx_platform_data *ag71xx_get_pdata(struct ag71xx *ag)
180 {
181 return ag->pdev->dev.platform_data;
182 }
183
184 static inline int ag71xx_desc_empty(struct ag71xx_desc *desc)
185 {
186 return (desc->ctrl & DESC_EMPTY) != 0;
187 }
188
189 static inline int ag71xx_desc_pktlen(struct ag71xx_desc *desc)
190 {
191 return desc->ctrl & DESC_PKTLEN_M;
192 }
193
194 /* Register offsets */
195 #define AG71XX_REG_MAC_CFG1 0x0000
196 #define AG71XX_REG_MAC_CFG2 0x0004
197 #define AG71XX_REG_MAC_IPG 0x0008
198 #define AG71XX_REG_MAC_HDX 0x000c
199 #define AG71XX_REG_MAC_MFL 0x0010
200 #define AG71XX_REG_MII_CFG 0x0020
201 #define AG71XX_REG_MII_CMD 0x0024
202 #define AG71XX_REG_MII_ADDR 0x0028
203 #define AG71XX_REG_MII_CTRL 0x002c
204 #define AG71XX_REG_MII_STATUS 0x0030
205 #define AG71XX_REG_MII_IND 0x0034
206 #define AG71XX_REG_MAC_IFCTL 0x0038
207 #define AG71XX_REG_MAC_ADDR1 0x0040
208 #define AG71XX_REG_MAC_ADDR2 0x0044
209 #define AG71XX_REG_FIFO_CFG0 0x0048
210 #define AG71XX_REG_FIFO_CFG1 0x004c
211 #define AG71XX_REG_FIFO_CFG2 0x0050
212 #define AG71XX_REG_FIFO_CFG3 0x0054
213 #define AG71XX_REG_FIFO_CFG4 0x0058
214 #define AG71XX_REG_FIFO_CFG5 0x005c
215 #define AG71XX_REG_FIFO_RAM0 0x0060
216 #define AG71XX_REG_FIFO_RAM1 0x0064
217 #define AG71XX_REG_FIFO_RAM2 0x0068
218 #define AG71XX_REG_FIFO_RAM3 0x006c
219 #define AG71XX_REG_FIFO_RAM4 0x0070
220 #define AG71XX_REG_FIFO_RAM5 0x0074
221 #define AG71XX_REG_FIFO_RAM6 0x0078
222 #define AG71XX_REG_FIFO_RAM7 0x007c
223
224 #define AG71XX_REG_TX_CTRL 0x0180
225 #define AG71XX_REG_TX_DESC 0x0184
226 #define AG71XX_REG_TX_STATUS 0x0188
227 #define AG71XX_REG_RX_CTRL 0x018c
228 #define AG71XX_REG_RX_DESC 0x0190
229 #define AG71XX_REG_RX_STATUS 0x0194
230 #define AG71XX_REG_INT_ENABLE 0x0198
231 #define AG71XX_REG_INT_STATUS 0x019c
232
233 #define MAC_CFG1_TXE BIT(0) /* Tx Enable */
234 #define MAC_CFG1_STX BIT(1) /* Synchronize Tx Enable */
235 #define MAC_CFG1_RXE BIT(2) /* Rx Enable */
236 #define MAC_CFG1_SRX BIT(3) /* Synchronize Rx Enable */
237 #define MAC_CFG1_TFC BIT(4) /* Tx Flow Control Enable */
238 #define MAC_CFG1_RFC BIT(5) /* Rx Flow Control Enable */
239 #define MAC_CFG1_LB BIT(8) /* Loopback mode */
240 #define MAC_CFG1_SR BIT(31) /* Soft Reset */
241
242 #define MAC_CFG2_FDX BIT(0)
243 #define MAC_CFG2_CRC_EN BIT(1)
244 #define MAC_CFG2_PAD_CRC_EN BIT(2)
245 #define MAC_CFG2_LEN_CHECK BIT(4)
246 #define MAC_CFG2_HUGE_FRAME_EN BIT(5)
247 #define MAC_CFG2_IF_1000 BIT(9)
248 #define MAC_CFG2_IF_10_100 BIT(8)
249
250 #define FIFO_CFG0_WTM BIT(0) /* Watermark Module */
251 #define FIFO_CFG0_RXS BIT(1) /* Rx System Module */
252 #define FIFO_CFG0_RXF BIT(2) /* Rx Fabric Module */
253 #define FIFO_CFG0_TXS BIT(3) /* Tx System Module */
254 #define FIFO_CFG0_TXF BIT(4) /* Tx Fabric Module */
255 #define FIFO_CFG0_ALL (FIFO_CFG0_WTM | FIFO_CFG0_RXS | FIFO_CFG0_RXF \
256 | FIFO_CFG0_TXS | FIFO_CFG0_TXF)
257
258 #define FIFO_CFG0_ENABLE_SHIFT 8
259
260 #define FIFO_CFG4_DE BIT(0) /* Drop Event */
261 #define FIFO_CFG4_DV BIT(1) /* RX_DV Event */
262 #define FIFO_CFG4_FC BIT(2) /* False Carrier */
263 #define FIFO_CFG4_CE BIT(3) /* Code Error */
264 #define FIFO_CFG4_CR BIT(4) /* CRC error */
265 #define FIFO_CFG4_LM BIT(5) /* Length Mismatch */
266 #define FIFO_CFG4_LO BIT(6) /* Length out of range */
267 #define FIFO_CFG4_OK BIT(7) /* Packet is OK */
268 #define FIFO_CFG4_MC BIT(8) /* Multicast Packet */
269 #define FIFO_CFG4_BC BIT(9) /* Broadcast Packet */
270 #define FIFO_CFG4_DR BIT(10) /* Dribble */
271 #define FIFO_CFG4_LE BIT(11) /* Long Event */
272 #define FIFO_CFG4_CF BIT(12) /* Control Frame */
273 #define FIFO_CFG4_PF BIT(13) /* Pause Frame */
274 #define FIFO_CFG4_UO BIT(14) /* Unsupported Opcode */
275 #define FIFO_CFG4_VT BIT(15) /* VLAN tag detected */
276 #define FIFO_CFG4_FT BIT(16) /* Frame Truncated */
277 #define FIFO_CFG4_UC BIT(17) /* Unicast Packet */
278
279 #define FIFO_CFG5_DE BIT(0) /* Drop Event */
280 #define FIFO_CFG5_DV BIT(1) /* RX_DV Event */
281 #define FIFO_CFG5_FC BIT(2) /* False Carrier */
282 #define FIFO_CFG5_CE BIT(3) /* Code Error */
283 #define FIFO_CFG5_LM BIT(4) /* Length Mismatch */
284 #define FIFO_CFG5_LO BIT(5) /* Length Out of Range */
285 #define FIFO_CFG5_OK BIT(6) /* Packet is OK */
286 #define FIFO_CFG5_MC BIT(7) /* Multicast Packet */
287 #define FIFO_CFG5_BC BIT(8) /* Broadcast Packet */
288 #define FIFO_CFG5_DR BIT(9) /* Dribble */
289 #define FIFO_CFG5_CF BIT(10) /* Control Frame */
290 #define FIFO_CFG5_PF BIT(11) /* Pause Frame */
291 #define FIFO_CFG5_UO BIT(12) /* Unsupported Opcode */
292 #define FIFO_CFG5_VT BIT(13) /* VLAN tag detected */
293 #define FIFO_CFG5_LE BIT(14) /* Long Event */
294 #define FIFO_CFG5_FT BIT(15) /* Frame Truncated */
295 #define FIFO_CFG5_16 BIT(16) /* unknown */
296 #define FIFO_CFG5_17 BIT(17) /* unknown */
297 #define FIFO_CFG5_SF BIT(18) /* Short Frame */
298 #define FIFO_CFG5_BM BIT(19) /* Byte Mode */
299
300 #define AG71XX_INT_TX_PS BIT(0)
301 #define AG71XX_INT_TX_UR BIT(1)
302 #define AG71XX_INT_TX_BE BIT(3)
303 #define AG71XX_INT_RX_PR BIT(4)
304 #define AG71XX_INT_RX_OF BIT(6)
305 #define AG71XX_INT_RX_BE BIT(7)
306
307 #define MAC_IFCTL_SPEED BIT(16)
308
309 #define MII_CFG_CLK_DIV_4 0
310 #define MII_CFG_CLK_DIV_6 2
311 #define MII_CFG_CLK_DIV_8 3
312 #define MII_CFG_CLK_DIV_10 4
313 #define MII_CFG_CLK_DIV_14 5
314 #define MII_CFG_CLK_DIV_20 6
315 #define MII_CFG_CLK_DIV_28 7
316 #define MII_CFG_RESET BIT(31)
317
318 #define MII_CMD_WRITE 0x0
319 #define MII_CMD_READ 0x1
320 #define MII_ADDR_SHIFT 8
321 #define MII_IND_BUSY BIT(0)
322 #define MII_IND_INVALID BIT(2)
323
324 #define TX_CTRL_TXE BIT(0) /* Tx Enable */
325
326 #define TX_STATUS_PS BIT(0) /* Packet Sent */
327 #define TX_STATUS_UR BIT(1) /* Tx Underrun */
328 #define TX_STATUS_BE BIT(3) /* Bus Error */
329
330 #define RX_CTRL_RXE BIT(0) /* Rx Enable */
331
332 #define RX_STATUS_PR BIT(0) /* Packet Received */
333 #define RX_STATUS_OF BIT(2) /* Rx Overflow */
334 #define RX_STATUS_BE BIT(3) /* Bus Error */
335
336 #define MII_CTRL_IF_MASK 3
337 #define MII_CTRL_SPEED_SHIFT 4
338 #define MII_CTRL_SPEED_MASK 3
339 #define MII_CTRL_SPEED_10 0
340 #define MII_CTRL_SPEED_100 1
341 #define MII_CTRL_SPEED_1000 2
342
343 static inline void ag71xx_check_reg_offset(struct ag71xx *ag, unsigned reg)
344 {
345 switch (reg) {
346 case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
347 case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_INT_STATUS:
348 break;
349
350 default:
351 BUG();
352 }
353 }
354
355 static inline void ag71xx_wr(struct ag71xx *ag, unsigned reg, u32 value)
356 {
357 ag71xx_check_reg_offset(ag, reg);
358
359 __raw_writel(value, ag->mac_base + reg);
360 /* flush write */
361 (void) __raw_readl(ag->mac_base + reg);
362 }
363
364 static inline u32 ag71xx_rr(struct ag71xx *ag, unsigned reg)
365 {
366 ag71xx_check_reg_offset(ag, reg);
367
368 return __raw_readl(ag->mac_base + reg);
369 }
370
371 static inline void ag71xx_sb(struct ag71xx *ag, unsigned reg, u32 mask)
372 {
373 void __iomem *r;
374
375 ag71xx_check_reg_offset(ag, reg);
376
377 r = ag->mac_base + reg;
378 __raw_writel(__raw_readl(r) | mask, r);
379 /* flush write */
380 (void)__raw_readl(r);
381 }
382
383 static inline void ag71xx_cb(struct ag71xx *ag, unsigned reg, u32 mask)
384 {
385 void __iomem *r;
386
387 ag71xx_check_reg_offset(ag, reg);
388
389 r = ag->mac_base + reg;
390 __raw_writel(__raw_readl(r) & ~mask, r);
391 /* flush write */
392 (void) __raw_readl(r);
393 }
394
395 static inline void ag71xx_int_enable(struct ag71xx *ag, u32 ints)
396 {
397 ag71xx_sb(ag, AG71XX_REG_INT_ENABLE, ints);
398 }
399
400 static inline void ag71xx_int_disable(struct ag71xx *ag, u32 ints)
401 {
402 ag71xx_cb(ag, AG71XX_REG_INT_ENABLE, ints);
403 }
404
405 static inline void ag71xx_mii_ctrl_wr(struct ag71xx *ag, u32 value)
406 {
407 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
408
409 if (pdata->is_ar724x)
410 return;
411
412 __raw_writel(value, ag->mii_ctrl);
413
414 /* flush write */
415 __raw_readl(ag->mii_ctrl);
416 }
417
418 static inline u32 ag71xx_mii_ctrl_rr(struct ag71xx *ag)
419 {
420 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
421
422 if (pdata->is_ar724x)
423 return 0xffffffff;
424
425 return __raw_readl(ag->mii_ctrl);
426 }
427
428 static inline void ag71xx_mii_ctrl_set_if(struct ag71xx *ag,
429 unsigned int mii_if)
430 {
431 u32 t;
432
433 t = ag71xx_mii_ctrl_rr(ag);
434 t &= ~(MII_CTRL_IF_MASK);
435 t |= (mii_if & MII_CTRL_IF_MASK);
436 ag71xx_mii_ctrl_wr(ag, t);
437 }
438
439 static inline void ag71xx_mii_ctrl_set_speed(struct ag71xx *ag,
440 unsigned int speed)
441 {
442 u32 t;
443
444 t = ag71xx_mii_ctrl_rr(ag);
445 t &= ~(MII_CTRL_SPEED_MASK << MII_CTRL_SPEED_SHIFT);
446 t |= (speed & MII_CTRL_SPEED_MASK) << MII_CTRL_SPEED_SHIFT;
447 ag71xx_mii_ctrl_wr(ag, t);
448 }
449
450 #ifdef CONFIG_AG71XX_AR8216_SUPPORT
451 void ag71xx_add_ar8216_header(struct ag71xx *ag, struct sk_buff *skb);
452 int ag71xx_remove_ar8216_header(struct ag71xx *ag, struct sk_buff *skb,
453 int pktlen);
454 static inline int ag71xx_has_ar8216(struct ag71xx *ag)
455 {
456 return ag71xx_get_pdata(ag)->has_ar8216;
457 }
458 #else
459 static inline void ag71xx_add_ar8216_header(struct ag71xx *ag,
460 struct sk_buff *skb)
461 {
462 }
463
464 static inline int ag71xx_remove_ar8216_header(struct ag71xx *ag,
465 struct sk_buff *skb,
466 int pktlen)
467 {
468 return 0;
469 }
470 static inline int ag71xx_has_ar8216(struct ag71xx *ag)
471 {
472 return 0;
473 }
474 #endif
475
476 #ifdef CONFIG_AG71XX_DEBUG_FS
477 int ag71xx_debugfs_root_init(void);
478 void ag71xx_debugfs_root_exit(void);
479 int ag71xx_debugfs_init(struct ag71xx *ag);
480 void ag71xx_debugfs_exit(struct ag71xx *ag);
481 void ag71xx_debugfs_update_int_stats(struct ag71xx *ag, u32 status);
482 void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag, int rx, int tx);
483 #else
484 static inline int ag71xx_debugfs_root_init(void) { return 0; }
485 static inline void ag71xx_debugfs_root_exit(void) {}
486 static inline int ag71xx_debugfs_init(struct ag71xx *ag) { return 0; }
487 static inline void ag71xx_debugfs_exit(struct ag71xx *ag) {}
488 static inline void ag71xx_debugfs_update_int_stats(struct ag71xx *ag,
489 u32 status) {}
490 static inline void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag,
491 int rx, int tx) {}
492 #endif /* CONFIG_AG71XX_DEBUG_FS */
493
494 void ag71xx_ar7240_start(struct ag71xx *ag);
495 void ag71xx_ar7240_stop(struct ag71xx *ag);
496 int ag71xx_ar7240_init(struct ag71xx *ag);
497 void ag71xx_ar7240_cleanup(struct ag71xx *ag);
498
499 int ag71xx_mdio_mii_read(struct ag71xx_mdio *am, int addr, int reg);
500 void ag71xx_mdio_mii_write(struct ag71xx_mdio *am, int addr, int reg, u16 val);
501
502 u16 ar7240sw_phy_read(struct mii_bus *mii, unsigned phy_addr,
503 unsigned reg_addr);
504 int ar7240sw_phy_write(struct mii_bus *mii, unsigned phy_addr,
505 unsigned reg_addr, u16 reg_val);
506
507 #endif /* _AG71XX_H */
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