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[openwrt/staging/yousong.git] / target / linux / ar71xx / files / drivers / net / ag71xx / ag71xx_ar7240.c
1 /*
2 * Driver for the built-in ethernet switch of the Atheros AR7240 SoC
3 * Copyright (c) 2010 Gabor Juhos <juhosg@openwrt.org>
4 * Copyright (c) 2010 Felix Fietkau <nbd@openwrt.org>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 */
11
12 #include <linux/etherdevice.h>
13 #include <linux/list.h>
14 #include <linux/netdevice.h>
15 #include <linux/phy.h>
16 #include <linux/mii.h>
17 #include <linux/bitops.h>
18 #include <linux/switch.h>
19 #include "ag71xx.h"
20
21 #define BITM(_count) (BIT(_count) - 1)
22 #define BITS(_shift, _count) (BITM(_count) << _shift)
23
24 #define AR7240_REG_MASK_CTRL 0x00
25 #define AR7240_MASK_CTRL_REVISION_M BITM(8)
26 #define AR7240_MASK_CTRL_VERSION_M BITM(8)
27 #define AR7240_MASK_CTRL_VERSION_S 8
28 #define AR7240_MASK_CTRL_SOFT_RESET BIT(31)
29
30 #define AR7240_REG_MAC_ADDR0 0x20
31 #define AR7240_REG_MAC_ADDR1 0x24
32
33 #define AR7240_REG_FLOOD_MASK 0x2c
34 #define AR7240_FLOOD_MASK_BROAD_TO_CPU BIT(26)
35
36 #define AR7240_REG_GLOBAL_CTRL 0x30
37 #define AR7240_GLOBAL_CTRL_MTU_M BITM(12)
38
39 #define AR7240_REG_VTU 0x0040
40 #define AR7240_VTU_OP BITM(3)
41 #define AR7240_VTU_OP_NOOP 0x0
42 #define AR7240_VTU_OP_FLUSH 0x1
43 #define AR7240_VTU_OP_LOAD 0x2
44 #define AR7240_VTU_OP_PURGE 0x3
45 #define AR7240_VTU_OP_REMOVE_PORT 0x4
46 #define AR7240_VTU_ACTIVE BIT(3)
47 #define AR7240_VTU_FULL BIT(4)
48 #define AR7240_VTU_PORT BITS(8, 4)
49 #define AR7240_VTU_PORT_S 8
50 #define AR7240_VTU_VID BITS(16, 12)
51 #define AR7240_VTU_VID_S 16
52 #define AR7240_VTU_PRIO BITS(28, 3)
53 #define AR7240_VTU_PRIO_S 28
54 #define AR7240_VTU_PRIO_EN BIT(31)
55
56 #define AR7240_REG_VTU_DATA 0x0044
57 #define AR7240_VTUDATA_MEMBER BITS(0, 10)
58 #define AR7240_VTUDATA_VALID BIT(11)
59
60 #define AR7240_REG_ATU 0x50
61 #define AR7240_ATU_FLUSH_ALL 0x1
62
63 #define AR7240_REG_AT_CTRL 0x5c
64 #define AR7240_AT_CTRL_AGE_TIME BITS(0, 15)
65 #define AR7240_AT_CTRL_AGE_EN BIT(17)
66 #define AR7240_AT_CTRL_LEARN_CHANGE BIT(18)
67 #define AR7240_AT_CTRL_ARP_EN BIT(20)
68
69 #define AR7240_REG_TAG_PRIORITY 0x70
70
71 #define AR7240_REG_SERVICE_TAG 0x74
72 #define AR7240_SERVICE_TAG_M BITM(16)
73
74 #define AR7240_REG_CPU_PORT 0x78
75 #define AR7240_MIRROR_PORT_S 4
76 #define AR7240_CPU_PORT_EN BIT(8)
77
78 #define AR7240_REG_MIB_FUNCTION0 0x80
79 #define AR7240_MIB_TIMER_M BITM(16)
80 #define AR7240_MIB_AT_HALF_EN BIT(16)
81 #define AR7240_MIB_BUSY BIT(17)
82 #define AR7240_MIB_FUNC_S 24
83 #define AR7240_MIB_FUNC_NO_OP 0x0
84 #define AR7240_MIB_FUNC_FLUSH 0x1
85 #define AR7240_MIB_FUNC_CAPTURE 0x3
86
87 #define AR7240_REG_MDIO_CTRL 0x98
88 #define AR7240_MDIO_CTRL_DATA_M BITM(16)
89 #define AR7240_MDIO_CTRL_REG_ADDR_S 16
90 #define AR7240_MDIO_CTRL_PHY_ADDR_S 21
91 #define AR7240_MDIO_CTRL_CMD_WRITE 0
92 #define AR7240_MDIO_CTRL_CMD_READ BIT(27)
93 #define AR7240_MDIO_CTRL_MASTER_EN BIT(30)
94 #define AR7240_MDIO_CTRL_BUSY BIT(31)
95
96 #define AR7240_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100)
97
98 #define AR7240_REG_PORT_STATUS(_port) (AR7240_REG_PORT_BASE((_port)) + 0x00)
99 #define AR7240_PORT_STATUS_SPEED_M BITM(2)
100 #define AR7240_PORT_STATUS_SPEED_10 0
101 #define AR7240_PORT_STATUS_SPEED_100 1
102 #define AR7240_PORT_STATUS_SPEED_1000 2
103 #define AR7240_PORT_STATUS_TXMAC BIT(2)
104 #define AR7240_PORT_STATUS_RXMAC BIT(3)
105 #define AR7240_PORT_STATUS_TXFLOW BIT(4)
106 #define AR7240_PORT_STATUS_RXFLOW BIT(5)
107 #define AR7240_PORT_STATUS_DUPLEX BIT(6)
108 #define AR7240_PORT_STATUS_LINK_UP BIT(8)
109 #define AR7240_PORT_STATUS_LINK_AUTO BIT(9)
110 #define AR7240_PORT_STATUS_LINK_PAUSE BIT(10)
111
112 #define AR7240_REG_PORT_CTRL(_port) (AR7240_REG_PORT_BASE((_port)) + 0x04)
113 #define AR7240_PORT_CTRL_STATE_M BITM(3)
114 #define AR7240_PORT_CTRL_STATE_DISABLED 0
115 #define AR7240_PORT_CTRL_STATE_BLOCK 1
116 #define AR7240_PORT_CTRL_STATE_LISTEN 2
117 #define AR7240_PORT_CTRL_STATE_LEARN 3
118 #define AR7240_PORT_CTRL_STATE_FORWARD 4
119 #define AR7240_PORT_CTRL_LEARN_LOCK BIT(7)
120 #define AR7240_PORT_CTRL_VLAN_MODE_S 8
121 #define AR7240_PORT_CTRL_VLAN_MODE_KEEP 0
122 #define AR7240_PORT_CTRL_VLAN_MODE_STRIP 1
123 #define AR7240_PORT_CTRL_VLAN_MODE_ADD 2
124 #define AR7240_PORT_CTRL_VLAN_MODE_DOUBLE_TAG 3
125 #define AR7240_PORT_CTRL_IGMP_SNOOP BIT(10)
126 #define AR7240_PORT_CTRL_HEADER BIT(11)
127 #define AR7240_PORT_CTRL_MAC_LOOP BIT(12)
128 #define AR7240_PORT_CTRL_SINGLE_VLAN BIT(13)
129 #define AR7240_PORT_CTRL_LEARN BIT(14)
130 #define AR7240_PORT_CTRL_DOUBLE_TAG BIT(15)
131 #define AR7240_PORT_CTRL_MIRROR_TX BIT(16)
132 #define AR7240_PORT_CTRL_MIRROR_RX BIT(17)
133
134 #define AR7240_REG_PORT_VLAN(_port) (AR7240_REG_PORT_BASE((_port)) + 0x08)
135
136 #define AR7240_PORT_VLAN_DEFAULT_ID_S 0
137 #define AR7240_PORT_VLAN_DEST_PORTS_S 16
138 #define AR7240_PORT_VLAN_MODE_S 30
139 #define AR7240_PORT_VLAN_MODE_PORT_ONLY 0
140 #define AR7240_PORT_VLAN_MODE_PORT_FALLBACK 1
141 #define AR7240_PORT_VLAN_MODE_VLAN_ONLY 2
142 #define AR7240_PORT_VLAN_MODE_SECURE 3
143
144
145 #define AR7240_REG_STATS_BASE(_port) (0x20000 + (_port) * 0x100)
146
147 #define AR7240_STATS_RXBROAD 0x00
148 #define AR7240_STATS_RXPAUSE 0x04
149 #define AR7240_STATS_RXMULTI 0x08
150 #define AR7240_STATS_RXFCSERR 0x0c
151 #define AR7240_STATS_RXALIGNERR 0x10
152 #define AR7240_STATS_RXRUNT 0x14
153 #define AR7240_STATS_RXFRAGMENT 0x18
154 #define AR7240_STATS_RX64BYTE 0x1c
155 #define AR7240_STATS_RX128BYTE 0x20
156 #define AR7240_STATS_RX256BYTE 0x24
157 #define AR7240_STATS_RX512BYTE 0x28
158 #define AR7240_STATS_RX1024BYTE 0x2c
159 #define AR7240_STATS_RX1518BYTE 0x30
160 #define AR7240_STATS_RXMAXBYTE 0x34
161 #define AR7240_STATS_RXTOOLONG 0x38
162 #define AR7240_STATS_RXGOODBYTE 0x3c
163 #define AR7240_STATS_RXBADBYTE 0x44
164 #define AR7240_STATS_RXOVERFLOW 0x4c
165 #define AR7240_STATS_FILTERED 0x50
166 #define AR7240_STATS_TXBROAD 0x54
167 #define AR7240_STATS_TXPAUSE 0x58
168 #define AR7240_STATS_TXMULTI 0x5c
169 #define AR7240_STATS_TXUNDERRUN 0x60
170 #define AR7240_STATS_TX64BYTE 0x64
171 #define AR7240_STATS_TX128BYTE 0x68
172 #define AR7240_STATS_TX256BYTE 0x6c
173 #define AR7240_STATS_TX512BYTE 0x70
174 #define AR7240_STATS_TX1024BYTE 0x74
175 #define AR7240_STATS_TX1518BYTE 0x78
176 #define AR7240_STATS_TXMAXBYTE 0x7c
177 #define AR7240_STATS_TXOVERSIZE 0x80
178 #define AR7240_STATS_TXBYTE 0x84
179 #define AR7240_STATS_TXCOLLISION 0x8c
180 #define AR7240_STATS_TXABORTCOL 0x90
181 #define AR7240_STATS_TXMULTICOL 0x94
182 #define AR7240_STATS_TXSINGLECOL 0x98
183 #define AR7240_STATS_TXEXCDEFER 0x9c
184 #define AR7240_STATS_TXDEFER 0xa0
185 #define AR7240_STATS_TXLATECOL 0xa4
186
187 #define AR7240_PORT_CPU 0
188 #define AR7240_NUM_PORTS 6
189 #define AR7240_NUM_PHYS 5
190
191 #define AR7240_PHY_ID1 0x004d
192 #define AR7240_PHY_ID2 0xd041
193
194 #define AR7240_PORT_MASK(_port) BIT((_port))
195 #define AR7240_PORT_MASK_ALL BITM(AR7240_NUM_PORTS)
196 #define AR7240_PORT_MASK_BUT(_port) (AR7240_PORT_MASK_ALL & ~BIT((_port)))
197
198 #define AR7240_MAX_VLANS 16
199
200 #define sw_to_ar7240(_dev) container_of(_dev, struct ar7240sw, swdev)
201
202 struct ar7240sw {
203 struct mii_bus *mii_bus;
204 struct switch_dev swdev;
205 bool vlan;
206 u16 vlan_id[AR7240_MAX_VLANS];
207 u8 vlan_table[AR7240_MAX_VLANS];
208 u8 vlan_tagged;
209 u16 pvid[AR7240_NUM_PORTS];
210 };
211
212 struct ar7240sw_hw_stat {
213 char string[ETH_GSTRING_LEN];
214 int sizeof_stat;
215 int reg;
216 };
217
218 static DEFINE_MUTEX(reg_mutex);
219
220 static inline void ar7240sw_init(struct ar7240sw *as, struct mii_bus *mii)
221 {
222 as->mii_bus = mii;
223 }
224
225 static inline u16 mk_phy_addr(u32 reg)
226 {
227 return 0x17 & ((reg >> 4) | 0x10);
228 }
229
230 static inline u16 mk_phy_reg(u32 reg)
231 {
232 return (reg << 1) & 0x1e;
233 }
234
235 static inline u16 mk_high_addr(u32 reg)
236 {
237 return (reg >> 7) & 0x1ff;
238 }
239
240 static u32 __ar7240sw_reg_read(struct mii_bus *mii, u32 reg)
241 {
242 unsigned long flags;
243 u16 phy_addr;
244 u16 phy_reg;
245 u32 hi, lo;
246
247 reg = (reg & 0xfffffffc) >> 2;
248 phy_addr = mk_phy_addr(reg);
249 phy_reg = mk_phy_reg(reg);
250
251 local_irq_save(flags);
252 ag71xx_mdio_mii_write(mii->priv, 0x1f, 0x10, mk_high_addr(reg));
253 lo = (u32) ag71xx_mdio_mii_read(mii->priv, phy_addr, phy_reg);
254 hi = (u32) ag71xx_mdio_mii_read(mii->priv, phy_addr, phy_reg + 1);
255 local_irq_restore(flags);
256
257 return (hi << 16) | lo;
258 }
259
260 static void __ar7240sw_reg_write(struct mii_bus *mii, u32 reg, u32 val)
261 {
262 unsigned long flags;
263 u16 phy_addr;
264 u16 phy_reg;
265
266 reg = (reg & 0xfffffffc) >> 2;
267 phy_addr = mk_phy_addr(reg);
268 phy_reg = mk_phy_reg(reg);
269
270 local_irq_save(flags);
271 ag71xx_mdio_mii_write(mii->priv, 0x1f, 0x10, mk_high_addr(reg));
272 ag71xx_mdio_mii_write(mii->priv, phy_addr, phy_reg + 1, (val >> 16));
273 ag71xx_mdio_mii_write(mii->priv, phy_addr, phy_reg, (val & 0xffff));
274 local_irq_restore(flags);
275 }
276
277 static u32 ar7240sw_reg_read(struct mii_bus *mii, u32 reg_addr)
278 {
279 u32 ret;
280
281 mutex_lock(&reg_mutex);
282 ret = __ar7240sw_reg_read(mii, reg_addr);
283 mutex_unlock(&reg_mutex);
284
285 return ret;
286 }
287
288 static void ar7240sw_reg_write(struct mii_bus *mii, u32 reg_addr, u32 reg_val)
289 {
290 mutex_lock(&reg_mutex);
291 __ar7240sw_reg_write(mii, reg_addr, reg_val);
292 mutex_unlock(&reg_mutex);
293 }
294
295 static u32 ar7240sw_reg_rmw(struct mii_bus *mii, u32 reg, u32 mask, u32 val)
296 {
297 u32 t;
298
299 mutex_lock(&reg_mutex);
300 t = __ar7240sw_reg_read(mii, reg);
301 t &= ~mask;
302 t |= val;
303 __ar7240sw_reg_write(mii, reg, t);
304 mutex_unlock(&reg_mutex);
305
306 return t;
307 }
308
309 static void ar7240sw_reg_set(struct mii_bus *mii, u32 reg, u32 val)
310 {
311 u32 t;
312
313 mutex_lock(&reg_mutex);
314 t = __ar7240sw_reg_read(mii, reg);
315 t |= val;
316 __ar7240sw_reg_write(mii, reg, t);
317 mutex_unlock(&reg_mutex);
318 }
319
320 static int __ar7240sw_reg_wait(struct mii_bus *mii, u32 reg, u32 mask, u32 val,
321 unsigned timeout)
322 {
323 int i;
324
325 for (i = 0; i < timeout; i++) {
326 u32 t;
327
328 t = __ar7240sw_reg_read(mii, reg);
329 if ((t & mask) == val)
330 return 0;
331
332 msleep(1);
333 }
334
335 return -ETIMEDOUT;
336 }
337
338 static int ar7240sw_reg_wait(struct mii_bus *mii, u32 reg, u32 mask, u32 val,
339 unsigned timeout)
340 {
341 int ret;
342
343 mutex_lock(&reg_mutex);
344 ret = __ar7240sw_reg_wait(mii, reg, mask, val, timeout);
345 mutex_unlock(&reg_mutex);
346 return ret;
347 }
348
349 u16 ar7240sw_phy_read(struct mii_bus *mii, unsigned phy_addr,
350 unsigned reg_addr)
351 {
352 u32 t, val = 0xffff;
353 int err;
354
355 if (phy_addr >= AR7240_NUM_PHYS)
356 return 0xffff;
357
358 mutex_lock(&reg_mutex);
359 t = (reg_addr << AR7240_MDIO_CTRL_REG_ADDR_S) |
360 (phy_addr << AR7240_MDIO_CTRL_PHY_ADDR_S) |
361 AR7240_MDIO_CTRL_MASTER_EN |
362 AR7240_MDIO_CTRL_BUSY |
363 AR7240_MDIO_CTRL_CMD_READ;
364
365 __ar7240sw_reg_write(mii, AR7240_REG_MDIO_CTRL, t);
366 err = __ar7240sw_reg_wait(mii, AR7240_REG_MDIO_CTRL,
367 AR7240_MDIO_CTRL_BUSY, 0, 5);
368 if (!err)
369 val = __ar7240sw_reg_read(mii, AR7240_REG_MDIO_CTRL);
370 mutex_unlock(&reg_mutex);
371
372 return val & AR7240_MDIO_CTRL_DATA_M;
373 }
374
375 int ar7240sw_phy_write(struct mii_bus *mii, unsigned phy_addr,
376 unsigned reg_addr, u16 reg_val)
377 {
378 u32 t;
379 int ret;
380
381 if (phy_addr >= AR7240_NUM_PHYS)
382 return -EINVAL;
383
384 mutex_lock(&reg_mutex);
385 t = (phy_addr << AR7240_MDIO_CTRL_PHY_ADDR_S) |
386 (reg_addr << AR7240_MDIO_CTRL_REG_ADDR_S) |
387 AR7240_MDIO_CTRL_MASTER_EN |
388 AR7240_MDIO_CTRL_BUSY |
389 AR7240_MDIO_CTRL_CMD_WRITE |
390 reg_val;
391
392 __ar7240sw_reg_write(mii, AR7240_REG_MDIO_CTRL, t);
393 ret = __ar7240sw_reg_wait(mii, AR7240_REG_MDIO_CTRL,
394 AR7240_MDIO_CTRL_BUSY, 0, 5);
395 mutex_unlock(&reg_mutex);
396
397 return ret;
398 }
399
400 static void ar7240sw_disable_port(struct ar7240sw *as, unsigned port)
401 {
402 ar7240sw_reg_write(as->mii_bus, AR7240_REG_PORT_CTRL(port),
403 AR7240_PORT_CTRL_STATE_DISABLED);
404 }
405
406 static void ar7240sw_setup(struct ar7240sw *as)
407 {
408 struct mii_bus *mii = as->mii_bus;
409
410 /* Enable CPU port, and disable mirror port */
411 ar7240sw_reg_write(mii, AR7240_REG_CPU_PORT,
412 AR7240_CPU_PORT_EN |
413 (15 << AR7240_MIRROR_PORT_S));
414
415 /* Setup TAG priority mapping */
416 ar7240sw_reg_write(mii, AR7240_REG_TAG_PRIORITY, 0xfa50);
417
418 /* Enable ARP frame acknowledge, aging, MAC replacing */
419 ar7240sw_reg_write(mii, AR7240_REG_AT_CTRL,
420 0x2b /* 5 min age time */ |
421 AR7240_AT_CTRL_AGE_EN |
422 AR7240_AT_CTRL_ARP_EN |
423 AR7240_AT_CTRL_LEARN_CHANGE);
424
425 /* Enable Broadcast frames transmitted to the CPU */
426 ar7240sw_reg_set(mii, AR7240_REG_FLOOD_MASK,
427 AR7240_FLOOD_MASK_BROAD_TO_CPU);
428
429 /* setup MTU */
430 ar7240sw_reg_rmw(mii, AR7240_REG_GLOBAL_CTRL, AR7240_GLOBAL_CTRL_MTU_M,
431 1536);
432
433 /* setup Service TAG */
434 ar7240sw_reg_rmw(mii, AR7240_REG_SERVICE_TAG, AR7240_SERVICE_TAG_M, 0);
435 }
436
437 static int ar7240sw_reset(struct ar7240sw *as)
438 {
439 struct mii_bus *mii = as->mii_bus;
440 int ret;
441 int i;
442
443 /* Set all ports to disabled state. */
444 for (i = 0; i < AR7240_NUM_PORTS; i++)
445 ar7240sw_disable_port(as, i);
446
447 /* Wait for transmit queues to drain. */
448 msleep(2);
449
450 /* Reset the switch. */
451 ar7240sw_reg_write(mii, AR7240_REG_MASK_CTRL,
452 AR7240_MASK_CTRL_SOFT_RESET);
453
454 ret = ar7240sw_reg_wait(mii, AR7240_REG_MASK_CTRL,
455 AR7240_MASK_CTRL_SOFT_RESET, 0, 1000);
456
457 ar7240sw_setup(as);
458 return ret;
459 }
460
461 static void ar7240sw_setup_port(struct ar7240sw *as, unsigned port, u8 portmask)
462 {
463 struct mii_bus *mii = as->mii_bus;
464 u32 ctrl;
465 u32 vlan;
466
467 ctrl = AR7240_PORT_CTRL_STATE_FORWARD | AR7240_PORT_CTRL_LEARN |
468 AR7240_PORT_CTRL_SINGLE_VLAN;
469
470 if (port == AR7240_PORT_CPU) {
471 ar7240sw_reg_write(mii, AR7240_REG_PORT_STATUS(port),
472 AR7240_PORT_STATUS_SPEED_1000 |
473 AR7240_PORT_STATUS_TXFLOW |
474 AR7240_PORT_STATUS_RXFLOW |
475 AR7240_PORT_STATUS_TXMAC |
476 AR7240_PORT_STATUS_RXMAC |
477 AR7240_PORT_STATUS_DUPLEX);
478 } else {
479 ar7240sw_reg_write(mii, AR7240_REG_PORT_STATUS(port),
480 AR7240_PORT_STATUS_LINK_AUTO);
481 }
482
483 /* Set the default VID for this port */
484 if (as->vlan) {
485 vlan = as->vlan_id[as->pvid[port]];
486 vlan |= AR7240_PORT_VLAN_MODE_SECURE <<
487 AR7240_PORT_VLAN_MODE_S;
488 } else {
489 vlan = port;
490 vlan |= AR7240_PORT_VLAN_MODE_PORT_ONLY <<
491 AR7240_PORT_VLAN_MODE_S;
492 }
493
494 if (as->vlan && (as->vlan_tagged & BIT(port))) {
495 ctrl |= AR7240_PORT_CTRL_VLAN_MODE_ADD <<
496 AR7240_PORT_CTRL_VLAN_MODE_S;
497 } else {
498 ctrl |= AR7240_PORT_CTRL_VLAN_MODE_STRIP <<
499 AR7240_PORT_CTRL_VLAN_MODE_S;
500 }
501
502 if (!portmask) {
503 if (port == AR7240_PORT_CPU)
504 portmask = AR7240_PORT_MASK_BUT(AR7240_PORT_CPU);
505 else
506 portmask = AR7240_PORT_MASK(AR7240_PORT_CPU);
507 }
508
509 /* allow the port to talk to all other ports, but exclude its
510 * own ID to prevent frames from being reflected back to the
511 * port that they came from */
512 portmask &= AR7240_PORT_MASK_BUT(port);
513
514 /* set default VID and and destination ports for this VLAN */
515 vlan |= (portmask << AR7240_PORT_VLAN_DEST_PORTS_S);
516
517 ar7240sw_reg_write(mii, AR7240_REG_PORT_CTRL(port), ctrl);
518 ar7240sw_reg_write(mii, AR7240_REG_PORT_VLAN(port), vlan);
519 }
520
521 static int ar7240_set_addr(struct ar7240sw *as, u8 *addr)
522 {
523 struct mii_bus *mii = as->mii_bus;
524 u32 t;
525
526 t = (addr[4] << 8) | addr[5];
527 ar7240sw_reg_write(mii, AR7240_REG_MAC_ADDR0, t);
528
529 t = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
530 ar7240sw_reg_write(mii, AR7240_REG_MAC_ADDR1, t);
531
532 return 0;
533 }
534
535 static int
536 ar7240_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
537 struct switch_val *val)
538 {
539 struct ar7240sw *as = sw_to_ar7240(dev);
540 as->vlan_id[val->port_vlan] = val->value.i;
541 return 0;
542 }
543
544 static int
545 ar7240_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
546 struct switch_val *val)
547 {
548 struct ar7240sw *as = sw_to_ar7240(dev);
549 val->value.i = as->vlan_id[val->port_vlan];
550 return 0;
551 }
552
553 static int
554 ar7240_set_pvid(struct switch_dev *dev, int port, int vlan)
555 {
556 struct ar7240sw *as = sw_to_ar7240(dev);
557
558 /* make sure no invalid PVIDs get set */
559
560 if (vlan >= dev->vlans)
561 return -EINVAL;
562
563 as->pvid[port] = vlan;
564 return 0;
565 }
566
567 static int
568 ar7240_get_pvid(struct switch_dev *dev, int port, int *vlan)
569 {
570 struct ar7240sw *as = sw_to_ar7240(dev);
571 *vlan = as->pvid[port];
572 return 0;
573 }
574
575 static int
576 ar7240_get_ports(struct switch_dev *dev, struct switch_val *val)
577 {
578 struct ar7240sw *as = sw_to_ar7240(dev);
579 u8 ports = as->vlan_table[val->port_vlan];
580 int i;
581
582 val->len = 0;
583 for (i = 0; i < AR7240_NUM_PORTS; i++) {
584 struct switch_port *p;
585
586 if (!(ports & (1 << i)))
587 continue;
588
589 p = &val->value.ports[val->len++];
590 p->id = i;
591 if (as->vlan_tagged & (1 << i))
592 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
593 else
594 p->flags = 0;
595 }
596 return 0;
597 }
598
599 static int
600 ar7240_set_ports(struct switch_dev *dev, struct switch_val *val)
601 {
602 struct ar7240sw *as = sw_to_ar7240(dev);
603 u8 *vt = &as->vlan_table[val->port_vlan];
604 int i, j;
605
606 *vt = 0;
607 for (i = 0; i < val->len; i++) {
608 struct switch_port *p = &val->value.ports[i];
609
610 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED))
611 as->vlan_tagged |= (1 << p->id);
612 else {
613 as->vlan_tagged &= ~(1 << p->id);
614 as->pvid[p->id] = val->port_vlan;
615
616 /* make sure that an untagged port does not
617 * appear in other vlans */
618 for (j = 0; j < AR7240_MAX_VLANS; j++) {
619 if (j == val->port_vlan)
620 continue;
621 as->vlan_table[j] &= ~(1 << p->id);
622 }
623 }
624
625 *vt |= 1 << p->id;
626 }
627 return 0;
628 }
629
630 static int
631 ar7240_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
632 struct switch_val *val)
633 {
634 struct ar7240sw *as = sw_to_ar7240(dev);
635 as->vlan = !!val->value.i;
636 return 0;
637 }
638
639 static int
640 ar7240_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
641 struct switch_val *val)
642 {
643 struct ar7240sw *as = sw_to_ar7240(dev);
644 val->value.i = as->vlan;
645 return 0;
646 }
647
648
649 static void
650 ar7240_vtu_op(struct ar7240sw *as, u32 op, u32 val)
651 {
652 struct mii_bus *mii = as->mii_bus;
653
654 if (ar7240sw_reg_wait(mii, AR7240_REG_VTU, AR7240_VTU_ACTIVE, 0, 5))
655 return;
656
657 if ((op & AR7240_VTU_OP) == AR7240_VTU_OP_LOAD) {
658 val &= AR7240_VTUDATA_MEMBER;
659 val |= AR7240_VTUDATA_VALID;
660 ar7240sw_reg_write(mii, AR7240_REG_VTU_DATA, val);
661 }
662 op |= AR7240_VTU_ACTIVE;
663 ar7240sw_reg_write(mii, AR7240_REG_VTU, op);
664 }
665
666 static int
667 ar7240_hw_apply(struct switch_dev *dev)
668 {
669 struct ar7240sw *as = sw_to_ar7240(dev);
670 u8 portmask[AR7240_NUM_PORTS];
671 int i, j;
672
673 /* flush all vlan translation unit entries */
674 ar7240_vtu_op(as, AR7240_VTU_OP_FLUSH, 0);
675
676 memset(portmask, 0, sizeof(portmask));
677 if (as->vlan) {
678 /* calculate the port destination masks and load vlans
679 * into the vlan translation unit */
680 for (j = 0; j < AR7240_MAX_VLANS; j++) {
681 u8 vp = as->vlan_table[j];
682
683 if (!vp)
684 continue;
685
686 for (i = 0; i < AR7240_NUM_PORTS; i++) {
687 u8 mask = (1 << i);
688 if (vp & mask)
689 portmask[i] |= vp & ~mask;
690 }
691
692 ar7240_vtu_op(as,
693 AR7240_VTU_OP_LOAD |
694 (as->vlan_id[j] << AR7240_VTU_VID_S),
695 as->vlan_table[j]);
696 }
697 } else {
698 /* vlan disabled:
699 * isolate all ports, but connect them to the cpu port */
700 for (i = 0; i < AR7240_NUM_PORTS; i++) {
701 if (i == AR7240_PORT_CPU)
702 continue;
703
704 portmask[i] = 1 << AR7240_PORT_CPU;
705 portmask[AR7240_PORT_CPU] |= (1 << i);
706 }
707 }
708
709 /* update the port destination mask registers and tag settings */
710 for (i = 0; i < AR7240_NUM_PORTS; i++)
711 ar7240sw_setup_port(as, i, portmask[i]);
712
713 return 0;
714 }
715
716 static int
717 ar7240_reset_switch(struct switch_dev *dev)
718 {
719 struct ar7240sw *as = sw_to_ar7240(dev);
720 ar7240sw_reset(as);
721 return 0;
722 }
723
724 static struct switch_attr ar7240_globals[] = {
725 {
726 .type = SWITCH_TYPE_INT,
727 .name = "enable_vlan",
728 .description = "Enable VLAN mode",
729 .set = ar7240_set_vlan,
730 .get = ar7240_get_vlan,
731 .max = 1
732 },
733 };
734
735 static struct switch_attr ar7240_port[] = {
736 };
737
738 static struct switch_attr ar7240_vlan[] = {
739 {
740 .type = SWITCH_TYPE_INT,
741 .name = "vid",
742 .description = "VLAN ID",
743 .set = ar7240_set_vid,
744 .get = ar7240_get_vid,
745 .max = 4094,
746 },
747 };
748
749 static const struct switch_dev_ops ar7240_ops = {
750 .attr_global = {
751 .attr = ar7240_globals,
752 .n_attr = ARRAY_SIZE(ar7240_globals),
753 },
754 .attr_port = {
755 .attr = ar7240_port,
756 .n_attr = ARRAY_SIZE(ar7240_port),
757 },
758 .attr_vlan = {
759 .attr = ar7240_vlan,
760 .n_attr = ARRAY_SIZE(ar7240_vlan),
761 },
762 .get_port_pvid = ar7240_get_pvid,
763 .set_port_pvid = ar7240_set_pvid,
764 .get_vlan_ports = ar7240_get_ports,
765 .set_vlan_ports = ar7240_set_ports,
766 .apply_config = ar7240_hw_apply,
767 .reset_switch = ar7240_reset_switch,
768 };
769
770 static struct ar7240sw *ar7240_probe(struct ag71xx *ag)
771 {
772 struct mii_bus *mii = ag->mii_bus;
773 struct ar7240sw *as;
774 struct switch_dev *swdev;
775 u32 ctrl;
776 u16 phy_id1;
777 u16 phy_id2;
778 u8 ver;
779 int i;
780
781 as = kzalloc(sizeof(*as), GFP_KERNEL);
782 if (!as)
783 return NULL;
784
785 ar7240sw_init(as, mii);
786
787 ctrl = ar7240sw_reg_read(mii, AR7240_REG_MASK_CTRL);
788
789 ver = (ctrl >> AR7240_MASK_CTRL_VERSION_S) & AR7240_MASK_CTRL_VERSION_M;
790 if (ver != 1) {
791 pr_err("%s: unsupported chip, ctrl=%08x\n",
792 ag->dev->name, ctrl);
793 return NULL;
794 }
795
796 phy_id1 = ar7240sw_phy_read(mii, 0, MII_PHYSID1);
797 phy_id2 = ar7240sw_phy_read(mii, 0, MII_PHYSID2);
798 if (phy_id1 != AR7240_PHY_ID1 || phy_id2 != AR7240_PHY_ID2) {
799 pr_err("%s: unknown phy id '%04x:%04x'\n",
800 ag->dev->name, phy_id1, phy_id2);
801 return NULL;
802 }
803
804 swdev = &as->swdev;
805 swdev->name = "AR7240 built-in switch";
806 swdev->ports = AR7240_NUM_PORTS;
807 swdev->cpu_port = AR7240_PORT_CPU;
808 swdev->vlans = AR7240_MAX_VLANS;
809 swdev->ops = &ar7240_ops;
810
811 if (register_switch(&as->swdev, ag->dev) < 0) {
812 kfree(as);
813 return NULL;
814 }
815
816 pr_info("%s: Found an AR7240 built-in switch\n", ag->dev->name);
817
818 /* initialize defaults */
819 for (i = 0; i < AR7240_MAX_VLANS; i++)
820 as->vlan_id[i] = i;
821
822 as->vlan_table[0] = AR7240_PORT_MASK_ALL;
823
824 return as;
825 }
826
827 static void link_function(struct work_struct *work) {
828 struct ag71xx *ag = container_of(work, struct ag71xx, link_work.work);
829 unsigned long flags;
830 int i;
831 int status = 0;
832
833 for (i = 0; i < 4; i++) {
834 int link = ar7240sw_phy_read(ag->mii_bus, i, MII_BMSR);
835 if(link & BMSR_LSTATUS) {
836 status = 1;
837 break;
838 }
839 }
840
841 spin_lock_irqsave(&ag->lock, flags);
842 if(status != ag->link) {
843 ag->link = status;
844 ag71xx_link_adjust(ag);
845 }
846 spin_unlock_irqrestore(&ag->lock, flags);
847
848 schedule_delayed_work(&ag->link_work, HZ / 2);
849 }
850
851 void ag71xx_ar7240_start(struct ag71xx *ag)
852 {
853 struct ar7240sw *as = ag->phy_priv;
854
855 ar7240sw_reset(as);
856
857 ag->speed = SPEED_1000;
858 ag->duplex = 1;
859
860 ar7240_set_addr(as, ag->dev->dev_addr);
861 ar7240_hw_apply(&as->swdev);
862
863 schedule_delayed_work(&ag->link_work, HZ / 10);
864 }
865
866 void ag71xx_ar7240_stop(struct ag71xx *ag)
867 {
868 cancel_delayed_work_sync(&ag->link_work);
869 }
870
871 int __devinit ag71xx_ar7240_init(struct ag71xx *ag)
872 {
873 struct ar7240sw *as;
874
875 as = ar7240_probe(ag);
876 if (!as)
877 return -ENODEV;
878
879 ag->phy_priv = as;
880 ar7240sw_reset(as);
881
882 INIT_DELAYED_WORK(&ag->link_work, link_function);
883
884 return 0;
885 }
886
887 void ag71xx_ar7240_cleanup(struct ag71xx *ag)
888 {
889 struct ar7240sw *as = ag->phy_priv;
890
891 if (!as)
892 return;
893
894 unregister_switch(&as->swdev);
895 kfree(as);
896 ag->phy_priv = NULL;
897 }
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