[ar71xx] ethernet driver updates
[openwrt/svn-archive/archive.git] / target / linux / ar71xx / files / drivers / net / ag71xx / ag71xx_main.c
1 /*
2 * Atheros AR71xx built-in ethernet mac driver
3 *
4 * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Based on Atheros' AG7100 driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #include "ag71xx.h"
15
16 static void ag71xx_dump_regs(struct ag71xx *ag)
17 {
18 DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
19 ag->dev->name,
20 ag71xx_rr(ag, AG71XX_REG_MAC_CFG1),
21 ag71xx_rr(ag, AG71XX_REG_MAC_CFG2),
22 ag71xx_rr(ag, AG71XX_REG_MAC_IPG),
23 ag71xx_rr(ag, AG71XX_REG_MAC_HDX),
24 ag71xx_rr(ag, AG71XX_REG_MAC_MFL));
25 DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
26 ag->dev->name,
27 ag71xx_rr(ag, AG71XX_REG_MAC_IFCTL),
28 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR1),
29 ag71xx_rr(ag, AG71XX_REG_MAC_ADDR2));
30 DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
31 ag->dev->name,
32 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG0),
33 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG1),
34 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG2));
35 DBG("%s: fifo_cfg3=%08x, fifo_cfg3=%08x, fifo_cfg5=%08x\n",
36 ag->dev->name,
37 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG3),
38 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG4),
39 ag71xx_rr(ag, AG71XX_REG_FIFO_CFG5));
40 }
41
42 static void ag71xx_ring_free(struct ag71xx_ring *ring)
43 {
44 kfree(ring->buf);
45
46 if (ring->descs)
47 dma_free_coherent(NULL, ring->size * sizeof(*ring->descs),
48 ring->descs, ring->descs_dma);
49 }
50
51 static int ag71xx_ring_alloc(struct ag71xx_ring *ring, unsigned int size)
52 {
53 int err;
54
55 ring->descs = dma_alloc_coherent(NULL, size * sizeof(*ring->descs),
56 &ring->descs_dma,
57 GFP_ATOMIC);
58 if (!ring->descs) {
59 err = -ENOMEM;
60 goto err;
61 }
62
63 ring->size = size;
64
65 ring->buf = kzalloc(size * sizeof(*ring->buf), GFP_KERNEL);
66 if (!ring->buf) {
67 err = -ENOMEM;
68 goto err;
69 }
70
71 return 0;
72
73 err:
74 return err;
75 }
76
77 static void ag71xx_ring_tx_clean(struct ag71xx *ag)
78 {
79 struct ag71xx_ring *ring = &ag->tx_ring;
80 struct net_device *dev = ag->dev;
81
82 while (ring->curr != ring->dirty) {
83 u32 i = ring->dirty % AG71XX_TX_RING_SIZE;
84
85 if (!ag71xx_desc_empty(&ring->descs[i])) {
86 ring->descs[i].ctrl = 0;
87 dev->stats.tx_errors++;
88 }
89
90 if (ring->buf[i].skb)
91 dev_kfree_skb_any(ring->buf[i].skb);
92
93 ring->buf[i].skb = NULL;
94
95 ring->dirty++;
96 }
97
98 /* flush descriptors */
99 wmb();
100
101 }
102
103 static void ag71xx_ring_tx_init(struct ag71xx *ag)
104 {
105 struct ag71xx_ring *ring = &ag->tx_ring;
106 int i;
107
108 for (i = 0; i < AG71XX_TX_RING_SIZE; i++) {
109 ring->descs[i].next = (u32) (ring->descs_dma +
110 sizeof(*ring->descs) * ((i + 1) % AG71XX_TX_RING_SIZE));
111
112 ring->descs[i].ctrl = DESC_EMPTY;
113 ring->buf[i].skb = NULL;
114 }
115
116 /* flush descriptors */
117 wmb();
118
119 ring->curr = 0;
120 ring->dirty = 0;
121 }
122
123 static void ag71xx_ring_rx_clean(struct ag71xx *ag)
124 {
125 struct ag71xx_ring *ring = &ag->rx_ring;
126 int i;
127
128 if (!ring->buf)
129 return;
130
131 for (i = 0; i < AG71XX_RX_RING_SIZE; i++)
132 if (ring->buf[i].skb)
133 kfree_skb(ring->buf[i].skb);
134
135 }
136
137 static int ag71xx_ring_rx_init(struct ag71xx *ag)
138 {
139 struct ag71xx_ring *ring = &ag->rx_ring;
140 unsigned int i;
141 int ret;
142
143 ret = 0;
144 for (i = 0; i < AG71XX_RX_RING_SIZE; i++)
145 ring->descs[i].next = (u32) (ring->descs_dma +
146 sizeof(*ring->descs) * ((i + 1) % AG71XX_RX_RING_SIZE));
147
148 for (i = 0; i < AG71XX_RX_RING_SIZE; i++) {
149 struct sk_buff *skb;
150
151 skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE);
152 if (!skb) {
153 ret = -ENOMEM;
154 break;
155 }
156
157 skb->dev = ag->dev;
158 skb_reserve(skb, AG71XX_RX_PKT_RESERVE);
159
160 ring->buf[i].skb = skb;
161 ring->descs[i].data = virt_to_phys(skb->data);
162 ring->descs[i].ctrl = DESC_EMPTY;
163 }
164
165 /* flush descriptors */
166 wmb();
167
168 ring->curr = 0;
169 ring->dirty = 0;
170
171 return ret;
172 }
173
174 static int ag71xx_ring_rx_refill(struct ag71xx *ag)
175 {
176 struct ag71xx_ring *ring = &ag->rx_ring;
177 unsigned int count;
178
179 count = 0;
180 for (; ring->curr - ring->dirty > 0; ring->dirty++) {
181 unsigned int i;
182
183 i = ring->dirty % AG71XX_RX_RING_SIZE;
184
185 if (ring->buf[i].skb == NULL) {
186 struct sk_buff *skb;
187
188 skb = dev_alloc_skb(AG71XX_RX_PKT_SIZE);
189 if (skb == NULL) {
190 printk(KERN_ERR "%s: no memory for skb\n",
191 ag->dev->name);
192 break;
193 }
194
195 skb_reserve(skb, AG71XX_RX_PKT_RESERVE);
196 skb->dev = ag->dev;
197 ring->buf[i].skb = skb;
198 ring->descs[i].data = virt_to_phys(skb->data);
199 }
200
201 ring->descs[i].ctrl = DESC_EMPTY;
202 count++;
203 }
204
205 /* flush descriptors */
206 wmb();
207
208 DBG("%s: %u rx descriptors refilled\n", ag->dev->name, count);
209
210 return count;
211 }
212
213 static int ag71xx_rings_init(struct ag71xx *ag)
214 {
215 int ret;
216
217 ret = ag71xx_ring_alloc(&ag->tx_ring, AG71XX_TX_RING_SIZE);
218 if (ret)
219 return ret;
220
221 ag71xx_ring_tx_init(ag);
222
223 ret = ag71xx_ring_alloc(&ag->rx_ring, AG71XX_RX_RING_SIZE);
224 if (ret)
225 return ret;
226
227 ret = ag71xx_ring_rx_init(ag);
228 return ret;
229 }
230
231 static void ag71xx_rings_cleanup(struct ag71xx *ag)
232 {
233 ag71xx_ring_rx_clean(ag);
234 ag71xx_ring_free(&ag->rx_ring);
235
236 ag71xx_ring_tx_clean(ag);
237 ag71xx_ring_free(&ag->tx_ring);
238 }
239
240 static void ag71xx_hw_set_macaddr(struct ag71xx *ag, unsigned char *mac)
241 {
242 u32 t;
243
244 t = (((u32) mac[0]) << 24) | (((u32) mac[1]) << 16)
245 | (((u32) mac[2]) << 8) | ((u32) mac[2]);
246
247 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR1, t);
248
249 t = (((u32) mac[4]) << 24) | (((u32) mac[5]) << 16);
250 ag71xx_wr(ag, AG71XX_REG_MAC_ADDR2, t);
251 }
252
253 #define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | MAC_CFG1_SRX \
254 | MAC_CFG1_STX)
255
256 static void ag71xx_hw_init(struct ag71xx *ag)
257 {
258 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
259
260 ag71xx_sb(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_SR);
261 udelay(20);
262
263 ar71xx_device_stop(pdata->reset_bit);
264 mdelay(100);
265 ar71xx_device_start(pdata->reset_bit);
266 mdelay(100);
267
268 ag71xx_wr(ag, AG71XX_REG_MAC_CFG1, MAC_CFG1_INIT);
269
270 /* TODO: set max packet size */
271
272 ag71xx_sb(ag, AG71XX_REG_MAC_CFG2,
273 MAC_CFG2_PAD_CRC_EN | MAC_CFG2_LEN_CHECK);
274
275 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG0, 0x00001f00);
276
277 ag71xx_mii_ctrl_set_if(ag, pdata->mii_if);
278
279 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG1, 0x0fff0000);
280 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG2, 0x00001fff);
281 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG4, 0x0000ffff);
282 ag71xx_wr(ag, AG71XX_REG_FIFO_CFG5, 0x0007ffef);
283 }
284
285 static void ag71xx_hw_start(struct ag71xx *ag)
286 {
287 /* start RX engine */
288 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
289
290 /* enable interrupts */
291 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, AG71XX_INT_INIT);
292 }
293
294 static void ag71xx_hw_stop(struct ag71xx *ag)
295 {
296 /* stop RX and TX */
297 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, 0);
298 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, 0);
299
300 /* disable all interrupts */
301 ag71xx_wr(ag, AG71XX_REG_INT_ENABLE, 0);
302 }
303
304 static int ag71xx_open(struct net_device *dev)
305 {
306 struct ag71xx *ag = netdev_priv(dev);
307 int ret;
308
309 ret = ag71xx_rings_init(ag);
310 if (ret)
311 goto err;
312
313 napi_enable(&ag->napi);
314
315 netif_carrier_off(dev);
316 ag71xx_phy_start(ag);
317
318 ag71xx_wr(ag, AG71XX_REG_TX_DESC, ag->tx_ring.descs_dma);
319 ag71xx_wr(ag, AG71XX_REG_RX_DESC, ag->rx_ring.descs_dma);
320
321 ag71xx_hw_set_macaddr(ag, dev->dev_addr);
322
323 ag71xx_hw_start(ag);
324
325 netif_start_queue(dev);
326
327 return 0;
328
329 err:
330 ag71xx_rings_cleanup(ag);
331 return ret;
332 }
333
334 static int ag71xx_stop(struct net_device *dev)
335 {
336 struct ag71xx *ag = netdev_priv(dev);
337 unsigned long flags;
338
339 spin_lock_irqsave(&ag->lock, flags);
340
341 netif_stop_queue(dev);
342
343 ag71xx_hw_stop(ag);
344
345 netif_carrier_off(dev);
346 ag71xx_phy_stop(ag);
347
348 napi_disable(&ag->napi);
349
350 spin_unlock_irqrestore(&ag->lock, flags);
351
352 ag71xx_rings_cleanup(ag);
353
354 return 0;
355 }
356
357 static int ag71xx_hard_start_xmit(struct sk_buff *skb, struct net_device *dev)
358 {
359 struct ag71xx *ag = netdev_priv(dev);
360 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
361 struct ag71xx_ring *ring = &ag->tx_ring;
362 struct ag71xx_desc *desc;
363 unsigned long flags;
364 int i;
365
366 i = ring->curr % AG71XX_TX_RING_SIZE;
367 desc = &ring->descs[i];
368
369 spin_lock_irqsave(&ag->lock, flags);
370 ar71xx_ddr_flush(pdata->flush_reg);
371 spin_unlock_irqrestore(&ag->lock, flags);
372
373 if (!ag71xx_desc_empty(desc))
374 goto err_drop;
375
376 if (skb->len <= 0) {
377 DBG("%s: packet len is too small\n", ag->dev->name);
378 goto err_drop;
379 }
380
381 dma_cache_wback_inv((unsigned long)skb->data, skb->len);
382
383 ring->buf[i].skb = skb;
384
385 /* setup descriptor fields */
386 desc->data = virt_to_phys(skb->data);
387 desc->ctrl = (skb->len & DESC_PKTLEN_M);
388
389 /* flush descriptor */
390 wmb();
391
392 ring->curr++;
393 if (ring->curr == (ring->dirty + AG71XX_TX_THRES_STOP)) {
394 DBG("%s: tx queue full\n", ag->dev->name);
395 netif_stop_queue(dev);
396 }
397
398 DBG("%s: packet injected into TX queue\n", ag->dev->name);
399
400 /* enable TX engine */
401 ag71xx_wr(ag, AG71XX_REG_TX_CTRL, TX_CTRL_TXE);
402
403 dev->trans_start = jiffies;
404
405 return 0;
406
407 err_drop:
408 dev->stats.tx_dropped++;
409
410 dev_kfree_skb(skb);
411 return 0;
412 }
413
414 static int ag71xx_do_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
415 {
416 struct mii_ioctl_data *data = (struct mii_ioctl_data *) &ifr->ifr_data;
417 struct ag71xx *ag = netdev_priv(dev);
418 int ret;
419
420 switch (cmd) {
421 case SIOCETHTOOL:
422 if (ag->phy_dev == NULL)
423 break;
424
425 spin_lock_irq(&ag->lock);
426 ret = phy_ethtool_ioctl(ag->phy_dev, (void *) ifr->ifr_data);
427 spin_unlock_irq(&ag->lock);
428 return ret;
429
430 case SIOCSIFHWADDR:
431 if (copy_from_user
432 (dev->dev_addr, ifr->ifr_data, sizeof(dev->dev_addr)))
433 return -EFAULT;
434 return 0;
435
436 case SIOCGIFHWADDR:
437 if (copy_to_user
438 (ifr->ifr_data, dev->dev_addr, sizeof(dev->dev_addr)))
439 return -EFAULT;
440 return 0;
441
442 case SIOCGMIIPHY:
443 case SIOCGMIIREG:
444 case SIOCSMIIREG:
445 if (ag->phy_dev == NULL)
446 break;
447
448 return phy_mii_ioctl(ag->phy_dev, data, cmd);
449
450 default:
451 break;
452 }
453
454 return -EOPNOTSUPP;
455 }
456
457 static void ag71xx_tx_packets(struct ag71xx *ag)
458 {
459 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
460 struct ag71xx_ring *ring = &ag->tx_ring;
461 unsigned int sent;
462
463 DBG("%s: processing TX ring\n", ag->dev->name);
464
465 #ifdef AG71XX_NAPI_TX
466 ar71xx_ddr_flush(pdata->flush_reg);
467 #endif
468
469 sent = 0;
470 while (ring->dirty != ring->curr) {
471 unsigned int i = ring->dirty % AG71XX_TX_RING_SIZE;
472 struct ag71xx_desc *desc = &ring->descs[i];
473 struct sk_buff *skb = ring->buf[i].skb;
474
475 if (!ag71xx_desc_empty(desc))
476 break;
477
478 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_PS);
479
480 ag->dev->stats.tx_bytes += skb->len;
481 ag->dev->stats.tx_packets++;
482
483 dev_kfree_skb_any(skb);
484 ring->buf[i].skb = NULL;
485
486 ring->dirty++;
487 sent++;
488 }
489
490 DBG("%s: %d packets sent out\n", ag->dev->name, sent);
491
492 if ((ring->curr - ring->dirty) < AG71XX_TX_THRES_WAKEUP)
493 netif_wake_queue(ag->dev);
494
495 }
496
497 static int ag71xx_rx_packets(struct ag71xx *ag, int limit)
498 {
499 struct net_device *dev = ag->dev;
500 struct ag71xx_ring *ring = &ag->rx_ring;
501 #ifndef AG71XX_NAPI_TX
502 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
503 unsigned long flags;
504 #endif
505 int done = 0;
506
507 #ifndef AG71XX_NAPI_TX
508 spin_lock_irqsave(&ag->lock, flags);
509 ar71xx_ddr_flush(pdata->flush_reg);
510 spin_unlock_irqrestore(&ag->lock, flags);
511 #endif
512
513 DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
514 dev->name, limit, ring->curr, ring->dirty);
515
516 while (done < limit) {
517 unsigned int i = ring->curr % AG71XX_RX_RING_SIZE;
518 struct ag71xx_desc *desc = &ring->descs[i];
519 struct sk_buff *skb;
520 int pktlen;
521
522 if (ag71xx_desc_empty(desc))
523 break;
524
525 if ((ring->dirty + AG71XX_RX_RING_SIZE) == ring->curr) {
526 ag71xx_assert(0);
527 break;
528 }
529
530 skb = ring->buf[i].skb;
531 pktlen = ag71xx_desc_pktlen(desc);
532 pktlen -= ETH_FCS_LEN;
533
534 /* TODO: move it into the refill function */
535 dma_cache_wback_inv((unsigned long)skb->data, pktlen);
536 skb_put(skb, pktlen);
537
538 skb->dev = dev;
539 skb->protocol = eth_type_trans(skb, dev);
540 skb->ip_summed = CHECKSUM_UNNECESSARY;
541
542 netif_receive_skb(skb);
543
544 dev->last_rx = jiffies;
545 dev->stats.rx_packets++;
546 dev->stats.rx_bytes += pktlen;
547
548 ring->buf[i].skb = NULL;
549 done++;
550
551 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_PR);
552
553 ring->curr++;
554 if ((ring->curr - ring->dirty) > (AG71XX_RX_RING_SIZE / 4))
555 ag71xx_ring_rx_refill(ag);
556 }
557
558 ag71xx_ring_rx_refill(ag);
559
560 DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
561 dev->name, ring->curr, ring->dirty, done);
562
563 return done;
564 }
565
566 static int ag71xx_poll(struct napi_struct *napi, int limit)
567 {
568 struct ag71xx *ag = container_of(napi, struct ag71xx, napi);
569 #ifdef AG71XX_NAPI_TX
570 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
571 #endif
572 struct net_device *dev = ag->dev;
573 unsigned long flags;
574 u32 status;
575 int done;
576
577 #ifdef AG71XX_NAPI_TX
578 ar71xx_ddr_flush(pdata->flush_reg);
579 ag71xx_tx_packets(ag);
580 #endif
581
582 DBG("%s: processing RX ring\n", dev->name);
583 done = ag71xx_rx_packets(ag, limit);
584
585 /* TODO: add OOM handler */
586
587 status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
588 status &= AG71XX_INT_POLL;
589
590 if ((done < limit) && (!status)) {
591 DBG("%s: disable polling mode, done=%d, status=%x\n",
592 dev->name, done, status);
593
594 netif_rx_complete(dev, napi);
595
596 /* enable interrupts */
597 spin_lock_irqsave(&ag->lock, flags);
598 ag71xx_int_enable(ag, AG71XX_INT_POLL);
599 spin_unlock_irqrestore(&ag->lock, flags);
600 return 0;
601 }
602
603 if (status & AG71XX_INT_RX_OF) {
604 printk(KERN_ALERT "%s: rx owerflow, restarting dma\n",
605 dev->name);
606
607 /* ack interrupt */
608 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_OF);
609 /* restart RX */
610 ag71xx_wr(ag, AG71XX_REG_RX_CTRL, RX_CTRL_RXE);
611 }
612
613 DBG("%s: stay in polling mode, done=%d, status=%x\n",
614 dev->name, done, status);
615 return 1;
616 }
617
618 static irqreturn_t ag71xx_interrupt(int irq, void *dev_id)
619 {
620 struct net_device *dev = dev_id;
621 struct ag71xx *ag = netdev_priv(dev);
622 u32 status;
623
624 status = ag71xx_rr(ag, AG71XX_REG_INT_STATUS);
625 status &= ag71xx_rr(ag, AG71XX_REG_INT_ENABLE);
626
627 if (unlikely(!status))
628 return IRQ_NONE;
629
630 if (unlikely(status & AG71XX_INT_ERR)) {
631 if (status & AG71XX_INT_TX_BE) {
632 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_BE);
633 dev_err(&dev->dev, "TX BUS error\n");
634 }
635 if (status & AG71XX_INT_RX_BE) {
636 ag71xx_wr(ag, AG71XX_REG_RX_STATUS, RX_STATUS_BE);
637 dev_err(&dev->dev, "RX BUS error\n");
638 }
639 }
640
641 #if 0
642 if (unlikely(status & AG71XX_INT_TX_UR)) {
643 ag71xx_wr(ag, AG71XX_REG_TX_STATUS, TX_STATUS_UR);
644 DBG("%s: TX underrun\n", dev->name);
645 }
646 #endif
647
648 #ifndef AG71XX_NAPI_TX
649 if (likely(status & AG71XX_INT_TX_PS))
650 ag71xx_tx_packets(ag);
651 #endif
652
653 if (likely(status & AG71XX_INT_POLL)) {
654 ag71xx_int_disable(ag, AG71XX_INT_POLL);
655 DBG("%s: enable polling mode\n", dev->name);
656 netif_rx_schedule(dev, &ag->napi);
657 }
658
659 return IRQ_HANDLED;
660 }
661
662 static void ag71xx_set_multicast_list(struct net_device *dev)
663 {
664 /* TODO */
665 }
666
667 static int __init ag71xx_probe(struct platform_device *pdev)
668 {
669 struct net_device *dev;
670 struct resource *res;
671 struct ag71xx *ag;
672 struct ag71xx_platform_data *pdata;
673 int err;
674
675 pdata = pdev->dev.platform_data;
676 if (!pdata) {
677 dev_err(&pdev->dev, "no platform data specified\n");
678 err = -ENXIO;
679 goto err_out;
680 }
681
682 dev = alloc_etherdev(sizeof(*ag));
683 if (!dev) {
684 dev_err(&pdev->dev, "alloc_etherdev failed\n");
685 err = -ENOMEM;
686 goto err_out;
687 }
688
689 SET_NETDEV_DEV(dev, &pdev->dev);
690
691 ag = netdev_priv(dev);
692 ag->pdev = pdev;
693 ag->dev = dev;
694 ag->mii_bus = &ag71xx_mdio_bus->mii_bus;
695 spin_lock_init(&ag->lock);
696
697 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base");
698 if (!res) {
699 dev_err(&pdev->dev, "no mac_base resource found\n");
700 err = -ENXIO;
701 goto err_out;
702 }
703
704 ag->mac_base = ioremap_nocache(res->start, res->end - res->start + 1);
705 if (!ag->mac_base) {
706 dev_err(&pdev->dev, "unable to ioremap mac_base\n");
707 err = -ENOMEM;
708 goto err_free_dev;
709 }
710
711 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mac_base2");
712 if (!res) {
713 dev_err(&pdev->dev, "no mac_base2 resource found\n");
714 err = -ENXIO;
715 goto err_unmap_base1;
716 }
717
718 ag->mac_base2 = ioremap_nocache(res->start, res->end - res->start + 1);
719 if (!ag->mac_base) {
720 dev_err(&pdev->dev, "unable to ioremap mac_base2\n");
721 err = -ENOMEM;
722 goto err_unmap_base1;
723 }
724
725 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mii_ctrl");
726 if (!res) {
727 dev_err(&pdev->dev, "no mii_ctrl resource found\n");
728 err = -ENXIO;
729 goto err_unmap_base2;
730 }
731
732 ag->mii_ctrl = ioremap_nocache(res->start, res->end - res->start + 1);
733 if (!ag->mii_ctrl) {
734 dev_err(&pdev->dev, "unable to ioremap mii_ctrl\n");
735 err = -ENOMEM;
736 goto err_unmap_base2;
737 }
738
739 dev->irq = platform_get_irq(pdev, 0);
740 err = request_irq(dev->irq, ag71xx_interrupt,
741 IRQF_DISABLED | IRQF_SAMPLE_RANDOM,
742 dev->name, dev);
743 if (err) {
744 dev_err(&pdev->dev, "unable to request IRQ %d\n", dev->irq);
745 goto err_unmap_mii_ctrl;
746 }
747
748 dev->base_addr = (unsigned long)ag->mac_base;
749 dev->open = ag71xx_open;
750 dev->stop = ag71xx_stop;
751 dev->hard_start_xmit = ag71xx_hard_start_xmit;
752 dev->set_multicast_list = ag71xx_set_multicast_list;
753 dev->do_ioctl = ag71xx_do_ioctl;
754 dev->ethtool_ops = &ag71xx_ethtool_ops;
755
756 netif_napi_add(dev, &ag->napi, ag71xx_poll, AG71XX_NAPI_WEIGHT);
757
758 if (is_valid_ether_addr(pdata->mac_addr))
759 memcpy(dev->dev_addr, pdata->mac_addr, ETH_ALEN);
760 else {
761 dev->dev_addr[0] = 0xde;
762 dev->dev_addr[1] = 0xad;
763 get_random_bytes(&dev->dev_addr[2], 3);
764 dev->dev_addr[5] = pdev->id & 0xff;
765 }
766
767 err = register_netdev(dev);
768 if (err) {
769 dev_err(&pdev->dev, "unable to register net device\n");
770 goto err_free_irq;
771 }
772
773 printk(KERN_INFO "%s: Atheros AG71xx at 0x%08lx, irq %d\n",
774 dev->name, dev->base_addr, dev->irq);
775
776 ag71xx_dump_regs(ag);
777
778 ag71xx_hw_init(ag);
779
780 ag71xx_dump_regs(ag);
781
782 /* Reset the mdio bus explicitly */
783 if (ag->mii_bus) {
784 mutex_lock(&ag->mii_bus->mdio_lock);
785 ag->mii_bus->reset(ag->mii_bus);
786 mutex_unlock(&ag->mii_bus->mdio_lock);
787 }
788
789 err = ag71xx_phy_connect(ag);
790 if (err)
791 goto err_unregister_netdev;
792
793 platform_set_drvdata(pdev, dev);
794
795 return 0;
796
797 err_unregister_netdev:
798 unregister_netdev(dev);
799 err_free_irq:
800 free_irq(dev->irq, dev);
801 err_unmap_mii_ctrl:
802 iounmap(ag->mii_ctrl);
803 err_unmap_base2:
804 iounmap(ag->mac_base2);
805 err_unmap_base1:
806 iounmap(ag->mac_base);
807 err_free_dev:
808 kfree(dev);
809 err_out:
810 platform_set_drvdata(pdev, NULL);
811 return err;
812 }
813
814 static int __exit ag71xx_remove(struct platform_device *pdev)
815 {
816 struct net_device *dev = platform_get_drvdata(pdev);
817
818 if (dev) {
819 struct ag71xx *ag = netdev_priv(dev);
820
821 ag71xx_phy_disconnect(ag);
822 unregister_netdev(dev);
823 free_irq(dev->irq, dev);
824 iounmap(ag->mii_ctrl);
825 iounmap(ag->mac_base2);
826 iounmap(ag->mac_base);
827 kfree(dev);
828 platform_set_drvdata(pdev, NULL);
829 }
830
831 return 0;
832 }
833
834 static struct platform_driver ag71xx_driver = {
835 .probe = ag71xx_probe,
836 .remove = __exit_p(ag71xx_remove),
837 .driver = {
838 .name = AG71XX_DRV_NAME,
839 }
840 };
841
842 static int __init ag71xx_module_init(void)
843 {
844 int ret;
845
846 ret = ag71xx_mdio_driver_init();
847 if (ret)
848 goto err_out;
849
850 ret = platform_driver_register(&ag71xx_driver);
851 if (ret)
852 goto err_mdio_exit;
853
854 return 0;
855
856 err_mdio_exit:
857 ag71xx_mdio_driver_exit();
858 err_out:
859 return ret;
860 }
861
862 static void __exit ag71xx_module_exit(void)
863 {
864 platform_driver_unregister(&ag71xx_driver);
865 }
866
867 module_init(ag71xx_module_init);
868 module_exit(ag71xx_module_exit);
869
870 MODULE_VERSION(AG71XX_DRV_VERSION);
871 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
872 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
873 MODULE_LICENSE("GPL v2");
874 MODULE_ALIAS("platform:" AG71XX_DRV_NAME);