2 * Atheros AR71xx built-in ethernet mac driver
4 * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
7 * Based on Atheros' AG7100 driver
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
16 static void ag71xx_dump_regs(struct ag71xx
*ag
)
18 DBG("%s: mac_cfg1=%08x, mac_cfg2=%08x, ipg=%08x, hdx=%08x, mfl=%08x\n",
20 ag71xx_rr(ag
, AG71XX_REG_MAC_CFG1
),
21 ag71xx_rr(ag
, AG71XX_REG_MAC_CFG2
),
22 ag71xx_rr(ag
, AG71XX_REG_MAC_IPG
),
23 ag71xx_rr(ag
, AG71XX_REG_MAC_HDX
),
24 ag71xx_rr(ag
, AG71XX_REG_MAC_MFL
));
25 DBG("%s: mac_ifctl=%08x, mac_addr1=%08x, mac_addr2=%08x\n",
27 ag71xx_rr(ag
, AG71XX_REG_MAC_IFCTL
),
28 ag71xx_rr(ag
, AG71XX_REG_MAC_ADDR1
),
29 ag71xx_rr(ag
, AG71XX_REG_MAC_ADDR2
));
30 DBG("%s: fifo_cfg0=%08x, fifo_cfg1=%08x, fifo_cfg2=%08x\n",
32 ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG0
),
33 ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG1
),
34 ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG2
));
35 DBG("%s: fifo_cfg3=%08x, fifo_cfg3=%08x, fifo_cfg5=%08x\n",
37 ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG3
),
38 ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG4
),
39 ag71xx_rr(ag
, AG71XX_REG_FIFO_CFG5
));
42 static void ag71xx_ring_free(struct ag71xx_ring
*ring
)
47 dma_free_coherent(NULL
, ring
->size
* sizeof(*ring
->descs
),
48 ring
->descs
, ring
->descs_dma
);
51 static int ag71xx_ring_alloc(struct ag71xx_ring
*ring
, unsigned int size
)
55 ring
->descs
= dma_alloc_coherent(NULL
, size
* sizeof(*ring
->descs
),
65 ring
->buf
= kzalloc(size
* sizeof(*ring
->buf
), GFP_KERNEL
);
77 static void ag71xx_ring_tx_clean(struct ag71xx
*ag
)
79 struct ag71xx_ring
*ring
= &ag
->tx_ring
;
80 struct net_device
*dev
= ag
->dev
;
82 while (ring
->curr
!= ring
->dirty
) {
83 u32 i
= ring
->dirty
% AG71XX_TX_RING_SIZE
;
85 if (!ag71xx_desc_empty(&ring
->descs
[i
])) {
86 ring
->descs
[i
].ctrl
= 0;
87 dev
->stats
.tx_errors
++;
91 dev_kfree_skb_any(ring
->buf
[i
].skb
);
93 ring
->buf
[i
].skb
= NULL
;
98 /* flush descriptors */
103 static void ag71xx_ring_tx_init(struct ag71xx
*ag
)
105 struct ag71xx_ring
*ring
= &ag
->tx_ring
;
108 for (i
= 0; i
< AG71XX_TX_RING_SIZE
; i
++) {
109 ring
->descs
[i
].next
= (u32
) (ring
->descs_dma
+
110 sizeof(*ring
->descs
) * ((i
+ 1) % AG71XX_TX_RING_SIZE
));
112 ring
->descs
[i
].ctrl
= DESC_EMPTY
;
113 ring
->buf
[i
].skb
= NULL
;
116 /* flush descriptors */
123 static void ag71xx_ring_rx_clean(struct ag71xx
*ag
)
125 struct ag71xx_ring
*ring
= &ag
->rx_ring
;
131 for (i
= 0; i
< AG71XX_RX_RING_SIZE
; i
++)
132 if (ring
->buf
[i
].skb
)
133 kfree_skb(ring
->buf
[i
].skb
);
137 static int ag71xx_ring_rx_init(struct ag71xx
*ag
)
139 struct ag71xx_ring
*ring
= &ag
->rx_ring
;
144 for (i
= 0; i
< AG71XX_RX_RING_SIZE
; i
++)
145 ring
->descs
[i
].next
= (u32
) (ring
->descs_dma
+
146 sizeof(*ring
->descs
) * ((i
+ 1) % AG71XX_RX_RING_SIZE
));
148 for (i
= 0; i
< AG71XX_RX_RING_SIZE
; i
++) {
151 skb
= dev_alloc_skb(AG71XX_RX_PKT_SIZE
);
158 skb_reserve(skb
, AG71XX_RX_PKT_RESERVE
);
160 ring
->buf
[i
].skb
= skb
;
161 ring
->descs
[i
].data
= virt_to_phys(skb
->data
);
162 ring
->descs
[i
].ctrl
= DESC_EMPTY
;
165 /* flush descriptors */
174 static int ag71xx_ring_rx_refill(struct ag71xx
*ag
)
176 struct ag71xx_ring
*ring
= &ag
->rx_ring
;
180 for (; ring
->curr
- ring
->dirty
> 0; ring
->dirty
++) {
183 i
= ring
->dirty
% AG71XX_RX_RING_SIZE
;
185 if (ring
->buf
[i
].skb
== NULL
) {
188 skb
= dev_alloc_skb(AG71XX_RX_PKT_SIZE
);
190 printk(KERN_ERR
"%s: no memory for skb\n",
195 skb_reserve(skb
, AG71XX_RX_PKT_RESERVE
);
197 ring
->buf
[i
].skb
= skb
;
198 ring
->descs
[i
].data
= virt_to_phys(skb
->data
);
201 ring
->descs
[i
].ctrl
= DESC_EMPTY
;
205 /* flush descriptors */
208 DBG("%s: %u rx descriptors refilled\n", ag
->dev
->name
, count
);
213 static int ag71xx_rings_init(struct ag71xx
*ag
)
217 ret
= ag71xx_ring_alloc(&ag
->tx_ring
, AG71XX_TX_RING_SIZE
);
221 ag71xx_ring_tx_init(ag
);
223 ret
= ag71xx_ring_alloc(&ag
->rx_ring
, AG71XX_RX_RING_SIZE
);
227 ret
= ag71xx_ring_rx_init(ag
);
231 static void ag71xx_rings_cleanup(struct ag71xx
*ag
)
233 ag71xx_ring_rx_clean(ag
);
234 ag71xx_ring_free(&ag
->rx_ring
);
236 ag71xx_ring_tx_clean(ag
);
237 ag71xx_ring_free(&ag
->tx_ring
);
240 static void ag71xx_hw_set_macaddr(struct ag71xx
*ag
, unsigned char *mac
)
244 t
= (((u32
) mac
[0]) << 24) | (((u32
) mac
[1]) << 16)
245 | (((u32
) mac
[2]) << 8) | ((u32
) mac
[2]);
247 ag71xx_wr(ag
, AG71XX_REG_MAC_ADDR1
, t
);
249 t
= (((u32
) mac
[4]) << 24) | (((u32
) mac
[5]) << 16);
250 ag71xx_wr(ag
, AG71XX_REG_MAC_ADDR2
, t
);
253 #define MAC_CFG1_INIT (MAC_CFG1_RXE | MAC_CFG1_TXE | MAC_CFG1_SRX \
256 static void ag71xx_hw_init(struct ag71xx
*ag
)
258 struct ag71xx_platform_data
*pdata
= ag71xx_get_pdata(ag
);
260 ag71xx_sb(ag
, AG71XX_REG_MAC_CFG1
, MAC_CFG1_SR
);
263 ar71xx_device_stop(pdata
->reset_bit
);
265 ar71xx_device_start(pdata
->reset_bit
);
268 ag71xx_wr(ag
, AG71XX_REG_MAC_CFG1
, MAC_CFG1_INIT
);
270 /* TODO: set max packet size */
272 ag71xx_sb(ag
, AG71XX_REG_MAC_CFG2
,
273 MAC_CFG2_PAD_CRC_EN
| MAC_CFG2_LEN_CHECK
);
275 ag71xx_wr(ag
, AG71XX_REG_FIFO_CFG0
, 0x00001f00);
277 ag71xx_mii_ctrl_set_if(ag
, pdata
->mii_if
);
279 ag71xx_wr(ag
, AG71XX_REG_FIFO_CFG1
, 0x0fff0000);
280 ag71xx_wr(ag
, AG71XX_REG_FIFO_CFG2
, 0x00001fff);
281 ag71xx_wr(ag
, AG71XX_REG_FIFO_CFG4
, 0x0000ffff);
282 ag71xx_wr(ag
, AG71XX_REG_FIFO_CFG5
, 0x0007ffef);
285 static void ag71xx_hw_start(struct ag71xx
*ag
)
287 /* start RX engine */
288 ag71xx_wr(ag
, AG71XX_REG_RX_CTRL
, RX_CTRL_RXE
);
290 /* enable interrupts */
291 ag71xx_wr(ag
, AG71XX_REG_INT_ENABLE
, AG71XX_INT_INIT
);
294 static void ag71xx_hw_stop(struct ag71xx
*ag
)
297 ag71xx_wr(ag
, AG71XX_REG_RX_CTRL
, 0);
298 ag71xx_wr(ag
, AG71XX_REG_TX_CTRL
, 0);
300 /* disable all interrupts */
301 ag71xx_wr(ag
, AG71XX_REG_INT_ENABLE
, 0);
304 static int ag71xx_open(struct net_device
*dev
)
306 struct ag71xx
*ag
= netdev_priv(dev
);
309 ret
= ag71xx_rings_init(ag
);
313 napi_enable(&ag
->napi
);
315 netif_carrier_off(dev
);
316 ag71xx_phy_start(ag
);
318 ag71xx_wr(ag
, AG71XX_REG_TX_DESC
, ag
->tx_ring
.descs_dma
);
319 ag71xx_wr(ag
, AG71XX_REG_RX_DESC
, ag
->rx_ring
.descs_dma
);
321 ag71xx_hw_set_macaddr(ag
, dev
->dev_addr
);
325 netif_start_queue(dev
);
330 ag71xx_rings_cleanup(ag
);
334 static int ag71xx_stop(struct net_device
*dev
)
336 struct ag71xx
*ag
= netdev_priv(dev
);
339 spin_lock_irqsave(&ag
->lock
, flags
);
341 netif_stop_queue(dev
);
345 netif_carrier_off(dev
);
348 napi_disable(&ag
->napi
);
350 spin_unlock_irqrestore(&ag
->lock
, flags
);
352 ag71xx_rings_cleanup(ag
);
357 static int ag71xx_hard_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
359 struct ag71xx
*ag
= netdev_priv(dev
);
360 struct ag71xx_platform_data
*pdata
= ag71xx_get_pdata(ag
);
361 struct ag71xx_ring
*ring
= &ag
->tx_ring
;
362 struct ag71xx_desc
*desc
;
366 i
= ring
->curr
% AG71XX_TX_RING_SIZE
;
367 desc
= &ring
->descs
[i
];
369 spin_lock_irqsave(&ag
->lock
, flags
);
370 ar71xx_ddr_flush(pdata
->flush_reg
);
371 spin_unlock_irqrestore(&ag
->lock
, flags
);
373 if (!ag71xx_desc_empty(desc
))
377 DBG("%s: packet len is too small\n", ag
->dev
->name
);
381 dma_cache_wback_inv((unsigned long)skb
->data
, skb
->len
);
383 ring
->buf
[i
].skb
= skb
;
385 /* setup descriptor fields */
386 desc
->data
= virt_to_phys(skb
->data
);
387 desc
->ctrl
= (skb
->len
& DESC_PKTLEN_M
);
389 /* flush descriptor */
393 if (ring
->curr
== (ring
->dirty
+ AG71XX_TX_THRES_STOP
)) {
394 DBG("%s: tx queue full\n", ag
->dev
->name
);
395 netif_stop_queue(dev
);
398 DBG("%s: packet injected into TX queue\n", ag
->dev
->name
);
400 /* enable TX engine */
401 ag71xx_wr(ag
, AG71XX_REG_TX_CTRL
, TX_CTRL_TXE
);
403 dev
->trans_start
= jiffies
;
408 dev
->stats
.tx_dropped
++;
414 static int ag71xx_do_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
416 struct mii_ioctl_data
*data
= (struct mii_ioctl_data
*) &ifr
->ifr_data
;
417 struct ag71xx
*ag
= netdev_priv(dev
);
422 if (ag
->phy_dev
== NULL
)
425 spin_lock_irq(&ag
->lock
);
426 ret
= phy_ethtool_ioctl(ag
->phy_dev
, (void *) ifr
->ifr_data
);
427 spin_unlock_irq(&ag
->lock
);
432 (dev
->dev_addr
, ifr
->ifr_data
, sizeof(dev
->dev_addr
)))
438 (ifr
->ifr_data
, dev
->dev_addr
, sizeof(dev
->dev_addr
)))
445 if (ag
->phy_dev
== NULL
)
448 return phy_mii_ioctl(ag
->phy_dev
, data
, cmd
);
457 static void ag71xx_tx_packets(struct ag71xx
*ag
)
459 struct ag71xx_platform_data
*pdata
= ag71xx_get_pdata(ag
);
460 struct ag71xx_ring
*ring
= &ag
->tx_ring
;
463 DBG("%s: processing TX ring\n", ag
->dev
->name
);
465 #ifdef AG71XX_NAPI_TX
466 ar71xx_ddr_flush(pdata
->flush_reg
);
470 while (ring
->dirty
!= ring
->curr
) {
471 unsigned int i
= ring
->dirty
% AG71XX_TX_RING_SIZE
;
472 struct ag71xx_desc
*desc
= &ring
->descs
[i
];
473 struct sk_buff
*skb
= ring
->buf
[i
].skb
;
475 if (!ag71xx_desc_empty(desc
))
478 ag71xx_wr(ag
, AG71XX_REG_TX_STATUS
, TX_STATUS_PS
);
480 ag
->dev
->stats
.tx_bytes
+= skb
->len
;
481 ag
->dev
->stats
.tx_packets
++;
483 dev_kfree_skb_any(skb
);
484 ring
->buf
[i
].skb
= NULL
;
490 DBG("%s: %d packets sent out\n", ag
->dev
->name
, sent
);
492 if ((ring
->curr
- ring
->dirty
) < AG71XX_TX_THRES_WAKEUP
)
493 netif_wake_queue(ag
->dev
);
497 static int ag71xx_rx_packets(struct ag71xx
*ag
, int limit
)
499 struct net_device
*dev
= ag
->dev
;
500 struct ag71xx_ring
*ring
= &ag
->rx_ring
;
501 #ifndef AG71XX_NAPI_TX
502 struct ag71xx_platform_data
*pdata
= ag71xx_get_pdata(ag
);
507 #ifndef AG71XX_NAPI_TX
508 spin_lock_irqsave(&ag
->lock
, flags
);
509 ar71xx_ddr_flush(pdata
->flush_reg
);
510 spin_unlock_irqrestore(&ag
->lock
, flags
);
513 DBG("%s: rx packets, limit=%d, curr=%u, dirty=%u\n",
514 dev
->name
, limit
, ring
->curr
, ring
->dirty
);
516 while (done
< limit
) {
517 unsigned int i
= ring
->curr
% AG71XX_RX_RING_SIZE
;
518 struct ag71xx_desc
*desc
= &ring
->descs
[i
];
522 if (ag71xx_desc_empty(desc
))
525 if ((ring
->dirty
+ AG71XX_RX_RING_SIZE
) == ring
->curr
) {
530 skb
= ring
->buf
[i
].skb
;
531 pktlen
= ag71xx_desc_pktlen(desc
);
532 pktlen
-= ETH_FCS_LEN
;
534 /* TODO: move it into the refill function */
535 dma_cache_wback_inv((unsigned long)skb
->data
, pktlen
);
536 skb_put(skb
, pktlen
);
539 skb
->protocol
= eth_type_trans(skb
, dev
);
540 skb
->ip_summed
= CHECKSUM_UNNECESSARY
;
542 netif_receive_skb(skb
);
544 dev
->last_rx
= jiffies
;
545 dev
->stats
.rx_packets
++;
546 dev
->stats
.rx_bytes
+= pktlen
;
548 ring
->buf
[i
].skb
= NULL
;
551 ag71xx_wr(ag
, AG71XX_REG_RX_STATUS
, RX_STATUS_PR
);
554 if ((ring
->curr
- ring
->dirty
) > (AG71XX_RX_RING_SIZE
/ 4))
555 ag71xx_ring_rx_refill(ag
);
558 ag71xx_ring_rx_refill(ag
);
560 DBG("%s: rx finish, curr=%u, dirty=%u, done=%d\n",
561 dev
->name
, ring
->curr
, ring
->dirty
, done
);
566 static int ag71xx_poll(struct napi_struct
*napi
, int limit
)
568 struct ag71xx
*ag
= container_of(napi
, struct ag71xx
, napi
);
569 #ifdef AG71XX_NAPI_TX
570 struct ag71xx_platform_data
*pdata
= ag71xx_get_pdata(ag
);
572 struct net_device
*dev
= ag
->dev
;
577 #ifdef AG71XX_NAPI_TX
578 ar71xx_ddr_flush(pdata
->flush_reg
);
579 ag71xx_tx_packets(ag
);
582 DBG("%s: processing RX ring\n", dev
->name
);
583 done
= ag71xx_rx_packets(ag
, limit
);
585 /* TODO: add OOM handler */
587 status
= ag71xx_rr(ag
, AG71XX_REG_INT_STATUS
);
588 status
&= AG71XX_INT_POLL
;
590 if ((done
< limit
) && (!status
)) {
591 DBG("%s: disable polling mode, done=%d, status=%x\n",
592 dev
->name
, done
, status
);
594 netif_rx_complete(dev
, napi
);
596 /* enable interrupts */
597 spin_lock_irqsave(&ag
->lock
, flags
);
598 ag71xx_int_enable(ag
, AG71XX_INT_POLL
);
599 spin_unlock_irqrestore(&ag
->lock
, flags
);
603 if (status
& AG71XX_INT_RX_OF
) {
604 printk(KERN_ALERT
"%s: rx owerflow, restarting dma\n",
608 ag71xx_wr(ag
, AG71XX_REG_RX_STATUS
, RX_STATUS_OF
);
610 ag71xx_wr(ag
, AG71XX_REG_RX_CTRL
, RX_CTRL_RXE
);
613 DBG("%s: stay in polling mode, done=%d, status=%x\n",
614 dev
->name
, done
, status
);
618 static irqreturn_t
ag71xx_interrupt(int irq
, void *dev_id
)
620 struct net_device
*dev
= dev_id
;
621 struct ag71xx
*ag
= netdev_priv(dev
);
624 status
= ag71xx_rr(ag
, AG71XX_REG_INT_STATUS
);
625 status
&= ag71xx_rr(ag
, AG71XX_REG_INT_ENABLE
);
627 if (unlikely(!status
))
630 if (unlikely(status
& AG71XX_INT_ERR
)) {
631 if (status
& AG71XX_INT_TX_BE
) {
632 ag71xx_wr(ag
, AG71XX_REG_TX_STATUS
, TX_STATUS_BE
);
633 dev_err(&dev
->dev
, "TX BUS error\n");
635 if (status
& AG71XX_INT_RX_BE
) {
636 ag71xx_wr(ag
, AG71XX_REG_RX_STATUS
, RX_STATUS_BE
);
637 dev_err(&dev
->dev
, "RX BUS error\n");
642 if (unlikely(status
& AG71XX_INT_TX_UR
)) {
643 ag71xx_wr(ag
, AG71XX_REG_TX_STATUS
, TX_STATUS_UR
);
644 DBG("%s: TX underrun\n", dev
->name
);
648 #ifndef AG71XX_NAPI_TX
649 if (likely(status
& AG71XX_INT_TX_PS
))
650 ag71xx_tx_packets(ag
);
653 if (likely(status
& AG71XX_INT_POLL
)) {
654 ag71xx_int_disable(ag
, AG71XX_INT_POLL
);
655 DBG("%s: enable polling mode\n", dev
->name
);
656 netif_rx_schedule(dev
, &ag
->napi
);
662 static void ag71xx_set_multicast_list(struct net_device
*dev
)
667 static int __init
ag71xx_probe(struct platform_device
*pdev
)
669 struct net_device
*dev
;
670 struct resource
*res
;
672 struct ag71xx_platform_data
*pdata
;
675 pdata
= pdev
->dev
.platform_data
;
677 dev_err(&pdev
->dev
, "no platform data specified\n");
682 dev
= alloc_etherdev(sizeof(*ag
));
684 dev_err(&pdev
->dev
, "alloc_etherdev failed\n");
689 SET_NETDEV_DEV(dev
, &pdev
->dev
);
691 ag
= netdev_priv(dev
);
694 ag
->mii_bus
= &ag71xx_mdio_bus
->mii_bus
;
695 spin_lock_init(&ag
->lock
);
697 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "mac_base");
699 dev_err(&pdev
->dev
, "no mac_base resource found\n");
704 ag
->mac_base
= ioremap_nocache(res
->start
, res
->end
- res
->start
+ 1);
706 dev_err(&pdev
->dev
, "unable to ioremap mac_base\n");
711 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "mac_base2");
713 dev_err(&pdev
->dev
, "no mac_base2 resource found\n");
715 goto err_unmap_base1
;
718 ag
->mac_base2
= ioremap_nocache(res
->start
, res
->end
- res
->start
+ 1);
720 dev_err(&pdev
->dev
, "unable to ioremap mac_base2\n");
722 goto err_unmap_base1
;
725 res
= platform_get_resource_byname(pdev
, IORESOURCE_MEM
, "mii_ctrl");
727 dev_err(&pdev
->dev
, "no mii_ctrl resource found\n");
729 goto err_unmap_base2
;
732 ag
->mii_ctrl
= ioremap_nocache(res
->start
, res
->end
- res
->start
+ 1);
734 dev_err(&pdev
->dev
, "unable to ioremap mii_ctrl\n");
736 goto err_unmap_base2
;
739 dev
->irq
= platform_get_irq(pdev
, 0);
740 err
= request_irq(dev
->irq
, ag71xx_interrupt
,
741 IRQF_DISABLED
| IRQF_SAMPLE_RANDOM
,
744 dev_err(&pdev
->dev
, "unable to request IRQ %d\n", dev
->irq
);
745 goto err_unmap_mii_ctrl
;
748 dev
->base_addr
= (unsigned long)ag
->mac_base
;
749 dev
->open
= ag71xx_open
;
750 dev
->stop
= ag71xx_stop
;
751 dev
->hard_start_xmit
= ag71xx_hard_start_xmit
;
752 dev
->set_multicast_list
= ag71xx_set_multicast_list
;
753 dev
->do_ioctl
= ag71xx_do_ioctl
;
754 dev
->ethtool_ops
= &ag71xx_ethtool_ops
;
756 netif_napi_add(dev
, &ag
->napi
, ag71xx_poll
, AG71XX_NAPI_WEIGHT
);
758 if (is_valid_ether_addr(pdata
->mac_addr
))
759 memcpy(dev
->dev_addr
, pdata
->mac_addr
, ETH_ALEN
);
761 dev
->dev_addr
[0] = 0xde;
762 dev
->dev_addr
[1] = 0xad;
763 get_random_bytes(&dev
->dev_addr
[2], 3);
764 dev
->dev_addr
[5] = pdev
->id
& 0xff;
767 err
= register_netdev(dev
);
769 dev_err(&pdev
->dev
, "unable to register net device\n");
773 printk(KERN_INFO
"%s: Atheros AG71xx at 0x%08lx, irq %d\n",
774 dev
->name
, dev
->base_addr
, dev
->irq
);
776 ag71xx_dump_regs(ag
);
780 ag71xx_dump_regs(ag
);
782 /* Reset the mdio bus explicitly */
784 mutex_lock(&ag
->mii_bus
->mdio_lock
);
785 ag
->mii_bus
->reset(ag
->mii_bus
);
786 mutex_unlock(&ag
->mii_bus
->mdio_lock
);
789 err
= ag71xx_phy_connect(ag
);
791 goto err_unregister_netdev
;
793 platform_set_drvdata(pdev
, dev
);
797 err_unregister_netdev
:
798 unregister_netdev(dev
);
800 free_irq(dev
->irq
, dev
);
802 iounmap(ag
->mii_ctrl
);
804 iounmap(ag
->mac_base2
);
806 iounmap(ag
->mac_base
);
810 platform_set_drvdata(pdev
, NULL
);
814 static int __exit
ag71xx_remove(struct platform_device
*pdev
)
816 struct net_device
*dev
= platform_get_drvdata(pdev
);
819 struct ag71xx
*ag
= netdev_priv(dev
);
821 ag71xx_phy_disconnect(ag
);
822 unregister_netdev(dev
);
823 free_irq(dev
->irq
, dev
);
824 iounmap(ag
->mii_ctrl
);
825 iounmap(ag
->mac_base2
);
826 iounmap(ag
->mac_base
);
828 platform_set_drvdata(pdev
, NULL
);
834 static struct platform_driver ag71xx_driver
= {
835 .probe
= ag71xx_probe
,
836 .remove
= __exit_p(ag71xx_remove
),
838 .name
= AG71XX_DRV_NAME
,
842 static int __init
ag71xx_module_init(void)
846 ret
= ag71xx_mdio_driver_init();
850 ret
= platform_driver_register(&ag71xx_driver
);
857 ag71xx_mdio_driver_exit();
862 static void __exit
ag71xx_module_exit(void)
864 platform_driver_unregister(&ag71xx_driver
);
867 module_init(ag71xx_module_init
);
868 module_exit(ag71xx_module_exit
);
870 MODULE_VERSION(AG71XX_DRV_VERSION
);
871 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
872 MODULE_AUTHOR("Imre Kaloz <kaloz@openwrt.org>");
873 MODULE_LICENSE("GPL v2");
874 MODULE_ALIAS("platform:" AG71XX_DRV_NAME
);