ar71xx: ethernet: reduce tx and rx DMA ring size to improve cache footprint
[openwrt/openwrt.git] / target / linux / ar71xx / files / drivers / net / ethernet / atheros / ag71xx / ag71xx.h
1 /*
2 * Atheros AR71xx built-in ethernet mac driver
3 *
4 * Copyright (C) 2008-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2008 Imre Kaloz <kaloz@openwrt.org>
6 *
7 * Based on Atheros' AG7100 driver
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14 #ifndef __AG71XX_H
15 #define __AG71XX_H
16
17 #include <linux/kernel.h>
18 #include <linux/version.h>
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/types.h>
22 #include <linux/random.h>
23 #include <linux/spinlock.h>
24 #include <linux/interrupt.h>
25 #include <linux/platform_device.h>
26 #include <linux/ethtool.h>
27 #include <linux/etherdevice.h>
28 #include <linux/if_vlan.h>
29 #include <linux/phy.h>
30 #include <linux/skbuff.h>
31 #include <linux/dma-mapping.h>
32 #include <linux/workqueue.h>
33
34 #include <linux/bitops.h>
35
36 #include <asm/mach-ath79/ar71xx_regs.h>
37 #include <asm/mach-ath79/ath79.h>
38 #include <asm/mach-ath79/ag71xx_platform.h>
39
40 #define AG71XX_DRV_NAME "ag71xx"
41 #define AG71XX_DRV_VERSION "0.5.35"
42
43 #define AG71XX_NAPI_WEIGHT 64
44 #define AG71XX_OOM_REFILL (1 + HZ/10)
45
46 #define AG71XX_INT_ERR (AG71XX_INT_RX_BE | AG71XX_INT_TX_BE)
47 #define AG71XX_INT_TX (AG71XX_INT_TX_PS)
48 #define AG71XX_INT_RX (AG71XX_INT_RX_PR | AG71XX_INT_RX_OF)
49
50 #define AG71XX_INT_POLL (AG71XX_INT_RX | AG71XX_INT_TX)
51 #define AG71XX_INT_INIT (AG71XX_INT_ERR | AG71XX_INT_POLL)
52
53 #define AG71XX_TX_MTU_LEN 1540
54 #define AG71XX_RX_PKT_SIZE \
55 (ETH_FRAME_LEN + ETH_FCS_LEN + VLAN_HLEN)
56 #define AG71XX_RX_BUF_SIZE (AG71XX_RX_PKT_SIZE + NET_SKB_PAD + NET_IP_ALIGN)
57
58 #define AG71XX_TX_RING_SIZE_DEFAULT 64
59 #define AG71XX_RX_RING_SIZE_DEFAULT 128
60
61 #define AG71XX_TX_RING_SIZE_MAX 128
62 #define AG71XX_RX_RING_SIZE_MAX 128
63
64 #ifdef CONFIG_AG71XX_DEBUG
65 #define DBG(fmt, args...) pr_debug(fmt, ## args)
66 #else
67 #define DBG(fmt, args...) do {} while (0)
68 #endif
69
70 #define ag71xx_assert(_cond) \
71 do { \
72 if (_cond) \
73 break; \
74 printk("%s,%d: assertion failed\n", __FILE__, __LINE__); \
75 BUG(); \
76 } while (0)
77
78 struct ag71xx_desc {
79 u32 data;
80 u32 ctrl;
81 #define DESC_EMPTY BIT(31)
82 #define DESC_MORE BIT(24)
83 #define DESC_PKTLEN_M 0xfff
84 u32 next;
85 u32 pad;
86 } __attribute__((aligned(4)));
87
88 struct ag71xx_buf {
89 union {
90 struct sk_buff *skb;
91 void *rx_buf;
92 };
93 struct ag71xx_desc *desc;
94 union {
95 dma_addr_t dma_addr;
96 unsigned long timestamp;
97 };
98 unsigned int len;
99 };
100
101 struct ag71xx_ring {
102 struct ag71xx_buf *buf;
103 u8 *descs_cpu;
104 dma_addr_t descs_dma;
105 unsigned int desc_size;
106 unsigned int curr;
107 unsigned int dirty;
108 unsigned int size;
109 };
110
111 struct ag71xx_mdio {
112 struct mii_bus *mii_bus;
113 int mii_irq[PHY_MAX_ADDR];
114 void __iomem *mdio_base;
115 struct ag71xx_mdio_platform_data *pdata;
116 };
117
118 struct ag71xx_int_stats {
119 unsigned long rx_pr;
120 unsigned long rx_be;
121 unsigned long rx_of;
122 unsigned long tx_ps;
123 unsigned long tx_be;
124 unsigned long tx_ur;
125 unsigned long total;
126 };
127
128 struct ag71xx_napi_stats {
129 unsigned long napi_calls;
130 unsigned long rx_count;
131 unsigned long rx_packets;
132 unsigned long rx_packets_max;
133 unsigned long tx_count;
134 unsigned long tx_packets;
135 unsigned long tx_packets_max;
136
137 unsigned long rx[AG71XX_NAPI_WEIGHT + 1];
138 unsigned long tx[AG71XX_NAPI_WEIGHT + 1];
139 };
140
141 struct ag71xx_debug {
142 struct dentry *debugfs_dir;
143
144 struct ag71xx_int_stats int_stats;
145 struct ag71xx_napi_stats napi_stats;
146 };
147
148 struct ag71xx {
149 void __iomem *mac_base;
150
151 spinlock_t lock;
152 struct platform_device *pdev;
153 struct net_device *dev;
154 struct napi_struct napi;
155 u32 msg_enable;
156
157 struct ag71xx_desc *stop_desc;
158 dma_addr_t stop_desc_dma;
159
160 struct ag71xx_ring rx_ring;
161 struct ag71xx_ring tx_ring;
162
163 struct mii_bus *mii_bus;
164 struct phy_device *phy_dev;
165 void *phy_priv;
166
167 unsigned int link;
168 unsigned int speed;
169 int duplex;
170
171 struct work_struct restart_work;
172 struct delayed_work link_work;
173 struct timer_list oom_timer;
174
175 #ifdef CONFIG_AG71XX_DEBUG_FS
176 struct ag71xx_debug debug;
177 #endif
178 };
179
180 extern struct ethtool_ops ag71xx_ethtool_ops;
181 void ag71xx_link_adjust(struct ag71xx *ag);
182
183 int ag71xx_mdio_driver_init(void) __init;
184 void ag71xx_mdio_driver_exit(void);
185
186 int ag71xx_phy_connect(struct ag71xx *ag);
187 void ag71xx_phy_disconnect(struct ag71xx *ag);
188 void ag71xx_phy_start(struct ag71xx *ag);
189 void ag71xx_phy_stop(struct ag71xx *ag);
190
191 static inline struct ag71xx_platform_data *ag71xx_get_pdata(struct ag71xx *ag)
192 {
193 return ag->pdev->dev.platform_data;
194 }
195
196 static inline int ag71xx_desc_empty(struct ag71xx_desc *desc)
197 {
198 return (desc->ctrl & DESC_EMPTY) != 0;
199 }
200
201 static inline int ag71xx_desc_pktlen(struct ag71xx_desc *desc)
202 {
203 return desc->ctrl & DESC_PKTLEN_M;
204 }
205
206 /* Register offsets */
207 #define AG71XX_REG_MAC_CFG1 0x0000
208 #define AG71XX_REG_MAC_CFG2 0x0004
209 #define AG71XX_REG_MAC_IPG 0x0008
210 #define AG71XX_REG_MAC_HDX 0x000c
211 #define AG71XX_REG_MAC_MFL 0x0010
212 #define AG71XX_REG_MII_CFG 0x0020
213 #define AG71XX_REG_MII_CMD 0x0024
214 #define AG71XX_REG_MII_ADDR 0x0028
215 #define AG71XX_REG_MII_CTRL 0x002c
216 #define AG71XX_REG_MII_STATUS 0x0030
217 #define AG71XX_REG_MII_IND 0x0034
218 #define AG71XX_REG_MAC_IFCTL 0x0038
219 #define AG71XX_REG_MAC_ADDR1 0x0040
220 #define AG71XX_REG_MAC_ADDR2 0x0044
221 #define AG71XX_REG_FIFO_CFG0 0x0048
222 #define AG71XX_REG_FIFO_CFG1 0x004c
223 #define AG71XX_REG_FIFO_CFG2 0x0050
224 #define AG71XX_REG_FIFO_CFG3 0x0054
225 #define AG71XX_REG_FIFO_CFG4 0x0058
226 #define AG71XX_REG_FIFO_CFG5 0x005c
227 #define AG71XX_REG_FIFO_RAM0 0x0060
228 #define AG71XX_REG_FIFO_RAM1 0x0064
229 #define AG71XX_REG_FIFO_RAM2 0x0068
230 #define AG71XX_REG_FIFO_RAM3 0x006c
231 #define AG71XX_REG_FIFO_RAM4 0x0070
232 #define AG71XX_REG_FIFO_RAM5 0x0074
233 #define AG71XX_REG_FIFO_RAM6 0x0078
234 #define AG71XX_REG_FIFO_RAM7 0x007c
235
236 #define AG71XX_REG_TX_CTRL 0x0180
237 #define AG71XX_REG_TX_DESC 0x0184
238 #define AG71XX_REG_TX_STATUS 0x0188
239 #define AG71XX_REG_RX_CTRL 0x018c
240 #define AG71XX_REG_RX_DESC 0x0190
241 #define AG71XX_REG_RX_STATUS 0x0194
242 #define AG71XX_REG_INT_ENABLE 0x0198
243 #define AG71XX_REG_INT_STATUS 0x019c
244
245 #define AG71XX_REG_FIFO_DEPTH 0x01a8
246 #define AG71XX_REG_RX_SM 0x01b0
247 #define AG71XX_REG_TX_SM 0x01b4
248
249 #define MAC_CFG1_TXE BIT(0) /* Tx Enable */
250 #define MAC_CFG1_STX BIT(1) /* Synchronize Tx Enable */
251 #define MAC_CFG1_RXE BIT(2) /* Rx Enable */
252 #define MAC_CFG1_SRX BIT(3) /* Synchronize Rx Enable */
253 #define MAC_CFG1_TFC BIT(4) /* Tx Flow Control Enable */
254 #define MAC_CFG1_RFC BIT(5) /* Rx Flow Control Enable */
255 #define MAC_CFG1_LB BIT(8) /* Loopback mode */
256 #define MAC_CFG1_SR BIT(31) /* Soft Reset */
257
258 #define MAC_CFG2_FDX BIT(0)
259 #define MAC_CFG2_CRC_EN BIT(1)
260 #define MAC_CFG2_PAD_CRC_EN BIT(2)
261 #define MAC_CFG2_LEN_CHECK BIT(4)
262 #define MAC_CFG2_HUGE_FRAME_EN BIT(5)
263 #define MAC_CFG2_IF_1000 BIT(9)
264 #define MAC_CFG2_IF_10_100 BIT(8)
265
266 #define FIFO_CFG0_WTM BIT(0) /* Watermark Module */
267 #define FIFO_CFG0_RXS BIT(1) /* Rx System Module */
268 #define FIFO_CFG0_RXF BIT(2) /* Rx Fabric Module */
269 #define FIFO_CFG0_TXS BIT(3) /* Tx System Module */
270 #define FIFO_CFG0_TXF BIT(4) /* Tx Fabric Module */
271 #define FIFO_CFG0_ALL (FIFO_CFG0_WTM | FIFO_CFG0_RXS | FIFO_CFG0_RXF \
272 | FIFO_CFG0_TXS | FIFO_CFG0_TXF)
273
274 #define FIFO_CFG0_ENABLE_SHIFT 8
275
276 #define FIFO_CFG4_DE BIT(0) /* Drop Event */
277 #define FIFO_CFG4_DV BIT(1) /* RX_DV Event */
278 #define FIFO_CFG4_FC BIT(2) /* False Carrier */
279 #define FIFO_CFG4_CE BIT(3) /* Code Error */
280 #define FIFO_CFG4_CR BIT(4) /* CRC error */
281 #define FIFO_CFG4_LM BIT(5) /* Length Mismatch */
282 #define FIFO_CFG4_LO BIT(6) /* Length out of range */
283 #define FIFO_CFG4_OK BIT(7) /* Packet is OK */
284 #define FIFO_CFG4_MC BIT(8) /* Multicast Packet */
285 #define FIFO_CFG4_BC BIT(9) /* Broadcast Packet */
286 #define FIFO_CFG4_DR BIT(10) /* Dribble */
287 #define FIFO_CFG4_LE BIT(11) /* Long Event */
288 #define FIFO_CFG4_CF BIT(12) /* Control Frame */
289 #define FIFO_CFG4_PF BIT(13) /* Pause Frame */
290 #define FIFO_CFG4_UO BIT(14) /* Unsupported Opcode */
291 #define FIFO_CFG4_VT BIT(15) /* VLAN tag detected */
292 #define FIFO_CFG4_FT BIT(16) /* Frame Truncated */
293 #define FIFO_CFG4_UC BIT(17) /* Unicast Packet */
294
295 #define FIFO_CFG5_DE BIT(0) /* Drop Event */
296 #define FIFO_CFG5_DV BIT(1) /* RX_DV Event */
297 #define FIFO_CFG5_FC BIT(2) /* False Carrier */
298 #define FIFO_CFG5_CE BIT(3) /* Code Error */
299 #define FIFO_CFG5_LM BIT(4) /* Length Mismatch */
300 #define FIFO_CFG5_LO BIT(5) /* Length Out of Range */
301 #define FIFO_CFG5_OK BIT(6) /* Packet is OK */
302 #define FIFO_CFG5_MC BIT(7) /* Multicast Packet */
303 #define FIFO_CFG5_BC BIT(8) /* Broadcast Packet */
304 #define FIFO_CFG5_DR BIT(9) /* Dribble */
305 #define FIFO_CFG5_CF BIT(10) /* Control Frame */
306 #define FIFO_CFG5_PF BIT(11) /* Pause Frame */
307 #define FIFO_CFG5_UO BIT(12) /* Unsupported Opcode */
308 #define FIFO_CFG5_VT BIT(13) /* VLAN tag detected */
309 #define FIFO_CFG5_LE BIT(14) /* Long Event */
310 #define FIFO_CFG5_FT BIT(15) /* Frame Truncated */
311 #define FIFO_CFG5_16 BIT(16) /* unknown */
312 #define FIFO_CFG5_17 BIT(17) /* unknown */
313 #define FIFO_CFG5_SF BIT(18) /* Short Frame */
314 #define FIFO_CFG5_BM BIT(19) /* Byte Mode */
315
316 #define AG71XX_INT_TX_PS BIT(0)
317 #define AG71XX_INT_TX_UR BIT(1)
318 #define AG71XX_INT_TX_BE BIT(3)
319 #define AG71XX_INT_RX_PR BIT(4)
320 #define AG71XX_INT_RX_OF BIT(6)
321 #define AG71XX_INT_RX_BE BIT(7)
322
323 #define MAC_IFCTL_SPEED BIT(16)
324
325 #define MII_CFG_CLK_DIV_4 0
326 #define MII_CFG_CLK_DIV_6 2
327 #define MII_CFG_CLK_DIV_8 3
328 #define MII_CFG_CLK_DIV_10 4
329 #define MII_CFG_CLK_DIV_14 5
330 #define MII_CFG_CLK_DIV_20 6
331 #define MII_CFG_CLK_DIV_28 7
332 #define MII_CFG_CLK_DIV_34 8
333 #define MII_CFG_CLK_DIV_42 9
334 #define MII_CFG_CLK_DIV_50 10
335 #define MII_CFG_CLK_DIV_58 11
336 #define MII_CFG_CLK_DIV_66 12
337 #define MII_CFG_CLK_DIV_74 13
338 #define MII_CFG_CLK_DIV_82 14
339 #define MII_CFG_CLK_DIV_98 15
340 #define MII_CFG_RESET BIT(31)
341
342 #define MII_CMD_WRITE 0x0
343 #define MII_CMD_READ 0x1
344 #define MII_ADDR_SHIFT 8
345 #define MII_IND_BUSY BIT(0)
346 #define MII_IND_INVALID BIT(2)
347
348 #define TX_CTRL_TXE BIT(0) /* Tx Enable */
349
350 #define TX_STATUS_PS BIT(0) /* Packet Sent */
351 #define TX_STATUS_UR BIT(1) /* Tx Underrun */
352 #define TX_STATUS_BE BIT(3) /* Bus Error */
353
354 #define RX_CTRL_RXE BIT(0) /* Rx Enable */
355
356 #define RX_STATUS_PR BIT(0) /* Packet Received */
357 #define RX_STATUS_OF BIT(2) /* Rx Overflow */
358 #define RX_STATUS_BE BIT(3) /* Bus Error */
359
360 static inline void ag71xx_check_reg_offset(struct ag71xx *ag, unsigned reg)
361 {
362 switch (reg) {
363 case AG71XX_REG_MAC_CFG1 ... AG71XX_REG_MAC_MFL:
364 case AG71XX_REG_MAC_IFCTL ... AG71XX_REG_TX_SM:
365 case AG71XX_REG_MII_CFG:
366 break;
367
368 default:
369 BUG();
370 }
371 }
372
373 static inline void ag71xx_wr(struct ag71xx *ag, unsigned reg, u32 value)
374 {
375 ag71xx_check_reg_offset(ag, reg);
376
377 __raw_writel(value, ag->mac_base + reg);
378 /* flush write */
379 (void) __raw_readl(ag->mac_base + reg);
380 }
381
382 static inline u32 ag71xx_rr(struct ag71xx *ag, unsigned reg)
383 {
384 ag71xx_check_reg_offset(ag, reg);
385
386 return __raw_readl(ag->mac_base + reg);
387 }
388
389 static inline void ag71xx_sb(struct ag71xx *ag, unsigned reg, u32 mask)
390 {
391 void __iomem *r;
392
393 ag71xx_check_reg_offset(ag, reg);
394
395 r = ag->mac_base + reg;
396 __raw_writel(__raw_readl(r) | mask, r);
397 /* flush write */
398 (void)__raw_readl(r);
399 }
400
401 static inline void ag71xx_cb(struct ag71xx *ag, unsigned reg, u32 mask)
402 {
403 void __iomem *r;
404
405 ag71xx_check_reg_offset(ag, reg);
406
407 r = ag->mac_base + reg;
408 __raw_writel(__raw_readl(r) & ~mask, r);
409 /* flush write */
410 (void) __raw_readl(r);
411 }
412
413 static inline void ag71xx_int_enable(struct ag71xx *ag, u32 ints)
414 {
415 ag71xx_sb(ag, AG71XX_REG_INT_ENABLE, ints);
416 }
417
418 static inline void ag71xx_int_disable(struct ag71xx *ag, u32 ints)
419 {
420 ag71xx_cb(ag, AG71XX_REG_INT_ENABLE, ints);
421 }
422
423 #ifdef CONFIG_AG71XX_AR8216_SUPPORT
424 void ag71xx_add_ar8216_header(struct ag71xx *ag, struct sk_buff *skb);
425 int ag71xx_remove_ar8216_header(struct ag71xx *ag, struct sk_buff *skb,
426 int pktlen);
427 static inline int ag71xx_has_ar8216(struct ag71xx *ag)
428 {
429 return ag71xx_get_pdata(ag)->has_ar8216;
430 }
431 #else
432 static inline void ag71xx_add_ar8216_header(struct ag71xx *ag,
433 struct sk_buff *skb)
434 {
435 }
436
437 static inline int ag71xx_remove_ar8216_header(struct ag71xx *ag,
438 struct sk_buff *skb,
439 int pktlen)
440 {
441 return 0;
442 }
443 static inline int ag71xx_has_ar8216(struct ag71xx *ag)
444 {
445 return 0;
446 }
447 #endif
448
449 #ifdef CONFIG_AG71XX_DEBUG_FS
450 int ag71xx_debugfs_root_init(void);
451 void ag71xx_debugfs_root_exit(void);
452 int ag71xx_debugfs_init(struct ag71xx *ag);
453 void ag71xx_debugfs_exit(struct ag71xx *ag);
454 void ag71xx_debugfs_update_int_stats(struct ag71xx *ag, u32 status);
455 void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag, int rx, int tx);
456 #else
457 static inline int ag71xx_debugfs_root_init(void) { return 0; }
458 static inline void ag71xx_debugfs_root_exit(void) {}
459 static inline int ag71xx_debugfs_init(struct ag71xx *ag) { return 0; }
460 static inline void ag71xx_debugfs_exit(struct ag71xx *ag) {}
461 static inline void ag71xx_debugfs_update_int_stats(struct ag71xx *ag,
462 u32 status) {}
463 static inline void ag71xx_debugfs_update_napi_stats(struct ag71xx *ag,
464 int rx, int tx) {}
465 #endif /* CONFIG_AG71XX_DEBUG_FS */
466
467 void ag71xx_ar7240_start(struct ag71xx *ag);
468 void ag71xx_ar7240_stop(struct ag71xx *ag);
469 int ag71xx_ar7240_init(struct ag71xx *ag);
470 void ag71xx_ar7240_cleanup(struct ag71xx *ag);
471
472 int ag71xx_mdio_mii_read(struct ag71xx_mdio *am, int addr, int reg);
473 void ag71xx_mdio_mii_write(struct ag71xx_mdio *am, int addr, int reg, u16 val);
474
475 u16 ar7240sw_phy_read(struct mii_bus *mii, unsigned phy_addr,
476 unsigned reg_addr);
477 int ar7240sw_phy_write(struct mii_bus *mii, unsigned phy_addr,
478 unsigned reg_addr, u16 reg_val);
479
480 #endif /* _AG71XX_H */