target/linux/ar71xx/patches-4.9/920-usb-chipidea-AR933x-platform-support.patch

   1 --- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
   2 +++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
   3 @@ -659,6 +659,7 @@
   4
   5  #define AR933X_BOOTSTRAP_MDIO_GPIO_EN  BIT(18)
   6  #define AR933X_BOOTSTRAP_EEPBUSY       BIT(4)
   7 +#define AR933X_BOOTSTRAP_USB_MODE_HOST BIT(3)
   8  #define AR933X_BOOTSTRAP_REF_CLK_40    BIT(0)
   9
  10  #define AR934X_BOOTSTRAP_SW_OPTION8    BIT(23)
  11 @@ -688,6 +689,8 @@
  12
  13  #define QCA956X_BOOTSTRAP_REF_CLK_40   BIT(2)
  14
  15 +#define AR933X_USB_CONFIG_HOST_ONLY   BIT(8)
  16 +
  17  #define AR934X_PCIE_WMAC_INT_WMAC_MISC         BIT(0)
  18  #define AR934X_PCIE_WMAC_INT_WMAC_TX           BIT(1)
  19  #define AR934X_PCIE_WMAC_INT_WMAC_RXLP         BIT(2)
  20 --- a/arch/mips/ath79/dev-usb.c
  21 +++ b/arch/mips/ath79/dev-usb.c
  22 @@ -19,6 +19,9 @@
  23  #include <linux/platform_device.h>
  24  #include <linux/usb/ehci_pdriver.h>
  25  #include <linux/usb/ohci_pdriver.h>
  26 +#include <linux/usb/otg.h>
  27 +#include <linux/usb/chipidea.h>
  28 +#include <linux/usb/usb_phy_generic.h>
  29
  30  #include <asm/mach-ath79/ath79.h>
  31  #include <asm/mach-ath79/ar71xx_regs.h>
  32 @@ -170,6 +173,64 @@ static void __init ar913x_usb_setup(void
  33                            &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
  34  }
  35
  36 +static void __init ar933x_usb_setup_ctrl_config(void)
  37 +{
  38 +       void __iomem *usb_ctrl_base, *usb_config_reg;
  39 +       u32 usb_config;
  40 +
  41 +       usb_ctrl_base = ioremap(AR71XX_USB_CTRL_BASE, AR71XX_USB_CTRL_SIZE);
  42 +       usb_config_reg = usb_ctrl_base + AR71XX_USB_CTRL_REG_CONFIG;
  43 +       usb_config = __raw_readl(usb_config_reg);
  44 +       usb_config &= ~AR933X_USB_CONFIG_HOST_ONLY;
  45 +       __raw_writel(usb_config, usb_config_reg);
  46 +       iounmap(usb_ctrl_base);
  47 +}
  48 +
  49 +static void __init ar9xxx_ci_usb_setup(int irq)
  50 +{
  51 +       struct ci_hdrc_platform_data ci_pdata;
  52 +       enum usb_dr_mode dr_mode;
  53 +       bool host_mode = true;
  54 +
  55 +       if (soc_is_ar933x())
  56 +               host_mode = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP) &
  57 +                           AR933X_BOOTSTRAP_USB_MODE_HOST;
  58 +       else if (soc_is_ar934x() || soc_is_qca955x())
  59 +               host_mode = !(ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP) &
  60 +                             AR934X_BOOTSTRAP_USB_MODE_DEVICE);
  61 +
  62 +       if (host_mode) {
  63 +               dr_mode = USB_DR_MODE_HOST;
  64 +       } else {
  65 +               dr_mode = USB_DR_MODE_PERIPHERAL;
  66 +               if (soc_is_ar933x())
  67 +                       ar933x_usb_setup_ctrl_config();
  68 +       }
  69 +
  70 +       memset(&ci_pdata, 0, sizeof(ci_pdata));
  71 +       ci_pdata.name = "ci_hdrc_ar9xxx";
  72 +       ci_pdata.capoffset = DEF_CAPOFFSET;
  73 +       ci_pdata.dr_mode = dr_mode;
  74 +       ci_pdata.flags = CI_HDRC_DUAL_ROLE_NOT_OTG | CI_HDRC_DP_ALWAYS_PULLUP;
  75 +       ci_pdata.vbus_extcon.edev = ERR_PTR(-ENODEV);
  76 +       ci_pdata.id_extcon.edev = ERR_PTR(-ENODEV);
  77 +       ci_pdata.itc_setting = 1;
  78 +
  79 +       platform_device_register_simple("usb_phy_generic",
  80 +                                       PLATFORM_DEVID_AUTO, NULL, 0);
  81 +
  82 +       if (!host_mode)
  83 +               ath79_usb_register("ci_hdrc", -1,
  84 +                                  AR933X_EHCI_BASE, AR933X_EHCI_SIZE,
  85 +                                  irq, &ci_pdata, sizeof(ci_pdata));
  86 +       else
  87 +               ath79_usb_register("ehci-platform", -1,
  88 +                                  AR934X_EHCI_BASE, AR934X_EHCI_SIZE,
  89 +                                  irq, &ath79_ehci_pdata_v2,
  90 +                                  sizeof(ath79_ehci_pdata_v2));
  91 +
  92 +}
  93 +
  94  static void __init ar933x_usb_setup(void)
  95  {
  96         ath79_device_reset_set(AR933X_RESET_USBSUS_OVERRIDE);
  97 @@ -181,10 +242,7 @@ static void __init ar933x_usb_setup(void
  98         ath79_device_reset_clear(AR933X_RESET_USB_PHY);
  99         mdelay(10);
 100
 101 -       ath79_usb_register("ehci-platform", -1,
 102 -                          AR933X_EHCI_BASE, AR933X_EHCI_SIZE,
 103 -                          ATH79_CPU_IRQ(3),
 104 -                          &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
 105 +       ar9xxx_ci_usb_setup(ATH79_CPU_IRQ(3));
 106  }
 107
 108  static void enable_tx_tx_idp_violation_fix(unsigned base)
 109 @@ -230,10 +288,7 @@ static void __init ar934x_usb_setup(void
 110         if (ath79_soc_rev >= 3)
 111                 ath79_ehci_pdata_v2.reset_notifier = ar934x_usb_reset_notifier;
 112
 113 -       ath79_usb_register("ehci-platform", -1,
 114 -                          AR934X_EHCI_BASE, AR934X_EHCI_SIZE,
 115 -                          ATH79_CPU_IRQ(3),
 116 -                          &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
 117 +       ar9xxx_ci_usb_setup(ATH79_CPU_IRQ(3));
 118  }
 119
 120  static void __init qca953x_usb_setup(void)
 121 @@ -285,10 +340,7 @@ static void __init qca955x_usb_setup(voi
 122  {
 123         ath79_ehci_pdata_v2.reset_notifier = qca955x_usb_reset_notifier;
 124
 125 -       ath79_usb_register("ehci-platform", 0,
 126 -                          QCA955X_EHCI0_BASE, QCA955X_EHCI_SIZE,
 127 -                          ATH79_IP3_IRQ(0),
 128 -                          &ath79_ehci_pdata_v2, sizeof(ath79_ehci_pdata_v2));
 129 +       ar9xxx_ci_usb_setup(ATH79_IP3_IRQ(0));
 130
 131         ath79_usb_register("ehci-platform", 1,
 132                            QCA955X_EHCI1_BASE, QCA955X_EHCI_SIZE,