ath79: create WNDR3700 series .dtsi and adjust WNDR3800
[openwrt/staging/stintel.git] / target / linux / ath79 / dts / ar7161_netgear_wndr3700.dtsi
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2 /dts-v1/;
3
4 #include <dt-bindings/gpio/gpio.h>
5 #include <dt-bindings/input/input.h>
6
7 #include "ar7100.dtsi"
8
9 / {
10 aliases {
11 led-status = &power_green;
12 };
13
14 chosen {
15 bootargs = "console=ttyS0,115200";
16 };
17
18 extosc: ref {
19 compatible = "fixed-clock";
20 #clock-cells = <0>;
21 clock-output-names = "ref";
22 clock-frequency = <40000000>;
23 };
24
25 reset-leds {
26 compatible = "reset-leds";
27
28 usb_led {
29 label = "netgear:green:usb";
30 resets = <&rst 12>;
31 trigger-sources = <&usb_ochi_port>, <&usb_echi_port>;
32 linux,default-trigger = "usbport";
33 };
34 };
35
36 gpio-leds {
37 compatible = "gpio-leds";
38
39 wps {
40 label = "netgear:orange:wps";
41 gpios = <&gpio 0 GPIO_ACTIVE_LOW>;
42 default-state = "off";
43 };
44
45 power_green: power_green {
46 label = "netgear:green:power";
47 gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
48 default-state = "off";
49 };
50
51 power_orange {
52 label = "netgear:orange:power";
53 gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
54 default-state = "off";
55 };
56
57 wps_green {
58 label = "netgear:green:wps";
59 gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
60 default-state = "off";
61 };
62
63 wan_green {
64 label = "netgear:green:wan";
65 gpios = <&gpio 6 GPIO_ACTIVE_LOW>;
66 default-state = "off";
67 };
68 };
69
70 gpio-keys-polled {
71 compatible = "gpio-keys-polled";
72 poll-interval = <100>;
73
74 wps {
75 label = "wps";
76 linux,code = <KEY_WPS_BUTTON>;
77 gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
78 };
79
80 reset {
81 label = "reset";
82 linux,code = <KEY_RESTART>;
83 gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
84 };
85
86 rfkill {
87 label = "rfkill";
88 linux,code = <KEY_RFKILL>;
89 gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
90 };
91 };
92
93 rtl8366s {
94 compatible = "realtek,rtl8366s";
95 gpio-sda = <&gpio 5 GPIO_ACTIVE_HIGH>;
96 gpio-sck = <&gpio 7 GPIO_ACTIVE_HIGH>;
97
98 mdio-bus {
99 #address-cells = <1>;
100 #size-cells = <0>;
101 status = "okay";
102
103 phy-mask = <0x10>;
104
105 phy4: ethernet-phy@4 {
106 reg = <4>;
107 phy-mode = "rgmii";
108 };
109 };
110 };
111 };
112
113 &usb_phy {
114 status = "okay";
115 };
116
117 &usb1 {
118 #address-cells = <1>;
119 #size-cells = <0>;
120 status = "okay";
121
122 usb_ochi_port: port@1 {
123 reg = <1>;
124 #trigger-source-cells = <0>;
125 };
126 };
127
128 &usb2 {
129 #address-cells = <1>;
130 #size-cells = <0>;
131 status = "okay";
132
133 usb_echi_port: port@1 {
134 reg = <1>;
135 #trigger-source-cells = <0>;
136 };
137 };
138
139 &pcie0 {
140 status = "okay";
141 };
142
143 &uart {
144 status = "okay";
145 };
146
147 &spi {
148 status = "okay";
149 num-cs = <1>;
150
151 flash@0 {
152 compatible = "jedec,spi-nor";
153 reg = <0>;
154 spi-max-frequency = <25000000>;
155
156 partitions: partitions {
157 compatible = "fixed-partitions";
158 #address-cells = <1>;
159 #size-cells = <1>;
160 };
161 };
162 };
163
164 &eth0 {
165 status = "okay";
166
167 pll-data = <0x11110000 0x00001099 0x00991099>;
168
169 mtd-mac-address = <&art 0x00>;
170
171 fixed-link {
172 speed = <1000>;
173 full-duplex;
174 };
175 };
176
177 &eth1 {
178 status = "okay";
179
180 pll-data = <0x11110000 0x00001099 0x00991099>;
181
182 mtd-mac-address = <&art 0x06>;
183
184 phy-handle = <&phy4>;
185 };