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atheros: rename some interrupt control handlers
[openwrt/staging/lynxis/omap.git] / target / linux / atheros / patches-3.10 / 100-board.patch
1 --- a/arch/mips/Kconfig
2 +++ b/arch/mips/Kconfig
3 @@ -138,6 +138,19 @@ config BCM63XX
4 help
5 Support for BCM63XX based boards
6
7 +config ATHEROS_AR231X
8 + bool "Atheros 231x/531x SoC support"
9 + select CEVT_R4K
10 + select CSRC_R4K
11 + select DMA_NONCOHERENT
12 + select IRQ_CPU
13 + select SYS_HAS_CPU_MIPS32_R1
14 + select SYS_SUPPORTS_BIG_ENDIAN
15 + select SYS_SUPPORTS_32BIT_KERNEL
16 + select ARCH_REQUIRE_GPIOLIB
17 + help
18 + Support for AR231x and AR531x based boards
19 +
20 config MIPS_COBALT
21 bool "Cobalt Server"
22 select CEVT_R4K
23 @@ -838,6 +851,7 @@ config NLM_XLP_BOARD
24
25 endchoice
26
27 +source "arch/mips/ar231x/Kconfig"
28 source "arch/mips/alchemy/Kconfig"
29 source "arch/mips/ath79/Kconfig"
30 source "arch/mips/bcm47xx/Kconfig"
31 --- a/arch/mips/Kbuild.platforms
32 +++ b/arch/mips/Kbuild.platforms
33 @@ -6,6 +6,7 @@ platforms += ath79
34 platforms += bcm47xx
35 platforms += bcm63xx
36 platforms += cavium-octeon
37 +platforms += ar231x
38 platforms += cobalt
39 platforms += dec
40 platforms += emma
41 --- /dev/null
42 +++ b/arch/mips/ar231x/Platform
43 @@ -0,0 +1,6 @@
44 +#
45 +# Atheros AR5312/AR2312 WiSoC
46 +#
47 +platform-$(CONFIG_ATHEROS_AR231X) += ar231x/
48 +cflags-$(CONFIG_ATHEROS_AR231X) += -I$(srctree)/arch/mips/include/asm/mach-ar231x
49 +load-$(CONFIG_ATHEROS_AR231X) += 0xffffffff80041000
50 --- /dev/null
51 +++ b/arch/mips/ar231x/Kconfig
52 @@ -0,0 +1,16 @@
53 +config ATHEROS_AR5312
54 + bool "Atheros 5312/2312+ support"
55 + depends on ATHEROS_AR231X
56 + default y
57 +
58 +config ATHEROS_AR2315
59 + bool "Atheros 2315+ support"
60 + depends on ATHEROS_AR231X
61 + select DMA_NONCOHERENT
62 + select CEVT_R4K
63 + select CSRC_R4K
64 + select IRQ_CPU
65 + select SYS_HAS_CPU_MIPS32_R1
66 + select SYS_SUPPORTS_32BIT_KERNEL
67 + select SYS_SUPPORTS_BIG_ENDIAN
68 + default y
69 --- /dev/null
70 +++ b/arch/mips/ar231x/Makefile
71 @@ -0,0 +1,13 @@
72 +#
73 +# This file is subject to the terms and conditions of the GNU General Public
74 +# License. See the file "COPYING" in the main directory of this archive
75 +# for more details.
76 +#
77 +# Copyright (C) 2006 FON Technology, SL.
78 +# Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
79 +# Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
80 +#
81 +
82 +obj-y += board.o prom.o devices.o
83 +obj-$(CONFIG_ATHEROS_AR5312) += ar5312.o
84 +obj-$(CONFIG_ATHEROS_AR2315) += ar2315.o
85 --- /dev/null
86 +++ b/arch/mips/ar231x/board.c
87 @@ -0,0 +1,261 @@
88 +/*
89 + * This file is subject to the terms and conditions of the GNU General Public
90 + * License. See the file "COPYING" in the main directory of this archive
91 + * for more details.
92 + *
93 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
94 + * Copyright (C) 2006 FON Technology, SL.
95 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
96 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
97 + */
98 +
99 +#include <generated/autoconf.h>
100 +#include <linux/init.h>
101 +#include <linux/module.h>
102 +#include <linux/types.h>
103 +#include <linux/string.h>
104 +#include <linux/platform_device.h>
105 +#include <linux/kernel.h>
106 +#include <linux/random.h>
107 +#include <linux/etherdevice.h>
108 +#include <linux/irq.h>
109 +#include <linux/io.h>
110 +#include <asm/irq_cpu.h>
111 +#include <asm/reboot.h>
112 +
113 +#include <ar231x_platform.h>
114 +#include "devices.h"
115 +#include "ar5312.h"
116 +#include "ar2315.h"
117 +
118 +void (*ar231x_irq_dispatch)(void);
119 +
120 +static inline bool
121 +check_radio_magic(u8 *addr)
122 +{
123 + addr += 0x7a; /* offset for flash magic */
124 + if ((addr[0] == 0x5a) && (addr[1] == 0xa5))
125 + return 1;
126 +
127 + return 0;
128 +}
129 +
130 +static inline bool
131 +check_board_data(u8 *flash_limit, u8 *addr, bool broken)
132 +{
133 + /* config magic found */
134 + if (*((u32 *)addr) == AR531X_BD_MAGIC)
135 + return 1;
136 +
137 + if (!broken)
138 + return 0;
139 +
140 + if (check_radio_magic(addr + 0xf8))
141 + ar231x_board.radio = addr + 0xf8;
142 + if ((addr < flash_limit + 0x10000) &&
143 + check_radio_magic(addr + 0x10000))
144 + ar231x_board.radio = addr + 0x10000;
145 +
146 + if (ar231x_board.radio) {
147 + /* broken board data detected, use radio data to find the
148 + * offset, user will fix this */
149 + return 1;
150 + }
151 + return 0;
152 +}
153 +
154 +static u8 *
155 +find_board_config(u8 *flash_limit, bool broken)
156 +{
157 + u8 *addr;
158 + int found = 0;
159 +
160 + for (addr = flash_limit - 0x1000;
161 + addr >= flash_limit - 0x30000;
162 + addr -= 0x1000) {
163 +
164 + if (check_board_data(flash_limit, addr, broken)) {
165 + found = 1;
166 + break;
167 + }
168 + }
169 +
170 + if (!found)
171 + addr = NULL;
172 +
173 + return addr;
174 +}
175 +
176 +static u8 *
177 +find_radio_config(u8 *flash_limit, u8 *board_config)
178 +{
179 + int found;
180 + u8 *radio_config;
181 +
182 + /*
183 + * Now find the start of Radio Configuration data, using heuristics:
184 + * Search forward from Board Configuration data by 0x1000 bytes
185 + * at a time until we find non-0xffffffff.
186 + */
187 + found = 0;
188 + for (radio_config = board_config + 0x1000;
189 + (radio_config < flash_limit);
190 + radio_config += 0x1000) {
191 + if ((*(u32 *)radio_config != 0xffffffff) &&
192 + check_radio_magic(radio_config)) {
193 + found = 1;
194 + break;
195 + }
196 + }
197 +
198 + /* AR2316 relocates radio config to new location */
199 + if (!found) {
200 + for (radio_config = board_config + 0xf8;
201 + (radio_config < flash_limit - 0x1000 + 0xf8);
202 + radio_config += 0x1000) {
203 + if ((*(u32 *)radio_config != 0xffffffff) &&
204 + check_radio_magic(radio_config)) {
205 + found = 1;
206 + break;
207 + }
208 + }
209 + }
210 +
211 + if (!found) {
212 + pr_warn("WARNING: Could not find Radio Configuration data\n");
213 + radio_config = 0;
214 + }
215 +
216 + return radio_config;
217 +}
218 +
219 +int __init
220 +ar231x_find_config(u8 *flash_limit)
221 +{
222 + struct ar231x_boarddata *config;
223 + unsigned int rcfg_size;
224 + int broken_boarddata = 0;
225 + u8 *bcfg, *rcfg;
226 + u8 *board_data;
227 + u8 *radio_data;
228 + u8 *mac_addr;
229 + u32 offset;
230 +
231 + ar231x_board.config = NULL;
232 + ar231x_board.radio = NULL;
233 + /* Copy the board and radio data to RAM, because accessing the mapped
234 + * memory of the flash directly after booting is not safe */
235 +
236 + /* Try to find valid board and radio data */
237 + bcfg = find_board_config(flash_limit, false);
238 +
239 + /* If that fails, try to at least find valid radio data */
240 + if (!bcfg) {
241 + bcfg = find_board_config(flash_limit, true);
242 + broken_boarddata = 1;
243 + }
244 +
245 + if (!bcfg) {
246 + pr_warn("WARNING: No board configuration data found!\n");
247 + return -ENODEV;
248 + }
249 +
250 + board_data = kzalloc(BOARD_CONFIG_BUFSZ, GFP_KERNEL);
251 + ar231x_board.config = (struct ar231x_boarddata *)board_data;
252 + memcpy(board_data, bcfg, 0x100);
253 + if (broken_boarddata) {
254 + pr_warn("WARNING: broken board data detected\n");
255 + config = ar231x_board.config;
256 + if (!memcmp(config->enet0_mac, "\x00\x00\x00\x00\x00\x00", 6)) {
257 + pr_info("Fixing up empty mac addresses\n");
258 + config->reset_config_gpio = 0xffff;
259 + config->sys_led_gpio = 0xffff;
260 + random_ether_addr(config->wlan0_mac);
261 + config->wlan0_mac[0] &= ~0x06;
262 + random_ether_addr(config->enet0_mac);
263 + random_ether_addr(config->enet1_mac);
264 + }
265 + }
266 +
267 +
268 + /* Radio config starts 0x100 bytes after board config, regardless
269 + * of what the physical layout on the flash chip looks like */
270 +
271 + if (ar231x_board.radio)
272 + rcfg = (u8 *)ar231x_board.radio;
273 + else
274 + rcfg = find_radio_config(flash_limit, bcfg);
275 +
276 + if (!rcfg)
277 + return -ENODEV;
278 +
279 + radio_data = board_data + 0x100 + ((rcfg - bcfg) & 0xfff);
280 + ar231x_board.radio = radio_data;
281 + offset = radio_data - board_data;
282 + pr_info("Radio config found at offset 0x%x (0x%x)\n", rcfg - bcfg,
283 + offset);
284 + rcfg_size = BOARD_CONFIG_BUFSZ - offset;
285 + memcpy(radio_data, rcfg, rcfg_size);
286 +
287 + mac_addr = &radio_data[0x1d * 2];
288 + if (is_broadcast_ether_addr(mac_addr)) {
289 + pr_info("Radio MAC is blank; using board-data\n");
290 + memcpy(mac_addr, ar231x_board.config->wlan0_mac, ETH_ALEN);
291 + }
292 +
293 + return 0;
294 +}
295 +
296 +static void
297 +ar231x_halt(void)
298 +{
299 + local_irq_disable();
300 + while (1)
301 + ;
302 +}
303 +
304 +void __init
305 +plat_mem_setup(void)
306 +{
307 + _machine_halt = ar231x_halt;
308 + pm_power_off = ar231x_halt;
309 +
310 + ar5312_plat_setup();
311 + ar2315_plat_setup();
312 +
313 + /* Disable data watchpoints */
314 + write_c0_watchlo0(0);
315 +}
316 +
317 +
318 +asmlinkage void
319 +plat_irq_dispatch(void)
320 +{
321 + ar231x_irq_dispatch();
322 +}
323 +
324 +void __init
325 +plat_time_init(void)
326 +{
327 + ar5312_time_init();
328 + ar2315_time_init();
329 +}
330 +
331 +unsigned int __cpuinit
332 +get_c0_compare_int(void)
333 +{
334 + return CP0_LEGACY_COMPARE_IRQ;
335 +}
336 +
337 +void __init
338 +arch_init_irq(void)
339 +{
340 + clear_c0_status(ST0_IM);
341 + mips_cpu_irq_init();
342 +
343 + /* Initialize interrupt controllers */
344 + ar5312_irq_init();
345 + ar2315_irq_init();
346 +}
347 +
348 +
349 --- /dev/null
350 +++ b/arch/mips/ar231x/prom.c
351 @@ -0,0 +1,37 @@
352 +/*
353 + * This file is subject to the terms and conditions of the GNU General Public
354 + * License. See the file "COPYING" in the main directory of this archive
355 + * for more details.
356 + *
357 + * Copyright MontaVista Software Inc
358 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
359 + * Copyright (C) 2006 FON Technology, SL.
360 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
361 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
362 + */
363 +
364 +/*
365 + * Prom setup file for ar531x
366 + */
367 +
368 +#include <linux/init.h>
369 +#include <generated/autoconf.h>
370 +#include <linux/kernel.h>
371 +#include <linux/string.h>
372 +#include <linux/mm.h>
373 +#include <linux/bootmem.h>
374 +
375 +#include <asm/bootinfo.h>
376 +#include <asm/addrspace.h>
377 +#include "ar5312.h"
378 +#include "ar2315.h"
379 +
380 +void __init prom_init(void)
381 +{
382 + ar5312_prom_init();
383 + ar2315_prom_init();
384 +}
385 +
386 +void __init prom_free_prom_memory(void)
387 +{
388 +}
389 --- /dev/null
390 +++ b/arch/mips/include/asm/mach-ar231x/ar231x_platform.h
391 @@ -0,0 +1,84 @@
392 +#ifndef __AR531X_PLATFORM_H
393 +#define __AR531X_PLATFORM_H
394 +
395 +/*
396 + * This is board-specific data that is stored in a "fixed" location in flash.
397 + * It is shared across operating systems, so it should not be changed lightly.
398 + * The main reason we need it is in order to extract the ethernet MAC
399 + * address(es).
400 + */
401 +struct ar231x_boarddata {
402 + u32 magic; /* board data is valid */
403 +#define AR531X_BD_MAGIC 0x35333131 /* "5311", for all 531x platforms */
404 + u16 cksum; /* checksum (starting with BD_REV 2) */
405 + u16 rev; /* revision of this struct */
406 +#define BD_REV 4
407 + char board_name[64]; /* Name of board */
408 + u16 major; /* Board major number */
409 + u16 minor; /* Board minor number */
410 + u32 flags; /* Board configuration */
411 +#define BD_ENET0 0x00000001 /* ENET0 is stuffed */
412 +#define BD_ENET1 0x00000002 /* ENET1 is stuffed */
413 +#define BD_UART1 0x00000004 /* UART1 is stuffed */
414 +#define BD_UART0 0x00000008 /* UART0 is stuffed (dma) */
415 +#define BD_RSTFACTORY 0x00000010 /* Reset factory defaults stuffed */
416 +#define BD_SYSLED 0x00000020 /* System LED stuffed */
417 +#define BD_EXTUARTCLK 0x00000040 /* External UART clock */
418 +#define BD_CPUFREQ 0x00000080 /* cpu freq is valid in nvram */
419 +#define BD_SYSFREQ 0x00000100 /* sys freq is set in nvram */
420 +#define BD_WLAN0 0x00000200 /* Enable WLAN0 */
421 +#define BD_MEMCAP 0x00000400 /* CAP SDRAM @ mem_cap for testing */
422 +#define BD_DISWATCHDOG 0x00000800 /* disable system watchdog */
423 +#define BD_WLAN1 0x00001000 /* Enable WLAN1 (ar5212) */
424 +#define BD_ISCASPER 0x00002000 /* FLAG for AR2312 */
425 +#define BD_WLAN0_2G_EN 0x00004000 /* FLAG for radio0_2G */
426 +#define BD_WLAN0_5G_EN 0x00008000 /* FLAG for radio0_2G */
427 +#define BD_WLAN1_2G_EN 0x00020000 /* FLAG for radio0_2G */
428 +#define BD_WLAN1_5G_EN 0x00040000 /* FLAG for radio0_2G */
429 + u16 reset_config_gpio; /* Reset factory GPIO pin */
430 + u16 sys_led_gpio; /* System LED GPIO pin */
431 +
432 + u32 cpu_freq; /* CPU core frequency in Hz */
433 + u32 sys_freq; /* System frequency in Hz */
434 + u32 cnt_freq; /* Calculated C0_COUNT frequency */
435 +
436 + u8 wlan0_mac[6];
437 + u8 enet0_mac[6];
438 + u8 enet1_mac[6];
439 +
440 + u16 pci_id; /* Pseudo PCIID for common code */
441 + u16 mem_cap; /* cap bank1 in MB */
442 +
443 + /* version 3 */
444 + u8 wlan1_mac[6]; /* (ar5212) */
445 +};
446 +
447 +#define BOARD_CONFIG_BUFSZ 0x1000
448 +
449 +/*
450 + * Platform device information for the Wireless MAC
451 + */
452 +struct ar231x_board_config {
453 + u16 devid;
454 +
455 + /* board config data */
456 + struct ar231x_boarddata *config;
457 +
458 + /* radio calibration data */
459 + const char *radio;
460 +};
461 +
462 +/*
463 + * Platform device information for the Ethernet MAC
464 + */
465 +struct ar231x_eth {
466 + void (*reset_set)(u32);
467 + void (*reset_clear)(u32);
468 + u32 reset_mac;
469 + u32 reset_phy;
470 + u32 phy_base;
471 + struct ar231x_board_config *config;
472 + char *macaddr;
473 +};
474 +
475 +#endif /* __AR531X_PLATFORM_H */
476 --- /dev/null
477 +++ b/arch/mips/include/asm/mach-ar231x/cpu-feature-overrides.h
478 @@ -0,0 +1,84 @@
479 +/*
480 + * Atheros SoC specific CPU feature overrides
481 + *
482 + * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
483 + *
484 + * This file was derived from: include/asm-mips/cpu-features.h
485 + * Copyright (C) 2003, 2004 Ralf Baechle
486 + * Copyright (C) 2004 Maciej W. Rozycki
487 + *
488 + * This program is free software; you can redistribute it and/or modify it
489 + * under the terms of the GNU General Public License version 2 as published
490 + * by the Free Software Foundation.
491 + *
492 + */
493 +#ifndef __ASM_MACH_ATHEROS_CPU_FEATURE_OVERRIDES_H
494 +#define __ASM_MACH_ATHEROS_CPU_FEATURE_OVERRIDES_H
495 +
496 +/*
497 + * The ATHEROS SoCs have MIPS 4Kc/4KEc core.
498 + */
499 +#define cpu_has_tlb 1
500 +#define cpu_has_4kex 1
501 +#define cpu_has_3k_cache 0
502 +#define cpu_has_4k_cache 1
503 +#define cpu_has_tx39_cache 0
504 +#define cpu_has_sb1_cache 0
505 +#define cpu_has_fpu 0
506 +#define cpu_has_32fpr 0
507 +#define cpu_has_counter 1
508 +/* #define cpu_has_watch ? */
509 +/* #define cpu_has_divec ? */
510 +/* #define cpu_has_vce ? */
511 +/* #define cpu_has_cache_cdex_p ? */
512 +/* #define cpu_has_cache_cdex_s ? */
513 +/* #define cpu_has_prefetch ? */
514 +/* #define cpu_has_mcheck ? */
515 +#define cpu_has_ejtag 1
516 +
517 +#if !defined(CONFIG_ATHEROS_AR5312)
518 +# define cpu_has_llsc 1
519 +#else
520 +/*
521 + * The MIPS 4Kc V0.9 core in the AR5312/AR2312 have problems with the
522 + * ll/sc instructions.
523 + */
524 +# define cpu_has_llsc 0
525 +#endif
526 +
527 +#define cpu_has_mips16 0
528 +#define cpu_has_mdmx 0
529 +#define cpu_has_mips3d 0
530 +#define cpu_has_smartmips 0
531 +
532 +/* #define cpu_has_vtag_icache ? */
533 +/* #define cpu_has_dc_aliases ? */
534 +/* #define cpu_has_ic_fills_f_dc ? */
535 +/* #define cpu_has_pindexed_dcache ? */
536 +
537 +/* #define cpu_icache_snoops_remote_store ? */
538 +
539 +#define cpu_has_mips32r1 1
540 +
541 +#if !defined(CONFIG_ATHEROS_AR5312)
542 +# define cpu_has_mips32r2 1
543 +#endif
544 +
545 +#define cpu_has_mips64r1 0
546 +#define cpu_has_mips64r2 0
547 +
548 +#define cpu_has_dsp 0
549 +#define cpu_has_mipsmt 0
550 +
551 +/* #define cpu_has_nofpuex ? */
552 +#define cpu_has_64bits 0
553 +#define cpu_has_64bit_zero_reg 0
554 +#define cpu_has_64bit_gp_regs 0
555 +#define cpu_has_64bit_addresses 0
556 +
557 +/* #define cpu_has_inclusive_pcaches ? */
558 +
559 +/* #define cpu_dcache_line_size() ? */
560 +/* #define cpu_icache_line_size() ? */
561 +
562 +#endif /* __ASM_MACH_ATHEROS_CPU_FEATURE_OVERRIDES_H */
563 --- /dev/null
564 +++ b/arch/mips/include/asm/mach-ar231x/dma-coherence.h
565 @@ -0,0 +1,79 @@
566 +/*
567 + * This file is subject to the terms and conditions of the GNU General Public
568 + * License. See the file "COPYING" in the main directory of this archive
569 + * for more details.
570 + *
571 + * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
572 + * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
573 + *
574 + */
575 +#ifndef __ASM_MACH_GENERIC_DMA_COHERENCE_H
576 +#define __ASM_MACH_GENERIC_DMA_COHERENCE_H
577 +
578 +#define PCI_DMA_OFFSET 0x20000000
579 +
580 +#include <linux/device.h>
581 +
582 +static inline dma_addr_t ar231x_dev_offset(struct device *dev)
583 +{
584 +#ifdef CONFIG_PCI
585 + extern struct bus_type pci_bus_type;
586 +
587 + if (dev && dev->bus == &pci_bus_type)
588 + return PCI_DMA_OFFSET;
589 + else
590 +#endif
591 + return 0;
592 +}
593 +
594 +static inline dma_addr_t
595 +plat_map_dma_mem(struct device *dev, void *addr, size_t size)
596 +{
597 + return virt_to_phys(addr) + ar231x_dev_offset(dev);
598 +}
599 +
600 +static inline dma_addr_t
601 +plat_map_dma_mem_page(struct device *dev, struct page *page)
602 +{
603 + return page_to_phys(page) + ar231x_dev_offset(dev);
604 +}
605 +
606 +static inline unsigned long
607 +plat_dma_addr_to_phys(struct device *dev, dma_addr_t dma_addr)
608 +{
609 + return dma_addr - ar231x_dev_offset(dev);
610 +}
611 +
612 +static inline void
613 +plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, size_t size,
614 + enum dma_data_direction direction)
615 +{
616 +}
617 +
618 +static inline int plat_dma_supported(struct device *dev, u64 mask)
619 +{
620 + return 1;
621 +}
622 +
623 +static inline void plat_extra_sync_for_device(struct device *dev)
624 +{
625 + return;
626 +}
627 +
628 +static inline int plat_dma_mapping_error(struct device *dev,
629 + dma_addr_t dma_addr)
630 +{
631 + return 0;
632 +}
633 +
634 +static inline int plat_device_is_coherent(struct device *dev)
635 +{
636 +#ifdef CONFIG_DMA_COHERENT
637 + return 1;
638 +#endif
639 +#ifdef CONFIG_DMA_NONCOHERENT
640 + return 0;
641 +#endif
642 +}
643 +
644 +#endif /* __ASM_MACH_GENERIC_DMA_COHERENCE_H */
645 --- /dev/null
646 +++ b/arch/mips/include/asm/mach-ar231x/gpio.h
647 @@ -0,0 +1,30 @@
648 +#ifndef _ATHEROS_GPIO_H_
649 +#define _ATHEROS_GPIO_H_
650 +
651 +#include <ar231x.h>
652 +
653 +#define gpio_get_value __gpio_get_value
654 +#define gpio_set_value __gpio_set_value
655 +#define gpio_cansleep __gpio_cansleep
656 +
657 +/*
658 + * Wrappers for the generic GPIO layer
659 + */
660 +
661 +/* not sure if these are used? */
662 +
663 +/* Returns IRQ to attach for gpio. Unchecked function */
664 +static inline int gpio_to_irq(unsigned gpio)
665 +{
666 + return AR531X_GPIO_IRQ(gpio);
667 +}
668 +
669 +/* Returns gpio for IRQ attached. Unchecked function */
670 +static inline int irq_to_gpio(unsigned irq)
671 +{
672 + return irq - AR531X_GPIO_IRQ(0);
673 +}
674 +
675 +#include <asm-generic/gpio.h> /* cansleep wrappers */
676 +
677 +#endif
678 --- /dev/null
679 +++ b/arch/mips/include/asm/mach-ar231x/reset.h
680 @@ -0,0 +1,6 @@
681 +#ifndef __AR531X_RESET_H
682 +#define __AR531X_RESET_H
683 +
684 +void ar531x_disable_reset_button(void);
685 +
686 +#endif /* __AR531X_RESET_H */
687 --- /dev/null
688 +++ b/arch/mips/include/asm/mach-ar231x/war.h
689 @@ -0,0 +1,25 @@
690 +/*
691 + * This file is subject to the terms and conditions of the GNU General Public
692 + * License. See the file "COPYING" in the main directory of this archive
693 + * for more details.
694 + *
695 + * Copyright (C) 2008 Felix Fietkau <nbd@openwrt.org>
696 + */
697 +#ifndef __ASM_MIPS_MACH_ATHEROS_WAR_H
698 +#define __ASM_MIPS_MACH_ATHEROS_WAR_H
699 +
700 +#define R4600_V1_INDEX_ICACHEOP_WAR 0
701 +#define R4600_V1_HIT_CACHEOP_WAR 0
702 +#define R4600_V2_HIT_CACHEOP_WAR 0
703 +#define R5432_CP0_INTERRUPT_WAR 0
704 +#define BCM1250_M3_WAR 0
705 +#define SIBYTE_1956_WAR 0
706 +#define MIPS4K_ICACHE_REFILL_WAR 0
707 +#define MIPS_CACHE_SYNC_WAR 0
708 +#define TX49XX_ICACHE_INDEX_INV_WAR 0
709 +#define RM9000_CDEX_SMP_WAR 0
710 +#define ICACHE_REFILLS_WORKAROUND_WAR 0
711 +#define R10000_LLSC_WAR 0
712 +#define MIPS34K_MISSED_ITLB_WAR 0
713 +
714 +#endif /* __ASM_MIPS_MACH_ATHEROS_WAR_H */
715 --- /dev/null
716 +++ b/arch/mips/include/asm/mach-ar231x/ar2315_regs.h
717 @@ -0,0 +1,597 @@
718 +/*
719 + * Register definitions for AR2315+
720 + *
721 + * This file is subject to the terms and conditions of the GNU General Public
722 + * License. See the file "COPYING" in the main directory of this archive
723 + * for more details.
724 + *
725 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
726 + * Copyright (C) 2006 FON Technology, SL.
727 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
728 + * Copyright (C) 2006-2008 Felix Fietkau <nbd@openwrt.org>
729 + */
730 +
731 +#ifndef __AR2315_REG_H
732 +#define __AR2315_REG_H
733 +
734 +/*
735 + * IRQs
736 + */
737 +#define AR2315_IRQ_MISC_INTRS (MIPS_CPU_IRQ_BASE+2) /* C0_CAUSE: 0x0400 */
738 +#define AR2315_IRQ_WLAN0_INTRS (MIPS_CPU_IRQ_BASE+3) /* C0_CAUSE: 0x0800 */
739 +#define AR2315_IRQ_ENET0_INTRS (MIPS_CPU_IRQ_BASE+4) /* C0_CAUSE: 0x1000 */
740 +#define AR2315_IRQ_LCBUS_PCI (MIPS_CPU_IRQ_BASE+5) /* C0_CAUSE: 0x2000 */
741 +#define AR2315_IRQ_WLAN0_POLL (MIPS_CPU_IRQ_BASE+6) /* C0_CAUSE: 0x4000 */
742 +
743 +/*
744 + * Address map
745 + */
746 +#define AR2315_SPI_READ 0x08000000 /* SPI FLASH */
747 +#define AR2315_WLAN0 0x10000000 /* Wireless MMR */
748 +#define AR2315_PCI 0x10100000 /* PCI MMR */
749 +#define AR2315_SDRAMCTL 0x10300000 /* SDRAM MMR */
750 +#define AR2315_LOCAL 0x10400000 /* LOCAL BUS MMR */
751 +#define AR2315_ENET0 0x10500000 /* ETHERNET MMR */
752 +#define AR2315_DSLBASE 0x11000000 /* RESET CONTROL MMR */
753 +#define AR2315_UART0 0x11100003 /* UART MMR */
754 +#define AR2315_SPI_MMR 0x11300000 /* SPI FLASH MMR */
755 +#define AR2315_PCIEXT 0x80000000 /* pci external */
756 +
757 +/*
758 + * Reset Register
759 + */
760 +#define AR2315_COLD_RESET (AR2315_DSLBASE + 0x0000)
761 +
762 +#define AR2315_RESET_COLD_AHB 0x00000001
763 +#define AR2315_RESET_COLD_APB 0x00000002
764 +#define AR2315_RESET_COLD_CPU 0x00000004
765 +#define AR2315_RESET_COLD_CPUWARM 0x00000008
766 +#define AR2315_RESET_SYSTEM \
767 + (RESET_COLD_CPU |\
768 + RESET_COLD_APB |\
769 + RESET_COLD_AHB) /* full system */
770 +#define AR2317_RESET_SYSTEM 0x00000010
771 +
772 +
773 +#define AR2315_RESET (AR2315_DSLBASE + 0x0004)
774 +
775 +/* warm reset WLAN0 MAC */
776 +#define AR2315_RESET_WARM_WLAN0_MAC 0x00000001
777 +/* warm reset WLAN0 BaseBand */
778 +#define AR2315_RESET_WARM_WLAN0_BB 0x00000002
779 +/* warm reset MPEG-TS */
780 +#define AR2315_RESET_MPEGTS_RSVD 0x00000004
781 +/* warm reset PCI ahb/dma */
782 +#define AR2315_RESET_PCIDMA 0x00000008
783 +/* warm reset memory controller */
784 +#define AR2315_RESET_MEMCTL 0x00000010
785 +/* warm reset local bus */
786 +#define AR2315_RESET_LOCAL 0x00000020
787 +/* warm reset I2C bus */
788 +#define AR2315_RESET_I2C_RSVD 0x00000040
789 +/* warm reset SPI interface */
790 +#define AR2315_RESET_SPI 0x00000080
791 +/* warm reset UART0 */
792 +#define AR2315_RESET_UART0 0x00000100
793 +/* warm reset IR interface */
794 +#define AR2315_RESET_IR_RSVD 0x00000200
795 +/* cold reset ENET0 phy */
796 +#define AR2315_RESET_EPHY0 0x00000400
797 +/* cold reset ENET0 mac */
798 +#define AR2315_RESET_ENET0 0x00000800
799 +
800 +/*
801 + * AHB master arbitration control
802 + */
803 +#define AR2315_AHB_ARB_CTL (AR2315_DSLBASE + 0x0008)
804 +
805 +/* CPU, default */
806 +#define AR2315_ARB_CPU 0x00000001
807 +/* WLAN */
808 +#define AR2315_ARB_WLAN 0x00000002
809 +/* MPEG-TS */
810 +#define AR2315_ARB_MPEGTS_RSVD 0x00000004
811 +/* LOCAL */
812 +#define AR2315_ARB_LOCAL 0x00000008
813 +/* PCI */
814 +#define AR2315_ARB_PCI 0x00000010
815 +/* Ethernet */
816 +#define AR2315_ARB_ETHERNET 0x00000020
817 +/* retry policy, debug only */
818 +#define AR2315_ARB_RETRY 0x00000100
819 +
820 +/*
821 + * Config Register
822 + */
823 +#define AR2315_ENDIAN_CTL (AR2315_DSLBASE + 0x000c)
824 +
825 +/* EC - AHB bridge endianess */
826 +#define AR2315_CONFIG_AHB 0x00000001
827 +/* WLAN byteswap */
828 +#define AR2315_CONFIG_WLAN 0x00000002
829 +/* MPEG-TS byteswap */
830 +#define AR2315_CONFIG_MPEGTS_RSVD 0x00000004
831 +/* PCI byteswap */
832 +#define AR2315_CONFIG_PCI 0x00000008
833 +/* Memory controller endianess */
834 +#define AR2315_CONFIG_MEMCTL 0x00000010
835 +/* Local bus byteswap */
836 +#define AR2315_CONFIG_LOCAL 0x00000020
837 +/* Ethernet byteswap */
838 +#define AR2315_CONFIG_ETHERNET 0x00000040
839 +
840 +/* CPU write buffer merge */
841 +#define AR2315_CONFIG_MERGE 0x00000200
842 +/* CPU big endian */
843 +#define AR2315_CONFIG_CPU 0x00000400
844 +#define AR2315_CONFIG_PCIAHB 0x00000800
845 +#define AR2315_CONFIG_PCIAHB_BRIDGE 0x00001000
846 +/* SPI byteswap */
847 +#define AR2315_CONFIG_SPI 0x00008000
848 +#define AR2315_CONFIG_CPU_DRAM 0x00010000
849 +#define AR2315_CONFIG_CPU_PCI 0x00020000
850 +#define AR2315_CONFIG_CPU_MMR 0x00040000
851 +#define AR2315_CONFIG_BIG 0x00000400
852 +
853 +
854 +/*
855 + * NMI control
856 + */
857 +#define AR2315_NMI_CTL (AR2315_DSLBASE + 0x0010)
858 +
859 +#define AR2315_NMI_EN 1
860 +
861 +/*
862 + * Revision Register - Initial value is 0x3010 (WMAC 3.0, AR531X 1.0).
863 + */
864 +#define AR2315_SREV (AR2315_DSLBASE + 0x0014)
865 +
866 +#define AR2315_REV_MAJ 0x00f0
867 +#define AR2315_REV_MAJ_S 4
868 +#define AR2315_REV_MIN 0x000f
869 +#define AR2315_REV_MIN_S 0
870 +#define AR2315_REV_CHIP (AR2315_REV_MAJ|AR2315_REV_MIN)
871 +
872 +/*
873 + * Interface Enable
874 + */
875 +#define AR2315_IF_CTL (AR2315_DSLBASE + 0x0018)
876 +
877 +#define AR2315_IF_MASK 0x00000007
878 +#define AR2315_IF_DISABLED 0
879 +#define AR2315_IF_PCI 1
880 +#define AR2315_IF_TS_LOCAL 2
881 +/* only for emulation with separate pins */
882 +#define AR2315_IF_ALL 3
883 +#define AR2315_IF_LOCAL_HOST 0x00000008
884 +#define AR2315_IF_PCI_HOST 0x00000010
885 +#define AR2315_IF_PCI_INTR 0x00000020
886 +#define AR2315_IF_PCI_CLK_MASK 0x00030000
887 +#define AR2315_IF_PCI_CLK_INPUT 0
888 +#define AR2315_IF_PCI_CLK_OUTPUT_LOW 1
889 +#define AR2315_IF_PCI_CLK_OUTPUT_CLK 2
890 +#define AR2315_IF_PCI_CLK_OUTPUT_HIGH 3
891 +#define AR2315_IF_PCI_CLK_SHIFT 16
892 +
893 +/*
894 + * APB Interrupt control
895 + */
896 +
897 +#define AR2315_ISR (AR2315_DSLBASE + 0x0020)
898 +#define AR2315_IMR (AR2315_DSLBASE + 0x0024)
899 +#define AR2315_GISR (AR2315_DSLBASE + 0x0028)
900 +
901 +#define AR2315_ISR_UART0 0x0001 /* high speed UART */
902 +#define AR2315_ISR_I2C_RSVD 0x0002 /* I2C bus */
903 +#define AR2315_ISR_SPI 0x0004 /* SPI bus */
904 +#define AR2315_ISR_AHB 0x0008 /* AHB error */
905 +#define AR2315_ISR_APB 0x0010 /* APB error */
906 +#define AR2315_ISR_TIMER 0x0020 /* timer */
907 +#define AR2315_ISR_GPIO 0x0040 /* GPIO */
908 +#define AR2315_ISR_WD 0x0080 /* watchdog */
909 +#define AR2315_ISR_IR_RSVD 0x0100 /* IR */
910 +
911 +#define AR2315_GISR_MISC 0x0001
912 +#define AR2315_GISR_WLAN0 0x0002
913 +#define AR2315_GISR_MPEGTS_RSVD 0x0004
914 +#define AR2315_GISR_LOCALPCI 0x0008
915 +#define AR2315_GISR_WMACPOLL 0x0010
916 +#define AR2315_GISR_TIMER 0x0020
917 +#define AR2315_GISR_ETHERNET 0x0040
918 +
919 +/*
920 + * Interrupt routing from IO to the processor IP bits
921 + * Define our inter mask and level
922 + */
923 +#define AR2315_INTR_MISCIO SR_IBIT3
924 +#define AR2315_INTR_WLAN0 SR_IBIT4
925 +#define AR2315_INTR_ENET0 SR_IBIT5
926 +#define AR2315_INTR_LOCALPCI SR_IBIT6
927 +#define AR2315_INTR_WMACPOLL SR_IBIT7
928 +#define AR2315_INTR_COMPARE SR_IBIT8
929 +
930 +/*
931 + * Timers
932 + */
933 +#define AR2315_TIMER (AR2315_DSLBASE + 0x0030)
934 +#define AR2315_RELOAD (AR2315_DSLBASE + 0x0034)
935 +#define AR2315_WD (AR2315_DSLBASE + 0x0038)
936 +#define AR2315_WDC (AR2315_DSLBASE + 0x003c)
937 +
938 +#define AR2315_WDC_IGNORE_EXPIRATION 0x00000000
939 +#define AR2315_WDC_NMI 0x00000001 /* NMI on watchdog */
940 +#define AR2315_WDC_RESET 0x00000002 /* reset on watchdog */
941 +
942 +/*
943 + * CPU Performance Counters
944 + */
945 +#define AR2315_PERFCNT0 (AR2315_DSLBASE + 0x0048)
946 +#define AR2315_PERFCNT1 (AR2315_DSLBASE + 0x004c)
947 +
948 +#define AR2315_PERF0_DATAHIT 0x0001 /* Count Data Cache Hits */
949 +#define AR2315_PERF0_DATAMISS 0x0002 /* Count Data Cache Misses */
950 +#define AR2315_PERF0_INSTHIT 0x0004 /* Count Instruction Cache Hits */
951 +#define AR2315_PERF0_INSTMISS 0x0008 /* Count Instruction Cache Misses */
952 +#define AR2315_PERF0_ACTIVE 0x0010 /* Count Active Processor Cycles */
953 +#define AR2315_PERF0_WBHIT 0x0020 /* Count CPU Write Buffer Hits */
954 +#define AR2315_PERF0_WBMISS 0x0040 /* Count CPU Write Buffer Misses */
955 +
956 +#define AR2315_PERF1_EB_ARDY 0x0001 /* Count EB_ARdy signal */
957 +#define AR2315_PERF1_EB_AVALID 0x0002 /* Count EB_AValid signal */
958 +#define AR2315_PERF1_EB_WDRDY 0x0004 /* Count EB_WDRdy signal */
959 +#define AR2315_PERF1_EB_RDVAL 0x0008 /* Count EB_RdVal signal */
960 +#define AR2315_PERF1_VRADDR 0x0010 /* Count valid read address cycles */
961 +#define AR2315_PERF1_VWADDR 0x0020 /* Count valid write address cycles */
962 +#define AR2315_PERF1_VWDATA 0x0040 /* Count valid write data cycles */
963 +
964 +/*
965 + * AHB Error Reporting.
966 + */
967 +#define AR2315_AHB_ERR0 (AR2315_DSLBASE + 0x0050) /* error */
968 +#define AR2315_AHB_ERR1 (AR2315_DSLBASE + 0x0054) /* haddr */
969 +#define AR2315_AHB_ERR2 (AR2315_DSLBASE + 0x0058) /* hwdata */
970 +#define AR2315_AHB_ERR3 (AR2315_DSLBASE + 0x005c) /* hrdata */
971 +#define AR2315_AHB_ERR4 (AR2315_DSLBASE + 0x0060) /* status */
972 +
973 +#define AHB_ERROR_DET 1 /* AHB Error has been detected, */
974 + /* write 1 to clear all bits in ERR0 */
975 +#define AHB_ERROR_OVR 2 /* AHB Error overflow has been detected */
976 +#define AHB_ERROR_WDT 4 /* AHB Error due to wdt instead of hresp */
977 +
978 +#define AR2315_PROCERR_HMAST 0x0000000f
979 +#define AR2315_PROCERR_HMAST_DFLT 0
980 +#define AR2315_PROCERR_HMAST_WMAC 1
981 +#define AR2315_PROCERR_HMAST_ENET 2
982 +#define AR2315_PROCERR_HMAST_PCIENDPT 3
983 +#define AR2315_PROCERR_HMAST_LOCAL 4
984 +#define AR2315_PROCERR_HMAST_CPU 5
985 +#define AR2315_PROCERR_HMAST_PCITGT 6
986 +
987 +#define AR2315_PROCERR_HMAST_S 0
988 +#define AR2315_PROCERR_HWRITE 0x00000010
989 +#define AR2315_PROCERR_HSIZE 0x00000060
990 +#define AR2315_PROCERR_HSIZE_S 5
991 +#define AR2315_PROCERR_HTRANS 0x00000180
992 +#define AR2315_PROCERR_HTRANS_S 7
993 +#define AR2315_PROCERR_HBURST 0x00000e00
994 +#define AR2315_PROCERR_HBURST_S 9
995 +
996 +/*
997 + * Clock Control
998 + */
999 +#define AR2315_PLLC_CTL (AR2315_DSLBASE + 0x0064)
1000 +#define AR2315_PLLV_CTL (AR2315_DSLBASE + 0x0068)
1001 +#define AR2315_CPUCLK (AR2315_DSLBASE + 0x006c)
1002 +#define AR2315_AMBACLK (AR2315_DSLBASE + 0x0070)
1003 +#define AR2315_SYNCCLK (AR2315_DSLBASE + 0x0074)
1004 +#define AR2315_DSL_SLEEP_CTL (AR2315_DSLBASE + 0x0080)
1005 +#define AR2315_DSL_SLEEP_DUR (AR2315_DSLBASE + 0x0084)
1006 +
1007 +/* PLLc Control fields */
1008 +#define PLLC_REF_DIV_M 0x00000003
1009 +#define PLLC_REF_DIV_S 0
1010 +#define PLLC_FDBACK_DIV_M 0x0000007C
1011 +#define PLLC_FDBACK_DIV_S 2
1012 +#define PLLC_ADD_FDBACK_DIV_M 0x00000080
1013 +#define PLLC_ADD_FDBACK_DIV_S 7
1014 +#define PLLC_CLKC_DIV_M 0x0001c000
1015 +#define PLLC_CLKC_DIV_S 14
1016 +#define PLLC_CLKM_DIV_M 0x00700000
1017 +#define PLLC_CLKM_DIV_S 20
1018 +
1019 +/* CPU CLK Control fields */
1020 +#define CPUCLK_CLK_SEL_M 0x00000003
1021 +#define CPUCLK_CLK_SEL_S 0
1022 +#define CPUCLK_CLK_DIV_M 0x0000000c
1023 +#define CPUCLK_CLK_DIV_S 2
1024 +
1025 +/* AMBA CLK Control fields */
1026 +#define AMBACLK_CLK_SEL_M 0x00000003
1027 +#define AMBACLK_CLK_SEL_S 0
1028 +#define AMBACLK_CLK_DIV_M 0x0000000c
1029 +#define AMBACLK_CLK_DIV_S 2
1030 +
1031 +/*
1032 + * GPIO
1033 + */
1034 +#define AR2315_GPIO_DI (AR2315_DSLBASE + 0x0088)
1035 +#define AR2315_GPIO_DO (AR2315_DSLBASE + 0x0090)
1036 +#define AR2315_GPIO_CR (AR2315_DSLBASE + 0x0098)
1037 +#define AR2315_GPIO_INT (AR2315_DSLBASE + 0x00a0)
1038 +
1039 +#define AR2315_GPIO_CR_M(x) (1 << (x)) /* mask for i/o */
1040 +#define AR2315_GPIO_CR_O(x) (1 << (x)) /* output */
1041 +#define AR2315_GPIO_CR_I(x) (0) /* input */
1042 +
1043 +#define AR2315_GPIO_INT_S(x) (x) /* interrupt enable */
1044 +#define AR2315_GPIO_INT_M (0x3F) /* mask for int */
1045 +#define AR2315_GPIO_INT_LVL(x) ((x) << 6) /* interrupt level */
1046 +#define AR2315_GPIO_INT_LVL_M ((0x3) << 6) /* mask for int level */
1047 +
1048 +#define AR2315_GPIO_INT_MAX_Y 1 /* Maximum value of Y for
1049 + * AR5313_GPIO_INT_* macros */
1050 +#define AR2315_GPIO_INT_LVL_OFF 0 /* Triggerring off */
1051 +#define AR2315_GPIO_INT_LVL_LOW 1 /* Low Level Triggered */
1052 +#define AR2315_GPIO_INT_LVL_HIGH 2 /* High Level Triggered */
1053 +#define AR2315_GPIO_INT_LVL_EDGE 3 /* Edge Triggered */
1054 +
1055 +#define AR2315_RESET_GPIO 5
1056 +#define AR2315_NUM_GPIO 22
1057 +
1058 +/*
1059 + * PCI Clock Control
1060 + */
1061 +#define AR2315_PCICLK (AR2315_DSLBASE + 0x00a4)
1062 +
1063 +#define AR2315_PCICLK_INPUT_M 0x3
1064 +#define AR2315_PCICLK_INPUT_S 0
1065 +
1066 +#define AR2315_PCICLK_PLLC_CLKM 0
1067 +#define AR2315_PCICLK_PLLC_CLKM1 1
1068 +#define AR2315_PCICLK_PLLC_CLKC 2
1069 +#define AR2315_PCICLK_REF_CLK 3
1070 +
1071 +#define AR2315_PCICLK_DIV_M 0xc
1072 +#define AR2315_PCICLK_DIV_S 2
1073 +
1074 +#define AR2315_PCICLK_IN_FREQ 0
1075 +#define AR2315_PCICLK_IN_FREQ_DIV_6 1
1076 +#define AR2315_PCICLK_IN_FREQ_DIV_8 2
1077 +#define AR2315_PCICLK_IN_FREQ_DIV_10 3
1078 +
1079 +/*
1080 + * Observation Control Register
1081 + */
1082 +#define AR2315_OCR (AR2315_DSLBASE + 0x00b0)
1083 +#define OCR_GPIO0_IRIN 0x0040
1084 +#define OCR_GPIO1_IROUT 0x0080
1085 +#define OCR_GPIO3_RXCLR 0x0200
1086 +
1087 +/*
1088 + * General Clock Control
1089 + */
1090 +
1091 +#define AR2315_MISCCLK (AR2315_DSLBASE + 0x00b4)
1092 +#define MISCCLK_PLLBYPASS_EN 0x00000001
1093 +#define MISCCLK_PROCREFCLK 0x00000002
1094 +
1095 +/*
1096 + * SDRAM Controller
1097 + * - No read or write buffers are included.
1098 + */
1099 +#define AR2315_MEM_CFG (AR2315_SDRAMCTL + 0x00)
1100 +#define AR2315_MEM_CTRL (AR2315_SDRAMCTL + 0x0c)
1101 +#define AR2315_MEM_REF (AR2315_SDRAMCTL + 0x10)
1102 +
1103 +#define SDRAM_DATA_WIDTH_M 0x00006000
1104 +#define SDRAM_DATA_WIDTH_S 13
1105 +
1106 +#define SDRAM_COL_WIDTH_M 0x00001E00
1107 +#define SDRAM_COL_WIDTH_S 9
1108 +
1109 +#define SDRAM_ROW_WIDTH_M 0x000001E0
1110 +#define SDRAM_ROW_WIDTH_S 5
1111 +
1112 +#define SDRAM_BANKADDR_BITS_M 0x00000018
1113 +#define SDRAM_BANKADDR_BITS_S 3
1114 +
1115 +/*
1116 + * PCI Bus Interface Registers
1117 + */
1118 +#define AR2315_PCI_1MS_REG (AR2315_PCI + 0x0008)
1119 +#define AR2315_PCI_1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
1120 +
1121 +#define AR2315_PCI_MISC_CONFIG (AR2315_PCI + 0x000c)
1122 +#define AR2315_PCIMISC_TXD_EN 0x00000001 /* Enable TXD for fragments */
1123 +#define AR2315_PCIMISC_CFG_SEL 0x00000002 /* mem or config cycles */
1124 +#define AR2315_PCIMISC_GIG_MASK 0x0000000C /* bits 31-30 for pci req */
1125 +#define AR2315_PCIMISC_RST_MODE 0x00000030
1126 +#define AR2315_PCIRST_INPUT 0x00000000 /* 4:5=0 rst is input */
1127 +#define AR2315_PCIRST_LOW 0x00000010 /* 4:5=1 rst to GND */
1128 +#define AR2315_PCIRST_HIGH 0x00000020 /* 4:5=2 rst to VDD */
1129 +#define AR2315_PCIGRANT_EN 0x00000000 /* 6:7=0 early grant en */
1130 +#define AR2315_PCIGRANT_FRAME 0x00000040 /* 6:7=1 grant waits 4 frame */
1131 +#define AR2315_PCIGRANT_IDLE 0x00000080 /* 6:7=2 grant waits 4 idle */
1132 +#define AR2315_PCIGRANT_GAP 0x00000000 /* 6:7=2 grant waits 4 idle */
1133 +#define AR2315_PCICACHE_DIS 0x00001000 /* PCI external access cache
1134 + * disable */
1135 +
1136 +#define AR2315_PCI_OUT_TSTAMP (AR2315_PCI + 0x0010)
1137 +
1138 +#define AR2315_PCI_UNCACHE_CFG (AR2315_PCI + 0x0014)
1139 +
1140 +#define AR2315_PCI_IN_EN (AR2315_PCI + 0x0100)
1141 +#define AR2315_PCI_IN_EN0 0x01 /* Enable chain 0 */
1142 +#define AR2315_PCI_IN_EN1 0x02 /* Enable chain 1 */
1143 +#define AR2315_PCI_IN_EN2 0x04 /* Enable chain 2 */
1144 +#define AR2315_PCI_IN_EN3 0x08 /* Enable chain 3 */
1145 +
1146 +#define AR2315_PCI_IN_DIS (AR2315_PCI + 0x0104)
1147 +#define AR2315_PCI_IN_DIS0 0x01 /* Disable chain 0 */
1148 +#define AR2315_PCI_IN_DIS1 0x02 /* Disable chain 1 */
1149 +#define AR2315_PCI_IN_DIS2 0x04 /* Disable chain 2 */
1150 +#define AR2315_PCI_IN_DIS3 0x08 /* Disable chain 3 */
1151 +
1152 +#define AR2315_PCI_IN_PTR (AR2315_PCI + 0x0200)
1153 +
1154 +#define AR2315_PCI_OUT_EN (AR2315_PCI + 0x0400)
1155 +#define AR2315_PCI_OUT_EN0 0x01 /* Enable chain 0 */
1156 +
1157 +#define AR2315_PCI_OUT_DIS (AR2315_PCI + 0x0404)
1158 +#define AR2315_PCI_OUT_DIS0 0x01 /* Disable chain 0 */
1159 +
1160 +#define AR2315_PCI_OUT_PTR (AR2315_PCI + 0x0408)
1161 +
1162 +#define AR2315_PCI_INT_STATUS (AR2315_PCI + 0x0500) /* write one to clr */
1163 +#define AR2315_PCI_TXINT 0x00000001 /* Desc In Completed */
1164 +#define AR2315_PCI_TXOK 0x00000002 /* Desc In OK */
1165 +#define AR2315_PCI_TXERR 0x00000004 /* Desc In ERR */
1166 +#define AR2315_PCI_TXEOL 0x00000008 /* Desc In End-of-List */
1167 +#define AR2315_PCI_RXINT 0x00000010 /* Desc Out Completed */
1168 +#define AR2315_PCI_RXOK 0x00000020 /* Desc Out OK */
1169 +#define AR2315_PCI_RXERR 0x00000040 /* Desc Out ERR */
1170 +#define AR2315_PCI_RXEOL 0x00000080 /* Desc Out EOL */
1171 +#define AR2315_PCI_TXOOD 0x00000200 /* Desc In Out-of-Desc */
1172 +#define AR2315_PCI_MASK 0x0000FFFF /* Desc Mask */
1173 +#define AR2315_PCI_EXT_INT 0x02000000
1174 +#define AR2315_PCI_ABORT_INT 0x04000000
1175 +
1176 +#define AR2315_PCI_INT_MASK (AR2315_PCI + 0x0504) /* same as INT_STATUS */
1177 +
1178 +#define AR2315_PCI_INTEN_REG (AR2315_PCI + 0x0508)
1179 +#define AR2315_PCI_INT_DISABLE 0x00 /* disable pci interrupts */
1180 +#define AR2315_PCI_INT_ENABLE 0x01 /* enable pci interrupts */
1181 +
1182 +#define AR2315_PCI_HOST_IN_EN (AR2315_PCI + 0x0800)
1183 +#define AR2315_PCI_HOST_IN_DIS (AR2315_PCI + 0x0804)
1184 +#define AR2315_PCI_HOST_IN_PTR (AR2315_PCI + 0x0810)
1185 +#define AR2315_PCI_HOST_OUT_EN (AR2315_PCI + 0x0900)
1186 +#define AR2315_PCI_HOST_OUT_DIS (AR2315_PCI + 0x0904)
1187 +#define AR2315_PCI_HOST_OUT_PTR (AR2315_PCI + 0x0908)
1188 +
1189 +
1190 +/*
1191 + * Local Bus Interface Registers
1192 + */
1193 +#define AR2315_LB_CONFIG (AR2315_LOCAL + 0x0000)
1194 +#define AR2315_LBCONF_OE 0x00000001 /* =1 OE is low-true */
1195 +#define AR2315_LBCONF_CS0 0x00000002 /* =1 first CS is low-true */
1196 +#define AR2315_LBCONF_CS1 0x00000004 /* =1 2nd CS is low-true */
1197 +#define AR2315_LBCONF_RDY 0x00000008 /* =1 RDY is low-true */
1198 +#define AR2315_LBCONF_WE 0x00000010 /* =1 Write En is low-true */
1199 +#define AR2315_LBCONF_WAIT 0x00000020 /* =1 WAIT is low-true */
1200 +#define AR2315_LBCONF_ADS 0x00000040 /* =1 Adr Strobe is low-true */
1201 +#define AR2315_LBCONF_MOT 0x00000080 /* =0 Intel, =1 Motorola */
1202 +#define AR2315_LBCONF_8CS 0x00000100 /* =1 8 bits CS, 0= 16bits */
1203 +#define AR2315_LBCONF_8DS 0x00000200 /* =1 8 bits Data S, 0=16bits */
1204 +#define AR2315_LBCONF_ADS_EN 0x00000400 /* =1 Enable ADS */
1205 +#define AR2315_LBCONF_ADR_OE 0x00000800 /* =1 Adr cap on OE, WE or DS */
1206 +#define AR2315_LBCONF_ADDT_MUX 0x00001000 /* =1 Adr and Data share bus */
1207 +#define AR2315_LBCONF_DATA_OE 0x00002000 /* =1 Data cap on OE, WE, DS */
1208 +#define AR2315_LBCONF_16DATA 0x00004000 /* =1 Data is 16 bits wide */
1209 +#define AR2315_LBCONF_SWAPDT 0x00008000 /* =1 Byte swap data */
1210 +#define AR2315_LBCONF_SYNC 0x00010000 /* =1 Bus synchronous to clk */
1211 +#define AR2315_LBCONF_INT 0x00020000 /* =1 Intr is low true */
1212 +#define AR2315_LBCONF_INT_CTR0 0x00000000 /* GND high-Z, Vdd is high-Z */
1213 +#define AR2315_LBCONF_INT_CTR1 0x00040000 /* GND drive, Vdd is high-Z */
1214 +#define AR2315_LBCONF_INT_CTR2 0x00080000 /* GND high-Z, Vdd drive */
1215 +#define AR2315_LBCONF_INT_CTR3 0x000C0000 /* GND drive, Vdd drive */
1216 +#define AR2315_LBCONF_RDY_WAIT 0x00100000 /* =1 RDY is negative of WAIT */
1217 +#define AR2315_LBCONF_INT_PULSE 0x00200000 /* =1 Interrupt is a pulse */
1218 +#define AR2315_LBCONF_ENABLE 0x00400000 /* =1 Falcon respond to LB */
1219 +
1220 +#define AR2315_LB_CLKSEL (AR2315_LOCAL + 0x0004)
1221 +#define AR2315_LBCLK_EXT 0x0001 /* use external clk for lb */
1222 +
1223 +#define AR2315_LB_1MS (AR2315_LOCAL + 0x0008)
1224 +#define AR2315_LB1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
1225 +
1226 +#define AR2315_LB_MISCCFG (AR2315_LOCAL + 0x000C)
1227 +#define AR2315_LBM_TXD_EN 0x00000001 /* Enable TXD for fragments */
1228 +#define AR2315_LBM_RX_INTEN 0x00000002 /* Enable LB ints on RX ready */
1229 +#define AR2315_LBM_MBOXWR_INTEN 0x00000004 /* Enable LB ints on mbox wr */
1230 +#define AR2315_LBM_MBOXRD_INTEN 0x00000008 /* Enable LB ints on mbox rd */
1231 +#define AR2315_LMB_DESCSWAP_EN 0x00000010 /* Byte swap desc enable */
1232 +#define AR2315_LBM_TIMEOUT_MASK 0x00FFFF80
1233 +#define AR2315_LBM_TIMEOUT_SHFT 7
1234 +#define AR2315_LBM_PORTMUX 0x07000000
1235 +
1236 +
1237 +#define AR2315_LB_RXTSOFF (AR2315_LOCAL + 0x0010)
1238 +
1239 +#define AR2315_LB_TX_CHAIN_EN (AR2315_LOCAL + 0x0100)
1240 +#define AR2315_LB_TXEN_0 0x01
1241 +#define AR2315_LB_TXEN_1 0x02
1242 +#define AR2315_LB_TXEN_2 0x04
1243 +#define AR2315_LB_TXEN_3 0x08
1244 +
1245 +#define AR2315_LB_TX_CHAIN_DIS (AR2315_LOCAL + 0x0104)
1246 +#define AR2315_LB_TX_DESC_PTR (AR2315_LOCAL + 0x0200)
1247 +
1248 +#define AR2315_LB_RX_CHAIN_EN (AR2315_LOCAL + 0x0400)
1249 +#define AR2315_LB_RXEN 0x01
1250 +
1251 +#define AR2315_LB_RX_CHAIN_DIS (AR2315_LOCAL + 0x0404)
1252 +#define AR2315_LB_RX_DESC_PTR (AR2315_LOCAL + 0x0408)
1253 +
1254 +#define AR2315_LB_INT_STATUS (AR2315_LOCAL + 0x0500)
1255 +#define AR2315_INT_TX_DESC 0x0001
1256 +#define AR2315_INT_TX_OK 0x0002
1257 +#define AR2315_INT_TX_ERR 0x0004
1258 +#define AR2315_INT_TX_EOF 0x0008
1259 +#define AR2315_INT_RX_DESC 0x0010
1260 +#define AR2315_INT_RX_OK 0x0020
1261 +#define AR2315_INT_RX_ERR 0x0040
1262 +#define AR2315_INT_RX_EOF 0x0080
1263 +#define AR2315_INT_TX_TRUNC 0x0100
1264 +#define AR2315_INT_TX_STARVE 0x0200
1265 +#define AR2315_INT_LB_TIMEOUT 0x0400
1266 +#define AR2315_INT_LB_ERR 0x0800
1267 +#define AR2315_INT_MBOX_WR 0x1000
1268 +#define AR2315_INT_MBOX_RD 0x2000
1269 +
1270 +/* Bit definitions for INT MASK are the same as INT_STATUS */
1271 +#define AR2315_LB_INT_MASK (AR2315_LOCAL + 0x0504)
1272 +
1273 +#define AR2315_LB_INT_EN (AR2315_LOCAL + 0x0508)
1274 +#define AR2315_LB_MBOX (AR2315_LOCAL + 0x0600)
1275 +
1276 +/*
1277 + * IR Interface Registers
1278 + */
1279 +#define AR2315_IR_PKTDATA (AR2315_IR + 0x0000)
1280 +
1281 +#define AR2315_IR_PKTLEN (AR2315_IR + 0x07fc) /* 0 - 63 */
1282 +
1283 +#define AR2315_IR_CONTROL (AR2315_IR + 0x0800)
1284 +#define AR2315_IRCTL_TX 0x00000000 /* use as tranmitter */
1285 +#define AR2315_IRCTL_RX 0x00000001 /* use as receiver */
1286 +#define AR2315_IRCTL_SAMPLECLK_MASK 0x00003ffe /* Sample clk divisor */
1287 +#define AR2315_IRCTL_SAMPLECLK_SHFT 1
1288 +#define AR2315_IRCTL_OUTPUTCLK_MASK 0x03ffc000 /* Output clk div */
1289 +#define AR2315_IRCTL_OUTPUTCLK_SHFT 14
1290 +
1291 +#define AR2315_IR_STATUS (AR2315_IR + 0x0804)
1292 +#define AR2315_IRSTS_RX 0x00000001 /* receive in progress */
1293 +#define AR2315_IRSTS_TX 0x00000002 /* transmit in progress */
1294 +
1295 +#define AR2315_IR_CONFIG (AR2315_IR + 0x0808)
1296 +#define AR2315_IRCFG_INVIN 0x00000001 /* invert in polarity */
1297 +#define AR2315_IRCFG_INVOUT 0x00000002 /* invert out polarity */
1298 +#define AR2315_IRCFG_SEQ_START_WIN_SEL 0x00000004 /* 1 => 28, 0 => 7 */
1299 +#define AR2315_IRCFG_SEQ_START_THRESH 0x000000f0
1300 +#define AR2315_IRCFG_SEQ_END_UNIT_SEL 0x00000100
1301 +#define AR2315_IRCFG_SEQ_END_UNIT_THRESH 0x00007e00
1302 +#define AR2315_IRCFG_SEQ_END_WIN_SEL 0x00008000
1303 +#define AR2315_IRCFG_SEQ_END_WIN_THRESH 0x001f0000
1304 +#define AR2315_IRCFG_NUM_BACKOFF_WORDS 0x01e00000
1305 +
1306 +#define HOST_PCI_DEV_ID 3
1307 +#define HOST_PCI_MBAR0 0x10000000
1308 +#define HOST_PCI_MBAR1 0x20000000
1309 +#define HOST_PCI_MBAR2 0x30000000
1310 +
1311 +#define HOST_PCI_SDRAM_BASEADDR HOST_PCI_MBAR1
1312 +#define PCI_DEVICE_MEM_SPACE 0x800000
1313 +
1314 +#endif /* __AR2315_REG_H */
1315 --- /dev/null
1316 +++ b/arch/mips/include/asm/mach-ar231x/ar5312_regs.h
1317 @@ -0,0 +1,233 @@
1318 +/*
1319 + * This file is subject to the terms and conditions of the GNU General Public
1320 + * License. See the file "COPYING" in the main directory of this archive
1321 + * for more details.
1322 + *
1323 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1324 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1325 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
1326 + */
1327 +
1328 +#ifndef AR5312_H
1329 +#define AR5312_H
1330 +
1331 +#include <asm/addrspace.h>
1332 +
1333 +/*
1334 + * IRQs
1335 + */
1336 +
1337 +#define AR5312_IRQ_WLAN0_INTRS (MIPS_CPU_IRQ_BASE+2) /* C0_CAUSE: 0x0400 */
1338 +#define AR5312_IRQ_ENET0_INTRS (MIPS_CPU_IRQ_BASE+3) /* C0_CAUSE: 0x0800 */
1339 +#define AR5312_IRQ_ENET1_INTRS (MIPS_CPU_IRQ_BASE+4) /* C0_CAUSE: 0x1000 */
1340 +#define AR5312_IRQ_WLAN1_INTRS (MIPS_CPU_IRQ_BASE+5) /* C0_CAUSE: 0x2000 */
1341 +#define AR5312_IRQ_MISC_INTRS (MIPS_CPU_IRQ_BASE+6) /* C0_CAUSE: 0x4000 */
1342 +
1343 +
1344 +/* Address Map */
1345 +#define AR531X_WLAN0 0x18000000
1346 +#define AR531X_WLAN1 0x18500000
1347 +#define AR531X_ENET0 0x18100000
1348 +#define AR531X_ENET1 0x18200000
1349 +#define AR531X_SDRAMCTL 0x18300000
1350 +#define AR531X_FLASHCTL 0x18400000
1351 +#define AR531X_APBBASE 0x1c000000
1352 +#define AR531X_FLASH 0x1e000000
1353 +#define AR531X_UART0 0xbc000003 /* UART MMR */
1354 +
1355 +/*
1356 + * AR531X_NUM_ENET_MAC defines the number of ethernet MACs that
1357 + * should be considered available. The AR5312 supports 2 enet MACS,
1358 + * even though many reference boards only actually use 1 of them
1359 + * (i.e. Only MAC 0 is actually connected to an enet PHY or PHY switch.
1360 + * The AR2312 supports 1 enet MAC.
1361 + */
1362 +#define AR531X_NUM_ENET_MAC 2
1363 +
1364 +/*
1365 + * Need these defines to determine true number of ethernet MACs
1366 + */
1367 +#define AR5212_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */
1368 +#define AR5212_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
1369 +#define AR5212_AR2313_REV8 0x0058 /* AR2313 WMAC (AP43-030) */
1370 +
1371 +/*
1372 + * AR531X_NUM_WMAC defines the number of Wireless MACs that\
1373 + * should be considered available.
1374 + */
1375 +#define AR531X_NUM_WMAC 2
1376 +
1377 +/* Reset/Timer Block Address Map */
1378 +#define AR531X_RESETTMR (AR531X_APBBASE + 0x3000)
1379 +#define AR531X_TIMER (AR531X_RESETTMR + 0x0000) /* countdown timer */
1380 +#define AR531X_WD_CTRL (AR531X_RESETTMR + 0x0008) /* watchdog cntrl */
1381 +#define AR531X_WD_TIMER (AR531X_RESETTMR + 0x000c) /* watchdog timer */
1382 +#define AR531X_ISR (AR531X_RESETTMR + 0x0010) /* Intr Status Reg */
1383 +#define AR531X_IMR (AR531X_RESETTMR + 0x0014) /* Intr Mask Reg */
1384 +#define AR531X_RESET (AR531X_RESETTMR + 0x0020)
1385 +#define AR5312_CLOCKCTL1 (AR531X_RESETTMR + 0x0064)
1386 +#define AR5312_SCRATCH (AR531X_RESETTMR + 0x006c)
1387 +#define AR531X_PROCADDR (AR531X_RESETTMR + 0x0070)
1388 +#define AR531X_PROC1 (AR531X_RESETTMR + 0x0074)
1389 +#define AR531X_DMAADDR (AR531X_RESETTMR + 0x0078)
1390 +#define AR531X_DMA1 (AR531X_RESETTMR + 0x007c)
1391 +#define AR531X_ENABLE (AR531X_RESETTMR + 0x0080) /* interface enb */
1392 +#define AR531X_REV (AR531X_RESETTMR + 0x0090) /* revision */
1393 +
1394 +/* AR531X_WD_CTRL register bit field definitions */
1395 +#define AR531X_WD_CTRL_IGNORE_EXPIRATION 0x0000
1396 +#define AR531X_WD_CTRL_NMI 0x0001
1397 +#define AR531X_WD_CTRL_RESET 0x0002
1398 +
1399 +/* AR531X_ISR register bit field definitions */
1400 +#define AR531X_ISR_NONE 0x0000
1401 +#define AR531X_ISR_TIMER 0x0001
1402 +#define AR531X_ISR_AHBPROC 0x0002
1403 +#define AR531X_ISR_AHBDMA 0x0004
1404 +#define AR531X_ISR_GPIO 0x0008
1405 +#define AR531X_ISR_UART0 0x0010
1406 +#define AR531X_ISR_UART0DMA 0x0020
1407 +#define AR531X_ISR_WD 0x0040
1408 +#define AR531X_ISR_LOCAL 0x0080
1409 +
1410 +/* AR531X_RESET register bit field definitions */
1411 +#define AR531X_RESET_SYSTEM 0x00000001 /* cold reset full system */
1412 +#define AR531X_RESET_PROC 0x00000002 /* cold reset MIPS core */
1413 +#define AR531X_RESET_WLAN0 0x00000004 /* cold reset WLAN MAC and BB */
1414 +#define AR531X_RESET_EPHY0 0x00000008 /* cold reset ENET0 phy */
1415 +#define AR531X_RESET_EPHY1 0x00000010 /* cold reset ENET1 phy */
1416 +#define AR531X_RESET_ENET0 0x00000020 /* cold reset ENET0 mac */
1417 +#define AR531X_RESET_ENET1 0x00000040 /* cold reset ENET1 mac */
1418 +#define AR531X_RESET_UART0 0x00000100 /* cold reset UART0 (high speed) */
1419 +#define AR531X_RESET_WLAN1 0x00000200 /* cold reset WLAN MAC/BB */
1420 +#define AR531X_RESET_APB 0x00000400 /* cold reset APB (ar5312) */
1421 +#define AR531X_RESET_WARM_PROC 0x00001000 /* warm reset MIPS core */
1422 +#define AR531X_RESET_WARM_WLAN0_MAC 0x00002000 /* warm reset WLAN0 MAC */
1423 +#define AR531X_RESET_WARM_WLAN0_BB 0x00004000 /* warm reset WLAN0 BaseBand */
1424 +#define AR531X_RESET_NMI 0x00010000 /* send an NMI to the processor */
1425 +#define AR531X_RESET_WARM_WLAN1_MAC 0x00020000 /* warm reset WLAN1 mac */
1426 +#define AR531X_RESET_WARM_WLAN1_BB 0x00040000 /* warm reset WLAN1 baseband */
1427 +#define AR531X_RESET_LOCAL_BUS 0x00080000 /* reset local bus */
1428 +#define AR531X_RESET_WDOG 0x00100000 /* last reset was a watchdog */
1429 +
1430 +#define AR531X_RESET_WMAC0_BITS \
1431 + (AR531X_RESET_WLAN0 |\
1432 + AR531X_RESET_WARM_WLAN0_MAC |\
1433 + AR531X_RESET_WARM_WLAN0_BB)
1434 +
1435 +#define AR531X_RESERT_WMAC1_BITS \
1436 + (AR531X_RESET_WLAN1 |\
1437 + AR531X_RESET_WARM_WLAN1_MAC |\
1438 + AR531X_RESET_WARM_WLAN1_BB)
1439 +
1440 +/* AR5312_CLOCKCTL1 register bit field definitions */
1441 +#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1442 +#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1443 +#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1444 +#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1445 +#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1446 +
1447 +/* Valid for AR5312 and AR2312 */
1448 +#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1449 +#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1450 +#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1451 +#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1452 +#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1453 +
1454 +/* Valid for AR2313 */
1455 +#define AR2313_CLOCKCTL1_PREDIVIDE_MASK 0x00003000
1456 +#define AR2313_CLOCKCTL1_PREDIVIDE_SHIFT 12
1457 +#define AR2313_CLOCKCTL1_MULTIPLIER_MASK 0x001f0000
1458 +#define AR2313_CLOCKCTL1_MULTIPLIER_SHIFT 16
1459 +#define AR2313_CLOCKCTL1_DOUBLER_MASK 0x00000000
1460 +
1461 +
1462 +/* AR531X_ENABLE register bit field definitions */
1463 +#define AR531X_ENABLE_WLAN0 0x0001
1464 +#define AR531X_ENABLE_ENET0 0x0002
1465 +#define AR531X_ENABLE_ENET1 0x0004
1466 +#define AR531X_ENABLE_UART_AND_WLAN1_PIO 0x0008 /* UART, and WLAN1 PIOs */
1467 +#define AR531X_ENABLE_WLAN1_DMA 0x0010 /* WLAN1 DMAs */
1468 +#define AR531X_ENABLE_WLAN1 \
1469 + (AR531X_ENABLE_UART_AND_WLAN1_PIO |\
1470 + AR531X_ENABLE_WLAN1_DMA)
1471 +
1472 +/* AR531X_REV register bit field definitions */
1473 +#define AR531X_REV_WMAC_MAJ 0xf000
1474 +#define AR531X_REV_WMAC_MAJ_S 12
1475 +#define AR531X_REV_WMAC_MIN 0x0f00
1476 +#define AR531X_REV_WMAC_MIN_S 8
1477 +#define AR531X_REV_MAJ 0x00f0
1478 +#define AR531X_REV_MAJ_S 4
1479 +#define AR531X_REV_MIN 0x000f
1480 +#define AR531X_REV_MIN_S 0
1481 +#define AR531X_REV_CHIP (AR531X_REV_MAJ|AR531X_REV_MIN)
1482 +
1483 +/* Major revision numbers, bits 7..4 of Revision ID register */
1484 +#define AR531X_REV_MAJ_AR5312 0x4
1485 +#define AR531X_REV_MAJ_AR2313 0x5
1486 +
1487 +/* Minor revision numbers, bits 3..0 of Revision ID register */
1488 +#define AR5312_REV_MIN_DUAL 0x0 /* Dual WLAN version */
1489 +#define AR5312_REV_MIN_SINGLE 0x1 /* Single WLAN version */
1490 +
1491 +/* AR531X_FLASHCTL register bit field definitions */
1492 +#define FLASHCTL_IDCY 0x0000000f /* Idle cycle turn around time */
1493 +#define FLASHCTL_IDCY_S 0
1494 +#define FLASHCTL_WST1 0x000003e0 /* Wait state 1 */
1495 +#define FLASHCTL_WST1_S 5
1496 +#define FLASHCTL_RBLE 0x00000400 /* Read byte lane enable */
1497 +#define FLASHCTL_WST2 0x0000f800 /* Wait state 2 */
1498 +#define FLASHCTL_WST2_S 11
1499 +#define FLASHCTL_AC 0x00070000 /* Flash address check (added) */
1500 +#define FLASHCTL_AC_S 16
1501 +#define FLASHCTL_AC_128K 0x00000000
1502 +#define FLASHCTL_AC_256K 0x00010000
1503 +#define FLASHCTL_AC_512K 0x00020000
1504 +#define FLASHCTL_AC_1M 0x00030000
1505 +#define FLASHCTL_AC_2M 0x00040000
1506 +#define FLASHCTL_AC_4M 0x00050000
1507 +#define FLASHCTL_AC_8M 0x00060000
1508 +#define FLASHCTL_AC_RES 0x00070000 /* 16MB is not supported */
1509 +#define FLASHCTL_E 0x00080000 /* Flash bank enable (added) */
1510 +#define FLASHCTL_BUSERR 0x01000000 /* Bus transfer error status flag */
1511 +#define FLASHCTL_WPERR 0x02000000 /* Write protect error status flag */
1512 +#define FLASHCTL_WP 0x04000000 /* Write protect */
1513 +#define FLASHCTL_BM 0x08000000 /* Burst mode */
1514 +#define FLASHCTL_MW 0x30000000 /* Memory width */
1515 +#define FLASHCTL_MWx8 0x00000000 /* Memory width x8 */
1516 +#define FLASHCTL_MWx16 0x10000000 /* Memory width x16 */
1517 +#define FLASHCTL_MWx32 0x20000000 /* Memory width x32 (not supported) */
1518 +#define FLASHCTL_ATNR 0x00000000 /* Access type == no retry */
1519 +#define FLASHCTL_ATR 0x80000000 /* Access type == retry every */
1520 +#define FLASHCTL_ATR4 0xc0000000 /* Access type == retry every 4 */
1521 +
1522 +/* ARM Flash Controller -- 3 flash banks with either x8 or x16 devices. */
1523 +#define AR531X_FLASHCTL0 (AR531X_FLASHCTL + 0x00)
1524 +#define AR531X_FLASHCTL1 (AR531X_FLASHCTL + 0x04)
1525 +#define AR531X_FLASHCTL2 (AR531X_FLASHCTL + 0x08)
1526 +
1527 +/* ARM SDRAM Controller -- just enough to determine memory size */
1528 +#define AR531X_MEM_CFG1 (AR531X_SDRAMCTL + 0x04)
1529 +#define MEM_CFG1_AC0 0x00000700 /* bank 0: SDRAM addr check (added) */
1530 +#define MEM_CFG1_AC0_S 8
1531 +#define MEM_CFG1_AC1 0x00007000 /* bank 1: SDRAM addr check (added) */
1532 +#define MEM_CFG1_AC1_S 12
1533 +
1534 +/* GPIO Address Map */
1535 +#define AR531X_GPIO (AR531X_APBBASE + 0x2000)
1536 +#define AR531X_GPIO_DO (AR531X_GPIO + 0x00) /* output register */
1537 +#define AR531X_GPIO_DI (AR531X_GPIO + 0x04) /* intput register */
1538 +#define AR531X_GPIO_CR (AR531X_GPIO + 0x08) /* control register */
1539 +
1540 +/* GPIO Control Register bit field definitions */
1541 +#define AR531X_GPIO_CR_M(x) (1 << (x)) /* mask for i/o */
1542 +#define AR531X_GPIO_CR_O(x) (0 << (x)) /* mask for output */
1543 +#define AR531X_GPIO_CR_I(x) (1 << (x)) /* mask for input */
1544 +#define AR531X_GPIO_CR_INT(x) (1 << ((x)+8)) /* mask for interrupt*/
1545 +#define AR531X_GPIO_CR_UART(x) (1 << ((x)+16)) /* uart multiplex */
1546 +#define AR531X_NUM_GPIO 8
1547 +
1548 +
1549 +#endif
1550 +
1551 --- /dev/null
1552 +++ b/arch/mips/ar231x/ar5312.c
1553 @@ -0,0 +1,602 @@
1554 +/*
1555 + * This file is subject to the terms and conditions of the GNU General Public
1556 + * License. See the file "COPYING" in the main directory of this archive
1557 + * for more details.
1558 + *
1559 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1560 + * Copyright (C) 2006 FON Technology, SL.
1561 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1562 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
1563 + * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
1564 + */
1565 +
1566 +/*
1567 + * Platform devices for Atheros SoCs
1568 + */
1569 +
1570 +#include <generated/autoconf.h>
1571 +#include <linux/init.h>
1572 +#include <linux/module.h>
1573 +#include <linux/types.h>
1574 +#include <linux/string.h>
1575 +#include <linux/mtd/physmap.h>
1576 +#include <linux/platform_device.h>
1577 +#include <linux/kernel.h>
1578 +#include <linux/reboot.h>
1579 +#include <linux/leds.h>
1580 +#include <linux/gpio.h>
1581 +#include <asm/bootinfo.h>
1582 +#include <asm/reboot.h>
1583 +#include <asm/time.h>
1584 +#include <linux/irq.h>
1585 +#include <linux/io.h>
1586 +
1587 +#include <ar231x_platform.h>
1588 +#include <ar5312_regs.h>
1589 +#include <ar231x.h>
1590 +#include "devices.h"
1591 +#include "ar5312.h"
1592 +
1593 +static void
1594 +ar5312_misc_irq_dispatch(void)
1595 +{
1596 + unsigned int ar231x_misc_intrs = ar231x_read_reg(AR531X_ISR) &
1597 + ar231x_read_reg(AR531X_IMR);
1598 +
1599 + if (ar231x_misc_intrs & AR531X_ISR_TIMER) {
1600 + do_IRQ(AR531X_MISC_IRQ_TIMER);
1601 + (void)ar231x_read_reg(AR531X_TIMER);
1602 + } else if (ar231x_misc_intrs & AR531X_ISR_AHBPROC)
1603 + do_IRQ(AR531X_MISC_IRQ_AHB_PROC);
1604 + else if ((ar231x_misc_intrs & AR531X_ISR_UART0))
1605 + do_IRQ(AR531X_MISC_IRQ_UART0);
1606 + else if (ar231x_misc_intrs & AR531X_ISR_WD)
1607 + do_IRQ(AR531X_MISC_IRQ_WATCHDOG);
1608 + else
1609 + do_IRQ(AR531X_MISC_IRQ_NONE);
1610 +}
1611 +
1612 +static asmlinkage void
1613 +ar5312_irq_dispatch(void)
1614 +{
1615 + int pending = read_c0_status() & read_c0_cause();
1616 +
1617 + if (pending & CAUSEF_IP2)
1618 + do_IRQ(AR5312_IRQ_WLAN0_INTRS);
1619 + else if (pending & CAUSEF_IP3)
1620 + do_IRQ(AR5312_IRQ_ENET0_INTRS);
1621 + else if (pending & CAUSEF_IP4)
1622 + do_IRQ(AR5312_IRQ_ENET1_INTRS);
1623 + else if (pending & CAUSEF_IP5)
1624 + do_IRQ(AR5312_IRQ_WLAN1_INTRS);
1625 + else if (pending & CAUSEF_IP6)
1626 + ar5312_misc_irq_dispatch();
1627 + else if (pending & CAUSEF_IP7)
1628 + do_IRQ(AR531X_IRQ_CPU_CLOCK);
1629 +}
1630 +
1631 +
1632 +/* Enable the specified AR531X_MISC_IRQ interrupt */
1633 +static void
1634 +ar5312_misc_irq_unmask(struct irq_data *d)
1635 +{
1636 + unsigned int imr;
1637 +
1638 + imr = ar231x_read_reg(AR531X_IMR);
1639 + imr |= (1 << (d->irq - AR531X_MISC_IRQ_BASE - 1));
1640 + ar231x_write_reg(AR531X_IMR, imr);
1641 +}
1642 +
1643 +/* Disable the specified AR531X_MISC_IRQ interrupt */
1644 +static void
1645 +ar5312_misc_irq_mask(struct irq_data *d)
1646 +{
1647 + unsigned int imr;
1648 +
1649 + imr = ar231x_read_reg(AR531X_IMR);
1650 + imr &= ~(1 << (d->irq - AR531X_MISC_IRQ_BASE - 1));
1651 + ar231x_write_reg(AR531X_IMR, imr);
1652 + ar231x_read_reg(AR531X_IMR); /* flush write buffer */
1653 +}
1654 +
1655 +static struct irq_chip ar5312_misc_irq_chip = {
1656 + .name = "AR5312-MISC",
1657 + .irq_unmask = ar5312_misc_irq_unmask,
1658 + .irq_mask = ar5312_misc_irq_mask,
1659 +};
1660 +
1661 +
1662 +static irqreturn_t ar5312_ahb_proc_handler(int cpl, void *dev_id)
1663 +{
1664 + u32 proc1 = ar231x_read_reg(AR531X_PROC1);
1665 + u32 proc_addr = ar231x_read_reg(AR531X_PROCADDR); /* clears error */
1666 + u32 dma1 = ar231x_read_reg(AR531X_DMA1);
1667 + u32 dma_addr = ar231x_read_reg(AR531X_DMAADDR); /* clears error */
1668 +
1669 + pr_emerg("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x "
1670 + "DMAADDR=0x%8.8x DMA1=0x%8.8x\n", proc_addr, proc1, dma_addr,
1671 + dma1);
1672 +
1673 + machine_restart("AHB error"); /* Catastrophic failure */
1674 + return IRQ_HANDLED;
1675 +}
1676 +
1677 +
1678 +static struct irqaction ar5312_ahb_proc_interrupt = {
1679 + .handler = ar5312_ahb_proc_handler,
1680 + .name = "ar5312_ahb_proc_interrupt",
1681 +};
1682 +
1683 +
1684 +static struct irqaction cascade = {
1685 + .handler = no_action,
1686 + .name = "cascade",
1687 +};
1688 +
1689 +void __init ar5312_irq_init(void)
1690 +{
1691 + int i;
1692 +
1693 + if (!is_5312())
1694 + return;
1695 +
1696 + ar231x_irq_dispatch = ar5312_irq_dispatch;
1697 + for (i = 0; i < AR531X_MISC_IRQ_COUNT; i++) {
1698 + int irq = AR531X_MISC_IRQ_BASE + i;
1699 + irq_set_chip_and_handler(irq, &ar5312_misc_irq_chip,
1700 + handle_level_irq);
1701 + }
1702 + setup_irq(AR531X_MISC_IRQ_AHB_PROC, &ar5312_ahb_proc_interrupt);
1703 + setup_irq(AR5312_IRQ_MISC_INTRS, &cascade);
1704 +}
1705 +
1706 +static u32
1707 +ar5312_gpio_set_output(u32 mask, u32 val)
1708 +{
1709 + u32 reg;
1710 +
1711 + reg = ar231x_read_reg(AR531X_GPIO_CR);
1712 + reg |= mask;
1713 + reg &= ~val;
1714 + ar231x_write_reg(AR531X_GPIO_CR, reg);
1715 + return reg;
1716 +}
1717 +
1718 +static u32
1719 +ar5312_gpio_get(u32 valid_mask)
1720 +{
1721 + u32 reg;
1722 + reg = ar231x_read_reg(AR531X_GPIO_DI);
1723 + reg &= valid_mask;
1724 + return reg;
1725 +}
1726 +
1727 +static u32
1728 +ar5312_gpio_set(u32 mask, u32 value)
1729 +{
1730 + u32 reg;
1731 + reg = ar231x_read_reg(AR531X_GPIO_DO);
1732 + reg &= ~mask;
1733 + reg |= value;
1734 + ar231x_write_reg(AR531X_GPIO_DO, reg);
1735 + return reg;
1736 +}
1737 +
1738 +/*
1739 + * gpiolib implementations. Original mask based methods preserved
1740 + */
1741 +static int
1742 +ar5312_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
1743 +{
1744 + struct ar231x_gpio_chip *gpch =
1745 + container_of(chip, struct ar231x_gpio_chip, chip);
1746 + u32 mask = 1 << gpio;
1747 + u32 rett;
1748 + if (!(gpch->valid_mask & mask))
1749 + return 0;
1750 + rett = ar5312_gpio_get(gpch->valid_mask);
1751 + return !!(rett & mask);
1752 +}
1753 +
1754 +static void
1755 +ar5312_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
1756 +{
1757 + struct ar231x_gpio_chip *gpch =
1758 + container_of(chip, struct ar231x_gpio_chip, chip);
1759 + u32 mask = 1 << gpio;
1760 + if (!(gpch->valid_mask & mask))
1761 + return;
1762 + ar5312_gpio_set(mask, (!!value) * mask);
1763 +}
1764 +
1765 +static int
1766 +ar5312_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
1767 +{
1768 + struct ar231x_gpio_chip *gpch =
1769 + container_of(chip, struct ar231x_gpio_chip, chip);
1770 + u32 mask = 1 << gpio;
1771 + if (!(gpch->valid_mask & mask))
1772 + return -ENXIO;
1773 + ar5312_gpio_set_output(mask, 0);
1774 + return 0;
1775 +}
1776 +static int
1777 +ar5312_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
1778 +{
1779 + struct ar231x_gpio_chip *gpch =
1780 + container_of(chip, struct ar231x_gpio_chip, chip);
1781 + u32 mask = 1 << gpio;
1782 + if (!(gpch->valid_mask & mask))
1783 + return -ENXIO;
1784 + ar5312_gpio_set_output(mask, mask);
1785 + ar5312_gpio_set(mask, (!!value) * mask);
1786 + return 0;
1787 +}
1788 +
1789 +static struct ar231x_gpio_chip ar5312_gpio_chip = {
1790 + .valid_mask = (1 << 22) - 1,
1791 + .chip = {
1792 + .label = "ar5312-gpio",
1793 + .direction_input = ar5312_gpio_direction_input,
1794 + .direction_output = ar5312_gpio_direction_output,
1795 + .set = ar5312_gpio_set_value,
1796 + .get = ar5312_gpio_get_value,
1797 + .base = 0,
1798 + .ngpio = AR531X_GPIO_IRQ_COUNT, /* 22 */
1799 + }
1800 +};
1801 +
1802 +/* end of gpiolib */
1803 +
1804 +static void ar5312_device_reset_set(u32 mask)
1805 +{
1806 + u32 val;
1807 +
1808 + val = ar231x_read_reg(AR531X_RESET);
1809 + ar231x_write_reg(AR531X_RESET, val | mask);
1810 +}
1811 +
1812 +static void ar5312_device_reset_clear(u32 mask)
1813 +{
1814 + u32 val;
1815 +
1816 + val = ar231x_read_reg(AR531X_RESET);
1817 + ar231x_write_reg(AR531X_RESET, val & ~mask);
1818 +}
1819 +
1820 +static struct physmap_flash_data ar5312_flash_data = {
1821 + .width = 2,
1822 +};
1823 +
1824 +static struct resource ar5312_flash_resource = {
1825 + .start = AR531X_FLASH,
1826 + .end = AR531X_FLASH + 0x800000 - 1,
1827 + .flags = IORESOURCE_MEM,
1828 +};
1829 +
1830 +static struct ar231x_eth ar5312_eth0_data = {
1831 + .reset_set = ar5312_device_reset_set,
1832 + .reset_clear = ar5312_device_reset_clear,
1833 + .reset_mac = AR531X_RESET_ENET0,
1834 + .reset_phy = AR531X_RESET_EPHY0,
1835 + .phy_base = KSEG1ADDR(AR531X_ENET0),
1836 + .config = &ar231x_board,
1837 +};
1838 +
1839 +static struct ar231x_eth ar5312_eth1_data = {
1840 + .reset_set = ar5312_device_reset_set,
1841 + .reset_clear = ar5312_device_reset_clear,
1842 + .reset_mac = AR531X_RESET_ENET1,
1843 + .reset_phy = AR531X_RESET_EPHY1,
1844 + .phy_base = KSEG1ADDR(AR531X_ENET1),
1845 + .config = &ar231x_board,
1846 +};
1847 +
1848 +static struct platform_device ar5312_physmap_flash = {
1849 + .name = "physmap-flash",
1850 + .id = 0,
1851 + .dev.platform_data = &ar5312_flash_data,
1852 + .resource = &ar5312_flash_resource,
1853 + .num_resources = 1,
1854 +};
1855 +
1856 +#ifdef CONFIG_LEDS_GPIO
1857 +static struct gpio_led ar5312_leds[] = {
1858 + { .name = "wlan", .gpio = 0, .active_low = 1, },
1859 +};
1860 +
1861 +static const struct gpio_led_platform_data ar5312_led_data = {
1862 + .num_leds = ARRAY_SIZE(ar5312_leds),
1863 + .leds = (void *)ar5312_leds,
1864 +};
1865 +
1866 +static struct platform_device ar5312_gpio_leds = {
1867 + .name = "leds-gpio",
1868 + .id = -1,
1869 + .dev.platform_data = (void *)&ar5312_led_data,
1870 +};
1871 +#endif
1872 +
1873 +/*
1874 + * NB: This mapping size is larger than the actual flash size,
1875 + * but this shouldn't be a problem here, because the flash
1876 + * will simply be mapped multiple times.
1877 + */
1878 +static char __init *ar5312_flash_limit(void)
1879 +{
1880 + u32 ctl;
1881 + /*
1882 + * Configure flash bank 0.
1883 + * Assume 8M window size. Flash will be aliased if it's smaller
1884 + */
1885 + ctl = FLASHCTL_E |
1886 + FLASHCTL_AC_8M |
1887 + FLASHCTL_RBLE |
1888 + (0x01 << FLASHCTL_IDCY_S) |
1889 + (0x07 << FLASHCTL_WST1_S) |
1890 + (0x07 << FLASHCTL_WST2_S) |
1891 + (ar231x_read_reg(AR531X_FLASHCTL0) & FLASHCTL_MW);
1892 +
1893 + ar231x_write_reg(AR531X_FLASHCTL0, ctl);
1894 +
1895 + /* Disable other flash banks */
1896 + ar231x_write_reg(AR531X_FLASHCTL1,
1897 + ar231x_read_reg(AR531X_FLASHCTL1) &
1898 + ~(FLASHCTL_E | FLASHCTL_AC));
1899 +
1900 + ar231x_write_reg(AR531X_FLASHCTL2,
1901 + ar231x_read_reg(AR531X_FLASHCTL2) &
1902 + ~(FLASHCTL_E | FLASHCTL_AC));
1903 +
1904 + return (char *)KSEG1ADDR(AR531X_FLASH + 0x800000);
1905 +}
1906 +
1907 +int __init ar5312_init_devices(void)
1908 +{
1909 + struct ar231x_boarddata *config;
1910 + u32 fctl = 0;
1911 + u8 *c;
1912 +
1913 + if (!is_5312())
1914 + return 0;
1915 +
1916 + /* Locate board/radio config data */
1917 + ar231x_find_config(ar5312_flash_limit());
1918 + config = ar231x_board.config;
1919 +
1920 + /* AR2313 has CPU minor rev. 10 */
1921 + if ((current_cpu_data.processor_id & 0xff) == 0x0a)
1922 + ar231x_devtype = DEV_TYPE_AR2313;
1923 +
1924 + /* AR2312 shares the same Silicon ID as AR5312 */
1925 + else if (config->flags & BD_ISCASPER)
1926 + ar231x_devtype = DEV_TYPE_AR2312;
1927 +
1928 + /* Everything else is probably AR5312 or compatible */
1929 + else
1930 + ar231x_devtype = DEV_TYPE_AR5312;
1931 +
1932 + /* fixup flash width */
1933 + fctl = ar231x_read_reg(AR531X_FLASHCTL) & FLASHCTL_MW;
1934 + switch (fctl) {
1935 + case FLASHCTL_MWx16:
1936 + ar5312_flash_data.width = 2;
1937 + break;
1938 + case FLASHCTL_MWx8:
1939 + default:
1940 + ar5312_flash_data.width = 1;
1941 + break;
1942 + }
1943 +
1944 + platform_device_register(&ar5312_physmap_flash);
1945 +
1946 +#ifdef CONFIG_LEDS_GPIO
1947 + ar5312_leds[0].gpio = config->sys_led_gpio;
1948 + platform_device_register(&ar5312_gpio_leds);
1949 +#endif
1950 +
1951 + /* Fix up MAC addresses if necessary */
1952 + if (!memcmp(config->enet0_mac, "\xff\xff\xff\xff\xff\xff", 6))
1953 + memcpy(config->enet0_mac, config->enet1_mac, 6);
1954 +
1955 + /* If ENET0 and ENET1 have the same mac address,
1956 + * increment the one from ENET1 */
1957 + if (memcmp(config->enet0_mac, config->enet1_mac, 6) == 0) {
1958 + c = config->enet1_mac + 5;
1959 + while ((c >= config->enet1_mac) && !(++(*c)))
1960 + c--;
1961 + }
1962 +
1963 + switch (ar231x_devtype) {
1964 + case DEV_TYPE_AR5312:
1965 + ar5312_eth0_data.macaddr = config->enet0_mac;
1966 + ar231x_add_ethernet(0, KSEG1ADDR(AR531X_ENET0),
1967 + AR5312_IRQ_ENET0_INTRS, &ar5312_eth0_data);
1968 +
1969 + ar5312_eth1_data.macaddr = config->enet1_mac;
1970 + ar231x_add_ethernet(1, KSEG1ADDR(AR531X_ENET1),
1971 + AR5312_IRQ_ENET1_INTRS, &ar5312_eth1_data);
1972 +
1973 + if (!ar231x_board.radio)
1974 + return 0;
1975 +
1976 + if (!(config->flags & BD_WLAN0))
1977 + break;
1978 +
1979 + ar231x_add_wmac(0, AR531X_WLAN0, AR5312_IRQ_WLAN0_INTRS);
1980 + break;
1981 + /*
1982 + * AR2312/3 ethernet uses the PHY of ENET0, but the MAC
1983 + * of ENET1. Atheros calls it 'twisted' for a reason :)
1984 + */
1985 + case DEV_TYPE_AR2312:
1986 + case DEV_TYPE_AR2313:
1987 + ar5312_eth1_data.phy_base = ar5312_eth0_data.phy_base;
1988 + ar5312_eth1_data.reset_phy = ar5312_eth0_data.reset_phy;
1989 + ar5312_eth1_data.macaddr = config->enet0_mac;
1990 + ar231x_add_ethernet(0, KSEG1ADDR(AR531X_ENET1),
1991 + AR5312_IRQ_ENET1_INTRS, &ar5312_eth1_data);
1992 +
1993 + if (!ar231x_board.radio)
1994 + return 0;
1995 + break;
1996 + default:
1997 + break;
1998 + }
1999 +
2000 + if (config->flags & BD_WLAN1)
2001 + ar231x_add_wmac(1, AR531X_WLAN1, AR5312_IRQ_WLAN1_INTRS);
2002 +
2003 + return 0;
2004 +}
2005 +
2006 +
2007 +static void ar5312_restart(char *command)
2008 +{
2009 + /* reset the system */
2010 + local_irq_disable();
2011 + while (1)
2012 + ar231x_write_reg(AR531X_RESET, AR531X_RESET_SYSTEM);
2013 +}
2014 +
2015 +
2016 +/*
2017 + * This table is indexed by bits 5..4 of the CLOCKCTL1 register
2018 + * to determine the predevisor value.
2019 + */
2020 +static int clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
2021 +
2022 +
2023 +static int __init
2024 +ar5312_cpu_frequency(void)
2025 +{
2026 + unsigned int scratch;
2027 + unsigned int predivide_mask, predivide_shift;
2028 + unsigned int multiplier_mask, multiplier_shift;
2029 + unsigned int clock_ctl1, predivide_select, predivisor, multiplier;
2030 + unsigned int doubler_mask;
2031 + u16 devid;
2032 +
2033 + /* Trust the bootrom's idea of cpu frequency. */
2034 + scratch = ar231x_read_reg(AR5312_SCRATCH);
2035 + if (scratch)
2036 + return scratch;
2037 +
2038 + devid = ar231x_read_reg(AR531X_REV);
2039 + devid &= AR531X_REV_MAJ;
2040 + devid >>= AR531X_REV_MAJ_S;
2041 + if (devid == AR531X_REV_MAJ_AR2313) {
2042 + predivide_mask = AR2313_CLOCKCTL1_PREDIVIDE_MASK;
2043 + predivide_shift = AR2313_CLOCKCTL1_PREDIVIDE_SHIFT;
2044 + multiplier_mask = AR2313_CLOCKCTL1_MULTIPLIER_MASK;
2045 + multiplier_shift = AR2313_CLOCKCTL1_MULTIPLIER_SHIFT;
2046 + doubler_mask = AR2313_CLOCKCTL1_DOUBLER_MASK;
2047 + } else { /* AR5312 and AR2312 */
2048 + predivide_mask = AR5312_CLOCKCTL1_PREDIVIDE_MASK;
2049 + predivide_shift = AR5312_CLOCKCTL1_PREDIVIDE_SHIFT;
2050 + multiplier_mask = AR5312_CLOCKCTL1_MULTIPLIER_MASK;
2051 + multiplier_shift = AR5312_CLOCKCTL1_MULTIPLIER_SHIFT;
2052 + doubler_mask = AR5312_CLOCKCTL1_DOUBLER_MASK;
2053 + }
2054 +
2055 + /*
2056 + * Clocking is derived from a fixed 40MHz input clock.
2057 + *
2058 + * cpu_freq = input_clock * MULT (where MULT is PLL multiplier)
2059 + * sys_freq = cpu_freq / 4 (used for APB clock, serial,
2060 + * flash, Timer, Watchdog Timer)
2061 + *
2062 + * cnt_freq = cpu_freq / 2 (use for CPU count/compare)
2063 + *
2064 + * So, for example, with a PLL multiplier of 5, we have
2065 + *
2066 + * cpu_freq = 200MHz
2067 + * sys_freq = 50MHz
2068 + * cnt_freq = 100MHz
2069 + *
2070 + * We compute the CPU frequency, based on PLL settings.
2071 + */
2072 +
2073 + clock_ctl1 = ar231x_read_reg(AR5312_CLOCKCTL1);
2074 + predivide_select = (clock_ctl1 & predivide_mask) >> predivide_shift;
2075 + predivisor = clockctl1_predivide_table[predivide_select];
2076 + multiplier = (clock_ctl1 & multiplier_mask) >> multiplier_shift;
2077 +
2078 + if (clock_ctl1 & doubler_mask)
2079 + multiplier = multiplier << 1;
2080 +
2081 + return (40000000 / predivisor) * multiplier;
2082 +}
2083 +
2084 +static inline int
2085 +ar5312_sys_frequency(void)
2086 +{
2087 + return ar5312_cpu_frequency() / 4;
2088 +}
2089 +
2090 +void __init
2091 +ar5312_time_init(void)
2092 +{
2093 + if (!is_5312())
2094 + return;
2095 +
2096 + mips_hpt_frequency = ar5312_cpu_frequency() / 2;
2097 +}
2098 +
2099 +int __init
2100 +ar5312_gpio_init(void)
2101 +{
2102 + int ret;
2103 + struct ar231x_gpio_chip *gpch;
2104 + gpch = &ar5312_gpio_chip;
2105 + ret = gpiochip_add(&gpch->chip);
2106 + if (ret) {
2107 + pr_err("%s: failed to add gpiochip\n", gpch->chip.label);
2108 + return ret;
2109 + }
2110 + pr_info("%s: registered %d GPIOs\n", gpch->chip.label,
2111 + gpch->chip.ngpio);
2112 + return ret;
2113 +}
2114 +
2115 +void __init
2116 +ar5312_prom_init(void)
2117 +{
2118 + u32 memsize, memcfg, bank0AC, bank1AC;
2119 + u32 devid;
2120 +
2121 + if (!is_5312())
2122 + return;
2123 +
2124 + /* Detect memory size */
2125 + memcfg = ar231x_read_reg(AR531X_MEM_CFG1);
2126 + bank0AC = (memcfg & MEM_CFG1_AC0) >> MEM_CFG1_AC0_S;
2127 + bank1AC = (memcfg & MEM_CFG1_AC1) >> MEM_CFG1_AC1_S;
2128 + memsize = (bank0AC ? (1 << (bank0AC+1)) : 0) +
2129 + (bank1AC ? (1 << (bank1AC+1)) : 0);
2130 + memsize <<= 20;
2131 + add_memory_region(0, memsize, BOOT_MEM_RAM);
2132 +
2133 + devid = ar231x_read_reg(AR531X_REV);
2134 + devid >>= AR531X_REV_WMAC_MIN_S;
2135 + devid &= AR531X_REV_CHIP;
2136 + ar231x_board.devid = (u16) devid;
2137 + ar5312_gpio_init();
2138 +}
2139 +
2140 +void __init
2141 +ar5312_plat_setup(void)
2142 +{
2143 + if (!is_5312())
2144 + return;
2145 +
2146 + /* Clear any lingering AHB errors */
2147 + ar231x_read_reg(AR531X_PROCADDR);
2148 + ar231x_read_reg(AR531X_DMAADDR);
2149 + ar231x_write_reg(AR531X_WD_CTRL, AR531X_WD_CTRL_IGNORE_EXPIRATION);
2150 +
2151 + _machine_restart = ar5312_restart;
2152 + ar231x_serial_setup(KSEG1ADDR(AR531X_UART0), AR531X_MISC_IRQ_UART0,
2153 + ar5312_sys_frequency());
2154 +}
2155 +
2156 --- /dev/null
2157 +++ b/arch/mips/ar231x/ar2315.c
2158 @@ -0,0 +1,663 @@
2159 +/*
2160 + * This file is subject to the terms and conditions of the GNU General Public
2161 + * License. See the file "COPYING" in the main directory of this archive
2162 + * for more details.
2163 + *
2164 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
2165 + * Copyright (C) 2006 FON Technology, SL.
2166 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
2167 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
2168 + * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
2169 + */
2170 +
2171 +/*
2172 + * Platform devices for Atheros SoCs
2173 + */
2174 +
2175 +#include <generated/autoconf.h>
2176 +#include <linux/init.h>
2177 +#include <linux/module.h>
2178 +#include <linux/types.h>
2179 +#include <linux/string.h>
2180 +#include <linux/platform_device.h>
2181 +#include <linux/kernel.h>
2182 +#include <linux/reboot.h>
2183 +#include <linux/delay.h>
2184 +#include <linux/leds.h>
2185 +#include <linux/gpio.h>
2186 +#include <asm/bootinfo.h>
2187 +#include <asm/reboot.h>
2188 +#include <asm/time.h>
2189 +#include <linux/irq.h>
2190 +#include <linux/io.h>
2191 +
2192 +#include <ar231x_platform.h>
2193 +#include <ar2315_regs.h>
2194 +#include <ar231x.h>
2195 +#include "devices.h"
2196 +#include "ar2315.h"
2197 +
2198 +static u32 gpiointmask, gpiointval;
2199 +
2200 +static inline void ar2315_gpio_irq(void)
2201 +{
2202 + u32 pend;
2203 + int bit = -1;
2204 +
2205 + /* only do one gpio interrupt at a time */
2206 + pend = (ar231x_read_reg(AR2315_GPIO_DI) ^ gpiointval) & gpiointmask;
2207 +
2208 + if (pend) {
2209 + bit = fls(pend) - 1;
2210 + pend &= ~(1 << bit);
2211 + gpiointval ^= (1 << bit);
2212 + }
2213 +
2214 + if (!pend)
2215 + ar231x_write_reg(AR2315_ISR, AR2315_ISR_GPIO);
2216 +
2217 + /* Enable interrupt with edge detection */
2218 + if ((ar231x_read_reg(AR2315_GPIO_CR) & AR2315_GPIO_CR_M(bit)) !=
2219 + AR2315_GPIO_CR_I(bit))
2220 + return;
2221 +
2222 + if (bit >= 0)
2223 + do_IRQ(AR531X_GPIO_IRQ_BASE + bit);
2224 +}
2225 +
2226 +static void
2227 +ar2315_misc_irq_dispatch(void)
2228 +{
2229 + unsigned int misc_intr = ar231x_read_reg(AR2315_ISR) &
2230 + ar231x_read_reg(AR2315_IMR);
2231 +
2232 + if (misc_intr & AR2315_ISR_SPI)
2233 + do_IRQ(AR531X_MISC_IRQ_SPI);
2234 + else if (misc_intr & AR2315_ISR_TIMER)
2235 + do_IRQ(AR531X_MISC_IRQ_TIMER);
2236 + else if (misc_intr & AR2315_ISR_AHB)
2237 + do_IRQ(AR531X_MISC_IRQ_AHB_PROC);
2238 + else if (misc_intr & AR2315_ISR_GPIO)
2239 + ar2315_gpio_irq();
2240 + else if (misc_intr & AR2315_ISR_UART0)
2241 + do_IRQ(AR531X_MISC_IRQ_UART0);
2242 + else if (misc_intr & AR2315_ISR_WD) {
2243 + ar231x_write_reg(AR2315_ISR, AR2315_ISR_WD);
2244 + do_IRQ(AR531X_MISC_IRQ_WATCHDOG);
2245 + } else
2246 + do_IRQ(AR531X_MISC_IRQ_NONE);
2247 +}
2248 +
2249 +/*
2250 + * Called when an interrupt is received, this function
2251 + * determines exactly which interrupt it was, and it
2252 + * invokes the appropriate handler.
2253 + *
2254 + * Implicitly, we also define interrupt priority by
2255 + * choosing which to dispatch first.
2256 + */
2257 +static asmlinkage void
2258 +ar2315_irq_dispatch(void)
2259 +{
2260 + int pending = read_c0_status() & read_c0_cause();
2261 +
2262 + if (pending & CAUSEF_IP3)
2263 + do_IRQ(AR2315_IRQ_WLAN0_INTRS);
2264 + else if (pending & CAUSEF_IP4)
2265 + do_IRQ(AR2315_IRQ_ENET0_INTRS);
2266 + else if (pending & CAUSEF_IP2)
2267 + ar2315_misc_irq_dispatch();
2268 + else if (pending & CAUSEF_IP7)
2269 + do_IRQ(AR531X_IRQ_CPU_CLOCK);
2270 +}
2271 +
2272 +static void ar2315_set_gpiointmask(int gpio, int level)
2273 +{
2274 + u32 reg;
2275 +
2276 + reg = ar231x_read_reg(AR2315_GPIO_INT);
2277 + reg &= ~(AR2315_GPIO_INT_M | AR2315_GPIO_INT_LVL_M);
2278 + reg |= gpio | AR2315_GPIO_INT_LVL(level);
2279 + ar231x_write_reg(AR2315_GPIO_INT, reg);
2280 +}
2281 +
2282 +static void ar2315_gpio_irq_unmask(struct irq_data *d)
2283 +{
2284 + unsigned int gpio = d->irq - AR531X_GPIO_IRQ_BASE;
2285 +
2286 + /* Enable interrupt with edge detection */
2287 + if ((ar231x_read_reg(AR2315_GPIO_CR) & AR2315_GPIO_CR_M(gpio)) !=
2288 + AR2315_GPIO_CR_I(gpio))
2289 + return;
2290 +
2291 + gpiointmask |= (1 << gpio);
2292 + ar2315_set_gpiointmask(gpio, 3);
2293 +}
2294 +
2295 +static void ar2315_gpio_irq_mask(struct irq_data *d)
2296 +{
2297 + unsigned int gpio = d->irq - AR531X_GPIO_IRQ_BASE;
2298 +
2299 + /* Disable interrupt */
2300 + gpiointmask &= ~(1 << gpio);
2301 + ar2315_set_gpiointmask(gpio, 0);
2302 +}
2303 +
2304 +static struct irq_chip ar2315_gpio_irq_chip = {
2305 + .name = "AR2315-GPIO",
2306 + .irq_unmask = ar2315_gpio_irq_unmask,
2307 + .irq_mask = ar2315_gpio_irq_mask,
2308 +};
2309 +
2310 +static void
2311 +ar2315_misc_irq_unmask(struct irq_data *d)
2312 +{
2313 + unsigned int imr;
2314 +
2315 + imr = ar231x_read_reg(AR2315_IMR);
2316 + switch (d->irq) {
2317 + case AR531X_MISC_IRQ_SPI:
2318 + imr |= AR2315_ISR_SPI;
2319 + break;
2320 + case AR531X_MISC_IRQ_TIMER:
2321 + imr |= AR2315_ISR_TIMER;
2322 + break;
2323 + case AR531X_MISC_IRQ_AHB_PROC:
2324 + imr |= AR2315_ISR_AHB;
2325 + break;
2326 + case AR531X_MISC_IRQ_GPIO:
2327 + imr |= AR2315_ISR_GPIO;
2328 + break;
2329 + case AR531X_MISC_IRQ_UART0:
2330 + imr |= AR2315_ISR_UART0;
2331 + break;
2332 + case AR531X_MISC_IRQ_WATCHDOG:
2333 + imr |= AR2315_ISR_WD;
2334 + break;
2335 + default:
2336 + break;
2337 + }
2338 + ar231x_write_reg(AR2315_IMR, imr);
2339 +}
2340 +
2341 +static void
2342 +ar2315_misc_irq_mask(struct irq_data *d)
2343 +{
2344 + unsigned int imr;
2345 +
2346 + imr = ar231x_read_reg(AR2315_IMR);
2347 + switch (d->irq) {
2348 + case AR531X_MISC_IRQ_SPI:
2349 + imr &= ~AR2315_ISR_SPI;
2350 + break;
2351 + case AR531X_MISC_IRQ_TIMER:
2352 + imr &= ~AR2315_ISR_TIMER;
2353 + break;
2354 + case AR531X_MISC_IRQ_AHB_PROC:
2355 + imr &= ~AR2315_ISR_AHB;
2356 + break;
2357 + case AR531X_MISC_IRQ_GPIO:
2358 + imr &= ~AR2315_ISR_GPIO;
2359 + break;
2360 + case AR531X_MISC_IRQ_UART0:
2361 + imr &= ~AR2315_ISR_UART0;
2362 + break;
2363 + case AR531X_MISC_IRQ_WATCHDOG:
2364 + imr &= ~AR2315_ISR_WD;
2365 + break;
2366 + default:
2367 + break;
2368 + }
2369 + ar231x_write_reg(AR2315_IMR, imr);
2370 +}
2371 +
2372 +static struct irq_chip ar2315_misc_irq_chip = {
2373 + .name = "AR2315-MISC",
2374 + .irq_unmask = ar2315_misc_irq_unmask,
2375 + .irq_mask = ar2315_misc_irq_mask,
2376 +};
2377 +
2378 +static irqreturn_t ar2315_ahb_proc_handler(int cpl, void *dev_id)
2379 +{
2380 + ar231x_write_reg(AR2315_AHB_ERR0, AHB_ERROR_DET);
2381 + ar231x_read_reg(AR2315_AHB_ERR1);
2382 +
2383 + pr_emerg("AHB fatal error\n");
2384 + machine_restart("AHB error"); /* Catastrophic failure */
2385 +
2386 + return IRQ_HANDLED;
2387 +}
2388 +
2389 +static struct irqaction ar2315_ahb_proc_interrupt = {
2390 + .handler = ar2315_ahb_proc_handler,
2391 + .name = "ar2315_ahb_proc_interrupt",
2392 +};
2393 +
2394 +static struct irqaction cascade = {
2395 + .handler = no_action,
2396 + .name = "cascade",
2397 +};
2398 +
2399 +void
2400 +ar2315_irq_init(void)
2401 +{
2402 + int i;
2403 +
2404 + if (!is_2315())
2405 + return;
2406 +
2407 + ar231x_irq_dispatch = ar2315_irq_dispatch;
2408 + gpiointval = ar231x_read_reg(AR2315_GPIO_DI);
2409 + for (i = 0; i < AR531X_MISC_IRQ_COUNT; i++) {
2410 + int irq = AR531X_MISC_IRQ_BASE + i;
2411 + irq_set_chip_and_handler(irq, &ar2315_misc_irq_chip,
2412 + handle_level_irq);
2413 + }
2414 + for (i = 0; i < AR531X_GPIO_IRQ_COUNT; i++) {
2415 + int irq = AR531X_GPIO_IRQ_BASE + i;
2416 + irq_set_chip_and_handler(irq, &ar2315_gpio_irq_chip,
2417 + handle_level_irq);
2418 + }
2419 + setup_irq(AR531X_MISC_IRQ_GPIO, &cascade);
2420 + setup_irq(AR531X_MISC_IRQ_AHB_PROC, &ar2315_ahb_proc_interrupt);
2421 + setup_irq(AR2315_IRQ_MISC_INTRS, &cascade);
2422 +}
2423 +
2424 +static u32
2425 +ar2315_gpio_set_output(u32 mask, u32 val)
2426 +{
2427 + u32 reg;
2428 +
2429 + reg = ar231x_read_reg(AR2315_GPIO_CR);
2430 + reg &= ~mask;
2431 + reg |= val;
2432 + ar231x_write_reg(AR2315_GPIO_CR, reg);
2433 + return reg;
2434 +}
2435 +
2436 +static u32
2437 +ar2315_gpio_get(u32 valid_mask)
2438 +{
2439 + u32 reg;
2440 + reg = ar231x_read_reg(AR2315_GPIO_DI);
2441 + reg &= valid_mask;
2442 + return reg;
2443 +}
2444 +
2445 +static u32
2446 +ar2315_gpio_set(u32 mask, u32 value)
2447 +{
2448 + u32 reg;
2449 + reg = ar231x_read_reg(AR2315_GPIO_DO);
2450 + reg &= ~mask;
2451 + reg |= value;
2452 + ar231x_write_reg(AR2315_GPIO_DO, reg);
2453 + return reg;
2454 +}
2455 +
2456 +/*
2457 + * gpiolib implementation. Original legacy mask based methods
2458 + * preserved for now.
2459 + */
2460 +static int
2461 +ar2315_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
2462 +{
2463 + struct ar231x_gpio_chip *gpch =
2464 + container_of(chip, struct ar231x_gpio_chip, chip);
2465 + u32 mask = 1 << gpio;
2466 + u32 rett;
2467 + if (!(gpch->valid_mask & mask))
2468 + return 0;
2469 + rett = ar2315_gpio_get(gpch->valid_mask); /* legacy code */
2470 + return !!(rett & mask);
2471 +}
2472 +
2473 +static void
2474 +ar2315_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
2475 +{
2476 + struct ar231x_gpio_chip *gpch =
2477 + container_of(chip, struct ar231x_gpio_chip, chip);
2478 + u32 mask = 1 << gpio;
2479 + if (!(gpch->valid_mask & mask))
2480 + return;
2481 + ar2315_gpio_set(mask, (!!value) * mask); /* legacy */
2482 +}
2483 +
2484 +static int
2485 +ar2315_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
2486 +{
2487 + struct ar231x_gpio_chip *gpch =
2488 + container_of(chip, struct ar231x_gpio_chip, chip);
2489 + u32 mask = 1 << gpio;
2490 + if (!(gpch->valid_mask & mask))
2491 + return -ENXIO;
2492 + ar2315_gpio_set_output(mask, 0); /* legacy */
2493 + return 0;
2494 +}
2495 +
2496 +static int
2497 +ar2315_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
2498 +{
2499 + struct ar231x_gpio_chip *gpch =
2500 + container_of(chip, struct ar231x_gpio_chip, chip);
2501 + u32 mask = 1 << gpio;
2502 + if (!(gpch->valid_mask & mask))
2503 + return -ENXIO;
2504 + ar2315_gpio_set_output(mask, mask); /* both legacy */
2505 + ar2315_gpio_set(mask, (!!value) * mask);
2506 + return 0;
2507 +}
2508 +
2509 +static struct ar231x_gpio_chip ar2315_gpio_chip = {
2510 + .valid_mask = (1 << 22) - 1,
2511 + .chip = {
2512 + .label = "ar2315-gpio",
2513 + .direction_input = ar2315_gpio_direction_input,
2514 + .direction_output = ar2315_gpio_direction_output,
2515 + .set = ar2315_gpio_set_value,
2516 + .get = ar2315_gpio_get_value,
2517 + .base = 0,
2518 + .ngpio = AR531X_GPIO_IRQ_COUNT, /* 22 */
2519 + }
2520 +};
2521 +
2522 +/* end of gpiolib */
2523 +
2524 +static void ar2315_device_reset_set(u32 mask)
2525 +{
2526 + u32 val;
2527 +
2528 + val = ar231x_read_reg(AR2315_RESET);
2529 + ar231x_write_reg(AR2315_RESET, val | mask);
2530 +}
2531 +
2532 +static void ar2315_device_reset_clear(u32 mask)
2533 +{
2534 + u32 val;
2535 +
2536 + val = ar231x_read_reg(AR2315_RESET);
2537 + ar231x_write_reg(AR2315_RESET, val & ~mask);
2538 +}
2539 +
2540 +static struct ar231x_eth ar2315_eth_data = {
2541 + .reset_set = ar2315_device_reset_set,
2542 + .reset_clear = ar2315_device_reset_clear,
2543 + .reset_mac = AR2315_RESET_ENET0,
2544 + .reset_phy = AR2315_RESET_EPHY0,
2545 + .phy_base = KSEG1ADDR(AR2315_ENET0),
2546 + .config = &ar231x_board,
2547 +};
2548 +
2549 +static struct resource ar2315_spiflash_res[] = {
2550 + {
2551 + .name = "spiflash_read",
2552 + .flags = IORESOURCE_MEM,
2553 + .start = AR2315_SPI_READ,
2554 + .end = AR2315_SPI_READ + 0x1000000 - 1,
2555 + },
2556 + {
2557 + .name = "spiflash_mmr",
2558 + .flags = IORESOURCE_MEM,
2559 + .start = AR2315_SPI_MMR,
2560 + .end = AR2315_SPI_MMR + 12 - 1,
2561 + },
2562 +};
2563 +
2564 +static struct platform_device ar2315_spiflash = {
2565 + .id = 0,
2566 + .name = "ar2315-spiflash",
2567 + .resource = ar2315_spiflash_res,
2568 + .num_resources = ARRAY_SIZE(ar2315_spiflash_res)
2569 +};
2570 +
2571 +static struct resource ar2315_wdt_res[] = {
2572 + {
2573 + .flags = IORESOURCE_MEM,
2574 + .start = AR2315_WD,
2575 + .end = AR2315_WD + 8 - 1,
2576 + },
2577 + {
2578 + .flags = IORESOURCE_IRQ,
2579 + .start = AR531X_MISC_IRQ_WATCHDOG,
2580 + .end = AR531X_MISC_IRQ_WATCHDOG,
2581 + }
2582 +};
2583 +
2584 +static struct platform_device ar2315_wdt = {
2585 + .id = 0,
2586 + .name = "ar2315-wdt",
2587 + .resource = ar2315_wdt_res,
2588 + .num_resources = ARRAY_SIZE(ar2315_wdt_res)
2589 +};
2590 +
2591 +/*
2592 + * NB: We use mapping size that is larger than the actual flash size,
2593 + * but this shouldn't be a problem here, because the flash will simply
2594 + * be mapped multiple times.
2595 + */
2596 +static u8 __init *ar2315_flash_limit(void)
2597 +{
2598 + return (u8 *)KSEG1ADDR(ar2315_spiflash_res[0].end + 1);
2599 +}
2600 +
2601 +#ifdef CONFIG_LEDS_GPIO
2602 +static struct gpio_led ar2315_leds[6];
2603 +static struct gpio_led_platform_data ar2315_led_data = {
2604 + .leds = (void *)ar2315_leds,
2605 +};
2606 +
2607 +static struct platform_device ar2315_gpio_leds = {
2608 + .name = "leds-gpio",
2609 + .id = -1,
2610 + .dev = {
2611 + .platform_data = (void *)&ar2315_led_data,
2612 + }
2613 +};
2614 +
2615 +static void __init
2616 +ar2315_init_gpio_leds(void)
2617 +{
2618 + static char led_names[6][6];
2619 + int i, led = 0;
2620 +
2621 + ar2315_led_data.num_leds = 0;
2622 + for (i = 1; i < 8; i++) {
2623 + if ((i == AR2315_RESET_GPIO) ||
2624 + (i == ar231x_board.config->reset_config_gpio))
2625 + continue;
2626 +
2627 + if (i == ar231x_board.config->sys_led_gpio)
2628 + strcpy(led_names[led], "wlan");
2629 + else
2630 + sprintf(led_names[led], "gpio%d", i);
2631 +
2632 + ar2315_leds[led].name = led_names[led];
2633 + ar2315_leds[led].gpio = i;
2634 + ar2315_leds[led].active_low = 0;
2635 + led++;
2636 + }
2637 + ar2315_led_data.num_leds = led;
2638 + platform_device_register(&ar2315_gpio_leds);
2639 +}
2640 +#else
2641 +static inline void ar2315_init_gpio_leds(void)
2642 +{
2643 +}
2644 +#endif
2645 +
2646 +int __init
2647 +ar2315_init_devices(void)
2648 +{
2649 + if (!is_2315())
2650 + return 0;
2651 +
2652 + /* Find board configuration */
2653 + ar231x_find_config(ar2315_flash_limit());
2654 + ar2315_eth_data.macaddr = ar231x_board.config->enet0_mac;
2655 +
2656 + ar2315_init_gpio_leds();
2657 + platform_device_register(&ar2315_wdt);
2658 + platform_device_register(&ar2315_spiflash);
2659 + ar231x_add_ethernet(0, KSEG1ADDR(AR2315_ENET0), AR2315_IRQ_ENET0_INTRS,
2660 + &ar2315_eth_data);
2661 + ar231x_add_wmac(0, AR2315_WLAN0, AR2315_IRQ_WLAN0_INTRS);
2662 +
2663 + return 0;
2664 +}
2665 +
2666 +static void
2667 +ar2315_restart(char *command)
2668 +{
2669 + void (*mips_reset_vec)(void) = (void *)0xbfc00000;
2670 +
2671 + local_irq_disable();
2672 +
2673 + /* try reset the system via reset control */
2674 + ar231x_write_reg(AR2315_COLD_RESET, AR2317_RESET_SYSTEM);
2675 +
2676 + /* Cold reset does not work on the AR2315/6, use the GPIO reset bits
2677 + * a workaround. Give it some time to attempt a gpio based hardware
2678 + * reset (atheros reference design workaround) */
2679 + gpio_request_one(AR2315_RESET_GPIO, GPIOF_OUT_INIT_LOW, "Reset");
2680 + mdelay(100);
2681 +
2682 + /* Some boards (e.g. Senao EOC-2610) don't implement the reset logic
2683 + * workaround. Attempt to jump to the mips reset location -
2684 + * the boot loader itself might be able to recover the system */
2685 + mips_reset_vec();
2686 +}
2687 +
2688 +
2689 +/*
2690 + * This table is indexed by bits 5..4 of the CLOCKCTL1 register
2691 + * to determine the predevisor value.
2692 + */
2693 +static int clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
2694 +static int pllc_divide_table[5] __initdata = { 2, 3, 4, 6, 3 };
2695 +
2696 +static unsigned int __init
2697 +ar2315_sys_clk(unsigned int clock_ctl)
2698 +{
2699 + unsigned int pllc_ctrl, cpu_div;
2700 + unsigned int pllc_out, refdiv, fdiv, divby2;
2701 + unsigned int clk_div;
2702 +
2703 + pllc_ctrl = ar231x_read_reg(AR2315_PLLC_CTL);
2704 + refdiv = (pllc_ctrl & PLLC_REF_DIV_M) >> PLLC_REF_DIV_S;
2705 + refdiv = clockctl1_predivide_table[refdiv];
2706 + fdiv = (pllc_ctrl & PLLC_FDBACK_DIV_M) >> PLLC_FDBACK_DIV_S;
2707 + divby2 = (pllc_ctrl & PLLC_ADD_FDBACK_DIV_M) >> PLLC_ADD_FDBACK_DIV_S;
2708 + divby2 += 1;
2709 + pllc_out = (40000000/refdiv)*(2*divby2)*fdiv;
2710 +
2711 + /* clkm input selected */
2712 + switch (clock_ctl & CPUCLK_CLK_SEL_M) {
2713 + case 0:
2714 + case 1:
2715 + clk_div = pllc_divide_table[(pllc_ctrl & PLLC_CLKM_DIV_M) >>
2716 + PLLC_CLKM_DIV_S];
2717 + break;
2718 + case 2:
2719 + clk_div = pllc_divide_table[(pllc_ctrl & PLLC_CLKC_DIV_M) >>
2720 + PLLC_CLKC_DIV_S];
2721 + break;
2722 + default:
2723 + pllc_out = 40000000;
2724 + clk_div = 1;
2725 + break;
2726 + }
2727 +
2728 + cpu_div = (clock_ctl & CPUCLK_CLK_DIV_M) >> CPUCLK_CLK_DIV_S;
2729 + cpu_div = cpu_div * 2 ?: 1;
2730 +
2731 + return pllc_out / (clk_div * cpu_div);
2732 +}
2733 +
2734 +static inline unsigned int
2735 +ar2315_cpu_frequency(void)
2736 +{
2737 + return ar2315_sys_clk(ar231x_read_reg(AR2315_CPUCLK));
2738 +}
2739 +
2740 +static inline unsigned int
2741 +ar2315_apb_frequency(void)
2742 +{
2743 + return ar2315_sys_clk(ar231x_read_reg(AR2315_AMBACLK));
2744 +}
2745 +
2746 +void __init
2747 +ar2315_time_init(void)
2748 +{
2749 + if (!is_2315())
2750 + return;
2751 +
2752 + mips_hpt_frequency = ar2315_cpu_frequency() / 2;
2753 +}
2754 +
2755 +int __init
2756 +ar2315_gpio_init(void)
2757 +{
2758 + int ret;
2759 + struct ar231x_gpio_chip *gpch;
2760 + gpch = &ar2315_gpio_chip;
2761 + ret = gpiochip_add(&gpch->chip);
2762 + if (ret) {
2763 + pr_err("%s: failed to add gpiochip\n", gpch->chip.label);
2764 + return ret;
2765 + }
2766 + pr_info("%s: registered %d GPIOs\n", gpch->chip.label,
2767 + gpch->chip.ngpio);
2768 + return ret;
2769 +}
2770 +
2771 +
2772 +
2773 +void __init
2774 +ar2315_prom_init(void)
2775 +{
2776 + u32 memsize, memcfg, devid;
2777 +
2778 + if (!is_2315())
2779 + return;
2780 +
2781 + memcfg = ar231x_read_reg(AR2315_MEM_CFG);
2782 + memsize = 1 + ((memcfg & SDRAM_DATA_WIDTH_M) >> SDRAM_DATA_WIDTH_S);
2783 + memsize <<= 1 + ((memcfg & SDRAM_COL_WIDTH_M) >> SDRAM_COL_WIDTH_S);
2784 + memsize <<= 1 + ((memcfg & SDRAM_ROW_WIDTH_M) >> SDRAM_ROW_WIDTH_S);
2785 + memsize <<= 3;
2786 + add_memory_region(0, memsize, BOOT_MEM_RAM);
2787 +
2788 + /* Detect the hardware based on the device ID */
2789 + devid = ar231x_read_reg(AR2315_SREV) & AR2315_REV_CHIP;
2790 + switch (devid) {
2791 + case 0x90:
2792 + case 0x91:
2793 + ar231x_devtype = DEV_TYPE_AR2317;
2794 + break;
2795 + default:
2796 + ar231x_devtype = DEV_TYPE_AR2315;
2797 + break;
2798 + }
2799 + ar2315_gpio_init();
2800 + ar231x_board.devid = devid;
2801 +}
2802 +
2803 +void __init
2804 +ar2315_plat_setup(void)
2805 +{
2806 + u32 config;
2807 +
2808 + if (!is_2315())
2809 + return;
2810 +
2811 + /* Clear any lingering AHB errors */
2812 + config = read_c0_config();
2813 + write_c0_config(config & ~0x3);
2814 + ar231x_write_reg(AR2315_AHB_ERR0, AHB_ERROR_DET);
2815 + ar231x_read_reg(AR2315_AHB_ERR1);
2816 + ar231x_write_reg(AR2315_WDC, AR2315_WDC_IGNORE_EXPIRATION);
2817 +
2818 + _machine_restart = ar2315_restart;
2819 + ar231x_serial_setup(KSEG1ADDR(AR2315_UART0), AR531X_MISC_IRQ_UART0,
2820 + ar2315_apb_frequency());
2821 +}
2822 --- /dev/null
2823 +++ b/arch/mips/ar231x/ar2315.h
2824 @@ -0,0 +1,37 @@
2825 +#ifndef __AR2315_H
2826 +#define __AR2315_H
2827 +
2828 +#ifdef CONFIG_ATHEROS_AR2315
2829 +
2830 +extern void ar2315_irq_init(void);
2831 +extern int ar2315_init_devices(void);
2832 +extern void ar2315_prom_init(void);
2833 +extern void ar2315_plat_setup(void);
2834 +extern void ar2315_time_init(void);
2835 +
2836 +#else
2837 +
2838 +static inline void ar2315_irq_init(void)
2839 +{
2840 +}
2841 +
2842 +static inline int ar2315_init_devices(void)
2843 +{
2844 + return 0;
2845 +}
2846 +
2847 +static inline void ar2315_prom_init(void)
2848 +{
2849 +}
2850 +
2851 +static inline void ar2315_plat_setup(void)
2852 +{
2853 +}
2854 +
2855 +static inline void ar2315_time_init(void)
2856 +{
2857 +}
2858 +
2859 +#endif
2860 +
2861 +#endif
2862 --- /dev/null
2863 +++ b/arch/mips/ar231x/ar5312.h
2864 @@ -0,0 +1,38 @@
2865 +#ifndef __AR5312_H
2866 +#define __AR5312_H
2867 +
2868 +#ifdef CONFIG_ATHEROS_AR5312
2869 +
2870 +extern void ar5312_irq_init(void);
2871 +extern int ar5312_init_devices(void);
2872 +extern void ar5312_prom_init(void);
2873 +extern void ar5312_plat_setup(void);
2874 +extern void ar5312_time_init(void);
2875 +extern void ar5312_time_init(void);
2876 +
2877 +#else
2878 +
2879 +static inline void ar5312_irq_init(void)
2880 +{
2881 +}
2882 +
2883 +static inline int ar5312_init_devices(void)
2884 +{
2885 + return 0;
2886 +}
2887 +
2888 +static inline void ar5312_prom_init(void)
2889 +{
2890 +}
2891 +
2892 +static inline void ar5312_plat_setup(void)
2893 +{
2894 +}
2895 +
2896 +static inline void ar5312_time_init(void)
2897 +{
2898 +}
2899 +
2900 +#endif
2901 +
2902 +#endif
2903 --- /dev/null
2904 +++ b/arch/mips/include/asm/mach-ar231x/ar231x.h
2905 @@ -0,0 +1,57 @@
2906 +#ifndef __AR531X_H
2907 +#define __AR531X_H
2908 +
2909 +#include <linux/types.h>
2910 +#include <linux/io.h>
2911 +
2912 +#define AR531X_MISC_IRQ_BASE 0x20
2913 +#define AR531X_GPIO_IRQ_BASE 0x30
2914 +
2915 +/* Software's idea of interrupts handled by "CPU Interrupt Controller" */
2916 +#define AR531X_IRQ_NONE (MIPS_CPU_IRQ_BASE+0)
2917 +#define AR531X_IRQ_CPU_CLOCK (MIPS_CPU_IRQ_BASE+7) /* C0_CAUSE: 0x8000 */
2918 +
2919 +/* Miscellaneous interrupts, which share IP6 */
2920 +#define AR531X_MISC_IRQ_NONE (AR531X_MISC_IRQ_BASE+0)
2921 +#define AR531X_MISC_IRQ_TIMER (AR531X_MISC_IRQ_BASE+1)
2922 +#define AR531X_MISC_IRQ_AHB_PROC (AR531X_MISC_IRQ_BASE+2)
2923 +#define AR531X_MISC_IRQ_AHB_DMA (AR531X_MISC_IRQ_BASE+3)
2924 +#define AR531X_MISC_IRQ_GPIO (AR531X_MISC_IRQ_BASE+4)
2925 +#define AR531X_MISC_IRQ_UART0 (AR531X_MISC_IRQ_BASE+5)
2926 +#define AR531X_MISC_IRQ_UART0_DMA (AR531X_MISC_IRQ_BASE+6)
2927 +#define AR531X_MISC_IRQ_WATCHDOG (AR531X_MISC_IRQ_BASE+7)
2928 +#define AR531X_MISC_IRQ_LOCAL (AR531X_MISC_IRQ_BASE+8)
2929 +#define AR531X_MISC_IRQ_SPI (AR531X_MISC_IRQ_BASE+9)
2930 +#define AR531X_MISC_IRQ_COUNT 10
2931 +
2932 +/* GPIO Interrupts [0..7], share AR531X_MISC_IRQ_GPIO */
2933 +#define AR531X_GPIO_IRQ_NONE (AR531X_GPIO_IRQ_BASE+0)
2934 +#define AR531X_GPIO_IRQ(n) (AR531X_GPIO_IRQ_BASE+n)
2935 +#define AR531X_GPIO_IRQ_COUNT 22
2936 +
2937 +static inline u32
2938 +ar231x_read_reg(u32 reg)
2939 +{
2940 + return __raw_readl((void __iomem *)KSEG1ADDR(reg));
2941 +}
2942 +
2943 +static inline void
2944 +ar231x_write_reg(u32 reg, u32 val)
2945 +{
2946 + __raw_writel(val, (void __iomem *)KSEG1ADDR(reg));
2947 +}
2948 +
2949 +static inline u32
2950 +ar231x_mask_reg(u32 reg, u32 mask, u32 val)
2951 +{
2952 + u32 ret;
2953 +
2954 + ret = ar231x_read_reg(reg);
2955 + ret &= ~mask;
2956 + ret |= val;
2957 + ar231x_write_reg(reg, ret);
2958 +
2959 + return ret;
2960 +}
2961 +
2962 +#endif
2963 --- /dev/null
2964 +++ b/arch/mips/ar231x/devices.h
2965 @@ -0,0 +1,42 @@
2966 +#ifndef __AR231X_DEVICES_H
2967 +#define __AR231X_DEVICES_H
2968 +#include <linux/gpio.h>
2969 +
2970 +enum {
2971 + /* handled by ar5312.c */
2972 + DEV_TYPE_AR2312,
2973 + DEV_TYPE_AR2313,
2974 + DEV_TYPE_AR5312,
2975 +
2976 + /* handled by ar2315.c */
2977 + DEV_TYPE_AR2315,
2978 + DEV_TYPE_AR2316,
2979 + DEV_TYPE_AR2317,
2980 +
2981 + DEV_TYPE_UNKNOWN
2982 +};
2983 +
2984 +extern int ar231x_devtype;
2985 +extern struct ar231x_board_config ar231x_board;
2986 +extern asmlinkage void (*ar231x_irq_dispatch)(void);
2987 +
2988 +extern int ar231x_find_config(u8 *flash_limit);
2989 +extern void ar231x_serial_setup(u32 mapbase, int irq, unsigned int uartclk);
2990 +extern int ar231x_add_wmac(int nr, u32 base, int irq);
2991 +extern int ar231x_add_ethernet(int nr, u32 base, int irq, void *pdata);
2992 +
2993 +static inline bool is_2315(void)
2994 +{
2995 + return (current_cpu_data.cputype == CPU_4KEC);
2996 +}
2997 +
2998 +static inline bool is_5312(void)
2999 +{
3000 + return !is_2315();
3001 +}
3002 +
3003 +struct ar231x_gpio_chip {
3004 + u32 valid_mask;
3005 + struct gpio_chip chip;
3006 +};
3007 +#endif
3008 --- /dev/null
3009 +++ b/arch/mips/ar231x/devices.c
3010 @@ -0,0 +1,168 @@
3011 +#include <linux/kernel.h>
3012 +#include <linux/init.h>
3013 +#include <linux/serial.h>
3014 +#include <linux/serial_core.h>
3015 +#include <linux/serial_8250.h>
3016 +#include <linux/platform_device.h>
3017 +#include <ar231x_platform.h>
3018 +#include <ar231x.h>
3019 +#include "devices.h"
3020 +#include "ar5312.h"
3021 +#include "ar2315.h"
3022 +
3023 +struct ar231x_board_config ar231x_board;
3024 +int ar231x_devtype = DEV_TYPE_UNKNOWN;
3025 +
3026 +static struct resource ar231x_eth0_res[] = {
3027 + {
3028 + .name = "eth0_membase",
3029 + .flags = IORESOURCE_MEM,
3030 + },
3031 + {
3032 + .name = "eth0_irq",
3033 + .flags = IORESOURCE_IRQ,
3034 + }
3035 +};
3036 +
3037 +static struct resource ar231x_eth1_res[] = {
3038 + {
3039 + .name = "eth1_membase",
3040 + .flags = IORESOURCE_MEM,
3041 + },
3042 + {
3043 + .name = "eth1_irq",
3044 + .flags = IORESOURCE_IRQ,
3045 + }
3046 +};
3047 +
3048 +static struct platform_device ar231x_eth[] = {
3049 + {
3050 + .id = 0,
3051 + .name = "ar231x-eth",
3052 + .resource = ar231x_eth0_res,
3053 + .num_resources = ARRAY_SIZE(ar231x_eth0_res)
3054 + },
3055 + {
3056 + .id = 1,
3057 + .name = "ar231x-eth",
3058 + .resource = ar231x_eth1_res,
3059 + .num_resources = ARRAY_SIZE(ar231x_eth1_res)
3060 + }
3061 +};
3062 +
3063 +static struct resource ar231x_wmac0_res[] = {
3064 + {
3065 + .name = "wmac0_membase",
3066 + .flags = IORESOURCE_MEM,
3067 + },
3068 + {
3069 + .name = "wmac0_irq",
3070 + .flags = IORESOURCE_IRQ,
3071 + }
3072 +};
3073 +
3074 +static struct resource ar231x_wmac1_res[] = {
3075 + {
3076 + .name = "wmac1_membase",
3077 + .flags = IORESOURCE_MEM,
3078 + },
3079 + {
3080 + .name = "wmac1_irq",
3081 + .flags = IORESOURCE_IRQ,
3082 + }
3083 +};
3084 +
3085 +
3086 +static struct platform_device ar231x_wmac[] = {
3087 + {
3088 + .id = 0,
3089 + .name = "ar231x-wmac",
3090 + .resource = ar231x_wmac0_res,
3091 + .num_resources = ARRAY_SIZE(ar231x_wmac0_res),
3092 + .dev.platform_data = &ar231x_board,
3093 + },
3094 + {
3095 + .id = 1,
3096 + .name = "ar231x-wmac",
3097 + .resource = ar231x_wmac1_res,
3098 + .num_resources = ARRAY_SIZE(ar231x_wmac1_res),
3099 + .dev.platform_data = &ar231x_board,
3100 + },
3101 +};
3102 +
3103 +static const char * const devtype_strings[] = {
3104 + [DEV_TYPE_AR5312] = "Atheros AR5312",
3105 + [DEV_TYPE_AR2312] = "Atheros AR2312",
3106 + [DEV_TYPE_AR2313] = "Atheros AR2313",
3107 + [DEV_TYPE_AR2315] = "Atheros AR2315",
3108 + [DEV_TYPE_AR2316] = "Atheros AR2316",
3109 + [DEV_TYPE_AR2317] = "Atheros AR2317",
3110 + [DEV_TYPE_UNKNOWN] = "Atheros (unknown)",
3111 +};
3112 +
3113 +const char *get_system_type(void)
3114 +{
3115 + if ((ar231x_devtype >= ARRAY_SIZE(devtype_strings)) ||
3116 + !devtype_strings[ar231x_devtype])
3117 + return devtype_strings[DEV_TYPE_UNKNOWN];
3118 + return devtype_strings[ar231x_devtype];
3119 +}
3120 +
3121 +
3122 +int __init
3123 +ar231x_add_ethernet(int nr, u32 base, int irq, void *pdata)
3124 +{
3125 + struct resource *res;
3126 +
3127 + ar231x_eth[nr].dev.platform_data = pdata;
3128 + res = &ar231x_eth[nr].resource[0];
3129 + res->start = base;
3130 + res->end = base + 0x2000 - 1;
3131 + res++;
3132 + res->start = irq;
3133 + res->end = irq;
3134 + return platform_device_register(&ar231x_eth[nr]);
3135 +}
3136 +
3137 +void __init
3138 +ar231x_serial_setup(u32 mapbase, int irq, unsigned int uartclk)
3139 +{
3140 + struct uart_port s;
3141 +
3142 + memset(&s, 0, sizeof(s));
3143 +
3144 + s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST;
3145 + s.iotype = UPIO_MEM;
3146 + s.irq = irq;
3147 + s.regshift = 2;
3148 + s.mapbase = mapbase;
3149 + s.uartclk = uartclk;
3150 + s.membase = (void __iomem *)s.mapbase;
3151 +
3152 + early_serial_setup(&s);
3153 +}
3154 +
3155 +int __init
3156 +ar231x_add_wmac(int nr, u32 base, int irq)
3157 +{
3158 + struct resource *res;
3159 +
3160 + ar231x_wmac[nr].dev.platform_data = &ar231x_board;
3161 + res = &ar231x_wmac[nr].resource[0];
3162 + res->start = base;
3163 + res->end = base + 0x10000 - 1;
3164 + res++;
3165 + res->start = irq;
3166 + res->end = irq;
3167 + return platform_device_register(&ar231x_wmac[nr]);
3168 +}
3169 +
3170 +static int __init ar231x_register_devices(void)
3171 +{
3172 + ar5312_init_devices();
3173 + ar2315_init_devices();
3174 +
3175 + return 0;
3176 +}
3177 +
3178 +device_initcall(ar231x_register_devices);
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