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atheros: convert AR5312 GPIO code to platform driver
[openwrt/svn-archive/archive.git] / target / linux / atheros / patches-3.14 / 100-board.patch
1 --- a/arch/mips/Kconfig
2 +++ b/arch/mips/Kconfig
3 @@ -144,6 +144,19 @@ config BCM63XX
4 help
5 Support for BCM63XX based boards
6
7 +config ATHEROS_AR231X
8 + bool "Atheros 231x/531x SoC support"
9 + select CEVT_R4K
10 + select CSRC_R4K
11 + select DMA_NONCOHERENT
12 + select IRQ_CPU
13 + select SYS_HAS_CPU_MIPS32_R1
14 + select SYS_SUPPORTS_BIG_ENDIAN
15 + select SYS_SUPPORTS_32BIT_KERNEL
16 + select ARCH_REQUIRE_GPIOLIB
17 + help
18 + Support for AR231x and AR531x based boards
19 +
20 config MIPS_COBALT
21 bool "Cobalt Server"
22 select CEVT_R4K
23 @@ -795,6 +808,7 @@ config NLM_XLP_BOARD
24
25 endchoice
26
27 +source "arch/mips/ar231x/Kconfig"
28 source "arch/mips/alchemy/Kconfig"
29 source "arch/mips/ath79/Kconfig"
30 source "arch/mips/bcm47xx/Kconfig"
31 --- a/arch/mips/Kbuild.platforms
32 +++ b/arch/mips/Kbuild.platforms
33 @@ -6,6 +6,7 @@ platforms += ath79
34 platforms += bcm47xx
35 platforms += bcm63xx
36 platforms += cavium-octeon
37 +platforms += ar231x
38 platforms += cobalt
39 platforms += dec
40 platforms += emma
41 --- /dev/null
42 +++ b/arch/mips/ar231x/Platform
43 @@ -0,0 +1,6 @@
44 +#
45 +# Atheros AR531X/AR231X WiSoC
46 +#
47 +platform-$(CONFIG_ATHEROS_AR231X) += ar231x/
48 +cflags-$(CONFIG_ATHEROS_AR231X) += -I$(srctree)/arch/mips/include/asm/mach-ar231x
49 +load-$(CONFIG_ATHEROS_AR231X) += 0xffffffff80041000
50 --- /dev/null
51 +++ b/arch/mips/ar231x/Kconfig
52 @@ -0,0 +1,9 @@
53 +config SOC_AR5312
54 + bool "Atheros 5312/2312+ support"
55 + depends on ATHEROS_AR231X
56 + default y
57 +
58 +config SOC_AR2315
59 + bool "Atheros 2315+ support"
60 + depends on ATHEROS_AR231X
61 + default y
62 --- /dev/null
63 +++ b/arch/mips/ar231x/Makefile
64 @@ -0,0 +1,13 @@
65 +#
66 +# This file is subject to the terms and conditions of the GNU General Public
67 +# License. See the file "COPYING" in the main directory of this archive
68 +# for more details.
69 +#
70 +# Copyright (C) 2006 FON Technology, SL.
71 +# Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
72 +# Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
73 +#
74 +
75 +obj-y += board.o prom.o devices.o
76 +obj-$(CONFIG_SOC_AR5312) += ar5312.o
77 +obj-$(CONFIG_SOC_AR2315) += ar2315.o
78 --- /dev/null
79 +++ b/arch/mips/ar231x/board.c
80 @@ -0,0 +1,229 @@
81 +/*
82 + * This file is subject to the terms and conditions of the GNU General Public
83 + * License. See the file "COPYING" in the main directory of this archive
84 + * for more details.
85 + *
86 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
87 + * Copyright (C) 2006 FON Technology, SL.
88 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
89 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
90 + */
91 +
92 +#include <generated/autoconf.h>
93 +#include <linux/init.h>
94 +#include <linux/module.h>
95 +#include <linux/types.h>
96 +#include <linux/string.h>
97 +#include <linux/platform_device.h>
98 +#include <linux/kernel.h>
99 +#include <linux/random.h>
100 +#include <linux/etherdevice.h>
101 +#include <linux/irq.h>
102 +#include <linux/io.h>
103 +#include <asm/irq_cpu.h>
104 +#include <asm/reboot.h>
105 +#include <asm/bootinfo.h>
106 +#include <asm/time.h>
107 +
108 +#include <ar231x_platform.h>
109 +#include "devices.h"
110 +#include "ar5312.h"
111 +#include "ar2315.h"
112 +
113 +void (*ar231x_irq_dispatch)(void);
114 +
115 +static inline bool check_radio_magic(u8 *addr)
116 +{
117 + addr += 0x7a; /* offset for flash magic */
118 + return (addr[0] == 0x5a) && (addr[1] == 0xa5);
119 +}
120 +
121 +static inline bool check_notempty(u8 *addr)
122 +{
123 + return *(u32 *)addr != 0xffffffff;
124 +}
125 +
126 +static inline bool check_board_data(u8 *flash_limit, u8 *addr, bool broken)
127 +{
128 + /* config magic found */
129 + if (*((u32 *)addr) == AR231X_BD_MAGIC)
130 + return true;
131 +
132 + if (!broken)
133 + return false;
134 +
135 + if (check_radio_magic(addr + 0xf8))
136 + ar231x_board.radio = addr + 0xf8;
137 + if ((addr < flash_limit + 0x10000) &&
138 + check_radio_magic(addr + 0x10000))
139 + ar231x_board.radio = addr + 0x10000;
140 +
141 + if (ar231x_board.radio) {
142 + /* broken board data detected, use radio data to find the
143 + * offset, user will fix this */
144 + return true;
145 + }
146 +
147 + return false;
148 +}
149 +
150 +static u8 * __init find_board_config(u8 *flash_limit, bool broken)
151 +{
152 + u8 *addr;
153 + u8 *begin = flash_limit - 0x1000;
154 + u8 *end = flash_limit - 0x30000;
155 +
156 + for (addr = begin; addr >= end; addr -= 0x1000)
157 + if (check_board_data(flash_limit, addr, broken))
158 + return addr;
159 +
160 + return NULL;
161 +}
162 +
163 +static u8 * __init find_radio_config(u8 *flash_limit, u8 *bcfg)
164 +{
165 + u8 *rcfg, *begin, *end;
166 +
167 + /*
168 + * Now find the start of Radio Configuration data, using heuristics:
169 + * Search forward from Board Configuration data by 0x1000 bytes
170 + * at a time until we find non-0xffffffff.
171 + */
172 + begin = bcfg + 0x1000;
173 + end = flash_limit;
174 + for (rcfg = begin; rcfg < end; rcfg += 0x1000)
175 + if (check_notempty(rcfg) && check_radio_magic(rcfg))
176 + return rcfg;
177 +
178 + /* AR2316 relocates radio config to new location */
179 + begin = bcfg + 0xf8;
180 + end = flash_limit - 0x1000 + 0xf8;
181 + for (rcfg = begin; rcfg < end; rcfg += 0x1000)
182 + if (check_notempty(rcfg) && check_radio_magic(rcfg))
183 + return rcfg;
184 +
185 + pr_warn("WARNING: Could not find Radio Configuration data\n");
186 +
187 + return NULL;
188 +}
189 +
190 +int __init ar231x_find_config(u8 *flash_limit)
191 +{
192 + struct ar231x_boarddata *config;
193 + unsigned int rcfg_size;
194 + int broken_boarddata = 0;
195 + u8 *bcfg, *rcfg;
196 + u8 *board_data;
197 + u8 *radio_data;
198 + u8 *mac_addr;
199 + u32 offset;
200 +
201 + ar231x_board.config = NULL;
202 + ar231x_board.radio = NULL;
203 + /* Copy the board and radio data to RAM, because accessing the mapped
204 + * memory of the flash directly after booting is not safe */
205 +
206 + /* Try to find valid board and radio data */
207 + bcfg = find_board_config(flash_limit, false);
208 +
209 + /* If that fails, try to at least find valid radio data */
210 + if (!bcfg) {
211 + bcfg = find_board_config(flash_limit, true);
212 + broken_boarddata = 1;
213 + }
214 +
215 + if (!bcfg) {
216 + pr_warn("WARNING: No board configuration data found!\n");
217 + return -ENODEV;
218 + }
219 +
220 + board_data = kzalloc(BOARD_CONFIG_BUFSZ, GFP_KERNEL);
221 + ar231x_board.config = (struct ar231x_boarddata *)board_data;
222 + memcpy(board_data, bcfg, 0x100);
223 + if (broken_boarddata) {
224 + pr_warn("WARNING: broken board data detected\n");
225 + config = ar231x_board.config;
226 + if (is_zero_ether_addr(config->enet0_mac)) {
227 + pr_info("Fixing up empty mac addresses\n");
228 + config->reset_config_gpio = 0xffff;
229 + config->sys_led_gpio = 0xffff;
230 + random_ether_addr(config->wlan0_mac);
231 + config->wlan0_mac[0] &= ~0x06;
232 + random_ether_addr(config->enet0_mac);
233 + random_ether_addr(config->enet1_mac);
234 + }
235 + }
236 +
237 + /* Radio config starts 0x100 bytes after board config, regardless
238 + * of what the physical layout on the flash chip looks like */
239 +
240 + if (ar231x_board.radio)
241 + rcfg = (u8 *)ar231x_board.radio;
242 + else
243 + rcfg = find_radio_config(flash_limit, bcfg);
244 +
245 + if (!rcfg)
246 + return -ENODEV;
247 +
248 + radio_data = board_data + 0x100 + ((rcfg - bcfg) & 0xfff);
249 + ar231x_board.radio = radio_data;
250 + offset = radio_data - board_data;
251 + pr_info("Radio config found at offset 0x%x (0x%x)\n", rcfg - bcfg,
252 + offset);
253 + rcfg_size = BOARD_CONFIG_BUFSZ - offset;
254 + memcpy(radio_data, rcfg, rcfg_size);
255 +
256 + mac_addr = &radio_data[0x1d * 2];
257 + if (is_broadcast_ether_addr(mac_addr)) {
258 + pr_info("Radio MAC is blank; using board-data\n");
259 + ether_addr_copy(mac_addr, ar231x_board.config->wlan0_mac);
260 + }
261 +
262 + return 0;
263 +}
264 +
265 +static void ar231x_halt(void)
266 +{
267 + local_irq_disable();
268 + while (1)
269 + ;
270 +}
271 +
272 +void __init plat_mem_setup(void)
273 +{
274 + _machine_halt = ar231x_halt;
275 + pm_power_off = ar231x_halt;
276 +
277 + ar5312_plat_setup();
278 + ar2315_plat_setup();
279 +
280 + /* Disable data watchpoints */
281 + write_c0_watchlo0(0);
282 +}
283 +
284 +asmlinkage void plat_irq_dispatch(void)
285 +{
286 + ar231x_irq_dispatch();
287 +}
288 +
289 +void __init plat_time_init(void)
290 +{
291 + ar5312_time_init();
292 + ar2315_time_init();
293 +}
294 +
295 +unsigned int __cpuinit get_c0_compare_int(void)
296 +{
297 + return CP0_LEGACY_COMPARE_IRQ;
298 +}
299 +
300 +void __init arch_init_irq(void)
301 +{
302 + clear_c0_status(ST0_IM);
303 + mips_cpu_irq_init();
304 +
305 + /* Initialize interrupt controllers */
306 + ar5312_irq_init();
307 + ar2315_irq_init();
308 +}
309 +
310 --- /dev/null
311 +++ b/arch/mips/ar231x/prom.c
312 @@ -0,0 +1,37 @@
313 +/*
314 + * This file is subject to the terms and conditions of the GNU General Public
315 + * License. See the file "COPYING" in the main directory of this archive
316 + * for more details.
317 + *
318 + * Copyright MontaVista Software Inc
319 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
320 + * Copyright (C) 2006 FON Technology, SL.
321 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
322 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
323 + */
324 +
325 +/*
326 + * Prom setup file for ar231x
327 + */
328 +
329 +#include <linux/init.h>
330 +#include <generated/autoconf.h>
331 +#include <linux/kernel.h>
332 +#include <linux/string.h>
333 +#include <linux/mm.h>
334 +#include <linux/bootmem.h>
335 +
336 +#include <asm/bootinfo.h>
337 +#include <asm/addrspace.h>
338 +#include "ar5312.h"
339 +#include "ar2315.h"
340 +
341 +void __init prom_init(void)
342 +{
343 + ar5312_prom_init();
344 + ar2315_prom_init();
345 +}
346 +
347 +void __init prom_free_prom_memory(void)
348 +{
349 +}
350 --- /dev/null
351 +++ b/arch/mips/include/asm/mach-ar231x/ar231x_platform.h
352 @@ -0,0 +1,85 @@
353 +#ifndef __ASM_MACH_AR231X_PLATFORM_H
354 +#define __ASM_MACH_AR231X_PLATFORM_H
355 +
356 +#include <linux/etherdevice.h>
357 +
358 +/*
359 + * This is board-specific data that is stored in a "fixed" location in flash.
360 + * It is shared across operating systems, so it should not be changed lightly.
361 + * The main reason we need it is in order to extract the ethernet MAC
362 + * address(es).
363 + */
364 +struct ar231x_boarddata {
365 + u32 magic; /* board data is valid */
366 +#define AR231X_BD_MAGIC 0x35333131 /* "5311", for all 531x/231x platforms */
367 + u16 cksum; /* checksum (starting with BD_REV 2) */
368 + u16 rev; /* revision of this struct */
369 +#define BD_REV 4
370 + char board_name[64]; /* Name of board */
371 + u16 major; /* Board major number */
372 + u16 minor; /* Board minor number */
373 + u32 flags; /* Board configuration */
374 +#define BD_ENET0 0x00000001 /* ENET0 is stuffed */
375 +#define BD_ENET1 0x00000002 /* ENET1 is stuffed */
376 +#define BD_UART1 0x00000004 /* UART1 is stuffed */
377 +#define BD_UART0 0x00000008 /* UART0 is stuffed (dma) */
378 +#define BD_RSTFACTORY 0x00000010 /* Reset factory defaults stuffed */
379 +#define BD_SYSLED 0x00000020 /* System LED stuffed */
380 +#define BD_EXTUARTCLK 0x00000040 /* External UART clock */
381 +#define BD_CPUFREQ 0x00000080 /* cpu freq is valid in nvram */
382 +#define BD_SYSFREQ 0x00000100 /* sys freq is set in nvram */
383 +#define BD_WLAN0 0x00000200 /* Enable WLAN0 */
384 +#define BD_MEMCAP 0x00000400 /* CAP SDRAM @ mem_cap for testing */
385 +#define BD_DISWATCHDOG 0x00000800 /* disable system watchdog */
386 +#define BD_WLAN1 0x00001000 /* Enable WLAN1 (ar5212) */
387 +#define BD_ISCASPER 0x00002000 /* FLAG for AR2312 */
388 +#define BD_WLAN0_2G_EN 0x00004000 /* FLAG for radio0_2G */
389 +#define BD_WLAN0_5G_EN 0x00008000 /* FLAG for radio0_2G */
390 +#define BD_WLAN1_2G_EN 0x00020000 /* FLAG for radio0_2G */
391 +#define BD_WLAN1_5G_EN 0x00040000 /* FLAG for radio0_2G */
392 + u16 reset_config_gpio; /* Reset factory GPIO pin */
393 + u16 sys_led_gpio; /* System LED GPIO pin */
394 +
395 + u32 cpu_freq; /* CPU core frequency in Hz */
396 + u32 sys_freq; /* System frequency in Hz */
397 + u32 cnt_freq; /* Calculated C0_COUNT frequency */
398 +
399 + u8 wlan0_mac[ETH_ALEN];
400 + u8 enet0_mac[ETH_ALEN];
401 + u8 enet1_mac[ETH_ALEN];
402 +
403 + u16 pci_id; /* Pseudo PCIID for common code */
404 + u16 mem_cap; /* cap bank1 in MB */
405 +
406 + /* version 3 */
407 + u8 wlan1_mac[ETH_ALEN]; /* (ar5212) */
408 +};
409 +
410 +#define BOARD_CONFIG_BUFSZ 0x1000
411 +
412 +/*
413 + * Platform device information for the Wireless MAC
414 + */
415 +struct ar231x_board_config {
416 + u16 devid;
417 +
418 + /* board config data */
419 + struct ar231x_boarddata *config;
420 +
421 + /* radio calibration data */
422 + const char *radio;
423 +};
424 +
425 +/*
426 + * Platform device information for the Ethernet MAC
427 + */
428 +struct ar231x_eth {
429 + void (*reset_set)(u32);
430 + void (*reset_clear)(u32);
431 + u32 reset_mac;
432 + u32 reset_phy;
433 + struct ar231x_board_config *config;
434 + char *macaddr;
435 +};
436 +
437 +#endif /* __ASM_MACH_AR231X_PLATFORM_H */
438 --- /dev/null
439 +++ b/arch/mips/include/asm/mach-ar231x/cpu-feature-overrides.h
440 @@ -0,0 +1,84 @@
441 +/*
442 + * Atheros AR231x/AR531x SoC specific CPU feature overrides
443 + *
444 + * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
445 + *
446 + * This file was derived from: include/asm-mips/cpu-features.h
447 + * Copyright (C) 2003, 2004 Ralf Baechle
448 + * Copyright (C) 2004 Maciej W. Rozycki
449 + *
450 + * This program is free software; you can redistribute it and/or modify it
451 + * under the terms of the GNU General Public License version 2 as published
452 + * by the Free Software Foundation.
453 + *
454 + */
455 +#ifndef __ASM_MACH_AR231X_CPU_FEATURE_OVERRIDES_H
456 +#define __ASM_MACH_AR231X_CPU_FEATURE_OVERRIDES_H
457 +
458 +/*
459 + * The Atheros AR531x/AR231x SoCs have MIPS 4Kc/4KEc core.
460 + */
461 +#define cpu_has_tlb 1
462 +#define cpu_has_4kex 1
463 +#define cpu_has_3k_cache 0
464 +#define cpu_has_4k_cache 1
465 +#define cpu_has_tx39_cache 0
466 +#define cpu_has_sb1_cache 0
467 +#define cpu_has_fpu 0
468 +#define cpu_has_32fpr 0
469 +#define cpu_has_counter 1
470 +/* #define cpu_has_watch ? */
471 +/* #define cpu_has_divec ? */
472 +/* #define cpu_has_vce ? */
473 +/* #define cpu_has_cache_cdex_p ? */
474 +/* #define cpu_has_cache_cdex_s ? */
475 +/* #define cpu_has_prefetch ? */
476 +/* #define cpu_has_mcheck ? */
477 +#define cpu_has_ejtag 1
478 +
479 +#if !defined(CONFIG_SOC_AR5312)
480 +# define cpu_has_llsc 1
481 +#else
482 +/*
483 + * The MIPS 4Kc V0.9 core in the AR5312/AR2312 have problems with the
484 + * ll/sc instructions.
485 + */
486 +# define cpu_has_llsc 0
487 +#endif
488 +
489 +#define cpu_has_mips16 0
490 +#define cpu_has_mdmx 0
491 +#define cpu_has_mips3d 0
492 +#define cpu_has_smartmips 0
493 +
494 +/* #define cpu_has_vtag_icache ? */
495 +/* #define cpu_has_dc_aliases ? */
496 +/* #define cpu_has_ic_fills_f_dc ? */
497 +/* #define cpu_has_pindexed_dcache ? */
498 +
499 +/* #define cpu_icache_snoops_remote_store ? */
500 +
501 +#define cpu_has_mips32r1 1
502 +
503 +#if !defined(CONFIG_SOC_AR5312)
504 +# define cpu_has_mips32r2 1
505 +#endif
506 +
507 +#define cpu_has_mips64r1 0
508 +#define cpu_has_mips64r2 0
509 +
510 +#define cpu_has_dsp 0
511 +#define cpu_has_mipsmt 0
512 +
513 +/* #define cpu_has_nofpuex ? */
514 +#define cpu_has_64bits 0
515 +#define cpu_has_64bit_zero_reg 0
516 +#define cpu_has_64bit_gp_regs 0
517 +#define cpu_has_64bit_addresses 0
518 +
519 +/* #define cpu_has_inclusive_pcaches ? */
520 +
521 +/* #define cpu_dcache_line_size() ? */
522 +/* #define cpu_icache_line_size() ? */
523 +
524 +#endif /* __ASM_MACH_AR231X_CPU_FEATURE_OVERRIDES_H */
525 --- /dev/null
526 +++ b/arch/mips/include/asm/mach-ar231x/dma-coherence.h
527 @@ -0,0 +1,76 @@
528 +/*
529 + * This file is subject to the terms and conditions of the GNU General Public
530 + * License. See the file "COPYING" in the main directory of this archive
531 + * for more details.
532 + *
533 + * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
534 + * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
535 + *
536 + */
537 +#ifndef __ASM_MACH_AR231X_DMA_COHERENCE_H
538 +#define __ASM_MACH_AR231X_DMA_COHERENCE_H
539 +
540 +#include <linux/device.h>
541 +#include <ar2315_regs.h>
542 +
543 +static inline dma_addr_t ar231x_dev_offset(struct device *dev)
544 +{
545 +#ifdef CONFIG_PCI
546 + extern struct bus_type pci_bus_type;
547 +
548 + if (dev && dev->bus == &pci_bus_type)
549 + return AR2315_PCI_HOST_SDRAM_BASEADDR;
550 +#endif
551 + return 0;
552 +}
553 +
554 +static inline dma_addr_t
555 +plat_map_dma_mem(struct device *dev, void *addr, size_t size)
556 +{
557 + return virt_to_phys(addr) + ar231x_dev_offset(dev);
558 +}
559 +
560 +static inline dma_addr_t
561 +plat_map_dma_mem_page(struct device *dev, struct page *page)
562 +{
563 + return page_to_phys(page) + ar231x_dev_offset(dev);
564 +}
565 +
566 +static inline unsigned long
567 +plat_dma_addr_to_phys(struct device *dev, dma_addr_t dma_addr)
568 +{
569 + return dma_addr - ar231x_dev_offset(dev);
570 +}
571 +
572 +static inline void
573 +plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, size_t size,
574 + enum dma_data_direction direction)
575 +{
576 +}
577 +
578 +static inline int plat_dma_supported(struct device *dev, u64 mask)
579 +{
580 + return 1;
581 +}
582 +
583 +static inline void plat_extra_sync_for_device(struct device *dev)
584 +{
585 +}
586 +
587 +static inline int plat_dma_mapping_error(struct device *dev,
588 + dma_addr_t dma_addr)
589 +{
590 + return 0;
591 +}
592 +
593 +static inline int plat_device_is_coherent(struct device *dev)
594 +{
595 +#ifdef CONFIG_DMA_COHERENT
596 + return 1;
597 +#endif
598 +#ifdef CONFIG_DMA_NONCOHERENT
599 + return 0;
600 +#endif
601 +}
602 +
603 +#endif /* __ASM_MACH_AR231X_DMA_COHERENCE_H */
604 --- /dev/null
605 +++ b/arch/mips/include/asm/mach-ar231x/gpio.h
606 @@ -0,0 +1,16 @@
607 +#ifndef __ASM_MACH_AR231X_GPIO_H
608 +#define __ASM_MACH_AR231X_GPIO_H
609 +
610 +#include <asm-generic/gpio.h>
611 +
612 +#define gpio_get_value __gpio_get_value
613 +#define gpio_set_value __gpio_set_value
614 +#define gpio_cansleep __gpio_cansleep
615 +#define gpio_to_irq __gpio_to_irq
616 +
617 +static inline int irq_to_gpio(unsigned irq)
618 +{
619 + return -EINVAL;
620 +}
621 +
622 +#endif /* __ASM_MACH_AR231X_GPIO_H */
623 --- /dev/null
624 +++ b/arch/mips/include/asm/mach-ar231x/reset.h
625 @@ -0,0 +1,6 @@
626 +#ifndef __ASM_MACH_AR231X_RESET_H
627 +#define __ASM_MACH_AR231X_RESET_H
628 +
629 +void ar231x_disable_reset_button(void);
630 +
631 +#endif /* __ASM_MACH_AR231X_RESET_H */
632 --- /dev/null
633 +++ b/arch/mips/include/asm/mach-ar231x/war.h
634 @@ -0,0 +1,25 @@
635 +/*
636 + * This file is subject to the terms and conditions of the GNU General Public
637 + * License. See the file "COPYING" in the main directory of this archive
638 + * for more details.
639 + *
640 + * Copyright (C) 2008 Felix Fietkau <nbd@openwrt.org>
641 + */
642 +#ifndef __ASM_MACH_AR231X_WAR_H
643 +#define __ASM_MACH_AR231X_WAR_H
644 +
645 +#define R4600_V1_INDEX_ICACHEOP_WAR 0
646 +#define R4600_V1_HIT_CACHEOP_WAR 0
647 +#define R4600_V2_HIT_CACHEOP_WAR 0
648 +#define R5432_CP0_INTERRUPT_WAR 0
649 +#define BCM1250_M3_WAR 0
650 +#define SIBYTE_1956_WAR 0
651 +#define MIPS4K_ICACHE_REFILL_WAR 0
652 +#define MIPS_CACHE_SYNC_WAR 0
653 +#define TX49XX_ICACHE_INDEX_INV_WAR 0
654 +#define RM9000_CDEX_SMP_WAR 0
655 +#define ICACHE_REFILLS_WORKAROUND_WAR 0
656 +#define R10000_LLSC_WAR 0
657 +#define MIPS34K_MISSED_ITLB_WAR 0
658 +
659 +#endif /* __ASM_MACH_AR231X_WAR_H */
660 --- /dev/null
661 +++ b/arch/mips/include/asm/mach-ar231x/ar2315_regs.h
662 @@ -0,0 +1,630 @@
663 +/*
664 + * Register definitions for AR2315+
665 + *
666 + * This file is subject to the terms and conditions of the GNU General Public
667 + * License. See the file "COPYING" in the main directory of this archive
668 + * for more details.
669 + *
670 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
671 + * Copyright (C) 2006 FON Technology, SL.
672 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
673 + * Copyright (C) 2006-2008 Felix Fietkau <nbd@openwrt.org>
674 + */
675 +
676 +#ifndef __ASM_MACH_AR231X_AR2315_REGS_H
677 +#define __ASM_MACH_AR231X_AR2315_REGS_H
678 +
679 +/*
680 + * IRQs
681 + */
682 +#define AR2315_IRQ_MISC_INTRS (MIPS_CPU_IRQ_BASE+2) /* C0_CAUSE: 0x0400 */
683 +#define AR2315_IRQ_WLAN0_INTRS (MIPS_CPU_IRQ_BASE+3) /* C0_CAUSE: 0x0800 */
684 +#define AR2315_IRQ_ENET0_INTRS (MIPS_CPU_IRQ_BASE+4) /* C0_CAUSE: 0x1000 */
685 +#define AR2315_IRQ_LCBUS_PCI (MIPS_CPU_IRQ_BASE+5) /* C0_CAUSE: 0x2000 */
686 +#define AR2315_IRQ_WLAN0_POLL (MIPS_CPU_IRQ_BASE+6) /* C0_CAUSE: 0x4000 */
687 +
688 +/*
689 + * Miscellaneous interrupts, which share IP2.
690 + */
691 +#define AR2315_MISC_IRQ_UART0 (AR231X_MISC_IRQ_BASE+0)
692 +#define AR2315_MISC_IRQ_I2C_RSVD (AR231X_MISC_IRQ_BASE+1)
693 +#define AR2315_MISC_IRQ_SPI (AR231X_MISC_IRQ_BASE+2)
694 +#define AR2315_MISC_IRQ_AHB (AR231X_MISC_IRQ_BASE+3)
695 +#define AR2315_MISC_IRQ_APB (AR231X_MISC_IRQ_BASE+4)
696 +#define AR2315_MISC_IRQ_TIMER (AR231X_MISC_IRQ_BASE+5)
697 +#define AR2315_MISC_IRQ_GPIO (AR231X_MISC_IRQ_BASE+6)
698 +#define AR2315_MISC_IRQ_WATCHDOG (AR231X_MISC_IRQ_BASE+7)
699 +#define AR2315_MISC_IRQ_IR_RSVD (AR231X_MISC_IRQ_BASE+8)
700 +#define AR2315_MISC_IRQ_COUNT 9
701 +
702 +/*
703 + * PCI interrupts, which share IP5
704 + * Keep ordered according to AR2315_PCI_INT_XXX bits
705 + */
706 +#define AR2315_PCI_IRQ_BASE 0x50
707 +#define AR2315_PCI_IRQ_EXT (AR2315_PCI_IRQ_BASE+0)
708 +#define AR2315_PCI_IRQ_ABORT (AR2315_PCI_IRQ_BASE+1)
709 +#define AR2315_PCI_IRQ_COUNT 2
710 +#define AR2315_PCI_IRQ_SHIFT 25 /* in AR2315_PCI_INT_STATUS */
711 +
712 +/*
713 + * Address map
714 + */
715 +#define AR2315_SPI_READ 0x08000000 /* SPI FLASH */
716 +#define AR2315_WLAN0 0x10000000 /* Wireless MMR */
717 +#define AR2315_PCI 0x10100000 /* PCI MMR */
718 +#define AR2315_SDRAMCTL 0x10300000 /* SDRAM MMR */
719 +#define AR2315_LOCAL 0x10400000 /* LOCAL BUS MMR */
720 +#define AR2315_ENET0 0x10500000 /* ETHERNET MMR */
721 +#define AR2315_DSLBASE 0x11000000 /* RESET CONTROL MMR */
722 +#define AR2315_UART0 0x11100000 /* UART MMR */
723 +#define AR2315_SPI_MMR 0x11300000 /* SPI FLASH MMR */
724 +#define AR2315_PCIEXT 0x80000000 /* pci external */
725 +#define AR2315_PCIEXT_SZ 0x40000000
726 +
727 +/* MII registers offset inside Ethernet MMR region */
728 +#define AR2315_ENET0_MII (AR2315_ENET0 + 0x14)
729 +
730 +/*
731 + * Cold reset register
732 + */
733 +#define AR2315_COLD_RESET (AR2315_DSLBASE + 0x0000)
734 +
735 +#define AR2315_RESET_COLD_AHB 0x00000001
736 +#define AR2315_RESET_COLD_APB 0x00000002
737 +#define AR2315_RESET_COLD_CPU 0x00000004
738 +#define AR2315_RESET_COLD_CPUWARM 0x00000008
739 +#define AR2315_RESET_SYSTEM \
740 + (RESET_COLD_CPU |\
741 + RESET_COLD_APB |\
742 + RESET_COLD_AHB) /* full system */
743 +#define AR2317_RESET_SYSTEM 0x00000010
744 +
745 +/*
746 + * Reset register
747 + */
748 +#define AR2315_RESET (AR2315_DSLBASE + 0x0004)
749 +
750 +/* warm reset WLAN0 MAC */
751 +#define AR2315_RESET_WARM_WLAN0_MAC 0x00000001
752 +/* warm reset WLAN0 BaseBand */
753 +#define AR2315_RESET_WARM_WLAN0_BB 0x00000002
754 +/* warm reset MPEG-TS */
755 +#define AR2315_RESET_MPEGTS_RSVD 0x00000004
756 +/* warm reset PCI ahb/dma */
757 +#define AR2315_RESET_PCIDMA 0x00000008
758 +/* warm reset memory controller */
759 +#define AR2315_RESET_MEMCTL 0x00000010
760 +/* warm reset local bus */
761 +#define AR2315_RESET_LOCAL 0x00000020
762 +/* warm reset I2C bus */
763 +#define AR2315_RESET_I2C_RSVD 0x00000040
764 +/* warm reset SPI interface */
765 +#define AR2315_RESET_SPI 0x00000080
766 +/* warm reset UART0 */
767 +#define AR2315_RESET_UART0 0x00000100
768 +/* warm reset IR interface */
769 +#define AR2315_RESET_IR_RSVD 0x00000200
770 +/* cold reset ENET0 phy */
771 +#define AR2315_RESET_EPHY0 0x00000400
772 +/* cold reset ENET0 mac */
773 +#define AR2315_RESET_ENET0 0x00000800
774 +
775 +/*
776 + * AHB master arbitration control
777 + */
778 +#define AR2315_AHB_ARB_CTL (AR2315_DSLBASE + 0x0008)
779 +
780 +/* CPU, default */
781 +#define AR2315_ARB_CPU 0x00000001
782 +/* WLAN */
783 +#define AR2315_ARB_WLAN 0x00000002
784 +/* MPEG-TS */
785 +#define AR2315_ARB_MPEGTS_RSVD 0x00000004
786 +/* LOCAL */
787 +#define AR2315_ARB_LOCAL 0x00000008
788 +/* PCI */
789 +#define AR2315_ARB_PCI 0x00000010
790 +/* Ethernet */
791 +#define AR2315_ARB_ETHERNET 0x00000020
792 +/* retry policy, debug only */
793 +#define AR2315_ARB_RETRY 0x00000100
794 +
795 +/*
796 + * Config Register
797 + */
798 +#define AR2315_ENDIAN_CTL (AR2315_DSLBASE + 0x000c)
799 +
800 +/* EC - AHB bridge endianess */
801 +#define AR2315_CONFIG_AHB 0x00000001
802 +/* WLAN byteswap */
803 +#define AR2315_CONFIG_WLAN 0x00000002
804 +/* MPEG-TS byteswap */
805 +#define AR2315_CONFIG_MPEGTS_RSVD 0x00000004
806 +/* PCI byteswap */
807 +#define AR2315_CONFIG_PCI 0x00000008
808 +/* Memory controller endianess */
809 +#define AR2315_CONFIG_MEMCTL 0x00000010
810 +/* Local bus byteswap */
811 +#define AR2315_CONFIG_LOCAL 0x00000020
812 +/* Ethernet byteswap */
813 +#define AR2315_CONFIG_ETHERNET 0x00000040
814 +
815 +/* CPU write buffer merge */
816 +#define AR2315_CONFIG_MERGE 0x00000200
817 +/* CPU big endian */
818 +#define AR2315_CONFIG_CPU 0x00000400
819 +#define AR2315_CONFIG_PCIAHB 0x00000800
820 +#define AR2315_CONFIG_PCIAHB_BRIDGE 0x00001000
821 +/* SPI byteswap */
822 +#define AR2315_CONFIG_SPI 0x00008000
823 +#define AR2315_CONFIG_CPU_DRAM 0x00010000
824 +#define AR2315_CONFIG_CPU_PCI 0x00020000
825 +#define AR2315_CONFIG_CPU_MMR 0x00040000
826 +#define AR2315_CONFIG_BIG 0x00000400
827 +
828 +/*
829 + * NMI control
830 + */
831 +#define AR2315_NMI_CTL (AR2315_DSLBASE + 0x0010)
832 +
833 +#define AR2315_NMI_EN 1
834 +
835 +/*
836 + * Revision Register - Initial value is 0x3010 (WMAC 3.0, AR231X 1.0).
837 + */
838 +#define AR2315_SREV (AR2315_DSLBASE + 0x0014)
839 +
840 +#define AR2315_REV_MAJ 0x00f0
841 +#define AR2315_REV_MAJ_S 4
842 +#define AR2315_REV_MIN 0x000f
843 +#define AR2315_REV_MIN_S 0
844 +#define AR2315_REV_CHIP (AR2315_REV_MAJ|AR2315_REV_MIN)
845 +
846 +/*
847 + * Interface Enable
848 + */
849 +#define AR2315_IF_CTL (AR2315_DSLBASE + 0x0018)
850 +
851 +#define AR2315_IF_MASK 0x00000007
852 +#define AR2315_IF_DISABLED 0
853 +#define AR2315_IF_PCI 1
854 +#define AR2315_IF_TS_LOCAL 2
855 +/* only for emulation with separate pins */
856 +#define AR2315_IF_ALL 3
857 +#define AR2315_IF_LOCAL_HOST 0x00000008
858 +#define AR2315_IF_PCI_HOST 0x00000010
859 +#define AR2315_IF_PCI_INTR 0x00000020
860 +#define AR2315_IF_PCI_CLK_MASK 0x00030000
861 +#define AR2315_IF_PCI_CLK_INPUT 0
862 +#define AR2315_IF_PCI_CLK_OUTPUT_LOW 1
863 +#define AR2315_IF_PCI_CLK_OUTPUT_CLK 2
864 +#define AR2315_IF_PCI_CLK_OUTPUT_HIGH 3
865 +#define AR2315_IF_PCI_CLK_SHIFT 16
866 +
867 +/*
868 + * APB Interrupt control
869 + */
870 +
871 +#define AR2315_ISR (AR2315_DSLBASE + 0x0020)
872 +#define AR2315_IMR (AR2315_DSLBASE + 0x0024)
873 +#define AR2315_GISR (AR2315_DSLBASE + 0x0028)
874 +
875 +#define AR2315_ISR_UART0 0x0001 /* high speed UART */
876 +#define AR2315_ISR_I2C_RSVD 0x0002 /* I2C bus */
877 +#define AR2315_ISR_SPI 0x0004 /* SPI bus */
878 +#define AR2315_ISR_AHB 0x0008 /* AHB error */
879 +#define AR2315_ISR_APB 0x0010 /* APB error */
880 +#define AR2315_ISR_TIMER 0x0020 /* timer */
881 +#define AR2315_ISR_GPIO 0x0040 /* GPIO */
882 +#define AR2315_ISR_WD 0x0080 /* watchdog */
883 +#define AR2315_ISR_IR_RSVD 0x0100 /* IR */
884 +
885 +#define AR2315_GISR_MISC 0x0001
886 +#define AR2315_GISR_WLAN0 0x0002
887 +#define AR2315_GISR_MPEGTS_RSVD 0x0004
888 +#define AR2315_GISR_LOCALPCI 0x0008
889 +#define AR2315_GISR_WMACPOLL 0x0010
890 +#define AR2315_GISR_TIMER 0x0020
891 +#define AR2315_GISR_ETHERNET 0x0040
892 +
893 +/*
894 + * Interrupt routing from IO to the processor IP bits
895 + * Define our inter mask and level
896 + */
897 +#define AR2315_INTR_MISCIO SR_IBIT3
898 +#define AR2315_INTR_WLAN0 SR_IBIT4
899 +#define AR2315_INTR_ENET0 SR_IBIT5
900 +#define AR2315_INTR_LOCALPCI SR_IBIT6
901 +#define AR2315_INTR_WMACPOLL SR_IBIT7
902 +#define AR2315_INTR_COMPARE SR_IBIT8
903 +
904 +/*
905 + * Timers
906 + */
907 +#define AR2315_TIMER (AR2315_DSLBASE + 0x0030)
908 +#define AR2315_RELOAD (AR2315_DSLBASE + 0x0034)
909 +#define AR2315_WD (AR2315_DSLBASE + 0x0038)
910 +#define AR2315_WDC (AR2315_DSLBASE + 0x003c)
911 +
912 +#define AR2315_WDC_IGNORE_EXPIRATION 0x00000000
913 +#define AR2315_WDC_NMI 0x00000001 /* NMI on watchdog */
914 +#define AR2315_WDC_RESET 0x00000002 /* reset on watchdog */
915 +
916 +/*
917 + * CPU Performance Counters
918 + */
919 +#define AR2315_PERFCNT0 (AR2315_DSLBASE + 0x0048)
920 +#define AR2315_PERFCNT1 (AR2315_DSLBASE + 0x004c)
921 +
922 +#define AR2315_PERF0_DATAHIT 0x0001 /* Count Data Cache Hits */
923 +#define AR2315_PERF0_DATAMISS 0x0002 /* Count Data Cache Misses */
924 +#define AR2315_PERF0_INSTHIT 0x0004 /* Count Instruction Cache Hits */
925 +#define AR2315_PERF0_INSTMISS 0x0008 /* Count Instruction Cache Misses */
926 +#define AR2315_PERF0_ACTIVE 0x0010 /* Count Active Processor Cycles */
927 +#define AR2315_PERF0_WBHIT 0x0020 /* Count CPU Write Buffer Hits */
928 +#define AR2315_PERF0_WBMISS 0x0040 /* Count CPU Write Buffer Misses */
929 +
930 +#define AR2315_PERF1_EB_ARDY 0x0001 /* Count EB_ARdy signal */
931 +#define AR2315_PERF1_EB_AVALID 0x0002 /* Count EB_AValid signal */
932 +#define AR2315_PERF1_EB_WDRDY 0x0004 /* Count EB_WDRdy signal */
933 +#define AR2315_PERF1_EB_RDVAL 0x0008 /* Count EB_RdVal signal */
934 +#define AR2315_PERF1_VRADDR 0x0010 /* Count valid read address cycles */
935 +#define AR2315_PERF1_VWADDR 0x0020 /* Count valid write address cycles */
936 +#define AR2315_PERF1_VWDATA 0x0040 /* Count valid write data cycles */
937 +
938 +/*
939 + * AHB Error Reporting.
940 + */
941 +#define AR2315_AHB_ERR0 (AR2315_DSLBASE + 0x0050) /* error */
942 +#define AR2315_AHB_ERR1 (AR2315_DSLBASE + 0x0054) /* haddr */
943 +#define AR2315_AHB_ERR2 (AR2315_DSLBASE + 0x0058) /* hwdata */
944 +#define AR2315_AHB_ERR3 (AR2315_DSLBASE + 0x005c) /* hrdata */
945 +#define AR2315_AHB_ERR4 (AR2315_DSLBASE + 0x0060) /* status */
946 +
947 +#define AHB_ERROR_DET 1 /* AHB Error has been detected, */
948 + /* write 1 to clear all bits in ERR0 */
949 +#define AHB_ERROR_OVR 2 /* AHB Error overflow has been detected */
950 +#define AHB_ERROR_WDT 4 /* AHB Error due to wdt instead of hresp */
951 +
952 +#define AR2315_PROCERR_HMAST 0x0000000f
953 +#define AR2315_PROCERR_HMAST_DFLT 0
954 +#define AR2315_PROCERR_HMAST_WMAC 1
955 +#define AR2315_PROCERR_HMAST_ENET 2
956 +#define AR2315_PROCERR_HMAST_PCIENDPT 3
957 +#define AR2315_PROCERR_HMAST_LOCAL 4
958 +#define AR2315_PROCERR_HMAST_CPU 5
959 +#define AR2315_PROCERR_HMAST_PCITGT 6
960 +
961 +#define AR2315_PROCERR_HMAST_S 0
962 +#define AR2315_PROCERR_HWRITE 0x00000010
963 +#define AR2315_PROCERR_HSIZE 0x00000060
964 +#define AR2315_PROCERR_HSIZE_S 5
965 +#define AR2315_PROCERR_HTRANS 0x00000180
966 +#define AR2315_PROCERR_HTRANS_S 7
967 +#define AR2315_PROCERR_HBURST 0x00000e00
968 +#define AR2315_PROCERR_HBURST_S 9
969 +
970 +/*
971 + * Clock Control
972 + */
973 +#define AR2315_PLLC_CTL (AR2315_DSLBASE + 0x0064)
974 +#define AR2315_PLLV_CTL (AR2315_DSLBASE + 0x0068)
975 +#define AR2315_CPUCLK (AR2315_DSLBASE + 0x006c)
976 +#define AR2315_AMBACLK (AR2315_DSLBASE + 0x0070)
977 +#define AR2315_SYNCCLK (AR2315_DSLBASE + 0x0074)
978 +#define AR2315_DSL_SLEEP_CTL (AR2315_DSLBASE + 0x0080)
979 +#define AR2315_DSL_SLEEP_DUR (AR2315_DSLBASE + 0x0084)
980 +
981 +/* PLLc Control fields */
982 +#define PLLC_REF_DIV_M 0x00000003
983 +#define PLLC_REF_DIV_S 0
984 +#define PLLC_FDBACK_DIV_M 0x0000007C
985 +#define PLLC_FDBACK_DIV_S 2
986 +#define PLLC_ADD_FDBACK_DIV_M 0x00000080
987 +#define PLLC_ADD_FDBACK_DIV_S 7
988 +#define PLLC_CLKC_DIV_M 0x0001c000
989 +#define PLLC_CLKC_DIV_S 14
990 +#define PLLC_CLKM_DIV_M 0x00700000
991 +#define PLLC_CLKM_DIV_S 20
992 +
993 +/* CPU CLK Control fields */
994 +#define CPUCLK_CLK_SEL_M 0x00000003
995 +#define CPUCLK_CLK_SEL_S 0
996 +#define CPUCLK_CLK_DIV_M 0x0000000c
997 +#define CPUCLK_CLK_DIV_S 2
998 +
999 +/* AMBA CLK Control fields */
1000 +#define AMBACLK_CLK_SEL_M 0x00000003
1001 +#define AMBACLK_CLK_SEL_S 0
1002 +#define AMBACLK_CLK_DIV_M 0x0000000c
1003 +#define AMBACLK_CLK_DIV_S 2
1004 +
1005 +/*
1006 + * GPIO
1007 + */
1008 +#define AR2315_GPIO_DI (AR2315_DSLBASE + 0x0088)
1009 +#define AR2315_GPIO_DO (AR2315_DSLBASE + 0x0090)
1010 +#define AR2315_GPIO_DIR (AR2315_DSLBASE + 0x0098)
1011 +#define AR2315_GPIO_INT (AR2315_DSLBASE + 0x00a0)
1012 +
1013 +#define AR2315_GPIO_DIR_M(x) (1 << (x)) /* mask for i/o */
1014 +#define AR2315_GPIO_DIR_O(x) (1 << (x)) /* output */
1015 +#define AR2315_GPIO_DIR_I(x) (0) /* input */
1016 +
1017 +#define AR2315_GPIO_INT_S(x) (x) /* interrupt enable */
1018 +#define AR2315_GPIO_INT_M (0x3F) /* mask for int */
1019 +#define AR2315_GPIO_INT_LVL(x) ((x) << 6) /* interrupt level */
1020 +#define AR2315_GPIO_INT_LVL_M ((0x3) << 6) /* mask for int level */
1021 +
1022 +#define AR2315_GPIO_INT_MAX_Y 1 /* Maximum value of Y for
1023 + * AR2315_GPIO_INT_* macros */
1024 +#define AR2315_GPIO_INT_LVL_OFF 0 /* Triggerring off */
1025 +#define AR2315_GPIO_INT_LVL_LOW 1 /* Low Level Triggered */
1026 +#define AR2315_GPIO_INT_LVL_HIGH 2 /* High Level Triggered */
1027 +#define AR2315_GPIO_INT_LVL_EDGE 3 /* Edge Triggered */
1028 +
1029 +#define AR2315_RESET_GPIO 5
1030 +#define AR2315_NUM_GPIO 22
1031 +
1032 +/*
1033 + * PCI Clock Control
1034 + */
1035 +#define AR2315_PCICLK (AR2315_DSLBASE + 0x00a4)
1036 +
1037 +#define AR2315_PCICLK_INPUT_M 0x3
1038 +#define AR2315_PCICLK_INPUT_S 0
1039 +
1040 +#define AR2315_PCICLK_PLLC_CLKM 0
1041 +#define AR2315_PCICLK_PLLC_CLKM1 1
1042 +#define AR2315_PCICLK_PLLC_CLKC 2
1043 +#define AR2315_PCICLK_REF_CLK 3
1044 +
1045 +#define AR2315_PCICLK_DIV_M 0xc
1046 +#define AR2315_PCICLK_DIV_S 2
1047 +
1048 +#define AR2315_PCICLK_IN_FREQ 0
1049 +#define AR2315_PCICLK_IN_FREQ_DIV_6 1
1050 +#define AR2315_PCICLK_IN_FREQ_DIV_8 2
1051 +#define AR2315_PCICLK_IN_FREQ_DIV_10 3
1052 +
1053 +/*
1054 + * Observation Control Register
1055 + */
1056 +#define AR2315_OCR (AR2315_DSLBASE + 0x00b0)
1057 +#define OCR_GPIO0_IRIN 0x0040
1058 +#define OCR_GPIO1_IROUT 0x0080
1059 +#define OCR_GPIO3_RXCLR 0x0200
1060 +
1061 +/*
1062 + * General Clock Control
1063 + */
1064 +
1065 +#define AR2315_MISCCLK (AR2315_DSLBASE + 0x00b4)
1066 +#define MISCCLK_PLLBYPASS_EN 0x00000001
1067 +#define MISCCLK_PROCREFCLK 0x00000002
1068 +
1069 +/*
1070 + * SDRAM Controller
1071 + * - No read or write buffers are included.
1072 + */
1073 +#define AR2315_MEM_CFG (AR2315_SDRAMCTL + 0x00)
1074 +#define AR2315_MEM_CTRL (AR2315_SDRAMCTL + 0x0c)
1075 +#define AR2315_MEM_REF (AR2315_SDRAMCTL + 0x10)
1076 +
1077 +#define SDRAM_DATA_WIDTH_M 0x00006000
1078 +#define SDRAM_DATA_WIDTH_S 13
1079 +
1080 +#define SDRAM_COL_WIDTH_M 0x00001E00
1081 +#define SDRAM_COL_WIDTH_S 9
1082 +
1083 +#define SDRAM_ROW_WIDTH_M 0x000001E0
1084 +#define SDRAM_ROW_WIDTH_S 5
1085 +
1086 +#define SDRAM_BANKADDR_BITS_M 0x00000018
1087 +#define SDRAM_BANKADDR_BITS_S 3
1088 +
1089 +/*
1090 + * PCI Bus Interface Registers
1091 + */
1092 +#define AR2315_PCI_1MS_REG (AR2315_PCI + 0x0008)
1093 +#define AR2315_PCI_1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
1094 +
1095 +#define AR2315_PCI_MISC_CONFIG (AR2315_PCI + 0x000c)
1096 +#define AR2315_PCIMISC_TXD_EN 0x00000001 /* Enable TXD for fragments */
1097 +#define AR2315_PCIMISC_CFG_SEL 0x00000002 /* mem or config cycles */
1098 +#define AR2315_PCIMISC_GIG_MASK 0x0000000C /* bits 31-30 for pci req */
1099 +#define AR2315_PCIMISC_RST_MODE 0x00000030
1100 +#define AR2315_PCIRST_INPUT 0x00000000 /* 4:5=0 rst is input */
1101 +#define AR2315_PCIRST_LOW 0x00000010 /* 4:5=1 rst to GND */
1102 +#define AR2315_PCIRST_HIGH 0x00000020 /* 4:5=2 rst to VDD */
1103 +#define AR2315_PCIGRANT_EN 0x00000000 /* 6:7=0 early grant en */
1104 +#define AR2315_PCIGRANT_FRAME 0x00000040 /* 6:7=1 grant waits 4 frame */
1105 +#define AR2315_PCIGRANT_IDLE 0x00000080 /* 6:7=2 grant waits 4 idle */
1106 +#define AR2315_PCIGRANT_GAP 0x00000000 /* 6:7=2 grant waits 4 idle */
1107 +#define AR2315_PCICACHE_DIS 0x00001000 /* PCI external access cache
1108 + * disable */
1109 +
1110 +#define AR2315_PCI_OUT_TSTAMP (AR2315_PCI + 0x0010)
1111 +
1112 +#define AR2315_PCI_UNCACHE_CFG (AR2315_PCI + 0x0014)
1113 +
1114 +#define AR2315_PCI_IN_EN (AR2315_PCI + 0x0100)
1115 +#define AR2315_PCI_IN_EN0 0x01 /* Enable chain 0 */
1116 +#define AR2315_PCI_IN_EN1 0x02 /* Enable chain 1 */
1117 +#define AR2315_PCI_IN_EN2 0x04 /* Enable chain 2 */
1118 +#define AR2315_PCI_IN_EN3 0x08 /* Enable chain 3 */
1119 +
1120 +#define AR2315_PCI_IN_DIS (AR2315_PCI + 0x0104)
1121 +#define AR2315_PCI_IN_DIS0 0x01 /* Disable chain 0 */
1122 +#define AR2315_PCI_IN_DIS1 0x02 /* Disable chain 1 */
1123 +#define AR2315_PCI_IN_DIS2 0x04 /* Disable chain 2 */
1124 +#define AR2315_PCI_IN_DIS3 0x08 /* Disable chain 3 */
1125 +
1126 +#define AR2315_PCI_IN_PTR (AR2315_PCI + 0x0200)
1127 +
1128 +#define AR2315_PCI_OUT_EN (AR2315_PCI + 0x0400)
1129 +#define AR2315_PCI_OUT_EN0 0x01 /* Enable chain 0 */
1130 +
1131 +#define AR2315_PCI_OUT_DIS (AR2315_PCI + 0x0404)
1132 +#define AR2315_PCI_OUT_DIS0 0x01 /* Disable chain 0 */
1133 +
1134 +#define AR2315_PCI_OUT_PTR (AR2315_PCI + 0x0408)
1135 +
1136 +#define AR2315_PCI_ISR (AR2315_PCI + 0x0500) /* write one to clr */
1137 +#define AR2315_PCI_INT_TX 0x00000001 /* Desc In Completed */
1138 +#define AR2315_PCI_INT_TXOK 0x00000002 /* Desc In OK */
1139 +#define AR2315_PCI_INT_TXERR 0x00000004 /* Desc In ERR */
1140 +#define AR2315_PCI_INT_TXEOL 0x00000008 /* Desc In End-of-List */
1141 +#define AR2315_PCI_INT_RX 0x00000010 /* Desc Out Completed */
1142 +#define AR2315_PCI_INT_RXOK 0x00000020 /* Desc Out OK */
1143 +#define AR2315_PCI_INT_RXERR 0x00000040 /* Desc Out ERR */
1144 +#define AR2315_PCI_INT_RXEOL 0x00000080 /* Desc Out EOL */
1145 +#define AR2315_PCI_INT_TXOOD 0x00000200 /* Desc In Out-of-Desc */
1146 +#define AR2315_PCI_INT_DESCMASK 0x0000FFFF /* Desc Mask */
1147 +#define AR2315_PCI_INT_EXT 0x02000000 /* Extern PCI INTA */
1148 +#define AR2315_PCI_INT_ABORT 0x04000000 /* PCI bus abort event */
1149 +
1150 +#define AR2315_PCI_IMR (AR2315_PCI + 0x0504) /* mask _PCI_ISR bits */
1151 +
1152 +#define AR2315_PCI_IER (AR2315_PCI + 0x0508) /* global PCI int en */
1153 +#define AR2315_PCI_IER_DISABLE 0x00 /* disable pci interrupts */
1154 +#define AR2315_PCI_IER_ENABLE 0x01 /* enable pci interrupts */
1155 +
1156 +#define AR2315_PCI_HOST_IN_EN (AR2315_PCI + 0x0800)
1157 +#define AR2315_PCI_HOST_IN_DIS (AR2315_PCI + 0x0804)
1158 +#define AR2315_PCI_HOST_IN_PTR (AR2315_PCI + 0x0810)
1159 +#define AR2315_PCI_HOST_OUT_EN (AR2315_PCI + 0x0900)
1160 +#define AR2315_PCI_HOST_OUT_DIS (AR2315_PCI + 0x0904)
1161 +#define AR2315_PCI_HOST_OUT_PTR (AR2315_PCI + 0x0908)
1162 +
1163 +/*
1164 + * Local Bus Interface Registers
1165 + */
1166 +#define AR2315_LB_CONFIG (AR2315_LOCAL + 0x0000)
1167 +#define AR2315_LBCONF_OE 0x00000001 /* =1 OE is low-true */
1168 +#define AR2315_LBCONF_CS0 0x00000002 /* =1 first CS is low-true */
1169 +#define AR2315_LBCONF_CS1 0x00000004 /* =1 2nd CS is low-true */
1170 +#define AR2315_LBCONF_RDY 0x00000008 /* =1 RDY is low-true */
1171 +#define AR2315_LBCONF_WE 0x00000010 /* =1 Write En is low-true */
1172 +#define AR2315_LBCONF_WAIT 0x00000020 /* =1 WAIT is low-true */
1173 +#define AR2315_LBCONF_ADS 0x00000040 /* =1 Adr Strobe is low-true */
1174 +#define AR2315_LBCONF_MOT 0x00000080 /* =0 Intel, =1 Motorola */
1175 +#define AR2315_LBCONF_8CS 0x00000100 /* =1 8 bits CS, 0= 16bits */
1176 +#define AR2315_LBCONF_8DS 0x00000200 /* =1 8 bits Data S, 0=16bits */
1177 +#define AR2315_LBCONF_ADS_EN 0x00000400 /* =1 Enable ADS */
1178 +#define AR2315_LBCONF_ADR_OE 0x00000800 /* =1 Adr cap on OE, WE or DS */
1179 +#define AR2315_LBCONF_ADDT_MUX 0x00001000 /* =1 Adr and Data share bus */
1180 +#define AR2315_LBCONF_DATA_OE 0x00002000 /* =1 Data cap on OE, WE, DS */
1181 +#define AR2315_LBCONF_16DATA 0x00004000 /* =1 Data is 16 bits wide */
1182 +#define AR2315_LBCONF_SWAPDT 0x00008000 /* =1 Byte swap data */
1183 +#define AR2315_LBCONF_SYNC 0x00010000 /* =1 Bus synchronous to clk */
1184 +#define AR2315_LBCONF_INT 0x00020000 /* =1 Intr is low true */
1185 +#define AR2315_LBCONF_INT_CTR0 0x00000000 /* GND high-Z, Vdd is high-Z */
1186 +#define AR2315_LBCONF_INT_CTR1 0x00040000 /* GND drive, Vdd is high-Z */
1187 +#define AR2315_LBCONF_INT_CTR2 0x00080000 /* GND high-Z, Vdd drive */
1188 +#define AR2315_LBCONF_INT_CTR3 0x000C0000 /* GND drive, Vdd drive */
1189 +#define AR2315_LBCONF_RDY_WAIT 0x00100000 /* =1 RDY is negative of WAIT */
1190 +#define AR2315_LBCONF_INT_PULSE 0x00200000 /* =1 Interrupt is a pulse */
1191 +#define AR2315_LBCONF_ENABLE 0x00400000 /* =1 Falcon respond to LB */
1192 +
1193 +#define AR2315_LB_CLKSEL (AR2315_LOCAL + 0x0004)
1194 +#define AR2315_LBCLK_EXT 0x0001 /* use external clk for lb */
1195 +
1196 +#define AR2315_LB_1MS (AR2315_LOCAL + 0x0008)
1197 +#define AR2315_LB1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
1198 +
1199 +#define AR2315_LB_MISCCFG (AR2315_LOCAL + 0x000C)
1200 +#define AR2315_LBM_TXD_EN 0x00000001 /* Enable TXD for fragments */
1201 +#define AR2315_LBM_RX_INTEN 0x00000002 /* Enable LB ints on RX ready */
1202 +#define AR2315_LBM_MBOXWR_INTEN 0x00000004 /* Enable LB ints on mbox wr */
1203 +#define AR2315_LBM_MBOXRD_INTEN 0x00000008 /* Enable LB ints on mbox rd */
1204 +#define AR2315_LMB_DESCSWAP_EN 0x00000010 /* Byte swap desc enable */
1205 +#define AR2315_LBM_TIMEOUT_MASK 0x00FFFF80
1206 +#define AR2315_LBM_TIMEOUT_SHFT 7
1207 +#define AR2315_LBM_PORTMUX 0x07000000
1208 +
1209 +#define AR2315_LB_RXTSOFF (AR2315_LOCAL + 0x0010)
1210 +
1211 +#define AR2315_LB_TX_CHAIN_EN (AR2315_LOCAL + 0x0100)
1212 +#define AR2315_LB_TXEN_0 0x01
1213 +#define AR2315_LB_TXEN_1 0x02
1214 +#define AR2315_LB_TXEN_2 0x04
1215 +#define AR2315_LB_TXEN_3 0x08
1216 +
1217 +#define AR2315_LB_TX_CHAIN_DIS (AR2315_LOCAL + 0x0104)
1218 +#define AR2315_LB_TX_DESC_PTR (AR2315_LOCAL + 0x0200)
1219 +
1220 +#define AR2315_LB_RX_CHAIN_EN (AR2315_LOCAL + 0x0400)
1221 +#define AR2315_LB_RXEN 0x01
1222 +
1223 +#define AR2315_LB_RX_CHAIN_DIS (AR2315_LOCAL + 0x0404)
1224 +#define AR2315_LB_RX_DESC_PTR (AR2315_LOCAL + 0x0408)
1225 +
1226 +#define AR2315_LB_INT_STATUS (AR2315_LOCAL + 0x0500)
1227 +#define AR2315_INT_TX_DESC 0x0001
1228 +#define AR2315_INT_TX_OK 0x0002
1229 +#define AR2315_INT_TX_ERR 0x0004
1230 +#define AR2315_INT_TX_EOF 0x0008
1231 +#define AR2315_INT_RX_DESC 0x0010
1232 +#define AR2315_INT_RX_OK 0x0020
1233 +#define AR2315_INT_RX_ERR 0x0040
1234 +#define AR2315_INT_RX_EOF 0x0080
1235 +#define AR2315_INT_TX_TRUNC 0x0100
1236 +#define AR2315_INT_TX_STARVE 0x0200
1237 +#define AR2315_INT_LB_TIMEOUT 0x0400
1238 +#define AR2315_INT_LB_ERR 0x0800
1239 +#define AR2315_INT_MBOX_WR 0x1000
1240 +#define AR2315_INT_MBOX_RD 0x2000
1241 +
1242 +/* Bit definitions for INT MASK are the same as INT_STATUS */
1243 +#define AR2315_LB_INT_MASK (AR2315_LOCAL + 0x0504)
1244 +
1245 +#define AR2315_LB_INT_EN (AR2315_LOCAL + 0x0508)
1246 +#define AR2315_LB_MBOX (AR2315_LOCAL + 0x0600)
1247 +
1248 +/*
1249 + * IR Interface Registers
1250 + */
1251 +#define AR2315_IR_PKTDATA (AR2315_IR + 0x0000)
1252 +
1253 +#define AR2315_IR_PKTLEN (AR2315_IR + 0x07fc) /* 0 - 63 */
1254 +
1255 +#define AR2315_IR_CONTROL (AR2315_IR + 0x0800)
1256 +#define AR2315_IRCTL_TX 0x00000000 /* use as tranmitter */
1257 +#define AR2315_IRCTL_RX 0x00000001 /* use as receiver */
1258 +#define AR2315_IRCTL_SAMPLECLK_MASK 0x00003ffe /* Sample clk divisor */
1259 +#define AR2315_IRCTL_SAMPLECLK_SHFT 1
1260 +#define AR2315_IRCTL_OUTPUTCLK_MASK 0x03ffc000 /* Output clk div */
1261 +#define AR2315_IRCTL_OUTPUTCLK_SHFT 14
1262 +
1263 +#define AR2315_IR_STATUS (AR2315_IR + 0x0804)
1264 +#define AR2315_IRSTS_RX 0x00000001 /* receive in progress */
1265 +#define AR2315_IRSTS_TX 0x00000002 /* transmit in progress */
1266 +
1267 +#define AR2315_IR_CONFIG (AR2315_IR + 0x0808)
1268 +#define AR2315_IRCFG_INVIN 0x00000001 /* invert in polarity */
1269 +#define AR2315_IRCFG_INVOUT 0x00000002 /* invert out polarity */
1270 +#define AR2315_IRCFG_SEQ_START_WIN_SEL 0x00000004 /* 1 => 28, 0 => 7 */
1271 +#define AR2315_IRCFG_SEQ_START_THRESH 0x000000f0
1272 +#define AR2315_IRCFG_SEQ_END_UNIT_SEL 0x00000100
1273 +#define AR2315_IRCFG_SEQ_END_UNIT_THRESH 0x00007e00
1274 +#define AR2315_IRCFG_SEQ_END_WIN_SEL 0x00008000
1275 +#define AR2315_IRCFG_SEQ_END_WIN_THRESH 0x001f0000
1276 +#define AR2315_IRCFG_NUM_BACKOFF_WORDS 0x01e00000
1277 +
1278 +/*
1279 + * We need some arbitrary non-zero value to be programmed to the BAR1 register
1280 + * of PCI host controller to enable DMA. The same value should be used as the
1281 + * offset to calculate the physical address of DMA buffer for PCI devices.
1282 + */
1283 +#define AR2315_PCI_HOST_SDRAM_BASEADDR 0x20000000
1284 +
1285 +/* ??? access BAR */
1286 +#define AR2315_PCI_HOST_MBAR0 0x10000000
1287 +/* RAM access BAR */
1288 +#define AR2315_PCI_HOST_MBAR1 AR2315_PCI_HOST_SDRAM_BASEADDR
1289 +/* ??? access BAR */
1290 +#define AR2315_PCI_HOST_MBAR2 0x30000000
1291 +
1292 +#endif /* __ASM_MACH_AR231X_AR2315_REGS_H */
1293 --- /dev/null
1294 +++ b/arch/mips/include/asm/mach-ar231x/ar5312_regs.h
1295 @@ -0,0 +1,235 @@
1296 +/*
1297 + * This file is subject to the terms and conditions of the GNU General Public
1298 + * License. See the file "COPYING" in the main directory of this archive
1299 + * for more details.
1300 + *
1301 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1302 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1303 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
1304 + */
1305 +
1306 +#ifndef __ASM_MACH_AR231X_AR5312_REGS_H
1307 +#define __ASM_MACH_AR231X_AR5312_REGS_H
1308 +
1309 +#include <asm/addrspace.h>
1310 +
1311 +/*
1312 + * IRQs
1313 + */
1314 +#define AR5312_IRQ_WLAN0_INTRS (MIPS_CPU_IRQ_BASE+2) /* C0_CAUSE: 0x0400 */
1315 +#define AR5312_IRQ_ENET0_INTRS (MIPS_CPU_IRQ_BASE+3) /* C0_CAUSE: 0x0800 */
1316 +#define AR5312_IRQ_ENET1_INTRS (MIPS_CPU_IRQ_BASE+4) /* C0_CAUSE: 0x1000 */
1317 +#define AR5312_IRQ_WLAN1_INTRS (MIPS_CPU_IRQ_BASE+5) /* C0_CAUSE: 0x2000 */
1318 +#define AR5312_IRQ_MISC_INTRS (MIPS_CPU_IRQ_BASE+6) /* C0_CAUSE: 0x4000 */
1319 +
1320 +/*
1321 + * Miscellaneous interrupts, which share IP6.
1322 + */
1323 +#define AR5312_MISC_IRQ_TIMER (AR231X_MISC_IRQ_BASE+0)
1324 +#define AR5312_MISC_IRQ_AHB_PROC (AR231X_MISC_IRQ_BASE+1)
1325 +#define AR5312_MISC_IRQ_AHB_DMA (AR231X_MISC_IRQ_BASE+2)
1326 +#define AR5312_MISC_IRQ_GPIO (AR231X_MISC_IRQ_BASE+3)
1327 +#define AR5312_MISC_IRQ_UART0 (AR231X_MISC_IRQ_BASE+4)
1328 +#define AR5312_MISC_IRQ_UART0_DMA (AR231X_MISC_IRQ_BASE+5)
1329 +#define AR5312_MISC_IRQ_WATCHDOG (AR231X_MISC_IRQ_BASE+6)
1330 +#define AR5312_MISC_IRQ_LOCAL (AR231X_MISC_IRQ_BASE+7)
1331 +#define AR5312_MISC_IRQ_SPI (AR231X_MISC_IRQ_BASE+8)
1332 +#define AR5312_MISC_IRQ_COUNT 9
1333 +
1334 +/*
1335 + * Address Map
1336 + */
1337 +#define AR5312_WLAN0 0x18000000
1338 +#define AR5312_WLAN1 0x18500000
1339 +#define AR5312_ENET0 0x18100000
1340 +#define AR5312_ENET1 0x18200000
1341 +#define AR5312_SDRAMCTL 0x18300000
1342 +#define AR5312_FLASHCTL 0x18400000
1343 +#define AR5312_APBBASE 0x1c000000
1344 +#define AR5312_UART0 0x1c000000 /* UART MMR */
1345 +#define AR5312_FLASH 0x1e000000
1346 +
1347 +/*
1348 + * AR5312_NUM_ENET_MAC defines the number of ethernet MACs that
1349 + * should be considered available. The AR5312 supports 2 enet MACS,
1350 + * even though many reference boards only actually use 1 of them
1351 + * (i.e. Only MAC 0 is actually connected to an enet PHY or PHY switch.
1352 + * The AR2312 supports 1 enet MAC.
1353 + */
1354 +#define AR5312_NUM_ENET_MAC 2
1355 +
1356 +/*
1357 + * Need these defines to determine true number of ethernet MACs
1358 + */
1359 +#define AR5312_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */
1360 +#define AR5312_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
1361 +#define AR5312_AR2313_REV8 0x0058 /* AR2313 WMAC (AP43-030) */
1362 +
1363 +/* MII registers offset inside Ethernet MMR region */
1364 +#define AR5312_ENET0_MII (AR5312_ENET0 + 0x14)
1365 +#define AR5312_ENET1_MII (AR5312_ENET1 + 0x14)
1366 +
1367 +/*
1368 + * AR5312_NUM_WMAC defines the number of Wireless MACs that\
1369 + * should be considered available.
1370 + */
1371 +#define AR5312_NUM_WMAC 2
1372 +
1373 +/* Reset/Timer Block Address Map */
1374 +#define AR5312_RESETTMR (AR5312_APBBASE + 0x3000)
1375 +#define AR5312_TIMER (AR5312_RESETTMR + 0x0000) /* countdown timer */
1376 +#define AR5312_WD_CTRL (AR5312_RESETTMR + 0x0008) /* watchdog cntrl */
1377 +#define AR5312_WD_TIMER (AR5312_RESETTMR + 0x000c) /* watchdog timer */
1378 +#define AR5312_ISR (AR5312_RESETTMR + 0x0010) /* Intr Status Reg */
1379 +#define AR5312_IMR (AR5312_RESETTMR + 0x0014) /* Intr Mask Reg */
1380 +#define AR5312_RESET (AR5312_RESETTMR + 0x0020)
1381 +#define AR5312_CLOCKCTL1 (AR5312_RESETTMR + 0x0064)
1382 +#define AR5312_SCRATCH (AR5312_RESETTMR + 0x006c)
1383 +#define AR5312_PROCADDR (AR5312_RESETTMR + 0x0070)
1384 +#define AR5312_PROC1 (AR5312_RESETTMR + 0x0074)
1385 +#define AR5312_DMAADDR (AR5312_RESETTMR + 0x0078)
1386 +#define AR5312_DMA1 (AR5312_RESETTMR + 0x007c)
1387 +#define AR5312_ENABLE (AR5312_RESETTMR + 0x0080) /* interface enb */
1388 +#define AR5312_REV (AR5312_RESETTMR + 0x0090) /* revision */
1389 +
1390 +/* AR5312_WD_CTRL register bit field definitions */
1391 +#define AR5312_WD_CTRL_IGNORE_EXPIRATION 0x0000
1392 +#define AR5312_WD_CTRL_NMI 0x0001
1393 +#define AR5312_WD_CTRL_RESET 0x0002
1394 +
1395 +/* AR5312_ISR register bit field definitions */
1396 +#define AR5312_ISR_TIMER 0x0001
1397 +#define AR5312_ISR_AHBPROC 0x0002
1398 +#define AR5312_ISR_AHBDMA 0x0004
1399 +#define AR5312_ISR_GPIO 0x0008
1400 +#define AR5312_ISR_UART0 0x0010
1401 +#define AR5312_ISR_UART0DMA 0x0020
1402 +#define AR5312_ISR_WD 0x0040
1403 +#define AR5312_ISR_LOCAL 0x0080
1404 +
1405 +/* AR5312_RESET register bit field definitions */
1406 +#define AR5312_RESET_SYSTEM 0x00000001 /* cold reset full system */
1407 +#define AR5312_RESET_PROC 0x00000002 /* cold reset MIPS core */
1408 +#define AR5312_RESET_WLAN0 0x00000004 /* cold reset WLAN MAC and BB */
1409 +#define AR5312_RESET_EPHY0 0x00000008 /* cold reset ENET0 phy */
1410 +#define AR5312_RESET_EPHY1 0x00000010 /* cold reset ENET1 phy */
1411 +#define AR5312_RESET_ENET0 0x00000020 /* cold reset ENET0 mac */
1412 +#define AR5312_RESET_ENET1 0x00000040 /* cold reset ENET1 mac */
1413 +#define AR5312_RESET_UART0 0x00000100 /* cold reset UART0 (high speed) */
1414 +#define AR5312_RESET_WLAN1 0x00000200 /* cold reset WLAN MAC/BB */
1415 +#define AR5312_RESET_APB 0x00000400 /* cold reset APB (ar5312) */
1416 +#define AR5312_RESET_WARM_PROC 0x00001000 /* warm reset MIPS core */
1417 +#define AR5312_RESET_WARM_WLAN0_MAC 0x00002000 /* warm reset WLAN0 MAC */
1418 +#define AR5312_RESET_WARM_WLAN0_BB 0x00004000 /* warm reset WLAN0 BaseBand */
1419 +#define AR5312_RESET_NMI 0x00010000 /* send an NMI to the processor */
1420 +#define AR5312_RESET_WARM_WLAN1_MAC 0x00020000 /* warm reset WLAN1 mac */
1421 +#define AR5312_RESET_WARM_WLAN1_BB 0x00040000 /* warm reset WLAN1 baseband */
1422 +#define AR5312_RESET_LOCAL_BUS 0x00080000 /* reset local bus */
1423 +#define AR5312_RESET_WDOG 0x00100000 /* last reset was a watchdog */
1424 +
1425 +#define AR5312_RESET_WMAC0_BITS \
1426 + (AR5312_RESET_WLAN0 |\
1427 + AR5312_RESET_WARM_WLAN0_MAC |\
1428 + AR5312_RESET_WARM_WLAN0_BB)
1429 +
1430 +#define AR5312_RESET_WMAC1_BITS \
1431 + (AR5312_RESET_WLAN1 |\
1432 + AR5312_RESET_WARM_WLAN1_MAC |\
1433 + AR5312_RESET_WARM_WLAN1_BB)
1434 +
1435 +/* AR5312_CLOCKCTL1 register bit field definitions */
1436 +#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1437 +#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1438 +#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1439 +#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1440 +#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1441 +
1442 +/* Valid for AR5312 and AR2312 */
1443 +#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1444 +#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1445 +#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1446 +#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1447 +#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1448 +
1449 +/* Valid for AR2313 */
1450 +#define AR2313_CLOCKCTL1_PREDIVIDE_MASK 0x00003000
1451 +#define AR2313_CLOCKCTL1_PREDIVIDE_SHIFT 12
1452 +#define AR2313_CLOCKCTL1_MULTIPLIER_MASK 0x001f0000
1453 +#define AR2313_CLOCKCTL1_MULTIPLIER_SHIFT 16
1454 +#define AR2313_CLOCKCTL1_DOUBLER_MASK 0x00000000
1455 +
1456 +/* AR5312_ENABLE register bit field definitions */
1457 +#define AR5312_ENABLE_WLAN0 0x0001
1458 +#define AR5312_ENABLE_ENET0 0x0002
1459 +#define AR5312_ENABLE_ENET1 0x0004
1460 +#define AR5312_ENABLE_UART_AND_WLAN1_PIO 0x0008 /* UART, and WLAN1 PIOs */
1461 +#define AR5312_ENABLE_WLAN1_DMA 0x0010 /* WLAN1 DMAs */
1462 +#define AR5312_ENABLE_WLAN1 \
1463 + (AR5312_ENABLE_UART_AND_WLAN1_PIO |\
1464 + AR5312_ENABLE_WLAN1_DMA)
1465 +
1466 +/* AR5312_REV register bit field definitions */
1467 +#define AR5312_REV_WMAC_MAJ 0xf000
1468 +#define AR5312_REV_WMAC_MAJ_S 12
1469 +#define AR5312_REV_WMAC_MIN 0x0f00
1470 +#define AR5312_REV_WMAC_MIN_S 8
1471 +#define AR5312_REV_MAJ 0x00f0
1472 +#define AR5312_REV_MAJ_S 4
1473 +#define AR5312_REV_MIN 0x000f
1474 +#define AR5312_REV_MIN_S 0
1475 +#define AR5312_REV_CHIP (AR5312_REV_MAJ|AR5312_REV_MIN)
1476 +
1477 +/* Major revision numbers, bits 7..4 of Revision ID register */
1478 +#define AR5312_REV_MAJ_AR5312 0x4
1479 +#define AR5312_REV_MAJ_AR2313 0x5
1480 +
1481 +/* Minor revision numbers, bits 3..0 of Revision ID register */
1482 +#define AR5312_REV_MIN_DUAL 0x0 /* Dual WLAN version */
1483 +#define AR5312_REV_MIN_SINGLE 0x1 /* Single WLAN version */
1484 +
1485 +/* AR5312_FLASHCTL register bit field definitions */
1486 +#define FLASHCTL_IDCY 0x0000000f /* Idle cycle turn around time */
1487 +#define FLASHCTL_IDCY_S 0
1488 +#define FLASHCTL_WST1 0x000003e0 /* Wait state 1 */
1489 +#define FLASHCTL_WST1_S 5
1490 +#define FLASHCTL_RBLE 0x00000400 /* Read byte lane enable */
1491 +#define FLASHCTL_WST2 0x0000f800 /* Wait state 2 */
1492 +#define FLASHCTL_WST2_S 11
1493 +#define FLASHCTL_AC 0x00070000 /* Flash address check (added) */
1494 +#define FLASHCTL_AC_S 16
1495 +#define FLASHCTL_AC_128K 0x00000000
1496 +#define FLASHCTL_AC_256K 0x00010000
1497 +#define FLASHCTL_AC_512K 0x00020000
1498 +#define FLASHCTL_AC_1M 0x00030000
1499 +#define FLASHCTL_AC_2M 0x00040000
1500 +#define FLASHCTL_AC_4M 0x00050000
1501 +#define FLASHCTL_AC_8M 0x00060000
1502 +#define FLASHCTL_AC_RES 0x00070000 /* 16MB is not supported */
1503 +#define FLASHCTL_E 0x00080000 /* Flash bank enable (added) */
1504 +#define FLASHCTL_BUSERR 0x01000000 /* Bus transfer error status flag */
1505 +#define FLASHCTL_WPERR 0x02000000 /* Write protect error status flag */
1506 +#define FLASHCTL_WP 0x04000000 /* Write protect */
1507 +#define FLASHCTL_BM 0x08000000 /* Burst mode */
1508 +#define FLASHCTL_MW 0x30000000 /* Memory width */
1509 +#define FLASHCTL_MW8 0x00000000 /* Memory width x8 */
1510 +#define FLASHCTL_MW16 0x10000000 /* Memory width x16 */
1511 +#define FLASHCTL_MW32 0x20000000 /* Memory width x32 (not supported) */
1512 +#define FLASHCTL_ATNR 0x00000000 /* Access type == no retry */
1513 +#define FLASHCTL_ATR 0x80000000 /* Access type == retry every */
1514 +#define FLASHCTL_ATR4 0xc0000000 /* Access type == retry every 4 */
1515 +
1516 +/* ARM Flash Controller -- 3 flash banks with either x8 or x16 devices. */
1517 +#define AR5312_FLASHCTL0 (AR5312_FLASHCTL + 0x00)
1518 +#define AR5312_FLASHCTL1 (AR5312_FLASHCTL + 0x04)
1519 +#define AR5312_FLASHCTL2 (AR5312_FLASHCTL + 0x08)
1520 +
1521 +/* ARM SDRAM Controller -- just enough to determine memory size */
1522 +#define AR5312_MEM_CFG1 (AR5312_SDRAMCTL + 0x04)
1523 +#define MEM_CFG1_AC0 0x00000700 /* bank 0: SDRAM addr check (added) */
1524 +#define MEM_CFG1_AC0_S 8
1525 +#define MEM_CFG1_AC1 0x00007000 /* bank 1: SDRAM addr check (added) */
1526 +#define MEM_CFG1_AC1_S 12
1527 +
1528 +#define AR5312_GPIO (AR5312_APBBASE + 0x2000)
1529 +
1530 +#endif /* __ASM_MACH_AR231X_AR5312_REGS_H */
1531 --- /dev/null
1532 +++ b/arch/mips/ar231x/ar5312.c
1533 @@ -0,0 +1,476 @@
1534 +/*
1535 + * This file is subject to the terms and conditions of the GNU General Public
1536 + * License. See the file "COPYING" in the main directory of this archive
1537 + * for more details.
1538 + *
1539 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1540 + * Copyright (C) 2006 FON Technology, SL.
1541 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1542 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
1543 + * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
1544 + */
1545 +
1546 +/*
1547 + * Platform devices for Atheros SoCs
1548 + */
1549 +
1550 +#include <generated/autoconf.h>
1551 +#include <linux/init.h>
1552 +#include <linux/module.h>
1553 +#include <linux/types.h>
1554 +#include <linux/string.h>
1555 +#include <linux/mtd/physmap.h>
1556 +#include <linux/platform_device.h>
1557 +#include <linux/kernel.h>
1558 +#include <linux/reboot.h>
1559 +#include <linux/leds.h>
1560 +#include <linux/gpio.h>
1561 +#include <asm/bootinfo.h>
1562 +#include <asm/reboot.h>
1563 +#include <asm/time.h>
1564 +#include <linux/irq.h>
1565 +#include <linux/io.h>
1566 +
1567 +#include <ar231x_platform.h>
1568 +#include <ar5312_regs.h>
1569 +#include <ar231x.h>
1570 +#include "devices.h"
1571 +#include "ar5312.h"
1572 +
1573 +static void ar5312_misc_irq_handler(unsigned irq, struct irq_desc *desc)
1574 +{
1575 + unsigned int ar231x_misc_intrs = ar231x_read_reg(AR5312_ISR) &
1576 + ar231x_read_reg(AR5312_IMR);
1577 +
1578 + if (ar231x_misc_intrs & AR5312_ISR_TIMER) {
1579 + generic_handle_irq(AR5312_MISC_IRQ_TIMER);
1580 + (void)ar231x_read_reg(AR5312_TIMER);
1581 + } else if (ar231x_misc_intrs & AR5312_ISR_AHBPROC)
1582 + generic_handle_irq(AR5312_MISC_IRQ_AHB_PROC);
1583 + else if ((ar231x_misc_intrs & AR5312_ISR_UART0))
1584 + generic_handle_irq(AR5312_MISC_IRQ_UART0);
1585 + else if (ar231x_misc_intrs & AR5312_ISR_WD)
1586 + generic_handle_irq(AR5312_MISC_IRQ_WATCHDOG);
1587 + else
1588 + spurious_interrupt();
1589 +}
1590 +
1591 +static asmlinkage void
1592 +ar5312_irq_dispatch(void)
1593 +{
1594 + int pending = read_c0_status() & read_c0_cause();
1595 +
1596 + if (pending & CAUSEF_IP2)
1597 + do_IRQ(AR5312_IRQ_WLAN0_INTRS);
1598 + else if (pending & CAUSEF_IP3)
1599 + do_IRQ(AR5312_IRQ_ENET0_INTRS);
1600 + else if (pending & CAUSEF_IP4)
1601 + do_IRQ(AR5312_IRQ_ENET1_INTRS);
1602 + else if (pending & CAUSEF_IP5)
1603 + do_IRQ(AR5312_IRQ_WLAN1_INTRS);
1604 + else if (pending & CAUSEF_IP6)
1605 + do_IRQ(AR5312_IRQ_MISC_INTRS);
1606 + else if (pending & CAUSEF_IP7)
1607 + do_IRQ(AR231X_IRQ_CPU_CLOCK);
1608 + else
1609 + spurious_interrupt();
1610 +}
1611 +
1612 +/* Enable the specified AR5312_MISC_IRQ interrupt */
1613 +static void
1614 +ar5312_misc_irq_unmask(struct irq_data *d)
1615 +{
1616 + unsigned int imr;
1617 +
1618 + imr = ar231x_read_reg(AR5312_IMR);
1619 + imr |= 1 << (d->irq - AR231X_MISC_IRQ_BASE);
1620 + ar231x_write_reg(AR5312_IMR, imr);
1621 +}
1622 +
1623 +/* Disable the specified AR5312_MISC_IRQ interrupt */
1624 +static void
1625 +ar5312_misc_irq_mask(struct irq_data *d)
1626 +{
1627 + unsigned int imr;
1628 +
1629 + imr = ar231x_read_reg(AR5312_IMR);
1630 + imr &= ~(1 << (d->irq - AR231X_MISC_IRQ_BASE));
1631 + ar231x_write_reg(AR5312_IMR, imr);
1632 + ar231x_read_reg(AR5312_IMR); /* flush write buffer */
1633 +}
1634 +
1635 +static struct irq_chip ar5312_misc_irq_chip = {
1636 + .name = "AR5312-MISC",
1637 + .irq_unmask = ar5312_misc_irq_unmask,
1638 + .irq_mask = ar5312_misc_irq_mask,
1639 +};
1640 +
1641 +static irqreturn_t ar5312_ahb_proc_handler(int cpl, void *dev_id)
1642 +{
1643 + u32 proc1 = ar231x_read_reg(AR5312_PROC1);
1644 + u32 proc_addr = ar231x_read_reg(AR5312_PROCADDR); /* clears error */
1645 + u32 dma1 = ar231x_read_reg(AR5312_DMA1);
1646 + u32 dma_addr = ar231x_read_reg(AR5312_DMAADDR); /* clears error */
1647 +
1648 + pr_emerg("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x DMAADDR=0x%8.8x DMA1=0x%8.8x\n",
1649 + proc_addr, proc1, dma_addr, dma1);
1650 +
1651 + machine_restart("AHB error"); /* Catastrophic failure */
1652 + return IRQ_HANDLED;
1653 +}
1654 +
1655 +static struct irqaction ar5312_ahb_proc_interrupt = {
1656 + .handler = ar5312_ahb_proc_handler,
1657 + .name = "ar5312_ahb_proc_interrupt",
1658 +};
1659 +
1660 +void __init ar5312_irq_init(void)
1661 +{
1662 + int i;
1663 +
1664 + if (!is_5312())
1665 + return;
1666 +
1667 + ar231x_irq_dispatch = ar5312_irq_dispatch;
1668 + for (i = 0; i < AR5312_MISC_IRQ_COUNT; i++) {
1669 + int irq = AR231X_MISC_IRQ_BASE + i;
1670 +
1671 + irq_set_chip_and_handler(irq, &ar5312_misc_irq_chip,
1672 + handle_level_irq);
1673 + }
1674 + setup_irq(AR5312_MISC_IRQ_AHB_PROC, &ar5312_ahb_proc_interrupt);
1675 + irq_set_chained_handler(AR5312_IRQ_MISC_INTRS, ar5312_misc_irq_handler);
1676 +}
1677 +
1678 +static void ar5312_device_reset_set(u32 mask)
1679 +{
1680 + u32 val;
1681 +
1682 + val = ar231x_read_reg(AR5312_RESET);
1683 + ar231x_write_reg(AR5312_RESET, val | mask);
1684 +}
1685 +
1686 +static void ar5312_device_reset_clear(u32 mask)
1687 +{
1688 + u32 val;
1689 +
1690 + val = ar231x_read_reg(AR5312_RESET);
1691 + ar231x_write_reg(AR5312_RESET, val & ~mask);
1692 +}
1693 +
1694 +static struct physmap_flash_data ar5312_flash_data = {
1695 + .width = 2,
1696 +};
1697 +
1698 +static struct resource ar5312_flash_resource = {
1699 + .start = AR5312_FLASH,
1700 + .end = AR5312_FLASH + 0x800000 - 1,
1701 + .flags = IORESOURCE_MEM,
1702 +};
1703 +
1704 +static struct ar231x_eth ar5312_eth0_data = {
1705 + .reset_set = ar5312_device_reset_set,
1706 + .reset_clear = ar5312_device_reset_clear,
1707 + .reset_mac = AR5312_RESET_ENET0,
1708 + .reset_phy = AR5312_RESET_EPHY0,
1709 + .config = &ar231x_board,
1710 +};
1711 +
1712 +static struct ar231x_eth ar5312_eth1_data = {
1713 + .reset_set = ar5312_device_reset_set,
1714 + .reset_clear = ar5312_device_reset_clear,
1715 + .reset_mac = AR5312_RESET_ENET1,
1716 + .reset_phy = AR5312_RESET_EPHY1,
1717 + .config = &ar231x_board,
1718 +};
1719 +
1720 +static struct platform_device ar5312_physmap_flash = {
1721 + .name = "physmap-flash",
1722 + .id = 0,
1723 + .dev.platform_data = &ar5312_flash_data,
1724 + .resource = &ar5312_flash_resource,
1725 + .num_resources = 1,
1726 +};
1727 +
1728 +#ifdef CONFIG_LEDS_GPIO
1729 +static struct gpio_led ar5312_leds[] = {
1730 + { .name = "wlan", .gpio = 0, .active_low = 1, },
1731 +};
1732 +
1733 +static const struct gpio_led_platform_data ar5312_led_data = {
1734 + .num_leds = ARRAY_SIZE(ar5312_leds),
1735 + .leds = (void *)ar5312_leds,
1736 +};
1737 +
1738 +static struct platform_device ar5312_gpio_leds = {
1739 + .name = "leds-gpio",
1740 + .id = -1,
1741 + .dev.platform_data = (void *)&ar5312_led_data,
1742 +};
1743 +#endif
1744 +
1745 +/*
1746 + * NB: This mapping size is larger than the actual flash size,
1747 + * but this shouldn't be a problem here, because the flash
1748 + * will simply be mapped multiple times.
1749 + */
1750 +static char __init *ar5312_flash_limit(void)
1751 +{
1752 + u32 ctl;
1753 + /*
1754 + * Configure flash bank 0.
1755 + * Assume 8M window size. Flash will be aliased if it's smaller
1756 + */
1757 + ctl = FLASHCTL_E |
1758 + FLASHCTL_AC_8M |
1759 + FLASHCTL_RBLE |
1760 + (0x01 << FLASHCTL_IDCY_S) |
1761 + (0x07 << FLASHCTL_WST1_S) |
1762 + (0x07 << FLASHCTL_WST2_S) |
1763 + (ar231x_read_reg(AR5312_FLASHCTL0) & FLASHCTL_MW);
1764 +
1765 + ar231x_write_reg(AR5312_FLASHCTL0, ctl);
1766 +
1767 + /* Disable other flash banks */
1768 + ar231x_write_reg(AR5312_FLASHCTL1,
1769 + ar231x_read_reg(AR5312_FLASHCTL1) &
1770 + ~(FLASHCTL_E | FLASHCTL_AC));
1771 +
1772 + ar231x_write_reg(AR5312_FLASHCTL2,
1773 + ar231x_read_reg(AR5312_FLASHCTL2) &
1774 + ~(FLASHCTL_E | FLASHCTL_AC));
1775 +
1776 + return (char *)KSEG1ADDR(AR5312_FLASH + 0x800000);
1777 +}
1778 +
1779 +int __init ar5312_init_devices(void)
1780 +{
1781 + struct ar231x_boarddata *config;
1782 + u32 fctl = 0;
1783 + u8 *c;
1784 +
1785 + if (!is_5312())
1786 + return 0;
1787 +
1788 + /* Locate board/radio config data */
1789 + ar231x_find_config(ar5312_flash_limit());
1790 + config = ar231x_board.config;
1791 +
1792 + /* AR2313 has CPU minor rev. 10 */
1793 + if ((current_cpu_data.processor_id & 0xff) == 0x0a)
1794 + ar231x_devtype = DEV_TYPE_AR2313;
1795 +
1796 + /* AR2312 shares the same Silicon ID as AR5312 */
1797 + else if (config->flags & BD_ISCASPER)
1798 + ar231x_devtype = DEV_TYPE_AR2312;
1799 +
1800 + /* Everything else is probably AR5312 or compatible */
1801 + else
1802 + ar231x_devtype = DEV_TYPE_AR5312;
1803 +
1804 + /* fixup flash width */
1805 + fctl = ar231x_read_reg(AR5312_FLASHCTL) & FLASHCTL_MW;
1806 + switch (fctl) {
1807 + case FLASHCTL_MW16:
1808 + ar5312_flash_data.width = 2;
1809 + break;
1810 + case FLASHCTL_MW8:
1811 + default:
1812 + ar5312_flash_data.width = 1;
1813 + break;
1814 + }
1815 +
1816 + platform_device_register(&ar5312_physmap_flash);
1817 +
1818 +#ifdef CONFIG_LEDS_GPIO
1819 + ar5312_leds[0].gpio = config->sys_led_gpio;
1820 + platform_device_register(&ar5312_gpio_leds);
1821 +#endif
1822 +
1823 + /* Fix up MAC addresses if necessary */
1824 + if (is_broadcast_ether_addr(config->enet0_mac))
1825 + ether_addr_copy(config->enet0_mac, config->enet1_mac);
1826 +
1827 + /* If ENET0 and ENET1 have the same mac address,
1828 + * increment the one from ENET1 */
1829 + if (ether_addr_equal(config->enet0_mac, config->enet1_mac)) {
1830 + c = config->enet1_mac + 5;
1831 + while ((c >= config->enet1_mac) && !(++(*c)))
1832 + c--;
1833 + }
1834 +
1835 + switch (ar231x_devtype) {
1836 + case DEV_TYPE_AR5312:
1837 + ar5312_eth0_data.macaddr = config->enet0_mac;
1838 + ar231x_add_ethernet(0, AR5312_ENET0, "eth0_mii",
1839 + AR5312_ENET0_MII, AR5312_IRQ_ENET0_INTRS,
1840 + &ar5312_eth0_data);
1841 +
1842 + ar5312_eth1_data.macaddr = config->enet1_mac;
1843 + ar231x_add_ethernet(1, AR5312_ENET1, "eth1_mii",
1844 + AR5312_ENET1_MII, AR5312_IRQ_ENET1_INTRS,
1845 + &ar5312_eth1_data);
1846 +
1847 + if (!ar231x_board.radio)
1848 + return 0;
1849 +
1850 + if (!(config->flags & BD_WLAN0))
1851 + break;
1852 +
1853 + ar231x_add_wmac(0, AR5312_WLAN0, AR5312_IRQ_WLAN0_INTRS);
1854 + break;
1855 + /*
1856 + * AR2312/3 ethernet uses the PHY of ENET0, but the MAC
1857 + * of ENET1. Atheros calls it 'twisted' for a reason :)
1858 + */
1859 + case DEV_TYPE_AR2312:
1860 + case DEV_TYPE_AR2313:
1861 + ar5312_eth1_data.reset_phy = ar5312_eth0_data.reset_phy;
1862 + ar5312_eth1_data.macaddr = config->enet0_mac;
1863 + ar231x_add_ethernet(1, AR5312_ENET1, "eth0_mii",
1864 + AR5312_ENET0_MII, AR5312_IRQ_ENET1_INTRS,
1865 + &ar5312_eth1_data);
1866 +
1867 + if (!ar231x_board.radio)
1868 + return 0;
1869 + break;
1870 + default:
1871 + break;
1872 + }
1873 +
1874 + if (config->flags & BD_WLAN1)
1875 + ar231x_add_wmac(1, AR5312_WLAN1, AR5312_IRQ_WLAN1_INTRS);
1876 +
1877 + return 0;
1878 +}
1879 +
1880 +static void ar5312_restart(char *command)
1881 +{
1882 + /* reset the system */
1883 + local_irq_disable();
1884 + while (1)
1885 + ar231x_write_reg(AR5312_RESET, AR5312_RESET_SYSTEM);
1886 +}
1887 +
1888 +/*
1889 + * This table is indexed by bits 5..4 of the CLOCKCTL1 register
1890 + * to determine the predevisor value.
1891 + */
1892 +static int clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
1893 +
1894 +static int __init
1895 +ar5312_cpu_frequency(void)
1896 +{
1897 + unsigned int scratch;
1898 + unsigned int predivide_mask, predivide_shift;
1899 + unsigned int multiplier_mask, multiplier_shift;
1900 + unsigned int clock_ctl1, predivide_select, predivisor, multiplier;
1901 + unsigned int doubler_mask;
1902 + u16 devid;
1903 +
1904 + /* Trust the bootrom's idea of cpu frequency. */
1905 + scratch = ar231x_read_reg(AR5312_SCRATCH);
1906 + if (scratch)
1907 + return scratch;
1908 +
1909 + devid = ar231x_read_reg(AR5312_REV);
1910 + devid &= AR5312_REV_MAJ;
1911 + devid >>= AR5312_REV_MAJ_S;
1912 + if (devid == AR5312_REV_MAJ_AR2313) {
1913 + predivide_mask = AR2313_CLOCKCTL1_PREDIVIDE_MASK;
1914 + predivide_shift = AR2313_CLOCKCTL1_PREDIVIDE_SHIFT;
1915 + multiplier_mask = AR2313_CLOCKCTL1_MULTIPLIER_MASK;
1916 + multiplier_shift = AR2313_CLOCKCTL1_MULTIPLIER_SHIFT;
1917 + doubler_mask = AR2313_CLOCKCTL1_DOUBLER_MASK;
1918 + } else { /* AR5312 and AR2312 */
1919 + predivide_mask = AR5312_CLOCKCTL1_PREDIVIDE_MASK;
1920 + predivide_shift = AR5312_CLOCKCTL1_PREDIVIDE_SHIFT;
1921 + multiplier_mask = AR5312_CLOCKCTL1_MULTIPLIER_MASK;
1922 + multiplier_shift = AR5312_CLOCKCTL1_MULTIPLIER_SHIFT;
1923 + doubler_mask = AR5312_CLOCKCTL1_DOUBLER_MASK;
1924 + }
1925 +
1926 + /*
1927 + * Clocking is derived from a fixed 40MHz input clock.
1928 + *
1929 + * cpu_freq = input_clock * MULT (where MULT is PLL multiplier)
1930 + * sys_freq = cpu_freq / 4 (used for APB clock, serial,
1931 + * flash, Timer, Watchdog Timer)
1932 + *
1933 + * cnt_freq = cpu_freq / 2 (use for CPU count/compare)
1934 + *
1935 + * So, for example, with a PLL multiplier of 5, we have
1936 + *
1937 + * cpu_freq = 200MHz
1938 + * sys_freq = 50MHz
1939 + * cnt_freq = 100MHz
1940 + *
1941 + * We compute the CPU frequency, based on PLL settings.
1942 + */
1943 +
1944 + clock_ctl1 = ar231x_read_reg(AR5312_CLOCKCTL1);
1945 + predivide_select = (clock_ctl1 & predivide_mask) >> predivide_shift;
1946 + predivisor = clockctl1_predivide_table[predivide_select];
1947 + multiplier = (clock_ctl1 & multiplier_mask) >> multiplier_shift;
1948 +
1949 + if (clock_ctl1 & doubler_mask)
1950 + multiplier = multiplier << 1;
1951 +
1952 + return (40000000 / predivisor) * multiplier;
1953 +}
1954 +
1955 +static inline int
1956 +ar5312_sys_frequency(void)
1957 +{
1958 + return ar5312_cpu_frequency() / 4;
1959 +}
1960 +
1961 +void __init
1962 +ar5312_time_init(void)
1963 +{
1964 + if (!is_5312())
1965 + return;
1966 +
1967 + mips_hpt_frequency = ar5312_cpu_frequency() / 2;
1968 +}
1969 +
1970 +void __init
1971 +ar5312_prom_init(void)
1972 +{
1973 + u32 memsize, memcfg, bank0AC, bank1AC;
1974 + u32 devid;
1975 +
1976 + if (!is_5312())
1977 + return;
1978 +
1979 + /* Detect memory size */
1980 + memcfg = ar231x_read_reg(AR5312_MEM_CFG1);
1981 + bank0AC = (memcfg & MEM_CFG1_AC0) >> MEM_CFG1_AC0_S;
1982 + bank1AC = (memcfg & MEM_CFG1_AC1) >> MEM_CFG1_AC1_S;
1983 + memsize = (bank0AC ? (1 << (bank0AC+1)) : 0) +
1984 + (bank1AC ? (1 << (bank1AC+1)) : 0);
1985 + memsize <<= 20;
1986 + add_memory_region(0, memsize, BOOT_MEM_RAM);
1987 +
1988 + devid = ar231x_read_reg(AR5312_REV);
1989 + devid >>= AR5312_REV_WMAC_MIN_S;
1990 + devid &= AR5312_REV_CHIP;
1991 + ar231x_board.devid = (u16)devid;
1992 +}
1993 +
1994 +void __init
1995 +ar5312_plat_setup(void)
1996 +{
1997 + if (!is_5312())
1998 + return;
1999 +
2000 + /* Clear any lingering AHB errors */
2001 + ar231x_read_reg(AR5312_PROCADDR);
2002 + ar231x_read_reg(AR5312_DMAADDR);
2003 + ar231x_write_reg(AR5312_WD_CTRL, AR5312_WD_CTRL_IGNORE_EXPIRATION);
2004 +
2005 + _machine_restart = ar5312_restart;
2006 + ar231x_serial_setup(AR5312_UART0, AR5312_MISC_IRQ_UART0,
2007 + ar5312_sys_frequency());
2008 +}
2009 +
2010 --- /dev/null
2011 +++ b/arch/mips/ar231x/ar2315.c
2012 @@ -0,0 +1,570 @@
2013 +/*
2014 + * This file is subject to the terms and conditions of the GNU General Public
2015 + * License. See the file "COPYING" in the main directory of this archive
2016 + * for more details.
2017 + *
2018 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
2019 + * Copyright (C) 2006 FON Technology, SL.
2020 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
2021 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
2022 + * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
2023 + */
2024 +
2025 +/*
2026 + * Platform devices for Atheros SoCs
2027 + */
2028 +
2029 +#include <generated/autoconf.h>
2030 +#include <linux/init.h>
2031 +#include <linux/module.h>
2032 +#include <linux/types.h>
2033 +#include <linux/string.h>
2034 +#include <linux/platform_device.h>
2035 +#include <linux/kernel.h>
2036 +#include <linux/reboot.h>
2037 +#include <linux/delay.h>
2038 +#include <linux/leds.h>
2039 +#include <linux/gpio.h>
2040 +#include <asm/bootinfo.h>
2041 +#include <asm/reboot.h>
2042 +#include <asm/time.h>
2043 +#include <linux/irq.h>
2044 +#include <linux/io.h>
2045 +
2046 +#include <ar231x_platform.h>
2047 +#include <ar2315_regs.h>
2048 +#include <ar231x.h>
2049 +#include "devices.h"
2050 +#include "ar2315.h"
2051 +
2052 +static u32 gpiointmask, gpiointval;
2053 +
2054 +static void ar2315_gpio_irq_handler(unsigned irq, struct irq_desc *desc)
2055 +{
2056 + u32 pend;
2057 + int bit = -1;
2058 +
2059 + /* only do one gpio interrupt at a time */
2060 + pend = (ar231x_read_reg(AR2315_GPIO_DI) ^ gpiointval) & gpiointmask;
2061 +
2062 + if (pend) {
2063 + bit = fls(pend) - 1;
2064 + pend &= ~(1 << bit);
2065 + gpiointval ^= (1 << bit);
2066 + }
2067 +
2068 + if (!pend)
2069 + ar231x_write_reg(AR2315_ISR, AR2315_ISR_GPIO);
2070 +
2071 + /* Enable interrupt with edge detection */
2072 + if ((ar231x_read_reg(AR2315_GPIO_DIR) & AR2315_GPIO_DIR_M(bit)) !=
2073 + AR2315_GPIO_DIR_I(bit))
2074 + return;
2075 +
2076 + if (bit >= 0)
2077 + generic_handle_irq(AR231X_GPIO_IRQ_BASE + bit);
2078 +}
2079 +
2080 +static void ar2315_misc_irq_handler(unsigned irq, struct irq_desc *desc)
2081 +{
2082 + unsigned int misc_intr = ar231x_read_reg(AR2315_ISR) &
2083 + ar231x_read_reg(AR2315_IMR);
2084 +
2085 + if (misc_intr & AR2315_ISR_SPI)
2086 + generic_handle_irq(AR2315_MISC_IRQ_SPI);
2087 + else if (misc_intr & AR2315_ISR_TIMER)
2088 + generic_handle_irq(AR2315_MISC_IRQ_TIMER);
2089 + else if (misc_intr & AR2315_ISR_AHB)
2090 + generic_handle_irq(AR2315_MISC_IRQ_AHB);
2091 + else if (misc_intr & AR2315_ISR_GPIO)
2092 + generic_handle_irq(AR2315_MISC_IRQ_GPIO);
2093 + else if (misc_intr & AR2315_ISR_UART0)
2094 + generic_handle_irq(AR2315_MISC_IRQ_UART0);
2095 + else if (misc_intr & AR2315_ISR_WD) {
2096 + ar231x_write_reg(AR2315_ISR, AR2315_ISR_WD);
2097 + generic_handle_irq(AR2315_MISC_IRQ_WATCHDOG);
2098 + } else
2099 + spurious_interrupt();
2100 +}
2101 +
2102 +/*
2103 + * Called when an interrupt is received, this function
2104 + * determines exactly which interrupt it was, and it
2105 + * invokes the appropriate handler.
2106 + *
2107 + * Implicitly, we also define interrupt priority by
2108 + * choosing which to dispatch first.
2109 + */
2110 +static asmlinkage void
2111 +ar2315_irq_dispatch(void)
2112 +{
2113 + int pending = read_c0_status() & read_c0_cause();
2114 +
2115 + if (pending & CAUSEF_IP3)
2116 + do_IRQ(AR2315_IRQ_WLAN0_INTRS);
2117 + else if (pending & CAUSEF_IP4)
2118 + do_IRQ(AR2315_IRQ_ENET0_INTRS);
2119 + else if (pending & CAUSEF_IP2)
2120 + do_IRQ(AR2315_IRQ_MISC_INTRS);
2121 + else if (pending & CAUSEF_IP7)
2122 + do_IRQ(AR231X_IRQ_CPU_CLOCK);
2123 + else
2124 + spurious_interrupt();
2125 +}
2126 +
2127 +static void ar2315_set_gpiointmask(int gpio, int level)
2128 +{
2129 + u32 reg;
2130 +
2131 + reg = ar231x_read_reg(AR2315_GPIO_INT);
2132 + reg &= ~(AR2315_GPIO_INT_M | AR2315_GPIO_INT_LVL_M);
2133 + reg |= gpio | AR2315_GPIO_INT_LVL(level);
2134 + ar231x_write_reg(AR2315_GPIO_INT, reg);
2135 +}
2136 +
2137 +static void ar2315_gpio_irq_unmask(struct irq_data *d)
2138 +{
2139 + unsigned int gpio = d->irq - AR231X_GPIO_IRQ_BASE;
2140 +
2141 + /* Enable interrupt with edge detection */
2142 + if ((ar231x_read_reg(AR2315_GPIO_DIR) & AR2315_GPIO_DIR_M(gpio)) !=
2143 + AR2315_GPIO_DIR_I(gpio))
2144 + return;
2145 +
2146 + gpiointmask |= (1 << gpio);
2147 + ar2315_set_gpiointmask(gpio, 3);
2148 +}
2149 +
2150 +static void ar2315_gpio_irq_mask(struct irq_data *d)
2151 +{
2152 + unsigned int gpio = d->irq - AR231X_GPIO_IRQ_BASE;
2153 +
2154 + /* Disable interrupt */
2155 + gpiointmask &= ~(1 << gpio);
2156 + ar2315_set_gpiointmask(gpio, 0);
2157 +}
2158 +
2159 +static struct irq_chip ar2315_gpio_irq_chip = {
2160 + .name = "AR2315-GPIO",
2161 + .irq_unmask = ar2315_gpio_irq_unmask,
2162 + .irq_mask = ar2315_gpio_irq_mask,
2163 +};
2164 +
2165 +static void
2166 +ar2315_misc_irq_unmask(struct irq_data *d)
2167 +{
2168 + unsigned int imr;
2169 +
2170 + imr = ar231x_read_reg(AR2315_IMR);
2171 + imr |= 1 << (d->irq - AR231X_MISC_IRQ_BASE);
2172 + ar231x_write_reg(AR2315_IMR, imr);
2173 +}
2174 +
2175 +static void
2176 +ar2315_misc_irq_mask(struct irq_data *d)
2177 +{
2178 + unsigned int imr;
2179 +
2180 + imr = ar231x_read_reg(AR2315_IMR);
2181 + imr &= ~(1 << (d->irq - AR231X_MISC_IRQ_BASE));
2182 + ar231x_write_reg(AR2315_IMR, imr);
2183 +}
2184 +
2185 +static struct irq_chip ar2315_misc_irq_chip = {
2186 + .name = "AR2315-MISC",
2187 + .irq_unmask = ar2315_misc_irq_unmask,
2188 + .irq_mask = ar2315_misc_irq_mask,
2189 +};
2190 +
2191 +static irqreturn_t ar2315_ahb_proc_handler(int cpl, void *dev_id)
2192 +{
2193 + ar231x_write_reg(AR2315_AHB_ERR0, AHB_ERROR_DET);
2194 + ar231x_read_reg(AR2315_AHB_ERR1);
2195 +
2196 + pr_emerg("AHB fatal error\n");
2197 + machine_restart("AHB error"); /* Catastrophic failure */
2198 +
2199 + return IRQ_HANDLED;
2200 +}
2201 +
2202 +static struct irqaction ar2315_ahb_proc_interrupt = {
2203 + .handler = ar2315_ahb_proc_handler,
2204 + .name = "ar2315_ahb_proc_interrupt",
2205 +};
2206 +
2207 +void
2208 +ar2315_irq_init(void)
2209 +{
2210 + int i;
2211 +
2212 + if (!is_2315())
2213 + return;
2214 +
2215 + ar231x_irq_dispatch = ar2315_irq_dispatch;
2216 + gpiointval = ar231x_read_reg(AR2315_GPIO_DI);
2217 + for (i = 0; i < AR2315_MISC_IRQ_COUNT; i++) {
2218 + int irq = AR231X_MISC_IRQ_BASE + i;
2219 +
2220 + irq_set_chip_and_handler(irq, &ar2315_misc_irq_chip,
2221 + handle_level_irq);
2222 + }
2223 + for (i = 0; i < AR2315_NUM_GPIO; i++) {
2224 + int irq = AR231X_GPIO_IRQ_BASE + i;
2225 +
2226 + irq_set_chip_and_handler(irq, &ar2315_gpio_irq_chip,
2227 + handle_level_irq);
2228 + }
2229 + irq_set_chained_handler(AR2315_MISC_IRQ_GPIO, ar2315_gpio_irq_handler);
2230 + setup_irq(AR2315_MISC_IRQ_AHB, &ar2315_ahb_proc_interrupt);
2231 + irq_set_chained_handler(AR2315_IRQ_MISC_INTRS, ar2315_misc_irq_handler);
2232 +}
2233 +
2234 +/*
2235 + * gpiolib implementation
2236 + */
2237 +static int
2238 +ar2315_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
2239 +{
2240 + return (ar231x_read_reg(AR2315_GPIO_DI) >> gpio) & 1;
2241 +}
2242 +
2243 +static void
2244 +ar2315_gpio_set_value(struct gpio_chip *chip, unsigned gpio, int value)
2245 +{
2246 + u32 reg = ar231x_read_reg(AR2315_GPIO_DO);
2247 +
2248 + reg = value ? reg | (1 << gpio) : reg & ~(1 << gpio);
2249 + ar231x_write_reg(AR2315_GPIO_DO, reg);
2250 +}
2251 +
2252 +static int
2253 +ar2315_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
2254 +{
2255 + ar231x_mask_reg(AR2315_GPIO_DIR, 1 << gpio, 0);
2256 + return 0;
2257 +}
2258 +
2259 +static int
2260 +ar2315_gpio_direction_output(struct gpio_chip *chip, unsigned gpio, int value)
2261 +{
2262 + ar231x_mask_reg(AR2315_GPIO_DIR, 0, 1 << gpio);
2263 + ar2315_gpio_set_value(chip, gpio, value);
2264 + return 0;
2265 +}
2266 +
2267 +static int ar2315_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
2268 +{
2269 + return AR231X_GPIO_IRQ_BASE + gpio;
2270 +}
2271 +
2272 +static struct gpio_chip ar2315_gpio_chip = {
2273 + .label = "ar2315-gpio",
2274 + .direction_input = ar2315_gpio_direction_input,
2275 + .direction_output = ar2315_gpio_direction_output,
2276 + .set = ar2315_gpio_set_value,
2277 + .get = ar2315_gpio_get_value,
2278 + .to_irq = ar2315_gpio_to_irq,
2279 + .base = 0,
2280 + .ngpio = AR2315_NUM_GPIO, /* 22 */
2281 +};
2282 +
2283 +/* end of gpiolib */
2284 +
2285 +static void ar2315_device_reset_set(u32 mask)
2286 +{
2287 + u32 val;
2288 +
2289 + val = ar231x_read_reg(AR2315_RESET);
2290 + ar231x_write_reg(AR2315_RESET, val | mask);
2291 +}
2292 +
2293 +static void ar2315_device_reset_clear(u32 mask)
2294 +{
2295 + u32 val;
2296 +
2297 + val = ar231x_read_reg(AR2315_RESET);
2298 + ar231x_write_reg(AR2315_RESET, val & ~mask);
2299 +}
2300 +
2301 +static struct ar231x_eth ar2315_eth_data = {
2302 + .reset_set = ar2315_device_reset_set,
2303 + .reset_clear = ar2315_device_reset_clear,
2304 + .reset_mac = AR2315_RESET_ENET0,
2305 + .reset_phy = AR2315_RESET_EPHY0,
2306 + .config = &ar231x_board,
2307 +};
2308 +
2309 +static struct resource ar2315_spiflash_res[] = {
2310 + {
2311 + .name = "spiflash_read",
2312 + .flags = IORESOURCE_MEM,
2313 + .start = AR2315_SPI_READ,
2314 + .end = AR2315_SPI_READ + 0x1000000 - 1,
2315 + },
2316 + {
2317 + .name = "spiflash_mmr",
2318 + .flags = IORESOURCE_MEM,
2319 + .start = AR2315_SPI_MMR,
2320 + .end = AR2315_SPI_MMR + 12 - 1,
2321 + },
2322 +};
2323 +
2324 +static struct platform_device ar2315_spiflash = {
2325 + .id = 0,
2326 + .name = "ar2315-spiflash",
2327 + .resource = ar2315_spiflash_res,
2328 + .num_resources = ARRAY_SIZE(ar2315_spiflash_res)
2329 +};
2330 +
2331 +static struct resource ar2315_wdt_res[] = {
2332 + {
2333 + .flags = IORESOURCE_MEM,
2334 + .start = AR2315_WD,
2335 + .end = AR2315_WD + 8 - 1,
2336 + },
2337 + {
2338 + .flags = IORESOURCE_IRQ,
2339 + .start = AR2315_MISC_IRQ_WATCHDOG,
2340 + .end = AR2315_MISC_IRQ_WATCHDOG,
2341 + }
2342 +};
2343 +
2344 +static struct platform_device ar2315_wdt = {
2345 + .id = 0,
2346 + .name = "ar2315-wdt",
2347 + .resource = ar2315_wdt_res,
2348 + .num_resources = ARRAY_SIZE(ar2315_wdt_res)
2349 +};
2350 +
2351 +/*
2352 + * NB: We use mapping size that is larger than the actual flash size,
2353 + * but this shouldn't be a problem here, because the flash will simply
2354 + * be mapped multiple times.
2355 + */
2356 +static u8 __init *ar2315_flash_limit(void)
2357 +{
2358 + return (u8 *)KSEG1ADDR(ar2315_spiflash_res[0].end + 1);
2359 +}
2360 +
2361 +#ifdef CONFIG_LEDS_GPIO
2362 +static struct gpio_led ar2315_leds[6];
2363 +static struct gpio_led_platform_data ar2315_led_data = {
2364 + .leds = (void *)ar2315_leds,
2365 +};
2366 +
2367 +static struct platform_device ar2315_gpio_leds = {
2368 + .name = "leds-gpio",
2369 + .id = -1,
2370 + .dev = {
2371 + .platform_data = (void *)&ar2315_led_data,
2372 + }
2373 +};
2374 +
2375 +static void __init
2376 +ar2315_init_gpio_leds(void)
2377 +{
2378 + static char led_names[6][6];
2379 + int i, led = 0;
2380 +
2381 + ar2315_led_data.num_leds = 0;
2382 + for (i = 1; i < 8; i++) {
2383 + if ((i == AR2315_RESET_GPIO) ||
2384 + (i == ar231x_board.config->reset_config_gpio))
2385 + continue;
2386 +
2387 + if (i == ar231x_board.config->sys_led_gpio)
2388 + strcpy(led_names[led], "wlan");
2389 + else
2390 + sprintf(led_names[led], "gpio%d", i);
2391 +
2392 + ar2315_leds[led].name = led_names[led];
2393 + ar2315_leds[led].gpio = i;
2394 + ar2315_leds[led].active_low = 0;
2395 + led++;
2396 + }
2397 + ar2315_led_data.num_leds = led;
2398 + platform_device_register(&ar2315_gpio_leds);
2399 +}
2400 +#else
2401 +static inline void ar2315_init_gpio_leds(void)
2402 +{
2403 +}
2404 +#endif
2405 +
2406 +int __init
2407 +ar2315_init_devices(void)
2408 +{
2409 + if (!is_2315())
2410 + return 0;
2411 +
2412 + /* Find board configuration */
2413 + ar231x_find_config(ar2315_flash_limit());
2414 + ar2315_eth_data.macaddr = ar231x_board.config->enet0_mac;
2415 +
2416 + ar2315_init_gpio_leds();
2417 + platform_device_register(&ar2315_wdt);
2418 + platform_device_register(&ar2315_spiflash);
2419 + ar231x_add_ethernet(0, AR2315_ENET0, "eth0_mii", AR2315_ENET0_MII,
2420 + AR2315_IRQ_ENET0_INTRS, &ar2315_eth_data);
2421 + ar231x_add_wmac(0, AR2315_WLAN0, AR2315_IRQ_WLAN0_INTRS);
2422 +
2423 + return 0;
2424 +}
2425 +
2426 +static void
2427 +ar2315_restart(char *command)
2428 +{
2429 + void (*mips_reset_vec)(void) = (void *)0xbfc00000;
2430 +
2431 + local_irq_disable();
2432 +
2433 + /* try reset the system via reset control */
2434 + ar231x_write_reg(AR2315_COLD_RESET, AR2317_RESET_SYSTEM);
2435 +
2436 + /* Cold reset does not work on the AR2315/6, use the GPIO reset bits
2437 + * a workaround. Give it some time to attempt a gpio based hardware
2438 + * reset (atheros reference design workaround) */
2439 + gpio_request_one(AR2315_RESET_GPIO, GPIOF_OUT_INIT_LOW, "Reset");
2440 + mdelay(100);
2441 +
2442 + /* Some boards (e.g. Senao EOC-2610) don't implement the reset logic
2443 + * workaround. Attempt to jump to the mips reset location -
2444 + * the boot loader itself might be able to recover the system */
2445 + mips_reset_vec();
2446 +}
2447 +
2448 +/*
2449 + * This table is indexed by bits 5..4 of the CLOCKCTL1 register
2450 + * to determine the predevisor value.
2451 + */
2452 +static int clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
2453 +static int pllc_divide_table[5] __initdata = { 2, 3, 4, 6, 3 };
2454 +
2455 +static unsigned int __init
2456 +ar2315_sys_clk(unsigned int clock_ctl)
2457 +{
2458 + unsigned int pllc_ctrl, cpu_div;
2459 + unsigned int pllc_out, refdiv, fdiv, divby2;
2460 + unsigned int clk_div;
2461 +
2462 + pllc_ctrl = ar231x_read_reg(AR2315_PLLC_CTL);
2463 + refdiv = (pllc_ctrl & PLLC_REF_DIV_M) >> PLLC_REF_DIV_S;
2464 + refdiv = clockctl1_predivide_table[refdiv];
2465 + fdiv = (pllc_ctrl & PLLC_FDBACK_DIV_M) >> PLLC_FDBACK_DIV_S;
2466 + divby2 = (pllc_ctrl & PLLC_ADD_FDBACK_DIV_M) >> PLLC_ADD_FDBACK_DIV_S;
2467 + divby2 += 1;
2468 + pllc_out = (40000000/refdiv)*(2*divby2)*fdiv;
2469 +
2470 + /* clkm input selected */
2471 + switch (clock_ctl & CPUCLK_CLK_SEL_M) {
2472 + case 0:
2473 + case 1:
2474 + clk_div = pllc_divide_table[(pllc_ctrl & PLLC_CLKM_DIV_M) >>
2475 + PLLC_CLKM_DIV_S];
2476 + break;
2477 + case 2:
2478 + clk_div = pllc_divide_table[(pllc_ctrl & PLLC_CLKC_DIV_M) >>
2479 + PLLC_CLKC_DIV_S];
2480 + break;
2481 + default:
2482 + pllc_out = 40000000;
2483 + clk_div = 1;
2484 + break;
2485 + }
2486 +
2487 + cpu_div = (clock_ctl & CPUCLK_CLK_DIV_M) >> CPUCLK_CLK_DIV_S;
2488 + cpu_div = cpu_div * 2 ?: 1;
2489 +
2490 + return pllc_out / (clk_div * cpu_div);
2491 +}
2492 +
2493 +static inline unsigned int
2494 +ar2315_cpu_frequency(void)
2495 +{
2496 + return ar2315_sys_clk(ar231x_read_reg(AR2315_CPUCLK));
2497 +}
2498 +
2499 +static inline unsigned int
2500 +ar2315_apb_frequency(void)
2501 +{
2502 + return ar2315_sys_clk(ar231x_read_reg(AR2315_AMBACLK));
2503 +}
2504 +
2505 +void __init
2506 +ar2315_time_init(void)
2507 +{
2508 + if (!is_2315())
2509 + return;
2510 +
2511 + mips_hpt_frequency = ar2315_cpu_frequency() / 2;
2512 +}
2513 +
2514 +static int __init
2515 +ar2315_gpio_init(void)
2516 +{
2517 + int ret = gpiochip_add(&ar2315_gpio_chip);
2518 +
2519 + if (ret) {
2520 + pr_err("%s: failed to add gpiochip\n", ar2315_gpio_chip.label);
2521 + return ret;
2522 + }
2523 + pr_info("%s: registered %d GPIOs\n", ar2315_gpio_chip.label,
2524 + ar2315_gpio_chip.ngpio);
2525 + return ret;
2526 +}
2527 +
2528 +void __init
2529 +ar2315_prom_init(void)
2530 +{
2531 + u32 memsize, memcfg, devid;
2532 +
2533 + if (!is_2315())
2534 + return;
2535 +
2536 + memcfg = ar231x_read_reg(AR2315_MEM_CFG);
2537 + memsize = 1 + ((memcfg & SDRAM_DATA_WIDTH_M) >> SDRAM_DATA_WIDTH_S);
2538 + memsize <<= 1 + ((memcfg & SDRAM_COL_WIDTH_M) >> SDRAM_COL_WIDTH_S);
2539 + memsize <<= 1 + ((memcfg & SDRAM_ROW_WIDTH_M) >> SDRAM_ROW_WIDTH_S);
2540 + memsize <<= 3;
2541 + add_memory_region(0, memsize, BOOT_MEM_RAM);
2542 +
2543 + /* Detect the hardware based on the device ID */
2544 + devid = ar231x_read_reg(AR2315_SREV) & AR2315_REV_CHIP;
2545 + switch (devid) {
2546 + case 0x91: /* Need to check */
2547 + ar231x_devtype = DEV_TYPE_AR2318;
2548 + break;
2549 + case 0x90:
2550 + ar231x_devtype = DEV_TYPE_AR2317;
2551 + break;
2552 + case 0x87:
2553 + ar231x_devtype = DEV_TYPE_AR2316;
2554 + break;
2555 + case 0x86:
2556 + default:
2557 + ar231x_devtype = DEV_TYPE_AR2315;
2558 + break;
2559 + }
2560 + ar2315_gpio_init();
2561 + ar231x_board.devid = devid;
2562 +}
2563 +
2564 +void __init
2565 +ar2315_plat_setup(void)
2566 +{
2567 + u32 config;
2568 +
2569 + if (!is_2315())
2570 + return;
2571 +
2572 + /* Clear any lingering AHB errors */
2573 + config = read_c0_config();
2574 + write_c0_config(config & ~0x3);
2575 + ar231x_write_reg(AR2315_AHB_ERR0, AHB_ERROR_DET);
2576 + ar231x_read_reg(AR2315_AHB_ERR1);
2577 + ar231x_write_reg(AR2315_WDC, AR2315_WDC_IGNORE_EXPIRATION);
2578 +
2579 + _machine_restart = ar2315_restart;
2580 + ar231x_serial_setup(AR2315_UART0, AR2315_MISC_IRQ_UART0,
2581 + ar2315_apb_frequency());
2582 +}
2583 --- /dev/null
2584 +++ b/arch/mips/ar231x/ar2315.h
2585 @@ -0,0 +1,37 @@
2586 +#ifndef __AR2315_H
2587 +#define __AR2315_H
2588 +
2589 +#ifdef CONFIG_SOC_AR2315
2590 +
2591 +void ar2315_irq_init(void);
2592 +int ar2315_init_devices(void);
2593 +void ar2315_prom_init(void);
2594 +void ar2315_plat_setup(void);
2595 +void ar2315_time_init(void);
2596 +
2597 +#else
2598 +
2599 +static inline void ar2315_irq_init(void)
2600 +{
2601 +}
2602 +
2603 +static inline int ar2315_init_devices(void)
2604 +{
2605 + return 0;
2606 +}
2607 +
2608 +static inline void ar2315_prom_init(void)
2609 +{
2610 +}
2611 +
2612 +static inline void ar2315_plat_setup(void)
2613 +{
2614 +}
2615 +
2616 +static inline void ar2315_time_init(void)
2617 +{
2618 +}
2619 +
2620 +#endif
2621 +
2622 +#endif
2623 --- /dev/null
2624 +++ b/arch/mips/ar231x/ar5312.h
2625 @@ -0,0 +1,37 @@
2626 +#ifndef __AR5312_H
2627 +#define __AR5312_H
2628 +
2629 +#ifdef CONFIG_SOC_AR5312
2630 +
2631 +void ar5312_irq_init(void);
2632 +int ar5312_init_devices(void);
2633 +void ar5312_prom_init(void);
2634 +void ar5312_plat_setup(void);
2635 +void ar5312_time_init(void);
2636 +
2637 +#else
2638 +
2639 +static inline void ar5312_irq_init(void)
2640 +{
2641 +}
2642 +
2643 +static inline int ar5312_init_devices(void)
2644 +{
2645 + return 0;
2646 +}
2647 +
2648 +static inline void ar5312_prom_init(void)
2649 +{
2650 +}
2651 +
2652 +static inline void ar5312_plat_setup(void)
2653 +{
2654 +}
2655 +
2656 +static inline void ar5312_time_init(void)
2657 +{
2658 +}
2659 +
2660 +#endif
2661 +
2662 +#endif
2663 --- /dev/null
2664 +++ b/arch/mips/include/asm/mach-ar231x/ar231x.h
2665 @@ -0,0 +1,38 @@
2666 +#ifndef __ASM_MACH_AR231X_H
2667 +#define __ASM_MACH_AR231X_H
2668 +
2669 +#include <linux/types.h>
2670 +#include <linux/io.h>
2671 +
2672 +#define AR231X_MISC_IRQ_BASE 0x20
2673 +#define AR231X_GPIO_IRQ_BASE 0x30
2674 +
2675 +/* Software's idea of interrupts handled by "CPU Interrupt Controller" */
2676 +#define AR231X_IRQ_CPU_CLOCK (MIPS_CPU_IRQ_BASE+7) /* C0_CAUSE: 0x8000 */
2677 +
2678 +static inline u32
2679 +ar231x_read_reg(u32 reg)
2680 +{
2681 + return __raw_readl((void __iomem *)KSEG1ADDR(reg));
2682 +}
2683 +
2684 +static inline void
2685 +ar231x_write_reg(u32 reg, u32 val)
2686 +{
2687 + __raw_writel(val, (void __iomem *)KSEG1ADDR(reg));
2688 +}
2689 +
2690 +static inline u32
2691 +ar231x_mask_reg(u32 reg, u32 mask, u32 val)
2692 +{
2693 + u32 ret;
2694 +
2695 + ret = ar231x_read_reg(reg);
2696 + ret &= ~mask;
2697 + ret |= val;
2698 + ar231x_write_reg(reg, ret);
2699 +
2700 + return ret;
2701 +}
2702 +
2703 +#endif /* __ASM_MACH_AR231X_H */
2704 --- /dev/null
2705 +++ b/arch/mips/ar231x/devices.h
2706 @@ -0,0 +1,39 @@
2707 +#ifndef __AR231X_DEVICES_H
2708 +#define __AR231X_DEVICES_H
2709 +
2710 +enum {
2711 + /* handled by ar5312.c */
2712 + DEV_TYPE_AR2312,
2713 + DEV_TYPE_AR2313,
2714 + DEV_TYPE_AR5312,
2715 +
2716 + /* handled by ar2315.c */
2717 + DEV_TYPE_AR2315,
2718 + DEV_TYPE_AR2316,
2719 + DEV_TYPE_AR2317,
2720 + DEV_TYPE_AR2318,
2721 +
2722 + DEV_TYPE_UNKNOWN
2723 +};
2724 +
2725 +extern int ar231x_devtype;
2726 +extern struct ar231x_board_config ar231x_board;
2727 +extern asmlinkage void (*ar231x_irq_dispatch)(void);
2728 +
2729 +int ar231x_find_config(u8 *flash_limit);
2730 +void ar231x_serial_setup(u32 mapbase, int irq, unsigned int uartclk);
2731 +int ar231x_add_wmac(int nr, u32 base, int irq);
2732 +int ar231x_add_ethernet(int nr, u32 base, const char *mii_name, u32 mii_base,
2733 + int irq, void *pdata);
2734 +
2735 +static inline bool is_2315(void)
2736 +{
2737 + return (current_cpu_data.cputype == CPU_4KEC);
2738 +}
2739 +
2740 +static inline bool is_5312(void)
2741 +{
2742 + return !is_2315();
2743 +}
2744 +
2745 +#endif
2746 --- /dev/null
2747 +++ b/arch/mips/ar231x/devices.c
2748 @@ -0,0 +1,181 @@
2749 +#include <linux/kernel.h>
2750 +#include <linux/init.h>
2751 +#include <linux/serial.h>
2752 +#include <linux/serial_core.h>
2753 +#include <linux/serial_8250.h>
2754 +#include <linux/platform_device.h>
2755 +#include <asm/bootinfo.h>
2756 +
2757 +#include <ar231x_platform.h>
2758 +#include <ar231x.h>
2759 +#include "devices.h"
2760 +#include "ar5312.h"
2761 +#include "ar2315.h"
2762 +
2763 +struct ar231x_board_config ar231x_board;
2764 +int ar231x_devtype = DEV_TYPE_UNKNOWN;
2765 +
2766 +static struct resource ar231x_eth0_res[] = {
2767 + {
2768 + .name = "eth0_membase",
2769 + .flags = IORESOURCE_MEM,
2770 + },
2771 + {
2772 + .name = "eth0_mii",
2773 + .flags = IORESOURCE_MEM,
2774 + },
2775 + {
2776 + .name = "eth0_irq",
2777 + .flags = IORESOURCE_IRQ,
2778 + }
2779 +};
2780 +
2781 +static struct resource ar231x_eth1_res[] = {
2782 + {
2783 + .name = "eth1_membase",
2784 + .flags = IORESOURCE_MEM,
2785 + },
2786 + {
2787 + .name = "eth1_mii",
2788 + .flags = IORESOURCE_MEM,
2789 + },
2790 + {
2791 + .name = "eth1_irq",
2792 + .flags = IORESOURCE_IRQ,
2793 + }
2794 +};
2795 +
2796 +static struct platform_device ar231x_eth[] = {
2797 + {
2798 + .id = 0,
2799 + .name = "ar231x-eth",
2800 + .resource = ar231x_eth0_res,
2801 + .num_resources = ARRAY_SIZE(ar231x_eth0_res)
2802 + },
2803 + {
2804 + .id = 1,
2805 + .name = "ar231x-eth",
2806 + .resource = ar231x_eth1_res,
2807 + .num_resources = ARRAY_SIZE(ar231x_eth1_res)
2808 + }
2809 +};
2810 +
2811 +static struct resource ar231x_wmac0_res[] = {
2812 + {
2813 + .name = "wmac0_membase",
2814 + .flags = IORESOURCE_MEM,
2815 + },
2816 + {
2817 + .name = "wmac0_irq",
2818 + .flags = IORESOURCE_IRQ,
2819 + }
2820 +};
2821 +
2822 +static struct resource ar231x_wmac1_res[] = {
2823 + {
2824 + .name = "wmac1_membase",
2825 + .flags = IORESOURCE_MEM,
2826 + },
2827 + {
2828 + .name = "wmac1_irq",
2829 + .flags = IORESOURCE_IRQ,
2830 + }
2831 +};
2832 +
2833 +static struct platform_device ar231x_wmac[] = {
2834 + {
2835 + .id = 0,
2836 + .name = "ar231x-wmac",
2837 + .resource = ar231x_wmac0_res,
2838 + .num_resources = ARRAY_SIZE(ar231x_wmac0_res),
2839 + .dev.platform_data = &ar231x_board,
2840 + },
2841 + {
2842 + .id = 1,
2843 + .name = "ar231x-wmac",
2844 + .resource = ar231x_wmac1_res,
2845 + .num_resources = ARRAY_SIZE(ar231x_wmac1_res),
2846 + .dev.platform_data = &ar231x_board,
2847 + },
2848 +};
2849 +
2850 +static const char * const devtype_strings[] = {
2851 + [DEV_TYPE_AR5312] = "Atheros AR5312",
2852 + [DEV_TYPE_AR2312] = "Atheros AR2312",
2853 + [DEV_TYPE_AR2313] = "Atheros AR2313",
2854 + [DEV_TYPE_AR2315] = "Atheros AR2315",
2855 + [DEV_TYPE_AR2316] = "Atheros AR2316",
2856 + [DEV_TYPE_AR2317] = "Atheros AR2317",
2857 + [DEV_TYPE_AR2318] = "Atheros AR2318",
2858 + [DEV_TYPE_UNKNOWN] = "Atheros (unknown)",
2859 +};
2860 +
2861 +const char *get_system_type(void)
2862 +{
2863 + if ((ar231x_devtype >= ARRAY_SIZE(devtype_strings)) ||
2864 + !devtype_strings[ar231x_devtype])
2865 + return devtype_strings[DEV_TYPE_UNKNOWN];
2866 + return devtype_strings[ar231x_devtype];
2867 +}
2868 +
2869 +int __init
2870 +ar231x_add_ethernet(int nr, u32 base, const char *mii_name, u32 mii_base,
2871 + int irq, void *pdata)
2872 +{
2873 + struct resource *res;
2874 +
2875 + ar231x_eth[nr].dev.platform_data = pdata;
2876 + res = &ar231x_eth[nr].resource[0];
2877 + res->start = base;
2878 + res->end = base + 0x2000 - 1;
2879 + res++;
2880 + res->name = mii_name;
2881 + res->start = mii_base;
2882 + res->end = mii_base + 8 - 1;
2883 + res++;
2884 + res->start = irq;
2885 + res->end = irq;
2886 + return platform_device_register(&ar231x_eth[nr]);
2887 +}
2888 +
2889 +void __init
2890 +ar231x_serial_setup(u32 mapbase, int irq, unsigned int uartclk)
2891 +{
2892 + struct uart_port s;
2893 +
2894 + memset(&s, 0, sizeof(s));
2895 +
2896 + s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP;
2897 + s.iotype = UPIO_MEM32;
2898 + s.irq = irq;
2899 + s.regshift = 2;
2900 + s.mapbase = mapbase;
2901 + s.uartclk = uartclk;
2902 +
2903 + early_serial_setup(&s);
2904 +}
2905 +
2906 +int __init
2907 +ar231x_add_wmac(int nr, u32 base, int irq)
2908 +{
2909 + struct resource *res;
2910 +
2911 + ar231x_wmac[nr].dev.platform_data = &ar231x_board;
2912 + res = &ar231x_wmac[nr].resource[0];
2913 + res->start = base;
2914 + res->end = base + 0x10000 - 1;
2915 + res++;
2916 + res->start = irq;
2917 + res->end = irq;
2918 + return platform_device_register(&ar231x_wmac[nr]);
2919 +}
2920 +
2921 +static int __init ar231x_register_devices(void)
2922 +{
2923 + ar5312_init_devices();
2924 + ar2315_init_devices();
2925 +
2926 + return 0;
2927 +}
2928 +
2929 +device_initcall(ar231x_register_devices);
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