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14ba5c3ef0fa904e2be063fe00c50b069ff08687
[openwrt/svn-archive/archive.git] / target / linux / atheros / patches-3.18 / 100-board.patch
1 --- a/arch/mips/Kconfig
2 +++ b/arch/mips/Kconfig
3 @@ -96,6 +96,19 @@ config AR7
4 Support for the Texas Instruments AR7 System-on-a-Chip
5 family: TNETD7100, 7200 and 7300.
6
7 +config ATH25
8 + bool "Atheros 231x/531x SoC support"
9 + select CEVT_R4K
10 + select CSRC_R4K
11 + select DMA_NONCOHERENT
12 + select IRQ_CPU
13 + select IRQ_DOMAIN
14 + select SYS_HAS_CPU_MIPS32_R1
15 + select SYS_SUPPORTS_BIG_ENDIAN
16 + select SYS_SUPPORTS_32BIT_KERNEL
17 + help
18 + Support for AR231x and AR531x based boards
19 +
20 config ATH79
21 bool "Atheros AR71XX/AR724X/AR913X based boards"
22 select ARCH_REQUIRE_GPIOLIB
23 @@ -834,6 +847,7 @@ config MIPS_PARAVIRT
24
25 endchoice
26
27 +source "arch/mips/ath25/Kconfig"
28 source "arch/mips/alchemy/Kconfig"
29 source "arch/mips/ath79/Kconfig"
30 source "arch/mips/bcm47xx/Kconfig"
31 --- a/arch/mips/Kbuild.platforms
32 +++ b/arch/mips/Kbuild.platforms
33 @@ -2,6 +2,7 @@
34
35 platforms += alchemy
36 platforms += ar7
37 +platforms += ath25
38 platforms += ath79
39 platforms += bcm47xx
40 platforms += bcm63xx
41 --- /dev/null
42 +++ b/arch/mips/ath25/Platform
43 @@ -0,0 +1,6 @@
44 +#
45 +# Atheros AR531X/AR231X WiSoC
46 +#
47 +platform-$(CONFIG_ATH25) += ath25/
48 +cflags-$(CONFIG_ATH25) += -I$(srctree)/arch/mips/include/asm/mach-ath25
49 +load-$(CONFIG_ATH25) += 0xffffffff80041000
50 --- /dev/null
51 +++ b/arch/mips/ath25/Kconfig
52 @@ -0,0 +1,9 @@
53 +config SOC_AR5312
54 + bool "Atheros 5312/2312+ support"
55 + depends on ATH25
56 + default y
57 +
58 +config SOC_AR2315
59 + bool "Atheros 2315+ support"
60 + depends on ATH25
61 + default y
62 --- /dev/null
63 +++ b/arch/mips/ath25/Makefile
64 @@ -0,0 +1,13 @@
65 +#
66 +# This file is subject to the terms and conditions of the GNU General Public
67 +# License. See the file "COPYING" in the main directory of this archive
68 +# for more details.
69 +#
70 +# Copyright (C) 2006 FON Technology, SL.
71 +# Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
72 +# Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
73 +#
74 +
75 +obj-y += board.o prom.o devices.o
76 +obj-$(CONFIG_SOC_AR5312) += ar5312.o
77 +obj-$(CONFIG_SOC_AR2315) += ar2315.o
78 --- /dev/null
79 +++ b/arch/mips/ath25/board.c
80 @@ -0,0 +1,235 @@
81 +/*
82 + * This file is subject to the terms and conditions of the GNU General Public
83 + * License. See the file "COPYING" in the main directory of this archive
84 + * for more details.
85 + *
86 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
87 + * Copyright (C) 2006 FON Technology, SL.
88 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
89 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
90 + */
91 +
92 +#include <linux/init.h>
93 +#include <linux/interrupt.h>
94 +#include <asm/irq_cpu.h>
95 +#include <asm/reboot.h>
96 +#include <asm/bootinfo.h>
97 +#include <asm/time.h>
98 +
99 +#include <ath25_platform.h>
100 +#include "devices.h"
101 +#include "ar5312.h"
102 +#include "ar2315.h"
103 +
104 +void (*ath25_irq_dispatch)(void);
105 +
106 +static inline bool check_radio_magic(const void __iomem *addr)
107 +{
108 + addr += 0x7a; /* offset for flash magic */
109 + return (__raw_readb(addr) == 0x5a) && (__raw_readb(addr + 1) == 0xa5);
110 +}
111 +
112 +static inline bool check_notempty(const void __iomem *addr)
113 +{
114 + return __raw_readl(addr) != 0xffffffff;
115 +}
116 +
117 +static inline bool check_board_data(const void __iomem *addr, bool broken)
118 +{
119 + /* config magic found */
120 + if (__raw_readl(addr) == ATH25_BD_MAGIC)
121 + return true;
122 +
123 + if (!broken)
124 + return false;
125 +
126 + /* broken board data detected, use radio data to find the
127 + * offset, user will fix this */
128 +
129 + if (check_radio_magic(addr + 0x1000))
130 + return true;
131 + if (check_radio_magic(addr + 0xf8))
132 + return true;
133 +
134 + return false;
135 +}
136 +
137 +static const void __iomem * __init find_board_config(const void __iomem *limit,
138 + const bool broken)
139 +{
140 + const void __iomem *addr;
141 + const void __iomem *begin = limit - 0x1000;
142 + const void __iomem *end = limit - 0x30000;
143 +
144 + for (addr = begin; addr >= end; addr -= 0x1000)
145 + if (check_board_data(addr, broken))
146 + return addr;
147 +
148 + return NULL;
149 +}
150 +
151 +static const void __iomem * __init find_radio_config(const void __iomem *limit,
152 + const void __iomem *bcfg)
153 +{
154 + const void __iomem *rcfg, *begin, *end;
155 +
156 + /*
157 + * Now find the start of Radio Configuration data, using heuristics:
158 + * Search forward from Board Configuration data by 0x1000 bytes
159 + * at a time until we find non-0xffffffff.
160 + */
161 + begin = bcfg + 0x1000;
162 + end = limit;
163 + for (rcfg = begin; rcfg < end; rcfg += 0x1000)
164 + if (check_notempty(rcfg) && check_radio_magic(rcfg))
165 + return rcfg;
166 +
167 + /* AR2316 relocates radio config to new location */
168 + begin = bcfg + 0xf8;
169 + end = limit - 0x1000 + 0xf8;
170 + for (rcfg = begin; rcfg < end; rcfg += 0x1000)
171 + if (check_notempty(rcfg) && check_radio_magic(rcfg))
172 + return rcfg;
173 +
174 + return NULL;
175 +}
176 +
177 +/*
178 + * NB: Search region size could be larger than the actual flash size,
179 + * but this shouldn't be a problem here, because the flash
180 + * will simply be mapped multiple times.
181 + */
182 +int __init ath25_find_config(phys_addr_t base, unsigned long size)
183 +{
184 + const void __iomem *flash_base, *flash_limit;
185 + struct ath25_boarddata *config;
186 + unsigned int rcfg_size;
187 + int broken_boarddata = 0;
188 + const void __iomem *bcfg, *rcfg;
189 + u8 *board_data;
190 + u8 *radio_data;
191 + u8 *mac_addr;
192 + u32 offset;
193 +
194 + flash_base = ioremap_nocache(base, size);
195 + flash_limit = flash_base + size;
196 +
197 + ath25_board.config = NULL;
198 + ath25_board.radio = NULL;
199 +
200 + /* Copy the board and radio data to RAM, because accessing the mapped
201 + * memory of the flash directly after booting is not safe */
202 +
203 + /* Try to find valid board and radio data */
204 + bcfg = find_board_config(flash_limit, false);
205 +
206 + /* If that fails, try to at least find valid radio data */
207 + if (!bcfg) {
208 + bcfg = find_board_config(flash_limit, true);
209 + broken_boarddata = 1;
210 + }
211 +
212 + if (!bcfg) {
213 + pr_warn("WARNING: No board configuration data found!\n");
214 + goto error;
215 + }
216 +
217 + board_data = kzalloc(BOARD_CONFIG_BUFSZ, GFP_KERNEL);
218 + ath25_board.config = (struct ath25_boarddata *)board_data;
219 + memcpy_fromio(board_data, bcfg, 0x100);
220 + if (broken_boarddata) {
221 + pr_warn("WARNING: broken board data detected\n");
222 + config = ath25_board.config;
223 + if (is_zero_ether_addr(config->enet0_mac)) {
224 + pr_info("Fixing up empty mac addresses\n");
225 + config->reset_config_gpio = 0xffff;
226 + config->sys_led_gpio = 0xffff;
227 + random_ether_addr(config->wlan0_mac);
228 + config->wlan0_mac[0] &= ~0x06;
229 + random_ether_addr(config->enet0_mac);
230 + random_ether_addr(config->enet1_mac);
231 + }
232 + }
233 +
234 + /* Radio config starts 0x100 bytes after board config, regardless
235 + * of what the physical layout on the flash chip looks like */
236 +
237 + rcfg = find_radio_config(flash_limit, bcfg);
238 + if (!rcfg) {
239 + pr_warn("WARNING: Could not find Radio Configuration data\n");
240 + goto error;
241 + }
242 +
243 + radio_data = board_data + 0x100 + ((rcfg - bcfg) & 0xfff);
244 + ath25_board.radio = radio_data;
245 + offset = radio_data - board_data;
246 + pr_info("Radio config found at offset 0x%x (0x%x)\n", rcfg - bcfg,
247 + offset);
248 + rcfg_size = BOARD_CONFIG_BUFSZ - offset;
249 + memcpy_fromio(radio_data, rcfg, rcfg_size);
250 +
251 + mac_addr = &radio_data[0x1d * 2];
252 + if (is_broadcast_ether_addr(mac_addr)) {
253 + pr_info("Radio MAC is blank; using board-data\n");
254 + ether_addr_copy(mac_addr, ath25_board.config->wlan0_mac);
255 + }
256 +
257 + iounmap(flash_base);
258 +
259 + return 0;
260 +
261 +error:
262 + iounmap(flash_base);
263 + return -ENODEV;
264 +}
265 +
266 +static void ath25_halt(void)
267 +{
268 + local_irq_disable();
269 + while (1)
270 + ;
271 +}
272 +
273 +void __init plat_mem_setup(void)
274 +{
275 + _machine_halt = ath25_halt;
276 + pm_power_off = ath25_halt;
277 +
278 + if (is_ar5312())
279 + ar5312_plat_mem_setup();
280 + else
281 + ar2315_plat_mem_setup();
282 +
283 + /* Disable data watchpoints */
284 + write_c0_watchlo0(0);
285 +}
286 +
287 +asmlinkage void plat_irq_dispatch(void)
288 +{
289 + ath25_irq_dispatch();
290 +}
291 +
292 +void __init plat_time_init(void)
293 +{
294 + if (is_ar5312())
295 + ar5312_plat_time_init();
296 + else
297 + ar2315_plat_time_init();
298 +}
299 +
300 +unsigned int __cpuinit get_c0_compare_int(void)
301 +{
302 + return CP0_LEGACY_COMPARE_IRQ;
303 +}
304 +
305 +void __init arch_init_irq(void)
306 +{
307 + clear_c0_status(ST0_IM);
308 + mips_cpu_irq_init();
309 +
310 + /* Initialize interrupt controllers */
311 + if (is_ar5312())
312 + ar5312_arch_init_irq();
313 + else
314 + ar2315_arch_init_irq();
315 +}
316 --- /dev/null
317 +++ b/arch/mips/ath25/prom.c
318 @@ -0,0 +1,26 @@
319 +/*
320 + * This file is subject to the terms and conditions of the GNU General Public
321 + * License. See the file "COPYING" in the main directory of this archive
322 + * for more details.
323 + *
324 + * Copyright MontaVista Software Inc
325 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
326 + * Copyright (C) 2006 FON Technology, SL.
327 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
328 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
329 + */
330 +
331 +/*
332 + * Prom setup file for ar231x
333 + */
334 +
335 +#include <linux/init.h>
336 +#include <asm/bootinfo.h>
337 +
338 +void __init prom_init(void)
339 +{
340 +}
341 +
342 +void __init prom_free_prom_memory(void)
343 +{
344 +}
345 --- /dev/null
346 +++ b/arch/mips/include/asm/mach-ath25/ath25_platform.h
347 @@ -0,0 +1,73 @@
348 +#ifndef __ASM_MACH_ATH25_PLATFORM_H
349 +#define __ASM_MACH_ATH25_PLATFORM_H
350 +
351 +#include <linux/etherdevice.h>
352 +
353 +/*
354 + * This is board-specific data that is stored in a "fixed" location in flash.
355 + * It is shared across operating systems, so it should not be changed lightly.
356 + * The main reason we need it is in order to extract the ethernet MAC
357 + * address(es).
358 + */
359 +struct ath25_boarddata {
360 + u32 magic; /* board data is valid */
361 +#define ATH25_BD_MAGIC 0x35333131 /* "5311", for all 531x/231x platforms */
362 + u16 cksum; /* checksum (starting with BD_REV 2) */
363 + u16 rev; /* revision of this struct */
364 +#define BD_REV 4
365 + char board_name[64]; /* Name of board */
366 + u16 major; /* Board major number */
367 + u16 minor; /* Board minor number */
368 + u32 flags; /* Board configuration */
369 +#define BD_ENET0 0x00000001 /* ENET0 is stuffed */
370 +#define BD_ENET1 0x00000002 /* ENET1 is stuffed */
371 +#define BD_UART1 0x00000004 /* UART1 is stuffed */
372 +#define BD_UART0 0x00000008 /* UART0 is stuffed (dma) */
373 +#define BD_RSTFACTORY 0x00000010 /* Reset factory defaults stuffed */
374 +#define BD_SYSLED 0x00000020 /* System LED stuffed */
375 +#define BD_EXTUARTCLK 0x00000040 /* External UART clock */
376 +#define BD_CPUFREQ 0x00000080 /* cpu freq is valid in nvram */
377 +#define BD_SYSFREQ 0x00000100 /* sys freq is set in nvram */
378 +#define BD_WLAN0 0x00000200 /* Enable WLAN0 */
379 +#define BD_MEMCAP 0x00000400 /* CAP SDRAM @ mem_cap for testing */
380 +#define BD_DISWATCHDOG 0x00000800 /* disable system watchdog */
381 +#define BD_WLAN1 0x00001000 /* Enable WLAN1 (ar5212) */
382 +#define BD_ISCASPER 0x00002000 /* FLAG for AR2312 */
383 +#define BD_WLAN0_2G_EN 0x00004000 /* FLAG for radio0_2G */
384 +#define BD_WLAN0_5G_EN 0x00008000 /* FLAG for radio0_2G */
385 +#define BD_WLAN1_2G_EN 0x00020000 /* FLAG for radio0_2G */
386 +#define BD_WLAN1_5G_EN 0x00040000 /* FLAG for radio0_2G */
387 + u16 reset_config_gpio; /* Reset factory GPIO pin */
388 + u16 sys_led_gpio; /* System LED GPIO pin */
389 +
390 + u32 cpu_freq; /* CPU core frequency in Hz */
391 + u32 sys_freq; /* System frequency in Hz */
392 + u32 cnt_freq; /* Calculated C0_COUNT frequency */
393 +
394 + u8 wlan0_mac[ETH_ALEN];
395 + u8 enet0_mac[ETH_ALEN];
396 + u8 enet1_mac[ETH_ALEN];
397 +
398 + u16 pci_id; /* Pseudo PCIID for common code */
399 + u16 mem_cap; /* cap bank1 in MB */
400 +
401 + /* version 3 */
402 + u8 wlan1_mac[ETH_ALEN]; /* (ar5212) */
403 +};
404 +
405 +#define BOARD_CONFIG_BUFSZ 0x1000
406 +
407 +/*
408 + * Platform device information for the Wireless MAC
409 + */
410 +struct ar231x_board_config {
411 + u16 devid;
412 +
413 + /* board config data */
414 + struct ath25_boarddata *config;
415 +
416 + /* radio calibration data */
417 + const char *radio;
418 +};
419 +
420 +#endif /* __ASM_MACH_ATH25_PLATFORM_H */
421 --- /dev/null
422 +++ b/arch/mips/include/asm/mach-ath25/cpu-feature-overrides.h
423 @@ -0,0 +1,64 @@
424 +/*
425 + * Atheros AR231x/AR531x SoC specific CPU feature overrides
426 + *
427 + * Copyright (C) 2008 Gabor Juhos <juhosg@openwrt.org>
428 + *
429 + * This file was derived from: include/asm-mips/cpu-features.h
430 + * Copyright (C) 2003, 2004 Ralf Baechle
431 + * Copyright (C) 2004 Maciej W. Rozycki
432 + *
433 + * This program is free software; you can redistribute it and/or modify it
434 + * under the terms of the GNU General Public License version 2 as published
435 + * by the Free Software Foundation.
436 + *
437 + */
438 +#ifndef __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H
439 +#define __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H
440 +
441 +/*
442 + * The Atheros AR531x/AR231x SoCs have MIPS 4Kc/4KEc core.
443 + */
444 +#define cpu_has_tlb 1
445 +#define cpu_has_4kex 1
446 +#define cpu_has_3k_cache 0
447 +#define cpu_has_4k_cache 1
448 +#define cpu_has_tx39_cache 0
449 +#define cpu_has_sb1_cache 0
450 +#define cpu_has_fpu 0
451 +#define cpu_has_32fpr 0
452 +#define cpu_has_counter 1
453 +#define cpu_has_ejtag 1
454 +
455 +#if !defined(CONFIG_SOC_AR5312)
456 +# define cpu_has_llsc 1
457 +#else
458 +/*
459 + * The MIPS 4Kc V0.9 core in the AR5312/AR2312 have problems with the
460 + * ll/sc instructions.
461 + */
462 +# define cpu_has_llsc 0
463 +#endif
464 +
465 +#define cpu_has_mips16 0
466 +#define cpu_has_mdmx 0
467 +#define cpu_has_mips3d 0
468 +#define cpu_has_smartmips 0
469 +
470 +#define cpu_has_mips32r1 1
471 +
472 +#if !defined(CONFIG_SOC_AR5312)
473 +# define cpu_has_mips32r2 1
474 +#endif
475 +
476 +#define cpu_has_mips64r1 0
477 +#define cpu_has_mips64r2 0
478 +
479 +#define cpu_has_dsp 0
480 +#define cpu_has_mipsmt 0
481 +
482 +#define cpu_has_64bits 0
483 +#define cpu_has_64bit_zero_reg 0
484 +#define cpu_has_64bit_gp_regs 0
485 +#define cpu_has_64bit_addresses 0
486 +
487 +#endif /* __ASM_MACH_ATH25_CPU_FEATURE_OVERRIDES_H */
488 --- /dev/null
489 +++ b/arch/mips/include/asm/mach-ath25/dma-coherence.h
490 @@ -0,0 +1,82 @@
491 +/*
492 + * This file is subject to the terms and conditions of the GNU General Public
493 + * License. See the file "COPYING" in the main directory of this archive
494 + * for more details.
495 + *
496 + * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
497 + * Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
498 + *
499 + */
500 +#ifndef __ASM_MACH_ATH25_DMA_COHERENCE_H
501 +#define __ASM_MACH_ATH25_DMA_COHERENCE_H
502 +
503 +#include <linux/device.h>
504 +
505 +/*
506 + * We need some arbitrary non-zero value to be programmed to the BAR1 register
507 + * of PCI host controller to enable DMA. The same value should be used as the
508 + * offset to calculate the physical address of DMA buffer for PCI devices.
509 + */
510 +#define AR2315_PCI_HOST_SDRAM_BASEADDR 0x20000000
511 +
512 +static inline dma_addr_t ath25_dev_offset(struct device *dev)
513 +{
514 +#ifdef CONFIG_PCI
515 + extern struct bus_type pci_bus_type;
516 +
517 + if (dev && dev->bus == &pci_bus_type)
518 + return AR2315_PCI_HOST_SDRAM_BASEADDR;
519 +#endif
520 + return 0;
521 +}
522 +
523 +static inline dma_addr_t
524 +plat_map_dma_mem(struct device *dev, void *addr, size_t size)
525 +{
526 + return virt_to_phys(addr) + ath25_dev_offset(dev);
527 +}
528 +
529 +static inline dma_addr_t
530 +plat_map_dma_mem_page(struct device *dev, struct page *page)
531 +{
532 + return page_to_phys(page) + ath25_dev_offset(dev);
533 +}
534 +
535 +static inline unsigned long
536 +plat_dma_addr_to_phys(struct device *dev, dma_addr_t dma_addr)
537 +{
538 + return dma_addr - ath25_dev_offset(dev);
539 +}
540 +
541 +static inline void
542 +plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr, size_t size,
543 + enum dma_data_direction direction)
544 +{
545 +}
546 +
547 +static inline int plat_dma_supported(struct device *dev, u64 mask)
548 +{
549 + return 1;
550 +}
551 +
552 +static inline void plat_extra_sync_for_device(struct device *dev)
553 +{
554 +}
555 +
556 +static inline int plat_dma_mapping_error(struct device *dev,
557 + dma_addr_t dma_addr)
558 +{
559 + return 0;
560 +}
561 +
562 +static inline int plat_device_is_coherent(struct device *dev)
563 +{
564 +#ifdef CONFIG_DMA_COHERENT
565 + return 1;
566 +#endif
567 +#ifdef CONFIG_DMA_NONCOHERENT
568 + return 0;
569 +#endif
570 +}
571 +
572 +#endif /* __ASM_MACH_ATH25_DMA_COHERENCE_H */
573 --- /dev/null
574 +++ b/arch/mips/include/asm/mach-ath25/gpio.h
575 @@ -0,0 +1,16 @@
576 +#ifndef __ASM_MACH_ATH25_GPIO_H
577 +#define __ASM_MACH_ATH25_GPIO_H
578 +
579 +#include <asm-generic/gpio.h>
580 +
581 +#define gpio_get_value __gpio_get_value
582 +#define gpio_set_value __gpio_set_value
583 +#define gpio_cansleep __gpio_cansleep
584 +#define gpio_to_irq __gpio_to_irq
585 +
586 +static inline int irq_to_gpio(unsigned irq)
587 +{
588 + return -EINVAL;
589 +}
590 +
591 +#endif /* __ASM_MACH_ATH25_GPIO_H */
592 --- /dev/null
593 +++ b/arch/mips/include/asm/mach-ath25/war.h
594 @@ -0,0 +1,25 @@
595 +/*
596 + * This file is subject to the terms and conditions of the GNU General Public
597 + * License. See the file "COPYING" in the main directory of this archive
598 + * for more details.
599 + *
600 + * Copyright (C) 2008 Felix Fietkau <nbd@openwrt.org>
601 + */
602 +#ifndef __ASM_MACH_ATH25_WAR_H
603 +#define __ASM_MACH_ATH25_WAR_H
604 +
605 +#define R4600_V1_INDEX_ICACHEOP_WAR 0
606 +#define R4600_V1_HIT_CACHEOP_WAR 0
607 +#define R4600_V2_HIT_CACHEOP_WAR 0
608 +#define R5432_CP0_INTERRUPT_WAR 0
609 +#define BCM1250_M3_WAR 0
610 +#define SIBYTE_1956_WAR 0
611 +#define MIPS4K_ICACHE_REFILL_WAR 0
612 +#define MIPS_CACHE_SYNC_WAR 0
613 +#define TX49XX_ICACHE_INDEX_INV_WAR 0
614 +#define RM9000_CDEX_SMP_WAR 0
615 +#define ICACHE_REFILLS_WORKAROUND_WAR 0
616 +#define R10000_LLSC_WAR 0
617 +#define MIPS34K_MISSED_ITLB_WAR 0
618 +
619 +#endif /* __ASM_MACH_ATH25_WAR_H */
620 --- /dev/null
621 +++ b/arch/mips/ath25/ar2315_regs.h
622 @@ -0,0 +1,471 @@
623 +/*
624 + * Register definitions for AR2315+
625 + *
626 + * This file is subject to the terms and conditions of the GNU General Public
627 + * License. See the file "COPYING" in the main directory of this archive
628 + * for more details.
629 + *
630 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
631 + * Copyright (C) 2006 FON Technology, SL.
632 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
633 + * Copyright (C) 2006-2008 Felix Fietkau <nbd@openwrt.org>
634 + */
635 +
636 +#ifndef __ASM_MACH_ATH25_AR2315_REGS_H
637 +#define __ASM_MACH_ATH25_AR2315_REGS_H
638 +
639 +/*
640 + * IRQs
641 + */
642 +#define AR2315_IRQ_MISC (MIPS_CPU_IRQ_BASE + 2) /* C0_CAUSE: 0x0400 */
643 +#define AR2315_IRQ_WLAN0 (MIPS_CPU_IRQ_BASE + 3) /* C0_CAUSE: 0x0800 */
644 +#define AR2315_IRQ_ENET0 (MIPS_CPU_IRQ_BASE + 4) /* C0_CAUSE: 0x1000 */
645 +#define AR2315_IRQ_LCBUS_PCI (MIPS_CPU_IRQ_BASE + 5) /* C0_CAUSE: 0x2000 */
646 +#define AR2315_IRQ_WLAN0_POLL (MIPS_CPU_IRQ_BASE + 6) /* C0_CAUSE: 0x4000 */
647 +
648 +/*
649 + * Miscellaneous interrupts, which share IP2.
650 + */
651 +#define AR2315_MISC_IRQ_UART0 0
652 +#define AR2315_MISC_IRQ_I2C_RSVD 1
653 +#define AR2315_MISC_IRQ_SPI 2
654 +#define AR2315_MISC_IRQ_AHB 3
655 +#define AR2315_MISC_IRQ_APB 4
656 +#define AR2315_MISC_IRQ_TIMER 5
657 +#define AR2315_MISC_IRQ_GPIO 6
658 +#define AR2315_MISC_IRQ_WATCHDOG 7
659 +#define AR2315_MISC_IRQ_IR_RSVD 8
660 +#define AR2315_MISC_IRQ_COUNT 9
661 +
662 +/*
663 + * Address map
664 + */
665 +#define AR2315_SPI_READ_BASE 0x08000000 /* SPI flash */
666 +#define AR2315_SPI_READ_SIZE 0x01000000
667 +#define AR2315_WLAN0_BASE 0x10000000 /* Wireless MMR */
668 +#define AR2315_PCI_BASE 0x10100000 /* PCI MMR */
669 +#define AR2315_PCI_SIZE 0x00001000
670 +#define AR2315_SDRAMCTL_BASE 0x10300000 /* SDRAM MMR */
671 +#define AR2315_SDRAMCTL_SIZE 0x00000020
672 +#define AR2315_LOCAL_BASE 0x10400000 /* Local bus MMR */
673 +#define AR2315_ENET0_BASE 0x10500000 /* Ethernet MMR */
674 +#define AR2315_RST_BASE 0x11000000 /* Reset control MMR */
675 +#define AR2315_RST_SIZE 0x00000100
676 +#define AR2315_UART0_BASE 0x11100000 /* UART MMR */
677 +#define AR2315_SPI_MMR_BASE 0x11300000 /* SPI flash MMR */
678 +#define AR2315_SPI_MMR_SIZE 0x00000010
679 +#define AR2315_PCI_EXT_BASE 0x80000000 /* PCI external */
680 +#define AR2315_PCI_EXT_SIZE 0x40000000
681 +
682 +/*
683 + * Cold reset register
684 + */
685 +#define AR2315_COLD_RESET 0x0000
686 +
687 +#define AR2315_RESET_COLD_AHB 0x00000001
688 +#define AR2315_RESET_COLD_APB 0x00000002
689 +#define AR2315_RESET_COLD_CPU 0x00000004
690 +#define AR2315_RESET_COLD_CPUWARM 0x00000008
691 +#define AR2315_RESET_SYSTEM \
692 + (RESET_COLD_CPU |\
693 + RESET_COLD_APB |\
694 + RESET_COLD_AHB) /* full system */
695 +#define AR2317_RESET_SYSTEM 0x00000010
696 +
697 +/*
698 + * Reset register
699 + */
700 +#define AR2315_RESET 0x0004
701 +
702 +/* warm reset WLAN0 MAC */
703 +#define AR2315_RESET_WARM_WLAN0_MAC 0x00000001
704 +/* warm reset WLAN0 BaseBand */
705 +#define AR2315_RESET_WARM_WLAN0_BB 0x00000002
706 +/* warm reset MPEG-TS */
707 +#define AR2315_RESET_MPEGTS_RSVD 0x00000004
708 +/* warm reset PCI ahb/dma */
709 +#define AR2315_RESET_PCIDMA 0x00000008
710 +/* warm reset memory controller */
711 +#define AR2315_RESET_MEMCTL 0x00000010
712 +/* warm reset local bus */
713 +#define AR2315_RESET_LOCAL 0x00000020
714 +/* warm reset I2C bus */
715 +#define AR2315_RESET_I2C_RSVD 0x00000040
716 +/* warm reset SPI interface */
717 +#define AR2315_RESET_SPI 0x00000080
718 +/* warm reset UART0 */
719 +#define AR2315_RESET_UART0 0x00000100
720 +/* warm reset IR interface */
721 +#define AR2315_RESET_IR_RSVD 0x00000200
722 +/* cold reset ENET0 phy */
723 +#define AR2315_RESET_EPHY0 0x00000400
724 +/* cold reset ENET0 mac */
725 +#define AR2315_RESET_ENET0 0x00000800
726 +
727 +/*
728 + * AHB master arbitration control
729 + */
730 +#define AR2315_AHB_ARB_CTL 0x0008
731 +
732 +/* CPU, default */
733 +#define AR2315_ARB_CPU 0x00000001
734 +/* WLAN */
735 +#define AR2315_ARB_WLAN 0x00000002
736 +/* MPEG-TS */
737 +#define AR2315_ARB_MPEGTS_RSVD 0x00000004
738 +/* LOCAL */
739 +#define AR2315_ARB_LOCAL 0x00000008
740 +/* PCI */
741 +#define AR2315_ARB_PCI 0x00000010
742 +/* Ethernet */
743 +#define AR2315_ARB_ETHERNET 0x00000020
744 +/* retry policy, debug only */
745 +#define AR2315_ARB_RETRY 0x00000100
746 +
747 +/*
748 + * Config Register
749 + */
750 +#define AR2315_ENDIAN_CTL 0x000c
751 +
752 +/* EC - AHB bridge endianess */
753 +#define AR2315_CONFIG_AHB 0x00000001
754 +/* WLAN byteswap */
755 +#define AR2315_CONFIG_WLAN 0x00000002
756 +/* MPEG-TS byteswap */
757 +#define AR2315_CONFIG_MPEGTS_RSVD 0x00000004
758 +/* PCI byteswap */
759 +#define AR2315_CONFIG_PCI 0x00000008
760 +/* Memory controller endianess */
761 +#define AR2315_CONFIG_MEMCTL 0x00000010
762 +/* Local bus byteswap */
763 +#define AR2315_CONFIG_LOCAL 0x00000020
764 +/* Ethernet byteswap */
765 +#define AR2315_CONFIG_ETHERNET 0x00000040
766 +
767 +/* CPU write buffer merge */
768 +#define AR2315_CONFIG_MERGE 0x00000200
769 +/* CPU big endian */
770 +#define AR2315_CONFIG_CPU 0x00000400
771 +#define AR2315_CONFIG_PCIAHB 0x00000800
772 +#define AR2315_CONFIG_PCIAHB_BRIDGE 0x00001000
773 +/* SPI byteswap */
774 +#define AR2315_CONFIG_SPI 0x00008000
775 +#define AR2315_CONFIG_CPU_DRAM 0x00010000
776 +#define AR2315_CONFIG_CPU_PCI 0x00020000
777 +#define AR2315_CONFIG_CPU_MMR 0x00040000
778 +#define AR2315_CONFIG_BIG 0x00000400
779 +
780 +/*
781 + * NMI control
782 + */
783 +#define AR2315_NMI_CTL 0x0010
784 +
785 +#define AR2315_NMI_EN 1
786 +
787 +/*
788 + * Revision Register - Initial value is 0x3010 (WMAC 3.0, AR231X 1.0).
789 + */
790 +#define AR2315_SREV 0x0014
791 +
792 +#define AR2315_REV_MAJ 0x00f0
793 +#define AR2315_REV_MAJ_S 4
794 +#define AR2315_REV_MIN 0x000f
795 +#define AR2315_REV_MIN_S 0
796 +#define AR2315_REV_CHIP (AR2315_REV_MAJ|AR2315_REV_MIN)
797 +
798 +/*
799 + * Interface Enable
800 + */
801 +#define AR2315_IF_CTL 0x0018
802 +
803 +#define AR2315_IF_MASK 0x00000007
804 +#define AR2315_IF_DISABLED 0
805 +#define AR2315_IF_PCI 1
806 +#define AR2315_IF_TS_LOCAL 2
807 +/* only for emulation with separate pins */
808 +#define AR2315_IF_ALL 3
809 +#define AR2315_IF_LOCAL_HOST 0x00000008
810 +#define AR2315_IF_PCI_HOST 0x00000010
811 +#define AR2315_IF_PCI_INTR 0x00000020
812 +#define AR2315_IF_PCI_CLK_MASK 0x00030000
813 +#define AR2315_IF_PCI_CLK_INPUT 0
814 +#define AR2315_IF_PCI_CLK_OUTPUT_LOW 1
815 +#define AR2315_IF_PCI_CLK_OUTPUT_CLK 2
816 +#define AR2315_IF_PCI_CLK_OUTPUT_HIGH 3
817 +#define AR2315_IF_PCI_CLK_SHIFT 16
818 +
819 +/*
820 + * APB Interrupt control
821 + */
822 +
823 +#define AR2315_ISR 0x0020
824 +#define AR2315_IMR 0x0024
825 +#define AR2315_GISR 0x0028
826 +
827 +#define AR2315_ISR_UART0 0x0001 /* high speed UART */
828 +#define AR2315_ISR_I2C_RSVD 0x0002 /* I2C bus */
829 +#define AR2315_ISR_SPI 0x0004 /* SPI bus */
830 +#define AR2315_ISR_AHB 0x0008 /* AHB error */
831 +#define AR2315_ISR_APB 0x0010 /* APB error */
832 +#define AR2315_ISR_TIMER 0x0020 /* timer */
833 +#define AR2315_ISR_GPIO 0x0040 /* GPIO */
834 +#define AR2315_ISR_WD 0x0080 /* watchdog */
835 +#define AR2315_ISR_IR_RSVD 0x0100 /* IR */
836 +
837 +#define AR2315_GISR_MISC 0x0001
838 +#define AR2315_GISR_WLAN0 0x0002
839 +#define AR2315_GISR_MPEGTS_RSVD 0x0004
840 +#define AR2315_GISR_LOCALPCI 0x0008
841 +#define AR2315_GISR_WMACPOLL 0x0010
842 +#define AR2315_GISR_TIMER 0x0020
843 +#define AR2315_GISR_ETHERNET 0x0040
844 +
845 +/*
846 + * Timers
847 + */
848 +#define AR2315_TIMER 0x0030
849 +#define AR2315_RELOAD 0x0034
850 +
851 +#define AR2315_WDT_TIMER 0x0038
852 +#define AR2315_WDT_CTRL 0x003c
853 +
854 +#define AR2315_WDT_CTRL_IGNORE 0x00000000 /* ignore expiration */
855 +#define AR2315_WDT_CTRL_NMI 0x00000001 /* NMI on watchdog */
856 +#define AR2315_WDT_CTRL_RESET 0x00000002 /* reset on watchdog */
857 +
858 +/*
859 + * CPU Performance Counters
860 + */
861 +#define AR2315_PERFCNT0 0x0048
862 +#define AR2315_PERFCNT1 0x004c
863 +
864 +#define AR2315_PERF0_DATAHIT 0x0001 /* Count Data Cache Hits */
865 +#define AR2315_PERF0_DATAMISS 0x0002 /* Count Data Cache Misses */
866 +#define AR2315_PERF0_INSTHIT 0x0004 /* Count Instruction Cache Hits */
867 +#define AR2315_PERF0_INSTMISS 0x0008 /* Count Instruction Cache Misses */
868 +#define AR2315_PERF0_ACTIVE 0x0010 /* Count Active Processor Cycles */
869 +#define AR2315_PERF0_WBHIT 0x0020 /* Count CPU Write Buffer Hits */
870 +#define AR2315_PERF0_WBMISS 0x0040 /* Count CPU Write Buffer Misses */
871 +
872 +#define AR2315_PERF1_EB_ARDY 0x0001 /* Count EB_ARdy signal */
873 +#define AR2315_PERF1_EB_AVALID 0x0002 /* Count EB_AValid signal */
874 +#define AR2315_PERF1_EB_WDRDY 0x0004 /* Count EB_WDRdy signal */
875 +#define AR2315_PERF1_EB_RDVAL 0x0008 /* Count EB_RdVal signal */
876 +#define AR2315_PERF1_VRADDR 0x0010 /* Count valid read address cycles */
877 +#define AR2315_PERF1_VWADDR 0x0020 /* Count valid write address cycles */
878 +#define AR2315_PERF1_VWDATA 0x0040 /* Count valid write data cycles */
879 +
880 +/*
881 + * AHB Error Reporting.
882 + */
883 +#define AR2315_AHB_ERR0 0x0050 /* error */
884 +#define AR2315_AHB_ERR1 0x0054 /* haddr */
885 +#define AR2315_AHB_ERR2 0x0058 /* hwdata */
886 +#define AR2315_AHB_ERR3 0x005c /* hrdata */
887 +#define AR2315_AHB_ERR4 0x0060 /* status */
888 +
889 +#define AR2315_AHB_ERROR_DET 1 /* AHB Error has been detected, */
890 + /* write 1 to clear all bits in ERR0 */
891 +#define AR2315_AHB_ERROR_OVR 2 /* AHB Error overflow has been detected */
892 +#define AR2315_AHB_ERROR_WDT 4 /* AHB Error due to wdt instead of hresp */
893 +
894 +#define AR2315_PROCERR_HMAST 0x0000000f
895 +#define AR2315_PROCERR_HMAST_DFLT 0
896 +#define AR2315_PROCERR_HMAST_WMAC 1
897 +#define AR2315_PROCERR_HMAST_ENET 2
898 +#define AR2315_PROCERR_HMAST_PCIENDPT 3
899 +#define AR2315_PROCERR_HMAST_LOCAL 4
900 +#define AR2315_PROCERR_HMAST_CPU 5
901 +#define AR2315_PROCERR_HMAST_PCITGT 6
902 +
903 +#define AR2315_PROCERR_HMAST_S 0
904 +#define AR2315_PROCERR_HWRITE 0x00000010
905 +#define AR2315_PROCERR_HSIZE 0x00000060
906 +#define AR2315_PROCERR_HSIZE_S 5
907 +#define AR2315_PROCERR_HTRANS 0x00000180
908 +#define AR2315_PROCERR_HTRANS_S 7
909 +#define AR2315_PROCERR_HBURST 0x00000e00
910 +#define AR2315_PROCERR_HBURST_S 9
911 +
912 +/*
913 + * Clock Control
914 + */
915 +#define AR2315_PLLC_CTL 0x0064
916 +#define AR2315_PLLV_CTL 0x0068
917 +#define AR2315_CPUCLK 0x006c
918 +#define AR2315_AMBACLK 0x0070
919 +#define AR2315_SYNCCLK 0x0074
920 +#define AR2315_DSL_SLEEP_CTL 0x0080
921 +#define AR2315_DSL_SLEEP_DUR 0x0084
922 +
923 +/* PLLc Control fields */
924 +#define AR2315_PLLC_REF_DIV_M 0x00000003
925 +#define AR2315_PLLC_REF_DIV_S 0
926 +#define AR2315_PLLC_FDBACK_DIV_M 0x0000007c
927 +#define AR2315_PLLC_FDBACK_DIV_S 2
928 +#define AR2315_PLLC_ADD_FDBACK_DIV_M 0x00000080
929 +#define AR2315_PLLC_ADD_FDBACK_DIV_S 7
930 +#define AR2315_PLLC_CLKC_DIV_M 0x0001c000
931 +#define AR2315_PLLC_CLKC_DIV_S 14
932 +#define AR2315_PLLC_CLKM_DIV_M 0x00700000
933 +#define AR2315_PLLC_CLKM_DIV_S 20
934 +
935 +/* CPU CLK Control fields */
936 +#define AR2315_CPUCLK_CLK_SEL_M 0x00000003
937 +#define AR2315_CPUCLK_CLK_SEL_S 0
938 +#define AR2315_CPUCLK_CLK_DIV_M 0x0000000c
939 +#define AR2315_CPUCLK_CLK_DIV_S 2
940 +
941 +/* AMBA CLK Control fields */
942 +#define AR2315_AMBACLK_CLK_SEL_M 0x00000003
943 +#define AR2315_AMBACLK_CLK_SEL_S 0
944 +#define AR2315_AMBACLK_CLK_DIV_M 0x0000000c
945 +#define AR2315_AMBACLK_CLK_DIV_S 2
946 +
947 +/*
948 + * PCI Clock Control
949 + */
950 +#define AR2315_PCICLK 0x00a4
951 +
952 +#define AR2315_PCICLK_INPUT_M 0x3
953 +#define AR2315_PCICLK_INPUT_S 0
954 +
955 +#define AR2315_PCICLK_PLLC_CLKM 0
956 +#define AR2315_PCICLK_PLLC_CLKM1 1
957 +#define AR2315_PCICLK_PLLC_CLKC 2
958 +#define AR2315_PCICLK_REF_CLK 3
959 +
960 +#define AR2315_PCICLK_DIV_M 0xc
961 +#define AR2315_PCICLK_DIV_S 2
962 +
963 +#define AR2315_PCICLK_IN_FREQ 0
964 +#define AR2315_PCICLK_IN_FREQ_DIV_6 1
965 +#define AR2315_PCICLK_IN_FREQ_DIV_8 2
966 +#define AR2315_PCICLK_IN_FREQ_DIV_10 3
967 +
968 +/*
969 + * Observation Control Register
970 + */
971 +#define AR2315_OCR 0x00b0
972 +
973 +#define AR2315_OCR_GPIO0_IRIN 0x00000040
974 +#define AR2315_OCR_GPIO1_IROUT 0x00000080
975 +#define AR2315_OCR_GPIO3_RXCLR 0x00000200
976 +
977 +/*
978 + * General Clock Control
979 + */
980 +#define AR2315_MISCCLK 0x00b4
981 +
982 +#define AR2315_MISCCLK_PLLBYPASS_EN 0x00000001
983 +#define AR2315_MISCCLK_PROCREFCLK 0x00000002
984 +
985 +/*
986 + * SDRAM Controller
987 + * - No read or write buffers are included.
988 + */
989 +#define AR2315_MEM_CFG 0x0000
990 +#define AR2315_MEM_CTRL 0x000c
991 +#define AR2315_MEM_REF 0x0010
992 +
993 +#define AR2315_MEM_CFG_DATA_WIDTH_M 0x00006000
994 +#define AR2315_MEM_CFG_DATA_WIDTH_S 13
995 +#define AR2315_MEM_CFG_COL_WIDTH_M 0x00001e00
996 +#define AR2315_MEM_CFG_COL_WIDTH_S 9
997 +#define AR2315_MEM_CFG_ROW_WIDTH_M 0x000001e0
998 +#define AR2315_MEM_CFG_ROW_WIDTH_S 5
999 +#define AR2315_MEM_CFG_BANKADDR_BITS_M 0x00000018
1000 +#define AR2315_MEM_CFG_BANKADDR_BITS_S 3
1001 +
1002 +/*
1003 + * Local Bus Interface Registers
1004 + */
1005 +#define AR2315_LB_CONFIG 0x0000
1006 +
1007 +#define AR2315_LBCONF_OE 0x00000001 /* =1 OE is low-true */
1008 +#define AR2315_LBCONF_CS0 0x00000002 /* =1 first CS is low-true */
1009 +#define AR2315_LBCONF_CS1 0x00000004 /* =1 2nd CS is low-true */
1010 +#define AR2315_LBCONF_RDY 0x00000008 /* =1 RDY is low-true */
1011 +#define AR2315_LBCONF_WE 0x00000010 /* =1 Write En is low-true */
1012 +#define AR2315_LBCONF_WAIT 0x00000020 /* =1 WAIT is low-true */
1013 +#define AR2315_LBCONF_ADS 0x00000040 /* =1 Adr Strobe is low-true */
1014 +#define AR2315_LBCONF_MOT 0x00000080 /* =0 Intel, =1 Motorola */
1015 +#define AR2315_LBCONF_8CS 0x00000100 /* =1 8 bits CS, 0= 16bits */
1016 +#define AR2315_LBCONF_8DS 0x00000200 /* =1 8 bits Data S, 0=16bits */
1017 +#define AR2315_LBCONF_ADS_EN 0x00000400 /* =1 Enable ADS */
1018 +#define AR2315_LBCONF_ADR_OE 0x00000800 /* =1 Adr cap on OE, WE or DS */
1019 +#define AR2315_LBCONF_ADDT_MUX 0x00001000 /* =1 Adr and Data share bus */
1020 +#define AR2315_LBCONF_DATA_OE 0x00002000 /* =1 Data cap on OE, WE, DS */
1021 +#define AR2315_LBCONF_16DATA 0x00004000 /* =1 Data is 16 bits wide */
1022 +#define AR2315_LBCONF_SWAPDT 0x00008000 /* =1 Byte swap data */
1023 +#define AR2315_LBCONF_SYNC 0x00010000 /* =1 Bus synchronous to clk */
1024 +#define AR2315_LBCONF_INT 0x00020000 /* =1 Intr is low true */
1025 +#define AR2315_LBCONF_INT_CTR0 0x00000000 /* GND high-Z, Vdd is high-Z */
1026 +#define AR2315_LBCONF_INT_CTR1 0x00040000 /* GND drive, Vdd is high-Z */
1027 +#define AR2315_LBCONF_INT_CTR2 0x00080000 /* GND high-Z, Vdd drive */
1028 +#define AR2315_LBCONF_INT_CTR3 0x000C0000 /* GND drive, Vdd drive */
1029 +#define AR2315_LBCONF_RDY_WAIT 0x00100000 /* =1 RDY is negative of WAIT */
1030 +#define AR2315_LBCONF_INT_PULSE 0x00200000 /* =1 Interrupt is a pulse */
1031 +#define AR2315_LBCONF_ENABLE 0x00400000 /* =1 Falcon respond to LB */
1032 +
1033 +#define AR2315_LB_CLKSEL 0x0004
1034 +
1035 +#define AR2315_LBCLK_EXT 0x0001 /* use external clk for lb */
1036 +
1037 +#define AR2315_LB_1MS 0x0008
1038 +
1039 +#define AR2315_LB1MS_MASK 0x3FFFF /* # of AHB clk cycles in 1ms */
1040 +
1041 +#define AR2315_LB_MISCCFG 0x000c
1042 +#define AR2315_LBM_TXD_EN 0x00000001 /* Enable TXD for fragments */
1043 +#define AR2315_LBM_RX_INTEN 0x00000002 /* Enable LB ints on RX ready */
1044 +#define AR2315_LBM_MBOXWR_INTEN 0x00000004 /* Enable LB ints on mbox wr */
1045 +#define AR2315_LBM_MBOXRD_INTEN 0x00000008 /* Enable LB ints on mbox rd */
1046 +#define AR2315_LMB_DESCSWAP_EN 0x00000010 /* Byte swap desc enable */
1047 +#define AR2315_LBM_TIMEOUT_M 0x00ffff80
1048 +#define AR2315_LBM_TIMEOUT_S 7
1049 +#define AR2315_LBM_PORTMUX 0x07000000
1050 +
1051 +#define AR2315_LB_RXTSOFF 0x0010
1052 +
1053 +#define AR2315_LB_TX_CHAIN_EN 0x0100
1054 +
1055 +#define AR2315_LB_TXEN_0 0x01
1056 +#define AR2315_LB_TXEN_1 0x02
1057 +#define AR2315_LB_TXEN_2 0x04
1058 +#define AR2315_LB_TXEN_3 0x08
1059 +
1060 +#define AR2315_LB_TX_CHAIN_DIS 0x0104
1061 +#define AR2315_LB_TX_DESC_PTR 0x0200
1062 +
1063 +#define AR2315_LB_RX_CHAIN_EN 0x0400
1064 +
1065 +#define AR2315_LB_RXEN 0x01
1066 +
1067 +#define AR2315_LB_RX_CHAIN_DIS 0x0404
1068 +#define AR2315_LB_RX_DESC_PTR 0x0408
1069 +
1070 +#define AR2315_LB_INT_STATUS 0x0500
1071 +
1072 +#define AR2315_LB_INT_TX_DESC 0x00000001
1073 +#define AR2315_LB_INT_TX_OK 0x00000002
1074 +#define AR2315_LB_INT_TX_ERR 0x00000004
1075 +#define AR2315_LB_INT_TX_EOF 0x00000008
1076 +#define AR2315_LB_INT_RX_DESC 0x00000010
1077 +#define AR2315_LB_INT_RX_OK 0x00000020
1078 +#define AR2315_LB_INT_RX_ERR 0x00000040
1079 +#define AR2315_LB_INT_RX_EOF 0x00000080
1080 +#define AR2315_LB_INT_TX_TRUNC 0x00000100
1081 +#define AR2315_LB_INT_TX_STARVE 0x00000200
1082 +#define AR2315_LB_INT_LB_TIMEOUT 0x00000400
1083 +#define AR2315_LB_INT_LB_ERR 0x00000800
1084 +#define AR2315_LB_INT_MBOX_WR 0x00001000
1085 +#define AR2315_LB_INT_MBOX_RD 0x00002000
1086 +
1087 +/* Bit definitions for INT MASK are the same as INT_STATUS */
1088 +#define AR2315_LB_INT_MASK 0x0504
1089 +
1090 +#define AR2315_LB_INT_EN 0x0508
1091 +#define AR2315_LB_MBOX 0x0600
1092 +
1093 +#endif /* __ASM_MACH_ATH25_AR2315_REGS_H */
1094 --- /dev/null
1095 +++ b/arch/mips/ath25/ar5312_regs.h
1096 @@ -0,0 +1,223 @@
1097 +/*
1098 + * This file is subject to the terms and conditions of the GNU General Public
1099 + * License. See the file "COPYING" in the main directory of this archive
1100 + * for more details.
1101 + *
1102 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1103 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1104 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
1105 + */
1106 +
1107 +#ifndef __ASM_MACH_ATH25_AR5312_REGS_H
1108 +#define __ASM_MACH_ATH25_AR5312_REGS_H
1109 +
1110 +/*
1111 + * IRQs
1112 + */
1113 +#define AR5312_IRQ_WLAN0 (MIPS_CPU_IRQ_BASE + 2) /* C0_CAUSE: 0x0400 */
1114 +#define AR5312_IRQ_ENET0 (MIPS_CPU_IRQ_BASE + 3) /* C0_CAUSE: 0x0800 */
1115 +#define AR5312_IRQ_ENET1 (MIPS_CPU_IRQ_BASE + 4) /* C0_CAUSE: 0x1000 */
1116 +#define AR5312_IRQ_WLAN1 (MIPS_CPU_IRQ_BASE + 5) /* C0_CAUSE: 0x2000 */
1117 +#define AR5312_IRQ_MISC (MIPS_CPU_IRQ_BASE + 6) /* C0_CAUSE: 0x4000 */
1118 +
1119 +/*
1120 + * Miscellaneous interrupts, which share IP6.
1121 + */
1122 +#define AR5312_MISC_IRQ_TIMER 0
1123 +#define AR5312_MISC_IRQ_AHB_PROC 1
1124 +#define AR5312_MISC_IRQ_AHB_DMA 2
1125 +#define AR5312_MISC_IRQ_GPIO 3
1126 +#define AR5312_MISC_IRQ_UART0 4
1127 +#define AR5312_MISC_IRQ_UART0_DMA 5
1128 +#define AR5312_MISC_IRQ_WATCHDOG 6
1129 +#define AR5312_MISC_IRQ_LOCAL 7
1130 +#define AR5312_MISC_IRQ_SPI 8
1131 +#define AR5312_MISC_IRQ_COUNT 9
1132 +
1133 +/*
1134 + * Address Map
1135 + *
1136 + * The AR5312 supports 2 enet MACS, even though many reference boards only
1137 + * actually use 1 of them (i.e. Only MAC 0 is actually connected to an enet
1138 + * PHY or PHY switch. The AR2312 supports 1 enet MAC.
1139 + */
1140 +#define AR5312_WLAN0_BASE 0x18000000
1141 +#define AR5312_ENET0_BASE 0x18100000
1142 +#define AR5312_ENET1_BASE 0x18200000
1143 +#define AR5312_SDRAMCTL_BASE 0x18300000
1144 +#define AR5312_SDRAMCTL_SIZE 0x00000010
1145 +#define AR5312_FLASHCTL_BASE 0x18400000
1146 +#define AR5312_FLASHCTL_SIZE 0x00000010
1147 +#define AR5312_WLAN1_BASE 0x18500000
1148 +#define AR5312_UART0_BASE 0x1c000000 /* UART MMR */
1149 +#define AR5312_GPIO_BASE 0x1c002000
1150 +#define AR5312_GPIO_SIZE 0x00000010
1151 +#define AR5312_RST_BASE 0x1c003000
1152 +#define AR5312_RST_SIZE 0x00000100
1153 +#define AR5312_FLASH_BASE 0x1e000000
1154 +#define AR5312_FLASH_SIZE 0x00800000
1155 +
1156 +/*
1157 + * Need these defines to determine true number of ethernet MACs
1158 + */
1159 +#define AR5312_AR5312_REV2 0x0052 /* AR5312 WMAC (AP31) */
1160 +#define AR5312_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
1161 +#define AR5312_AR2313_REV8 0x0058 /* AR2313 WMAC (AP43-030) */
1162 +
1163 +/* Reset/Timer Block Address Map */
1164 +#define AR5312_TIMER 0x0000 /* countdown timer */
1165 +#define AR5312_RELOAD 0x0004 /* timer reload value */
1166 +#define AR5312_WDT_CTRL 0x0008 /* watchdog cntrl */
1167 +#define AR5312_WDT_TIMER 0x000c /* watchdog timer */
1168 +#define AR5312_ISR 0x0010 /* Intr Status Reg */
1169 +#define AR5312_IMR 0x0014 /* Intr Mask Reg */
1170 +#define AR5312_RESET 0x0020
1171 +#define AR5312_CLOCKCTL1 0x0064
1172 +#define AR5312_SCRATCH 0x006c
1173 +#define AR5312_PROCADDR 0x0070
1174 +#define AR5312_PROC1 0x0074
1175 +#define AR5312_DMAADDR 0x0078
1176 +#define AR5312_DMA1 0x007c
1177 +#define AR5312_ENABLE 0x0080 /* interface enb */
1178 +#define AR5312_REV 0x0090 /* revision */
1179 +
1180 +/* AR5312_WDT_CTRL register bit field definitions */
1181 +#define AR5312_WDT_CTRL_IGNORE 0x00000000 /* ignore expiration */
1182 +#define AR5312_WDT_CTRL_NMI 0x00000001
1183 +#define AR5312_WDT_CTRL_RESET 0x00000002
1184 +
1185 +/* AR5312_ISR register bit field definitions */
1186 +#define AR5312_ISR_TIMER 0x0001
1187 +#define AR5312_ISR_AHBPROC 0x0002
1188 +#define AR5312_ISR_AHBDMA 0x0004
1189 +#define AR5312_ISR_GPIO 0x0008
1190 +#define AR5312_ISR_UART0 0x0010
1191 +#define AR5312_ISR_UART0DMA 0x0020
1192 +#define AR5312_ISR_WD 0x0040
1193 +#define AR5312_ISR_LOCAL 0x0080
1194 +
1195 +/* AR5312_RESET register bit field definitions */
1196 +#define AR5312_RESET_SYSTEM 0x00000001 /* cold reset full system */
1197 +#define AR5312_RESET_PROC 0x00000002 /* cold reset MIPS core */
1198 +#define AR5312_RESET_WLAN0 0x00000004 /* cold reset WLAN MAC and BB */
1199 +#define AR5312_RESET_EPHY0 0x00000008 /* cold reset ENET0 phy */
1200 +#define AR5312_RESET_EPHY1 0x00000010 /* cold reset ENET1 phy */
1201 +#define AR5312_RESET_ENET0 0x00000020 /* cold reset ENET0 mac */
1202 +#define AR5312_RESET_ENET1 0x00000040 /* cold reset ENET1 mac */
1203 +#define AR5312_RESET_UART0 0x00000100 /* cold reset UART0 (high speed) */
1204 +#define AR5312_RESET_WLAN1 0x00000200 /* cold reset WLAN MAC/BB */
1205 +#define AR5312_RESET_APB 0x00000400 /* cold reset APB (ar5312) */
1206 +#define AR5312_RESET_WARM_PROC 0x00001000 /* warm reset MIPS core */
1207 +#define AR5312_RESET_WARM_WLAN0_MAC 0x00002000 /* warm reset WLAN0 MAC */
1208 +#define AR5312_RESET_WARM_WLAN0_BB 0x00004000 /* warm reset WLAN0 BaseBand */
1209 +#define AR5312_RESET_NMI 0x00010000 /* send an NMI to the processor */
1210 +#define AR5312_RESET_WARM_WLAN1_MAC 0x00020000 /* warm reset WLAN1 mac */
1211 +#define AR5312_RESET_WARM_WLAN1_BB 0x00040000 /* warm reset WLAN1 baseband */
1212 +#define AR5312_RESET_LOCAL_BUS 0x00080000 /* reset local bus */
1213 +#define AR5312_RESET_WDOG 0x00100000 /* last reset was a watchdog */
1214 +
1215 +#define AR5312_RESET_WMAC0_BITS \
1216 + (AR5312_RESET_WLAN0 |\
1217 + AR5312_RESET_WARM_WLAN0_MAC |\
1218 + AR5312_RESET_WARM_WLAN0_BB)
1219 +
1220 +#define AR5312_RESET_WMAC1_BITS \
1221 + (AR5312_RESET_WLAN1 |\
1222 + AR5312_RESET_WARM_WLAN1_MAC |\
1223 + AR5312_RESET_WARM_WLAN1_BB)
1224 +
1225 +/* AR5312_CLOCKCTL1 register bit field definitions */
1226 +#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1227 +#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1228 +#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1229 +#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1230 +#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1231 +
1232 +/* Valid for AR5312 and AR2312 */
1233 +#define AR5312_CLOCKCTL1_PREDIVIDE_MASK 0x00000030
1234 +#define AR5312_CLOCKCTL1_PREDIVIDE_SHIFT 4
1235 +#define AR5312_CLOCKCTL1_MULTIPLIER_MASK 0x00001f00
1236 +#define AR5312_CLOCKCTL1_MULTIPLIER_SHIFT 8
1237 +#define AR5312_CLOCKCTL1_DOUBLER_MASK 0x00010000
1238 +
1239 +/* Valid for AR2313 */
1240 +#define AR2313_CLOCKCTL1_PREDIVIDE_MASK 0x00003000
1241 +#define AR2313_CLOCKCTL1_PREDIVIDE_SHIFT 12
1242 +#define AR2313_CLOCKCTL1_MULTIPLIER_MASK 0x001f0000
1243 +#define AR2313_CLOCKCTL1_MULTIPLIER_SHIFT 16
1244 +#define AR2313_CLOCKCTL1_DOUBLER_MASK 0x00000000
1245 +
1246 +/* AR5312_ENABLE register bit field definitions */
1247 +#define AR5312_ENABLE_WLAN0 0x0001
1248 +#define AR5312_ENABLE_ENET0 0x0002
1249 +#define AR5312_ENABLE_ENET1 0x0004
1250 +#define AR5312_ENABLE_UART_AND_WLAN1_PIO 0x0008 /* UART, and WLAN1 PIOs */
1251 +#define AR5312_ENABLE_WLAN1_DMA 0x0010 /* WLAN1 DMAs */
1252 +#define AR5312_ENABLE_WLAN1 \
1253 + (AR5312_ENABLE_UART_AND_WLAN1_PIO |\
1254 + AR5312_ENABLE_WLAN1_DMA)
1255 +
1256 +/* AR5312_REV register bit field definitions */
1257 +#define AR5312_REV_WMAC_MAJ 0xf000
1258 +#define AR5312_REV_WMAC_MAJ_S 12
1259 +#define AR5312_REV_WMAC_MIN 0x0f00
1260 +#define AR5312_REV_WMAC_MIN_S 8
1261 +#define AR5312_REV_MAJ 0x00f0
1262 +#define AR5312_REV_MAJ_S 4
1263 +#define AR5312_REV_MIN 0x000f
1264 +#define AR5312_REV_MIN_S 0
1265 +#define AR5312_REV_CHIP (AR5312_REV_MAJ|AR5312_REV_MIN)
1266 +
1267 +/* Major revision numbers, bits 7..4 of Revision ID register */
1268 +#define AR5312_REV_MAJ_AR5312 0x4
1269 +#define AR5312_REV_MAJ_AR2313 0x5
1270 +
1271 +/* Minor revision numbers, bits 3..0 of Revision ID register */
1272 +#define AR5312_REV_MIN_DUAL 0x0 /* Dual WLAN version */
1273 +#define AR5312_REV_MIN_SINGLE 0x1 /* Single WLAN version */
1274 +
1275 +/* ARM Flash Controller -- 3 flash banks with either x8 or x16 devices. */
1276 +#define AR5312_FLASHCTL0 0x0000
1277 +#define AR5312_FLASHCTL1 0x0004
1278 +#define AR5312_FLASHCTL2 0x0008
1279 +
1280 +/* AR5312_FLASHCTL register bit field definitions */
1281 +#define AR5312_FLASHCTL_IDCY 0x0000000f /* Idle cycle turnaround time */
1282 +#define AR5312_FLASHCTL_IDCY_S 0
1283 +#define AR5312_FLASHCTL_WST1 0x000003e0 /* Wait state 1 */
1284 +#define AR5312_FLASHCTL_WST1_S 5
1285 +#define AR5312_FLASHCTL_RBLE 0x00000400 /* Read byte lane enable */
1286 +#define AR5312_FLASHCTL_WST2 0x0000f800 /* Wait state 2 */
1287 +#define AR5312_FLASHCTL_WST2_S 11
1288 +#define AR5312_FLASHCTL_AC 0x00070000 /* Flash addr check (added) */
1289 +#define AR5312_FLASHCTL_AC_S 16
1290 +#define AR5312_FLASHCTL_AC_128K 0x00000000
1291 +#define AR5312_FLASHCTL_AC_256K 0x00010000
1292 +#define AR5312_FLASHCTL_AC_512K 0x00020000
1293 +#define AR5312_FLASHCTL_AC_1M 0x00030000
1294 +#define AR5312_FLASHCTL_AC_2M 0x00040000
1295 +#define AR5312_FLASHCTL_AC_4M 0x00050000
1296 +#define AR5312_FLASHCTL_AC_8M 0x00060000
1297 +#define AR5312_FLASHCTL_AC_RES 0x00070000 /* 16MB is not supported */
1298 +#define AR5312_FLASHCTL_E 0x00080000 /* Flash bank enable (added) */
1299 +#define AR5312_FLASHCTL_BUSERR 0x01000000 /* Bus transfer error flag */
1300 +#define AR5312_FLASHCTL_WPERR 0x02000000 /* Write protect error flag */
1301 +#define AR5312_FLASHCTL_WP 0x04000000 /* Write protect */
1302 +#define AR5312_FLASHCTL_BM 0x08000000 /* Burst mode */
1303 +#define AR5312_FLASHCTL_MW 0x30000000 /* Mem width */
1304 +#define AR5312_FLASHCTL_MW8 0x00000000 /* Mem width x8 */
1305 +#define AR5312_FLASHCTL_MW16 0x10000000 /* Mem width x16 */
1306 +#define AR5312_FLASHCTL_MW32 0x20000000 /* Mem width x32 (not supp) */
1307 +#define AR5312_FLASHCTL_ATNR 0x00000000 /* Access == no retry */
1308 +#define AR5312_FLASHCTL_ATR 0x80000000 /* Access == retry every */
1309 +#define AR5312_FLASHCTL_ATR4 0xc0000000 /* Access == retry every 4 */
1310 +
1311 +/* ARM SDRAM Controller -- just enough to determine memory size */
1312 +#define AR5312_MEM_CFG1 0x0004
1313 +
1314 +#define AR5312_MEM_CFG1_AC0_M 0x00000700 /* bank 0: SDRAM addr check */
1315 +#define AR5312_MEM_CFG1_AC0_S 8
1316 +#define AR5312_MEM_CFG1_AC1_M 0x00007000 /* bank 1: SDRAM addr check */
1317 +#define AR5312_MEM_CFG1_AC1_S 12
1318 +
1319 +#endif /* __ASM_MACH_ATH25_AR5312_REGS_H */
1320 --- /dev/null
1321 +++ b/arch/mips/ath25/ar5312.c
1322 @@ -0,0 +1,396 @@
1323 +/*
1324 + * This file is subject to the terms and conditions of the GNU General Public
1325 + * License. See the file "COPYING" in the main directory of this archive
1326 + * for more details.
1327 + *
1328 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1329 + * Copyright (C) 2006 FON Technology, SL.
1330 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1331 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
1332 + * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
1333 + */
1334 +
1335 +/*
1336 + * Platform devices for Atheros SoCs
1337 + */
1338 +
1339 +#include <linux/init.h>
1340 +#include <linux/kernel.h>
1341 +#include <linux/bitops.h>
1342 +#include <linux/irqdomain.h>
1343 +#include <linux/interrupt.h>
1344 +#include <linux/platform_device.h>
1345 +#include <linux/mtd/physmap.h>
1346 +#include <linux/reboot.h>
1347 +#include <asm/bootinfo.h>
1348 +#include <asm/reboot.h>
1349 +#include <asm/time.h>
1350 +
1351 +#include <ath25_platform.h>
1352 +
1353 +#include "devices.h"
1354 +#include "ar5312.h"
1355 +#include "ar5312_regs.h"
1356 +
1357 +static void __iomem *ar5312_rst_base;
1358 +static struct irq_domain *ar5312_misc_irq_domain;
1359 +
1360 +static inline u32 ar5312_rst_reg_read(u32 reg)
1361 +{
1362 + return __raw_readl(ar5312_rst_base + reg);
1363 +}
1364 +
1365 +static inline void ar5312_rst_reg_write(u32 reg, u32 val)
1366 +{
1367 + __raw_writel(val, ar5312_rst_base + reg);
1368 +}
1369 +
1370 +static inline void ar5312_rst_reg_mask(u32 reg, u32 mask, u32 val)
1371 +{
1372 + u32 ret = ar5312_rst_reg_read(reg);
1373 +
1374 + ret &= ~mask;
1375 + ret |= val;
1376 + ar5312_rst_reg_write(reg, ret);
1377 +}
1378 +
1379 +static irqreturn_t ar5312_ahb_err_handler(int cpl, void *dev_id)
1380 +{
1381 + u32 proc1 = ar5312_rst_reg_read(AR5312_PROC1);
1382 + u32 proc_addr = ar5312_rst_reg_read(AR5312_PROCADDR); /* clears error */
1383 + u32 dma1 = ar5312_rst_reg_read(AR5312_DMA1);
1384 + u32 dma_addr = ar5312_rst_reg_read(AR5312_DMAADDR); /* clears error */
1385 +
1386 + pr_emerg("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x DMAADDR=0x%8.8x DMA1=0x%8.8x\n",
1387 + proc_addr, proc1, dma_addr, dma1);
1388 +
1389 + machine_restart("AHB error"); /* Catastrophic failure */
1390 + return IRQ_HANDLED;
1391 +}
1392 +
1393 +static struct irqaction ar5312_ahb_err_interrupt = {
1394 + .handler = ar5312_ahb_err_handler,
1395 + .name = "ar5312-ahb-error",
1396 +};
1397 +
1398 +static void ar5312_misc_irq_handler(unsigned irq, struct irq_desc *desc)
1399 +{
1400 + u32 pending = ar5312_rst_reg_read(AR5312_ISR) &
1401 + ar5312_rst_reg_read(AR5312_IMR);
1402 + unsigned nr, misc_irq = 0;
1403 +
1404 + if (pending) {
1405 + struct irq_domain *domain = irq_get_handler_data(irq);
1406 +
1407 + nr = __ffs(pending);
1408 + misc_irq = irq_find_mapping(domain, nr);
1409 + }
1410 +
1411 + if (misc_irq) {
1412 + generic_handle_irq(misc_irq);
1413 + if (nr == AR5312_MISC_IRQ_TIMER)
1414 + ar5312_rst_reg_read(AR5312_TIMER);
1415 + } else {
1416 + spurious_interrupt();
1417 + }
1418 +}
1419 +
1420 +/* Enable the specified AR5312_MISC_IRQ interrupt */
1421 +static void ar5312_misc_irq_unmask(struct irq_data *d)
1422 +{
1423 + ar5312_rst_reg_mask(AR5312_IMR, 0, BIT(d->hwirq));
1424 +}
1425 +
1426 +/* Disable the specified AR5312_MISC_IRQ interrupt */
1427 +static void ar5312_misc_irq_mask(struct irq_data *d)
1428 +{
1429 + ar5312_rst_reg_mask(AR5312_IMR, BIT(d->hwirq), 0);
1430 + ar5312_rst_reg_read(AR5312_IMR); /* flush write buffer */
1431 +}
1432 +
1433 +static struct irq_chip ar5312_misc_irq_chip = {
1434 + .name = "ar5312-misc",
1435 + .irq_unmask = ar5312_misc_irq_unmask,
1436 + .irq_mask = ar5312_misc_irq_mask,
1437 +};
1438 +
1439 +static int ar5312_misc_irq_map(struct irq_domain *d, unsigned irq,
1440 + irq_hw_number_t hw)
1441 +{
1442 + irq_set_chip_and_handler(irq, &ar5312_misc_irq_chip, handle_level_irq);
1443 + return 0;
1444 +}
1445 +
1446 +static struct irq_domain_ops ar5312_misc_irq_domain_ops = {
1447 + .map = ar5312_misc_irq_map,
1448 +};
1449 +
1450 +static void ar5312_irq_dispatch(void)
1451 +{
1452 + u32 pending = read_c0_status() & read_c0_cause();
1453 +
1454 + if (pending & CAUSEF_IP2)
1455 + do_IRQ(AR5312_IRQ_WLAN0);
1456 + else if (pending & CAUSEF_IP5)
1457 + do_IRQ(AR5312_IRQ_WLAN1);
1458 + else if (pending & CAUSEF_IP6)
1459 + do_IRQ(AR5312_IRQ_MISC);
1460 + else if (pending & CAUSEF_IP7)
1461 + do_IRQ(ATH25_IRQ_CPU_CLOCK);
1462 + else
1463 + spurious_interrupt();
1464 +}
1465 +
1466 +void __init ar5312_arch_init_irq(void)
1467 +{
1468 + struct irq_domain *domain;
1469 + unsigned irq;
1470 +
1471 + ath25_irq_dispatch = ar5312_irq_dispatch;
1472 +
1473 + domain = irq_domain_add_linear(NULL, AR5312_MISC_IRQ_COUNT,
1474 + &ar5312_misc_irq_domain_ops, NULL);
1475 + if (!domain)
1476 + panic("Failed to add IRQ domain");
1477 +
1478 + irq = irq_create_mapping(domain, AR5312_MISC_IRQ_AHB_PROC);
1479 + setup_irq(irq, &ar5312_ahb_err_interrupt);
1480 +
1481 + irq_set_chained_handler(AR5312_IRQ_MISC, ar5312_misc_irq_handler);
1482 + irq_set_handler_data(AR5312_IRQ_MISC, domain);
1483 +
1484 + ar5312_misc_irq_domain = domain;
1485 +}
1486 +
1487 +static struct physmap_flash_data ar5312_flash_data = {
1488 + .width = 2,
1489 +};
1490 +
1491 +static struct resource ar5312_flash_resource = {
1492 + .start = AR5312_FLASH_BASE,
1493 + .end = AR5312_FLASH_BASE + AR5312_FLASH_SIZE - 1,
1494 + .flags = IORESOURCE_MEM,
1495 +};
1496 +
1497 +static struct platform_device ar5312_physmap_flash = {
1498 + .name = "physmap-flash",
1499 + .id = 0,
1500 + .dev.platform_data = &ar5312_flash_data,
1501 + .resource = &ar5312_flash_resource,
1502 + .num_resources = 1,
1503 +};
1504 +
1505 +static void __init ar5312_flash_init(void)
1506 +{
1507 + void __iomem *flashctl_base;
1508 + u32 ctl;
1509 +
1510 + flashctl_base = ioremap_nocache(AR5312_FLASHCTL_BASE,
1511 + AR5312_FLASHCTL_SIZE);
1512 +
1513 + ctl = __raw_readl(flashctl_base + AR5312_FLASHCTL0);
1514 + ctl &= AR5312_FLASHCTL_MW;
1515 +
1516 + /* fixup flash width */
1517 + switch (ctl) {
1518 + case AR5312_FLASHCTL_MW16:
1519 + ar5312_flash_data.width = 2;
1520 + break;
1521 + case AR5312_FLASHCTL_MW8:
1522 + default:
1523 + ar5312_flash_data.width = 1;
1524 + break;
1525 + }
1526 +
1527 + /*
1528 + * Configure flash bank 0.
1529 + * Assume 8M window size. Flash will be aliased if it's smaller
1530 + */
1531 + ctl |= AR5312_FLASHCTL_E | AR5312_FLASHCTL_AC_8M | AR5312_FLASHCTL_RBLE;
1532 + ctl |= 0x01 << AR5312_FLASHCTL_IDCY_S;
1533 + ctl |= 0x07 << AR5312_FLASHCTL_WST1_S;
1534 + ctl |= 0x07 << AR5312_FLASHCTL_WST2_S;
1535 + __raw_writel(ctl, flashctl_base + AR5312_FLASHCTL0);
1536 +
1537 + /* Disable other flash banks */
1538 + ctl = __raw_readl(flashctl_base + AR5312_FLASHCTL1);
1539 + ctl &= ~(AR5312_FLASHCTL_E | AR5312_FLASHCTL_AC);
1540 + __raw_writel(ctl, flashctl_base + AR5312_FLASHCTL1);
1541 + ctl = __raw_readl(flashctl_base + AR5312_FLASHCTL2);
1542 + ctl &= ~(AR5312_FLASHCTL_E | AR5312_FLASHCTL_AC);
1543 + __raw_writel(ctl, flashctl_base + AR5312_FLASHCTL2);
1544 +
1545 + iounmap(flashctl_base);
1546 +}
1547 +
1548 +void __init ar5312_init_devices(void)
1549 +{
1550 + struct ath25_boarddata *config;
1551 +
1552 + ar5312_flash_init();
1553 +
1554 + /* Locate board/radio config data */
1555 + ath25_find_config(AR5312_FLASH_BASE, AR5312_FLASH_SIZE);
1556 + config = ath25_board.config;
1557 +
1558 + /* AR2313 has CPU minor rev. 10 */
1559 + if ((current_cpu_data.processor_id & 0xff) == 0x0a)
1560 + ath25_soc = ATH25_SOC_AR2313;
1561 +
1562 + /* AR2312 shares the same Silicon ID as AR5312 */
1563 + else if (config->flags & BD_ISCASPER)
1564 + ath25_soc = ATH25_SOC_AR2312;
1565 +
1566 + /* Everything else is probably AR5312 or compatible */
1567 + else
1568 + ath25_soc = ATH25_SOC_AR5312;
1569 +
1570 + platform_device_register(&ar5312_physmap_flash);
1571 +
1572 + switch (ath25_soc) {
1573 + case ATH25_SOC_AR5312:
1574 + if (!ath25_board.radio)
1575 + return;
1576 +
1577 + if (!(config->flags & BD_WLAN0))
1578 + break;
1579 +
1580 + ath25_add_wmac(0, AR5312_WLAN0_BASE, AR5312_IRQ_WLAN0);
1581 + break;
1582 + case ATH25_SOC_AR2312:
1583 + case ATH25_SOC_AR2313:
1584 + if (!ath25_board.radio)
1585 + return;
1586 + break;
1587 + default:
1588 + break;
1589 + }
1590 +
1591 + if (config->flags & BD_WLAN1)
1592 + ath25_add_wmac(1, AR5312_WLAN1_BASE, AR5312_IRQ_WLAN1);
1593 +}
1594 +
1595 +static void ar5312_restart(char *command)
1596 +{
1597 + /* reset the system */
1598 + local_irq_disable();
1599 + while (1)
1600 + ar5312_rst_reg_write(AR5312_RESET, AR5312_RESET_SYSTEM);
1601 +}
1602 +
1603 +/*
1604 + * This table is indexed by bits 5..4 of the CLOCKCTL1 register
1605 + * to determine the predevisor value.
1606 + */
1607 +static unsigned clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
1608 +
1609 +static unsigned __init ar5312_cpu_frequency(void)
1610 +{
1611 + unsigned int scratch;
1612 + unsigned int predivide_mask, predivide_shift;
1613 + unsigned int multiplier_mask, multiplier_shift;
1614 + unsigned int clock_ctl1, predivide_select, predivisor, multiplier;
1615 + unsigned int doubler_mask;
1616 + u16 devid;
1617 +
1618 + /* Trust the bootrom's idea of cpu frequency. */
1619 + scratch = ar5312_rst_reg_read(AR5312_SCRATCH);
1620 + if (scratch)
1621 + return scratch;
1622 +
1623 + devid = ar5312_rst_reg_read(AR5312_REV);
1624 + devid &= AR5312_REV_MAJ;
1625 + devid >>= AR5312_REV_MAJ_S;
1626 + if (devid == AR5312_REV_MAJ_AR2313) {
1627 + predivide_mask = AR2313_CLOCKCTL1_PREDIVIDE_MASK;
1628 + predivide_shift = AR2313_CLOCKCTL1_PREDIVIDE_SHIFT;
1629 + multiplier_mask = AR2313_CLOCKCTL1_MULTIPLIER_MASK;
1630 + multiplier_shift = AR2313_CLOCKCTL1_MULTIPLIER_SHIFT;
1631 + doubler_mask = AR2313_CLOCKCTL1_DOUBLER_MASK;
1632 + } else { /* AR5312 and AR2312 */
1633 + predivide_mask = AR5312_CLOCKCTL1_PREDIVIDE_MASK;
1634 + predivide_shift = AR5312_CLOCKCTL1_PREDIVIDE_SHIFT;
1635 + multiplier_mask = AR5312_CLOCKCTL1_MULTIPLIER_MASK;
1636 + multiplier_shift = AR5312_CLOCKCTL1_MULTIPLIER_SHIFT;
1637 + doubler_mask = AR5312_CLOCKCTL1_DOUBLER_MASK;
1638 + }
1639 +
1640 + /*
1641 + * Clocking is derived from a fixed 40MHz input clock.
1642 + *
1643 + * cpu_freq = input_clock * MULT (where MULT is PLL multiplier)
1644 + * sys_freq = cpu_freq / 4 (used for APB clock, serial,
1645 + * flash, Timer, Watchdog Timer)
1646 + *
1647 + * cnt_freq = cpu_freq / 2 (use for CPU count/compare)
1648 + *
1649 + * So, for example, with a PLL multiplier of 5, we have
1650 + *
1651 + * cpu_freq = 200MHz
1652 + * sys_freq = 50MHz
1653 + * cnt_freq = 100MHz
1654 + *
1655 + * We compute the CPU frequency, based on PLL settings.
1656 + */
1657 +
1658 + clock_ctl1 = ar5312_rst_reg_read(AR5312_CLOCKCTL1);
1659 + predivide_select = (clock_ctl1 & predivide_mask) >> predivide_shift;
1660 + predivisor = clockctl1_predivide_table[predivide_select];
1661 + multiplier = (clock_ctl1 & multiplier_mask) >> multiplier_shift;
1662 +
1663 + if (clock_ctl1 & doubler_mask)
1664 + multiplier = multiplier << 1;
1665 +
1666 + return (40000000 / predivisor) * multiplier;
1667 +}
1668 +
1669 +static inline unsigned ar5312_sys_frequency(void)
1670 +{
1671 + return ar5312_cpu_frequency() / 4;
1672 +}
1673 +
1674 +void __init ar5312_plat_time_init(void)
1675 +{
1676 + mips_hpt_frequency = ar5312_cpu_frequency() / 2;
1677 +}
1678 +
1679 +void __init ar5312_plat_mem_setup(void)
1680 +{
1681 + void __iomem *sdram_base;
1682 + u32 memsize, memcfg, bank0_ac, bank1_ac;
1683 + u32 devid;
1684 +
1685 + /* Detect memory size */
1686 + sdram_base = ioremap_nocache(AR5312_SDRAMCTL_BASE,
1687 + AR5312_SDRAMCTL_SIZE);
1688 + memcfg = __raw_readl(sdram_base + AR5312_MEM_CFG1);
1689 + bank0_ac = ATH25_REG_MS(memcfg, AR5312_MEM_CFG1_AC0);
1690 + bank1_ac = ATH25_REG_MS(memcfg, AR5312_MEM_CFG1_AC1);
1691 + memsize = (bank0_ac ? (1 << (bank0_ac + 1)) : 0) +
1692 + (bank1_ac ? (1 << (bank1_ac + 1)) : 0);
1693 + memsize <<= 20;
1694 + add_memory_region(0, memsize, BOOT_MEM_RAM);
1695 + iounmap(sdram_base);
1696 +
1697 + ar5312_rst_base = ioremap_nocache(AR5312_RST_BASE, AR5312_RST_SIZE);
1698 +
1699 + devid = ar5312_rst_reg_read(AR5312_REV);
1700 + devid >>= AR5312_REV_WMAC_MIN_S;
1701 + devid &= AR5312_REV_CHIP;
1702 + ath25_board.devid = (u16)devid;
1703 +
1704 + /* Clear any lingering AHB errors */
1705 + ar5312_rst_reg_read(AR5312_PROCADDR);
1706 + ar5312_rst_reg_read(AR5312_DMAADDR);
1707 + ar5312_rst_reg_write(AR5312_WDT_CTRL, AR5312_WDT_CTRL_IGNORE);
1708 +
1709 + _machine_restart = ar5312_restart;
1710 +}
1711 +
1712 +void __init ar5312_arch_init(void)
1713 +{
1714 + unsigned irq = irq_create_mapping(ar5312_misc_irq_domain,
1715 + AR5312_MISC_IRQ_UART0);
1716 +
1717 + ath25_serial_setup(AR5312_UART0_BASE, irq, ar5312_sys_frequency());
1718 +}
1719 --- /dev/null
1720 +++ b/arch/mips/ath25/ar2315.c
1721 @@ -0,0 +1,307 @@
1722 +/*
1723 + * This file is subject to the terms and conditions of the GNU General Public
1724 + * License. See the file "COPYING" in the main directory of this archive
1725 + * for more details.
1726 + *
1727 + * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
1728 + * Copyright (C) 2006 FON Technology, SL.
1729 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1730 + * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
1731 + * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
1732 + */
1733 +
1734 +/*
1735 + * Platform devices for Atheros SoCs
1736 + */
1737 +
1738 +#include <linux/init.h>
1739 +#include <linux/kernel.h>
1740 +#include <linux/bitops.h>
1741 +#include <linux/irqdomain.h>
1742 +#include <linux/interrupt.h>
1743 +#include <linux/platform_device.h>
1744 +#include <linux/reboot.h>
1745 +#include <asm/bootinfo.h>
1746 +#include <asm/reboot.h>
1747 +#include <asm/time.h>
1748 +
1749 +#include <ath25_platform.h>
1750 +
1751 +#include "devices.h"
1752 +#include "ar2315.h"
1753 +#include "ar2315_regs.h"
1754 +
1755 +static void __iomem *ar2315_rst_base;
1756 +static struct irq_domain *ar2315_misc_irq_domain;
1757 +
1758 +static inline u32 ar2315_rst_reg_read(u32 reg)
1759 +{
1760 + return __raw_readl(ar2315_rst_base + reg);
1761 +}
1762 +
1763 +static inline void ar2315_rst_reg_write(u32 reg, u32 val)
1764 +{
1765 + __raw_writel(val, ar2315_rst_base + reg);
1766 +}
1767 +
1768 +static inline void ar2315_rst_reg_mask(u32 reg, u32 mask, u32 val)
1769 +{
1770 + u32 ret = ar2315_rst_reg_read(reg);
1771 +
1772 + ret &= ~mask;
1773 + ret |= val;
1774 + ar2315_rst_reg_write(reg, ret);
1775 +}
1776 +
1777 +static irqreturn_t ar2315_ahb_err_handler(int cpl, void *dev_id)
1778 +{
1779 + ar2315_rst_reg_write(AR2315_AHB_ERR0, AR2315_AHB_ERROR_DET);
1780 + ar2315_rst_reg_read(AR2315_AHB_ERR1);
1781 +
1782 + pr_emerg("AHB fatal error\n");
1783 + machine_restart("AHB error"); /* Catastrophic failure */
1784 +
1785 + return IRQ_HANDLED;
1786 +}
1787 +
1788 +static struct irqaction ar2315_ahb_err_interrupt = {
1789 + .handler = ar2315_ahb_err_handler,
1790 + .name = "ar2315-ahb-error",
1791 +};
1792 +
1793 +static void ar2315_misc_irq_handler(unsigned irq, struct irq_desc *desc)
1794 +{
1795 + u32 pending = ar2315_rst_reg_read(AR2315_ISR) &
1796 + ar2315_rst_reg_read(AR2315_IMR);
1797 + unsigned nr, misc_irq = 0;
1798 +
1799 + if (pending) {
1800 + struct irq_domain *domain = irq_get_handler_data(irq);
1801 +
1802 + nr = __ffs(pending);
1803 + misc_irq = irq_find_mapping(domain, nr);
1804 + }
1805 +
1806 + if (misc_irq) {
1807 + if (nr == AR2315_MISC_IRQ_GPIO)
1808 + ar2315_rst_reg_write(AR2315_ISR, AR2315_ISR_GPIO);
1809 + else if (nr == AR2315_MISC_IRQ_WATCHDOG)
1810 + ar2315_rst_reg_write(AR2315_ISR, AR2315_ISR_WD);
1811 + generic_handle_irq(misc_irq);
1812 + } else {
1813 + spurious_interrupt();
1814 + }
1815 +}
1816 +
1817 +static void ar2315_misc_irq_unmask(struct irq_data *d)
1818 +{
1819 + ar2315_rst_reg_mask(AR2315_IMR, 0, BIT(d->hwirq));
1820 +}
1821 +
1822 +static void ar2315_misc_irq_mask(struct irq_data *d)
1823 +{
1824 + ar2315_rst_reg_mask(AR2315_IMR, BIT(d->hwirq), 0);
1825 +}
1826 +
1827 +static struct irq_chip ar2315_misc_irq_chip = {
1828 + .name = "ar2315-misc",
1829 + .irq_unmask = ar2315_misc_irq_unmask,
1830 + .irq_mask = ar2315_misc_irq_mask,
1831 +};
1832 +
1833 +static int ar2315_misc_irq_map(struct irq_domain *d, unsigned irq,
1834 + irq_hw_number_t hw)
1835 +{
1836 + irq_set_chip_and_handler(irq, &ar2315_misc_irq_chip, handle_level_irq);
1837 + return 0;
1838 +}
1839 +
1840 +static struct irq_domain_ops ar2315_misc_irq_domain_ops = {
1841 + .map = ar2315_misc_irq_map,
1842 +};
1843 +
1844 +/*
1845 + * Called when an interrupt is received, this function
1846 + * determines exactly which interrupt it was, and it
1847 + * invokes the appropriate handler.
1848 + *
1849 + * Implicitly, we also define interrupt priority by
1850 + * choosing which to dispatch first.
1851 + */
1852 +static void ar2315_irq_dispatch(void)
1853 +{
1854 + u32 pending = read_c0_status() & read_c0_cause();
1855 +
1856 + if (pending & CAUSEF_IP3)
1857 + do_IRQ(AR2315_IRQ_WLAN0);
1858 + else if (pending & CAUSEF_IP2)
1859 + do_IRQ(AR2315_IRQ_MISC);
1860 + else if (pending & CAUSEF_IP7)
1861 + do_IRQ(ATH25_IRQ_CPU_CLOCK);
1862 + else
1863 + spurious_interrupt();
1864 +}
1865 +
1866 +void __init ar2315_arch_init_irq(void)
1867 +{
1868 + struct irq_domain *domain;
1869 + unsigned irq;
1870 +
1871 + ath25_irq_dispatch = ar2315_irq_dispatch;
1872 +
1873 + domain = irq_domain_add_linear(NULL, AR2315_MISC_IRQ_COUNT,
1874 + &ar2315_misc_irq_domain_ops, NULL);
1875 + if (!domain)
1876 + panic("Failed to add IRQ domain");
1877 +
1878 + irq = irq_create_mapping(domain, AR2315_MISC_IRQ_AHB);
1879 + setup_irq(irq, &ar2315_ahb_err_interrupt);
1880 +
1881 + irq_set_chained_handler(AR2315_IRQ_MISC, ar2315_misc_irq_handler);
1882 + irq_set_handler_data(AR2315_IRQ_MISC, domain);
1883 +
1884 + ar2315_misc_irq_domain = domain;
1885 +}
1886 +
1887 +void __init ar2315_init_devices(void)
1888 +{
1889 + /* Find board configuration */
1890 + ath25_find_config(AR2315_SPI_READ_BASE, AR2315_SPI_READ_SIZE);
1891 +
1892 + ath25_add_wmac(0, AR2315_WLAN0_BASE, AR2315_IRQ_WLAN0);
1893 +}
1894 +
1895 +static void ar2315_restart(char *command)
1896 +{
1897 + void (*mips_reset_vec)(void) = (void *)0xbfc00000;
1898 +
1899 + local_irq_disable();
1900 +
1901 + /* try reset the system via reset control */
1902 + ar2315_rst_reg_write(AR2315_COLD_RESET, AR2317_RESET_SYSTEM);
1903 +
1904 + /* Cold reset does not work on the AR2315/6, use the GPIO reset bits
1905 + * a workaround. Give it some time to attempt a gpio based hardware
1906 + * reset (atheros reference design workaround) */
1907 +
1908 + /* TODO: implement the GPIO reset workaround */
1909 +
1910 + /* Some boards (e.g. Senao EOC-2610) don't implement the reset logic
1911 + * workaround. Attempt to jump to the mips reset location -
1912 + * the boot loader itself might be able to recover the system */
1913 + mips_reset_vec();
1914 +}
1915 +
1916 +/*
1917 + * This table is indexed by bits 5..4 of the CLOCKCTL1 register
1918 + * to determine the predevisor value.
1919 + */
1920 +static int clockctl1_predivide_table[4] __initdata = { 1, 2, 4, 5 };
1921 +static int pllc_divide_table[5] __initdata = { 2, 3, 4, 6, 3 };
1922 +
1923 +static unsigned __init ar2315_sys_clk(u32 clock_ctl)
1924 +{
1925 + unsigned int pllc_ctrl, cpu_div;
1926 + unsigned int pllc_out, refdiv, fdiv, divby2;
1927 + unsigned int clk_div;
1928 +
1929 + pllc_ctrl = ar2315_rst_reg_read(AR2315_PLLC_CTL);
1930 + refdiv = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_REF_DIV);
1931 + refdiv = clockctl1_predivide_table[refdiv];
1932 + fdiv = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_FDBACK_DIV);
1933 + divby2 = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_ADD_FDBACK_DIV) + 1;
1934 + pllc_out = (40000000/refdiv)*(2*divby2)*fdiv;
1935 +
1936 + /* clkm input selected */
1937 + switch (clock_ctl & AR2315_CPUCLK_CLK_SEL_M) {
1938 + case 0:
1939 + case 1:
1940 + clk_div = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_CLKM_DIV);
1941 + clk_div = pllc_divide_table[clk_div];
1942 + break;
1943 + case 2:
1944 + clk_div = ATH25_REG_MS(pllc_ctrl, AR2315_PLLC_CLKC_DIV);
1945 + clk_div = pllc_divide_table[clk_div];
1946 + break;
1947 + default:
1948 + pllc_out = 40000000;
1949 + clk_div = 1;
1950 + break;
1951 + }
1952 +
1953 + cpu_div = ATH25_REG_MS(clock_ctl, AR2315_CPUCLK_CLK_DIV);
1954 + cpu_div = cpu_div * 2 ?: 1;
1955 +
1956 + return pllc_out / (clk_div * cpu_div);
1957 +}
1958 +
1959 +static inline unsigned ar2315_cpu_frequency(void)
1960 +{
1961 + return ar2315_sys_clk(ar2315_rst_reg_read(AR2315_CPUCLK));
1962 +}
1963 +
1964 +static inline unsigned ar2315_apb_frequency(void)
1965 +{
1966 + return ar2315_sys_clk(ar2315_rst_reg_read(AR2315_AMBACLK));
1967 +}
1968 +
1969 +void __init ar2315_plat_time_init(void)
1970 +{
1971 + mips_hpt_frequency = ar2315_cpu_frequency() / 2;
1972 +}
1973 +
1974 +void __init ar2315_plat_mem_setup(void)
1975 +{
1976 + void __iomem *sdram_base;
1977 + u32 memsize, memcfg;
1978 + u32 devid;
1979 + u32 config;
1980 +
1981 + sdram_base = ioremap_nocache(AR2315_SDRAMCTL_BASE,
1982 + AR2315_SDRAMCTL_SIZE);
1983 + memcfg = __raw_readl(sdram_base + AR2315_MEM_CFG);
1984 + memsize = 1 + ATH25_REG_MS(memcfg, AR2315_MEM_CFG_DATA_WIDTH);
1985 + memsize <<= 1 + ATH25_REG_MS(memcfg, AR2315_MEM_CFG_COL_WIDTH);
1986 + memsize <<= 1 + ATH25_REG_MS(memcfg, AR2315_MEM_CFG_ROW_WIDTH);
1987 + memsize <<= 3;
1988 + add_memory_region(0, memsize, BOOT_MEM_RAM);
1989 + iounmap(sdram_base);
1990 +
1991 + ar2315_rst_base = ioremap_nocache(AR2315_RST_BASE, AR2315_RST_SIZE);
1992 +
1993 + /* Detect the hardware based on the device ID */
1994 + devid = ar2315_rst_reg_read(AR2315_SREV) & AR2315_REV_CHIP;
1995 + switch (devid) {
1996 + case 0x91: /* Need to check */
1997 + ath25_soc = ATH25_SOC_AR2318;
1998 + break;
1999 + case 0x90:
2000 + ath25_soc = ATH25_SOC_AR2317;
2001 + break;
2002 + case 0x87:
2003 + ath25_soc = ATH25_SOC_AR2316;
2004 + break;
2005 + case 0x86:
2006 + default:
2007 + ath25_soc = ATH25_SOC_AR2315;
2008 + break;
2009 + }
2010 + ath25_board.devid = devid;
2011 +
2012 + /* Clear any lingering AHB errors */
2013 + config = read_c0_config();
2014 + write_c0_config(config & ~0x3);
2015 + ar2315_rst_reg_write(AR2315_AHB_ERR0, AR2315_AHB_ERROR_DET);
2016 + ar2315_rst_reg_read(AR2315_AHB_ERR1);
2017 + ar2315_rst_reg_write(AR2315_WDT_CTRL, AR2315_WDT_CTRL_IGNORE);
2018 +
2019 + _machine_restart = ar2315_restart;
2020 +}
2021 +
2022 +void __init ar2315_arch_init(void)
2023 +{
2024 + unsigned irq = irq_create_mapping(ar2315_misc_irq_domain,
2025 + AR2315_MISC_IRQ_UART0);
2026 +
2027 + ath25_serial_setup(AR2315_UART0_BASE, irq, ar2315_apb_frequency());
2028 +}
2029 --- /dev/null
2030 +++ b/arch/mips/ath25/ar2315.h
2031 @@ -0,0 +1,36 @@
2032 +#ifndef __AR2315_H
2033 +#define __AR2315_H
2034 +
2035 +#ifdef CONFIG_SOC_AR2315
2036 +
2037 +void ar2315_arch_init_irq(void);
2038 +void ar2315_init_devices(void);
2039 +void ar2315_plat_time_init(void);
2040 +void ar2315_plat_mem_setup(void);
2041 +void ar2315_arch_init(void);
2042 +
2043 +#else
2044 +
2045 +static inline void ar2315_arch_init_irq(void)
2046 +{
2047 +}
2048 +
2049 +static inline void ar2315_init_devices(void)
2050 +{
2051 +}
2052 +
2053 +static inline void ar2315_plat_time_init(void)
2054 +{
2055 +}
2056 +
2057 +static inline void ar2315_plat_mem_setup(void)
2058 +{
2059 +}
2060 +
2061 +static inline void ar2315_arch_init(void)
2062 +{
2063 +}
2064 +
2065 +#endif
2066 +
2067 +#endif
2068 --- /dev/null
2069 +++ b/arch/mips/ath25/ar5312.h
2070 @@ -0,0 +1,36 @@
2071 +#ifndef __AR5312_H
2072 +#define __AR5312_H
2073 +
2074 +#ifdef CONFIG_SOC_AR5312
2075 +
2076 +void ar5312_arch_init_irq(void);
2077 +void ar5312_init_devices(void);
2078 +void ar5312_plat_time_init(void);
2079 +void ar5312_plat_mem_setup(void);
2080 +void ar5312_arch_init(void);
2081 +
2082 +#else
2083 +
2084 +static inline void ar5312_arch_init_irq(void)
2085 +{
2086 +}
2087 +
2088 +static inline void ar5312_init_devices(void)
2089 +{
2090 +}
2091 +
2092 +static inline void ar5312_plat_time_init(void)
2093 +{
2094 +}
2095 +
2096 +static inline void ar5312_plat_mem_setup(void)
2097 +{
2098 +}
2099 +
2100 +static inline void ar5312_arch_init(void)
2101 +{
2102 +}
2103 +
2104 +#endif
2105 +
2106 +#endif
2107 --- /dev/null
2108 +++ b/arch/mips/ath25/devices.h
2109 @@ -0,0 +1,43 @@
2110 +#ifndef __ATH25_DEVICES_H
2111 +#define __ATH25_DEVICES_H
2112 +
2113 +#include <linux/cpu.h>
2114 +
2115 +#define ATH25_REG_MS(_val, _field) (((_val) & _field##_M) >> _field##_S)
2116 +
2117 +#define ATH25_IRQ_CPU_CLOCK (MIPS_CPU_IRQ_BASE + 7) /* C0_CAUSE: 0x8000 */
2118 +
2119 +enum ath25_soc_type {
2120 + /* handled by ar5312.c */
2121 + ATH25_SOC_AR2312,
2122 + ATH25_SOC_AR2313,
2123 + ATH25_SOC_AR5312,
2124 +
2125 + /* handled by ar2315.c */
2126 + ATH25_SOC_AR2315,
2127 + ATH25_SOC_AR2316,
2128 + ATH25_SOC_AR2317,
2129 + ATH25_SOC_AR2318,
2130 +
2131 + ATH25_SOC_UNKNOWN
2132 +};
2133 +
2134 +extern enum ath25_soc_type ath25_soc;
2135 +extern struct ar231x_board_config ath25_board;
2136 +extern void (*ath25_irq_dispatch)(void);
2137 +
2138 +int ath25_find_config(phys_addr_t offset, unsigned long size);
2139 +void ath25_serial_setup(u32 mapbase, int irq, unsigned int uartclk);
2140 +int ath25_add_wmac(int nr, u32 base, int irq);
2141 +
2142 +static inline bool is_ar2315(void)
2143 +{
2144 + return (current_cpu_data.cputype == CPU_4KEC);
2145 +}
2146 +
2147 +static inline bool is_ar5312(void)
2148 +{
2149 + return !is_ar2315();
2150 +}
2151 +
2152 +#endif
2153 --- /dev/null
2154 +++ b/arch/mips/ath25/devices.c
2155 @@ -0,0 +1,125 @@
2156 +#include <linux/kernel.h>
2157 +#include <linux/init.h>
2158 +#include <linux/serial_8250.h>
2159 +#include <linux/platform_device.h>
2160 +#include <asm/bootinfo.h>
2161 +
2162 +#include <ath25_platform.h>
2163 +#include "devices.h"
2164 +#include "ar5312.h"
2165 +#include "ar2315.h"
2166 +
2167 +struct ar231x_board_config ath25_board;
2168 +enum ath25_soc_type ath25_soc = ATH25_SOC_UNKNOWN;
2169 +
2170 +static struct resource ath25_wmac0_res[] = {
2171 + {
2172 + .name = "wmac0_membase",
2173 + .flags = IORESOURCE_MEM,
2174 + },
2175 + {
2176 + .name = "wmac0_irq",
2177 + .flags = IORESOURCE_IRQ,
2178 + }
2179 +};
2180 +
2181 +static struct resource ath25_wmac1_res[] = {
2182 + {
2183 + .name = "wmac1_membase",
2184 + .flags = IORESOURCE_MEM,
2185 + },
2186 + {
2187 + .name = "wmac1_irq",
2188 + .flags = IORESOURCE_IRQ,
2189 + }
2190 +};
2191 +
2192 +static struct platform_device ath25_wmac[] = {
2193 + {
2194 + .id = 0,
2195 + .name = "ar231x-wmac",
2196 + .resource = ath25_wmac0_res,
2197 + .num_resources = ARRAY_SIZE(ath25_wmac0_res),
2198 + .dev.platform_data = &ath25_board,
2199 + },
2200 + {
2201 + .id = 1,
2202 + .name = "ar231x-wmac",
2203 + .resource = ath25_wmac1_res,
2204 + .num_resources = ARRAY_SIZE(ath25_wmac1_res),
2205 + .dev.platform_data = &ath25_board,
2206 + },
2207 +};
2208 +
2209 +static const char * const soc_type_strings[] = {
2210 + [ATH25_SOC_AR5312] = "Atheros AR5312",
2211 + [ATH25_SOC_AR2312] = "Atheros AR2312",
2212 + [ATH25_SOC_AR2313] = "Atheros AR2313",
2213 + [ATH25_SOC_AR2315] = "Atheros AR2315",
2214 + [ATH25_SOC_AR2316] = "Atheros AR2316",
2215 + [ATH25_SOC_AR2317] = "Atheros AR2317",
2216 + [ATH25_SOC_AR2318] = "Atheros AR2318",
2217 + [ATH25_SOC_UNKNOWN] = "Atheros (unknown)",
2218 +};
2219 +
2220 +const char *get_system_type(void)
2221 +{
2222 + if ((ath25_soc >= ARRAY_SIZE(soc_type_strings)) ||
2223 + !soc_type_strings[ath25_soc])
2224 + return soc_type_strings[ATH25_SOC_UNKNOWN];
2225 + return soc_type_strings[ath25_soc];
2226 +}
2227 +
2228 +void __init ath25_serial_setup(u32 mapbase, int irq, unsigned int uartclk)
2229 +{
2230 + struct uart_port s;
2231 +
2232 + memset(&s, 0, sizeof(s));
2233 +
2234 + s.flags = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST | UPF_IOREMAP;
2235 + s.iotype = UPIO_MEM32;
2236 + s.irq = irq;
2237 + s.regshift = 2;
2238 + s.mapbase = mapbase;
2239 + s.uartclk = uartclk;
2240 +
2241 + early_serial_setup(&s);
2242 +}
2243 +
2244 +int __init ath25_add_wmac(int nr, u32 base, int irq)
2245 +{
2246 + struct resource *res;
2247 +
2248 + ath25_wmac[nr].dev.platform_data = &ath25_board;
2249 + res = &ath25_wmac[nr].resource[0];
2250 + res->start = base;
2251 + res->end = base + 0x10000 - 1;
2252 + res++;
2253 + res->start = irq;
2254 + res->end = irq;
2255 + return platform_device_register(&ath25_wmac[nr]);
2256 +}
2257 +
2258 +static int __init ath25_register_devices(void)
2259 +{
2260 + if (is_ar5312())
2261 + ar5312_init_devices();
2262 + else
2263 + ar2315_init_devices();
2264 +
2265 + return 0;
2266 +}
2267 +
2268 +device_initcall(ath25_register_devices);
2269 +
2270 +static int __init ath25_arch_init(void)
2271 +{
2272 + if (is_ar5312())
2273 + ar5312_arch_init();
2274 + else
2275 + ar2315_arch_init();
2276 +
2277 + return 0;
2278 +}
2279 +
2280 +arch_initcall(ath25_arch_init);
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