target/linux/atheros/patches-3.18/105-ar2315_pci.patch

   1 --- a/arch/mips/pci/Makefile
   2 +++ b/arch/mips/pci/Makefile
   3 @@ -19,6 +19,7 @@ obj-$(CONFIG_BCM47XX)         += pci-bcm47xx.o
   4  obj-$(CONFIG_BCM63XX)          += pci-bcm63xx.o fixup-bcm63xx.o \
   5                                         ops-bcm63xx.o
   6  obj-$(CONFIG_MIPS_ALCHEMY)     += pci-alchemy.o
   7 +obj-$(CONFIG_PCI_AR2315)       += pci-ar2315.o
   8  obj-$(CONFIG_SOC_AR71XX)       += pci-ar71xx.o
   9  obj-$(CONFIG_PCI_AR724X)       += pci-ar724x.o
  10  obj-$(CONFIG_MIPS_PCI_VIRTIO)  += pci-virtio-guest.o
  11 --- /dev/null
  12 +++ b/arch/mips/pci/pci-ar2315.c
  13 @@ -0,0 +1,447 @@
  14 +/*
  15 + * This program is free software; you can redistribute it and/or
  16 + * modify it under the terms of the GNU General Public License
  17 + * as published by the Free Software Foundation; either version 2
  18 + * of the License, or (at your option) any later version.
  19 + *
  20 + * This program is distributed in the hope that it will be useful,
  21 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  22 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  23 + * GNU General Public License for more details.
  24 + *
  25 + * You should have received a copy of the GNU General Public License
  26 + * along with this program; if not, see <http://www.gnu.org/licenses/>.
  27 + */
  28 +
  29 +/**
  30 + * Both AR2315 and AR2316 chips have PCI interface unit, which supports DMA
  31 + * and interrupt. PCI interface supports MMIO access method, but does not
  32 + * seem to support I/O ports.
  33 + *
  34 + * Read/write operation in the region 0x80000000-0xBFFFFFFF causes
  35 + * a memory read/write command on the PCI bus. 30 LSBs of address on
  36 + * the bus are taken from memory read/write request and 2 MSBs are
  37 + * determined by PCI unit configuration.
  38 + *
  39 + * To work with the configuration space instead of memory is necessary set
  40 + * the CFG_SEL bit in the PCI_MISC_CONFIG register.
  41 + *
  42 + * Devices on the bus can perform DMA requests via chip BAR1. PCI host
  43 + * controller BARs are programmend as if an external device is programmed.
  44 + * Which means that during configuration, IDSEL pin of the chip should be
  45 + * asserted.
  46 + *
  47 + * We know (and support) only one board that uses the PCI interface -
  48 + * Fonera 2.0g (FON2202). It has a USB EHCI controller connected to the
  49 + * AR2315 PCI bus. IDSEL pin of USB controller is connected to AD[13] line
  50 + * and IDSEL pin of AR125 is connected to AD[16] line.
  51 + */
  52 +
  53 +#include <linux/types.h>
  54 +#include <linux/pci.h>
  55 +#include <linux/platform_device.h>
  56 +#include <linux/kernel.h>
  57 +#include <linux/init.h>
  58 +#include <linux/mm.h>
  59 +#include <linux/delay.h>
  60 +#include <linux/irq.h>
  61 +#include <linux/io.h>
  62 +#include <asm/paccess.h>
  63 +#include <ath25_platform.h>
  64 +#include <ar231x.h>
  65 +#include <ar2315_regs.h>
  66 +
  67 +/*
  68 + * PCI Bus Interface Registers
  69 + */
  70 +#define AR2315_PCI_1MS_REG             (AR2315_PCI + 0x0008)
  71 +
  72 +#define AR2315_PCI_1MS_MASK            0x3FFFF /* # of AHB clk cycles in 1ms */
  73 +
  74 +#define AR2315_PCI_MISC_CONFIG         (AR2315_PCI + 0x000c)
  75 +
  76 +#define AR2315_PCIMISC_TXD_EN  0x00000001      /* Enable TXD for fragments */
  77 +#define AR2315_PCIMISC_CFG_SEL 0x00000002      /* Mem or Config cycles */
  78 +#define AR2315_PCIMISC_GIG_MASK        0x0000000C      /* bits 31-30 for pci req */
  79 +#define AR2315_PCIMISC_RST_MODE        0x00000030
  80 +#define AR2315_PCIRST_INPUT    0x00000000      /* 4:5=0 rst is input */
  81 +#define AR2315_PCIRST_LOW      0x00000010      /* 4:5=1 rst to GND */
  82 +#define AR2315_PCIRST_HIGH     0x00000020      /* 4:5=2 rst to VDD */
  83 +#define AR2315_PCIGRANT_EN     0x00000000      /* 6:7=0 early grant en */
  84 +#define AR2315_PCIGRANT_FRAME  0x00000040      /* 6:7=1 grant waits 4 frame */
  85 +#define AR2315_PCIGRANT_IDLE   0x00000080      /* 6:7=2 grant waits 4 idle */
  86 +#define AR2315_PCIGRANT_GAP    0x00000000      /* 6:7=2 grant waits 4 idle */
  87 +#define AR2315_PCICACHE_DIS    0x00001000      /* PCI external access cache
  88 +                                                * disable */
  89 +
  90 +#define AR2315_PCI_OUT_TSTAMP          (AR2315_PCI + 0x0010)
  91 +
  92 +#define AR2315_PCI_UNCACHE_CFG         (AR2315_PCI + 0x0014)
  93 +
  94 +#define AR2315_PCI_IN_EN               (AR2315_PCI + 0x0100)
  95 +
  96 +#define AR2315_PCI_IN_EN0      0x01    /* Enable chain 0 */
  97 +#define AR2315_PCI_IN_EN1      0x02    /* Enable chain 1 */
  98 +#define AR2315_PCI_IN_EN2      0x04    /* Enable chain 2 */
  99 +#define AR2315_PCI_IN_EN3      0x08    /* Enable chain 3 */
 100 +
 101 +#define AR2315_PCI_IN_DIS              (AR2315_PCI + 0x0104)
 102 +
 103 +#define AR2315_PCI_IN_DIS0     0x01    /* Disable chain 0 */
 104 +#define AR2315_PCI_IN_DIS1     0x02    /* Disable chain 1 */
 105 +#define AR2315_PCI_IN_DIS2     0x04    /* Disable chain 2 */
 106 +#define AR2315_PCI_IN_DIS3     0x08    /* Disable chain 3 */
 107 +
 108 +#define AR2315_PCI_IN_PTR              (AR2315_PCI + 0x0200)
 109 +
 110 +#define AR2315_PCI_OUT_EN              (AR2315_PCI + 0x0400)
 111 +
 112 +#define AR2315_PCI_OUT_EN0     0x01    /* Enable chain 0 */
 113 +
 114 +#define AR2315_PCI_OUT_DIS             (AR2315_PCI + 0x0404)
 115 +
 116 +#define AR2315_PCI_OUT_DIS0    0x01    /* Disable chain 0 */
 117 +
 118 +#define AR2315_PCI_OUT_PTR             (AR2315_PCI + 0x0408)
 119 +
 120 +/* PCI interrupt status (write one to clear) */
 121 +#define AR2315_PCI_ISR                 (AR2315_PCI + 0x0500)
 122 +
 123 +#define AR2315_PCI_INT_TX      0x00000001      /* Desc In Completed */
 124 +#define AR2315_PCI_INT_TXOK    0x00000002      /* Desc In OK */
 125 +#define AR2315_PCI_INT_TXERR   0x00000004      /* Desc In ERR */
 126 +#define AR2315_PCI_INT_TXEOL   0x00000008      /* Desc In End-of-List */
 127 +#define AR2315_PCI_INT_RX      0x00000010      /* Desc Out Completed */
 128 +#define AR2315_PCI_INT_RXOK    0x00000020      /* Desc Out OK */
 129 +#define AR2315_PCI_INT_RXERR   0x00000040      /* Desc Out ERR */
 130 +#define AR2315_PCI_INT_RXEOL   0x00000080      /* Desc Out EOL */
 131 +#define AR2315_PCI_INT_TXOOD   0x00000200      /* Desc In Out-of-Desc */
 132 +#define AR2315_PCI_INT_DESCMASK        0x0000FFFF      /* Desc Mask */
 133 +#define AR2315_PCI_INT_EXT     0x02000000      /* Extern PCI INTA */
 134 +#define AR2315_PCI_INT_ABORT   0x04000000      /* PCI bus abort event */
 135 +
 136 +/* PCI interrupt mask */
 137 +#define AR2315_PCI_IMR                 (AR2315_PCI + 0x0504)
 138 +
 139 +/* Global PCI interrupt enable */
 140 +#define AR2315_PCI_IER                 (AR2315_PCI + 0x0508)
 141 +
 142 +#define AR2315_PCI_IER_DISABLE         0x00    /* disable pci interrupts */
 143 +#define AR2315_PCI_IER_ENABLE          0x01    /* enable pci interrupts */
 144 +
 145 +#define AR2315_PCI_HOST_IN_EN          (AR2315_PCI + 0x0800)
 146 +#define AR2315_PCI_HOST_IN_DIS         (AR2315_PCI + 0x0804)
 147 +#define AR2315_PCI_HOST_IN_PTR         (AR2315_PCI + 0x0810)
 148 +#define AR2315_PCI_HOST_OUT_EN         (AR2315_PCI + 0x0900)
 149 +#define AR2315_PCI_HOST_OUT_DIS                (AR2315_PCI + 0x0904)
 150 +#define AR2315_PCI_HOST_OUT_PTR                (AR2315_PCI + 0x0908)
 151 +
 152 +/*
 153 + * PCI interrupts, which share IP5
 154 + * Keep ordered according to AR2315_PCI_INT_XXX bits
 155 + */
 156 +#define AR2315_PCI_IRQ_BASE            0x50
 157 +#define AR2315_PCI_IRQ_EXT             (AR2315_PCI_IRQ_BASE+0)
 158 +#define AR2315_PCI_IRQ_ABORT           (AR2315_PCI_IRQ_BASE+1)
 159 +#define AR2315_PCI_IRQ_COUNT           2
 160 +#define AR2315_PCI_IRQ_SHIFT           25      /* in AR2315_PCI_INT_STATUS */
 161 +
 162 +/* Arbitrary size of memory region to access the configuration space */
 163 +#define AR2315_PCI_CFG_SIZE    0x00100000
 164 +
 165 +#define AR2315_PCI_HOST_SLOT   3
 166 +#define AR2315_PCI_HOST_DEVID  ((0xff18 << 16) | PCI_VENDOR_ID_ATHEROS)
 167 +
 168 +/* ??? access BAR */
 169 +#define AR2315_PCI_HOST_MBAR0          0x10000000
 170 +/* RAM access BAR */
 171 +#define AR2315_PCI_HOST_MBAR1          AR2315_PCI_HOST_SDRAM_BASEADDR
 172 +/* ??? access BAR */
 173 +#define AR2315_PCI_HOST_MBAR2          0x30000000
 174 +
 175 +static void __iomem *ar2315_pci_cfg_mem;
 176 +
 177 +static int ar2315_pci_cfg_access(int devfn, int where, int size, u32 *ptr,
 178 +                                bool write)
 179 +{
 180 +       int func = PCI_FUNC(devfn);
 181 +       int dev = PCI_SLOT(devfn);
 182 +       u32 addr = (1 << (13 + dev)) | (func << 8) | (where & ~3);
 183 +       u32 mask = 0xffffffff >> 8 * (4 - size);
 184 +       u32 sh = (where & 3) * 8;
 185 +       u32 value, isr;
 186 +
 187 +       /* Prevent access past the remapped area */
 188 +       if (addr >= AR2315_PCI_CFG_SIZE || dev > 18)
 189 +               return PCIBIOS_DEVICE_NOT_FOUND;
 190 +
 191 +       /* Clear pending errors */
 192 +       ar231x_write_reg(AR2315_PCI_ISR, AR2315_PCI_INT_ABORT);
 193 +       /* Select Configuration access */
 194 +       ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, 0, AR2315_PCIMISC_CFG_SEL);
 195 +
 196 +       mb();   /* PCI must see space change before we begin */
 197 +
 198 +       value = __raw_readl(ar2315_pci_cfg_mem + addr);
 199 +
 200 +       isr = ar231x_read_reg(AR2315_PCI_ISR);
 201 +       if (isr & AR2315_PCI_INT_ABORT)
 202 +               goto exit_err;
 203 +
 204 +       if (write) {
 205 +               value = (value & ~(mask << sh)) | *ptr << sh;
 206 +               __raw_writel(value, ar2315_pci_cfg_mem + addr);
 207 +               isr = ar231x_read_reg(AR2315_PCI_ISR);
 208 +               if (isr & AR2315_PCI_INT_ABORT)
 209 +                       goto exit_err;
 210 +       } else {
 211 +               *ptr = (value >> sh) & mask;
 212 +       }
 213 +
 214 +       goto exit;
 215 +
 216 +exit_err:
 217 +       ar231x_write_reg(AR2315_PCI_ISR, AR2315_PCI_INT_ABORT);
 218 +       if (!write)
 219 +               *ptr = 0xffffffff;
 220 +
 221 +exit:
 222 +       /* Select Memory access */
 223 +       ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_CFG_SEL, 0);
 224 +
 225 +       return isr & AR2315_PCI_INT_ABORT ? PCIBIOS_DEVICE_NOT_FOUND :
 226 +                                           PCIBIOS_SUCCESSFUL;
 227 +}
 228 +
 229 +static inline int ar2315_pci_local_cfg_rd(unsigned devfn, int where, u32 *val)
 230 +{
 231 +       return ar2315_pci_cfg_access(devfn, where, sizeof(u32), val, false);
 232 +}
 233 +
 234 +static inline int ar2315_pci_local_cfg_wr(unsigned devfn, int where, u32 val)
 235 +{
 236 +       return ar2315_pci_cfg_access(devfn, where, sizeof(u32), &val, true);
 237 +}
 238 +
 239 +static int ar2315_pci_cfg_read(struct pci_bus *bus, unsigned int devfn,
 240 +                              int where, int size, u32 *value)
 241 +{
 242 +       if (PCI_SLOT(devfn) == AR2315_PCI_HOST_SLOT)
 243 +               return PCIBIOS_DEVICE_NOT_FOUND;
 244 +
 245 +       return ar2315_pci_cfg_access(devfn, where, size, value, 0);
 246 +}
 247 +
 248 +static int ar2315_pci_cfg_write(struct pci_bus *bus, unsigned int devfn,
 249 +                               int where, int size, u32 value)
 250 +{
 251 +       if (PCI_SLOT(devfn) == AR2315_PCI_HOST_SLOT)
 252 +               return PCIBIOS_DEVICE_NOT_FOUND;
 253 +
 254 +       return ar2315_pci_cfg_access(devfn, where, size, &value, 1);
 255 +}
 256 +
 257 +static struct pci_ops ar2315_pci_ops = {
 258 +       .read   = ar2315_pci_cfg_read,
 259 +       .write  = ar2315_pci_cfg_write,
 260 +};
 261 +
 262 +static struct resource ar2315_mem_resource = {
 263 +       .name   = "ar2315-pci-mem",
 264 +       .start  = AR2315_PCIEXT,
 265 +       .end    = AR2315_PCIEXT + AR2315_PCIEXT_SZ - 1,
 266 +       .flags  = IORESOURCE_MEM,
 267 +};
 268 +
 269 +/* PCI controller does not support I/O ports */
 270 +static struct resource ar2315_io_resource = {
 271 +       .name   = "ar2315-pci-io",
 272 +       .start  = 0,
 273 +       .end    = 0,
 274 +       .flags  = IORESOURCE_IO,
 275 +};
 276 +
 277 +static struct pci_controller ar2315_pci_controller = {
 278 +       .pci_ops        = &ar2315_pci_ops,
 279 +       .mem_resource   = &ar2315_mem_resource,
 280 +       .io_resource    = &ar2315_io_resource,
 281 +       .mem_offset     = 0x00000000UL,
 282 +       .io_offset      = 0x00000000UL,
 283 +};
 284 +
 285 +static int ar2315_pci_host_setup(void)
 286 +{
 287 +       unsigned devfn = PCI_DEVFN(AR2315_PCI_HOST_SLOT, 0);
 288 +       int res;
 289 +       u32 id;
 290 +
 291 +       res = ar2315_pci_local_cfg_rd(devfn, PCI_VENDOR_ID, &id);
 292 +       if (res != PCIBIOS_SUCCESSFUL || id != AR2315_PCI_HOST_DEVID)
 293 +               return -ENODEV;
 294 +
 295 +       /* Program MBARs */
 296 +       ar2315_pci_local_cfg_wr(devfn, PCI_BASE_ADDRESS_0,
 297 +                               AR2315_PCI_HOST_MBAR0);
 298 +       ar2315_pci_local_cfg_wr(devfn, PCI_BASE_ADDRESS_1,
 299 +                               AR2315_PCI_HOST_MBAR1);
 300 +       ar2315_pci_local_cfg_wr(devfn, PCI_BASE_ADDRESS_2,
 301 +                               AR2315_PCI_HOST_MBAR2);
 302 +
 303 +       /* Run */
 304 +       ar2315_pci_local_cfg_wr(devfn, PCI_COMMAND, PCI_COMMAND_MEMORY |
 305 +                               PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL |
 306 +                               PCI_COMMAND_INVALIDATE | PCI_COMMAND_PARITY |
 307 +                               PCI_COMMAND_SERR | PCI_COMMAND_FAST_BACK);
 308 +
 309 +       return 0;
 310 +}
 311 +
 312 +static void ar2315_pci_irq_handler(unsigned irq, struct irq_desc *desc)
 313 +{
 314 +       u32 pending = ar231x_read_reg(AR2315_PCI_ISR) &
 315 +                     ar231x_read_reg(AR2315_PCI_IMR);
 316 +
 317 +       if (pending & AR2315_PCI_INT_EXT)
 318 +               generic_handle_irq(AR2315_PCI_IRQ_EXT);
 319 +       else if (pending & AR2315_PCI_INT_ABORT)
 320 +               generic_handle_irq(AR2315_PCI_IRQ_ABORT);
 321 +       else
 322 +               spurious_interrupt();
 323 +}
 324 +
 325 +static void ar2315_pci_irq_mask(struct irq_data *d)
 326 +{
 327 +       u32 m = 1 << (d->irq - AR2315_PCI_IRQ_BASE + AR2315_PCI_IRQ_SHIFT);
 328 +
 329 +       ar231x_mask_reg(AR2315_PCI_IMR, m, 0);
 330 +}
 331 +
 332 +static void ar2315_pci_irq_mask_ack(struct irq_data *d)
 333 +{
 334 +       u32 m = 1 << (d->irq - AR2315_PCI_IRQ_BASE + AR2315_PCI_IRQ_SHIFT);
 335 +
 336 +       ar231x_mask_reg(AR2315_PCI_IMR, m, 0);
 337 +       ar231x_write_reg(AR2315_PCI_ISR, m);
 338 +}
 339 +
 340 +static void ar2315_pci_irq_unmask(struct irq_data *d)
 341 +{
 342 +       u32 m = 1 << (d->irq - AR2315_PCI_IRQ_BASE + AR2315_PCI_IRQ_SHIFT);
 343 +
 344 +       ar231x_mask_reg(AR2315_PCI_IMR, 0, m);
 345 +}
 346 +
 347 +static struct irq_chip ar2315_pci_irq_chip = {
 348 +       .name = "AR2315-PCI",
 349 +       .irq_mask = ar2315_pci_irq_mask,
 350 +       .irq_mask_ack = ar2315_pci_irq_mask_ack,
 351 +       .irq_unmask = ar2315_pci_irq_unmask,
 352 +};
 353 +
 354 +static void ar2315_pci_irq_init(void)
 355 +{
 356 +       int i;
 357 +
 358 +       ar231x_mask_reg(AR2315_PCI_IER, AR2315_PCI_IER_ENABLE, 0);
 359 +       ar231x_mask_reg(AR2315_PCI_IMR, (AR2315_PCI_INT_ABORT |
 360 +                        AR2315_PCI_INT_EXT), 0);
 361 +
 362 +       for (i = 0; i < AR2315_PCI_IRQ_COUNT; ++i) {
 363 +               int irq = AR2315_PCI_IRQ_BASE + i;
 364 +
 365 +               irq_set_chip_and_handler(irq, &ar2315_pci_irq_chip,
 366 +                                        handle_level_irq);
 367 +       }
 368 +
 369 +       irq_set_chained_handler(AR2315_IRQ_LCBUS_PCI, ar2315_pci_irq_handler);
 370 +
 371 +       /* Clear any pending Abort or external Interrupts
 372 +        * and enable interrupt processing */
 373 +       ar231x_write_reg(AR2315_PCI_ISR, (AR2315_PCI_INT_ABORT |
 374 +                        AR2315_PCI_INT_EXT));
 375 +       ar231x_mask_reg(AR2315_PCI_IER, 0, AR2315_PCI_IER_ENABLE);
 376 +}
 377 +
 378 +static int ar2315_pci_probe(struct platform_device *pdev)
 379 +{
 380 +       struct device *dev = &pdev->dev;
 381 +       u32 reg;
 382 +       int res;
 383 +
 384 +       /* Remap PCI config space */
 385 +       ar2315_pci_cfg_mem = devm_ioremap_nocache(dev, AR2315_PCIEXT,
 386 +                                                 AR2315_PCI_CFG_SIZE);
 387 +       if (!ar2315_pci_cfg_mem) {
 388 +               dev_err(dev, "failed to remap PCI config space\n");
 389 +               return -ENOMEM;
 390 +       }
 391 +
 392 +       /* Reset PCI DMA logic */
 393 +       reg = ar231x_mask_reg(AR2315_RESET, 0, AR2315_RESET_PCIDMA);
 394 +       msleep(20);
 395 +       reg &= ~AR2315_RESET_PCIDMA;
 396 +       ar231x_write_reg(AR2315_RESET, reg);
 397 +       msleep(20);
 398 +
 399 +       ar231x_mask_reg(AR2315_ENDIAN_CTL, 0,
 400 +                       AR2315_CONFIG_PCIAHB | AR2315_CONFIG_PCIAHB_BRIDGE);
 401 +
 402 +       ar231x_write_reg(AR2315_PCICLK, AR2315_PCICLK_PLLC_CLKM |
 403 +                        (AR2315_PCICLK_IN_FREQ_DIV_6 << AR2315_PCICLK_DIV_S));
 404 +       ar231x_mask_reg(AR2315_AHB_ARB_CTL, 0, AR2315_ARB_PCI);
 405 +       ar231x_mask_reg(AR2315_IF_CTL, AR2315_IF_PCI_CLK_MASK | AR2315_IF_MASK,
 406 +                       AR2315_IF_PCI | AR2315_IF_PCI_HOST |
 407 +                       AR2315_IF_PCI_INTR | (AR2315_IF_PCI_CLK_OUTPUT_CLK <<
 408 +                                             AR2315_IF_PCI_CLK_SHIFT));
 409 +
 410 +       /* Reset the PCI bus by setting bits 5-4 in PCI_MCFG */
 411 +       ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_RST_MODE,
 412 +                       AR2315_PCIRST_LOW);
 413 +       msleep(100);
 414 +
 415 +       /* Bring the PCI out of reset */
 416 +       ar231x_mask_reg(AR2315_PCI_MISC_CONFIG, AR2315_PCIMISC_RST_MODE,
 417 +                       AR2315_PCIRST_HIGH | AR2315_PCICACHE_DIS | 0x8);
 418 +
 419 +       ar231x_write_reg(AR2315_PCI_UNCACHE_CFG,
 420 +                        0x1E | /* 1GB uncached */
 421 +                        (1 << 5) | /* Enable uncached */
 422 +                        (0x2 << 30) /* Base: 0x80000000 */);
 423 +       ar231x_read_reg(AR2315_PCI_UNCACHE_CFG);
 424 +
 425 +       msleep(500);
 426 +
 427 +       res = ar2315_pci_host_setup();
 428 +       if (res)
 429 +               return res;
 430 +
 431 +       ar2315_pci_irq_init();
 432 +
 433 +       register_pci_controller(&ar2315_pci_controller);
 434 +
 435 +       return 0;
 436 +}
 437 +
 438 +static struct platform_driver ar2315_pci_driver = {
 439 +       .probe = ar2315_pci_probe,
 440 +       .driver = {
 441 +               .name = "ar2315-pci",
 442 +               .owner = THIS_MODULE,
 443 +       },
 444 +};
 445 +
 446 +static int __init ar2315_pci_init(void)
 447 +{
 448 +       return platform_driver_register(&ar2315_pci_driver);
 449 +}
 450 +arch_initcall(ar2315_pci_init);
 451 +
 452 +int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
 453 +{
 454 +       return AR2315_PCI_IRQ_EXT;
 455 +}
 456 +
 457 +int pcibios_plat_dev_init(struct pci_dev *dev)
 458 +{
 459 +       return 0;
 460 +}
 461 --- a/arch/mips/ath25/Kconfig
 462 +++ b/arch/mips/ath25/Kconfig
 463 @@ -9,3 +9,10 @@ config SOC_AR2315
 464         depends on ATH25
 465         select GPIO_AR2315
 466         default y
 467 +
 468 +config PCI_AR2315
 469 +       bool "AR2315 PCI controller support"
 470 +       depends on SOC_AR2315
 471 +       select HW_HAS_PCI
 472 +       select PCI
 473 +       default y
 474 --- a/arch/mips/ath25/ar2315.c
 475 +++ b/arch/mips/ath25/ar2315.c
 476 @@ -116,6 +116,10 @@ static void ar2315_irq_dispatch(void)
 477                 do_IRQ(AR2315_IRQ_WLAN0_INTRS);
 478         else if (pending & CAUSEF_IP4)
 479                 do_IRQ(AR2315_IRQ_ENET0_INTRS);
 480 +#ifdef CONFIG_PCI_AR2315
 481 +       else if (pending & CAUSEF_IP5)
 482 +               do_IRQ(AR2315_IRQ_LCBUS_PCI);
 483 +#endif
 484         else if (pending & CAUSEF_IP2)
 485                 do_IRQ(AR2315_IRQ_MISC_INTRS);
 486         else if (pending & CAUSEF_IP7)
 487 @@ -427,4 +431,10 @@ void __init ar2315_arch_init(void)
 488  {
 489         ath25_serial_setup(AR2315_UART0, AR2315_MISC_IRQ_UART0,
 490                            ar2315_apb_frequency());
 491 +
 492 +#ifdef CONFIG_PCI_AR2315
 493 +       if (ath25_soc == ATH25_SOC_AR2315) {
 494 +               platform_device_register_simple("ar2315-pci", -1, NULL, 0);
 495 +       }
 496 +#endif
 497  }