2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 2003 Atheros Communications, Inc., All Rights Reserved.
7 * Copyright (C) 2006 FON Technology, SL.
8 * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
9 * Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
13 * Platform devices for Atheros SoCs
16 #include <linux/autoconf.h>
17 #include <linux/init.h>
18 #include <linux/module.h>
19 #include <linux/types.h>
20 #include <linux/string.h>
21 #include <linux/mtd/physmap.h>
22 #include <linux/platform_device.h>
23 #include <linux/kernel.h>
24 #include <linux/reboot.h>
25 #include <asm/bootinfo.h>
26 #include <asm/reboot.h>
34 static int is_5312
= 0;
35 static struct platform_device
*ar5312_devs
[5];
37 static struct resource ar5312_eth0_res
[] = {
39 .name
= "eth0_membase",
40 .flags
= IORESOURCE_MEM
,
41 .start
= KSEG1ADDR(AR531X_ENET0
),
42 .end
= KSEG1ADDR(AR531X_ENET0
+ 0x2000),
46 .flags
= IORESOURCE_IRQ
,
47 .start
= AR5312_IRQ_ENET0_INTRS
,
48 .end
= AR5312_IRQ_ENET0_INTRS
,
51 static struct ar531x_eth ar5312_eth0_data
= {
54 .reset_base
= AR531X_RESET
,
55 .reset_mac
= AR531X_RESET_ENET0
,
56 .reset_phy
= AR531X_RESET_EPHY0
,
57 .phy_base
= KSEG1ADDR(AR531X_ENET0
),
60 static struct resource ar5312_eth1_res
[] = {
62 .name
= "eth1_membase",
63 .flags
= IORESOURCE_MEM
,
64 .start
= KSEG1ADDR(AR531X_ENET1
),
65 .end
= KSEG1ADDR(AR531X_ENET1
+ 0x2000),
69 .flags
= IORESOURCE_IRQ
,
70 .start
= AR5312_IRQ_ENET1_INTRS
,
71 .end
= AR5312_IRQ_ENET1_INTRS
,
74 static struct ar531x_eth ar5312_eth1_data
= {
77 .reset_base
= AR531X_RESET
,
78 .reset_mac
= AR531X_RESET_ENET1
,
79 .reset_phy
= AR531X_RESET_EPHY1
,
80 .phy_base
= KSEG1ADDR(AR531X_ENET1
),
83 static struct platform_device ar5312_eth
[] = {
87 .dev
.platform_data
= &ar5312_eth0_data
,
88 .resource
= ar5312_eth0_res
,
89 .num_resources
= ARRAY_SIZE(ar5312_eth0_res
)
94 .dev
.platform_data
= &ar5312_eth1_data
,
95 .resource
= ar5312_eth1_res
,
96 .num_resources
= ARRAY_SIZE(ar5312_eth1_res
)
102 * AR2312/3 ethernet uses the PHY of ENET0, but the MAC
103 * of ENET1. Atheros calls it 'twisted' for a reason :)
105 static struct resource ar231x_eth0_res
[] = {
107 .name
= "eth0_membase",
108 .flags
= IORESOURCE_MEM
,
109 .start
= KSEG1ADDR(AR531X_ENET1
),
110 .end
= KSEG1ADDR(AR531X_ENET1
+ 0x2000),
114 .flags
= IORESOURCE_IRQ
,
115 .start
= AR5312_IRQ_ENET1_INTRS
,
116 .end
= AR5312_IRQ_ENET1_INTRS
,
119 static struct ar531x_eth ar231x_eth0_data
= {
122 .reset_base
= AR531X_RESET
,
123 .reset_mac
= AR531X_RESET_ENET1
,
124 .reset_phy
= AR531X_RESET_EPHY1
,
125 .phy_base
= KSEG1ADDR(AR531X_ENET0
),
127 static struct platform_device ar231x_eth0
= {
129 .name
= "ar531x-eth",
130 .dev
.platform_data
= &ar231x_eth0_data
,
131 .resource
= ar231x_eth0_res
,
132 .num_resources
= ARRAY_SIZE(ar231x_eth0_res
)
136 static struct platform_device ar5312_wmac
[] = {
139 .name
= "ar531x-wmac",
143 .name
= "ar531x-wmac",
147 static struct physmap_flash_data ar5312_flash_data
= {
151 static struct resource ar5312_flash_resource
= {
152 .start
= AR531X_FLASH
,
153 .end
= AR531X_FLASH
+ 0x400000 - 1,
154 .flags
= IORESOURCE_MEM
,
157 static struct platform_device ar5312_physmap_flash
= {
158 .name
= "physmap-flash",
161 .platform_data
= &ar5312_flash_data
,
164 .resource
= &ar5312_flash_resource
,
169 * NB: This mapping size is larger than the actual flash size,
170 * but this shouldn't be a problem here, because the flash
171 * will simply be mapped multiple times.
173 static char __init
*ar5312_flash_limit(void)
177 * Configure flash bank 0.
178 * Assume 8M window size. Flash will be aliased if it's smaller
183 (0x01 << FLASHCTL_IDCY_S
) |
184 (0x07 << FLASHCTL_WST1_S
) |
185 (0x07 << FLASHCTL_WST2_S
) |
186 (sysRegRead(AR531X_FLASHCTL0
) & FLASHCTL_MW
);
188 sysRegWrite(AR531X_FLASHCTL0
, ctl
);
190 /* Disable other flash banks */
191 sysRegWrite(AR531X_FLASHCTL1
,
192 sysRegRead(AR531X_FLASHCTL1
) & ~(FLASHCTL_E
| FLASHCTL_AC
));
194 sysRegWrite(AR531X_FLASHCTL2
,
195 sysRegRead(AR531X_FLASHCTL2
) & ~(FLASHCTL_E
| FLASHCTL_AC
));
197 return (char *) KSEG1ADDR(AR531X_FLASH
+ 0x800000);
200 static struct ar531x_config __init
*init_wmac(int unit
)
202 struct ar531x_config
*config
;
204 config
= (struct ar531x_config
*) kzalloc(sizeof(struct ar531x_config
), GFP_KERNEL
);
205 config
->board
= board_config
;
206 config
->radio
= radio_config
;
208 config
->tag
= (u_int16_t
) ((sysRegRead(AR531X_REV
) >> AR531X_REV_WMAC_MIN_S
) & AR531X_REV_CHIP
);
213 int __init
ar5312_init_devices(void)
215 struct ar531x_boarddata
*bcfg
;
222 /* Locate board/radio config data */
223 ar531x_find_config(ar5312_flash_limit());
224 bcfg
= (struct ar531x_boarddata
*) board_config
;
228 * Chip IDs and hardware detection for some Atheros
229 * models are really broken!
231 * Atheros uses a disabled WMAC0 and Silicon ID of AR5312
232 * as indication for AR2312, which is otherwise
233 * indistinguishable from the real AR5312.
236 radio
= radio_config
+ AR531X_RADIO_MASK_OFF
;
237 if ((*((u32
*) radio
) & AR531X_RADIO0_MASK
) == 0)
238 bcfg
->config
|= BD_ISCASPER
;
242 /* AR2313 has CPU minor rev. 10 */
243 if ((current_cpu_data
.processor_id
& 0xff) == 0x0a)
244 mips_machtype
= MACH_ATHEROS_AR2313
;
246 /* AR2312 shares the same Silicon ID as AR5312 */
247 else if (bcfg
->config
& BD_ISCASPER
)
248 mips_machtype
= MACH_ATHEROS_AR2312
;
250 /* Everything else is probably AR5312 or compatible */
252 mips_machtype
= MACH_ATHEROS_AR5312
;
254 ar5312_eth0_data
.board_config
= board_config
;
255 ar5312_eth1_data
.board_config
= board_config
;
256 ar5312_devs
[dev
++] = &ar5312_physmap_flash
;
258 if (!memcmp(bcfg
->enet0Mac
, "\xff\xff\xff\xff\xff\xff", 6))
259 memcpy(bcfg
->enet0Mac
, bcfg
->enet1Mac
, 6);
261 if (memcmp(bcfg
->enet0Mac
, bcfg
->enet1Mac
, 6) == 0) {
262 /* ENET0 and ENET1 have the same mac.
263 * Increment the one from ENET1 */
264 c
= bcfg
->enet1Mac
+ 5;
265 while ((c
>= (char *) bcfg
->enet1Mac
) && !(++(*c
)))
269 switch(mips_machtype
) {
270 case MACH_ATHEROS_AR5312
:
271 ar5312_eth0_data
.macaddr
= bcfg
->enet0Mac
;
272 ar5312_eth1_data
.macaddr
= bcfg
->enet1Mac
;
273 ar5312_devs
[dev
++] = &ar5312_eth
[0];
274 ar5312_devs
[dev
++] = &ar5312_eth
[1];
276 case MACH_ATHEROS_AR2312
:
277 case MACH_ATHEROS_AR2313
:
278 ar231x_eth0_data
.macaddr
= bcfg
->enet0Mac
;
279 ar5312_devs
[dev
++] = &ar231x_eth0
;
280 ar5312_flash_data
.width
= 1;
285 if (mips_machtype
== MACH_ATHEROS_AR5312
) {
286 if (*((u32
*) radio
) & AR531X_RADIO0_MASK
) {
287 ar5312_wmac
[0].dev
.platform_data
= init_wmac(0);
288 ar5312_devs
[dev
++] = &ar5312_wmac
[0];
291 if (*((u32
*) radio
) & AR531X_RADIO1_MASK
) {
292 ar5312_wmac
[1].dev
.platform_data
= init_wmac(1);
293 ar5312_devs
[dev
++] = &ar5312_wmac
[1];
297 return platform_add_devices(ar5312_devs
, dev
);
302 * Called when an interrupt is received, this function
303 * determines exactly which interrupt it was, and it
304 * invokes the appropriate handler.
306 * Implicitly, we also define interrupt priority by
307 * choosing which to dispatch first.
309 asmlinkage
void ar5312_irq_dispatch(void)
311 int pending
= read_c0_status() & read_c0_cause();
313 if (pending
& CAUSEF_IP2
)
314 do_IRQ(AR5312_IRQ_WLAN0_INTRS
);
315 else if (pending
& CAUSEF_IP3
)
316 do_IRQ(AR5312_IRQ_ENET0_INTRS
);
317 else if (pending
& CAUSEF_IP4
)
318 do_IRQ(AR5312_IRQ_ENET1_INTRS
);
319 else if (pending
& CAUSEF_IP5
)
320 do_IRQ(AR5312_IRQ_WLAN1_INTRS
);
321 else if (pending
& CAUSEF_IP6
) {
322 unsigned int ar531x_misc_intrs
= sysRegRead(AR531X_ISR
) & sysRegRead(AR531X_IMR
);
324 if (ar531x_misc_intrs
& AR531X_ISR_TIMER
) {
325 do_IRQ(AR531X_MISC_IRQ_TIMER
);
326 (void)sysRegRead(AR531X_TIMER
);
327 } else if (ar531x_misc_intrs
& AR531X_ISR_AHBPROC
)
328 do_IRQ(AR531X_MISC_IRQ_AHB_PROC
);
329 else if ((ar531x_misc_intrs
& AR531X_ISR_UART0
))
330 do_IRQ(AR531X_MISC_IRQ_UART0
);
331 else if (ar531x_misc_intrs
& AR531X_ISR_WD
)
332 do_IRQ(AR531X_MISC_IRQ_WATCHDOG
);
334 do_IRQ(AR531X_MISC_IRQ_NONE
);
335 } else if (pending
& CAUSEF_IP7
) {
336 do_IRQ(AR531X_IRQ_CPU_CLOCK
);
339 do_IRQ(AR531X_IRQ_NONE
);
342 static void ar5312_halt(void)
347 static void ar5312_power_off(void)
353 static void ar5312_restart(char *command
)
355 /* reset the system */
356 for(;;) sysRegWrite(AR531X_RESET
, AR531X_RESET_SYSTEM
);
361 * This table is indexed by bits 5..4 of the CLOCKCTL1 register
362 * to determine the predevisor value.
364 static int __initdata CLOCKCTL1_PREDIVIDE_TABLE
[4] = {
372 static unsigned int __init
ar5312_cpu_frequency(void)
375 unsigned int predivide_mask
, predivide_shift
;
376 unsigned int multiplier_mask
, multiplier_shift
;
377 unsigned int clockCtl1
, preDivideSelect
, preDivisor
, multiplier
;
378 unsigned int doubler_mask
;
379 unsigned int wisoc_revision
;
381 /* Trust the bootrom's idea of cpu frequency. */
382 if ((result
= sysRegRead(AR5312_SCRATCH
)))
385 wisoc_revision
= (sysRegRead(AR531X_REV
) & AR531X_REV_MAJ
) >> AR531X_REV_MAJ_S
;
386 if (wisoc_revision
== AR531X_REV_MAJ_AR2313
) {
387 predivide_mask
= AR2313_CLOCKCTL1_PREDIVIDE_MASK
;
388 predivide_shift
= AR2313_CLOCKCTL1_PREDIVIDE_SHIFT
;
389 multiplier_mask
= AR2313_CLOCKCTL1_MULTIPLIER_MASK
;
390 multiplier_shift
= AR2313_CLOCKCTL1_MULTIPLIER_SHIFT
;
391 doubler_mask
= AR2313_CLOCKCTL1_DOUBLER_MASK
;
392 } else { /* AR5312 and AR2312 */
393 predivide_mask
= AR5312_CLOCKCTL1_PREDIVIDE_MASK
;
394 predivide_shift
= AR5312_CLOCKCTL1_PREDIVIDE_SHIFT
;
395 multiplier_mask
= AR5312_CLOCKCTL1_MULTIPLIER_MASK
;
396 multiplier_shift
= AR5312_CLOCKCTL1_MULTIPLIER_SHIFT
;
397 doubler_mask
= AR5312_CLOCKCTL1_DOUBLER_MASK
;
401 * Clocking is derived from a fixed 40MHz input clock.
403 * cpuFreq = InputClock * MULT (where MULT is PLL multiplier)
404 * sysFreq = cpuFreq / 4 (used for APB clock, serial,
405 * flash, Timer, Watchdog Timer)
407 * cntFreq = cpuFreq / 2 (use for CPU count/compare)
409 * So, for example, with a PLL multiplier of 5, we have
415 * We compute the CPU frequency, based on PLL settings.
418 clockCtl1
= sysRegRead(AR5312_CLOCKCTL1
);
419 preDivideSelect
= (clockCtl1
& predivide_mask
) >> predivide_shift
;
420 preDivisor
= CLOCKCTL1_PREDIVIDE_TABLE
[preDivideSelect
];
421 multiplier
= (clockCtl1
& multiplier_mask
) >> multiplier_shift
;
423 if (clockCtl1
& doubler_mask
) {
424 multiplier
= multiplier
<< 1;
426 return (40000000 / preDivisor
) * multiplier
;
429 static inline int ar5312_sys_frequency(void)
431 return ar5312_cpu_frequency() / 4;
434 static void __init
ar5312_time_init(void)
436 mips_hpt_frequency
= ar5312_cpu_frequency() / 2;
440 /* Enable the specified AR531X_MISC_IRQ interrupt */
442 ar5312_misc_intr_enable(unsigned int irq
)
446 imr
= sysRegRead(AR531X_IMR
);
447 imr
|= (1 << (irq
- AR531X_MISC_IRQ_BASE
- 1));
448 sysRegWrite(AR531X_IMR
, imr
);
449 sysRegRead(AR531X_IMR
); /* flush write buffer */
452 /* Disable the specified AR531X_MISC_IRQ interrupt */
454 ar5312_misc_intr_disable(unsigned int irq
)
458 imr
= sysRegRead(AR531X_IMR
);
459 imr
&= ~(1 << (irq
- AR531X_MISC_IRQ_BASE
- 1));
460 sysRegWrite(AR531X_IMR
, imr
);
461 sysRegRead(AR531X_IMR
); /* flush write buffer */
464 /* Turn on the specified AR531X_MISC_IRQ interrupt */
466 ar5312_misc_intr_startup(unsigned int irq
)
468 ar5312_misc_intr_enable(irq
);
472 /* Turn off the specified AR531X_MISC_IRQ interrupt */
474 ar5312_misc_intr_shutdown(unsigned int irq
)
476 ar5312_misc_intr_disable(irq
);
480 ar5312_misc_intr_ack(unsigned int irq
)
482 ar5312_misc_intr_disable(irq
);
486 ar5312_misc_intr_end(unsigned int irq
)
488 if (!(irq_desc
[irq
].status
& (IRQ_DISABLED
| IRQ_INPROGRESS
)))
489 ar5312_misc_intr_enable(irq
);
492 static struct irq_chip ar5312_misc_intr_controller
= {
493 .typename
= "AR5312 misc",
494 .startup
= ar5312_misc_intr_startup
,
495 .shutdown
= ar5312_misc_intr_shutdown
,
496 .enable
= ar5312_misc_intr_enable
,
497 .disable
= ar5312_misc_intr_disable
,
498 .ack
= ar5312_misc_intr_ack
,
499 .end
= ar5312_misc_intr_end
,
502 static irqreturn_t
ar5312_ahb_proc_handler(int cpl
, void *dev_id
)
504 u32 proc1
= sysRegRead(AR531X_PROC1
);
505 u32 procAddr
= sysRegRead(AR531X_PROCADDR
); /* clears error state */
506 u32 dma1
= sysRegRead(AR531X_DMA1
);
507 u32 dmaAddr
= sysRegRead(AR531X_DMAADDR
); /* clears error state */
509 printk("AHB interrupt: PROCADDR=0x%8.8x PROC1=0x%8.8x DMAADDR=0x%8.8x DMA1=0x%8.8x\n",
510 procAddr
, proc1
, dmaAddr
, dma1
);
512 machine_restart("AHB error"); /* Catastrophic failure */
517 static struct irqaction ar5312_ahb_proc_interrupt
= {
518 .handler
= ar5312_ahb_proc_handler
,
519 .flags
= SA_INTERRUPT
,
520 .name
= "ar5312_ahb_proc_interrupt",
524 static struct irqaction cascade
= {
525 .handler
= no_action
,
526 .flags
= SA_INTERRUPT
,
530 void __init
ar5312_misc_intr_init(int irq_base
)
534 for (i
= irq_base
; i
< irq_base
+ AR531X_MISC_IRQ_COUNT
; i
++) {
535 irq_desc
[i
].status
= IRQ_DISABLED
;
536 irq_desc
[i
].action
= NULL
;
537 irq_desc
[i
].depth
= 1;
538 irq_desc
[i
].chip
= &ar5312_misc_intr_controller
;
540 setup_irq(AR531X_MISC_IRQ_AHB_PROC
, &ar5312_ahb_proc_interrupt
);
541 setup_irq(AR5312_IRQ_MISC_INTRS
, &cascade
);
544 void __init
ar5312_prom_init(void)
546 u32 memsize
, memcfg
, bank0AC
, bank1AC
;
550 /* Detect memory size */
551 memcfg
= sysRegRead(AR531X_MEM_CFG1
);
552 bank0AC
= (memcfg
& MEM_CFG1_AC0
) >> MEM_CFG1_AC0_S
;
553 bank1AC
= (memcfg
& MEM_CFG1_AC1
) >> MEM_CFG1_AC1_S
;
554 memsize
= (bank0AC
? (1 << (bank0AC
+1)) : 0)
555 + (bank1AC
? (1 << (bank1AC
+1)) : 0);
557 add_memory_region(0, memsize
, BOOT_MEM_RAM
);
559 /* Initialize it to AR5312 for now. Real detection will be done
560 * in ar5312_init_devices() */
561 mips_machtype
= MACH_ATHEROS_AR5312
;
564 void __init
ar5312_plat_setup(void)
566 /* Clear any lingering AHB errors */
567 sysRegRead(AR531X_PROCADDR
);
568 sysRegRead(AR531X_DMAADDR
);
569 sysRegWrite(AR531X_WD_CTRL
, AR531X_WD_CTRL_IGNORE_EXPIRATION
);
571 board_time_init
= ar5312_time_init
;
573 _machine_restart
= ar5312_restart
;
574 _machine_halt
= ar5312_halt
;
575 pm_power_off
= ar5312_power_off
;
577 serial_setup(KSEG1ADDR(AR531X_UART0
), ar5312_sys_frequency());
580 arch_initcall(ar5312_init_devices
);