projects / openwrt / staging / xback.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
bcm27xx: update 6.1 patches from RPi foundation
[openwrt/staging/xback.git] / target / linux / bcm27xx / patches-6.1 / 950-0885-drm-Add-RP1-DSI-driver.patch
1 From f93caa69a9af6476cd4d93944a83acd227e68fd4 Mon Sep 17 00:00:00 2001
2 From: Nick Hollinghurst <nick.hollinghurst@raspberrypi.com>
3 Date: Tue, 14 Feb 2023 14:58:33 +0000
4 Subject: [PATCH] drm: Add RP1 DSI driver
5
6 Add support for the RP1 DSI hardware.
7
8 Signed-off-by: Nick Hollinghurst <nick.hollinghurst@raspberrypi.com>
9 ---
10 drivers/gpu/drm/Kconfig | 2 +
11 drivers/gpu/drm/Makefile | 1 +
12 drivers/gpu/drm/rp1/Kconfig | 5 +
13 drivers/gpu/drm/rp1/Makefile | 4 +
14 drivers/gpu/drm/rp1/rp1-dsi/Kconfig | 15 +
15 drivers/gpu/drm/rp1/rp1-dsi/Makefile | 5 +
16 drivers/gpu/drm/rp1/rp1-dsi/rp1_dsi.c | 537 ++++++++
17 drivers/gpu/drm/rp1/rp1-dsi/rp1_dsi.h | 94 ++
18 drivers/gpu/drm/rp1/rp1-dsi/rp1_dsi_dma.c | 443 ++++++
19 drivers/gpu/drm/rp1/rp1-dsi/rp1_dsi_dsi.c | 1504 +++++++++++++++++++++
20 10 files changed, 2610 insertions(+)
21 create mode 100644 drivers/gpu/drm/rp1/Kconfig
22 create mode 100644 drivers/gpu/drm/rp1/Makefile
23 create mode 100644 drivers/gpu/drm/rp1/rp1-dsi/Kconfig
24 create mode 100644 drivers/gpu/drm/rp1/rp1-dsi/Makefile
25 create mode 100644 drivers/gpu/drm/rp1/rp1-dsi/rp1_dsi.c
26 create mode 100644 drivers/gpu/drm/rp1/rp1-dsi/rp1_dsi.h
27 create mode 100644 drivers/gpu/drm/rp1/rp1-dsi/rp1_dsi_dma.c
28 create mode 100644 drivers/gpu/drm/rp1/rp1-dsi/rp1_dsi_dsi.c
29
30 --- a/drivers/gpu/drm/Kconfig
31 +++ b/drivers/gpu/drm/Kconfig
32 @@ -384,6 +384,8 @@ source "drivers/gpu/drm/v3d/Kconfig"
33
34 source "drivers/gpu/drm/vc4/Kconfig"
35
36 +source "drivers/gpu/drm/rp1/Kconfig"
37 +
38 source "drivers/gpu/drm/etnaviv/Kconfig"
39
40 source "drivers/gpu/drm/hisilicon/Kconfig"
41 --- a/drivers/gpu/drm/Makefile
42 +++ b/drivers/gpu/drm/Makefile
43 @@ -148,3 +148,4 @@ obj-y += gud/
44 obj-$(CONFIG_DRM_HYPERV) += hyperv/
45 obj-y += solomon/
46 obj-$(CONFIG_DRM_SPRD) += sprd/
47 +obj-y += rp1/
48 --- /dev/null
49 +++ b/drivers/gpu/drm/rp1/Kconfig
50 @@ -0,0 +1,5 @@
51 +source "drivers/gpu/drm/rp1/rp1-dsi/Kconfig"
52 +
53 +source "drivers/gpu/drm/rp1/rp1-dpi/Kconfig"
54 +
55 +source "drivers/gpu/drm/rp1/rp1-vec/Kconfig"
56 --- /dev/null
57 +++ b/drivers/gpu/drm/rp1/Makefile
58 @@ -0,0 +1,4 @@
59 +obj-$(CONFIG_DRM_RP1_DSI) += rp1-dsi/
60 +obj-$(CONFIG_DRM_RP1_DPI) += rp1-dpi/
61 +obj-$(CONFIG_DRM_RP1_VEC) += rp1-vec/
62 +
63 --- /dev/null
64 +++ b/drivers/gpu/drm/rp1/rp1-dsi/Kconfig
65 @@ -0,0 +1,15 @@
66 +# SPDX-License-Identifier: GPL-2.0-only
67 +config DRM_RP1_DSI
68 + tristate "DRM Support for RP1 DSI"
69 + depends on DRM
70 + select MFD_RP1
71 + select DRM_GEM_DMA_HELPER
72 + select DRM_KMS_HELPER
73 + select DRM_MIPI_DSI
74 + select DRM_VRAM_HELPER
75 + select DRM_TTM
76 + select DRM_TTM_HELPER
77 + select GENERIC_PHY
78 + select GENERIC_PHY_MIPI_DPHY
79 + help
80 + Choose this option to enable DSI display on RP1
81 --- /dev/null
82 +++ b/drivers/gpu/drm/rp1/rp1-dsi/Makefile
83 @@ -0,0 +1,5 @@
84 +# SPDX-License-Identifier: GPL-2.0-only
85 +
86 +drm-rp1-dsi-y := rp1_dsi.o rp1_dsi_dma.o rp1_dsi_dsi.o
87 +
88 +obj-$(CONFIG_DRM_RP1_DSI) += drm-rp1-dsi.o
89 --- /dev/null
90 +++ b/drivers/gpu/drm/rp1/rp1-dsi/rp1_dsi.c
91 @@ -0,0 +1,537 @@
92 +// SPDX-License-Identifier: GPL-2.0-or-later
93 +/*
94 + * DRM Driver for DSI output on Raspberry Pi RP1
95 + *
96 + * Copyright (c) 2023 Raspberry Pi Limited.
97 + */
98 +
99 +#include <linux/clk.h>
100 +#include <linux/component.h>
101 +#include <linux/delay.h>
102 +#include <linux/dma-mapping.h>
103 +#include <linux/errno.h>
104 +#include <linux/init.h>
105 +#include <linux/interrupt.h>
106 +#include <linux/io.h>
107 +#include <linux/list.h>
108 +#include <linux/module.h>
109 +#include <linux/platform_device.h>
110 +#include <linux/phy/phy-mipi-dphy.h>
111 +#include <linux/string.h>
112 +
113 +#include <drm/drm_atomic_helper.h>
114 +#include <drm/drm_crtc.h>
115 +#include <drm/drm_crtc_helper.h>
116 +#include <drm/drm_drv.h>
117 +#include <drm/drm_encoder.h>
118 +#include <drm/drm_fourcc.h>
119 +#include <drm/drm_fb_helper.h>
120 +#include <drm/drm_framebuffer.h>
121 +#include <drm/drm_gem.h>
122 +#include <drm/drm_gem_atomic_helper.h>
123 +#include <drm/drm_gem_dma_helper.h>
124 +#include <drm/drm_gem_framebuffer_helper.h>
125 +#include <drm/drm_managed.h>
126 +#include <drm/drm_modeset_helper_vtables.h>
127 +#include <drm/drm_of.h>
128 +#include <drm/drm_print.h>
129 +#include <drm/drm_probe_helper.h>
130 +#include <drm/drm_simple_kms_helper.h>
131 +#include <drm/drm_vblank.h>
132 +
133 +#include "rp1_dsi.h"
134 +
135 +static inline struct rp1_dsi *
136 +bridge_to_rp1_dsi(struct drm_bridge *bridge)
137 +{
138 + return container_of(bridge, struct rp1_dsi, bridge);
139 +}
140 +
141 +static void rp1_dsi_bridge_pre_enable(struct drm_bridge *bridge,
142 + struct drm_bridge_state *old_state)
143 +{
144 + struct rp1_dsi *dsi = bridge_to_rp1_dsi(bridge);
145 +
146 + rp1dsi_dsi_setup(dsi, &dsi->pipe.crtc.state->adjusted_mode);
147 +}
148 +
149 +static void rp1_dsi_bridge_enable(struct drm_bridge *bridge,
150 + struct drm_bridge_state *old_state)
151 +{
152 +}
153 +
154 +static void rp1_dsi_bridge_disable(struct drm_bridge *bridge,
155 + struct drm_bridge_state *state)
156 +{
157 +}
158 +
159 +static void rp1_dsi_bridge_post_disable(struct drm_bridge *bridge,
160 + struct drm_bridge_state *state)
161 +{
162 + struct rp1_dsi *dsi = bridge_to_rp1_dsi(bridge);
163 +
164 + if (dsi->dsi_running) {
165 + rp1dsi_dsi_stop(dsi);
166 + dsi->dsi_running = false;
167 + }
168 +}
169 +
170 +static int rp1_dsi_bridge_attach(struct drm_bridge *bridge,
171 + enum drm_bridge_attach_flags flags)
172 +{
173 + struct rp1_dsi *dsi = bridge_to_rp1_dsi(bridge);
174 +
175 + /* Attach the panel or bridge to the dsi bridge */
176 + return drm_bridge_attach(bridge->encoder, dsi->out_bridge,
177 + &dsi->bridge, flags);
178 + return 0;
179 +}
180 +
181 +static const struct drm_bridge_funcs rp1_dsi_bridge_funcs = {
182 + .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
183 + .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
184 + .atomic_reset = drm_atomic_helper_bridge_reset,
185 + .atomic_pre_enable = rp1_dsi_bridge_pre_enable,
186 + .atomic_enable = rp1_dsi_bridge_enable,
187 + .atomic_disable = rp1_dsi_bridge_disable,
188 + .atomic_post_disable = rp1_dsi_bridge_post_disable,
189 + .attach = rp1_dsi_bridge_attach,
190 +};
191 +
192 +static void rp1dsi_pipe_update(struct drm_simple_display_pipe *pipe,
193 + struct drm_plane_state *old_state)
194 +{
195 + struct drm_pending_vblank_event *event;
196 + unsigned long flags;
197 + struct drm_framebuffer *fb = pipe->plane.state->fb;
198 + struct rp1_dsi *dsi = pipe->crtc.dev->dev_private;
199 + struct drm_gem_object *gem = fb ? drm_gem_fb_get_obj(fb, 0) : NULL;
200 + struct drm_gem_dma_object *dma_obj = gem ? to_drm_gem_dma_obj(gem) : NULL;
201 + bool can_update = fb && dma_obj && dsi && dsi->pipe_enabled;
202 +
203 + /* (Re-)start DSI,DMA where required; and update FB address */
204 + if (can_update) {
205 + if (!dsi->dma_running || fb->format->format != dsi->cur_fmt) {
206 + if (dsi->dma_running && fb->format->format != dsi->cur_fmt) {
207 + rp1dsi_dma_stop(dsi);
208 + dsi->dma_running = false;
209 + }
210 + if (!dsi->dma_running) {
211 + rp1dsi_dma_setup(dsi,
212 + fb->format->format, dsi->display_format,
213 + &pipe->crtc.state->adjusted_mode);
214 + dsi->dma_running = true;
215 + }
216 + dsi->cur_fmt = fb->format->format;
217 + drm_crtc_vblank_on(&pipe->crtc);
218 + }
219 + rp1dsi_dma_update(dsi, dma_obj->dma_addr, fb->offsets[0], fb->pitches[0]);
220 + }
221 +
222 + /* Arm VBLANK event (or call it immediately in some error cases) */
223 + spin_lock_irqsave(&pipe->crtc.dev->event_lock, flags);
224 + event = pipe->crtc.state->event;
225 + if (event) {
226 + pipe->crtc.state->event = NULL;
227 + if (can_update && drm_crtc_vblank_get(&pipe->crtc) == 0)
228 + drm_crtc_arm_vblank_event(&pipe->crtc, event);
229 + else
230 + drm_crtc_send_vblank_event(&pipe->crtc, event);
231 + }
232 + spin_unlock_irqrestore(&pipe->crtc.dev->event_lock, flags);
233 +}
234 +
235 +static inline struct rp1_dsi *
236 +encoder_to_rp1_dsi(struct drm_encoder *encoder)
237 +{
238 + struct drm_simple_display_pipe *pipe =
239 + container_of(encoder, struct drm_simple_display_pipe, encoder);
240 + return container_of(pipe, struct rp1_dsi, pipe);
241 +}
242 +
243 +static void rp1dsi_encoder_enable(struct drm_encoder *encoder)
244 +{
245 + struct rp1_dsi *dsi = encoder_to_rp1_dsi(encoder);
246 +
247 + /* Put DSI into video mode before starting video */
248 + rp1dsi_dsi_set_cmdmode(dsi, 0);
249 +
250 + /* Start DMA -> DPI */
251 + dsi->pipe_enabled = true;
252 + dsi->cur_fmt = 0xdeadbeef;
253 + rp1dsi_pipe_update(&dsi->pipe, 0);
254 +}
255 +
256 +static void rp1dsi_encoder_disable(struct drm_encoder *encoder)
257 +{
258 + struct rp1_dsi *dsi = encoder_to_rp1_dsi(encoder);
259 +
260 + drm_crtc_vblank_off(&dsi->pipe.crtc);
261 + if (dsi->dma_running) {
262 + rp1dsi_dma_stop(dsi);
263 + dsi->dma_running = false;
264 + }
265 + dsi->pipe_enabled = false;
266 +
267 + /* Return to command mode after stopping video */
268 + rp1dsi_dsi_set_cmdmode(dsi, 1);
269 +}
270 +
271 +static const struct drm_encoder_helper_funcs rp1_dsi_encoder_funcs = {
272 + .enable = rp1dsi_encoder_enable,
273 + .disable = rp1dsi_encoder_disable,
274 +};
275 +
276 +static void rp1dsi_pipe_enable(struct drm_simple_display_pipe *pipe,
277 + struct drm_crtc_state *crtc_state,
278 + struct drm_plane_state *plane_state)
279 +{
280 +}
281 +
282 +static void rp1dsi_pipe_disable(struct drm_simple_display_pipe *pipe)
283 +{
284 +}
285 +
286 +static int rp1dsi_pipe_enable_vblank(struct drm_simple_display_pipe *pipe)
287 +{
288 + struct rp1_dsi *dsi = pipe->crtc.dev->dev_private;
289 +
290 + if (dsi)
291 + rp1dsi_dma_vblank_ctrl(dsi, 1);
292 +
293 + return 0;
294 +}
295 +
296 +static void rp1dsi_pipe_disable_vblank(struct drm_simple_display_pipe *pipe)
297 +{
298 + struct rp1_dsi *dsi = pipe->crtc.dev->dev_private;
299 +
300 + if (dsi)
301 + rp1dsi_dma_vblank_ctrl(dsi, 0);
302 +}
303 +
304 +static const struct drm_simple_display_pipe_funcs rp1dsi_pipe_funcs = {
305 + .enable = rp1dsi_pipe_enable,
306 + .update = rp1dsi_pipe_update,
307 + .disable = rp1dsi_pipe_disable,
308 + .prepare_fb = drm_gem_simple_display_pipe_prepare_fb,
309 + .enable_vblank = rp1dsi_pipe_enable_vblank,
310 + .disable_vblank = rp1dsi_pipe_disable_vblank,
311 +};
312 +
313 +static const struct drm_mode_config_funcs rp1dsi_mode_funcs = {
314 + .fb_create = drm_gem_fb_create,
315 + .atomic_check = drm_atomic_helper_check,
316 + .atomic_commit = drm_atomic_helper_commit,
317 +};
318 +
319 +static const u32 rp1dsi_formats[] = {
320 + DRM_FORMAT_XRGB8888,
321 + DRM_FORMAT_XBGR8888,
322 + DRM_FORMAT_RGB888,
323 + DRM_FORMAT_BGR888,
324 + DRM_FORMAT_RGB565
325 +};
326 +
327 +static void rp1dsi_stopall(struct drm_device *drm)
328 +{
329 + if (drm->dev_private) {
330 + struct rp1_dsi *dsi = drm->dev_private;
331 +
332 + if (dsi->dma_running || rp1dsi_dma_busy(dsi)) {
333 + rp1dsi_dma_stop(dsi);
334 + dsi->dma_running = false;
335 + }
336 + if (dsi->dsi_running) {
337 + rp1dsi_dsi_stop(dsi);
338 + dsi->dsi_running = false;
339 + }
340 + if (dsi->clocks[RP1DSI_CLOCK_CFG])
341 + clk_disable_unprepare(dsi->clocks[RP1DSI_CLOCK_CFG]);
342 + }
343 +}
344 +
345 +DEFINE_DRM_GEM_DMA_FOPS(rp1dsi_fops);
346 +
347 +static struct drm_driver rp1dsi_driver = {
348 + .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
349 + .fops = &rp1dsi_fops,
350 + .name = "drm-rp1-dsi",
351 + .desc = "drm-rp1-dsi",
352 + .date = "0",
353 + .major = 1,
354 + .minor = 0,
355 + DRM_GEM_DMA_DRIVER_OPS,
356 + .release = rp1dsi_stopall,
357 +};
358 +
359 +static int rp1dsi_bind(struct rp1_dsi *dsi)
360 +{
361 + struct platform_device *pdev = dsi->pdev;
362 + struct drm_device *drm = dsi->drm;
363 + int ret;
364 +
365 + dsi->out_bridge = drmm_of_get_bridge(drm, pdev->dev.of_node, 0, 0);
366 + if (IS_ERR(dsi->out_bridge))
367 + return PTR_ERR(dsi->out_bridge);
368 +
369 + ret = drmm_mode_config_init(drm);
370 + if (ret)
371 + goto rtn;
372 +
373 + drm->mode_config.max_width = 4096;
374 + drm->mode_config.max_height = 4096;
375 + drm->mode_config.fb_base = 0;
376 + drm->mode_config.preferred_depth = 32;
377 + drm->mode_config.prefer_shadow = 0;
378 + drm->mode_config.prefer_shadow_fbdev = 1;
379 + drm->mode_config.quirk_addfb_prefer_host_byte_order = true;
380 + drm->mode_config.funcs = &rp1dsi_mode_funcs;
381 + drm_vblank_init(drm, 1);
382 +
383 + ret = drm_simple_display_pipe_init(drm,
384 + &dsi->pipe,
385 + &rp1dsi_pipe_funcs,
386 + rp1dsi_formats,
387 + ARRAY_SIZE(rp1dsi_formats),
388 + NULL, NULL);
389 + if (ret)
390 + goto rtn;
391 +
392 + /* We need slightly more complex encoder handling (enabling/disabling
393 + * video mode), so add encoder helper functions.
394 + */
395 + drm_encoder_helper_add(&dsi->pipe.encoder, &rp1_dsi_encoder_funcs);
396 +
397 + ret = drm_simple_display_pipe_attach_bridge(&dsi->pipe, &dsi->bridge);
398 + if (ret)
399 + goto rtn;
400 +
401 + drm_bridge_add(&dsi->bridge);
402 +
403 + drm_mode_config_reset(drm);
404 +
405 + if (dsi->clocks[RP1DSI_CLOCK_CFG])
406 + clk_prepare_enable(dsi->clocks[RP1DSI_CLOCK_CFG]);
407 +
408 + ret = drm_dev_register(drm, 0);
409 +
410 + if (ret == 0)
411 + drm_fbdev_generic_setup(drm, 32);
412 +
413 +rtn:
414 + if (ret)
415 + dev_err(&pdev->dev, "%s returned %d\n", __func__, ret);
416 + else
417 + dev_info(&pdev->dev, "%s succeeded", __func__);
418 +
419 + return ret;
420 +}
421 +
422 +static void rp1dsi_unbind(struct rp1_dsi *dsi)
423 +{
424 + struct drm_device *drm = dsi->drm;
425 +
426 + rp1dsi_stopall(drm);
427 + drm_dev_unregister(drm);
428 + drm_atomic_helper_shutdown(drm);
429 +}
430 +
431 +int rp1dsi_host_attach(struct mipi_dsi_host *host, struct mipi_dsi_device *dsi_dev)
432 +{
433 + struct rp1_dsi *dsi = container_of(host, struct rp1_dsi, dsi_host);
434 +
435 + dev_info(&dsi->pdev->dev, "%s: Attach DSI device name=%s channel=%d lanes=%d format=%d flags=0x%lx hs_rate=%lu lp_rate=%lu",
436 + __func__, dsi_dev->name, dsi_dev->channel, dsi_dev->lanes,
437 + dsi_dev->format, dsi_dev->mode_flags, dsi_dev->hs_rate,
438 + dsi_dev->lp_rate);
439 + dsi->vc = dsi_dev->channel & 3;
440 + dsi->lanes = dsi_dev->lanes;
441 +
442 + switch (dsi_dev->format) {
443 + case MIPI_DSI_FMT_RGB666:
444 + case MIPI_DSI_FMT_RGB666_PACKED:
445 + case MIPI_DSI_FMT_RGB565:
446 + case MIPI_DSI_FMT_RGB888:
447 + break;
448 + default:
449 + return -EINVAL;
450 + }
451 + dsi->display_format = dsi_dev->format;
452 + dsi->display_flags = dsi_dev->mode_flags;
453 + dsi->display_hs_rate = dsi_dev->hs_rate;
454 + dsi->display_lp_rate = dsi_dev->lp_rate;
455 +
456 + /*
457 + * Previously, we added a separate component to handle panel/bridge
458 + * discovery and DRM registration, but now it's just a function call.
459 + * The downstream/attaching device should deal with -EPROBE_DEFER
460 + */
461 + return rp1dsi_bind(dsi);
462 +}
463 +
464 +int rp1dsi_host_detach(struct mipi_dsi_host *host, struct mipi_dsi_device *dsi_dev)
465 +{
466 + struct rp1_dsi *dsi = container_of(host, struct rp1_dsi, dsi_host);
467 +
468 + /*
469 + * Unregister the DRM driver.
470 + * TODO: Check we are cleaning up correctly and not doing things multiple times!
471 + */
472 + rp1dsi_unbind(dsi);
473 + return 0;
474 +}
475 +
476 +ssize_t rp1dsi_host_transfer(struct mipi_dsi_host *host, const struct mipi_dsi_msg *msg)
477 +{
478 + struct rp1_dsi *dsi = container_of(host, struct rp1_dsi, dsi_host);
479 + struct mipi_dsi_packet packet;
480 + int ret = 0;
481 +
482 + /* Write */
483 + ret = mipi_dsi_create_packet(&packet, msg);
484 + if (ret) {
485 + dev_err(dsi->drm->dev, "RP1DSI: failed to create packet: %d\n", ret);
486 + return ret;
487 + }
488 +
489 + rp1dsi_dsi_send(dsi, *(u32 *)(&packet.header), packet.payload_length, packet.payload);
490 +
491 + /* Optional read back */
492 + if (msg->rx_len && msg->rx_buf)
493 + ret = rp1dsi_dsi_recv(dsi, msg->rx_len, msg->rx_buf);
494 +
495 + return (ssize_t)ret;
496 +}
497 +
498 +static const struct mipi_dsi_host_ops rp1dsi_mipi_dsi_host_ops = {
499 + .attach = rp1dsi_host_attach,
500 + .detach = rp1dsi_host_detach,
501 + .transfer = rp1dsi_host_transfer
502 +};
503 +
504 +static int rp1dsi_platform_probe(struct platform_device *pdev)
505 +{
506 + struct device *dev = &pdev->dev;
507 + struct drm_device *drm;
508 + struct rp1_dsi *dsi;
509 + int i, ret;
510 +
511 + drm = drm_dev_alloc(&rp1dsi_driver, dev);
512 + if (IS_ERR(drm)) {
513 + ret = PTR_ERR(drm);
514 + return ret;
515 + }
516 + dsi = drmm_kzalloc(drm, sizeof(*dsi), GFP_KERNEL);
517 + if (!dsi) {
518 + ret = -ENOMEM;
519 + goto err_free_drm;
520 + }
521 + init_completion(&dsi->finished);
522 + dsi->drm = drm;
523 + dsi->pdev = pdev;
524 + drm->dev_private = dsi;
525 + platform_set_drvdata(pdev, drm);
526 +
527 + dsi->bridge.funcs = &rp1_dsi_bridge_funcs;
528 + dsi->bridge.of_node = dev->of_node;
529 + dsi->bridge.type = DRM_MODE_CONNECTOR_DSI;
530 +
531 + /* Safe default values for DSI mode */
532 + dsi->lanes = 1;
533 + dsi->display_format = MIPI_DSI_FMT_RGB888;
534 + dsi->display_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_LPM;
535 +
536 + /* Hardware resources */
537 + for (i = 0; i < RP1DSI_NUM_CLOCKS; i++) {
538 + static const char * const myclocknames[RP1DSI_NUM_CLOCKS] = {
539 + "cfgclk", "dpiclk", "byteclk", "refclk"
540 + };
541 + dsi->clocks[i] = devm_clk_get(dev, myclocknames[i]);
542 + if (IS_ERR(dsi->clocks[i])) {
543 + ret = PTR_ERR(dsi->clocks[i]);
544 + dev_err(dev, "Error getting clocks[%d]\n", i);
545 + goto err_free_drm;
546 + }
547 + }
548 +
549 + for (i = 0; i < RP1DSI_NUM_HW_BLOCKS; i++) {
550 + dsi->hw_base[i] =
551 + devm_ioremap_resource(dev,
552 + platform_get_resource(dsi->pdev,
553 + IORESOURCE_MEM,
554 + i));
555 + if (IS_ERR(dsi->hw_base[i])) {
556 + ret = PTR_ERR(dsi->hw_base[i]);
557 + dev_err(dev, "Error memory mapping regs[%d]\n", i);
558 + goto err_free_drm;
559 + }
560 + }
561 + ret = platform_get_irq(dsi->pdev, 0);
562 + if (ret > 0)
563 + ret = devm_request_irq(dev, ret, rp1dsi_dma_isr,
564 + IRQF_SHARED, "rp1-dsi", dsi);
565 + if (ret) {
566 + dev_err(dev, "Unable to request interrupt\n");
567 + ret = -EINVAL;
568 + goto err_free_drm;
569 + }
570 + rp1dsi_mipicfg_setup(dsi);
571 + dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
572 +
573 + /* Create the MIPI DSI Host and wait for the panel/bridge to attach to it */
574 + dsi->dsi_host.ops = &rp1dsi_mipi_dsi_host_ops;
575 + dsi->dsi_host.dev = dev;
576 + ret = mipi_dsi_host_register(&dsi->dsi_host);
577 + if (ret)
578 + goto err_free_drm;
579 +
580 + return ret;
581 +
582 +err_free_drm:
583 + dev_err(dev, "%s fail %d\n", __func__, ret);
584 + drm_dev_put(drm);
585 + return ret;
586 +}
587 +
588 +static int rp1dsi_platform_remove(struct platform_device *pdev)
589 +{
590 + struct drm_device *drm = platform_get_drvdata(pdev);
591 + struct rp1_dsi *dsi = drm->dev_private;
592 +
593 + mipi_dsi_host_unregister(&dsi->dsi_host);
594 + return 0;
595 +}
596 +
597 +static void rp1dsi_platform_shutdown(struct platform_device *pdev)
598 +{
599 + struct drm_device *drm = platform_get_drvdata(pdev);
600 +
601 + rp1dsi_stopall(drm);
602 +}
603 +
604 +static const struct of_device_id rp1dsi_of_match[] = {
605 + {
606 + .compatible = "raspberrypi,rp1dsi",
607 + },
608 + { /* sentinel */ },
609 +};
610 +
611 +MODULE_DEVICE_TABLE(of, rp1dsi_of_match);
612 +
613 +static struct platform_driver rp1dsi_platform_driver = {
614 + .probe = rp1dsi_platform_probe,
615 + .remove = rp1dsi_platform_remove,
616 + .shutdown = rp1dsi_platform_shutdown,
617 + .driver = {
618 + .name = DRIVER_NAME,
619 + .owner = THIS_MODULE,
620 + .of_match_table = rp1dsi_of_match,
621 + },
622 +};
623 +
624 +module_platform_driver(rp1dsi_platform_driver);
625 +
626 +MODULE_LICENSE("GPL");
627 +MODULE_DESCRIPTION("MIPI DSI driver for Raspberry Pi RP1");
628 +MODULE_AUTHOR("Nick Hollinghurst");
629 --- /dev/null
630 +++ b/drivers/gpu/drm/rp1/rp1-dsi/rp1_dsi.h
631 @@ -0,0 +1,94 @@
632 +/* SPDX-License-Identifier: GPL-2.0 */
633 +/*
634 + * DRM Driver for DSI output on Raspberry Pi RP1
635 + *
636 + * Copyright (c) 2023 Raspberry Pi Limited.
637 + */
638 +#ifndef _RP1_DSI_H_
639 +#define _RP1_DSI_H_
640 +
641 +#include <linux/clk.h>
642 +#include <linux/io.h>
643 +#include <linux/types.h>
644 +
645 +#include <drm/drm_bridge.h>
646 +#include <drm/drm_device.h>
647 +#include <drm/drm_mipi_dsi.h>
648 +#include <drm/drm_simple_kms_helper.h>
649 +
650 +#define MODULE_NAME "drm-rp1-dsi"
651 +#define DRIVER_NAME "drm-rp1-dsi"
652 +
653 +/* ---------------------------------------------------------------------- */
654 +
655 +#define RP1DSI_HW_BLOCK_DMA 0
656 +#define RP1DSI_HW_BLOCK_DSI 1
657 +#define RP1DSI_HW_BLOCK_CFG 2
658 +#define RP1DSI_NUM_HW_BLOCKS 3
659 +
660 +#define RP1DSI_CLOCK_CFG 0
661 +#define RP1DSI_CLOCK_DPI 1
662 +#define RP1DSI_CLOCK_BYTE 2
663 +#define RP1DSI_CLOCK_REF 3
664 +#define RP1DSI_NUM_CLOCKS 4
665 +
666 +/* ---------------------------------------------------------------------- */
667 +
668 +struct rp1_dsi {
669 + /* DRM and platform device pointers */
670 + struct drm_device *drm;
671 + struct platform_device *pdev;
672 +
673 + /* Framework and helper objects */
674 + struct drm_simple_display_pipe pipe;
675 + struct drm_bridge bridge;
676 + struct drm_bridge *out_bridge;
677 + struct mipi_dsi_host dsi_host;
678 +
679 + /* Clocks. We need DPI clock; the others are frequency references */
680 + struct clk *clocks[RP1DSI_NUM_CLOCKS];
681 +
682 + /* Block (DSI DMA, DSI Host) base addresses, and current state */
683 + void __iomem *hw_base[RP1DSI_NUM_HW_BLOCKS];
684 + u32 cur_fmt;
685 + bool dsi_running, dma_running, pipe_enabled;
686 + struct completion finished;
687 +
688 + /* Attached display parameters (from mipi_dsi_device) */
689 + unsigned long display_flags, display_hs_rate, display_lp_rate;
690 + enum mipi_dsi_pixel_format display_format;
691 + u8 vc;
692 + u8 lanes;
693 +
694 + /* DPHY */
695 + u8 hsfreq_index;
696 +};
697 +
698 +/* ---------------------------------------------------------------------- */
699 +/* Functions to control the DSI/DPI/DMA block */
700 +
701 +void rp1dsi_dma_setup(struct rp1_dsi *dsi,
702 + u32 in_format, enum mipi_dsi_pixel_format out_format,
703 + struct drm_display_mode const *mode);
704 +void rp1dsi_dma_update(struct rp1_dsi *dsi, dma_addr_t addr, u32 offset, u32 stride);
705 +void rp1dsi_dma_stop(struct rp1_dsi *dsi);
706 +int rp1dsi_dma_busy(struct rp1_dsi *dsi);
707 +irqreturn_t rp1dsi_dma_isr(int irq, void *dev);
708 +void rp1dsi_dma_vblank_ctrl(struct rp1_dsi *dsi, int enable);
709 +
710 +/* ---------------------------------------------------------------------- */
711 +/* Functions to control the MIPICFG block and check RP1 platform */
712 +
713 +void rp1dsi_mipicfg_setup(struct rp1_dsi *dsi);
714 +
715 +/* ---------------------------------------------------------------------- */
716 +/* Functions to control the SNPS D-PHY and DSI block setup */
717 +
718 +void rp1dsi_dsi_setup(struct rp1_dsi *dsi, struct drm_display_mode const *mode);
719 +void rp1dsi_dsi_send(struct rp1_dsi *dsi, u32 header, int len, const u8 *buf);
720 +int rp1dsi_dsi_recv(struct rp1_dsi *dsi, int len, u8 *buf);
721 +void rp1dsi_dsi_set_cmdmode(struct rp1_dsi *dsi, int cmd_mode);
722 +void rp1dsi_dsi_stop(struct rp1_dsi *dsi);
723 +
724 +#endif
725 +
726 --- /dev/null
727 +++ b/drivers/gpu/drm/rp1/rp1-dsi/rp1_dsi_dma.c
728 @@ -0,0 +1,443 @@
729 +// SPDX-License-Identifier: GPL-2.0-or-later
730 +/*
731 + * DRM Driver for DSI output on Raspberry Pi RP1
732 + *
733 + * Copyright (c) 2023 Raspberry Pi Limited.
734 + */
735 +
736 +#include <linux/interrupt.h>
737 +#include <linux/platform_device.h>
738 +
739 +#include <drm/drm_fourcc.h>
740 +#include <drm/drm_print.h>
741 +#include <drm/drm_vblank.h>
742 +
743 +#include "rp1_dsi.h"
744 +
745 +// --- DPI DMA REGISTERS (derived from Argon firmware, via RP1 drivers/mipi, with corrections) ---
746 +
747 +// Control
748 +#define DPI_DMA_CONTROL 0x0
749 +#define DPI_DMA_CONTROL_ARM_SHIFT 0
750 +#define DPI_DMA_CONTROL_ARM_MASK BIT(DPI_DMA_CONTROL_ARM_SHIFT)
751 +#define DPI_DMA_CONTROL_ALIGN16_SHIFT 2
752 +#define DPI_DMA_CONTROL_ALIGN16_MASK BIT(DPI_DMA_CONTROL_ALIGN16_SHIFT)
753 +#define DPI_DMA_CONTROL_AUTO_REPEAT_SHIFT 1
754 +#define DPI_DMA_CONTROL_AUTO_REPEAT_MASK BIT(DPI_DMA_CONTROL_AUTO_REPEAT_SHIFT)
755 +#define DPI_DMA_CONTROL_HIGH_WATER_SHIFT 3
756 +#define DPI_DMA_CONTROL_HIGH_WATER_MASK (0x1FF << DPI_DMA_CONTROL_HIGH_WATER_SHIFT)
757 +#define DPI_DMA_CONTROL_DEN_POL_SHIFT 12
758 +#define DPI_DMA_CONTROL_DEN_POL_MASK BIT(DPI_DMA_CONTROL_DEN_POL_SHIFT)
759 +#define DPI_DMA_CONTROL_HSYNC_POL_SHIFT 13
760 +#define DPI_DMA_CONTROL_HSYNC_POL_MASK BIT(DPI_DMA_CONTROL_HSYNC_POL_SHIFT)
761 +#define DPI_DMA_CONTROL_VSYNC_POL_SHIFT 14
762 +#define DPI_DMA_CONTROL_VSYNC_POL_MASK BIT(DPI_DMA_CONTROL_VSYNC_POL_SHIFT)
763 +#define DPI_DMA_CONTROL_COLORM_SHIFT 15
764 +#define DPI_DMA_CONTROL_COLORM_MASK BIT(DPI_DMA_CONTROL_COLORM_SHIFT)
765 +#define DPI_DMA_CONTROL_SHUTDN_SHIFT 16
766 +#define DPI_DMA_CONTROL_SHUTDN_MASK BIT(DPI_DMA_CONTROL_SHUTDN_SHIFT)
767 +#define DPI_DMA_CONTROL_HBP_EN_SHIFT 17
768 +#define DPI_DMA_CONTROL_HBP_EN_MASK BIT(DPI_DMA_CONTROL_HBP_EN_SHIFT)
769 +#define DPI_DMA_CONTROL_HFP_EN_SHIFT 18
770 +#define DPI_DMA_CONTROL_HFP_EN_MASK BIT(DPI_DMA_CONTROL_HFP_EN_SHIFT)
771 +#define DPI_DMA_CONTROL_VBP_EN_SHIFT 19
772 +#define DPI_DMA_CONTROL_VBP_EN_MASK BIT(DPI_DMA_CONTROL_VBP_EN_SHIFT)
773 +#define DPI_DMA_CONTROL_VFP_EN_SHIFT 20
774 +#define DPI_DMA_CONTROL_VFP_EN_MASK BIT(DPI_DMA_CONTROL_VFP_EN_SHIFT)
775 +#define DPI_DMA_CONTROL_HSYNC_EN_SHIFT 21
776 +#define DPI_DMA_CONTROL_HSYNC_EN_MASK BIT(DPI_DMA_CONTROL_HSYNC_EN_SHIFT)
777 +#define DPI_DMA_CONTROL_VSYNC_EN_SHIFT 22
778 +#define DPI_DMA_CONTROL_VSYNC_EN_MASK BIT(DPI_DMA_CONTROL_VSYNC_EN_SHIFT)
779 +#define DPI_DMA_CONTROL_FORCE_IMMED_SHIFT 23
780 +#define DPI_DMA_CONTROL_FORCE_IMMED_MASK BIT(DPI_DMA_CONTROL_FORCE_IMMED_SHIFT)
781 +#define DPI_DMA_CONTROL_FORCE_DRAIN_SHIFT 24
782 +#define DPI_DMA_CONTROL_FORCE_DRAIN_MASK BIT(DPI_DMA_CONTROL_FORCE_DRAIN_SHIFT)
783 +#define DPI_DMA_CONTROL_FORCE_EMPTY_SHIFT 25
784 +#define DPI_DMA_CONTROL_FORCE_EMPTY_MASK BIT(DPI_DMA_CONTROL_FORCE_EMPTY_SHIFT)
785 +
786 +// IRQ_ENABLES
787 +#define DPI_DMA_IRQ_EN 0x04
788 +#define DPI_DMA_IRQ_EN_DMA_READY_SHIFT 0
789 +#define DPI_DMA_IRQ_EN_DMA_READY_MASK BIT(DPI_DMA_IRQ_EN_DMA_READY_SHIFT)
790 +#define DPI_DMA_IRQ_EN_UNDERFLOW_SHIFT 1
791 +#define DPI_DMA_IRQ_EN_UNDERFLOW_MASK BIT(DPI_DMA_IRQ_EN_UNDERFLOW_SHIFT)
792 +#define DPI_DMA_IRQ_EN_FRAME_START_SHIFT 2
793 +#define DPI_DMA_IRQ_EN_FRAME_START_MASK BIT(DPI_DMA_IRQ_EN_FRAME_START_SHIFT)
794 +#define DPI_DMA_IRQ_EN_AFIFO_EMPTY_SHIFT 3
795 +#define DPI_DMA_IRQ_EN_AFIFO_EMPTY_MASK BIT(DPI_DMA_IRQ_EN_AFIFO_EMPTY_SHIFT)
796 +#define DPI_DMA_IRQ_EN_TE_SHIFT 4
797 +#define DPI_DMA_IRQ_EN_TE_MASK BIT(DPI_DMA_IRQ_EN_TE_SHIFT)
798 +#define DPI_DMA_IRQ_EN_ERROR_SHIFT 5
799 +#define DPI_DMA_IRQ_EN_ERROR_MASK BIT(DPI_DMA_IRQ_EN_ERROR_SHIFT)
800 +#define DPI_DMA_IRQ_EN_MATCH_SHIFT 6
801 +#define DPI_DMA_IRQ_EN_MATCH_MASK BIT(DPI_DMA_IRQ_EN_MATCH_SHIFT)
802 +#define DPI_DMA_IRQ_EN_MATCH_LINE_SHIFT 16
803 +#define DPI_DMA_IRQ_EN_MATCH_LINE_MASK (0xFFF << DPI_DMA_IRQ_EN_MATCH_LINE_SHIFT)
804 +
805 +// IRQ_FLAGS
806 +#define DPI_DMA_IRQ_FLAGS 0x08
807 +#define DPI_DMA_IRQ_FLAGS_DMA_READY_SHIFT 0
808 +#define DPI_DMA_IRQ_FLAGS_DMA_READY_MASK BIT(DPI_DMA_IRQ_FLAGS_DMA_READY_SHIFT)
809 +#define DPI_DMA_IRQ_FLAGS_UNDERFLOW_SHIFT 1
810 +#define DPI_DMA_IRQ_FLAGS_UNDERFLOW_MASK BIT(DPI_DMA_IRQ_FLAGS_UNDERFLOW_SHIFT)
811 +#define DPI_DMA_IRQ_FLAGS_FRAME_START_SHIFT 2
812 +#define DPI_DMA_IRQ_FLAGS_FRAME_START_MASK BIT(DPI_DMA_IRQ_FLAGS_FRAME_START_SHIFT)
813 +#define DPI_DMA_IRQ_FLAGS_AFIFO_EMPTY_SHIFT 3
814 +#define DPI_DMA_IRQ_FLAGS_AFIFO_EMPTY_MASK BIT(DPI_DMA_IRQ_FLAGS_AFIFO_EMPTY_SHIFT)
815 +#define DPI_DMA_IRQ_FLAGS_TE_SHIFT 4
816 +#define DPI_DMA_IRQ_FLAGS_TE_MASK BIT(DPI_DMA_IRQ_FLAGS_TE_SHIFT)
817 +#define DPI_DMA_IRQ_FLAGS_ERROR_SHIFT 5
818 +#define DPI_DMA_IRQ_FLAGS_ERROR_MASK BIT(DPI_DMA_IRQ_FLAGS_ERROR_SHIFT)
819 +#define DPI_DMA_IRQ_FLAGS_MATCH_SHIFT 6
820 +#define DPI_DMA_IRQ_FLAGS_MATCH_MASK BIT(DPI_DMA_IRQ_FLAGS_MATCH_SHIFT)
821 +
822 +// QOS
823 +#define DPI_DMA_QOS 0xC
824 +#define DPI_DMA_QOS_DQOS_SHIFT 0
825 +#define DPI_DMA_QOS_DQOS_MASK (0xF << DPI_DMA_QOS_DQOS_SHIFT)
826 +#define DPI_DMA_QOS_ULEV_SHIFT 4
827 +#define DPI_DMA_QOS_ULEV_MASK (0xF << DPI_DMA_QOS_ULEV_SHIFT)
828 +#define DPI_DMA_QOS_UQOS_SHIFT 8
829 +#define DPI_DMA_QOS_UQOS_MASK (0xF << DPI_DMA_QOS_UQOS_SHIFT)
830 +#define DPI_DMA_QOS_LLEV_SHIFT 12
831 +#define DPI_DMA_QOS_LLEV_MASK (0xF << DPI_DMA_QOS_LLEV_SHIFT)
832 +#define DPI_DMA_QOS_LQOS_SHIFT 16
833 +#define DPI_DMA_QOS_LQOS_MASK (0xF << DPI_DMA_QOS_LQOS_SHIFT)
834 +
835 +// Panics
836 +#define DPI_DMA_PANICS 0x38
837 +#define DPI_DMA_PANICS_UPPER_COUNT_SHIFT 0
838 +#define DPI_DMA_PANICS_UPPER_COUNT_MASK \
839 + (0x0000FFFF << DPI_DMA_PANICS_UPPER_COUNT_SHIFT)
840 +#define DPI_DMA_PANICS_LOWER_COUNT_SHIFT 16
841 +#define DPI_DMA_PANICS_LOWER_COUNT_MASK \
842 + (0x0000FFFF << DPI_DMA_PANICS_LOWER_COUNT_SHIFT)
843 +
844 +// DMA Address Lower:
845 +#define DPI_DMA_DMA_ADDR_L 0x10
846 +
847 +// DMA Address Upper:
848 +#define DPI_DMA_DMA_ADDR_H 0x40
849 +
850 +// DMA stride
851 +#define DPI_DMA_DMA_STRIDE 0x14
852 +
853 +// Visible Area
854 +#define DPI_DMA_VISIBLE_AREA 0x18
855 +#define DPI_DMA_VISIBLE_AREA_ROWSM1_SHIFT 0
856 +#define DPI_DMA_VISIBLE_AREA_ROWSM1_MASK (0x0FFF << DPI_DMA_VISIBLE_AREA_ROWSM1_SHIFT)
857 +#define DPI_DMA_VISIBLE_AREA_COLSM1_SHIFT 16
858 +#define DPI_DMA_VISIBLE_AREA_COLSM1_MASK (0x0FFF << DPI_DMA_VISIBLE_AREA_COLSM1_SHIFT)
859 +
860 +// Sync width
861 +#define DPI_DMA_SYNC_WIDTH 0x1C
862 +#define DPI_DMA_SYNC_WIDTH_ROWSM1_SHIFT 0
863 +#define DPI_DMA_SYNC_WIDTH_ROWSM1_MASK (0x0FFF << DPI_DMA_SYNC_WIDTH_ROWSM1_SHIFT)
864 +#define DPI_DMA_SYNC_WIDTH_COLSM1_SHIFT 16
865 +#define DPI_DMA_SYNC_WIDTH_COLSM1_MASK (0x0FFF << DPI_DMA_SYNC_WIDTH_COLSM1_SHIFT)
866 +
867 +// Back porch
868 +#define DPI_DMA_BACK_PORCH 0x20
869 +#define DPI_DMA_BACK_PORCH_ROWSM1_SHIFT 0
870 +#define DPI_DMA_BACK_PORCH_ROWSM1_MASK (0x0FFF << DPI_DMA_BACK_PORCH_ROWSM1_SHIFT)
871 +#define DPI_DMA_BACK_PORCH_COLSM1_SHIFT 16
872 +#define DPI_DMA_BACK_PORCH_COLSM1_MASK (0x0FFF << DPI_DMA_BACK_PORCH_COLSM1_SHIFT)
873 +
874 +// Front porch
875 +#define DPI_DMA_FRONT_PORCH 0x24
876 +#define DPI_DMA_FRONT_PORCH_ROWSM1_SHIFT 0
877 +#define DPI_DMA_FRONT_PORCH_ROWSM1_MASK (0x0FFF << DPI_DMA_FRONT_PORCH_ROWSM1_SHIFT)
878 +#define DPI_DMA_FRONT_PORCH_COLSM1_SHIFT 16
879 +#define DPI_DMA_FRONT_PORCH_COLSM1_MASK (0x0FFF << DPI_DMA_FRONT_PORCH_COLSM1_SHIFT)
880 +
881 +// Input masks
882 +#define DPI_DMA_IMASK 0x2C
883 +#define DPI_DMA_IMASK_R_SHIFT 0
884 +#define DPI_DMA_IMASK_R_MASK (0x3FF << DPI_DMA_IMASK_R_SHIFT)
885 +#define DPI_DMA_IMASK_G_SHIFT 10
886 +#define DPI_DMA_IMASK_G_MASK (0x3FF << DPI_DMA_IMASK_G_SHIFT)
887 +#define DPI_DMA_IMASK_B_SHIFT 20
888 +#define DPI_DMA_IMASK_B_MASK (0x3FF << DPI_DMA_IMASK_B_SHIFT)
889 +
890 +// Output Masks
891 +#define DPI_DMA_OMASK 0x30
892 +#define DPI_DMA_OMASK_R_SHIFT 0
893 +#define DPI_DMA_OMASK_R_MASK (0x3FF << DPI_DMA_OMASK_R_SHIFT)
894 +#define DPI_DMA_OMASK_G_SHIFT 10
895 +#define DPI_DMA_OMASK_G_MASK (0x3FF << DPI_DMA_OMASK_G_SHIFT)
896 +#define DPI_DMA_OMASK_B_SHIFT 20
897 +#define DPI_DMA_OMASK_B_MASK (0x3FF << DPI_DMA_OMASK_B_SHIFT)
898 +
899 +// Shifts
900 +#define DPI_DMA_SHIFT 0x28
901 +#define DPI_DMA_SHIFT_IR_SHIFT 0
902 +#define DPI_DMA_SHIFT_IR_MASK (0x1F << DPI_DMA_SHIFT_IR_SHIFT)
903 +#define DPI_DMA_SHIFT_IG_SHIFT 5
904 +#define DPI_DMA_SHIFT_IG_MASK (0x1F << DPI_DMA_SHIFT_IG_SHIFT)
905 +#define DPI_DMA_SHIFT_IB_SHIFT 10
906 +#define DPI_DMA_SHIFT_IB_MASK (0x1F << DPI_DMA_SHIFT_IB_SHIFT)
907 +#define DPI_DMA_SHIFT_OR_SHIFT 15
908 +#define DPI_DMA_SHIFT_OR_MASK (0x1F << DPI_DMA_SHIFT_OR_SHIFT)
909 +#define DPI_DMA_SHIFT_OG_SHIFT 20
910 +#define DPI_DMA_SHIFT_OG_MASK (0x1F << DPI_DMA_SHIFT_OG_SHIFT)
911 +#define DPI_DMA_SHIFT_OB_SHIFT 25
912 +#define DPI_DMA_SHIFT_OB_MASK (0x1F << DPI_DMA_SHIFT_OB_SHIFT)
913 +
914 +// Scaling
915 +#define DPI_DMA_RGBSZ 0x34
916 +#define DPI_DMA_RGBSZ_BPP_SHIFT 16
917 +#define DPI_DMA_RGBSZ_BPP_MASK (0x3 << DPI_DMA_RGBSZ_BPP_SHIFT)
918 +#define DPI_DMA_RGBSZ_R_SHIFT 0
919 +#define DPI_DMA_RGBSZ_R_MASK (0xF << DPI_DMA_RGBSZ_R_SHIFT)
920 +#define DPI_DMA_RGBSZ_G_SHIFT 4
921 +#define DPI_DMA_RGBSZ_G_MASK (0xF << DPI_DMA_RGBSZ_G_SHIFT)
922 +#define DPI_DMA_RGBSZ_B_SHIFT 8
923 +#define DPI_DMA_RGBSZ_B_MASK (0xF << DPI_DMA_RGBSZ_B_SHIFT)
924 +
925 +// Status
926 +#define DPI_DMA_STATUS 0x3c
927 +
928 +#define BITS(field, val) (((val) << (field ## _SHIFT)) & (field ## _MASK))
929 +
930 +static unsigned int rp1dsi_dma_read(struct rp1_dsi *dsi, unsigned int reg)
931 +{
932 + void __iomem *addr = dsi->hw_base[RP1DSI_HW_BLOCK_DMA] + reg;
933 +
934 + return readl(addr);
935 +}
936 +
937 +static void rp1dsi_dma_write(struct rp1_dsi *dsi, unsigned int reg, unsigned int val)
938 +{
939 + void __iomem *addr = dsi->hw_base[RP1DSI_HW_BLOCK_DMA] + reg;
940 +
941 + writel(val, addr);
942 +}
943 +
944 +int rp1dsi_dma_busy(struct rp1_dsi *dsi)
945 +{
946 + return (rp1dsi_dma_read(dsi, DPI_DMA_STATUS) & 0xF8F) ? 1 : 0;
947 +}
948 +
949 +/* Table of supported input (in-memory/DMA) pixel formats. */
950 +struct rp1dsi_ipixfmt {
951 + u32 format; /* DRM format code */
952 + u32 mask; /* RGB masks (10 bits each, left justified) */
953 + u32 shift; /* RGB MSB positions in the memory word */
954 + u32 rgbsz; /* Shifts used for scaling; also (BPP/8-1) */
955 +};
956 +
957 +#define IMASK_RGB(r, g, b) (BITS(DPI_DMA_IMASK_R, r) | \
958 + BITS(DPI_DMA_IMASK_G, g) | \
959 + BITS(DPI_DMA_IMASK_B, b))
960 +#define ISHIFT_RGB(r, g, b) (BITS(DPI_DMA_SHIFT_IR, r) | \
961 + BITS(DPI_DMA_SHIFT_IG, g) | \
962 + BITS(DPI_DMA_SHIFT_IB, b))
963 +
964 +static const struct rp1dsi_ipixfmt my_formats[] = {
965 + {
966 + .format = DRM_FORMAT_XRGB8888,
967 + .mask = IMASK_RGB(0x3fc, 0x3fc, 0x3fc),
968 + .shift = ISHIFT_RGB(23, 15, 7),
969 + .rgbsz = BITS(DPI_DMA_RGBSZ_BPP, 3),
970 + },
971 + {
972 + .format = DRM_FORMAT_XBGR8888,
973 + .mask = IMASK_RGB(0x3fc, 0x3fc, 0x3fc),
974 + .shift = ISHIFT_RGB(7, 15, 23),
975 + .rgbsz = BITS(DPI_DMA_RGBSZ_BPP, 3),
976 + },
977 + {
978 + .format = DRM_FORMAT_RGB888,
979 + .mask = IMASK_RGB(0x3fc, 0x3fc, 0x3fc),
980 + .shift = ISHIFT_RGB(23, 15, 7),
981 + .rgbsz = BITS(DPI_DMA_RGBSZ_BPP, 2),
982 + },
983 + {
984 + .format = DRM_FORMAT_BGR888,
985 + .mask = IMASK_RGB(0x3fc, 0x3fc, 0x3fc),
986 + .shift = ISHIFT_RGB(7, 15, 23),
987 + .rgbsz = BITS(DPI_DMA_RGBSZ_BPP, 2),
988 + },
989 + {
990 + .format = DRM_FORMAT_RGB565,
991 + .mask = IMASK_RGB(0x3e0, 0x3f0, 0x3e0),
992 + .shift = ISHIFT_RGB(15, 10, 4),
993 + .rgbsz = BITS(DPI_DMA_RGBSZ_R, 5) | BITS(DPI_DMA_RGBSZ_G, 6) |
994 + BITS(DPI_DMA_RGBSZ_B, 5) | BITS(DPI_DMA_RGBSZ_BPP, 1),
995 + }
996 +};
997 +
998 +/* Choose the internal on-the-bus DPI format as expected by DSI Host. */
999 +static u32 get_omask_oshift(enum mipi_dsi_pixel_format fmt, u32 *oshift)
1000 +{
1001 + switch (fmt) {
1002 + case MIPI_DSI_FMT_RGB565:
1003 + *oshift = BITS(DPI_DMA_SHIFT_OR, 15) |
1004 + BITS(DPI_DMA_SHIFT_OG, 10) |
1005 + BITS(DPI_DMA_SHIFT_OB, 4);
1006 + return BITS(DPI_DMA_OMASK_R, 0x3e0) |
1007 + BITS(DPI_DMA_OMASK_G, 0x3f0) |
1008 + BITS(DPI_DMA_OMASK_B, 0x3e0);
1009 + case MIPI_DSI_FMT_RGB666_PACKED:
1010 + *oshift = BITS(DPI_DMA_SHIFT_OR, 17) |
1011 + BITS(DPI_DMA_SHIFT_OG, 11) |
1012 + BITS(DPI_DMA_SHIFT_OB, 5);
1013 + return BITS(DPI_DMA_OMASK_R, 0x3f0) |
1014 + BITS(DPI_DMA_OMASK_G, 0x3f0) |
1015 + BITS(DPI_DMA_OMASK_B, 0x3f0);
1016 + case MIPI_DSI_FMT_RGB666:
1017 + *oshift = BITS(DPI_DMA_SHIFT_OR, 21) |
1018 + BITS(DPI_DMA_SHIFT_OG, 13) |
1019 + BITS(DPI_DMA_SHIFT_OB, 5);
1020 + return BITS(DPI_DMA_OMASK_R, 0x3f0) |
1021 + BITS(DPI_DMA_OMASK_G, 0x3f0) |
1022 + BITS(DPI_DMA_OMASK_B, 0x3f0);
1023 + default:
1024 + *oshift = BITS(DPI_DMA_SHIFT_OR, 23) |
1025 + BITS(DPI_DMA_SHIFT_OG, 15) |
1026 + BITS(DPI_DMA_SHIFT_OB, 7);
1027 + return BITS(DPI_DMA_OMASK_R, 0x3fc) |
1028 + BITS(DPI_DMA_OMASK_G, 0x3fc) |
1029 + BITS(DPI_DMA_OMASK_B, 0x3fc);
1030 + }
1031 +}
1032 +
1033 +void rp1dsi_dma_setup(struct rp1_dsi *dsi,
1034 + u32 in_format, enum mipi_dsi_pixel_format out_format,
1035 + struct drm_display_mode const *mode)
1036 +{
1037 + u32 oshift;
1038 + int i;
1039 +
1040 + /*
1041 + * Configure all DSI/DPI/DMA block registers, except base address.
1042 + * DMA will not actually start until a FB base address is specified
1043 + * using rp1dsi_dma_update().
1044 + */
1045 +
1046 + rp1dsi_dma_write(dsi, DPI_DMA_VISIBLE_AREA,
1047 + BITS(DPI_DMA_VISIBLE_AREA_ROWSM1, mode->vdisplay - 1) |
1048 + BITS(DPI_DMA_VISIBLE_AREA_COLSM1, mode->hdisplay - 1));
1049 +
1050 + rp1dsi_dma_write(dsi, DPI_DMA_SYNC_WIDTH,
1051 + BITS(DPI_DMA_SYNC_WIDTH_ROWSM1, mode->vsync_end - mode->vsync_start - 1) |
1052 + BITS(DPI_DMA_SYNC_WIDTH_COLSM1, mode->hsync_end - mode->hsync_start - 1));
1053 +
1054 + /* In the DPIDMA registers, "back porch" time includes sync width */
1055 + rp1dsi_dma_write(dsi, DPI_DMA_BACK_PORCH,
1056 + BITS(DPI_DMA_BACK_PORCH_ROWSM1, mode->vtotal - mode->vsync_start - 1) |
1057 + BITS(DPI_DMA_BACK_PORCH_COLSM1, mode->htotal - mode->hsync_start - 1));
1058 +
1059 + rp1dsi_dma_write(dsi, DPI_DMA_FRONT_PORCH,
1060 + BITS(DPI_DMA_FRONT_PORCH_ROWSM1, mode->vsync_start - mode->vdisplay - 1) |
1061 + BITS(DPI_DMA_FRONT_PORCH_COLSM1, mode->hsync_start - mode->hdisplay - 1));
1062 +
1063 + /* Input to output pixel format conversion */
1064 + for (i = 0; i < ARRAY_SIZE(my_formats); ++i) {
1065 + if (my_formats[i].format == in_format)
1066 + break;
1067 + }
1068 + if (i >= ARRAY_SIZE(my_formats)) {
1069 + drm_err(dsi->drm, "%s: bad input format\n", __func__);
1070 + i = 0;
1071 + }
1072 + rp1dsi_dma_write(dsi, DPI_DMA_IMASK, my_formats[i].mask);
1073 + rp1dsi_dma_write(dsi, DPI_DMA_OMASK, get_omask_oshift(out_format, &oshift));
1074 + rp1dsi_dma_write(dsi, DPI_DMA_SHIFT, my_formats[i].shift | oshift);
1075 + if (out_format == MIPI_DSI_FMT_RGB888)
1076 + rp1dsi_dma_write(dsi, DPI_DMA_RGBSZ, my_formats[i].rgbsz);
1077 + else
1078 + rp1dsi_dma_write(dsi, DPI_DMA_RGBSZ, my_formats[i].rgbsz & DPI_DMA_RGBSZ_BPP_MASK);
1079 +
1080 + rp1dsi_dma_write(dsi, DPI_DMA_QOS,
1081 + BITS(DPI_DMA_QOS_DQOS, 0x0) |
1082 + BITS(DPI_DMA_QOS_ULEV, 0xb) |
1083 + BITS(DPI_DMA_QOS_UQOS, 0x2) |
1084 + BITS(DPI_DMA_QOS_LLEV, 0x8) |
1085 + BITS(DPI_DMA_QOS_LQOS, 0x7));
1086 +
1087 + rp1dsi_dma_write(dsi, DPI_DMA_IRQ_FLAGS, -1);
1088 + rp1dsi_dma_vblank_ctrl(dsi, 1);
1089 +
1090 + i = rp1dsi_dma_busy(dsi);
1091 + if (i)
1092 + drm_err(dsi->drm, "RP1DSI: Unexpectedly busy at start!");
1093 +
1094 + rp1dsi_dma_write(dsi, DPI_DMA_CONTROL,
1095 + BITS(DPI_DMA_CONTROL_ARM, (i == 0)) |
1096 + BITS(DPI_DMA_CONTROL_AUTO_REPEAT, 1) |
1097 + BITS(DPI_DMA_CONTROL_HIGH_WATER, 448) |
1098 + BITS(DPI_DMA_CONTROL_DEN_POL, 0) |
1099 + BITS(DPI_DMA_CONTROL_HSYNC_POL, 0) |
1100 + BITS(DPI_DMA_CONTROL_VSYNC_POL, 0) |
1101 + BITS(DPI_DMA_CONTROL_COLORM, 0) |
1102 + BITS(DPI_DMA_CONTROL_SHUTDN, 0) |
1103 + BITS(DPI_DMA_CONTROL_HBP_EN, 1) |
1104 + BITS(DPI_DMA_CONTROL_HFP_EN, 1) |
1105 + BITS(DPI_DMA_CONTROL_VBP_EN, 1) |
1106 + BITS(DPI_DMA_CONTROL_VFP_EN, 1) |
1107 + BITS(DPI_DMA_CONTROL_HSYNC_EN, 1) |
1108 + BITS(DPI_DMA_CONTROL_VSYNC_EN, 1));
1109 +}
1110 +
1111 +void rp1dsi_dma_update(struct rp1_dsi *dsi, dma_addr_t addr, u32 offset, u32 stride)
1112 +{
1113 + /*
1114 + * Update STRIDE, DMAH and DMAL only. When called after rp1dsi_dma_setup(),
1115 + * DMA starts immediately; if already running, the buffer will flip at
1116 + * the next vertical sync event.
1117 + */
1118 + u64 a = addr + offset;
1119 +
1120 + rp1dsi_dma_write(dsi, DPI_DMA_DMA_STRIDE, stride);
1121 + rp1dsi_dma_write(dsi, DPI_DMA_DMA_ADDR_H, a >> 32);
1122 + rp1dsi_dma_write(dsi, DPI_DMA_DMA_ADDR_L, a & 0xFFFFFFFFu);
1123 +}
1124 +
1125 +void rp1dsi_dma_stop(struct rp1_dsi *dsi)
1126 +{
1127 + /*
1128 + * Stop DMA by turning off the Auto-Repeat flag, and wait up to 100ms for
1129 + * the current and any queued frame to end. "Force drain" flags are not used,
1130 + * as they seem to prevent DMA from re-starting properly; it's safer to wait.
1131 + */
1132 + u32 ctrl;
1133 +
1134 + reinit_completion(&dsi->finished);
1135 + ctrl = rp1dsi_dma_read(dsi, DPI_DMA_CONTROL);
1136 + ctrl &= ~(DPI_DMA_CONTROL_ARM_MASK | DPI_DMA_CONTROL_AUTO_REPEAT_MASK);
1137 + rp1dsi_dma_write(dsi, DPI_DMA_CONTROL, ctrl);
1138 + if (!wait_for_completion_timeout(&dsi->finished, HZ / 10))
1139 + drm_err(dsi->drm, "%s: timed out waiting for idle\n", __func__);
1140 + rp1dsi_dma_write(dsi, DPI_DMA_IRQ_EN, 0);
1141 +}
1142 +
1143 +void rp1dsi_dma_vblank_ctrl(struct rp1_dsi *dsi, int enable)
1144 +{
1145 + rp1dsi_dma_write(dsi, DPI_DMA_IRQ_EN,
1146 + BITS(DPI_DMA_IRQ_EN_AFIFO_EMPTY, 1) |
1147 + BITS(DPI_DMA_IRQ_EN_UNDERFLOW, 1) |
1148 + BITS(DPI_DMA_IRQ_EN_DMA_READY, !!enable) |
1149 + BITS(DPI_DMA_IRQ_EN_MATCH_LINE, 4095));
1150 +}
1151 +
1152 +irqreturn_t rp1dsi_dma_isr(int irq, void *dev)
1153 +{
1154 + struct rp1_dsi *dsi = dev;
1155 + u32 u = rp1dsi_dma_read(dsi, DPI_DMA_IRQ_FLAGS);
1156 +
1157 + if (u) {
1158 + rp1dsi_dma_write(dsi, DPI_DMA_IRQ_FLAGS, u);
1159 + if (dsi) {
1160 + if (u & DPI_DMA_IRQ_FLAGS_UNDERFLOW_MASK)
1161 + drm_err_ratelimited(dsi->drm,
1162 + "Underflow! (panics=0x%08x)\n",
1163 + rp1dsi_dma_read(dsi, DPI_DMA_PANICS));
1164 + if (u & DPI_DMA_IRQ_FLAGS_DMA_READY_MASK)
1165 + drm_crtc_handle_vblank(&dsi->pipe.crtc);
1166 + if (u & DPI_DMA_IRQ_FLAGS_AFIFO_EMPTY_MASK)
1167 + complete(&dsi->finished);
1168 + }
1169 + }
1170 + return u ? IRQ_HANDLED : IRQ_NONE;
1171 +}
1172 --- /dev/null
1173 +++ b/drivers/gpu/drm/rp1/rp1-dsi/rp1_dsi_dsi.c
1174 @@ -0,0 +1,1504 @@
1175 +// SPDX-License-Identifier: GPL-2.0-or-later
1176 +/*
1177 + * DRM Driver for DSI output on Raspberry Pi RP1
1178 + *
1179 + * Copyright (c) 2023 Raspberry Pi Limited.
1180 + */
1181 +
1182 +#include <linux/delay.h>
1183 +#include <linux/errno.h>
1184 +#include <linux/platform_device.h>
1185 +#include <linux/rp1_platform.h>
1186 +#include "drm/drm_print.h"
1187 +
1188 +#include "rp1_dsi.h"
1189 +
1190 +/* ------------------------------- Synopsis DSI ------------------------ */
1191 +#define DSI_VERSION_CFG 0x000
1192 +#define DSI_PWR_UP 0x004
1193 +#define DSI_CLKMGR_CFG 0x008
1194 +#define DSI_DPI_VCID 0x00C
1195 +#define DSI_DPI_COLOR_CODING 0x010
1196 +#define DSI_DPI_CFG_POL 0x014
1197 +#define DSI_DPI_LP_CMD_TIM 0x018
1198 +#define DSI_DBI_VCID 0x01C
1199 +#define DSI_DBI_CFG 0x020
1200 +#define DSI_DBI_PARTITIONING_EN 0x024
1201 +#define DSI_DBI_CMDSIZE 0x028
1202 +#define DSI_PCKHDL_CFG 0x02C
1203 +#define DSI_GEN_VCID 0x030
1204 +#define DSI_MODE_CFG 0x034
1205 +#define DSI_VID_MODE_CFG 0x038
1206 +#define DSI_VID_PKT_SIZE 0x03C
1207 +#define DSI_VID_NUM_CHUNKS 0x040
1208 +#define DSI_VID_NULL_SIZE 0x044
1209 +#define DSI_VID_HSA_TIME 0x048
1210 +#define DSI_VID_HBP_TIME 0x04C
1211 +#define DSI_VID_HLINE_TIME 0x050
1212 +#define DSI_VID_VSA_LINES 0x054
1213 +#define DSI_VID_VBP_LINES 0x058
1214 +#define DSI_VID_VFP_LINES 0x05C
1215 +#define DSI_VID_VACTIVE_LINES 0x060
1216 +#define DSI_EDPI_CMD_SIZE 0x064
1217 +#define DSI_CMD_MODE_CFG 0x068
1218 +#define DSI_GEN_HDR 0x06C
1219 +#define DSI_GEN_PLD_DATA 0x070
1220 +#define DSI_CMD_PKT_STATUS 0x074
1221 +#define DSI_TO_CNT_CFG 0x078
1222 +#define DSI_HS_RD_TO_CNT 0x07C
1223 +#define DSI_LP_RD_TO_CNT 0x080
1224 +#define DSI_HS_WR_TO_CNT 0x084
1225 +#define DSI_LP_WR_TO_CNT 0x088
1226 +#define DSI_BTA_TO_CNT 0x08C
1227 +#define DSI_SDF_3D 0x090
1228 +#define DSI_LPCLK_CTRL 0x094
1229 +#define DSI_PHY_TMR_LPCLK_CFG 0x098
1230 +#define DSI_PHY_TMR_HS2LP_LSB 16
1231 +#define DSI_PHY_TMR_LP2HS_LSB 0
1232 +#define DSI_PHY_TMR_CFG 0x09C
1233 +#define DSI_PHY_TMR_RD_CFG 0x0F4
1234 +#define DSI_PHYRSTZ 0x0A0
1235 +#define DSI_PHY_IF_CFG 0x0A4
1236 +#define DSI_PHY_ULPS_CTRL 0x0A8
1237 +#define DSI_PHY_TX_TRIGGERS 0x0AC
1238 +#define DSI_PHY_STATUS 0x0B0
1239 +
1240 +#define DSI_PHY_TST_CTRL0 0x0B4
1241 +#define DSI_PHY_TST_CTRL1 0x0B8
1242 +#define DSI_INT_ST0 0x0BC
1243 +#define DSI_INT_ST1 0x0C0
1244 +#define DSI_INT_MASK0_CFG 0x0C4
1245 +#define DSI_INT_MASK1_CFG 0x0C8
1246 +#define DSI_PHY_CAL 0x0CC
1247 +#define DSI_HEXP_NPKT_CLR 0x104
1248 +#define DSI_HEXP_NPKT_SIZE 0x108
1249 +#define DSI_VID_SHADOW_CTRL 0x100
1250 +
1251 +#define DSI_DPI_VCID_ACT 0x10C
1252 +#define DSI_DPI_COLOR_CODING_ACT 0x110
1253 +#define DSI_DPI_LP_CMD_TIM_ACT 0x118
1254 +#define DSI_VID_MODE_CFG_ACT 0x138
1255 +#define DSI_VID_PKT_SIZE_ACT 0x13C
1256 +#define DSI_VID_NUM_CHUNKS_ACT 0x140
1257 +#define DSI_VID_NULL_SIZE_ACT 0x144
1258 +#define DSI_VID_HSA_TIME_ACT 0x148
1259 +#define DSI_VID_HBP_TIME_ACT 0x14C
1260 +#define DSI_VID_HLINE_TIME_ACT 0x150
1261 +#define DSI_VID_VSA_LINES_ACT 0x154
1262 +#define DSI_VID_VBP_LINES_ACT 0x158
1263 +#define DSI_VID_VFP_LINES_ACT 0x15C
1264 +#define DSI_VID_VACTIVE_LINES_ACT 0x160
1265 +#define DSI_SDF_3D_CFG_ACT 0x190
1266 +
1267 +#define DSI_INT_FORCE0 0x0D8
1268 +#define DSI_INT_FORCE1 0x0DC
1269 +
1270 +#define DSI_AUTO_ULPS_MODE 0x0E0
1271 +#define DSI_AUTO_ULPS_ENTRY_DELAY 0x0E4
1272 +#define DSI_AUTO_ULPS_WAKEUP_TIME 0x0E8
1273 +#define DSI_EDPI_ADV_FEATURES 0x0EC
1274 +
1275 +#define DSI_DSC_PARAMETER 0x0F0
1276 +
1277 +/* And some bitfield definitions */
1278 +
1279 +#define DPHY_PWR_UP_SHUTDOWNZ_LSB 0
1280 +#define DPHY_PWR_UP_SHUTDOWNZ_BITS BIT(DPHY_PWR_UP_SHUTDOWNZ_LSB)
1281 +
1282 +#define DPHY_CTRL0_PHY_TESTCLK_LSB 1
1283 +#define DPHY_CTRL0_PHY_TESTCLK_BITS BIT(DPHY_CTRL0_PHY_TESTCLK_LSB)
1284 +#define DPHY_CTRL0_PHY_TESTCLR_LSB 0
1285 +#define DPHY_CTRL0_PHY_TESTCLR_BITS BIT(DPHY_CTRL0_PHY_TESTCLR_LSB)
1286 +
1287 +#define DPHY_CTRL1_PHY_TESTDIN_LSB 0
1288 +#define DPHY_CTRL1_PHY_TESTDIN_BITS (0xff << DPHY_CTRL1_PHY_TESTDIN_LSB)
1289 +#define DPHY_CTRL1_PHY_TESTDOUT_LSB 8
1290 +#define DPHY_CTRL1_PHY_TESTDOUT_BITS (0xff << DPHY_CTRL1_PHY_TESTDOUT_LSB)
1291 +#define DPHY_CTRL1_PHY_TESTEN_LSB 16
1292 +#define DPHY_CTRL1_PHY_TESTEN_BITS BIT(DPHY_CTRL1_PHY_TESTEN_LSB)
1293 +
1294 +#define DSI_PHYRSTZ_SHUTDOWNZ_LSB 0
1295 +#define DSI_PHYRSTZ_SHUTDOWNZ_BITS BIT(DSI_PHYRSTZ_SHUTDOWNZ_LSB)
1296 +#define DSI_PHYRSTZ_RSTZ_LSB 1
1297 +#define DSI_PHYRSTZ_RSTZ_BITS BIT(DSI_PHYRSTZ_RSTZ_LSB)
1298 +#define DSI_PHYRSTZ_ENABLECLK_LSB 2
1299 +#define DSI_PHYRSTZ_ENABLECLK_BITS BIT(DSI_PHYRSTZ_ENABLECLK_LSB)
1300 +#define DSI_PHYRSTZ_FORCEPLL_LSB 3
1301 +#define DSI_PHYRSTZ_FORCEPLL_BITS BIT(DSI_PHYRSTZ_FORCEPLL_LSB)
1302 +
1303 +#define DPHY_HS_RX_CTRL_LANE0_OFFSET 0x44
1304 +#define DPHY_PLL_INPUT_DIV_OFFSET 0x17
1305 +#define DPHY_PLL_LOOP_DIV_OFFSET 0x18
1306 +#define DPHY_PLL_DIV_CTRL_OFFSET 0x19
1307 +
1308 +#define DPHY_PLL_BIAS_OFFSET 0x10
1309 +#define DPHY_PLL_BIAS_VCO_RANGE_LSB 3
1310 +#define DPHY_PLL_BIAS_USE_PROGRAMMED_VCO_RANGE BIT(7)
1311 +
1312 +#define DPHY_PLL_CHARGE_PUMP_OFFSET 0x11
1313 +#define DPHY_PLL_LPF_OFFSET 0x12
1314 +
1315 +#define DSI_WRITE(reg, val) writel((val), dsi->hw_base[RP1DSI_HW_BLOCK_DSI] + (reg))
1316 +#define DSI_READ(reg) readl(dsi->hw_base[RP1DSI_HW_BLOCK_DSI] + (reg))
1317 +
1318 +// ================================================================================
1319 +// Register block : RPI_MIPICFG
1320 +// Version : 1
1321 +// Bus type : apb
1322 +// Description : Register block to control mipi DPHY
1323 +// ================================================================================
1324 +#define RPI_MIPICFG_REGS_RWTYPE_MSB 13
1325 +#define RPI_MIPICFG_REGS_RWTYPE_LSB 12
1326 +// ================================================================================
1327 +// Register : RPI_MIPICFG_CLK2FC
1328 +// JTAG access : synchronous
1329 +// Description : None
1330 +#define RPI_MIPICFG_CLK2FC_OFFSET 0x00000000
1331 +#define RPI_MIPICFG_CLK2FC_BITS 0x00000007
1332 +#define RPI_MIPICFG_CLK2FC_RESET 0x00000000
1333 +// --------------------------------------------------------------------------------
1334 +// Field : RPI_MIPICFG_CLK2FC_SEL
1335 +// Description : select a clock to be sent to the frequency counter
1336 +// 7 = none
1337 +// 6 = none
1338 +// 5 = none
1339 +// 4 = rxbyteclkhs (187.5MHz)
1340 +// 3 = rxclkesc0 (20MHz)
1341 +// 2 = txbyteclkhs (187.5MHz)
1342 +// 1 = txclkesc (125MHz)
1343 +// 0 = none
1344 +#define RPI_MIPICFG_CLK2FC_SEL_RESET 0x0
1345 +#define RPI_MIPICFG_CLK2FC_SEL_BITS 0x00000007
1346 +#define RPI_MIPICFG_CLK2FC_SEL_MSB 2
1347 +#define RPI_MIPICFG_CLK2FC_SEL_LSB 0
1348 +#define RPI_MIPICFG_CLK2FC_SEL_ACCESS "RW"
1349 +// ================================================================================
1350 +// Register : RPI_MIPICFG_CFG
1351 +// JTAG access : asynchronous
1352 +// Description : Top level configuration
1353 +#define RPI_MIPICFG_CFG_OFFSET 0x00000004
1354 +#define RPI_MIPICFG_CFG_BITS 0x00000111
1355 +#define RPI_MIPICFG_CFG_RESET 0x00000001
1356 +// --------------------------------------------------------------------------------
1357 +// Field : RPI_MIPICFG_CFG_DPIUPDATE
1358 +// Description : Indicate the DSI block that the next frame will have a new video configuration
1359 +#define RPI_MIPICFG_CFG_DPIUPDATE_RESET 0x0
1360 +#define RPI_MIPICFG_CFG_DPIUPDATE_BITS 0x00000100
1361 +#define RPI_MIPICFG_CFG_DPIUPDATE_MSB 8
1362 +#define RPI_MIPICFG_CFG_DPIUPDATE_LSB 8
1363 +#define RPI_MIPICFG_CFG_DPIUPDATE_ACCESS "RW"
1364 +// --------------------------------------------------------------------------------
1365 +// Field : RPI_MIPICFG_CFG_SEL_TE_EXT
1366 +// Description : Select the TE source: 1 - ext, 0 - int
1367 +#define RPI_MIPICFG_CFG_SEL_TE_EXT_RESET 0x0
1368 +#define RPI_MIPICFG_CFG_SEL_TE_EXT_BITS 0x00000010
1369 +#define RPI_MIPICFG_CFG_SEL_TE_EXT_MSB 4
1370 +#define RPI_MIPICFG_CFG_SEL_TE_EXT_LSB 4
1371 +#define RPI_MIPICFG_CFG_SEL_TE_EXT_ACCESS "RW"
1372 +// --------------------------------------------------------------------------------
1373 +// Field : RPI_MIPICFG_CFG_SEL_CSI_DSI_N
1374 +// Description : Select PHY direction: input to CSI, output from DSI. CSI 1 DSI 0
1375 +#define RPI_MIPICFG_CFG_SEL_CSI_DSI_N_RESET 0x1
1376 +#define RPI_MIPICFG_CFG_SEL_CSI_DSI_N_BITS 0x00000001
1377 +#define RPI_MIPICFG_CFG_SEL_CSI_DSI_N_MSB 0
1378 +#define RPI_MIPICFG_CFG_SEL_CSI_DSI_N_LSB 0
1379 +#define RPI_MIPICFG_CFG_SEL_CSI_DSI_N_ACCESS "RW"
1380 +// ================================================================================
1381 +// Register : RPI_MIPICFG_TE
1382 +// JTAG access : synchronous
1383 +// Description : Tearing effect processing
1384 +#define RPI_MIPICFG_TE_OFFSET 0x00000008
1385 +#define RPI_MIPICFG_TE_BITS 0x10ffffff
1386 +#define RPI_MIPICFG_TE_RESET 0x00000000
1387 +// --------------------------------------------------------------------------------
1388 +// Field : RPI_MIPICFG_TE_ARM
1389 +// Description : Tearing effect arm
1390 +#define RPI_MIPICFG_TE_ARM_RESET 0x0
1391 +#define RPI_MIPICFG_TE_ARM_BITS 0x10000000
1392 +#define RPI_MIPICFG_TE_ARM_MSB 28
1393 +#define RPI_MIPICFG_TE_ARM_LSB 28
1394 +#define RPI_MIPICFG_TE_ARM_ACCESS "RW"
1395 +// --------------------------------------------------------------------------------
1396 +// Field : RPI_MIPICFG_TE_HALT_CYC
1397 +// Description : When arm pulse has been seen, wait for te; then halt the dpi block
1398 +// for this many clk_dpi cycles
1399 +#define RPI_MIPICFG_TE_HALT_CYC_RESET 0x000000
1400 +#define RPI_MIPICFG_TE_HALT_CYC_BITS 0x00ffffff
1401 +#define RPI_MIPICFG_TE_HALT_CYC_MSB 23
1402 +#define RPI_MIPICFG_TE_HALT_CYC_LSB 0
1403 +#define RPI_MIPICFG_TE_HALT_CYC_ACCESS "RW"
1404 +// ================================================================================
1405 +// Register : RPI_MIPICFG_DPHY_MONITOR
1406 +// JTAG access : asynchronous
1407 +// Description : DPHY status monitors for analog DFT
1408 +#define RPI_MIPICFG_DPHY_MONITOR_OFFSET 0x00000010
1409 +#define RPI_MIPICFG_DPHY_MONITOR_BITS 0x00111fff
1410 +#define RPI_MIPICFG_DPHY_MONITOR_RESET 0x00000000
1411 +// --------------------------------------------------------------------------------
1412 +// Field : RPI_MIPICFG_DPHY_MONITOR_LOCK
1413 +// Description : None
1414 +#define RPI_MIPICFG_DPHY_MONITOR_LOCK_RESET 0x0
1415 +#define RPI_MIPICFG_DPHY_MONITOR_LOCK_BITS 0x00100000
1416 +#define RPI_MIPICFG_DPHY_MONITOR_LOCK_MSB 20
1417 +#define RPI_MIPICFG_DPHY_MONITOR_LOCK_LSB 20
1418 +#define RPI_MIPICFG_DPHY_MONITOR_LOCK_ACCESS "RO"
1419 +// --------------------------------------------------------------------------------
1420 +// Field : RPI_MIPICFG_DPHY_MONITOR_BISTOK
1421 +// Description : None
1422 +#define RPI_MIPICFG_DPHY_MONITOR_BISTOK_RESET 0x0
1423 +#define RPI_MIPICFG_DPHY_MONITOR_BISTOK_BITS 0x00010000
1424 +#define RPI_MIPICFG_DPHY_MONITOR_BISTOK_MSB 16
1425 +#define RPI_MIPICFG_DPHY_MONITOR_BISTOK_LSB 16
1426 +#define RPI_MIPICFG_DPHY_MONITOR_BISTOK_ACCESS "RO"
1427 +// --------------------------------------------------------------------------------
1428 +// Field : RPI_MIPICFG_DPHY_MONITOR_STOPSTATECLK
1429 +// Description : None
1430 +#define RPI_MIPICFG_DPHY_MONITOR_STOPSTATECLK_RESET 0x0
1431 +#define RPI_MIPICFG_DPHY_MONITOR_STOPSTATECLK_BITS 0x00001000
1432 +#define RPI_MIPICFG_DPHY_MONITOR_STOPSTATECLK_MSB 12
1433 +#define RPI_MIPICFG_DPHY_MONITOR_STOPSTATECLK_LSB 12
1434 +#define RPI_MIPICFG_DPHY_MONITOR_STOPSTATECLK_ACCESS "RO"
1435 +// --------------------------------------------------------------------------------
1436 +// Field : RPI_MIPICFG_DPHY_MONITOR_STOPSTATEDATA
1437 +// Description : None
1438 +#define RPI_MIPICFG_DPHY_MONITOR_STOPSTATEDATA_RESET 0x0
1439 +#define RPI_MIPICFG_DPHY_MONITOR_STOPSTATEDATA_BITS 0x00000f00
1440 +#define RPI_MIPICFG_DPHY_MONITOR_STOPSTATEDATA_MSB 11
1441 +#define RPI_MIPICFG_DPHY_MONITOR_STOPSTATEDATA_LSB 8
1442 +#define RPI_MIPICFG_DPHY_MONITOR_STOPSTATEDATA_ACCESS "RO"
1443 +// --------------------------------------------------------------------------------
1444 +// Field : RPI_MIPICFG_DPHY_MONITOR_TESTDOUT
1445 +// Description : None
1446 +#define RPI_MIPICFG_DPHY_MONITOR_TESTDOUT_RESET 0x00
1447 +#define RPI_MIPICFG_DPHY_MONITOR_TESTDOUT_BITS 0x000000ff
1448 +#define RPI_MIPICFG_DPHY_MONITOR_TESTDOUT_MSB 7
1449 +#define RPI_MIPICFG_DPHY_MONITOR_TESTDOUT_LSB 0
1450 +#define RPI_MIPICFG_DPHY_MONITOR_TESTDOUT_ACCESS "RO"
1451 +// ================================================================================
1452 +// Register : RPI_MIPICFG_DPHY_CTRL_0
1453 +// JTAG access : asynchronous
1454 +// Description : DPHY control for analog DFT
1455 +#define RPI_MIPICFG_DPHY_CTRL_0_OFFSET 0x00000014
1456 +#define RPI_MIPICFG_DPHY_CTRL_0_BITS 0x0000003f
1457 +#define RPI_MIPICFG_DPHY_CTRL_0_RESET 0x00000000
1458 +// --------------------------------------------------------------------------------
1459 +// Field : RPI_MIPICFG_DPHY_CTRL_0_TEST_LPMODE
1460 +// Description : When set in lpmode, TXCLKESC is driven from clk_vec(driven from clocks block)
1461 +#define RPI_MIPICFG_DPHY_CTRL_0_TEST_LPMODE_RESET 0x0
1462 +#define RPI_MIPICFG_DPHY_CTRL_0_TEST_LPMODE_BITS 0x00000020
1463 +#define RPI_MIPICFG_DPHY_CTRL_0_TEST_LPMODE_MSB 5
1464 +#define RPI_MIPICFG_DPHY_CTRL_0_TEST_LPMODE_LSB 5
1465 +#define RPI_MIPICFG_DPHY_CTRL_0_TEST_LPMODE_ACCESS "RW"
1466 +// --------------------------------------------------------------------------------
1467 +// Field : RPI_MIPICFG_DPHY_CTRL_0_TEST_ENA
1468 +// Description : When set, drive the DPHY from the test registers
1469 +#define RPI_MIPICFG_DPHY_CTRL_0_TEST_ENA_RESET 0x0
1470 +#define RPI_MIPICFG_DPHY_CTRL_0_TEST_ENA_BITS 0x00000010
1471 +#define RPI_MIPICFG_DPHY_CTRL_0_TEST_ENA_MSB 4
1472 +#define RPI_MIPICFG_DPHY_CTRL_0_TEST_ENA_LSB 4
1473 +#define RPI_MIPICFG_DPHY_CTRL_0_TEST_ENA_ACCESS "RW"
1474 +// --------------------------------------------------------------------------------
1475 +// Field : RPI_MIPICFG_DPHY_CTRL_0_CFG_CLK_DIS
1476 +// Description : When test_ena is set, disable cfg_clk
1477 +#define RPI_MIPICFG_DPHY_CTRL_0_CFG_CLK_DIS_RESET 0x0
1478 +#define RPI_MIPICFG_DPHY_CTRL_0_CFG_CLK_DIS_BITS 0x00000008
1479 +#define RPI_MIPICFG_DPHY_CTRL_0_CFG_CLK_DIS_MSB 3
1480 +#define RPI_MIPICFG_DPHY_CTRL_0_CFG_CLK_DIS_LSB 3
1481 +#define RPI_MIPICFG_DPHY_CTRL_0_CFG_CLK_DIS_ACCESS "RW"
1482 +// --------------------------------------------------------------------------------
1483 +// Field : RPI_MIPICFG_DPHY_CTRL_0_REFCLK_DIS
1484 +// Description : When test_ena is set, disable refclk
1485 +#define RPI_MIPICFG_DPHY_CTRL_0_REFCLK_DIS_RESET 0x0
1486 +#define RPI_MIPICFG_DPHY_CTRL_0_REFCLK_DIS_BITS 0x00000004
1487 +#define RPI_MIPICFG_DPHY_CTRL_0_REFCLK_DIS_MSB 2
1488 +#define RPI_MIPICFG_DPHY_CTRL_0_REFCLK_DIS_LSB 2
1489 +#define RPI_MIPICFG_DPHY_CTRL_0_REFCLK_DIS_ACCESS "RW"
1490 +// --------------------------------------------------------------------------------
1491 +// Field : RPI_MIPICFG_DPHY_CTRL_0_TXCLKESC_DIS
1492 +// Description : When test_ena is set, disable txclkesc
1493 +#define RPI_MIPICFG_DPHY_CTRL_0_TXCLKESC_DIS_RESET 0x0
1494 +#define RPI_MIPICFG_DPHY_CTRL_0_TXCLKESC_DIS_BITS 0x00000002
1495 +#define RPI_MIPICFG_DPHY_CTRL_0_TXCLKESC_DIS_MSB 1
1496 +#define RPI_MIPICFG_DPHY_CTRL_0_TXCLKESC_DIS_LSB 1
1497 +#define RPI_MIPICFG_DPHY_CTRL_0_TXCLKESC_DIS_ACCESS "RW"
1498 +// --------------------------------------------------------------------------------
1499 +// Field : RPI_MIPICFG_DPHY_CTRL_0_TXBYTECLKHS_DIS
1500 +// Description : When test_ena is set, disable txbyteclkhs
1501 +#define RPI_MIPICFG_DPHY_CTRL_0_TXBYTECLKHS_DIS_RESET 0x0
1502 +#define RPI_MIPICFG_DPHY_CTRL_0_TXBYTECLKHS_DIS_BITS 0x00000001
1503 +#define RPI_MIPICFG_DPHY_CTRL_0_TXBYTECLKHS_DIS_MSB 0
1504 +#define RPI_MIPICFG_DPHY_CTRL_0_TXBYTECLKHS_DIS_LSB 0
1505 +#define RPI_MIPICFG_DPHY_CTRL_0_TXBYTECLKHS_DIS_ACCESS "RW"
1506 +// ================================================================================
1507 +// Register : RPI_MIPICFG_DPHY_CTRL_1
1508 +// JTAG access : asynchronous
1509 +// Description : DPHY control for analog DFT
1510 +#define RPI_MIPICFG_DPHY_CTRL_1_OFFSET 0x00000018
1511 +#define RPI_MIPICFG_DPHY_CTRL_1_BITS 0x7fffffff
1512 +#define RPI_MIPICFG_DPHY_CTRL_1_RESET 0x00000000
1513 +// --------------------------------------------------------------------------------
1514 +// Field : RPI_MIPICFG_DPHY_CTRL_1_FORCEPLL
1515 +// Description : None
1516 +#define RPI_MIPICFG_DPHY_CTRL_1_FORCEPLL_RESET 0x0
1517 +#define RPI_MIPICFG_DPHY_CTRL_1_FORCEPLL_BITS 0x40000000
1518 +#define RPI_MIPICFG_DPHY_CTRL_1_FORCEPLL_MSB 30
1519 +#define RPI_MIPICFG_DPHY_CTRL_1_FORCEPLL_LSB 30
1520 +#define RPI_MIPICFG_DPHY_CTRL_1_FORCEPLL_ACCESS "RW"
1521 +// --------------------------------------------------------------------------------
1522 +// Field : RPI_MIPICFG_DPHY_CTRL_1_SHUTDOWNZ
1523 +// Description : None
1524 +#define RPI_MIPICFG_DPHY_CTRL_1_SHUTDOWNZ_RESET 0x0
1525 +#define RPI_MIPICFG_DPHY_CTRL_1_SHUTDOWNZ_BITS 0x20000000
1526 +#define RPI_MIPICFG_DPHY_CTRL_1_SHUTDOWNZ_MSB 29
1527 +#define RPI_MIPICFG_DPHY_CTRL_1_SHUTDOWNZ_LSB 29
1528 +#define RPI_MIPICFG_DPHY_CTRL_1_SHUTDOWNZ_ACCESS "RW"
1529 +// --------------------------------------------------------------------------------
1530 +// Field : RPI_MIPICFG_DPHY_CTRL_1_RSTZ
1531 +// Description : None
1532 +#define RPI_MIPICFG_DPHY_CTRL_1_RSTZ_RESET 0x0
1533 +#define RPI_MIPICFG_DPHY_CTRL_1_RSTZ_BITS 0x10000000
1534 +#define RPI_MIPICFG_DPHY_CTRL_1_RSTZ_MSB 28
1535 +#define RPI_MIPICFG_DPHY_CTRL_1_RSTZ_LSB 28
1536 +#define RPI_MIPICFG_DPHY_CTRL_1_RSTZ_ACCESS "RW"
1537 +// --------------------------------------------------------------------------------
1538 +// Field : RPI_MIPICFG_DPHY_CTRL_1_MASTERSLAVEZ
1539 +// Description : None
1540 +#define RPI_MIPICFG_DPHY_CTRL_1_MASTERSLAVEZ_RESET 0x0
1541 +#define RPI_MIPICFG_DPHY_CTRL_1_MASTERSLAVEZ_BITS 0x08000000
1542 +#define RPI_MIPICFG_DPHY_CTRL_1_MASTERSLAVEZ_MSB 27
1543 +#define RPI_MIPICFG_DPHY_CTRL_1_MASTERSLAVEZ_LSB 27
1544 +#define RPI_MIPICFG_DPHY_CTRL_1_MASTERSLAVEZ_ACCESS "RW"
1545 +// --------------------------------------------------------------------------------
1546 +// Field : RPI_MIPICFG_DPHY_CTRL_1_BISTON
1547 +// Description : None
1548 +#define RPI_MIPICFG_DPHY_CTRL_1_BISTON_RESET 0x0
1549 +#define RPI_MIPICFG_DPHY_CTRL_1_BISTON_BITS 0x04000000
1550 +#define RPI_MIPICFG_DPHY_CTRL_1_BISTON_MSB 26
1551 +#define RPI_MIPICFG_DPHY_CTRL_1_BISTON_LSB 26
1552 +#define RPI_MIPICFG_DPHY_CTRL_1_BISTON_ACCESS "RW"
1553 +// --------------------------------------------------------------------------------
1554 +// Field : RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTHSCLK
1555 +// Description : None
1556 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTHSCLK_RESET 0x0
1557 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTHSCLK_BITS 0x02000000
1558 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTHSCLK_MSB 25
1559 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTHSCLK_LSB 25
1560 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTHSCLK_ACCESS "RW"
1561 +// --------------------------------------------------------------------------------
1562 +// Field : RPI_MIPICFG_DPHY_CTRL_1_ENABLECLK
1563 +// Description : None
1564 +#define RPI_MIPICFG_DPHY_CTRL_1_ENABLECLK_RESET 0x0
1565 +#define RPI_MIPICFG_DPHY_CTRL_1_ENABLECLK_BITS 0x01000000
1566 +#define RPI_MIPICFG_DPHY_CTRL_1_ENABLECLK_MSB 24
1567 +#define RPI_MIPICFG_DPHY_CTRL_1_ENABLECLK_LSB 24
1568 +#define RPI_MIPICFG_DPHY_CTRL_1_ENABLECLK_ACCESS "RW"
1569 +// --------------------------------------------------------------------------------
1570 +// Field : RPI_MIPICFG_DPHY_CTRL_1_ENABLE_3
1571 +// Description : None
1572 +#define RPI_MIPICFG_DPHY_CTRL_1_ENABLE_3_RESET 0x0
1573 +#define RPI_MIPICFG_DPHY_CTRL_1_ENABLE_3_BITS 0x00800000
1574 +#define RPI_MIPICFG_DPHY_CTRL_1_ENABLE_3_MSB 23
1575 +#define RPI_MIPICFG_DPHY_CTRL_1_ENABLE_3_LSB 23
1576 +#define RPI_MIPICFG_DPHY_CTRL_1_ENABLE_3_ACCESS "RW"
1577 +// --------------------------------------------------------------------------------
1578 +// Field : RPI_MIPICFG_DPHY_CTRL_1_ENABLE_2
1579 +// Description : None
1580 +#define RPI_MIPICFG_DPHY_CTRL_1_ENABLE_2_RESET 0x0
1581 +#define RPI_MIPICFG_DPHY_CTRL_1_ENABLE_2_BITS 0x00400000
1582 +#define RPI_MIPICFG_DPHY_CTRL_1_ENABLE_2_MSB 22
1583 +#define RPI_MIPICFG_DPHY_CTRL_1_ENABLE_2_LSB 22
1584 +#define RPI_MIPICFG_DPHY_CTRL_1_ENABLE_2_ACCESS "RW"
1585 +// --------------------------------------------------------------------------------
1586 +// Field : RPI_MIPICFG_DPHY_CTRL_1_ENABLE_1
1587 +// Description : None
1588 +#define RPI_MIPICFG_DPHY_CTRL_1_ENABLE_1_RESET 0x0
1589 +#define RPI_MIPICFG_DPHY_CTRL_1_ENABLE_1_BITS 0x00200000
1590 +#define RPI_MIPICFG_DPHY_CTRL_1_ENABLE_1_MSB 21
1591 +#define RPI_MIPICFG_DPHY_CTRL_1_ENABLE_1_LSB 21
1592 +#define RPI_MIPICFG_DPHY_CTRL_1_ENABLE_1_ACCESS "RW"
1593 +// --------------------------------------------------------------------------------
1594 +// Field : RPI_MIPICFG_DPHY_CTRL_1_ENABLE_0
1595 +// Description : None
1596 +#define RPI_MIPICFG_DPHY_CTRL_1_ENABLE_0_RESET 0x0
1597 +#define RPI_MIPICFG_DPHY_CTRL_1_ENABLE_0_BITS 0x00100000
1598 +#define RPI_MIPICFG_DPHY_CTRL_1_ENABLE_0_MSB 20
1599 +#define RPI_MIPICFG_DPHY_CTRL_1_ENABLE_0_LSB 20
1600 +#define RPI_MIPICFG_DPHY_CTRL_1_ENABLE_0_ACCESS "RW"
1601 +// --------------------------------------------------------------------------------
1602 +// Field : RPI_MIPICFG_DPHY_CTRL_1_BASEDIR_3
1603 +// Description : None
1604 +#define RPI_MIPICFG_DPHY_CTRL_1_BASEDIR_3_RESET 0x0
1605 +#define RPI_MIPICFG_DPHY_CTRL_1_BASEDIR_3_BITS 0x00080000
1606 +#define RPI_MIPICFG_DPHY_CTRL_1_BASEDIR_3_MSB 19
1607 +#define RPI_MIPICFG_DPHY_CTRL_1_BASEDIR_3_LSB 19
1608 +#define RPI_MIPICFG_DPHY_CTRL_1_BASEDIR_3_ACCESS "RW"
1609 +// --------------------------------------------------------------------------------
1610 +// Field : RPI_MIPICFG_DPHY_CTRL_1_BASEDIR_2
1611 +// Description : None
1612 +#define RPI_MIPICFG_DPHY_CTRL_1_BASEDIR_2_RESET 0x0
1613 +#define RPI_MIPICFG_DPHY_CTRL_1_BASEDIR_2_BITS 0x00040000
1614 +#define RPI_MIPICFG_DPHY_CTRL_1_BASEDIR_2_MSB 18
1615 +#define RPI_MIPICFG_DPHY_CTRL_1_BASEDIR_2_LSB 18
1616 +#define RPI_MIPICFG_DPHY_CTRL_1_BASEDIR_2_ACCESS "RW"
1617 +// --------------------------------------------------------------------------------
1618 +// Field : RPI_MIPICFG_DPHY_CTRL_1_BASEDIR_1
1619 +// Description : None
1620 +#define RPI_MIPICFG_DPHY_CTRL_1_BASEDIR_1_RESET 0x0
1621 +#define RPI_MIPICFG_DPHY_CTRL_1_BASEDIR_1_BITS 0x00020000
1622 +#define RPI_MIPICFG_DPHY_CTRL_1_BASEDIR_1_MSB 17
1623 +#define RPI_MIPICFG_DPHY_CTRL_1_BASEDIR_1_LSB 17
1624 +#define RPI_MIPICFG_DPHY_CTRL_1_BASEDIR_1_ACCESS "RW"
1625 +// --------------------------------------------------------------------------------
1626 +// Field : RPI_MIPICFG_DPHY_CTRL_1_BASEDIR_0
1627 +// Description : None
1628 +#define RPI_MIPICFG_DPHY_CTRL_1_BASEDIR_0_RESET 0x0
1629 +#define RPI_MIPICFG_DPHY_CTRL_1_BASEDIR_0_BITS 0x00010000
1630 +#define RPI_MIPICFG_DPHY_CTRL_1_BASEDIR_0_MSB 16
1631 +#define RPI_MIPICFG_DPHY_CTRL_1_BASEDIR_0_LSB 16
1632 +#define RPI_MIPICFG_DPHY_CTRL_1_BASEDIR_0_ACCESS "RW"
1633 +// --------------------------------------------------------------------------------
1634 +// Field : RPI_MIPICFG_DPHY_CTRL_1_TXLPDTESC_3
1635 +// Description : None
1636 +#define RPI_MIPICFG_DPHY_CTRL_1_TXLPDTESC_3_RESET 0x0
1637 +#define RPI_MIPICFG_DPHY_CTRL_1_TXLPDTESC_3_BITS 0x00008000
1638 +#define RPI_MIPICFG_DPHY_CTRL_1_TXLPDTESC_3_MSB 15
1639 +#define RPI_MIPICFG_DPHY_CTRL_1_TXLPDTESC_3_LSB 15
1640 +#define RPI_MIPICFG_DPHY_CTRL_1_TXLPDTESC_3_ACCESS "RW"
1641 +// --------------------------------------------------------------------------------
1642 +// Field : RPI_MIPICFG_DPHY_CTRL_1_TXLPDTESC_2
1643 +// Description : None
1644 +#define RPI_MIPICFG_DPHY_CTRL_1_TXLPDTESC_2_RESET 0x0
1645 +#define RPI_MIPICFG_DPHY_CTRL_1_TXLPDTESC_2_BITS 0x00004000
1646 +#define RPI_MIPICFG_DPHY_CTRL_1_TXLPDTESC_2_MSB 14
1647 +#define RPI_MIPICFG_DPHY_CTRL_1_TXLPDTESC_2_LSB 14
1648 +#define RPI_MIPICFG_DPHY_CTRL_1_TXLPDTESC_2_ACCESS "RW"
1649 +// --------------------------------------------------------------------------------
1650 +// Field : RPI_MIPICFG_DPHY_CTRL_1_TXLPDTESC_1
1651 +// Description : None
1652 +#define RPI_MIPICFG_DPHY_CTRL_1_TXLPDTESC_1_RESET 0x0
1653 +#define RPI_MIPICFG_DPHY_CTRL_1_TXLPDTESC_1_BITS 0x00002000
1654 +#define RPI_MIPICFG_DPHY_CTRL_1_TXLPDTESC_1_MSB 13
1655 +#define RPI_MIPICFG_DPHY_CTRL_1_TXLPDTESC_1_LSB 13
1656 +#define RPI_MIPICFG_DPHY_CTRL_1_TXLPDTESC_1_ACCESS "RW"
1657 +// --------------------------------------------------------------------------------
1658 +// Field : RPI_MIPICFG_DPHY_CTRL_1_TXLPDTESC_0
1659 +// Description : None
1660 +#define RPI_MIPICFG_DPHY_CTRL_1_TXLPDTESC_0_RESET 0x0
1661 +#define RPI_MIPICFG_DPHY_CTRL_1_TXLPDTESC_0_BITS 0x00001000
1662 +#define RPI_MIPICFG_DPHY_CTRL_1_TXLPDTESC_0_MSB 12
1663 +#define RPI_MIPICFG_DPHY_CTRL_1_TXLPDTESC_0_LSB 12
1664 +#define RPI_MIPICFG_DPHY_CTRL_1_TXLPDTESC_0_ACCESS "RW"
1665 +// --------------------------------------------------------------------------------
1666 +// Field : RPI_MIPICFG_DPHY_CTRL_1_TXVALIDESC_3
1667 +// Description : None
1668 +#define RPI_MIPICFG_DPHY_CTRL_1_TXVALIDESC_3_RESET 0x0
1669 +#define RPI_MIPICFG_DPHY_CTRL_1_TXVALIDESC_3_BITS 0x00000800
1670 +#define RPI_MIPICFG_DPHY_CTRL_1_TXVALIDESC_3_MSB 11
1671 +#define RPI_MIPICFG_DPHY_CTRL_1_TXVALIDESC_3_LSB 11
1672 +#define RPI_MIPICFG_DPHY_CTRL_1_TXVALIDESC_3_ACCESS "RW"
1673 +// --------------------------------------------------------------------------------
1674 +// Field : RPI_MIPICFG_DPHY_CTRL_1_TXVALIDESC_2
1675 +// Description : None
1676 +#define RPI_MIPICFG_DPHY_CTRL_1_TXVALIDESC_2_RESET 0x0
1677 +#define RPI_MIPICFG_DPHY_CTRL_1_TXVALIDESC_2_BITS 0x00000400
1678 +#define RPI_MIPICFG_DPHY_CTRL_1_TXVALIDESC_2_MSB 10
1679 +#define RPI_MIPICFG_DPHY_CTRL_1_TXVALIDESC_2_LSB 10
1680 +#define RPI_MIPICFG_DPHY_CTRL_1_TXVALIDESC_2_ACCESS "RW"
1681 +// --------------------------------------------------------------------------------
1682 +// Field : RPI_MIPICFG_DPHY_CTRL_1_TXVALIDESC_1
1683 +// Description : None
1684 +#define RPI_MIPICFG_DPHY_CTRL_1_TXVALIDESC_1_RESET 0x0
1685 +#define RPI_MIPICFG_DPHY_CTRL_1_TXVALIDESC_1_BITS 0x00000200
1686 +#define RPI_MIPICFG_DPHY_CTRL_1_TXVALIDESC_1_MSB 9
1687 +#define RPI_MIPICFG_DPHY_CTRL_1_TXVALIDESC_1_LSB 9
1688 +#define RPI_MIPICFG_DPHY_CTRL_1_TXVALIDESC_1_ACCESS "RW"
1689 +// --------------------------------------------------------------------------------
1690 +// Field : RPI_MIPICFG_DPHY_CTRL_1_TXVALIDESC_0
1691 +// Description : None
1692 +#define RPI_MIPICFG_DPHY_CTRL_1_TXVALIDESC_0_RESET 0x0
1693 +#define RPI_MIPICFG_DPHY_CTRL_1_TXVALIDESC_0_BITS 0x00000100
1694 +#define RPI_MIPICFG_DPHY_CTRL_1_TXVALIDESC_0_MSB 8
1695 +#define RPI_MIPICFG_DPHY_CTRL_1_TXVALIDESC_0_LSB 8
1696 +#define RPI_MIPICFG_DPHY_CTRL_1_TXVALIDESC_0_ACCESS "RW"
1697 +// --------------------------------------------------------------------------------
1698 +// Field : RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTESC_3
1699 +// Description : None
1700 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTESC_3_RESET 0x0
1701 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTESC_3_BITS 0x00000080
1702 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTESC_3_MSB 7
1703 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTESC_3_LSB 7
1704 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTESC_3_ACCESS "RW"
1705 +// --------------------------------------------------------------------------------
1706 +// Field : RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTESC_2
1707 +// Description : None
1708 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTESC_2_RESET 0x0
1709 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTESC_2_BITS 0x00000040
1710 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTESC_2_MSB 6
1711 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTESC_2_LSB 6
1712 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTESC_2_ACCESS "RW"
1713 +// --------------------------------------------------------------------------------
1714 +// Field : RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTESC_1
1715 +// Description : None
1716 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTESC_1_RESET 0x0
1717 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTESC_1_BITS 0x00000020
1718 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTESC_1_MSB 5
1719 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTESC_1_LSB 5
1720 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTESC_1_ACCESS "RW"
1721 +// --------------------------------------------------------------------------------
1722 +// Field : RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTESC_0
1723 +// Description : None
1724 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTESC_0_RESET 0x0
1725 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTESC_0_BITS 0x00000010
1726 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTESC_0_MSB 4
1727 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTESC_0_LSB 4
1728 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTESC_0_ACCESS "RW"
1729 +// --------------------------------------------------------------------------------
1730 +// Field : RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTDATAHS_3
1731 +// Description : None
1732 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTDATAHS_3_RESET 0x0
1733 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTDATAHS_3_BITS 0x00000008
1734 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTDATAHS_3_MSB 3
1735 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTDATAHS_3_LSB 3
1736 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTDATAHS_3_ACCESS "RW"
1737 +// --------------------------------------------------------------------------------
1738 +// Field : RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTDATAHS_2
1739 +// Description : None
1740 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTDATAHS_2_RESET 0x0
1741 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTDATAHS_2_BITS 0x00000004
1742 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTDATAHS_2_MSB 2
1743 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTDATAHS_2_LSB 2
1744 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTDATAHS_2_ACCESS "RW"
1745 +// --------------------------------------------------------------------------------
1746 +// Field : RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTDATAHS_1
1747 +// Description : None
1748 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTDATAHS_1_RESET 0x0
1749 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTDATAHS_1_BITS 0x00000002
1750 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTDATAHS_1_MSB 1
1751 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTDATAHS_1_LSB 1
1752 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTDATAHS_1_ACCESS "RW"
1753 +// --------------------------------------------------------------------------------
1754 +// Field : RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTDATAHS_0
1755 +// Description : None
1756 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTDATAHS_0_RESET 0x0
1757 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTDATAHS_0_BITS 0x00000001
1758 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTDATAHS_0_MSB 0
1759 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTDATAHS_0_LSB 0
1760 +#define RPI_MIPICFG_DPHY_CTRL_1_TXREQUESTDATAHS_0_ACCESS "RW"
1761 +// ================================================================================
1762 +// Register : RPI_MIPICFG_DPHY_CTRL_2
1763 +// JTAG access : asynchronous
1764 +// Description : DPHY control for analog DFT
1765 +#define RPI_MIPICFG_DPHY_CTRL_2_OFFSET 0x0000001c
1766 +#define RPI_MIPICFG_DPHY_CTRL_2_BITS 0x000007ff
1767 +#define RPI_MIPICFG_DPHY_CTRL_2_RESET 0x00000000
1768 +// --------------------------------------------------------------------------------
1769 +// Field : RPI_MIPICFG_DPHY_CTRL_2_TESTCLK
1770 +// Description : None
1771 +#define RPI_MIPICFG_DPHY_CTRL_2_TESTCLK_RESET 0x0
1772 +#define RPI_MIPICFG_DPHY_CTRL_2_TESTCLK_BITS 0x00000400
1773 +#define RPI_MIPICFG_DPHY_CTRL_2_TESTCLK_MSB 10
1774 +#define RPI_MIPICFG_DPHY_CTRL_2_TESTCLK_LSB 10
1775 +#define RPI_MIPICFG_DPHY_CTRL_2_TESTCLK_ACCESS "RW"
1776 +// --------------------------------------------------------------------------------
1777 +// Field : RPI_MIPICFG_DPHY_CTRL_2_TESTEN
1778 +// Description : None
1779 +#define RPI_MIPICFG_DPHY_CTRL_2_TESTEN_RESET 0x0
1780 +#define RPI_MIPICFG_DPHY_CTRL_2_TESTEN_BITS 0x00000200
1781 +#define RPI_MIPICFG_DPHY_CTRL_2_TESTEN_MSB 9
1782 +#define RPI_MIPICFG_DPHY_CTRL_2_TESTEN_LSB 9
1783 +#define RPI_MIPICFG_DPHY_CTRL_2_TESTEN_ACCESS "RW"
1784 +// --------------------------------------------------------------------------------
1785 +// Field : RPI_MIPICFG_DPHY_CTRL_2_TESTCLR
1786 +// Description : None
1787 +#define RPI_MIPICFG_DPHY_CTRL_2_TESTCLR_RESET 0x0
1788 +#define RPI_MIPICFG_DPHY_CTRL_2_TESTCLR_BITS 0x00000100
1789 +#define RPI_MIPICFG_DPHY_CTRL_2_TESTCLR_MSB 8
1790 +#define RPI_MIPICFG_DPHY_CTRL_2_TESTCLR_LSB 8
1791 +#define RPI_MIPICFG_DPHY_CTRL_2_TESTCLR_ACCESS "RW"
1792 +// --------------------------------------------------------------------------------
1793 +// Field : RPI_MIPICFG_DPHY_CTRL_2_TESTDIN
1794 +// Description : None
1795 +#define RPI_MIPICFG_DPHY_CTRL_2_TESTDIN_RESET 0x00
1796 +#define RPI_MIPICFG_DPHY_CTRL_2_TESTDIN_BITS 0x000000ff
1797 +#define RPI_MIPICFG_DPHY_CTRL_2_TESTDIN_MSB 7
1798 +#define RPI_MIPICFG_DPHY_CTRL_2_TESTDIN_LSB 0
1799 +#define RPI_MIPICFG_DPHY_CTRL_2_TESTDIN_ACCESS "RW"
1800 +// ================================================================================
1801 +// Register : RPI_MIPICFG_DPHY_CTRL_3
1802 +// JTAG access : asynchronous
1803 +// Description : DPHY control for analog DFT
1804 +#define RPI_MIPICFG_DPHY_CTRL_3_OFFSET 0x00000020
1805 +#define RPI_MIPICFG_DPHY_CTRL_3_BITS 0xffffffff
1806 +#define RPI_MIPICFG_DPHY_CTRL_3_RESET 0x00000000
1807 +// --------------------------------------------------------------------------------
1808 +// Field : RPI_MIPICFG_DPHY_CTRL_3_TXDATAESC_3
1809 +// Description : None
1810 +#define RPI_MIPICFG_DPHY_CTRL_3_TXDATAESC_3_RESET 0x00
1811 +#define RPI_MIPICFG_DPHY_CTRL_3_TXDATAESC_3_BITS 0xff000000
1812 +#define RPI_MIPICFG_DPHY_CTRL_3_TXDATAESC_3_MSB 31
1813 +#define RPI_MIPICFG_DPHY_CTRL_3_TXDATAESC_3_LSB 24
1814 +#define RPI_MIPICFG_DPHY_CTRL_3_TXDATAESC_3_ACCESS "RW"
1815 +// --------------------------------------------------------------------------------
1816 +// Field : RPI_MIPICFG_DPHY_CTRL_3_TXDATAESC_2
1817 +// Description : None
1818 +#define RPI_MIPICFG_DPHY_CTRL_3_TXDATAESC_2_RESET 0x00
1819 +#define RPI_MIPICFG_DPHY_CTRL_3_TXDATAESC_2_BITS 0x00ff0000
1820 +#define RPI_MIPICFG_DPHY_CTRL_3_TXDATAESC_2_MSB 23
1821 +#define RPI_MIPICFG_DPHY_CTRL_3_TXDATAESC_2_LSB 16
1822 +#define RPI_MIPICFG_DPHY_CTRL_3_TXDATAESC_2_ACCESS "RW"
1823 +// --------------------------------------------------------------------------------
1824 +// Field : RPI_MIPICFG_DPHY_CTRL_3_TXDATAESC_1
1825 +// Description : None
1826 +#define RPI_MIPICFG_DPHY_CTRL_3_TXDATAESC_1_RESET 0x00
1827 +#define RPI_MIPICFG_DPHY_CTRL_3_TXDATAESC_1_BITS 0x0000ff00
1828 +#define RPI_MIPICFG_DPHY_CTRL_3_TXDATAESC_1_MSB 15
1829 +#define RPI_MIPICFG_DPHY_CTRL_3_TXDATAESC_1_LSB 8
1830 +#define RPI_MIPICFG_DPHY_CTRL_3_TXDATAESC_1_ACCESS "RW"
1831 +// --------------------------------------------------------------------------------
1832 +// Field : RPI_MIPICFG_DPHY_CTRL_3_TXDATAESC_0
1833 +// Description : None
1834 +#define RPI_MIPICFG_DPHY_CTRL_3_TXDATAESC_0_RESET 0x00
1835 +#define RPI_MIPICFG_DPHY_CTRL_3_TXDATAESC_0_BITS 0x000000ff
1836 +#define RPI_MIPICFG_DPHY_CTRL_3_TXDATAESC_0_MSB 7
1837 +#define RPI_MIPICFG_DPHY_CTRL_3_TXDATAESC_0_LSB 0
1838 +#define RPI_MIPICFG_DPHY_CTRL_3_TXDATAESC_0_ACCESS "RW"
1839 +// ================================================================================
1840 +// Register : RPI_MIPICFG_DPHY_CTRL_4
1841 +// JTAG access : asynchronous
1842 +// Description : DPHY control for analog DFT
1843 +#define RPI_MIPICFG_DPHY_CTRL_4_OFFSET 0x00000024
1844 +#define RPI_MIPICFG_DPHY_CTRL_4_BITS 0xffffffff
1845 +#define RPI_MIPICFG_DPHY_CTRL_4_RESET 0x00000000
1846 +// --------------------------------------------------------------------------------
1847 +// Field : RPI_MIPICFG_DPHY_CTRL_4_TXDATAHS_3
1848 +// Description : None
1849 +#define RPI_MIPICFG_DPHY_CTRL_4_TXDATAHS_3_RESET 0x00
1850 +#define RPI_MIPICFG_DPHY_CTRL_4_TXDATAHS_3_BITS 0xff000000
1851 +#define RPI_MIPICFG_DPHY_CTRL_4_TXDATAHS_3_MSB 31
1852 +#define RPI_MIPICFG_DPHY_CTRL_4_TXDATAHS_3_LSB 24
1853 +#define RPI_MIPICFG_DPHY_CTRL_4_TXDATAHS_3_ACCESS "RW"
1854 +// --------------------------------------------------------------------------------
1855 +// Field : RPI_MIPICFG_DPHY_CTRL_4_TXDATAHS_2
1856 +// Description : None
1857 +#define RPI_MIPICFG_DPHY_CTRL_4_TXDATAHS_2_RESET 0x00
1858 +#define RPI_MIPICFG_DPHY_CTRL_4_TXDATAHS_2_BITS 0x00ff0000
1859 +#define RPI_MIPICFG_DPHY_CTRL_4_TXDATAHS_2_MSB 23
1860 +#define RPI_MIPICFG_DPHY_CTRL_4_TXDATAHS_2_LSB 16
1861 +#define RPI_MIPICFG_DPHY_CTRL_4_TXDATAHS_2_ACCESS "RW"
1862 +// --------------------------------------------------------------------------------
1863 +// Field : RPI_MIPICFG_DPHY_CTRL_4_TXDATAHS_1
1864 +// Description : None
1865 +#define RPI_MIPICFG_DPHY_CTRL_4_TXDATAHS_1_RESET 0x00
1866 +#define RPI_MIPICFG_DPHY_CTRL_4_TXDATAHS_1_BITS 0x0000ff00
1867 +#define RPI_MIPICFG_DPHY_CTRL_4_TXDATAHS_1_MSB 15
1868 +#define RPI_MIPICFG_DPHY_CTRL_4_TXDATAHS_1_LSB 8
1869 +#define RPI_MIPICFG_DPHY_CTRL_4_TXDATAHS_1_ACCESS "RW"
1870 +// --------------------------------------------------------------------------------
1871 +// Field : RPI_MIPICFG_DPHY_CTRL_4_TXDATAHS_0
1872 +// Description : None
1873 +#define RPI_MIPICFG_DPHY_CTRL_4_TXDATAHS_0_RESET 0x00
1874 +#define RPI_MIPICFG_DPHY_CTRL_4_TXDATAHS_0_BITS 0x000000ff
1875 +#define RPI_MIPICFG_DPHY_CTRL_4_TXDATAHS_0_MSB 7
1876 +#define RPI_MIPICFG_DPHY_CTRL_4_TXDATAHS_0_LSB 0
1877 +#define RPI_MIPICFG_DPHY_CTRL_4_TXDATAHS_0_ACCESS "RW"
1878 +// ================================================================================
1879 +// Register : RPI_MIPICFG_INTR
1880 +// JTAG access : synchronous
1881 +// Description : Raw Interrupts
1882 +#define RPI_MIPICFG_INTR_OFFSET 0x00000028
1883 +#define RPI_MIPICFG_INTR_BITS 0x0000000f
1884 +#define RPI_MIPICFG_INTR_RESET 0x00000000
1885 +// --------------------------------------------------------------------------------
1886 +// Field : RPI_MIPICFG_INTR_DSI_HOST
1887 +// Description : None
1888 +#define RPI_MIPICFG_INTR_DSI_HOST_RESET 0x0
1889 +#define RPI_MIPICFG_INTR_DSI_HOST_BITS 0x00000008
1890 +#define RPI_MIPICFG_INTR_DSI_HOST_MSB 3
1891 +#define RPI_MIPICFG_INTR_DSI_HOST_LSB 3
1892 +#define RPI_MIPICFG_INTR_DSI_HOST_ACCESS "RO"
1893 +// --------------------------------------------------------------------------------
1894 +// Field : RPI_MIPICFG_INTR_CSI_HOST
1895 +// Description : None
1896 +#define RPI_MIPICFG_INTR_CSI_HOST_RESET 0x0
1897 +#define RPI_MIPICFG_INTR_CSI_HOST_BITS 0x00000004
1898 +#define RPI_MIPICFG_INTR_CSI_HOST_MSB 2
1899 +#define RPI_MIPICFG_INTR_CSI_HOST_LSB 2
1900 +#define RPI_MIPICFG_INTR_CSI_HOST_ACCESS "RO"
1901 +// --------------------------------------------------------------------------------
1902 +// Field : RPI_MIPICFG_INTR_DSI_DMA
1903 +// Description : None
1904 +#define RPI_MIPICFG_INTR_DSI_DMA_RESET 0x0
1905 +#define RPI_MIPICFG_INTR_DSI_DMA_BITS 0x00000002
1906 +#define RPI_MIPICFG_INTR_DSI_DMA_MSB 1
1907 +#define RPI_MIPICFG_INTR_DSI_DMA_LSB 1
1908 +#define RPI_MIPICFG_INTR_DSI_DMA_ACCESS "RO"
1909 +// --------------------------------------------------------------------------------
1910 +// Field : RPI_MIPICFG_INTR_CSI_DMA
1911 +// Description : None
1912 +#define RPI_MIPICFG_INTR_CSI_DMA_RESET 0x0
1913 +#define RPI_MIPICFG_INTR_CSI_DMA_BITS 0x00000001
1914 +#define RPI_MIPICFG_INTR_CSI_DMA_MSB 0
1915 +#define RPI_MIPICFG_INTR_CSI_DMA_LSB 0
1916 +#define RPI_MIPICFG_INTR_CSI_DMA_ACCESS "RO"
1917 +// ================================================================================
1918 +// Register : RPI_MIPICFG_INTE
1919 +// JTAG access : synchronous
1920 +// Description : Interrupt Enable
1921 +#define RPI_MIPICFG_INTE_OFFSET 0x0000002c
1922 +#define RPI_MIPICFG_INTE_BITS 0x0000000f
1923 +#define RPI_MIPICFG_INTE_RESET 0x00000000
1924 +// --------------------------------------------------------------------------------
1925 +// Field : RPI_MIPICFG_INTE_DSI_HOST
1926 +// Description : None
1927 +#define RPI_MIPICFG_INTE_DSI_HOST_RESET 0x0
1928 +#define RPI_MIPICFG_INTE_DSI_HOST_BITS 0x00000008
1929 +#define RPI_MIPICFG_INTE_DSI_HOST_MSB 3
1930 +#define RPI_MIPICFG_INTE_DSI_HOST_LSB 3
1931 +#define RPI_MIPICFG_INTE_DSI_HOST_ACCESS "RW"
1932 +// --------------------------------------------------------------------------------
1933 +// Field : RPI_MIPICFG_INTE_CSI_HOST
1934 +// Description : None
1935 +#define RPI_MIPICFG_INTE_CSI_HOST_RESET 0x0
1936 +#define RPI_MIPICFG_INTE_CSI_HOST_BITS 0x00000004
1937 +#define RPI_MIPICFG_INTE_CSI_HOST_MSB 2
1938 +#define RPI_MIPICFG_INTE_CSI_HOST_LSB 2
1939 +#define RPI_MIPICFG_INTE_CSI_HOST_ACCESS "RW"
1940 +// --------------------------------------------------------------------------------
1941 +// Field : RPI_MIPICFG_INTE_DSI_DMA
1942 +// Description : None
1943 +#define RPI_MIPICFG_INTE_DSI_DMA_RESET 0x0
1944 +#define RPI_MIPICFG_INTE_DSI_DMA_BITS 0x00000002
1945 +#define RPI_MIPICFG_INTE_DSI_DMA_MSB 1
1946 +#define RPI_MIPICFG_INTE_DSI_DMA_LSB 1
1947 +#define RPI_MIPICFG_INTE_DSI_DMA_ACCESS "RW"
1948 +// --------------------------------------------------------------------------------
1949 +// Field : RPI_MIPICFG_INTE_CSI_DMA
1950 +// Description : None
1951 +#define RPI_MIPICFG_INTE_CSI_DMA_RESET 0x0
1952 +#define RPI_MIPICFG_INTE_CSI_DMA_BITS 0x00000001
1953 +#define RPI_MIPICFG_INTE_CSI_DMA_MSB 0
1954 +#define RPI_MIPICFG_INTE_CSI_DMA_LSB 0
1955 +#define RPI_MIPICFG_INTE_CSI_DMA_ACCESS "RW"
1956 +// ================================================================================
1957 +// Register : RPI_MIPICFG_INTF
1958 +// JTAG access : synchronous
1959 +// Description : Interrupt Force
1960 +#define RPI_MIPICFG_INTF_OFFSET 0x00000030
1961 +#define RPI_MIPICFG_INTF_BITS 0x0000000f
1962 +#define RPI_MIPICFG_INTF_RESET 0x00000000
1963 +// --------------------------------------------------------------------------------
1964 +// Field : RPI_MIPICFG_INTF_DSI_HOST
1965 +// Description : None
1966 +#define RPI_MIPICFG_INTF_DSI_HOST_RESET 0x0
1967 +#define RPI_MIPICFG_INTF_DSI_HOST_BITS 0x00000008
1968 +#define RPI_MIPICFG_INTF_DSI_HOST_MSB 3
1969 +#define RPI_MIPICFG_INTF_DSI_HOST_LSB 3
1970 +#define RPI_MIPICFG_INTF_DSI_HOST_ACCESS "RW"
1971 +// --------------------------------------------------------------------------------
1972 +// Field : RPI_MIPICFG_INTF_CSI_HOST
1973 +// Description : None
1974 +#define RPI_MIPICFG_INTF_CSI_HOST_RESET 0x0
1975 +#define RPI_MIPICFG_INTF_CSI_HOST_BITS 0x00000004
1976 +#define RPI_MIPICFG_INTF_CSI_HOST_MSB 2
1977 +#define RPI_MIPICFG_INTF_CSI_HOST_LSB 2
1978 +#define RPI_MIPICFG_INTF_CSI_HOST_ACCESS "RW"
1979 +// --------------------------------------------------------------------------------
1980 +// Field : RPI_MIPICFG_INTF_DSI_DMA
1981 +// Description : None
1982 +#define RPI_MIPICFG_INTF_DSI_DMA_RESET 0x0
1983 +#define RPI_MIPICFG_INTF_DSI_DMA_BITS 0x00000002
1984 +#define RPI_MIPICFG_INTF_DSI_DMA_MSB 1
1985 +#define RPI_MIPICFG_INTF_DSI_DMA_LSB 1
1986 +#define RPI_MIPICFG_INTF_DSI_DMA_ACCESS "RW"
1987 +// --------------------------------------------------------------------------------
1988 +// Field : RPI_MIPICFG_INTF_CSI_DMA
1989 +// Description : None
1990 +#define RPI_MIPICFG_INTF_CSI_DMA_RESET 0x0
1991 +#define RPI_MIPICFG_INTF_CSI_DMA_BITS 0x00000001
1992 +#define RPI_MIPICFG_INTF_CSI_DMA_MSB 0
1993 +#define RPI_MIPICFG_INTF_CSI_DMA_LSB 0
1994 +#define RPI_MIPICFG_INTF_CSI_DMA_ACCESS "RW"
1995 +// ================================================================================
1996 +// Register : RPI_MIPICFG_INTS
1997 +// JTAG access : synchronous
1998 +// Description : Interrupt status after masking & forcing
1999 +#define RPI_MIPICFG_INTS_OFFSET 0x00000034
2000 +#define RPI_MIPICFG_INTS_BITS 0x0000000f
2001 +#define RPI_MIPICFG_INTS_RESET 0x00000000
2002 +// --------------------------------------------------------------------------------
2003 +// Field : RPI_MIPICFG_INTS_DSI_HOST
2004 +// Description : None
2005 +#define RPI_MIPICFG_INTS_DSI_HOST_RESET 0x0
2006 +#define RPI_MIPICFG_INTS_DSI_HOST_BITS 0x00000008
2007 +#define RPI_MIPICFG_INTS_DSI_HOST_MSB 3
2008 +#define RPI_MIPICFG_INTS_DSI_HOST_LSB 3
2009 +#define RPI_MIPICFG_INTS_DSI_HOST_ACCESS "RO"
2010 +// --------------------------------------------------------------------------------
2011 +// Field : RPI_MIPICFG_INTS_CSI_HOST
2012 +// Description : None
2013 +#define RPI_MIPICFG_INTS_CSI_HOST_RESET 0x0
2014 +#define RPI_MIPICFG_INTS_CSI_HOST_BITS 0x00000004
2015 +#define RPI_MIPICFG_INTS_CSI_HOST_MSB 2
2016 +#define RPI_MIPICFG_INTS_CSI_HOST_LSB 2
2017 +#define RPI_MIPICFG_INTS_CSI_HOST_ACCESS "RO"
2018 +// --------------------------------------------------------------------------------
2019 +// Field : RPI_MIPICFG_INTS_DSI_DMA
2020 +// Description : None
2021 +#define RPI_MIPICFG_INTS_DSI_DMA_RESET 0x0
2022 +#define RPI_MIPICFG_INTS_DSI_DMA_BITS 0x00000002
2023 +#define RPI_MIPICFG_INTS_DSI_DMA_MSB 1
2024 +#define RPI_MIPICFG_INTS_DSI_DMA_LSB 1
2025 +#define RPI_MIPICFG_INTS_DSI_DMA_ACCESS "RO"
2026 +// --------------------------------------------------------------------------------
2027 +// Field : RPI_MIPICFG_INTS_CSI_DMA
2028 +// Description : None
2029 +#define RPI_MIPICFG_INTS_CSI_DMA_RESET 0x0
2030 +#define RPI_MIPICFG_INTS_CSI_DMA_BITS 0x00000001
2031 +#define RPI_MIPICFG_INTS_CSI_DMA_MSB 0
2032 +#define RPI_MIPICFG_INTS_CSI_DMA_LSB 0
2033 +#define RPI_MIPICFG_INTS_CSI_DMA_ACCESS "RO"
2034 +// ================================================================================
2035 +// Register : RPI_MIPICFG_BLOCK_ID
2036 +// JTAG access : asynchronous
2037 +// Description : Block Identifier
2038 +#define RPI_MIPICFG_BLOCK_ID_OFFSET 0x00000038
2039 +#define RPI_MIPICFG_BLOCK_ID_BITS 0xffffffff
2040 +#define RPI_MIPICFG_BLOCK_ID_RESET 0x4d495049
2041 +#define RPI_MIPICFG_BLOCK_ID_MSB 31
2042 +#define RPI_MIPICFG_BLOCK_ID_LSB 0
2043 +#define RPI_MIPICFG_BLOCK_ID_ACCESS "RO"
2044 +// ================================================================================
2045 +// Register : RPI_MIPICFG_INSTANCE_ID
2046 +// JTAG access : asynchronous
2047 +// Description : Block Instance Identifier
2048 +#define RPI_MIPICFG_INSTANCE_ID_OFFSET 0x0000003c
2049 +#define RPI_MIPICFG_INSTANCE_ID_BITS 0x0000000f
2050 +#define RPI_MIPICFG_INSTANCE_ID_RESET 0x00000000
2051 +#define RPI_MIPICFG_INSTANCE_ID_MSB 3
2052 +#define RPI_MIPICFG_INSTANCE_ID_LSB 0
2053 +#define RPI_MIPICFG_INSTANCE_ID_ACCESS "RO"
2054 +// ================================================================================
2055 +// Register : RPI_MIPICFG_RSTSEQ_AUTO
2056 +// JTAG access : synchronous
2057 +// Description : None
2058 +#define RPI_MIPICFG_RSTSEQ_AUTO_OFFSET 0x00000040
2059 +#define RPI_MIPICFG_RSTSEQ_AUTO_BITS 0x00000007
2060 +#define RPI_MIPICFG_RSTSEQ_AUTO_RESET 0x00000007
2061 +// --------------------------------------------------------------------------------
2062 +// Field : RPI_MIPICFG_RSTSEQ_AUTO_CSI
2063 +// Description : 1 = reset is controlled by the sequencer
2064 +// 0 = reset is controlled by rstseq_ctrl
2065 +#define RPI_MIPICFG_RSTSEQ_AUTO_CSI_RESET 0x1
2066 +#define RPI_MIPICFG_RSTSEQ_AUTO_CSI_BITS 0x00000004
2067 +#define RPI_MIPICFG_RSTSEQ_AUTO_CSI_MSB 2
2068 +#define RPI_MIPICFG_RSTSEQ_AUTO_CSI_LSB 2
2069 +#define RPI_MIPICFG_RSTSEQ_AUTO_CSI_ACCESS "RW"
2070 +// --------------------------------------------------------------------------------
2071 +// Field : RPI_MIPICFG_RSTSEQ_AUTO_DPI
2072 +// Description : 1 = reset is controlled by the sequencer
2073 +// 0 = reset is controlled by rstseq_ctrl
2074 +#define RPI_MIPICFG_RSTSEQ_AUTO_DPI_RESET 0x1
2075 +#define RPI_MIPICFG_RSTSEQ_AUTO_DPI_BITS 0x00000002
2076 +#define RPI_MIPICFG_RSTSEQ_AUTO_DPI_MSB 1
2077 +#define RPI_MIPICFG_RSTSEQ_AUTO_DPI_LSB 1
2078 +#define RPI_MIPICFG_RSTSEQ_AUTO_DPI_ACCESS "RW"
2079 +// --------------------------------------------------------------------------------
2080 +// Field : RPI_MIPICFG_RSTSEQ_AUTO_BUSADAPTER
2081 +// Description : 1 = reset is controlled by the sequencer
2082 +// 0 = reset is controlled by rstseq_ctrl
2083 +#define RPI_MIPICFG_RSTSEQ_AUTO_BUSADAPTER_RESET 0x1
2084 +#define RPI_MIPICFG_RSTSEQ_AUTO_BUSADAPTER_BITS 0x00000001
2085 +#define RPI_MIPICFG_RSTSEQ_AUTO_BUSADAPTER_MSB 0
2086 +#define RPI_MIPICFG_RSTSEQ_AUTO_BUSADAPTER_LSB 0
2087 +#define RPI_MIPICFG_RSTSEQ_AUTO_BUSADAPTER_ACCESS "RW"
2088 +// ================================================================================
2089 +// Register : RPI_MIPICFG_RSTSEQ_PARALLEL
2090 +// JTAG access : synchronous
2091 +// Description : None
2092 +#define RPI_MIPICFG_RSTSEQ_PARALLEL_OFFSET 0x00000044
2093 +#define RPI_MIPICFG_RSTSEQ_PARALLEL_BITS 0x00000007
2094 +#define RPI_MIPICFG_RSTSEQ_PARALLEL_RESET 0x00000006
2095 +// --------------------------------------------------------------------------------
2096 +// Field : RPI_MIPICFG_RSTSEQ_PARALLEL_CSI
2097 +// Description : Is this reset parallel (i.e. not part of the sequence)
2098 +#define RPI_MIPICFG_RSTSEQ_PARALLEL_CSI_RESET 0x1
2099 +#define RPI_MIPICFG_RSTSEQ_PARALLEL_CSI_BITS 0x00000004
2100 +#define RPI_MIPICFG_RSTSEQ_PARALLEL_CSI_MSB 2
2101 +#define RPI_MIPICFG_RSTSEQ_PARALLEL_CSI_LSB 2
2102 +#define RPI_MIPICFG_RSTSEQ_PARALLEL_CSI_ACCESS "RO"
2103 +// --------------------------------------------------------------------------------
2104 +// Field : RPI_MIPICFG_RSTSEQ_PARALLEL_DPI
2105 +// Description : Is this reset parallel (i.e. not part of the sequence)
2106 +#define RPI_MIPICFG_RSTSEQ_PARALLEL_DPI_RESET 0x1
2107 +#define RPI_MIPICFG_RSTSEQ_PARALLEL_DPI_BITS 0x00000002
2108 +#define RPI_MIPICFG_RSTSEQ_PARALLEL_DPI_MSB 1
2109 +#define RPI_MIPICFG_RSTSEQ_PARALLEL_DPI_LSB 1
2110 +#define RPI_MIPICFG_RSTSEQ_PARALLEL_DPI_ACCESS "RO"
2111 +// --------------------------------------------------------------------------------
2112 +// Field : RPI_MIPICFG_RSTSEQ_PARALLEL_BUSADAPTER
2113 +// Description : Is this reset parallel (i.e. not part of the sequence)
2114 +#define RPI_MIPICFG_RSTSEQ_PARALLEL_BUSADAPTER_RESET 0x0
2115 +#define RPI_MIPICFG_RSTSEQ_PARALLEL_BUSADAPTER_BITS 0x00000001
2116 +#define RPI_MIPICFG_RSTSEQ_PARALLEL_BUSADAPTER_MSB 0
2117 +#define RPI_MIPICFG_RSTSEQ_PARALLEL_BUSADAPTER_LSB 0
2118 +#define RPI_MIPICFG_RSTSEQ_PARALLEL_BUSADAPTER_ACCESS "RO"
2119 +// ================================================================================
2120 +// Register : RPI_MIPICFG_RSTSEQ_CTRL
2121 +// JTAG access : synchronous
2122 +// Description : None
2123 +#define RPI_MIPICFG_RSTSEQ_CTRL_OFFSET 0x00000048
2124 +#define RPI_MIPICFG_RSTSEQ_CTRL_BITS 0x00000007
2125 +#define RPI_MIPICFG_RSTSEQ_CTRL_RESET 0x00000000
2126 +// --------------------------------------------------------------------------------
2127 +// Field : RPI_MIPICFG_RSTSEQ_CTRL_CSI
2128 +// Description : 1 = keep the reset asserted
2129 +// 0 = keep the reset deasserted
2130 +// This is ignored if rstseq_auto=1
2131 +#define RPI_MIPICFG_RSTSEQ_CTRL_CSI_RESET 0x0
2132 +#define RPI_MIPICFG_RSTSEQ_CTRL_CSI_BITS 0x00000004
2133 +#define RPI_MIPICFG_RSTSEQ_CTRL_CSI_MSB 2
2134 +#define RPI_MIPICFG_RSTSEQ_CTRL_CSI_LSB 2
2135 +#define RPI_MIPICFG_RSTSEQ_CTRL_CSI_ACCESS "RW"
2136 +// --------------------------------------------------------------------------------
2137 +// Field : RPI_MIPICFG_RSTSEQ_CTRL_DPI
2138 +// Description : 1 = keep the reset asserted
2139 +// 0 = keep the reset deasserted
2140 +// This is ignored if rstseq_auto=1
2141 +#define RPI_MIPICFG_RSTSEQ_CTRL_DPI_RESET 0x0
2142 +#define RPI_MIPICFG_RSTSEQ_CTRL_DPI_BITS 0x00000002
2143 +#define RPI_MIPICFG_RSTSEQ_CTRL_DPI_MSB 1
2144 +#define RPI_MIPICFG_RSTSEQ_CTRL_DPI_LSB 1
2145 +#define RPI_MIPICFG_RSTSEQ_CTRL_DPI_ACCESS "RW"
2146 +// --------------------------------------------------------------------------------
2147 +// Field : RPI_MIPICFG_RSTSEQ_CTRL_BUSADAPTER
2148 +// Description : 1 = keep the reset asserted
2149 +// 0 = keep the reset deasserted
2150 +// This is ignored if rstseq_auto=1
2151 +#define RPI_MIPICFG_RSTSEQ_CTRL_BUSADAPTER_RESET 0x0
2152 +#define RPI_MIPICFG_RSTSEQ_CTRL_BUSADAPTER_BITS 0x00000001
2153 +#define RPI_MIPICFG_RSTSEQ_CTRL_BUSADAPTER_MSB 0
2154 +#define RPI_MIPICFG_RSTSEQ_CTRL_BUSADAPTER_LSB 0
2155 +#define RPI_MIPICFG_RSTSEQ_CTRL_BUSADAPTER_ACCESS "RW"
2156 +// ================================================================================
2157 +// Register : RPI_MIPICFG_RSTSEQ_TRIG
2158 +// JTAG access : synchronous
2159 +// Description : None
2160 +#define RPI_MIPICFG_RSTSEQ_TRIG_OFFSET 0x0000004c
2161 +#define RPI_MIPICFG_RSTSEQ_TRIG_BITS 0x00000007
2162 +#define RPI_MIPICFG_RSTSEQ_TRIG_RESET 0x00000000
2163 +// --------------------------------------------------------------------------------
2164 +// Field : RPI_MIPICFG_RSTSEQ_TRIG_CSI
2165 +// Description : Pulses the reset output
2166 +#define RPI_MIPICFG_RSTSEQ_TRIG_CSI_RESET 0x0
2167 +#define RPI_MIPICFG_RSTSEQ_TRIG_CSI_BITS 0x00000004
2168 +#define RPI_MIPICFG_RSTSEQ_TRIG_CSI_MSB 2
2169 +#define RPI_MIPICFG_RSTSEQ_TRIG_CSI_LSB 2
2170 +#define RPI_MIPICFG_RSTSEQ_TRIG_CSI_ACCESS "SC"
2171 +// --------------------------------------------------------------------------------
2172 +// Field : RPI_MIPICFG_RSTSEQ_TRIG_DPI
2173 +// Description : Pulses the reset output
2174 +#define RPI_MIPICFG_RSTSEQ_TRIG_DPI_RESET 0x0
2175 +#define RPI_MIPICFG_RSTSEQ_TRIG_DPI_BITS 0x00000002
2176 +#define RPI_MIPICFG_RSTSEQ_TRIG_DPI_MSB 1
2177 +#define RPI_MIPICFG_RSTSEQ_TRIG_DPI_LSB 1
2178 +#define RPI_MIPICFG_RSTSEQ_TRIG_DPI_ACCESS "SC"
2179 +// --------------------------------------------------------------------------------
2180 +// Field : RPI_MIPICFG_RSTSEQ_TRIG_BUSADAPTER
2181 +// Description : Pulses the reset output
2182 +#define RPI_MIPICFG_RSTSEQ_TRIG_BUSADAPTER_RESET 0x0
2183 +#define RPI_MIPICFG_RSTSEQ_TRIG_BUSADAPTER_BITS 0x00000001
2184 +#define RPI_MIPICFG_RSTSEQ_TRIG_BUSADAPTER_MSB 0
2185 +#define RPI_MIPICFG_RSTSEQ_TRIG_BUSADAPTER_LSB 0
2186 +#define RPI_MIPICFG_RSTSEQ_TRIG_BUSADAPTER_ACCESS "SC"
2187 +// ================================================================================
2188 +// Register : RPI_MIPICFG_RSTSEQ_DONE
2189 +// JTAG access : synchronous
2190 +// Description : None
2191 +#define RPI_MIPICFG_RSTSEQ_DONE_OFFSET 0x00000050
2192 +#define RPI_MIPICFG_RSTSEQ_DONE_BITS 0x00000007
2193 +#define RPI_MIPICFG_RSTSEQ_DONE_RESET 0x00000000
2194 +// --------------------------------------------------------------------------------
2195 +// Field : RPI_MIPICFG_RSTSEQ_DONE_CSI
2196 +// Description : Indicates the current state of the reset
2197 +#define RPI_MIPICFG_RSTSEQ_DONE_CSI_RESET 0x0
2198 +#define RPI_MIPICFG_RSTSEQ_DONE_CSI_BITS 0x00000004
2199 +#define RPI_MIPICFG_RSTSEQ_DONE_CSI_MSB 2
2200 +#define RPI_MIPICFG_RSTSEQ_DONE_CSI_LSB 2
2201 +#define RPI_MIPICFG_RSTSEQ_DONE_CSI_ACCESS "RO"
2202 +// --------------------------------------------------------------------------------
2203 +// Field : RPI_MIPICFG_RSTSEQ_DONE_DPI
2204 +// Description : Indicates the current state of the reset
2205 +#define RPI_MIPICFG_RSTSEQ_DONE_DPI_RESET 0x0
2206 +#define RPI_MIPICFG_RSTSEQ_DONE_DPI_BITS 0x00000002
2207 +#define RPI_MIPICFG_RSTSEQ_DONE_DPI_MSB 1
2208 +#define RPI_MIPICFG_RSTSEQ_DONE_DPI_LSB 1
2209 +#define RPI_MIPICFG_RSTSEQ_DONE_DPI_ACCESS "RO"
2210 +// --------------------------------------------------------------------------------
2211 +// Field : RPI_MIPICFG_RSTSEQ_DONE_BUSADAPTER
2212 +// Description : Indicates the current state of the reset
2213 +#define RPI_MIPICFG_RSTSEQ_DONE_BUSADAPTER_RESET 0x0
2214 +#define RPI_MIPICFG_RSTSEQ_DONE_BUSADAPTER_BITS 0x00000001
2215 +#define RPI_MIPICFG_RSTSEQ_DONE_BUSADAPTER_MSB 0
2216 +#define RPI_MIPICFG_RSTSEQ_DONE_BUSADAPTER_LSB 0
2217 +#define RPI_MIPICFG_RSTSEQ_DONE_BUSADAPTER_ACCESS "RO"
2218 +// ================================================================================
2219 +// Register : RPI_MIPICFG_DFTSS
2220 +// JTAG access : asynchronous
2221 +// Description : None
2222 +#define RPI_MIPICFG_DFTSS_OFFSET 0x00000054
2223 +#define RPI_MIPICFG_DFTSS_BITS 0x0000001f
2224 +#define RPI_MIPICFG_DFTSS_RESET 0x00000000
2225 +// --------------------------------------------------------------------------------
2226 +// Field : RPI_MIPICFG_DFTSS_JTAG_COPY
2227 +// Description : None
2228 +#define RPI_MIPICFG_DFTSS_JTAG_COPY_RESET 0x0
2229 +#define RPI_MIPICFG_DFTSS_JTAG_COPY_BITS 0x00000010
2230 +#define RPI_MIPICFG_DFTSS_JTAG_COPY_MSB 4
2231 +#define RPI_MIPICFG_DFTSS_JTAG_COPY_LSB 4
2232 +#define RPI_MIPICFG_DFTSS_JTAG_COPY_ACCESS "RW"
2233 +// --------------------------------------------------------------------------------
2234 +// Field : RPI_MIPICFG_DFTSS_JTAG_ACCESS_ONLY
2235 +// Description : None
2236 +#define RPI_MIPICFG_DFTSS_JTAG_ACCESS_ONLY_RESET 0x0
2237 +#define RPI_MIPICFG_DFTSS_JTAG_ACCESS_ONLY_BITS 0x00000008
2238 +#define RPI_MIPICFG_DFTSS_JTAG_ACCESS_ONLY_MSB 3
2239 +#define RPI_MIPICFG_DFTSS_JTAG_ACCESS_ONLY_LSB 3
2240 +#define RPI_MIPICFG_DFTSS_JTAG_ACCESS_ONLY_ACCESS "RW"
2241 +// --------------------------------------------------------------------------------
2242 +// Field : RPI_MIPICFG_DFTSS_BYPASS_OUTSYNCS
2243 +// Description : None
2244 +#define RPI_MIPICFG_DFTSS_BYPASS_OUTSYNCS_RESET 0x0
2245 +#define RPI_MIPICFG_DFTSS_BYPASS_OUTSYNCS_BITS 0x00000004
2246 +#define RPI_MIPICFG_DFTSS_BYPASS_OUTSYNCS_MSB 2
2247 +#define RPI_MIPICFG_DFTSS_BYPASS_OUTSYNCS_LSB 2
2248 +#define RPI_MIPICFG_DFTSS_BYPASS_OUTSYNCS_ACCESS "RW"
2249 +// --------------------------------------------------------------------------------
2250 +// Field : RPI_MIPICFG_DFTSS_BYPASS_INSYNCS
2251 +// Description : None
2252 +#define RPI_MIPICFG_DFTSS_BYPASS_INSYNCS_RESET 0x0
2253 +#define RPI_MIPICFG_DFTSS_BYPASS_INSYNCS_BITS 0x00000002
2254 +#define RPI_MIPICFG_DFTSS_BYPASS_INSYNCS_MSB 1
2255 +#define RPI_MIPICFG_DFTSS_BYPASS_INSYNCS_LSB 1
2256 +#define RPI_MIPICFG_DFTSS_BYPASS_INSYNCS_ACCESS "RW"
2257 +// --------------------------------------------------------------------------------
2258 +// Field : RPI_MIPICFG_DFTSS_BYPASS_RESETSYNCS
2259 +// Description : None
2260 +#define RPI_MIPICFG_DFTSS_BYPASS_RESETSYNCS_RESET 0x0
2261 +#define RPI_MIPICFG_DFTSS_BYPASS_RESETSYNCS_BITS 0x00000001
2262 +#define RPI_MIPICFG_DFTSS_BYPASS_RESETSYNCS_MSB 0
2263 +#define RPI_MIPICFG_DFTSS_BYPASS_RESETSYNCS_LSB 0
2264 +#define RPI_MIPICFG_DFTSS_BYPASS_RESETSYNCS_ACCESS "RW"
2265 +
2266 +#define CFG_WRITE(reg, val) writel((val), dsi->hw_base[RP1DSI_HW_BLOCK_CFG] + (reg ## _OFFSET))
2267 +#define CFG_READ(reg) readl(dsi->hw_base[RP1DSI_HW_BLOCK_CFG] + (reg ## _OFFSET))
2268 +
2269 +/* ------------------------------- DPHY setup stuff ------------------------ */
2270 +
2271 +static void dphy_transaction(struct rp1_dsi *dsi, uint8_t test_code, uint8_t test_data)
2272 +{
2273 + /*
2274 + * See pg 101 of mipi dphy bidir databook
2275 + * Assume we start with testclk high.
2276 + * Each APB write takes at least 10ns and we ignore TESTDOUT
2277 + * so there is no need for extra delays between the transitions.
2278 + */
2279 + u32 tmp;
2280 +
2281 + DSI_WRITE(DSI_PHY_TST_CTRL1, test_code | DPHY_CTRL1_PHY_TESTEN_BITS);
2282 + DSI_WRITE(DSI_PHY_TST_CTRL0, 0);
2283 + tmp = (DSI_READ(DSI_PHY_TST_CTRL1) >> DPHY_CTRL1_PHY_TESTDOUT_LSB) & 0xFF;
2284 + DSI_WRITE(DSI_PHY_TST_CTRL1, test_data);
2285 + DSI_WRITE(DSI_PHY_TST_CTRL0, DPHY_CTRL0_PHY_TESTCLK_BITS);
2286 +}
2287 +
2288 +static uint8_t dphy_get_div(u32 refclk_khz, u32 vco_freq_khz, u32 *ptr_m, u32 *ptr_n)
2289 +{
2290 + /*
2291 + * See pg 77-78 of dphy databook
2292 + * fvco = m/n * refclk
2293 + * with the limit
2294 + * 40MHz >= fREFCLK / N >= 5MHz
2295 + * M (multiplier) must be an even number between 2 and 300
2296 + * N (input divider) must be an integer between 1 and 100
2297 + *
2298 + * In practice, given a 50MHz reference clock, it can produce any
2299 + * multiple of 10MHz, 11.1111MHz, 12.5MHz, 14.286MHz or 16.667MHz
2300 + * with < 1% error for all frequencies above 495MHz.
2301 + */
2302 +
2303 + static const u32 REF_DIVN_MAX = 40000u;
2304 + static const u32 REF_DIVN_MIN = 5000u;
2305 + u32 best_n, best_m, best_err = 0x7fffffff;
2306 + unsigned int n;
2307 +
2308 + for (n = 1 + refclk_khz / REF_DIVN_MAX; n * REF_DIVN_MIN <= refclk_khz && n < 100; ++n) {
2309 + u32 half_m = (n * vco_freq_khz + refclk_khz) / (2 * refclk_khz);
2310 +
2311 + if (half_m < 150) {
2312 + u32 f = (2 * half_m * refclk_khz) / n;
2313 + u32 err = (f > vco_freq_khz) ? f - vco_freq_khz : vco_freq_khz - f;
2314 +
2315 + if (err < best_err) {
2316 + best_n = n;
2317 + best_m = 2 * half_m;
2318 + best_err = err;
2319 + if (err == 0)
2320 + break;
2321 + }
2322 + }
2323 + }
2324 +
2325 + if (64 * best_err < vco_freq_khz) { /* tolerate small error */
2326 + *ptr_n = best_n;
2327 + *ptr_m = best_m;
2328 + return 1;
2329 + }
2330 + return 0;
2331 +}
2332 +
2333 +struct hsfreq_range {
2334 + u16 mhz_max;
2335 + u8 hsfreqrange;
2336 + u8 clk_lp2hs;
2337 + u8 clk_hs2lp;
2338 + u8 data_lp2hs; /* excluding clk lane entry */
2339 + u8 data_hs2lp;
2340 +};
2341 +
2342 +/* See Table A-3 on page 258 of dphy databook */
2343 +static const struct hsfreq_range hsfreq_table[] = {
2344 + { 89, 0b000000, 32, 20, 26, 13 },
2345 + { 99, 0b010000, 35, 23, 28, 14 },
2346 + { 109, 0b100000, 32, 22, 26, 13 },
2347 + { 129, 0b000001, 31, 20, 27, 13 },
2348 + { 139, 0b010001, 33, 22, 26, 14 },
2349 + { 149, 0b100001, 33, 21, 26, 14 },
2350 + { 169, 0b000010, 32, 20, 27, 13 },
2351 + { 179, 0b010010, 36, 23, 30, 15 },
2352 + { 199, 0b100010, 40, 22, 33, 15 },
2353 + { 219, 0b000011, 40, 22, 33, 15 },
2354 + { 239, 0b010011, 44, 24, 36, 16 },
2355 + { 249, 0b100011, 48, 24, 38, 17 },
2356 + { 269, 0b000100, 48, 24, 38, 17 },
2357 + { 299, 0b010100, 50, 27, 41, 18 },
2358 + { 329, 0b000101, 56, 28, 45, 18 },
2359 + { 359, 0b010101, 59, 28, 48, 19 },
2360 + { 399, 0b100101, 61, 30, 50, 20 },
2361 + { 449, 0b000110, 67, 31, 55, 21 },
2362 + { 499, 0b010110, 73, 31, 59, 22 },
2363 + { 549, 0b000111, 79, 36, 63, 24 },
2364 + { 599, 0b010111, 83, 37, 68, 25 },
2365 + { 649, 0b001000, 90, 38, 73, 27 },
2366 + { 699, 0b011000, 95, 40, 77, 28 },
2367 + { 749, 0b001001, 102, 40, 84, 28 },
2368 + { 799, 0b011001, 106, 42, 87, 30 },
2369 + { 849, 0b101001, 113, 44, 93, 31 },
2370 + { 899, 0b111001, 118, 47, 98, 32 },
2371 + { 949, 0b001010, 124, 47, 102, 34 },
2372 + { 999, 0b011010, 130, 49, 107, 35 },
2373 + { 1049, 0b101010, 135, 51, 111, 37 },
2374 + { 1099, 0b111010, 139, 51, 114, 38 },
2375 + { 1149, 0b001011, 146, 54, 120, 40 },
2376 + { 1199, 0b011011, 153, 57, 125, 41 },
2377 + { 1249, 0b101011, 158, 58, 130, 42 },
2378 + { 1299, 0b111011, 163, 58, 135, 44 },
2379 + { 1349, 0b001100, 168, 60, 140, 45 },
2380 + { 1399, 0b011100, 172, 64, 144, 47 },
2381 + { 1449, 0b101100, 176, 65, 148, 48 },
2382 + { 1500, 0b111100, 181, 66, 153, 50 },
2383 +};
2384 +
2385 +static void dphy_set_hsfreqrange(struct rp1_dsi *dsi, u32 freq_mhz)
2386 +{
2387 + unsigned int i;
2388 +
2389 + if (freq_mhz < 80 || freq_mhz > 1500)
2390 + drm_err(dsi->drm, "DPHY: Frequency %u MHz out of range\n",
2391 + freq_mhz);
2392 +
2393 + for (i = 0; i < ARRAY_SIZE(hsfreq_table) - 1; i++) {
2394 + if (freq_mhz <= hsfreq_table[i].mhz_max)
2395 + break;
2396 + }
2397 +
2398 + dsi->hsfreq_index = i;
2399 + dphy_transaction(dsi, DPHY_HS_RX_CTRL_LANE0_OFFSET,
2400 + hsfreq_table[i].hsfreqrange << 1);
2401 +}
2402 +
2403 +static void dphy_configure_pll(struct rp1_dsi *dsi, u32 refclk_khz, u32 vco_freq_khz)
2404 +{
2405 + u32 m = 0;
2406 + u32 n = 0;
2407 +
2408 + if (dphy_get_div(refclk_khz, vco_freq_khz, &m, &n)) {
2409 + dphy_set_hsfreqrange(dsi, vco_freq_khz / 1000);
2410 + /* Program m,n from registers */
2411 + dphy_transaction(dsi, DPHY_PLL_DIV_CTRL_OFFSET, 0x30);
2412 + /* N (program N-1) */
2413 + dphy_transaction(dsi, DPHY_PLL_INPUT_DIV_OFFSET, n - 1);
2414 + /* M[8:5] ?? */
2415 + dphy_transaction(dsi, DPHY_PLL_LOOP_DIV_OFFSET, 0x80 | ((m - 1) >> 5));
2416 + /* M[4:0] (program M-1) */
2417 + dphy_transaction(dsi, DPHY_PLL_LOOP_DIV_OFFSET, ((m - 1) & 0x1F));
2418 + drm_dbg_driver(dsi->drm,
2419 + "DPHY: vco freq want %dkHz got %dkHz = %d * (%dkHz / %d), hsfreqrange = 0x%02x\r\n",
2420 + vco_freq_khz, refclk_khz * m / n, m, refclk_khz,
2421 + n, hsfreq_table[dsi->hsfreq_index].hsfreqrange);
2422 + } else {
2423 + drm_info(dsi->drm,
2424 + "rp1dsi: Error configuring DPHY PLL! %dkHz = %d * (%dkHz / %d)\r\n",
2425 + vco_freq_khz, m, refclk_khz, n);
2426 + }
2427 +}
2428 +
2429 +static void dphy_init_khz(struct rp1_dsi *dsi, u32 ref_freq, u32 vco_freq)
2430 +{
2431 + /* Reset the PHY */
2432 + DSI_WRITE(DSI_PHYRSTZ, 0);
2433 + DSI_WRITE(DSI_PHY_TST_CTRL0, DPHY_CTRL0_PHY_TESTCLK_BITS);
2434 + DSI_WRITE(DSI_PHY_TST_CTRL1, 0);
2435 + DSI_WRITE(DSI_PHY_TST_CTRL0, (DPHY_CTRL0_PHY_TESTCLK_BITS | DPHY_CTRL0_PHY_TESTCLR_BITS));
2436 + udelay(1);
2437 + DSI_WRITE(DSI_PHY_TST_CTRL0, DPHY_CTRL0_PHY_TESTCLK_BITS);
2438 + udelay(1);
2439 + /* Since we are in DSI (not CSI2) mode here, start the PLL */
2440 + dphy_configure_pll(dsi, ref_freq, vco_freq);
2441 + udelay(1);
2442 + /* Unreset */
2443 + DSI_WRITE(DSI_PHYRSTZ, DSI_PHYRSTZ_SHUTDOWNZ_BITS);
2444 + udelay(1);
2445 + DSI_WRITE(DSI_PHYRSTZ, (DSI_PHYRSTZ_SHUTDOWNZ_BITS | DSI_PHYRSTZ_RSTZ_BITS));
2446 + udelay(1); /* so we can see PLL coming up? */
2447 +}
2448 +
2449 +void rp1dsi_mipicfg_setup(struct rp1_dsi *dsi)
2450 +{
2451 + /* Select DSI rather than CSI-2 */
2452 + CFG_WRITE(RPI_MIPICFG_CFG, 0);
2453 + /* Enable DSIDMA interrupt only */
2454 + CFG_WRITE(RPI_MIPICFG_INTE, RPI_MIPICFG_INTE_DSI_DMA_BITS);
2455 +}
2456 +
2457 +static unsigned long rp1dsi_refclk_freq(struct rp1_dsi *dsi)
2458 +{
2459 + unsigned long u;
2460 +
2461 + u = (dsi->clocks[RP1DSI_CLOCK_REF]) ? clk_get_rate(dsi->clocks[RP1DSI_CLOCK_REF]) : 0;
2462 + if (u < 1 || u >= (1ul << 30))
2463 + u = 50000000ul; /* default XOSC frequency */
2464 + return u;
2465 +}
2466 +
2467 +static void rp1dsi_dpiclk_start(struct rp1_dsi *dsi, unsigned int bpp, unsigned int lanes)
2468 +{
2469 + unsigned long u;
2470 +
2471 + if (dsi->clocks[RP1DSI_CLOCK_DPI]) {
2472 + u = (dsi->clocks[RP1DSI_CLOCK_BYTE]) ?
2473 + clk_get_rate(dsi->clocks[RP1DSI_CLOCK_BYTE]) : 0;
2474 + drm_info(dsi->drm,
2475 + "rp1dsi: Nominal byte clock %lu; scale by %u/%u",
2476 + u, 4 * lanes, (bpp >> 1));
2477 + if (u < 1 || u >= (1ul << 28))
2478 + u = 72000000ul; /* default DUMMY frequency for byteclock */
2479 +
2480 + clk_set_parent(dsi->clocks[RP1DSI_CLOCK_DPI], dsi->clocks[RP1DSI_CLOCK_BYTE]);
2481 + clk_set_rate(dsi->clocks[RP1DSI_CLOCK_DPI], (4 * lanes * u) / (bpp >> 1));
2482 + clk_prepare_enable(dsi->clocks[RP1DSI_CLOCK_DPI]);
2483 + }
2484 +}
2485 +
2486 +static void rp1dsi_dpiclk_stop(struct rp1_dsi *dsi)
2487 +{
2488 + if (dsi->clocks[RP1DSI_CLOCK_DPI])
2489 + clk_disable_unprepare(dsi->clocks[RP1DSI_CLOCK_DPI]);
2490 +}
2491 +
2492 +/* Choose the internal on-the-bus DPI format, and DSI packing flag. */
2493 +static u32 get_colorcode(enum mipi_dsi_pixel_format fmt)
2494 +{
2495 + switch (fmt) {
2496 + case MIPI_DSI_FMT_RGB666:
2497 + return 0x104;
2498 + case MIPI_DSI_FMT_RGB666_PACKED:
2499 + return 0x003;
2500 + case MIPI_DSI_FMT_RGB565:
2501 + return 0x000;
2502 + case MIPI_DSI_FMT_RGB888:
2503 + return 0x005;
2504 + }
2505 +
2506 + /* This should be impossible as the format is validated in
2507 + * rp1dsi_host_attach
2508 + */
2509 + WARN_ONCE(1, "Invalid colour format configured for DSI");
2510 + return 0x005;
2511 +}
2512 +
2513 +void rp1dsi_dsi_setup(struct rp1_dsi *dsi, struct drm_display_mode const *mode)
2514 +{
2515 + u32 timeout, mask, vid_mode_cfg;
2516 + u32 freq_khz;
2517 + unsigned int bpp = mipi_dsi_pixel_format_to_bpp(dsi->display_format);
2518 +
2519 + DSI_WRITE(DSI_PHY_IF_CFG, dsi->lanes - 1);
2520 + DSI_WRITE(DSI_DPI_CFG_POL, 0);
2521 + DSI_WRITE(DSI_GEN_VCID, dsi->vc);
2522 + DSI_WRITE(DSI_DPI_COLOR_CODING, get_colorcode(dsi->display_format));
2523 + /* a conservative guess (LP escape is slow!) */
2524 + DSI_WRITE(DSI_DPI_LP_CMD_TIM, 0x00100000);
2525 +
2526 + /* Drop to LP where possible */
2527 + vid_mode_cfg = 0xbf00;
2528 + if (!(dsi->display_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE))
2529 + vid_mode_cfg |= 0x01;
2530 + if (dsi->display_flags & MIPI_DSI_MODE_VIDEO_BURST)
2531 + vid_mode_cfg |= 0x02;
2532 + DSI_WRITE(DSI_VID_MODE_CFG, vid_mode_cfg);
2533 +
2534 + /* Use LP Escape Data signalling for all commands */
2535 + DSI_WRITE(DSI_CMD_MODE_CFG, 0x10F7F00);
2536 + /* Select Command Mode */
2537 + DSI_WRITE(DSI_MODE_CFG, 1);
2538 + /* XXX magic number */
2539 + DSI_WRITE(DSI_TO_CNT_CFG, 0x02000200);
2540 + /* XXX magic number */
2541 + DSI_WRITE(DSI_BTA_TO_CNT, 0x800);
2542 +
2543 + DSI_WRITE(DSI_VID_PKT_SIZE, mode->hdisplay);
2544 + DSI_WRITE(DSI_VID_NUM_CHUNKS, 0);
2545 + DSI_WRITE(DSI_VID_NULL_SIZE, 0);
2546 +
2547 + /* Note, unlike Argon firmware, here we DON'T consider sync to be concurrent with porch */
2548 + DSI_WRITE(DSI_VID_HSA_TIME,
2549 + (bpp * (mode->hsync_end - mode->hsync_start)) / (8 * dsi->lanes));
2550 + DSI_WRITE(DSI_VID_HBP_TIME,
2551 + (bpp * (mode->htotal - mode->hsync_end)) / (8 * dsi->lanes));
2552 + DSI_WRITE(DSI_VID_HLINE_TIME, (bpp * mode->htotal) / (8 * dsi->lanes));
2553 + DSI_WRITE(DSI_VID_VSA_LINES, (mode->vsync_end - mode->vsync_start));
2554 + DSI_WRITE(DSI_VID_VBP_LINES, (mode->vtotal - mode->vsync_end));
2555 + DSI_WRITE(DSI_VID_VFP_LINES, (mode->vsync_start - mode->vdisplay));
2556 + DSI_WRITE(DSI_VID_VACTIVE_LINES, mode->vdisplay);
2557 +
2558 + freq_khz = (bpp * mode->clock) / dsi->lanes;
2559 +
2560 + dphy_init_khz(dsi, rp1dsi_refclk_freq(dsi) / 1000, freq_khz);
2561 +
2562 + DSI_WRITE(DSI_PHY_TMR_LPCLK_CFG,
2563 + (hsfreq_table[dsi->hsfreq_index].clk_lp2hs << DSI_PHY_TMR_LP2HS_LSB) |
2564 + (hsfreq_table[dsi->hsfreq_index].clk_hs2lp << DSI_PHY_TMR_HS2LP_LSB));
2565 + DSI_WRITE(DSI_PHY_TMR_CFG,
2566 + (hsfreq_table[dsi->hsfreq_index].data_lp2hs << DSI_PHY_TMR_LP2HS_LSB) |
2567 + (hsfreq_table[dsi->hsfreq_index].data_hs2lp << DSI_PHY_TMR_HS2LP_LSB));
2568 +
2569 + DSI_WRITE(DSI_CLKMGR_CFG, 0x00000505);
2570 +
2571 + /* Wait for PLL lock */
2572 + for (timeout = (1 << 14); timeout != 0; --timeout) {
2573 + usleep_range(10, 50);
2574 + if (DSI_READ(DSI_PHY_STATUS) & (1 << 0))
2575 + break;
2576 + }
2577 + if (timeout == 0)
2578 + drm_err(dsi->drm, "RP1DSI: Time out waiting for PLL\n");
2579 +
2580 + DSI_WRITE(DSI_LPCLK_CTRL, 0x1); /* configure the requesthsclk */
2581 + DSI_WRITE(DSI_PHY_TST_CTRL0, 0x2);
2582 + DSI_WRITE(DSI_PCKHDL_CFG, 1 << 2); /* allow bus turnaround */
2583 + DSI_WRITE(DSI_PWR_UP, 0x1); /* power up */
2584 +
2585 + /* Now it should be safe to start the external DPI clock divider */
2586 + rp1dsi_dpiclk_start(dsi, bpp, dsi->lanes);
2587 +
2588 + /* Wait for all lane(s) to be in Stopstate */
2589 + mask = (1 << 4);
2590 + if (dsi->lanes >= 2)
2591 + mask |= (1 << 7);
2592 + if (dsi->lanes >= 3)
2593 + mask |= (1 << 9);
2594 + if (dsi->lanes >= 4)
2595 + mask |= (1 << 11);
2596 + for (timeout = (1 << 10); timeout != 0; --timeout) {
2597 + usleep_range(10, 50);
2598 + if ((DSI_READ(DSI_PHY_STATUS) & mask) == mask)
2599 + break;
2600 + }
2601 + if (timeout == 0)
2602 + drm_err(dsi->drm, "RP1DSI: Time out waiting for lanes (%x %x)\n",
2603 + mask, DSI_READ(DSI_PHY_STATUS));
2604 +}
2605 +
2606 +void rp1dsi_dsi_send(struct rp1_dsi *dsi, u32 hdr, int len, const u8 *buf)
2607 +{
2608 + u32 val;
2609 +
2610 + /* Wait for both FIFOs empty */
2611 + for (val = 256; val > 0; --val) {
2612 + if ((DSI_READ(DSI_CMD_PKT_STATUS) & 0xF) == 0x5)
2613 + break;
2614 + usleep_range(100, 150);
2615 + }
2616 +
2617 + /* Write payload (in 32-bit words) and header */
2618 + for (; len > 0; len -= 4) {
2619 + val = *buf++;
2620 + if (len > 1)
2621 + val |= (*buf++) << 8;
2622 + if (len > 2)
2623 + val |= (*buf++) << 16;
2624 + if (len > 3)
2625 + val |= (*buf++) << 24;
2626 + DSI_WRITE(DSI_GEN_PLD_DATA, val);
2627 + }
2628 + DSI_WRITE(DSI_GEN_HDR, hdr);
2629 +
2630 + /* Wait for both FIFOs empty */
2631 + for (val = 256; val > 0; --val) {
2632 + if ((DSI_READ(DSI_CMD_PKT_STATUS) & 0xF) == 0x5)
2633 + break;
2634 + usleep_range(100, 150);
2635 + }
2636 +}
2637 +
2638 +int rp1dsi_dsi_recv(struct rp1_dsi *dsi, int len, u8 *buf)
2639 +{
2640 + int i, j;
2641 + u32 val;
2642 +
2643 + /* Wait until not busy and FIFO not empty */
2644 + for (i = 1024; i > 0; --i) {
2645 + val = DSI_READ(DSI_CMD_PKT_STATUS);
2646 + if ((val & ((1 << 6) | (1 << 4))) == 0)
2647 + break;
2648 + usleep_range(100, 150);
2649 + }
2650 + if (i == 0)
2651 + return -EIO;
2652 +
2653 + for (i = 0; i < len; i += 4) {
2654 + /* Read fifo must not be empty before all bytes are read */
2655 + if (DSI_READ(DSI_CMD_PKT_STATUS) & (1 << 4))
2656 + break;
2657 +
2658 + val = DSI_READ(DSI_GEN_PLD_DATA);
2659 + for (j = 0; j < 4 && j + i < len; j++)
2660 + *buf++ = val >> (8 * j);
2661 + }
2662 +
2663 + return (i >= len) ? len : (i > 0) ? i : -EIO;
2664 +}
2665 +
2666 +void rp1dsi_dsi_stop(struct rp1_dsi *dsi)
2667 +{
2668 + DSI_WRITE(DSI_MODE_CFG, 1); /* Return to Command Mode */
2669 + DSI_WRITE(DSI_LPCLK_CTRL, 2); /* Stop the HS clock */
2670 + DSI_WRITE(DSI_PWR_UP, 0x0); /* Power down host controller */
2671 + DSI_WRITE(DSI_PHYRSTZ, 0); /* PHY into reset. */
2672 + rp1dsi_dpiclk_stop(dsi);
2673 +}
2674 +
2675 +void rp1dsi_dsi_set_cmdmode(struct rp1_dsi *dsi, int mode)
2676 +{
2677 + DSI_WRITE(DSI_MODE_CFG, mode);
2678 +}
Staging tree of Koen Vandeputte