target/linux/bcm63xx/patches-5.4/441-mtd-rawnand-brcmnand-support-v2.1-v2.2-controllers.patch

   1 --- a/drivers/mtd/nand/raw/brcmnand/brcmnand.c
   2 +++ b/drivers/mtd/nand/raw/brcmnand/brcmnand.c
   3 @@ -269,6 +269,36 @@ enum brcmnand_reg {
   4         BRCMNAND_FC_BASE,
   5  };
   6
   7 +/* BRCMNAND v2.1-v2.2 */
   8 +static const u16 brcmnand_regs_v21[] = {
   9 +       [BRCMNAND_CMD_START]            =  0x04,
  10 +       [BRCMNAND_CMD_EXT_ADDRESS]      =  0x08,
  11 +       [BRCMNAND_CMD_ADDRESS]          =  0x0c,
  12 +       [BRCMNAND_INTFC_STATUS]         =  0x5c,
  13 +       [BRCMNAND_CS_SELECT]            =  0x14,
  14 +       [BRCMNAND_CS_XOR]               =  0x18,
  15 +       [BRCMNAND_LL_OP]                =     0,
  16 +       [BRCMNAND_CS0_BASE]             =  0x40,
  17 +       [BRCMNAND_CS1_BASE]             =     0,
  18 +       [BRCMNAND_CORR_THRESHOLD]       =     0,
  19 +       [BRCMNAND_CORR_THRESHOLD_EXT]   =     0,
  20 +       [BRCMNAND_UNCORR_COUNT]         =     0,
  21 +       [BRCMNAND_CORR_COUNT]           =     0,
  22 +       [BRCMNAND_CORR_EXT_ADDR]        =  0x60,
  23 +       [BRCMNAND_CORR_ADDR]            =  0x64,
  24 +       [BRCMNAND_UNCORR_EXT_ADDR]      =  0x68,
  25 +       [BRCMNAND_UNCORR_ADDR]          =  0x6c,
  26 +       [BRCMNAND_SEMAPHORE]            =  0x50,
  27 +       [BRCMNAND_ID]                   =  0x54,
  28 +       [BRCMNAND_ID_EXT]               =     0,
  29 +       [BRCMNAND_LL_RDATA]             =     0,
  30 +       [BRCMNAND_OOB_READ_BASE]        =  0x20,
  31 +       [BRCMNAND_OOB_READ_10_BASE]     =     0,
  32 +       [BRCMNAND_OOB_WRITE_BASE]       =  0x30,
  33 +       [BRCMNAND_OOB_WRITE_10_BASE]    =     0,
  34 +       [BRCMNAND_FC_BASE]              = 0x200,
  35 +};
  36 +
  37  /* BRCMNAND v3.3-v4.0 */
  38  static const u16 brcmnand_regs_v33[] = {
  39         [BRCMNAND_CMD_START]            =  0x04,
  40 @@ -502,12 +532,16 @@ static int brcmnand_revision_init(struct
  41  {
  42         static const unsigned int block_sizes_v6[] = { 8, 16, 128, 256, 512, 1024, 2048, 0 };
  43         static const unsigned int block_sizes_v4[] = { 16, 128, 8, 512, 256, 1024, 2048, 0 };
  44 +       static const unsigned int block_sizes_v2_2[] = { 16, 128, 8, 512, 256, 0 };
  45 +       static const unsigned int block_sizes_v2_1[] = { 16, 128, 8, 512, 0 };
  46         static const unsigned int page_sizes_v3_4[] = { 512, 2048, 4096, 8192, 0 };
  47 +       static const unsigned int page_sizes_v2_2[] = { 512, 2048, 4096, 0 };
  48 +       static const unsigned int page_sizes_v2_1[] = { 512, 2048, 0 };
  49
  50         ctrl->nand_version = nand_readreg(ctrl, 0) & 0xffff;
  51
  52 -       /* Only support v4.0+? */
  53 -       if (ctrl->nand_version < 0x0400) {
  54 +       /* Only support v2.1+ */
  55 +       if (ctrl->nand_version < 0x0201) {
  56                 dev_err(ctrl->dev, "version %#x not supported\n",
  57                         ctrl->nand_version);
  58                 return -ENODEV;
  59 @@ -524,6 +558,8 @@ static int brcmnand_revision_init(struct
  60                 ctrl->reg_offsets = brcmnand_regs_v50;
  61         else if (ctrl->nand_version >= 0x0303)
  62                 ctrl->reg_offsets = brcmnand_regs_v33;
  63 +       else if (ctrl->nand_version >= 0x0201)
  64 +               ctrl->reg_offsets = brcmnand_regs_v21;
  65
  66         /* Chip-select stride */
  67         if (ctrl->nand_version >= 0x0701)
  68 @@ -549,14 +585,27 @@ static int brcmnand_revision_init(struct
  69                 ctrl->max_page_size = 16 * 1024;
  70                 ctrl->max_block_size = 2 * 1024 * 1024;
  71         } else {
  72 -               ctrl->page_sizes = page_sizes_v3_4;
  73 +               if (ctrl->nand_version >= 0x0304)
  74 +                       ctrl->page_sizes = page_sizes_v3_4;
  75 +               else if (ctrl->nand_version >= 0x0202)
  76 +                       ctrl->page_sizes = page_sizes_v2_2;
  77 +               else
  78 +                       ctrl->page_sizes = page_sizes_v2_1;
  79 +
  80                 if (ctrl->nand_version >= 0x0600)
  81                         ctrl->block_sizes = block_sizes_v6;
  82 -               else
  83 +               else if (ctrl->nand_version >= 0x0400)
  84                         ctrl->block_sizes = block_sizes_v4;
  85 +               else if (ctrl->nand_version >= 0x0202)
  86 +                       ctrl->block_sizes = block_sizes_v2_2;
  87 +               else
  88 +                       ctrl->block_sizes = block_sizes_v2_1;
  89
  90                 if (ctrl->nand_version < 0x0400) {
  91 -                       ctrl->max_page_size = 4096;
  92 +                       if (ctrl->nand_version < 0x0202)
  93 +                               ctrl->max_page_size = 2048;
  94 +                       else
  95 +                               ctrl->max_page_size = 4096;
  96                         ctrl->max_block_size = 512 * 1024;
  97                 }
  98         }
  99 @@ -724,6 +773,9 @@ static void brcmnand_wr_corr_thresh(stru
 100         enum brcmnand_reg reg = BRCMNAND_CORR_THRESHOLD;
 101         int cs = host->cs;
 102
 103 +       if (!ctrl->reg_offsets[reg])
 104 +               return;
 105 +
 106         if (ctrl->nand_version == 0x0702)
 107                 bits = 7;
 108         else if (ctrl->nand_version >= 0x0600)
 109 @@ -782,8 +834,10 @@ static inline u32 brcmnand_spare_area_ma
 110                 return GENMASK(7, 0);
 111         else if (ctrl->nand_version >= 0x0600)
 112                 return GENMASK(6, 0);
 113 -       else
 114 +       else if (ctrl->nand_version >= 0x0303)
 115                 return GENMASK(5, 0);
 116 +       else
 117 +               return GENMASK(4, 0);
 118  }
 119
 120  #define NAND_ACC_CONTROL_ECC_SHIFT     16
 121 @@ -2158,9 +2212,11 @@ static int brcmnand_set_cfg(struct brcmn
 122
 123         tmp = nand_readreg(ctrl, acc_control_offs);
 124         tmp &= ~brcmnand_ecc_level_mask(ctrl);
 125 -       tmp |= cfg->ecc_level << NAND_ACC_CONTROL_ECC_SHIFT;
 126         tmp &= ~brcmnand_spare_area_mask(ctrl);
 127 -       tmp |= cfg->spare_area_size;
 128 +       if (ctrl->nand_version >= 0x0302) {
 129 +               tmp |= cfg->ecc_level << NAND_ACC_CONTROL_ECC_SHIFT;
 130 +               tmp |= cfg->spare_area_size;
 131 +       }
 132         nand_writereg(ctrl, acc_control_offs, tmp);
 133
 134         brcmnand_set_sector_size_1k(host, cfg->sector_size_1k);
 135 @@ -2524,6 +2580,8 @@ const struct dev_pm_ops brcmnand_pm_ops
 136  EXPORT_SYMBOL_GPL(brcmnand_pm_ops);
 137
 138  static const struct of_device_id brcmnand_of_match[] = {
 139 +       { .compatible = "brcm,brcmnand-v2.1" },
 140 +       { .compatible = "brcm,brcmnand-v2.2" },
 141         { .compatible = "brcm,brcmnand-v4.0" },
 142         { .compatible = "brcm,brcmnand-v5.0" },
 143         { .compatible = "brcm,brcmnand-v6.0" },