target/linux/bmips/dts/bcm63268.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 /dts-v1/;
   4
   5 #include <dt-bindings/clock/bcm63268-clock.h>
   6 #include <dt-bindings/gpio/gpio.h>
   7 #include <dt-bindings/input/input.h>
   8 #include <dt-bindings/interrupt-controller/bcm63268-interrupt-controller.h>
   9 #include <dt-bindings/reset/bcm63268-reset.h>
  10 #include <dt-bindings/soc/bcm63268-pm.h>
  11
  12 / {
  13         #address-cells = <1>;
  14         #size-cells = <1>;
  15         compatible = "brcm,bcm63268";
  16
  17         aliases {
  18                 nflash = &nflash;
  19                 pinctrl = &pinctrl;
  20                 serial0 = &uart0;
  21                 serial1 = &uart1;
  22                 spi0 = &lsspi;
  23                 spi1 = &hsspi;
  24         };
  25
  26         chosen {
  27                 bootargs = "earlycon";
  28                 stdout-path = "serial0:115200n8";
  29         };
  30
  31         clocks {
  32                 periph_osc: periph-osc {
  33                         compatible = "fixed-clock";
  34
  35                         #clock-cells = <0>;
  36
  37                         clock-frequency = <50000000>;
  38                         clock-output-names = "periph";
  39                 };
  40
  41                 hsspi_osc: hsspi-osc {
  42                         compatible = "fixed-clock";
  43
  44                         #clock-cells = <0>;
  45
  46                         clock-frequency = <400000000>;
  47                         clock-output-names = "hsspi_osc";
  48                 };
  49         };
  50
  51         cpus {
  52                 #address-cells = <1>;
  53                 #size-cells = <0>;
  54                 mips-hpt-frequency = <200000000>;
  55
  56                 cpu@0 {
  57                         compatible = "brcm,bmips4350", "mips,mips4Kc";
  58                         device_type = "cpu";
  59                         reg = <0>;
  60                 };
  61
  62                 cpu@1 {
  63                         compatible = "brcm,bmips4350", "mips,mips4Kc";
  64                         device_type = "cpu";
  65                         reg = <1>;
  66                 };
  67         };
  68
  69         cpu_intc: interrupt-controller {
  70                 #address-cells = <0>;
  71                 compatible = "mti,cpu-interrupt-controller";
  72
  73                 interrupt-controller;
  74                 #interrupt-cells = <1>;
  75         };
  76
  77         memory@0 {
  78                 device_type = "memory";
  79                 reg = <0 0>;
  80         };
  81
  82         ubus {
  83                 #address-cells = <1>;
  84                 #size-cells = <1>;
  85
  86                 compatible = "simple-bus";
  87                 ranges;
  88
  89                 periph_clk: clock-controller@10000004 {
  90                         compatible = "brcm,bcm63268-clocks";
  91                         reg = <0x10000004 0x4>;
  92                         #clock-cells = <1>;
  93                 };
  94
  95                 pll_cntl: syscon@10000008 {
  96                         compatible = "syscon", "simple-mfd";
  97                         reg = <0x10000008 0x4>;
  98                         native-endian;
  99
 100                         syscon-reboot {
 101                                 compatible = "syscon-reboot";
 102                                 offset = <0x0>;
 103                                 mask = <0x1>;
 104                         };
 105                 };
 106
 107                 periph_rst: reset-controller@10000010 {
 108                         compatible = "brcm,bcm6345-reset";
 109                         reg = <0x10000010 0x4>;
 110                         #reset-cells = <1>;
 111                 };
 112
 113                 ext_intc: interrupt-controller@10000018 {
 114                         #address-cells = <1>;
 115                         compatible = "brcm,bcm6345-ext-intc";
 116                         reg = <0x10000018 0x4>;
 117
 118                         interrupt-controller;
 119                         #interrupt-cells = <2>;
 120
 121                         interrupts = <BCM63268_IRQ_EXT0>,
 122                                      <BCM63268_IRQ_EXT1>,
 123                                      <BCM63268_IRQ_EXT2>,
 124                                      <BCM63268_IRQ_EXT3>;
 125                 };
 126
 127                 periph_intc: interrupt-controller@10000020 {
 128                         #address-cells = <1>;
 129                         compatible = "brcm,bcm6345-l1-intc";
 130                         reg = <0x10000020 0x20>,
 131                               <0x10000040 0x20>;
 132
 133                         interrupt-controller;
 134                         #interrupt-cells = <1>;
 135
 136                         interrupt-parent = <&cpu_intc>;
 137                         interrupts = <2>, <3>;
 138                 };
 139
 140                 wdt: watchdog@1000009c {
 141                         compatible = "brcm,bcm7038-wdt";
 142                         reg = <0x1000009c 0xc>;
 143
 144                         clocks = <&periph_osc>;
 145
 146                         timeout-sec = <30>;
 147                 };
 148
 149                 timer_clk: clock-controller@100000ac {
 150                         compatible = "brcm,bcm63268-timer-clocks";
 151                         reg = <0x100000ac 0x4>;
 152                         #clock-cells = <1>;
 153                         #reset-cells = <1>;
 154                 };
 155
 156                 gpio: syscon@100000c0 {
 157                         compatible = "syscon", "simple-mfd";
 158                         reg = <0x100000c0 0x80>;
 159                         native-endian;
 160
 161                         pinctrl: pin-controller {
 162                                 compatible = "brcm,bcm63268-pinctrl";
 163
 164                                 gpio-controller;
 165                                 #gpio-cells = <2>;
 166
 167                                 interrupts-extended = <&ext_intc 0 0>,
 168                                                       <&ext_intc 1 0>,
 169                                                       <&ext_intc 2 0>,
 170                                                       <&ext_intc 3 0>;
 171                                 interrupt-names = "gpio32",
 172                                                   "gpio33",
 173                                                   "gpio34",
 174                                                   "gpio35";
 175
 176                                 pinctrl_serial_led: serial_led {
 177                                         pinctrl_serial_led_clk: serial_led_clk {
 178                                                 function = "serial_led_clk";
 179                                                 pins = "gpio0";
 180                                         };
 181
 182                                         pinctrl_serial_led_data: serial_led_data {
 183                                                 function = "serial_led_data";
 184                                                 pins = "gpio1";
 185                                         };
 186                                 };
 187
 188                                 pinctrl_hsspi_cs4: hsspi_cs4 {
 189                                         function = "hsspi_cs4";
 190                                         pins = "gpio16";
 191                                 };
 192
 193                                 pinctrl_hsspi_cs5: hsspi_cs5 {
 194                                         function = "hsspi_cs5";
 195                                         pins = "gpio17";
 196                                 };
 197
 198                                 pinctrl_hsspi_cs6: hsspi_cs6 {
 199                                         function = "hsspi_cs6";
 200                                         pins = "gpio8";
 201                                 };
 202
 203                                 pinctrl_hsspi_cs7: hsspi_cs7 {
 204                                         function = "hsspi_cs7";
 205                                         pins = "gpio9";
 206                                 };
 207
 208                                 pinctrl_adsl_spi: adsl_spi {
 209                                         pinctrl_adsl_spi_miso: adsl_spi_miso {
 210                                                 function = "adsl_spi_miso";
 211                                                 pins = "gpio18";
 212                                         };
 213
 214                                         pinctrl_adsl_spi_mosi: adsl_spi_mosi {
 215                                                 function = "adsl_spi_mosi";
 216                                                 pins = "gpio19";
 217                                         };
 218                                 };
 219
 220                                 pinctrl_vreq_clk: vreq_clk {
 221                                         function = "vreq_clk";
 222                                         pins = "gpio22";
 223                                 };
 224
 225                                 pinctrl_pcie_clkreq_b: pcie_clkreq_b {
 226                                         function = "pcie_clkreq_b";
 227                                         pins = "gpio23";
 228                                 };
 229
 230                                 pinctrl_robosw_led_clk: robosw_led_clk {
 231                                         function = "robosw_led_clk";
 232                                         pins = "gpio30";
 233                                 };
 234
 235                                 pinctrl_robosw_led_data: robosw_led_data {
 236                                         function = "robosw_led_data";
 237                                         pins = "gpio31";
 238                                 };
 239
 240                                 pinctrl_nand: nand {
 241                                         function = "nand";
 242                                         group = "nand_grp";
 243                                 };
 244
 245                                 pinctrl_gpio35_alt: gpio35_alt {
 246                                         function = "gpio35_alt";
 247                                         pin = "gpio35";
 248                                 };
 249
 250                                 pinctrl_dectpd: dectpd {
 251                                         function = "dectpd";
 252                                         group = "dectpd_grp";
 253                                 };
 254
 255                                 pinctrl_vdsl_phy_override_0: vdsl_phy_override_0 {
 256                                         function = "vdsl_phy_override_0";
 257                                         group = "vdsl_phy_override_0_grp";
 258                                 };
 259
 260                                 pinctrl_vdsl_phy_override_1: vdsl_phy_override_1 {
 261                                         function = "vdsl_phy_override_1";
 262                                         group = "vdsl_phy_override_1_grp";
 263                                 };
 264
 265                                 pinctrl_vdsl_phy_override_2: vdsl_phy_override_2 {
 266                                         function = "vdsl_phy_override_2";
 267                                         group = "vdsl_phy_override_2_grp";
 268                                 };
 269
 270                                 pinctrl_vdsl_phy_override_3: vdsl_phy_override_3 {
 271                                         function = "vdsl_phy_override_3";
 272                                         group = "vdsl_phy_override_3_grp";
 273                                 };
 274
 275                                 pinctrl_dsl_gpio8: dsl_gpio8 {
 276                                         function = "dsl_gpio8";
 277                                         group = "dsl_gpio8";
 278                                 };
 279
 280                                 pinctrl_dsl_gpio9: dsl_gpio9 {
 281                                         function = "dsl_gpio9";
 282                                         group = "dsl_gpio9";
 283                                 };
 284                         };
 285                 };
 286
 287                 uart0: serial@10000180 {
 288                         compatible = "brcm,bcm6345-uart";
 289                         reg = <0x10000180 0x18>;
 290
 291                         interrupt-parent = <&periph_intc>;
 292                         interrupts = <BCM63268_IRQ_UART0>;
 293
 294                         clocks = <&periph_osc>;
 295                         clock-names = "periph";
 296
 297                         status = "disabled";
 298                 };
 299
 300                 uart1: serial@100001a0 {
 301                         compatible = "brcm,bcm6345-uart";
 302                         reg = <0x100001a0 0x18>;
 303
 304                         interrupt-parent = <&periph_intc>;
 305                         interrupts = <BCM63268_IRQ_UART1>;
 306
 307                         clocks = <&periph_osc>;
 308                         clock-names = "periph";
 309
 310                         status = "disabled";
 311                 };
 312
 313                 nflash: nand@10000200 {
 314                         #address-cells = <1>;
 315                         #size-cells = <0>;
 316                         compatible = "brcm,nand-bcm6368",
 317                                      "brcm,brcmnand-v4.0",
 318                                      "brcm,brcmnand";
 319                         reg = <0x10000200 0x180>,
 320                               <0x10000600 0x200>,
 321                               <0x100000b0 0x10>;
 322                         reg-names = "nand",
 323                                     "nand-cache",
 324                                     "nand-int-base";
 325
 326                         interrupt-parent = <&periph_intc>;
 327                         interrupts = <BCM63268_IRQ_NAND>;
 328
 329                         clocks = <&periph_clk BCM63268_CLK_NAND>;
 330                         clock-names = "nand";
 331
 332                         pinctrl-names = "default";
 333                         pinctrl-0 = <&pinctrl_nand>;
 334
 335                         status = "disabled";
 336                 };
 337
 338                 lsspi: spi@10000800 {
 339                         #address-cells = <1>;
 340                         #size-cells = <0>;
 341                         compatible = "brcm,bcm6358-spi";
 342                         reg = <0x10000800 0x70c>;
 343
 344                         interrupt-parent = <&periph_intc>;
 345                         interrupts = <BCM63268_IRQ_LSSPI>;
 346
 347                         clocks = <&periph_clk BCM63268_CLK_SPI>;
 348                         clock-names = "spi";
 349
 350                         resets = <&periph_rst BCM63268_RST_SPI>;
 351
 352                         status = "disabled";
 353                 };
 354
 355                 hsspi: spi@10001000 {
 356                         #address-cells = <1>;
 357                         #size-cells = <0>;
 358                         compatible = "brcm,bcm6328-hsspi";
 359                         reg = <0x10001000 0x600>;
 360
 361                         interrupt-parent = <&periph_intc>;
 362                         interrupts = <BCM63268_IRQ_HSSPI>;
 363
 364                         clocks = <&periph_clk BCM63268_CLK_HSSPI>,
 365                                  <&hsspi_osc>;
 366                         clock-names = "hsspi",
 367                                       "pll";
 368
 369                         resets = <&periph_rst BCM63268_RST_SPI>;
 370
 371                         status = "disabled";
 372                 };
 373
 374                 serdes_cntl: syscon@10001804 {
 375                         compatible = "syscon";
 376                         reg = <0x10001804 0x4>;
 377                         native-endian;
 378                 };
 379
 380                 periph_pwr: power-controller@1000184c {
 381                         compatible = "brcm,bcm63268-power-controller";
 382                         reg = <0x1000184c 0x4>;
 383                         #power-domain-cells = <1>;
 384                 };
 385
 386                 leds: led-controller@10001900 {
 387                         #address-cells = <1>;
 388                         #size-cells = <0>;
 389                         compatible = "brcm,bcm6328-leds";
 390                         reg = <0x10001900 0x24>;
 391
 392                         status = "disabled";
 393                 };
 394
 395                 ehci: usb@10002500 {
 396                         compatible = "brcm,bcm63268-ehci", "generic-ehci";
 397                         reg = <0x10002500 0x100>;
 398                         big-endian;
 399                         spurious-oc;
 400
 401                         interrupt-parent = <&periph_intc>;
 402                         interrupts = <BCM63268_IRQ_EHCI>;
 403
 404                         phys = <&usbh 0>;
 405                         phy-names = "usb";
 406
 407                         status = "disabled";
 408                 };
 409
 410                 ohci: usb@10002600 {
 411                         compatible = "brcm,bcm63268-ohci", "generic-ohci";
 412                         reg = <0x10002600 0x100>;
 413                         big-endian;
 414                         no-big-frame-no;
 415
 416                         interrupt-parent = <&periph_intc>;
 417                         interrupts = <BCM63268_IRQ_OHCI>;
 418
 419                         phys = <&usbh 0>;
 420                         phy-names = "usb";
 421
 422                         status = "disabled";
 423                 };
 424
 425                 usbh: usb-phy@10002700 {
 426                         compatible = "brcm,bcm63268-usbh-phy";
 427                         reg = <0x10002700 0x38>;
 428
 429                         #phy-cells = <1>;
 430
 431                         clocks = <&periph_clk BCM63268_CLK_USBH>,
 432                                  <&timer_clk BCM63268_TCLK_USB_REF>;
 433                         clock-names = "usbh",
 434                                       "usb_ref";
 435
 436                         power-domains = <&periph_pwr BCM63268_POWER_DOMAIN_USBH>;
 437                         resets = <&periph_rst BCM63268_RST_USBH>;
 438
 439                         status = "disabled";
 440                 };
 441
 442                 ethernet: ethernet@1000d800 {
 443                         compatible = "brcm,bcm63268-enetsw";
 444                         reg = <0x1000d800 0x80>,
 445                               <0x1000da00 0x80>,
 446                               <0x1000dc00 0x80>;
 447                         reg-names = "dma",
 448                                     "dma-channels",
 449                                     "dma-sram";
 450
 451                         interrupt-parent = <&periph_intc>;
 452                         interrupts = <BCM63268_IRQ_ENETSW_RX_DMA0>,
 453                                      <BCM63268_IRQ_ENETSW_TX_DMA0>;
 454                         interrupt-names = "rx",
 455                                           "tx";
 456
 457                         clocks = <&periph_clk BCM63268_CLK_GMAC>,
 458                                  <&periph_clk BCM63268_CLK_ROBOSW>,
 459                                  <&periph_clk BCM63268_CLK_ROBOSW250>,
 460                                  <&timer_clk BCM63268_TCLK_EPHY1>,
 461                                  <&timer_clk BCM63268_TCLK_EPHY2>,
 462                                  <&timer_clk BCM63268_TCLK_EPHY3>,
 463                                  <&timer_clk BCM63268_TCLK_GPHY1>;
 464
 465                         resets = <&periph_rst BCM63268_RST_ENETSW>,
 466                                  <&periph_rst BCM63268_RST_EPHY>,
 467                                  <&periph_rst BCM63268_RST_GPHY>;
 468
 469                         power-domains = <&periph_pwr BCM63268_POWER_DOMAIN_ROBOSW>;
 470
 471                         dma-rx = <0>;
 472                         dma-tx = <1>;
 473
 474                         status = "disabled";
 475                 };
 476
 477                 pcie: pcie@106e0000 {
 478                         compatible = "brcm,bcm6328-pcie";
 479                         reg = <0x106e0000 0x10000>;
 480                         #address-cells = <3>;
 481                         #size-cells = <2>;
 482
 483                         device_type = "pci";
 484                         bus-range = <0x00 0x01>;
 485                         ranges = <0x2000000 0 0x11000000 0x11000000 0 0xf00000>;
 486                         linux,pci-probe-only = <1>;
 487
 488                         interrupt-parent = <&periph_intc>;
 489                         interrupts = <BCM63268_IRQ_PCIE_RC>;
 490
 491                         clocks = <&periph_clk BCM63268_CLK_PCIE>;
 492                         clock-names = "pcie";
 493
 494                         resets = <&periph_rst BCM63268_RST_PCIE>,
 495                                  <&periph_rst BCM63268_RST_PCIE_EXT>,
 496                                  <&periph_rst BCM63268_RST_PCIE_CORE>,
 497                                  <&periph_rst BCM63268_RST_PCIE_HARD>;
 498                         reset-names = "pcie",
 499                                       "pcie-ext",
 500                                       "pcie-core",
 501                                       "pcie-hard";
 502
 503                         power-domains = <&periph_pwr BCM63268_POWER_DOMAIN_PCIE>;
 504
 505                         brcm,serdes = <&serdes_cntl>;
 506
 507                         status = "disabled";
 508                 };
 509
 510                 switch0: switch@10700000 {
 511                         #address-cells = <1>;
 512                         #size-cells = <0>;
 513                         compatible = "brcm,bcm6328-switch";
 514                         reg = <0x10700000 0x8000>;
 515                         big-endian;
 516
 517                         ports {
 518                                 #address-cells = <1>;
 519                                 #size-cells = <0>;
 520
 521                                 port@8 {
 522                                         reg = <8>;
 523                                         label = "cpu";
 524
 525                                         phy-mode = "internal";
 526                                         ethernet = <&ethernet>;
 527
 528                                         fixed-link {
 529                                                 speed = <1000>;
 530                                                 full-duplex;
 531                                         };
 532                                 };
 533                         };
 534                 };
 535
 536                 mdio: mdio@107000b0 {
 537                         #address-cells = <1>;
 538                         #size-cells = <0>;
 539                         compatible = "brcm,bcm6368-mdio-mux";
 540                         reg = <0x107000b0 0x8>;
 541
 542                         mdio_int: mdio@0 {
 543                                 #address-cells = <1>;
 544                                 #size-cells = <0>;
 545                                 reg = <0>;
 546
 547                                 phy1: ethernet-phy@1 {
 548                                         compatible = "ethernet-phy-ieee802.3-c22";
 549                                         reg = <1>;
 550                                 };
 551
 552                                 phy2: ethernet-phy@2 {
 553                                         compatible = "ethernet-phy-ieee802.3-c22";
 554                                         reg = <2>;
 555                                 };
 556
 557                                 phy3: ethernet-phy@3 {
 558                                         compatible = "ethernet-phy-ieee802.3-c22";
 559                                         reg = <3>;
 560                                 };
 561
 562                                 phy4: ethernet-phy@4 {
 563                                         compatible = "ethernet-phy-ieee802.3-c22";
 564                                         reg = <4>;
 565                                 };
 566                         };
 567
 568                         mdio_ext: mdio@1 {
 569                                 #address-cells = <1>;
 570                                 #size-cells = <0>;
 571                                 reg = <1>;
 572                         };
 573                 };
 574         };
 575 };