lantiq: Use the BAR0 base address in the ath PCI fixup code
[openwrt/staging/wigyori.git] / target / linux / brcm2708 / patches-3.18 / 0096-bcm2709-dwc_otg-Setup-FIQ-on-core-1-if-1-core-active.patch
1 From a31e1ba443ff061c4bf4abbac46ca8e197da3f0c Mon Sep 17 00:00:00 2001
2 From: P33M <P33M@github.com>
3 Date: Thu, 22 Jan 2015 18:45:23 +0000
4 Subject: [PATCH 096/114] bcm2709/dwc_otg: Setup FIQ on core 1 if >1 core
5 active
6
7 ---
8 arch/arm/mach-bcm2709/armctrl.c | 10 +++++++++-
9 drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c | 15 +++++++++++----
10 2 files changed, 20 insertions(+), 5 deletions(-)
11
12 --- a/arch/arm/mach-bcm2709/armctrl.c
13 +++ b/arch/arm/mach-bcm2709/armctrl.c
14 @@ -89,7 +89,15 @@ static void armctrl_unmask_irq(struct ir
15 };
16 int i;
17 if (d->irq >= FIQ_START) {
18 - unsigned int data = (unsigned int)irq_get_chip_data(d->irq) - FIQ_START;
19 + unsigned int data;
20 + if (num_online_cpus() > 1) {
21 + data = readl(__io_address(ARM_LOCAL_GPU_INT_ROUTING));
22 + data &= ~0xc;
23 + data |= (1 << 2);
24 + writel(data, __io_address(ARM_LOCAL_GPU_INT_ROUTING));
25 + }
26 + /* Unmask in ARMCTRL block after routing it properly */
27 + data = (unsigned int)irq_get_chip_data(d->irq) - FIQ_START;
28 writel(0x80 | data, __io_address(ARM_IRQ_FAST));
29 } else if (d->irq >= IRQ_ARM_LOCAL_CNTPSIRQ && d->irq < IRQ_ARM_LOCAL_CNTPSIRQ + 4) {
30 #if 1
31 --- a/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c
32 +++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_linux.c
33 @@ -407,7 +407,9 @@ static void hcd_init_fiq(void *cookie)
34 DWC_ERROR("Can't claim FIQ");
35 BUG();
36 }
37 - DWC_WARN("FIQ at 0x%08x", (fiq_fsm_enable ? (int)&dwc_otg_fiq_fsm : (int)&dwc_otg_fiq_nop));
38 + DWC_WARN("FIQ on core %d at 0x%08x",
39 + smp_processor_id(),
40 + (fiq_fsm_enable ? (int)&dwc_otg_fiq_fsm : (int)&dwc_otg_fiq_nop));
41 DWC_WARN("FIQ ASM at 0x%08x length %d", (int)&_dwc_otg_fiq_stub, (int)(&_dwc_otg_fiq_stub_end - &_dwc_otg_fiq_stub));
42 set_fiq_handler((void *) &_dwc_otg_fiq_stub, &_dwc_otg_fiq_stub_end - &_dwc_otg_fiq_stub);
43 memset(&regs,0,sizeof(regs));
44 @@ -510,9 +512,14 @@ int hcd_init(dwc_bus_dev_t *_dev)
45 goto error2;
46 }
47
48 - if (fiq_enable)
49 - smp_call_function_single(0, hcd_init_fiq, otg_dev, 1);
50 -
51 + if (fiq_enable) {
52 + if (num_online_cpus() > 1) {
53 + /* bcm2709: can run the FIQ on a separate core to IRQs */
54 + smp_call_function_single(1, hcd_init_fiq, otg_dev, 1);
55 + } else {
56 + smp_call_function_single(0, hcd_init_fiq, otg_dev, 1);
57 + }
58 + }
59
60 otg_dev->hcd->otg_dev = otg_dev;
61 hcd->self.otg_port = dwc_otg_hcd_otg_port(dwc_otg_hcd);