target/linux/brcm2708/patches-3.18/0105-dwc_otg-fixup-read-modify-write-in-critical-paths.patch

   1 From a05cd269cbf2623efe2499459efdd123ee04ab81 Mon Sep 17 00:00:00 2001
   2 From: P33M <P33M@github.com>
   3 Date: Wed, 4 Feb 2015 12:16:50 +0000
   4 Subject: [PATCH 105/114] dwc_otg: fixup read-modify-write in critical paths
   5
   6 Be more careful about read-modify-write on registers that the FIQ
   7 also touches.
   8 ---
   9  drivers/usb/host/dwc_otg/dwc_otg_hcd.c       | 13 +++++++++---
  10  drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c  | 30 +++++++++++++++++++++++++---
  11  drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c | 22 ++++++++++++++++----
  12  3 files changed, 55 insertions(+), 10 deletions(-)
  13
  14 --- a/drivers/usb/host/dwc_otg/dwc_otg_hcd.c
  15 +++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd.c
  16 @@ -2447,9 +2447,16 @@ void dwc_otg_hcd_queue_transactions(dwc_
  17                          */
  18                         gintmsk_data_t gintmsk = {.d32 = 0 };
  19                         gintmsk.b.nptxfempty = 1;
  20 -                       DWC_MODIFY_REG32(&hcd->core_if->
  21 -                                        core_global_regs->gintmsk, gintmsk.d32,
  22 -                                        0);
  23 +
  24 +                       if (fiq_enable) {
  25 +                               local_fiq_disable();
  26 +                               fiq_fsm_spin_lock(&hcd->fiq_state->lock);
  27 +                               DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
  28 +                               fiq_fsm_spin_unlock(&hcd->fiq_state->lock);
  29 +                               local_fiq_enable();
  30 +                       } else {
  31 +                               DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, gintmsk.d32, 0);
  32 +                       }
  33                 }
  34         }
  35  }
  36 --- a/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c
  37 +++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_intr.c
  38 @@ -165,7 +165,15 @@ int32_t dwc_otg_hcd_handle_intr(dwc_otg_
  39
  40                         gintmsk_data_t gintmsk = { .b.portintr = 1};
  41                         retval |= dwc_otg_hcd_handle_port_intr(dwc_otg_hcd);
  42 -                       DWC_MODIFY_REG32(&core_if->core_global_regs->gintmsk, 0, gintmsk.d32);
  43 +                       if (fiq_enable) {
  44 +                               local_fiq_disable();
  45 +                               fiq_fsm_spin_lock(&dwc_otg_hcd->fiq_state->lock);
  46 +                               DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk, 0, gintmsk.d32);
  47 +                               fiq_fsm_spin_unlock(&dwc_otg_hcd->fiq_state->lock);
  48 +                               local_fiq_enable();
  49 +                       } else {
  50 +                               DWC_MODIFY_REG32(&dwc_otg_hcd->core_if->core_global_regs->gintmsk, 0, gintmsk.d32);
  51 +                       }
  52                 }
  53                 if (gintsts.b.hcintr) {
  54                         retval |= dwc_otg_hcd_handle_hc_intr(dwc_otg_hcd);
  55 @@ -1069,7 +1077,15 @@ static void halt_channel(dwc_otg_hcd_t *
  56                          * be processed.
  57                          */
  58                         gintmsk.b.nptxfempty = 1;
  59 -                       DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32);
  60 +                       if (fiq_enable) {
  61 +                               local_fiq_disable();
  62 +                               fiq_fsm_spin_lock(&hcd->fiq_state->lock);
  63 +                               DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32);
  64 +                               fiq_fsm_spin_unlock(&hcd->fiq_state->lock);
  65 +                               local_fiq_enable();
  66 +                       } else {
  67 +                               DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32);
  68 +                       }
  69                 } else {
  70                         /*
  71                          * Move the QH from the periodic queued schedule to
  72 @@ -1086,7 +1102,15 @@ static void halt_channel(dwc_otg_hcd_t *
  73                          * processed.
  74                          */
  75                         gintmsk.b.ptxfempty = 1;
  76 -                       DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32);
  77 +                       if (fiq_enable) {
  78 +                               local_fiq_disable();
  79 +                               fiq_fsm_spin_lock(&hcd->fiq_state->lock);
  80 +                               DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32);
  81 +                               fiq_fsm_spin_unlock(&hcd->fiq_state->lock);
  82 +                               local_fiq_enable();
  83 +                       } else {
  84 +                               DWC_MODIFY_REG32(&global_regs->gintmsk, 0, gintmsk.d32);
  85 +                       }
  86                 }
  87         }
  88  }
  89 --- a/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c
  90 +++ b/drivers/usb/host/dwc_otg/dwc_otg_hcd_queue.c
  91 @@ -683,8 +683,15 @@ int dwc_otg_hcd_qh_add(dwc_otg_hcd_t * h
  92                 status = schedule_periodic(hcd, qh);
  93                 if ( !hcd->periodic_qh_count ) {
  94                         intr_mask.b.sofintr = 1;
  95 -                       DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk,
  96 -                                                               intr_mask.d32, intr_mask.d32);
  97 +                       if (fiq_enable) {
  98 +                               local_fiq_disable();
  99 +                               fiq_fsm_spin_lock(&hcd->fiq_state->lock);
 100 +                               DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
 101 +                               fiq_fsm_spin_unlock(&hcd->fiq_state->lock);
 102 +                               local_fiq_enable();
 103 +                       } else {
 104 +                               DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, intr_mask.d32, intr_mask.d32);
 105 +                       }
 106                 }
 107                 hcd->periodic_qh_count++;
 108         }
 109 @@ -745,8 +752,15 @@ void dwc_otg_hcd_qh_remove(dwc_otg_hcd_t
 110                 hcd->periodic_qh_count--;
 111                 if( !hcd->periodic_qh_count && !fiq_fsm_enable ) {
 112                         intr_mask.b.sofintr = 1;
 113 -                               DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk,
 114 -                                                                       intr_mask.d32, 0);
 115 +                       if (fiq_enable) {
 116 +                               local_fiq_disable();
 117 +                               fiq_fsm_spin_lock(&hcd->fiq_state->lock);
 118 +                               DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, intr_mask.d32, 0);
 119 +                               fiq_fsm_spin_unlock(&hcd->fiq_state->lock);
 120 +                               local_fiq_enable();
 121 +                       } else {
 122 +                               DWC_MODIFY_REG32(&hcd->core_if->core_global_regs->gintmsk, intr_mask.d32, 0);
 123 +                       }
 124                 }
 125         }
 126  }