target/linux/brcm63xx/files/include/asm-mips/mach-bcm63xx/bcm63xx_cpu.h

   1 #ifndef BCM63XX_CPU_H_
   2 #define BCM63XX_CPU_H_
   3
   4 #include <linux/types.h>
   5 #include <linux/init.h>
   6
   7 #include <bcm63xx_regs.h>
   8
   9 /*
  10  * Macro to fetch bcm63xx cpu id and revision, should be optimized at
  11  * compile time if only one CPU support is enabled (idea stolen from
  12  * arm mach-types)
  13  */
  14 #define BCM6338_CPU_ID          0x6338
  15 #define BCM6345_CPU_ID          0x6345
  16 #define BCM6348_CPU_ID          0x6348
  17 #define BCM6358_CPU_ID          0x6358
  18
  19 void __init bcm63xx_cpu_init(void);
  20 u16 __bcm63xx_get_cpu_id(void);
  21 u16 bcm63xx_get_cpu_rev(void);
  22 unsigned int bcm63xx_get_cpu_freq(void);
  23
  24 #ifdef CONFIG_BCM63XX_CPU_6338
  25 # ifdef bcm63xx_get_cpu_id
  26 #  undef bcm63xx_get_cpu_id
  27 #  define bcm63xx_get_cpu_id()  __bcm63xx_get_cpu_id()
  28 #  define BCMCPU_RUNTIME_DETECT
  29 # else
  30 #  define bcm63xx_get_cpu_id()  BCM6338_CPU_ID
  31 # endif
  32 # define BCMCPU_IS_6338()       (bcm63xx_get_cpu_id() == BCM6338_CPU_ID)
  33 #else
  34 # define BCMCPU_IS_6338()       (0)
  35 #endif
  36
  37 #ifdef CONFIG_BCM63XX_CPU_6345
  38 # ifdef bcm63xx_get_cpu_id
  39 #  undef bcm63xx_get_cpu_id
  40 #  define bcm63xx_get_cpu_id()  __bcm63xx_get_cpu_id()
  41 #  define BCMCPU_RUNTIME_DETECT
  42 # else
  43 #  define bcm63xx_get_cpu_id()  BCM6345_CPU_ID
  44 # endif
  45 # define BCMCPU_IS_6345()       (bcm63xx_get_cpu_id() == BCM6345_CPU_ID)
  46 #else
  47 # define BCMCPU_IS_6345()       (0)
  48 #endif
  49
  50 #ifdef CONFIG_BCM63XX_CPU_6348
  51 # ifdef bcm63xx_get_cpu_id
  52 #  undef bcm63xx_get_cpu_id
  53 #  define bcm63xx_get_cpu_id()  __bcm63xx_get_cpu_id()
  54 #  define BCMCPU_RUNTIME_DETECT
  55 # else
  56 #  define bcm63xx_get_cpu_id()  BCM6348_CPU_ID
  57 # endif
  58 # define BCMCPU_IS_6348()       (bcm63xx_get_cpu_id() == BCM6348_CPU_ID)
  59 #else
  60 # define BCMCPU_IS_6348()       (0)
  61 #endif
  62
  63 #ifdef CONFIG_BCM63XX_CPU_6358
  64 # ifdef bcm63xx_get_cpu_id
  65 #  undef bcm63xx_get_cpu_id
  66 #  define bcm63xx_get_cpu_id()  __bcm63xx_get_cpu_id()
  67 #  define BCMCPU_RUNTIME_DETECT
  68 # else
  69 #  define bcm63xx_get_cpu_id()  BCM6358_CPU_ID
  70 # endif
  71 # define BCMCPU_IS_6358()       (bcm63xx_get_cpu_id() == BCM6358_CPU_ID)
  72 #else
  73 # define BCMCPU_IS_6358()       (0)
  74 #endif
  75
  76 #ifndef bcm63xx_get_cpu_id
  77 #error "No CPU support configured"
  78 #endif
  79
  80 /*
  81  * While registers sets are (mostly) the same across 63xx CPU, base
  82  * address of these sets do change.
  83  */
  84 enum bcm63xx_regs_set {
  85         RSET_DSL_LMEM = 0,
  86         RSET_PERF,
  87         RSET_TIMER,
  88         RSET_WDT,
  89         RSET_UART0,
  90         RSET_GPIO,
  91         RSET_SPI,
  92         RSET_UDC0,
  93         RSET_OHCI0,
  94         RSET_OHCI_PRIV,
  95         RSET_USBH_PRIV,
  96         RSET_MPI,
  97         RSET_PCMCIA,
  98         RSET_DSL,
  99         RSET_ENET0,
 100         RSET_ENET1,
 101         RSET_ENETDMA,
 102         RSET_EHCI0,
 103         RSET_SDRAM,
 104         RSET_MEMC,
 105         RSET_DDR,
 106 };
 107
 108 #define RSET_DSL_LMEM_SIZE              (64 * 1024 * 4)
 109 #define RSET_DSL_SIZE                   4096
 110 #define RSET_WDT_SIZE                   12
 111 #define RSET_ENET_SIZE                  2048
 112 #define RSET_ENETDMA_SIZE               2048
 113 #define RSET_UART_SIZE                  24
 114 #define RSET_SPI_SIZE                   256
 115 #define RSET_UDC_SIZE                   256
 116 #define RSET_OHCI_SIZE                  256
 117 #define RSET_EHCI_SIZE                  256
 118 #define RSET_PCMCIA_SIZE                12
 119
 120 /*
 121  * 6338 register sets base address
 122  */
 123
 124 #define BCM_6338_DSL_LMEM_BASE          (0xfff00000)
 125 #define BCM_6338_PERF_BASE              (0xfffe0000)
 126 #define BCM_6338_BB_BASE                (0xfffe0100)
 127 #define BCM_6338_TIMER_BASE             (0xfffe0200)
 128 #define BCM_6338_WDT_BASE               (0xfffe021c)
 129 #define BCM_6338_UART0_BASE             (0xfffe0300)
 130 #define BCM_6338_GPIO_BASE              (0xfffe0400)
 131 #define BCM_6338_SPI_BASE               (0xfffe0c00)
 132 #define BCM_6338_UDC0_BASE              (0xdeadbeef)
 133 #define BCM_6338_USBDMA_BASE            (0xfffe2400)
 134 #define BCM_6338_OHCI0_BASE             (0xdeadbeef)
 135 #define BCM_6338_OHCI_PRIV_BASE         (0xfffe3000)
 136 #define BCM_6338_USBH_PRIV_BASE         (0xdeadbeef)
 137 #define BCM_6338_MPI_BASE               (0xfffe3160)
 138 #define BCM_6338_PCMCIA_BASE            (0xdeadbeef)
 139 #define BCM_6338_SDRAM_REGS_BASE        (0xfffe3100)
 140 #define BCM_6338_DSL_BASE               (0xfffe1000)
 141 #define BCM_6338_SAR_BASE               (0xfffe2000)
 142 #define BCM_6338_UBUS_BASE              (0xdeadbeef)
 143 #define BCM_6338_ENET0_BASE             (0xfffe2800)
 144 #define BCM_6338_ENET1_BASE             (0xdeadbeef)
 145 #define BCM_6338_ENETDMA_BASE           (0xfffe2400)
 146 #define BCM_6338_EHCI0_BASE             (0xdeadbeef)
 147 #define BCM_6338_SDRAM_BASE             (0xfffe3100)
 148 #define BCM_6338_MEMC_BASE              (0xdeadbeef)
 149 #define BCM_6338_DDR_BASE               (0xdeadbeef)
 150
 151 /*
 152  * 6345 register sets base address
 153  */
 154 #define BCM_6345_DSL_LMEM_BASE          (0xfff00000)
 155 #define BCM_6345_PERF_BASE              (0xfffe0000)
 156 #define BCM_6345_BB_BASE                (0xfffe0100)
 157 #define BCM_6345_TIMER_BASE             (0xfffe0200)
 158 #define BCM_6345_WDT_BASE               (0xfffe021c)
 159 #define BCM_6345_UART0_BASE             (0xfffe0300)
 160 #define BCM_6345_GPIO_BASE              (0xfffe0400)
 161 #define BCM_6345_SPI_BASE               (0xdeadbeef)
 162 #define BCM_6345_UDC0_BASE              (0xdeadbeef)
 163 #define BCM_6345_USBDMA_BASE            (0xfffe2800)
 164 #define BCM_6345_ENET0_BASE             (0xfffe1800)
 165 #define BCM_6345_ENETDMA_BASE           (0xfffe2800)
 166 #define BCM_6345_PCMCIA_BASE            (0xfffe2028)
 167 #define BCM_6345_MPI_BASE               (0xdeadbeef)
 168 #define BCM_6345_OHCI0_BASE             (0xfffe2100)
 169 #define BCM_6345_OHCI_PRIV_BASE         (0xfffe2200)
 170 #define BCM_6345_USBH_PRIV_BASE         (0xdeadbeef)
 171 #define BCM_6345_SDRAM_REGS_BASE        (0xfffe2300)
 172 #define BCM_6345_DSL_BASE               (0xdeadbeef)
 173 #define BCM_6345_SAR_BASE               (0xdeadbeef)
 174 #define BCM_6345_UBUS_BASE              (0xdeadbeef)
 175 #define BCM_6345_ENET1_BASE             (0xdeadbeef)
 176 #define BCM_6345_EHCI0_BASE             (0xdeadbeef)
 177 #define BCM_6345_SDRAM_BASE             (0xfffe2300)
 178 #define BCM_6345_MEMC_BASE              (0xdeadbeef)
 179 #define BCM_6345_DDR_BASE               (0xdeadbeef)
 180
 181 /*
 182  * 6348 register sets base address
 183  */
 184 #define BCM_6348_DSL_LMEM_BASE          (0xfff00000)
 185 #define BCM_6348_PERF_BASE              (0xfffe0000)
 186 #define BCM_6348_BB_BASE                (0xfffe0100)
 187 #define BCM_6348_TIMER_BASE             (0xfffe0200)
 188 #define BCM_6348_WDT_BASE               (0xfffe021c)
 189 #define BCM_6348_UART0_BASE             (0xfffe0300)
 190 #define BCM_6348_GPIO_BASE              (0xfffe0400)
 191 #define BCM_6348_SPI_BASE               (0xfffe0c00)
 192 #define BCM_6348_UDC0_BASE              (0xfffe1000)
 193 #define BCM_6348_USBDMA_BASE            (0xfffe1400)
 194 #define BCM_6348_OHCI0_BASE             (0xfffe1b00)
 195 #define BCM_6348_OHCI_PRIV_BASE         (0xfffe1c00)
 196 #define BCM_6348_USBH_PRIV_BASE         (0xdeadbeef)
 197 #define BCM_6348_MPI_BASE               (0xfffe2000)
 198 #define BCM_6348_PCMCIA_BASE            (0xfffe2054)
 199 #define BCM_6348_SDRAM_REGS_BASE        (0xfffe2300)
 200 #define BCM_6348_DSL_BASE               (0xfffe3000)
 201 #define BCM_6348_SAR_BASE               (0xfffe4000)
 202 #define BCM_6348_UBUS_BASE              (0xfffe5000)
 203 #define BCM_6348_ENET0_BASE             (0xfffe6000)
 204 #define BCM_6348_ENET1_BASE             (0xfffe6800)
 205 #define BCM_6348_ENETDMA_BASE           (0xfffe7000)
 206 #define BCM_6348_EHCI0_BASE             (0xdeadbeef)
 207 #define BCM_6348_SDRAM_BASE             (0xfffe2300)
 208 #define BCM_6348_MEMC_BASE              (0xdeadbeef)
 209 #define BCM_6348_DDR_BASE               (0xdeadbeef)
 210
 211 /*
 212  * 6358 register sets base address
 213  */
 214 #define BCM_6358_DSL_LMEM_BASE          (0xfff00000)
 215 #define BCM_6358_PERF_BASE              (0xfffe0000)
 216 #define BCM_6358_TIMER_BASE             (0xfffe0040)
 217 #define BCM_6358_WDT_BASE               (0xfffe005c)
 218 #define BCM_6358_GPIO_BASE              (0xfffe0080)
 219 #define BCM_6358_UART0_BASE             (0xfffe0100)
 220 #define BCM_6358_UDC0_BASE              (0xfffe0400)
 221 #define BCM_6358_SPI_BASE               (0xfffe0800)
 222 #define BCM_6358_MPI_BASE               (0xfffe1000)
 223 #define BCM_6358_PCMCIA_BASE            (0xfffe1054)
 224 #define BCM_6358_OHCI0_BASE             (0xfffe1400)
 225 #define BCM_6358_OHCI_PRIV_BASE         (0xdeadbeef)
 226 #define BCM_6358_USBH_PRIV_BASE         (0xfffe1500)
 227 #define BCM_6358_SDRAM_REGS_BASE        (0xfffe2300)
 228 #define BCM_6358_DSL_BASE               (0xfffe3000)
 229 #define BCM_6358_ENET0_BASE             (0xfffe4000)
 230 #define BCM_6358_ENET1_BASE             (0xfffe4800)
 231 #define BCM_6358_ENETDMA_BASE           (0xfffe5000)
 232 #define BCM_6358_EHCI0_BASE             (0xfffe1300)
 233 #define BCM_6358_SDRAM_BASE             (0xdeadbeef)
 234 #define BCM_6358_MEMC_BASE              (0xfffe1200)
 235 #define BCM_6358_DDR_BASE               (0xfffe12a0)
 236
 237
 238 extern const unsigned long *bcm63xx_regs_base;
 239
 240 static inline unsigned long bcm63xx_regset_address(enum bcm63xx_regs_set set)
 241 {
 242 #ifdef BCMCPU_RUNTIME_DETECT
 243         return bcm63xx_regs_base[set];
 244 #else
 245 #ifdef CONFIG_BCM63XX_CPU_6338
 246         switch (set) {
 247         case RSET_DSL_LMEM:
 248                 return BCM_6338_DSL_LMEM_BASE;
 249         case RSET_PERF:
 250                 return BCM_6338_PERF_BASE;
 251         case RSET_TIMER:
 252                 return BCM_6338_TIMER_BASE;
 253         case RSET_WDT:
 254                 return BCM_6338_WDT_BASE;
 255         case RSET_UART0:
 256                 return BCM_6338_UART0_BASE;
 257         case RSET_GPIO:
 258                 return BCM_6338_GPIO_BASE;
 259         case RSET_SPI:
 260                 return BCM_6338_SPI_BASE;
 261         case RSET_UDC0:
 262                 return BCM_6338_UDC0_BASE;
 263         case RSET_OHCI0:
 264                 return BCM_6338_OHCI0_BASE;
 265         case RSET_OHCI_PRIV:
 266                 return BCM_6338_OHCI_PRIV_BASE;
 267         case RSET_USBH_PRIV:
 268                 return BCM_6338_USBH_PRIV_BASE;
 269         case RSET_MPI:
 270                 return BCM_6338_MPI_BASE;
 271         case RSET_PCMCIA:
 272                 return BCM_6338_PCMCIA_BASE;
 273         case RSET_DSL:
 274                 return BCM_6338_DSL_BASE;
 275         case RSET_ENET0:
 276                 return BCM_6338_ENET0_BASE;
 277         case RSET_ENET1:
 278                 return BCM_6338_ENET1_BASE;
 279         case RSET_ENETDMA:
 280                 return BCM_6338_ENETDMA_BASE;
 281         case RSET_EHCI0:
 282                 return BCM_6338_EHCI0_BASE;
 283         case RSET_SDRAM:
 284                 return BCM_6338_SDRAM_BASE;
 285         case RSET_MEMC:
 286                 return BCM_6338_MEMC_BASE;
 287         case RSET_DDR:
 288                 return BCM_6338_DDR_BASE;
 289         }
 290 #endif
 291 #ifdef CONFIG_BCM63XX_CPU_6345
 292         switch (set) {
 293         case RSET_DSL_LMEM:
 294                 return BCM_6345_DSL_LMEM_BASE;
 295         case RSET_PERF:
 296                 return BCM_6345_PERF_BASE;
 297         case RSET_TIMER:
 298                 return BCM_6345_TIMER_BASE;
 299         case RSET_WDT:
 300                 return BCM_6345_WDT_BASE;
 301         case RSET_UART0:
 302                 return BCM_6345_UART0_BASE;
 303         case RSET_GPIO:
 304                 return BCM_6345_GPIO_BASE;
 305         case RSET_SPI_BASE:
 306                 return BCM_6345_SPI_BASE;
 307         case RSET_UDC0:
 308                 return BCM_6345_UDC0_BASE;
 309         case RSET_OHCI0:
 310                 return BCM_6345_OHCI0_BASE;
 311         case RSET_OHCI_PRIV:
 312                 return BCM_6345_OHCI_PRIV_BASE;
 313         case RSET_USBH_PRIV:
 314                 return BCM_6345_USBH_PRIV_BASE;
 315         case RSET_MPI:
 316                 return BCM_6345_MPI_BASE;
 317         case RSET_PCMCIA:
 318                 return BCM_6345_PCMCIA_BASE;
 319         case RSET_DSL:
 320                 return BCM_6345_DSL_BASE;
 321         case RSET_ENET0:
 322                 return BCM_6345_ENET0_BASE;
 323         case RSET_ENETDMA:
 324                 return BCM_6345_ENETDMA_BASE;
 325         case RSET_EHCI0:
 326                 return BCM_6345_EHCI0_BASE;
 327         case RSET_SDRAM:
 328                 return BCM_6345_SDRAM_BASE;
 329         case RSET_MEMC:
 330                 return BCM_6345_MEMC_BASE;
 331         case RSET_DDR:
 332                 return BCM_6345_DDR_BASE;
 333         }
 334 #endif
 335 #ifdef CONFIG_BCM63XX_CPU_6348
 336         switch (set) {
 337         case RSET_DSL_LMEM:
 338                 return BCM_6348_DSL_LMEM_BASE;
 339         case RSET_PERF:
 340                 return BCM_6348_PERF_BASE;
 341         case RSET_TIMER:
 342                 return BCM_6348_TIMER_BASE;
 343         case RSET_WDT:
 344                 return BCM_6348_WDT_BASE;
 345         case RSET_UART0:
 346                 return BCM_6348_UART0_BASE;
 347         case RSET_GPIO:
 348                 return BCM_6348_GPIO_BASE;
 349         case RSET_SPI:
 350                 return BCM_6348_SPI_BASE;
 351         case RSET_UDC0:
 352                 return BCM_6348_UDC0_BASE;
 353         case RSET_OHCI0:
 354                 return BCM_6348_OHCI0_BASE;
 355         case RSET_OHCI_PRIV:
 356                 return BCM_6348_OHCI_PRIV_BASE;
 357         case RSET_USBH_PRIV:
 358                 return BCM_6348_USBH_PRIV_BASE;
 359         case RSET_MPI:
 360                 return BCM_6348_MPI_BASE;
 361         case RSET_PCMCIA:
 362                 return BCM_6348_PCMCIA_BASE;
 363         case RSET_DSL:
 364                 return BCM_6348_DSL_BASE;
 365         case RSET_ENET0:
 366                 return BCM_6348_ENET0_BASE;
 367         case RSET_ENET1:
 368                 return BCM_6348_ENET1_BASE;
 369         case RSET_ENETDMA:
 370                 return BCM_6348_ENETDMA_BASE;
 371         case RSET_EHCI0:
 372                 return BCM_6348_EHCI0_BASE;
 373         case RSET_SDRAM:
 374                 return BCM_6348_SDRAM_BASE;
 375         case RSET_MEMC:
 376                 return BCM_6348_MEMC_BASE;
 377         case RSET_DDR:
 378                 return BCM_6348_DDR_BASE;
 379         }
 380 #endif
 381 #ifdef CONFIG_BCM63XX_CPU_6358
 382         switch (set) {
 383         case RSET_DSL_LMEM:
 384                 return BCM_6358_DSL_LMEM_BASE;
 385         case RSET_PERF:
 386                 return BCM_6358_PERF_BASE;
 387         case RSET_TIMER:
 388                 return BCM_6358_TIMER_BASE;
 389         case RSET_WDT:
 390                 return BCM_6358_WDT_BASE;
 391         case RSET_UART0:
 392                 return BCM_6358_UART0_BASE;
 393         case RSET_GPIO:
 394                 return BCM_6358_GPIO_BASE;
 395         case RSET_SPI:
 396                 return BCM_6358_SPI_BASE;
 397         case RSET_UDC0:
 398                 return BCM_6358_UDC0_BASE;
 399         case RSET_OHCI0:
 400                 return BCM_6358_OHCI0_BASE;
 401         case RSET_OHCI_PRIV:
 402                 return BCM_6358_OHCI_PRIV_BASE;
 403         case RSET_USBH_PRIV:
 404                 return BCM_6358_USBH_PRIV_BASE;
 405         case RSET_MPI:
 406                 return BCM_6358_MPI_BASE;
 407         case RSET_PCMCIA:
 408                 return BCM_6358_PCMCIA_BASE;
 409         case RSET_ENET0:
 410                 return BCM_6358_ENET0_BASE;
 411         case RSET_ENET1:
 412                 return BCM_6358_ENET1_BASE;
 413         case RSET_ENETDMA:
 414                 return BCM_6358_ENETDMA_BASE;
 415         case RSET_DSL:
 416                 return BCM_6358_DSL_BASE;
 417         case RSET_EHCI0:
 418                 return BCM_6358_EHCI0_BASE;
 419         case RSET_SDRAM:
 420                 return BCM_6358_SDRAM_BASE;
 421         case RSET_MEMC:
 422                 return BCM_6358_MEMC_BASE;
 423         case RSET_DDR:
 424                 return BCM_6358_DDR_BASE;
 425         }
 426 #endif
 427 #endif
 428         /* unreached */
 429         return 0;
 430 }
 431
 432 /*
 433  * SPI register layout is not compatible
 434  * accross CPU versions but it is software
 435  * compatible
 436  */
 437
 438 enum bcm63xx_regs_spi {
 439         SPI_CMD,
 440         SPI_INT_STATUS,
 441         SPI_INT_MASK_ST,
 442         SPI_INT_MASK,
 443         SPI_ST,
 444         SPI_CLK_CFG,
 445         SPI_FILL_BYTE,
 446         SPI_MSG_TAIL,
 447         SPI_RX_TAIL,
 448         SPI_MSG_CTL,
 449         SPI_MSG_DATA,
 450         SPI_RX_DATA,
 451 };
 452
 453 extern const unsigned long *bcm63xx_regs_spi;
 454
 455 static inline unsigned long bcm63xx_spireg(enum bcm63xx_regs_spi reg)
 456 {
 457 #ifdef BCMCPU_RUNTIME_DETECT
 458         return bcm63xx_regs_spi[reg];
 459 #else
 460 #ifdef CONFIG_BCM63XX_CPU_6338
 461 switch (reg) {
 462         case SPI_CMD:
 463                 return SPI_BCM_6338_SPI_CMD;
 464         case SPI_INT_STATUS:
 465                 return SPI_BCM_6338_SPI_INT_STATUS;
 466         case SPI_INT_MASK_ST:
 467                 return SPI_BCM_6338_SPI_MASK_INT_ST;
 468         case SPI_INT_MASK:
 469                 return SPI_BCM_6338_SPI_INT_MASK;
 470         case SPI_ST:
 471                 return SPI_BCM_6338_SPI_ST;
 472         case SPI_CLK_CFG:
 473                 return SPI_BCM_6338_SPI_CLK_CFG;
 474         case SPI_FILL_BYTE:
 475                 return SPI_BCM_6338_SPI_FILL_BYTE;
 476         case SPI_MSG_TAIL:
 477                 return SPI_BCM_6338_SPI_MSG_TAIL;
 478         case SPI_RX_TAIL:
 479                 return SPI_BCM_6338_SPI_RX_TAIL;
 480         case SPI_MSG_CTL:
 481                 return SPI_BCM_6338_SPI_MSG_CTL;
 482         case SPI_MSG_DATA:
 483                 return SPI_BCM_6338_SPI_MSG_DATA;
 484         case SPI_RX_DATA:
 485                 return SPI_BCM_6338_SPI_RX_DATA;
 486 }
 487 #endif
 488 #ifdef CONFIG_BCM63XX_CPU_6348
 489 switch (reg) {
 490         case SPI_CMD:
 491                 return SPI_BCM_6348_SPI_CMD;
 492         case SPI_INT_MASK_ST:
 493                 return SPI_BCM_6348_SPI_MASK_INT_ST;
 494         case SPI_INT_MASK:
 495                 return SPI_BCM_6348_SPI_INT_MASK;
 496         case SPI_INT_STATUS:
 497                 return SPI_BCM_6348_SPI_INT_STATUS;
 498         case SPI_ST:
 499                 return SPI_BCM_6348_SPI_ST;
 500         case SPI_CLK_CFG:
 501                 return SPI_BCM_6348_SPI_CLK_CFG;
 502         case SPI_FILL_BYTE:
 503                 return SPI_BCM_6348_SPI_FILL_BYTE;
 504         case SPI_MSG_TAIL:
 505                 return SPI_BCM_6348_SPI_MSG_TAIL;
 506         case SPI_RX_TAIL:
 507                 return SPI_BCM_6348_SPI_RX_TAIL;
 508         case SPI_MSG_CTL:
 509                 return SPI_BCM_6348_SPI_MSG_CTL;
 510         case SPI_MSG_DATA:
 511                 return SPI_BCM_6348_SPI_MSG_DATA;
 512         case SPI_RX_DATA:
 513                 return SPI_BCM_6348_SPI_RX_DATA;
 514 }
 515 #endif
 516 #ifdef CONFIG_BCM63XX_CPU_6358
 517 switch (reg) {
 518         case SPI_CMD:
 519                 return SPI_BCM_6358_SPI_CMD;
 520         case SPI_INT_STATUS:
 521                 return SPI_BCM_6358_SPI_INT_STATUS;
 522         case SPI_INT_MASK_ST:
 523                 return SPI_BCM_6358_SPI_MASK_INT_ST;
 524         case SPI_INT_MASK:
 525                 return SPI_BCM_6358_SPI_INT_MASK;
 526         case SPI_ST:
 527                 return SPI_BCM_6358_SPI_STATUS;
 528         case SPI_CLK_CFG:
 529                 return SPI_BCM_6358_SPI_CLK_CFG;
 530         case SPI_FILL_BYTE:
 531                 return SPI_BCM_6358_SPI_FILL_BYTE;
 532         case SPI_MSG_TAIL:
 533                 return SPI_BCM_6358_SPI_MSG_TAIL;
 534         case SPI_RX_TAIL:
 535                 return SPI_BCM_6358_SPI_RX_TAIL;
 536         case SPI_MSG_CTL:
 537                 return SPI_BCM_6358_MSG_CTL;
 538         case SPI_MSG_DATA:
 539                 return SPI_BCM_6358_SPI_MSG_DATA;
 540         case SPI_RX_DATA:
 541                 return SPI_BCM_6358_SPI_RX_DATA;
 542 }
 543 #endif
 544 #endif
 545         return 0;
 546 }
 547
 548 /*
 549  * IRQ number changes across CPU too
 550  */
 551 enum bcm63xx_irq {
 552         IRQ_TIMER = 0,
 553         IRQ_UART0,
 554         IRQ_SPI,
 555         IRQ_DSL,
 556         IRQ_UDC0,
 557         IRQ_ENET0,
 558         IRQ_ENET1,
 559         IRQ_ENET_PHY,
 560         IRQ_OHCI0,
 561         IRQ_EHCI0,
 562         IRQ_PCMCIA0,
 563         IRQ_ENET0_RXDMA,
 564         IRQ_ENET0_TXDMA,
 565         IRQ_ENET1_RXDMA,
 566         IRQ_ENET1_TXDMA,
 567         IRQ_PCI,
 568         IRQ_PCMCIA,
 569 };
 570
 571 /*
 572  * 6338 irqs
 573  */
 574 #define BCM_6338_TIMER_IRQ              (IRQ_INTERNAL_BASE + 0)
 575 #define BCM_6338_SPI_IRQ                (IRQ_INTERNAL_BASE + 1)
 576 #define BCM_6338_UART0_IRQ              (IRQ_INTERNAL_BASE + 2)
 577 #define BCM_6338_DG_IRQ                 (IRQ_INTERNAL_BASE + 4)
 578 #define BCM_6338_DSL_IRQ                (IRQ_INTERNAL_BASE + 5)
 579 #define BCM_6338_ATM_IRQ                (IRQ_INTERNAL_BASE + 6)
 580 #define BCM_6338_UDC0_IRQ               (IRQ_INTERNAL_BASE + 7)
 581 #define BCM_6338_ENET0_IRQ              (IRQ_INTERNAL_BASE + 8)
 582 #define BCM_6338_ENET_PHY_IRQ           (IRQ_INTERNAL_BASE + 9)
 583 #define BCM_6338_SDRAM_IRQ              (IRQ_INTERNAL_BASE + 10)
 584 #define BCM_6338_USB_CNTL_RX_DMA_IRQ    (IRQ_INTERNAL_BASE + 11)
 585 #define BCM_6338_USB_CNTL_TX_DMA_IRQ    (IRQ_INTERNAL_BASE + 12)
 586 #define BCM_6338_USB_BULK_RX_DMA_IRQ    (IRQ_INTERNAL_BASE + 13)
 587 #define BCM_6338_USB_BULK_TX_DMA_IRQ    (IRQ_INTERNAL_BASE + 14)
 588 #define BCM_6338_ENET0_RXDMA_IRQ        (IRQ_INTERNAL_BASE + 15)
 589 #define BCM_6338_ENET0_TXDMA_IRQ        (IRQ_INTERNAL_BASE + 16)
 590 #define BCM_6338_SDIO_IRQ               (IRQ_INTERNAL_BASE + 17)
 591
 592 /*
 593  * 6345 irqs
 594  */
 595 #define BCM_6345_TIMER_IRQ              (IRQ_INTERNAL_BASE + 0)
 596 #define BCM_6345_UART0_IRQ              (IRQ_INTERNAL_BASE + 2)
 597 #define BCM_6345_DSL_IRQ                (IRQ_INTERNAL_BASE + 3)
 598 #define BCM_6345_ATM_IRQ                (IRQ_INTERNAL_BASE + 4)
 599 #define BCM_6345_USB_IRQ                (IRQ_INTERNAL_BASE + 5)
 600 #define BCM_6345_ENET0_IRQ              (IRQ_INTERNAL_BASE + 8)
 601 #define BCM_6345_ENET_PHY_IRQ           (IRQ_INTERNAL_BASE + 12)
 602 #define BCM_6345_ENET0_RXDMA_IRQ        (IRQ_INTERNAL_BASE + 13 + 1)
 603 #define BCM_6345_ENET0_TXDMA_IRQ        (IRQ_INTERNAL_BASE + 13 + 2)
 604
 605 /*
 606  * 6348 irqs
 607  */
 608 #define BCM_6348_TIMER_IRQ              (IRQ_INTERNAL_BASE + 0)
 609 #define BCM_6348_SPI_IRQ                (IRQ_INTERNAL_BASE + 1)
 610 #define BCM_6348_UART0_IRQ              (IRQ_INTERNAL_BASE + 2)
 611 #define BCM_6348_DSL_IRQ                (IRQ_INTERNAL_BASE + 4)
 612 #define BCM_6348_UDC0_IRQ               (IRQ_INTERNAL_BASE + 6)
 613 #define BCM_6348_ENET1_IRQ              (IRQ_INTERNAL_BASE + 7)
 614 #define BCM_6348_ENET0_IRQ              (IRQ_INTERNAL_BASE + 8)
 615 #define BCM_6348_ENET_PHY_IRQ           (IRQ_INTERNAL_BASE + 9)
 616 #define BCM_6348_OHCI0_IRQ              (IRQ_INTERNAL_BASE + 12)
 617 #define BCM_6348_USB_CNTL_RX_DMA        (IRQ_INTERNAL_BASE + 14)
 618 #define BCM_6348_USB_CNTL_TX_DMA        (IRQ_INTERNAL_BASE + 15)
 619 #define BCM_6348_USB_BULK_RX_DMA        (IRQ_INTERNAL_BASE + 16)
 620 #define BCM_6348_USB_BULK_TX_DMA        (IRQ_INTERNAL_BASE + 17)
 621 #define BCM_6348_USB_ISO_RX_DMA         (IRQ_INTERNAL_BASE + 18)
 622 #define BCM_6348_USB_ISO_TX_DMA         (IRQ_INTERNAL_BASE + 19)
 623 #define BCM_6348_ENET0_RXDMA_IRQ        (IRQ_INTERNAL_BASE + 20)
 624 #define BCM_6348_ENET0_TXDMA_IRQ        (IRQ_INTERNAL_BASE + 21)
 625 #define BCM_6348_ENET1_RXDMA_IRQ        (IRQ_INTERNAL_BASE + 22)
 626 #define BCM_6348_ENET1_TXDMA_IRQ        (IRQ_INTERNAL_BASE + 23)
 627 #define BCM_6348_PCMCIA_IRQ             (IRQ_INTERNAL_BASE + 24)
 628 #define BCM_6348_PCI_IRQ                (IRQ_INTERNAL_BASE + 24)
 629
 630 /*
 631  * 6358 irqs
 632  */
 633 #define BCM_6358_TIMER_IRQ              (IRQ_INTERNAL_BASE + 0)
 634 #define BCM_6358_SPI_IRQ                (IRQ_INTERNAL_BASE + 1)
 635 #define BCM_6358_UART0_IRQ              (IRQ_INTERNAL_BASE + 2)
 636 #define BCM_6358_OHCI0_IRQ              (IRQ_INTERNAL_BASE + 5)
 637 #define BCM_6358_ENET1_IRQ              (IRQ_INTERNAL_BASE + 6)
 638 #define BCM_6358_ENET0_IRQ              (IRQ_INTERNAL_BASE + 8)
 639 #define BCM_6358_ENET_PHY_IRQ           (IRQ_INTERNAL_BASE + 9)
 640 #define BCM_6358_EHCI0_IRQ              (IRQ_INTERNAL_BASE + 10)
 641 #define BCM_6358_ENET0_RXDMA_IRQ        (IRQ_INTERNAL_BASE + 15)
 642 #define BCM_6358_ENET0_TXDMA_IRQ        (IRQ_INTERNAL_BASE + 16)
 643 #define BCM_6358_ENET1_RXDMA_IRQ        (IRQ_INTERNAL_BASE + 17)
 644 #define BCM_6358_ENET1_TXDMA_IRQ        (IRQ_INTERNAL_BASE + 18)
 645 #define BCM_6358_DSL_IRQ                (IRQ_INTERNAL_BASE + 29)
 646 #define BCM_6358_PCI_IRQ                (IRQ_INTERNAL_BASE + 31)
 647 #define BCM_6358_PCMCIA_IRQ             (IRQ_INTERNAL_BASE + 24)
 648
 649 extern const int *bcm63xx_irqs;
 650
 651 static inline int bcm63xx_get_irq_number(enum bcm63xx_irq irq)
 652 {
 653         return bcm63xx_irqs[irq];
 654 }
 655
 656 /*
 657  * return installed memory size
 658  */
 659 unsigned int bcm63xx_get_memory_size(void);
 660
 661 #endif /* !BCM63XX_CPU_H_ */