target/linux/coldfire/files-2.6.31/arch/m68k/coldfire/m547x/MCD_dma.h

   1 /*
   2  * drivers/dma/MCD_dma.h
   3  *
   4  * Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
   5  * Kurt Mahan <kmahan@freescale.com>
   6  * Shrek Wu b16972@freescale.com
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23 #ifndef _MCD_API_H
  24 #define _MCD_API_H
  25
  26 /*
  27  * Turn Execution Unit tasks ON (#define) or OFF (#undef)
  28  */
  29 #undef MCD_INCLUDE_EU
  30
  31 /*
  32  * Number of DMA channels
  33  */
  34 #define NCHANNELS 16
  35
  36 /*
  37  * Total number of variants
  38  */
  39 #ifdef MCD_INCLUDE_EU
  40 #define NUMOFVARIANTS   6
  41 #else
  42 #define NUMOFVARIANTS   4
  43 #endif
  44
  45 /*
  46  * Define sizes of the various tables
  47  */
  48 #define TASK_TABLE_SIZE     (NCHANNELS*32)
  49 #define VAR_TAB_SIZE        (128)
  50 #define CONTEXT_SAVE_SIZE   (128)
  51 #define FUNCDESC_TAB_SIZE   (256)
  52
  53 #ifdef MCD_INCLUDE_EU
  54 #define FUNCDESC_TAB_NUM    16
  55 #else
  56 #define FUNCDESC_TAB_NUM    1
  57 #endif
  58
  59
  60 #ifndef DEFINESONLY
  61
  62 /*
  63  * Portability typedefs
  64  */
  65 typedef int s32;
  66 typedef unsigned int u32;
  67 typedef short s16;
  68 typedef unsigned short u16;
  69 typedef char s8;
  70 typedef unsigned char u8;
  71
  72 /*
  73  * These structures represent the internal registers of the
  74  * multi-channel DMA
  75  */
  76 struct dmaRegs_s {
  77    u32 taskbar;         /* task table base address register */
  78    u32 currPtr;
  79    u32 endPtr;
  80    u32 varTablePtr;
  81    u16 dma_rsvd0;
  82    u16 ptdControl;      /* ptd control */
  83    u32 intPending;      /* interrupt pending register */
  84    u32 intMask;         /* interrupt mask register */
  85    u16 taskControl[16]; /* task control registers */
  86    u8  priority[32];    /* priority registers */
  87    u32 initiatorMux;    /* initiator mux control */
  88    u32 taskSize0;       /* task size control register 0. */
  89    u32 taskSize1;       /* task size control register 1. */
  90    u32 dma_rsvd1;       /* reserved */
  91    u32 dma_rsvd2;       /* reserved */
  92    u32 debugComp1;      /* debug comparator 1 */
  93    u32 debugComp2;      /* debug comparator 2 */
  94    u32 debugControl;    /* debug control */
  95    u32 debugStatus;     /* debug status */
  96    u32 ptdDebug;        /* priority task decode debug */
  97    u32 dma_rsvd3[31];   /* reserved */
  98 };
  99 typedef volatile struct dmaRegs_s dmaRegs;
 100
 101 #endif
 102
 103 /*
 104  * PTD contrl reg bits
 105  */
 106 #define PTD_CTL_TSK_PRI         0x8000
 107 #define PTD_CTL_COMM_PREFETCH   0x0001
 108
 109 /*
 110  * Task Control reg bits and field masks
 111  */
 112 #define TASK_CTL_EN             0x8000
 113 #define TASK_CTL_VALID          0x4000
 114 #define TASK_CTL_ALWAYS         0x2000
 115 #define TASK_CTL_INIT_MASK      0x1f00
 116 #define TASK_CTL_ASTRT          0x0080
 117 #define TASK_CTL_HIPRITSKEN     0x0040
 118 #define TASK_CTL_HLDINITNUM     0x0020
 119 #define TASK_CTL_ASTSKNUM_MASK  0x000f
 120
 121 /*
 122  * Priority reg bits and field masks
 123  */
 124 #define PRIORITY_HLD            0x80
 125 #define PRIORITY_PRI_MASK       0x07
 126
 127 /*
 128  * Debug Control reg bits and field masks
 129  */
 130 #define DBG_CTL_BLOCK_TASKS_MASK    0xffff0000
 131 #define DBG_CTL_AUTO_ARM            0x00008000
 132 #define DBG_CTL_BREAK               0x00004000
 133 #define DBG_CTL_COMP1_TYP_MASK      0x00003800
 134 #define DBG_CTL_COMP2_TYP_MASK      0x00000070
 135 #define DBG_CTL_EXT_BREAK           0x00000004
 136 #define DBG_CTL_INT_BREAK           0x00000002
 137
 138 /*
 139  * PTD Debug reg selector addresses
 140  * This reg must be written with a value to show the contents of
 141  * one of the desired internal register.
 142  */
 143 #define PTD_DBG_REQ             0x00
 144 /* shows the state of 31 initiators */
 145 #define PTD_DBG_TSK_VLD_INIT    0x01
 146 /* shows which 16 tasks are valid and
 147  * have initiators asserted */
 148
 149
 150 /*
 151  * General return values
 152  */
 153 #define MCD_OK                   0
 154 #define MCD_ERROR               -1
 155 #define MCD_TABLE_UNALIGNED     -2
 156 #define MCD_CHANNEL_INVALID     -3
 157
 158 /*
 159  * MCD_initDma input flags
 160  */
 161 #define MCD_RELOC_TASKS         0x00000001
 162 #define MCD_NO_RELOC_TASKS      0x00000000
 163 #define MCD_COMM_PREFETCH_EN    0x00000002
 164 /* Commbus Prefetching - MCF547x/548x ONLY */
 165
 166 /*
 167  * MCD_dmaStatus Status Values for each channel
 168  */
 169 #define MCD_NO_DMA  1
 170 /* No DMA has been requested since reset */
 171 #define MCD_IDLE    2
 172 /* DMA active, but the initiator is currently inactive */
 173 #define MCD_RUNNING 3
 174 /* DMA active, and the initiator is currently active */
 175 #define MCD_PAUSED  4
 176 /* DMA active but it is currently paused */
 177 #define MCD_HALTED  5
 178 /* the most recent DMA has been killed with MCD_killTask() */
 179 #define MCD_DONE    6
 180 /* the most recent DMA has completed. */
 181
 182
 183 /*
 184  * MCD_startDma parameter defines
 185  */
 186
 187 /*
 188  * Constants for the funcDesc parameter
 189  */
 190 /* Byte swapping: */
 191 #define MCD_NO_BYTE_SWAP    0x00045670
 192 /* to disable byte swapping. */
 193 #define MCD_BYTE_REVERSE    0x00076540
 194 /* to reverse the bytes of each u32 of the DMAed data. */
 195 #define MCD_U16_REVERSE     0x00067450
 196 /* to reverse the 16-bit halves of
 197  * each 32-bit data value being DMAed.*/
 198 #define MCD_U16_BYTE_REVERSE    0x00054760
 199 /* to reverse the byte halves of each
 200  * 16-bit half of each 32-bit data value DMAed */
 201 #define MCD_NO_BIT_REV  0x00000000
 202 /* do not reverse the bits of each byte DMAed. */
 203 #define MCD_BIT_REV     0x00088880
 204 /* reverse the bits of each byte DMAed */
 205 /* CRCing: */
 206 #define MCD_CRC16       0xc0100000
 207 /* to perform CRC-16 on DMAed data. */
 208 #define MCD_CRCCCITT    0xc0200000
 209 /* to perform CRC-CCITT on DMAed data. */
 210 #define MCD_CRC32       0xc0300000
 211 /* to perform CRC-32 on DMAed data. */
 212 #define MCD_CSUMINET    0xc0400000
 213 /* to perform internet checksums on DMAed data.*/
 214 #define MCD_NO_CSUM     0xa0000000
 215 /* to perform no checksumming. */
 216
 217 #define MCD_FUNC_NOEU1 (MCD_NO_BYTE_SWAP | MCD_NO_BIT_REV | MCD_NO_CSUM)
 218 #define MCD_FUNC_NOEU2 (MCD_NO_BYTE_SWAP | MCD_NO_CSUM)
 219
 220 /*
 221  * Constants for the flags parameter
 222  */
 223 #define MCD_TT_FLAGS_RL   0x00000001 /* Read line */
 224 #define MCD_TT_FLAGS_CW   0x00000002 /* Combine Writes */
 225 #define MCD_TT_FLAGS_SP   0x00000004
 226 /* Speculative prefetch(XLB) MCF547x/548x ONLY  */
 227 #define MCD_TT_FLAGS_PI   0x00000040 /* Precise Increment */
 228 #define MCD_TT_FLAGS_MASK 0x000000ff
 229 #define MCD_TT_FLAGS_DEF  (MCD_TT_FLAGS_RL | MCD_TT_FLAGS_CW)
 230
 231 #define MCD_SINGLE_DMA  0x00000100 /* Unchained DMA */
 232 #define MCD_CHAIN_DMA              /* TBD */
 233 #define MCD_EU_DMA                 /* TBD */
 234 #define MCD_FECTX_DMA   0x00001000 /* FEC TX ring DMA */
 235 #define MCD_FECRX_DMA   0x00002000 /* FEC RX ring DMA */
 236
 237
 238 /* these flags are valid for MCD_startDma
 239  * and the chained buffer descriptors */
 240 #define MCD_BUF_READY   0x80000000
 241 /* indicates that this buffer is now
 242  * under the DMA's control */
 243 #define MCD_WRAP        0x20000000
 244 /* to tell the FEC Dmas to wrap to the first BD */
 245 #define MCD_INTERRUPT   0x10000000
 246 /* to generate an interrupt after completion of the DMA. */
 247 #define MCD_END_FRAME   0x08000000
 248 /* tell the DMA to end the frame when transferring
 249  * last byte of data in buffer */
 250 #define MCD_CRC_RESTART 0x40000000
 251 /* to empty out the accumulated checksum
 252  prior to performing the DMA. */
 253
 254 /* Defines for the FEC buffer descriptor control/status word*/
 255 #define MCD_FEC_BUF_READY   0x8000
 256 #define MCD_FEC_WRAP        0x2000
 257 #define MCD_FEC_INTERRUPT   0x1000
 258 #define MCD_FEC_END_FRAME   0x0800
 259
 260
 261 /*
 262  * Defines for general intuitiveness
 263  */
 264
 265 #define MCD_TRUE  1
 266 #define MCD_FALSE 0
 267
 268 /*
 269  * Three different cases for destination and source.
 270  */
 271 #define MINUS1          -1
 272 #define ZERO            0
 273 #define PLUS1           1
 274
 275 #ifndef DEFINESONLY
 276
 277 /* Task Table Entry struct*/
 278 typedef struct {
 279     u32 TDTstart;   /* task descriptor table start */
 280     u32 TDTend;     /* task descriptor table end */
 281     u32 varTab;     /* variable table start */
 282     u32 FDTandFlags;    /* function descriptor table start and flags */
 283     volatile u32 descAddrAndStatus;
 284     volatile u32 modifiedVarTab;
 285     u32 contextSaveSpace;   /* context save space start */
 286     u32 literalBases;
 287 } TaskTableEntry;
 288
 289
 290 /* Chained buffer descriptor */
 291 typedef volatile struct MCD_bufDesc_struct MCD_bufDesc;
 292 struct MCD_bufDesc_struct {
 293    u32 flags;
 294 /* flags describing the DMA */
 295    u32 csumResult;
 296 /* checksum from checksumming performed since last checksum reset */
 297    s8  *srcAddr;
 298 /* the address to move data from */
 299    s8  *destAddr;
 300 /* the address to move data to */
 301    s8  *lastDestAddr;
 302 /* the last address written to */
 303    u32 dmaSize;
 304 /* the number of bytes to transfer independent of the transfer size */
 305    MCD_bufDesc *next;
 306 /* next buffer descriptor in chain */
 307    u32 info;
 308 /* private information about this descriptor;  DMA does not affect it */
 309 };
 310
 311 /* Progress Query struct */
 312 typedef volatile struct MCD_XferProg_struct {
 313    s8 *lastSrcAddr;
 314 /* the most-recent or last, post-increment source address */
 315    s8 *lastDestAddr;
 316 /* the most-recent or last, post-increment destination address */
 317    u32  dmaSize;
 318 /* the amount of data transferred for the current buffer */
 319    MCD_bufDesc *currBufDesc;
 320 /* pointer to the current buffer descriptor being DMAed */
 321 } MCD_XferProg;
 322
 323
 324 /* FEC buffer descriptor */
 325 typedef volatile struct MCD_bufDescFec_struct {
 326     u16 statCtrl;
 327     u16 length;
 328     u32 dataPointer;
 329 } MCD_bufDescFec;
 330
 331
 332 /*************************************************************************/
 333 /*
 334  * API function Prototypes  - see MCD_dmaApi.c for further notes
 335  */
 336
 337 /*
 338  * MCD_startDma starts a particular kind of DMA .
 339  */
 340 int MCD_startDma(
 341         int channel,
 342 /* the channel on which to run the DMA */
 343         s8  *srcAddr,
 344 /* the address to move data from, or buffer-descriptor address */
 345         s16 srcIncr,
 346 /* the amount to increment the source address per transfer */
 347         s8  *destAddr,
 348 /* the address to move data to */
 349         s16 destIncr,
 350 /* the amount to increment the destination address per transfer */
 351         u32 dmaSize,
 352 /* the number of bytes to transfer independent of the transfer size */
 353         u32 xferSize,
 354 /* the number bytes in of each data movement (1, 2, or 4) */
 355         u32 initiator,
 356 /* what device initiates the DMA */
 357         int priority,
 358 /* priority of the DMA */
 359         u32 flags,
 360 /* flags describing the DMA */
 361         u32 funcDesc
 362 /* a description of byte swapping, bit swapping, and CRC actions */
 363 );
 364
 365 /*
 366  * MCD_initDma() initializes the DMA API by setting up a pointer to the DMA
 367  * registers, relocating and creating the appropriate task structures, and
 368  * setting up some global settings
 369  */
 370 int MCD_initDma(dmaRegs *sDmaBarAddr, void *taskTableDest, u32 flags);
 371
 372 /*
 373  * MCD_dmaStatus() returns the status of the DMA on the requested channel.
 374  */
 375 int MCD_dmaStatus(int channel);
 376
 377 /*
 378  * MCD_XferProgrQuery() returns progress of DMA on requested channel
 379  */
 380 int MCD_XferProgrQuery(int channel, MCD_XferProg *progRep);
 381
 382 /*
 383  * MCD_killDma() halts the DMA on the requested channel, without any
 384  * intention of resuming the DMA.
 385  */
 386 int MCD_killDma(int channel);
 387
 388 /*
 389  * MCD_continDma() continues a DMA which as stopped due to encountering an
 390  * unready buffer descriptor.
 391  */
 392 int MCD_continDma(int channel);
 393
 394 /*
 395  * MCD_pauseDma() pauses the DMA on the given channel ( if any DMA is
 396  * running on that channel).
 397  */
 398 int MCD_pauseDma(int channel);
 399
 400 /*
 401  * MCD_resumeDma() resumes the DMA on a given channel (if any DMA is
 402  * running on that channel).
 403  */
 404 int MCD_resumeDma(int channel);
 405
 406 /*
 407  * MCD_csumQuery provides the checksum/CRC after performing a non-chained DMA
 408  */
 409 int MCD_csumQuery(int channel, u32 *csum);
 410
 411 /*
 412  * MCD_getCodeSize provides the packed size required by the microcoded task
 413  * and structures.
 414  */
 415 int MCD_getCodeSize(void);
 416
 417 /*
 418  * MCD_getVersion provides a pointer to a version string and returns a
 419  * version number.
 420  */
 421 int MCD_getVersion(char **longVersion);
 422
 423 /* macro for setting a location in the variable table */
 424 #define MCD_SET_VAR(taskTab, idx, value) \
 425         ((u32 *)(taskTab)->varTab)[idx] = value
 426    /* Note that MCD_SET_VAR() is invoked many times in firing up a DMA function,
 427       so I'm avoiding surrounding it with "do {} while(0)" */
 428
 429 #endif  /* DEFINESONLY */
 430
 431 #endif /* _MCD_API_H */