2 * Copyright 2007-2009 Freescale Semiconductor, Inc. All Rights Reserved.
4 * Purpose: Register and bit definitions for the MCF548X
10 #ifndef __MCF548X_PSC_H__
11 #define __MCF548X_PSC_H__
13 /*********************************************************************
15 * Programmable Serial Controller (PSC)
17 *********************************************************************/
19 /* Register read/write macros */
20 #define MCF_PSC_MR0 MCF_REG08(0x008600)
21 #define MCF_PSC_SR0 MCF_REG16(0x008604)
22 #define MCF_PSC_CSR0 MCF_REG08(0x008604)
23 #define MCF_PSC_CR0 MCF_REG08(0x008608)
24 #define MCF_PSC_RB0 MCF_REG32(0x00860C)
25 #define MCF_PSC_TB0 MCF_REG32(0x00860C)
26 #define MCF_PSC_TB_8BIT0 MCF_REG32(0x00860C)
27 #define MCF_PSC_TB_16BIT0 MCF_REG32(0x00860C)
28 #define MCF_PSC_TB_AC970 MCF_REG32(0x00860C)
29 #define MCF_PSC_IPCR0 MCF_REG08(0x008610)
30 #define MCF_PSC_ACR0 MCF_REG08(0x008610)
31 #define MCF_PSC_ISR0 MCF_REG16(0x008614)
32 #define MCF_PSC_IMR0 MCF_REG16(0x008614)
33 #define MCF_PSC_CTUR0 MCF_REG08(0x008618)
34 #define MCF_PSC_CTLR0 MCF_REG08(0x00861C)
35 #define MCF_PSC_IP0 MCF_REG08(0x008634)
36 #define MCF_PSC_OPSET0 MCF_REG08(0x008638)
37 #define MCF_PSC_OPRESET0 MCF_REG08(0x00863C)
38 #define MCF_PSC_SICR0 MCF_REG08(0x008640)
39 #define MCF_PSC_IRCR10 MCF_REG08(0x008644)
40 #define MCF_PSC_IRCR20 MCF_REG08(0x008648)
41 #define MCF_PSC_IRSDR0 MCF_REG08(0x00864C)
42 #define MCF_PSC_IRMDR0 MCF_REG08(0x008650)
43 #define MCF_PSC_IRFDR0 MCF_REG08(0x008654)
44 #define MCF_PSC_RFCNT0 MCF_REG16(0x008658)
45 #define MCF_PSC_TFCNT0 MCF_REG16(0x00865C)
46 #define MCF_PSC_RFSR0 MCF_REG16(0x008664)
47 #define MCF_PSC_TFSR0 MCF_REG16(0x008684)
48 #define MCF_PSC_RFCR0 MCF_REG32(0x008668)
49 #define MCF_PSC_TFCR0 MCF_REG32(0x008688)
50 #define MCF_PSC_RFAR0 MCF_REG16(0x00866E)
51 #define MCF_PSC_TFAR0 MCF_REG16(0x00868E)
52 #define MCF_PSC_RFRP0 MCF_REG16(0x008672)
53 #define MCF_PSC_TFRP0 MCF_REG16(0x008692)
54 #define MCF_PSC_RFWP0 MCF_REG16(0x008676)
55 #define MCF_PSC_TFWP0 MCF_REG16(0x008696)
56 #define MCF_PSC_RLRFP0 MCF_REG16(0x00867A)
57 #define MCF_PSC_TLRFP0 MCF_REG16(0x00869A)
58 #define MCF_PSC_RLWFP0 MCF_REG16(0x00867E)
59 #define MCF_PSC_TLWFP0 MCF_REG16(0x00869E)
60 #define MCF_PSC_MR1 MCF_REG08(0x008700)
61 #define MCF_PSC_SR1 MCF_REG16(0x008704)
62 #define MCF_PSC_CSR1 MCF_REG08(0x008704)
63 #define MCF_PSC_CR1 MCF_REG08(0x008708)
64 #define MCF_PSC_RB1 MCF_REG32(0x00870C)
65 #define MCF_PSC_TB1 MCF_REG32(0x00870C)
66 #define MCF_PSC_TB_8BIT1 MCF_REG32(0x00870C)
67 #define MCF_PSC_TB_16BIT1 MCF_REG32(0x00870C)
68 #define MCF_PSC_TB_AC971 MCF_REG32(0x00870C)
69 #define MCF_PSC_IPCR1 MCF_REG08(0x008710)
70 #define MCF_PSC_ACR1 MCF_REG08(0x008710)
71 #define MCF_PSC_ISR1 MCF_REG16(0x008714)
72 #define MCF_PSC_IMR1 MCF_REG16(0x008714)
73 #define MCF_PSC_CTUR1 MCF_REG08(0x008718)
74 #define MCF_PSC_CTLR1 MCF_REG08(0x00871C)
75 #define MCF_PSC_IP1 MCF_REG08(0x008734)
76 #define MCF_PSC_OPSET1 MCF_REG08(0x008738)
77 #define MCF_PSC_OPRESET1 MCF_REG08(0x00873C)
78 #define MCF_PSC_SICR1 MCF_REG08(0x008740)
79 #define MCF_PSC_IRCR11 MCF_REG08(0x008744)
80 #define MCF_PSC_IRCR21 MCF_REG08(0x008748)
81 #define MCF_PSC_IRSDR1 MCF_REG08(0x00874C)
82 #define MCF_PSC_IRMDR1 MCF_REG08(0x008750)
83 #define MCF_PSC_IRFDR1 MCF_REG08(0x008754)
84 #define MCF_PSC_RFCNT1 MCF_REG16(0x008758)
85 #define MCF_PSC_TFCNT1 MCF_REG16(0x00875C)
86 #define MCF_PSC_RFSR1 MCF_REG16(0x008764)
87 #define MCF_PSC_TFSR1 MCF_REG16(0x008784)
88 #define MCF_PSC_RFCR1 MCF_REG32(0x008768)
89 #define MCF_PSC_TFCR1 MCF_REG32(0x008788)
90 #define MCF_PSC_RFAR1 MCF_REG16(0x00876E)
91 #define MCF_PSC_TFAR1 MCF_REG16(0x00878E)
92 #define MCF_PSC_RFRP1 MCF_REG16(0x008772)
93 #define MCF_PSC_TFRP1 MCF_REG16(0x008792)
94 #define MCF_PSC_RFWP1 MCF_REG16(0x008776)
95 #define MCF_PSC_TFWP1 MCF_REG16(0x008796)
96 #define MCF_PSC_RLRFP1 MCF_REG16(0x00877A)
97 #define MCF_PSC_TLRFP1 MCF_REG16(0x00879A)
98 #define MCF_PSC_RLWFP1 MCF_REG16(0x00877E)
99 #define MCF_PSC_TLWFP1 MCF_REG16(0x00879E)
100 #define MCF_PSC_MR2 MCF_REG08(0x008800)
101 #define MCF_PSC_SR2 MCF_REG16(0x008804)
102 #define MCF_PSC_CSR2 MCF_REG08(0x008804)
103 #define MCF_PSC_CR2 MCF_REG08(0x008808)
104 #define MCF_PSC_RB2 MCF_REG32(0x00880C)
105 #define MCF_PSC_TB2 MCF_REG32(0x00880C)
106 #define MCF_PSC_TB_8BIT2 MCF_REG32(0x00880C)
107 #define MCF_PSC_TB_16BIT2 MCF_REG32(0x00880C)
108 #define MCF_PSC_TB_AC972 MCF_REG32(0x00880C)
109 #define MCF_PSC_IPCR2 MCF_REG08(0x008810)
110 #define MCF_PSC_ACR2 MCF_REG08(0x008810)
111 #define MCF_PSC_ISR2 MCF_REG16(0x008814)
112 #define MCF_PSC_IMR2 MCF_REG16(0x008814)
113 #define MCF_PSC_CTUR2 MCF_REG08(0x008818)
114 #define MCF_PSC_CTLR2 MCF_REG08(0x00881C)
115 #define MCF_PSC_IP2 MCF_REG08(0x008834)
116 #define MCF_PSC_OPSET2 MCF_REG08(0x008838)
117 #define MCF_PSC_OPRESET2 MCF_REG08(0x00883C)
118 #define MCF_PSC_SICR2 MCF_REG08(0x008840)
119 #define MCF_PSC_IRCR12 MCF_REG08(0x008844)
120 #define MCF_PSC_IRCR22 MCF_REG08(0x008848)
121 #define MCF_PSC_IRSDR2 MCF_REG08(0x00884C)
122 #define MCF_PSC_IRMDR2 MCF_REG08(0x008850)
123 #define MCF_PSC_IRFDR2 MCF_REG08(0x008854)
124 #define MCF_PSC_RFCNT2 MCF_REG16(0x008858)
125 #define MCF_PSC_TFCNT2 MCF_REG16(0x00885C)
126 #define MCF_PSC_RFSR2 MCF_REG16(0x008864)
127 #define MCF_PSC_TFSR2 MCF_REG16(0x008884)
128 #define MCF_PSC_RFCR2 MCF_REG32(0x008868)
129 #define MCF_PSC_TFCR2 MCF_REG32(0x008888)
130 #define MCF_PSC_RFAR2 MCF_REG16(0x00886E)
131 #define MCF_PSC_TFAR2 MCF_REG16(0x00888E)
132 #define MCF_PSC_RFRP2 MCF_REG16(0x008872)
133 #define MCF_PSC_TFRP2 MCF_REG16(0x008892)
134 #define MCF_PSC_RFWP2 MCF_REG16(0x008876)
135 #define MCF_PSC_TFWP2 MCF_REG16(0x008896)
136 #define MCF_PSC_RLRFP2 MCF_REG16(0x00887A)
137 #define MCF_PSC_TLRFP2 MCF_REG16(0x00889A)
138 #define MCF_PSC_RLWFP2 MCF_REG16(0x00887E)
139 #define MCF_PSC_TLWFP2 MCF_REG16(0x00889E)
140 #define MCF_PSC_MR3 MCF_REG08(0x008900)
141 #define MCF_PSC_SR3 MCF_REG16(0x008904)
142 #define MCF_PSC_CSR3 MCF_REG08(0x008904)
143 #define MCF_PSC_CR3 MCF_REG08(0x008908)
144 #define MCF_PSC_RB3 MCF_REG32(0x00890C)
145 #define MCF_PSC_TB3 MCF_REG32(0x00890C)
146 #define MCF_PSC_TB_8BIT3 MCF_REG32(0x00890C)
147 #define MCF_PSC_TB_16BIT3 MCF_REG32(0x00890C)
148 #define MCF_PSC_TB_AC973 MCF_REG32(0x00890C)
149 #define MCF_PSC_IPCR3 MCF_REG08(0x008910)
150 #define MCF_PSC_ACR3 MCF_REG08(0x008910)
151 #define MCF_PSC_ISR3 MCF_REG16(0x008914)
152 #define MCF_PSC_IMR3 MCF_REG16(0x008914)
153 #define MCF_PSC_CTUR3 MCF_REG08(0x008918)
154 #define MCF_PSC_CTLR3 MCF_REG08(0x00891C)
155 #define MCF_PSC_IP3 MCF_REG08(0x008934)
156 #define MCF_PSC_OPSET3 MCF_REG08(0x008938)
157 #define MCF_PSC_OPRESET3 MCF_REG08(0x00893C)
158 #define MCF_PSC_SICR3 MCF_REG08(0x008940)
159 #define MCF_PSC_IRCR13 MCF_REG08(0x008944)
160 #define MCF_PSC_IRCR23 MCF_REG08(0x008948)
161 #define MCF_PSC_IRSDR3 MCF_REG08(0x00894C)
162 #define MCF_PSC_IRMDR3 MCF_REG08(0x008950)
163 #define MCF_PSC_IRFDR3 MCF_REG08(0x008954)
164 #define MCF_PSC_RFCNT3 MCF_REG16(0x008958)
165 #define MCF_PSC_TFCNT3 MCF_REG16(0x00895C)
166 #define MCF_PSC_RFSR3 MCF_REG16(0x008964)
167 #define MCF_PSC_TFSR3 MCF_REG16(0x008984)
168 #define MCF_PSC_RFCR3 MCF_REG32(0x008968)
169 #define MCF_PSC_TFCR3 MCF_REG32(0x008988)
170 #define MCF_PSC_RFAR3 MCF_REG16(0x00896E)
171 #define MCF_PSC_TFAR3 MCF_REG16(0x00898E)
172 #define MCF_PSC_RFRP3 MCF_REG16(0x008972)
173 #define MCF_PSC_TFRP3 MCF_REG16(0x008992)
174 #define MCF_PSC_RFWP3 MCF_REG16(0x008976)
175 #define MCF_PSC_TFWP3 MCF_REG16(0x008996)
176 #define MCF_PSC_RLRFP3 MCF_REG16(0x00897A)
177 #define MCF_PSC_TLRFP3 MCF_REG16(0x00899A)
178 #define MCF_PSC_RLWFP3 MCF_REG16(0x00897E)
179 #define MCF_PSC_TLWFP3 MCF_REG16(0x00899E)
180 #define MCF_PSC_MR(x) MCF_REG08(0x008600+((x)*0x100))
181 #define MCF_PSC_SR(x) MCF_REG16(0x008604+((x)*0x100))
182 #define MCF_PSC_CSR(x) MCF_REG08(0x008604+((x)*0x100))
183 #define MCF_PSC_CR(x) MCF_REG08(0x008608+((x)*0x100))
184 #define MCF_PSC_RB(x) MCF_REG32(0x00860C+((x)*0x100))
185 #define MCF_PSC_TB(x) MCF_REG32(0x00860C+((x)*0x100))
186 #define MCF_PSC_TB_8BIT(x) MCF_REG32(0x00860C+((x)*0x100))
187 #define MCF_PSC_TB_16BIT(x) MCF_REG32(0x00860C+((x)*0x100))
188 #define MCF_PSC_TB_AC97(x) MCF_REG32(0x00860C+((x)*0x100))
189 #define MCF_PSC_IPCR(x) MCF_REG08(0x008610+((x)*0x100))
190 #define MCF_PSC_ACR(x) MCF_REG08(0x008610+((x)*0x100))
191 #define MCF_PSC_ISR(x) MCF_REG16(0x008614+((x)*0x100))
192 #define MCF_PSC_IMR(x) MCF_REG16(0x008614+((x)*0x100))
193 #define MCF_PSC_CTUR(x) MCF_REG08(0x008618+((x)*0x100))
194 #define MCF_PSC_CTLR(x) MCF_REG08(0x00861C+((x)*0x100))
195 #define MCF_PSC_IP(x) MCF_REG08(0x008634+((x)*0x100))
196 #define MCF_PSC_OPSET(x) MCF_REG08(0x008638+((x)*0x100))
197 #define MCF_PSC_OPRESET(x) MCF_REG08(0x00863C+((x)*0x100))
198 #define MCF_PSC_SICR(x) MCF_REG08(0x008640+((x)*0x100))
199 #define MCF_PSC_IRCR1(x) MCF_REG08(0x008644+((x)*0x100))
200 #define MCF_PSC_IRCR2(x) MCF_REG08(0x008648+((x)*0x100))
201 #define MCF_PSC_IRSDR(x) MCF_REG08(0x00864C+((x)*0x100))
202 #define MCF_PSC_IRMDR(x) MCF_REG08(0x008650+((x)*0x100))
203 #define MCF_PSC_IRFDR(x) MCF_REG08(0x008654+((x)*0x100))
204 #define MCF_PSC_RFCNT(x) MCF_REG16(0x008658+((x)*0x100))
205 #define MCF_PSC_TFCNT(x) MCF_REG16(0x00865C+((x)*0x100))
206 #define MCF_PSC_RFSR(x) MCF_REG16(0x008664+((x)*0x100))
207 #define MCF_PSC_TFSR(x) MCF_REG16(0x008684+((x)*0x100))
208 #define MCF_PSC_RFCR(x) MCF_REG32(0x008668+((x)*0x100))
209 #define MCF_PSC_TFCR(x) MCF_REG32(0x008688+((x)*0x100))
210 #define MCF_PSC_RFAR(x) MCF_REG16((0x00866E)+((x)*0x100))
211 #define MCF_PSC_TFAR(x) MCF_REG16((0x00868E)+((x)*0x100))
212 #define MCF_PSC_RFRP(x) MCF_REG16(0x008672+((x)*0x100))
213 #define MCF_PSC_TFRP(x) MCF_REG16(0x008692+((x)*0x100))
214 #define MCF_PSC_RFWP(x) MCF_REG16(0x008676+((x)*0x100))
215 #define MCF_PSC_TFWP(x) MCF_REG16(0x008696+((x)*0x100))
216 #define MCF_PSC_RLRFP(x) MCF_REG16(0x00867A+((x)*0x100))
217 #define MCF_PSC_TLRFP(x) MCF_REG16(0x00869A+((x)*0x100))
218 #define MCF_PSC_RLWFP(x) MCF_REG16(0x00867E+((x)*0x100))
219 #define MCF_PSC_TLWFP(x) MCF_REG16(0x00869E+((x)*0x100))
221 /* Bit definitions and macros for MCF_PSC_MR */
222 #define MCF_PSC_MR_BC(x) (((x)&0x03)<<0)
223 #define MCF_PSC_MR_PT (0x04)
224 #define MCF_PSC_MR_PM(x) (((x)&0x03)<<3)
225 #define MCF_PSC_MR_ERR (0x20)
226 #define MCF_PSC_MR_RXIRQ (0x40)
227 #define MCF_PSC_MR_RXRTS (0x80)
228 #define MCF_PSC_MR_SB(x) (((x)&0x0F)<<0)
229 #define MCF_PSC_MR_TXCTS (0x10)
230 #define MCF_PSC_MR_TXRTS (0x20)
231 #define MCF_PSC_MR_CM(x) (((x)&0x03)<<6)
232 #define MCF_PSC_MR_PM_MULTI_ADDR (0x1C)
233 #define MCF_PSC_MR_PM_MULTI_DATA (0x18)
234 #define MCF_PSC_MR_PM_NONE (0x10)
235 #define MCF_PSC_MR_PM_FORCE_HI (0x0C)
236 #define MCF_PSC_MR_PM_FORCE_LO (0x08)
237 #define MCF_PSC_MR_PM_ODD (0x04)
238 #define MCF_PSC_MR_PM_EVEN (0x00)
239 #define MCF_PSC_MR_BC_5 (0x00)
240 #define MCF_PSC_MR_BC_6 (0x01)
241 #define MCF_PSC_MR_BC_7 (0x02)
242 #define MCF_PSC_MR_BC_8 (0x03)
243 #define MCF_PSC_MR_CM_NORMAL (0x00)
244 #define MCF_PSC_MR_CM_ECHO (0x40)
245 #define MCF_PSC_MR_CM_LOCAL_LOOP (0x80)
246 #define MCF_PSC_MR_CM_REMOTE_LOOP (0xC0)
247 #define MCF_PSC_MR_SB_STOP_BITS_1 (0x07)
248 #define MCF_PSC_MR_SB_STOP_BITS_15 (0x08)
249 #define MCF_PSC_MR_SB_STOP_BITS_2 (0x0F)
251 /* Bit definitions and macros for MCF_PSC_SR */
252 #define MCF_PSC_SR_ERR (0x0040)
253 #define MCF_PSC_SR_CDE_DEOF (0x0080)
254 #define MCF_PSC_SR_RXRDY (0x0100)
255 #define MCF_PSC_SR_FU (0x0200)
256 #define MCF_PSC_SR_TXRDY (0x0400)
257 #define MCF_PSC_SR_TXEMP_URERR (0x0800)
258 #define MCF_PSC_SR_OE (0x1000)
259 #define MCF_PSC_SR_PE_CRCERR (0x2000)
260 #define MCF_PSC_SR_FE_PHYERR (0x4000)
261 #define MCF_PSC_SR_RB_NEOF (0x8000)
263 /* Bit definitions and macros for MCF_PSC_CSR */
264 #define MCF_PSC_CSR_TCSEL(x) (((x)&0x0F)<<0)
265 #define MCF_PSC_CSR_RCSEL(x) (((x)&0x0F)<<4)
266 #define MCF_PSC_CSR_RCSEL_SYS_CLK (0xD0)
267 #define MCF_PSC_CSR_RCSEL_CTM16 (0xE0)
268 #define MCF_PSC_CSR_RCSEL_CTM (0xF0)
269 #define MCF_PSC_CSR_TCSEL_SYS_CLK (0x0D)
270 #define MCF_PSC_CSR_TCSEL_CTM16 (0x0E)
271 #define MCF_PSC_CSR_TCSEL_CTM (0x0F)
273 /* Bit definitions and macros for MCF_PSC_CR */
274 #define MCF_PSC_CR_RXC(x) (((x)&0x03)<<0)
275 #define MCF_PSC_CR_TXC(x) (((x)&0x03)<<2)
276 #define MCF_PSC_CR_MISC(x) (((x)&0x07)<<4)
277 #define MCF_PSC_CR_NONE (0x00)
278 #define MCF_PSC_CR_STOP_BREAK (0x70)
279 #define MCF_PSC_CR_START_BREAK (0x60)
280 #define MCF_PSC_CR_BKCHGINT (0x50)
281 #define MCF_PSC_CR_RESET_ERROR (0x40)
282 #define MCF_PSC_CR_RESET_TX (0x30)
283 #define MCF_PSC_CR_RESET_RX (0x20)
284 #define MCF_PSC_CR_RESET_MR (0x10)
285 #define MCF_PSC_CR_TX_DISABLED (0x08)
286 #define MCF_PSC_CR_TX_ENABLED (0x04)
287 #define MCF_PSC_CR_RX_DISABLED (0x02)
288 #define MCF_PSC_CR_RX_ENABLED (0x01)
290 /* Bit definitions and macros for MCF_PSC_TB_8BIT */
291 #define MCF_PSC_TB_8BIT_TB3(x) (((x)&0x000000FF)<<0)
292 #define MCF_PSC_TB_8BIT_TB2(x) (((x)&0x000000FF)<<8)
293 #define MCF_PSC_TB_8BIT_TB1(x) (((x)&0x000000FF)<<16)
294 #define MCF_PSC_TB_8BIT_TB0(x) (((x)&0x000000FF)<<24)
296 /* Bit definitions and macros for MCF_PSC_TB_16BIT */
297 #define MCF_PSC_TB_16BIT_TB1(x) (((x)&0x0000FFFF)<<0)
298 #define MCF_PSC_TB_16BIT_TB0(x) (((x)&0x0000FFFF)<<16)
300 /* Bit definitions and macros for MCF_PSC_TB_AC97 */
301 #define MCF_PSC_TB_AC97_SOF (0x00000800)
302 #define MCF_PSC_TB_AC97_TB(x) (((x)&0x000FFFFF)<<12)
304 /* Bit definitions and macros for MCF_PSC_IPCR */
305 #define MCF_PSC_IPCR_RESERVED (0x0C)
306 #define MCF_PSC_IPCR_CTS (0x0D)
307 #define MCF_PSC_IPCR_D_CTS (0x1C)
308 #define MCF_PSC_IPCR_SYNC (0x8C)
310 /* Bit definitions and macros for MCF_PSC_ACR */
311 #define MCF_PSC_ACR_IEC0 (0x01)
312 #define MCF_PSC_ACR_CTMS(x) (((x)&0x07)<<4)
313 #define MCF_PSC_ACR_BRG (0x80)
315 /* Bit definitions and macros for MCF_PSC_ISR */
316 #define MCF_PSC_ISR_ERR (0x0040)
317 #define MCF_PSC_ISR_DEOF (0x0080)
318 #define MCF_PSC_ISR_TXRDY (0x0100)
319 #define MCF_PSC_ISR_RXRDY_FU (0x0200)
320 #define MCF_PSC_ISR_DB (0x0400)
321 #define MCF_PSC_ISR_IPC (0x8000)
323 /* Bit definitions and macros for MCF_PSC_IMR */
324 #define MCF_PSC_IMR_ERR (0x0040)
325 #define MCF_PSC_IMR_DEOF (0x0080)
326 #define MCF_PSC_IMR_TXRDY (0x0100)
327 #define MCF_PSC_IMR_RXRDY_FU (0x0200)
328 #define MCF_PSC_IMR_DB (0x0400)
329 #define MCF_PSC_IMR_IPC (0x8000)
331 /* Bit definitions and macros for MCF_PSC_IP */
332 #define MCF_PSC_IP_CTS (0x01)
333 #define MCF_PSC_IP_TGL (0x40)
334 #define MCF_PSC_IP_LWPR_B (0x80)
336 /* Bit definitions and macros for MCF_PSC_OPSET */
337 #define MCF_PSC_OPSET_RTS (0x01)
339 /* Bit definitions and macros for MCF_PSC_OPRESET */
340 #define MCF_PSC_OPRESET_RTS (0x01)
342 /* Bit definitions and macros for MCF_PSC_SICR */
343 #define MCF_PSC_SICR_SIM(x) (((x)&0x07)<<0)
344 #define MCF_PSC_SICR_SHDIR (0x10)
345 #define MCF_PSC_SICR_DTS (0x20)
346 #define MCF_PSC_SICR_AWR (0x40)
347 #define MCF_PSC_SICR_ACRB (0x80)
348 #define MCF_PSC_SICR_SIM_UART (0x00)
349 #define MCF_PSC_SICR_SIM_MODEM8 (0x01)
350 #define MCF_PSC_SICR_SIM_MODEM16 (0x02)
351 #define MCF_PSC_SICR_SIM_AC97 (0x03)
352 #define MCF_PSC_SICR_SIM_SIR (0x04)
353 #define MCF_PSC_SICR_SIM_MIR (0x05)
354 #define MCF_PSC_SICR_SIM_FIR (0x06)
356 /* Bit definitions and macros for MCF_PSC_IRCR1 */
357 #define MCF_PSC_IRCR1_SPUL (0x01)
358 #define MCF_PSC_IRCR1_SIPEN (0x02)
359 #define MCF_PSC_IRCR1_FD (0x04)
361 /* Bit definitions and macros for MCF_PSC_IRCR2 */
362 #define MCF_PSC_IRCR2_NXTEOF (0x01)
363 #define MCF_PSC_IRCR2_ABORT (0x02)
364 #define MCF_PSC_IRCR2_SIPREQ (0x04)
366 /* Bit definitions and macros for MCF_PSC_IRMDR */
367 #define MCF_PSC_IRMDR_M_FDIV(x) (((x)&0x7F)<<0)
368 #define MCF_PSC_IRMDR_FREQ (0x80)
370 /* Bit definitions and macros for MCF_PSC_IRFDR */
371 #define MCF_PSC_IRFDR_F_FDIV(x) (((x)&0x0F)<<0)
373 /* Bit definitions and macros for MCF_PSC_RFCNT */
374 #define MCF_PSC_RFCNT_CNT(x) (((x)&0x01FF)<<0)
376 /* Bit definitions and macros for MCF_PSC_TFCNT */
377 #define MCF_PSC_TFCNT_CNT(x) (((x)&0x01FF)<<0)
379 /* Bit definitions and macros for MCF_PSC_RFSR */
380 #define MCF_PSC_RFSR_EMT (0x0001)
381 #define MCF_PSC_RFSR_ALARM (0x0002)
382 #define MCF_PSC_RFSR_FU (0x0004)
383 #define MCF_PSC_RFSR_FRMRY (0x0008)
384 #define MCF_PSC_RFSR_OF (0x0010)
385 #define MCF_PSC_RFSR_UF (0x0020)
386 #define MCF_PSC_RFSR_RXW (0x0040)
387 #define MCF_PSC_RFSR_FAE (0x0080)
388 #define MCF_PSC_RFSR_FRM(x) (((x)&0x000F)<<8)
389 #define MCF_PSC_RFSR_TAG (0x1000)
390 #define MCF_PSC_RFSR_TXW (0x4000)
391 #define MCF_PSC_RFSR_IP (0x8000)
392 #define MCF_PSC_RFSR_FRM_BYTE0 (0x0800)
393 #define MCF_PSC_RFSR_FRM_BYTE1 (0x0400)
394 #define MCF_PSC_RFSR_FRM_BYTE2 (0x0200)
395 #define MCF_PSC_RFSR_FRM_BYTE3 (0x0100)
397 /* Bit definitions and macros for MCF_PSC_TFSR */
398 #define MCF_PSC_TFSR_EMT (0x0001)
399 #define MCF_PSC_TFSR_ALARM (0x0002)
400 #define MCF_PSC_TFSR_FU (0x0004)
401 #define MCF_PSC_TFSR_FRMRY (0x0008)
402 #define MCF_PSC_TFSR_OF (0x0010)
403 #define MCF_PSC_TFSR_UF (0x0020)
404 #define MCF_PSC_TFSR_RXW (0x0040)
405 #define MCF_PSC_TFSR_FAE (0x0080)
406 #define MCF_PSC_TFSR_FRM(x) (((x)&0x000F)<<8)
407 #define MCF_PSC_TFSR_TAG (0x1000)
408 #define MCF_PSC_TFSR_TXW (0x4000)
409 #define MCF_PSC_TFSR_IP (0x8000)
410 #define MCF_PSC_TFSR_FRM_BYTE0 (0x0800)
411 #define MCF_PSC_TFSR_FRM_BYTE1 (0x0400)
412 #define MCF_PSC_TFSR_FRM_BYTE2 (0x0200)
413 #define MCF_PSC_TFSR_FRM_BYTE3 (0x0100)
415 /* Bit definitions and macros for MCF_PSC_RFCR */
416 #define MCF_PSC_RFCR_CNTR(x) (((x)&0x0000FFFF)<<0)
417 #define MCF_PSC_RFCR_TXW_MSK (0x00040000)
418 #define MCF_PSC_RFCR_OF_MSK (0x00080000)
419 #define MCF_PSC_RFCR_UF_MSK (0x00100000)
420 #define MCF_PSC_RFCR_RXW_MSK (0x00200000)
421 #define MCF_PSC_RFCR_FAE_MSK (0x00400000)
422 #define MCF_PSC_RFCR_IP_MSK (0x00800000)
423 #define MCF_PSC_RFCR_GR(x) (((x)&0x00000007)<<24)
424 #define MCF_PSC_RFCR_FRMEN (0x08000000)
425 #define MCF_PSC_RFCR_TIMER (0x10000000)
426 #define MCF_PSC_RFCR_WRITETAG (0x20000000)
427 #define MCF_PSC_RFCR_SHADOW (0x80000000)
429 /* Bit definitions and macros for MCF_PSC_TFCR */
430 #define MCF_PSC_TFCR_CNTR(x) (((x)&0x0000FFFF)<<0)
431 #define MCF_PSC_TFCR_TXW_MSK (0x00040000)
432 #define MCF_PSC_TFCR_OF_MSK (0x00080000)
433 #define MCF_PSC_TFCR_UF_MSK (0x00100000)
434 #define MCF_PSC_TFCR_RXW_MSK (0x00200000)
435 #define MCF_PSC_TFCR_FAE_MSK (0x00400000)
436 #define MCF_PSC_TFCR_IP_MSK (0x00800000)
437 #define MCF_PSC_TFCR_GR(x) (((x)&0x00000007)<<24)
438 #define MCF_PSC_TFCR_FRMEN (0x08000000)
439 #define MCF_PSC_TFCR_TIMER (0x10000000)
440 #define MCF_PSC_TFCR_WRITETAG (0x20000000)
441 #define MCF_PSC_TFCR_SHADOW (0x80000000)
443 /* Bit definitions and macros for MCF_PSC_RFAR */
444 #define MCF_PSC_RFAR_ALARM(x) (((x)&0x01FF)<<0)
446 /* Bit definitions and macros for MCF_PSC_TFAR */
447 #define MCF_PSC_TFAR_ALARM(x) (((x)&0x01FF)<<0)
449 /* Bit definitions and macros for MCF_PSC_RFRP */
450 #define MCF_PSC_RFRP_READ(x) (((x)&0x01FF)<<0)
452 /* Bit definitions and macros for MCF_PSC_TFRP */
453 #define MCF_PSC_TFRP_READ(x) (((x)&0x01FF)<<0)
455 /* Bit definitions and macros for MCF_PSC_RFWP */
456 #define MCF_PSC_RFWP_WRITE(x) (((x)&0x01FF)<<0)
458 /* Bit definitions and macros for MCF_PSC_TFWP */
459 #define MCF_PSC_TFWP_WRITE(x) (((x)&0x01FF)<<0)
461 /* Bit definitions and macros for MCF_PSC_RLRFP */
462 #define MCF_PSC_RLRFP_LFP(x) (((x)&0x01FF)<<0)
464 /* Bit definitions and macros for MCF_PSC_TLRFP */
465 #define MCF_PSC_TLRFP_LFP(x) (((x)&0x01FF)<<0)
467 /* Bit definitions and macros for MCF_PSC_RLWFP */
468 #define MCF_PSC_RLWFP_LFP(x) (((x)&0x01FF)<<0)
470 /* Bit definitions and macros for MCF_PSC_TLWFP */
471 #define MCF_PSC_TLWFP_LFP(x) (((x)&0x01FF)<<0)
473 /********************************************************************/
475 #endif /* __MCF548X_PSC_H__ */
projects / openwrt / staging / lynxis / omap.git / blob