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3091fffcf097b013e2f79ded8106ad7bda43997e
[openwrt/staging/wigyori.git] / target / linux / generic / files / drivers / net / phy / ar8216.c
1 /*
2 * ar8216.c: AR8216 switch driver
3 *
4 * Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18 #include <linux/if.h>
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/if_ether.h>
23 #include <linux/skbuff.h>
24 #include <linux/netdevice.h>
25 #include <linux/netlink.h>
26 #include <linux/bitops.h>
27 #include <net/genetlink.h>
28 #include <linux/switch.h>
29 #include <linux/delay.h>
30 #include <linux/phy.h>
31 #include <linux/netdevice.h>
32 #include <linux/etherdevice.h>
33 #include <linux/lockdep.h>
34 #include <linux/ar8216_platform.h>
35 #include <linux/workqueue.h>
36 #include <linux/of_device.h>
37 #include <linux/leds.h>
38 #include <linux/gpio.h>
39 #include <linux/version.h>
40
41 #include "ar8216.h"
42
43 /* size of the vlan table */
44 #define AR8X16_MAX_VLANS 128
45 #define AR8X16_PROBE_RETRIES 10
46 #define AR8X16_MAX_PORTS 8
47
48 #define AR8XXX_MIB_WORK_DELAY 2000 /* msecs */
49
50 struct ar8xxx_priv;
51
52 #define AR8XXX_CAP_GIGE BIT(0)
53 #define AR8XXX_CAP_MIB_COUNTERS BIT(1)
54
55 #define AR8XXX_NUM_PHYS 5
56
57 static void ar8216_set_mirror_regs(struct ar8xxx_priv *priv);
58 static void ar8327_set_mirror_regs(struct ar8xxx_priv *priv);
59
60 enum {
61 AR8XXX_VER_AR8216 = 0x01,
62 AR8XXX_VER_AR8236 = 0x03,
63 AR8XXX_VER_AR8316 = 0x10,
64 AR8XXX_VER_AR8327 = 0x12,
65 AR8XXX_VER_AR8337 = 0x13,
66 };
67
68 struct ar8xxx_mib_desc {
69 unsigned int size;
70 unsigned int offset;
71 const char *name;
72 };
73
74 struct ar8xxx_chip {
75 unsigned long caps;
76 bool config_at_probe;
77
78 int (*hw_init)(struct ar8xxx_priv *priv);
79 void (*cleanup)(struct ar8xxx_priv *priv);
80
81 void (*init_globals)(struct ar8xxx_priv *priv);
82 void (*init_port)(struct ar8xxx_priv *priv, int port);
83 void (*setup_port)(struct ar8xxx_priv *priv, int port, u32 members);
84 u32 (*read_port_status)(struct ar8xxx_priv *priv, int port);
85 int (*atu_flush)(struct ar8xxx_priv *priv);
86 void (*vtu_flush)(struct ar8xxx_priv *priv);
87 void (*vtu_load_vlan)(struct ar8xxx_priv *priv, u32 vid, u32 port_mask);
88 void (*phy_fixup)(struct ar8xxx_priv *priv, int phy);
89 void (*set_mirror_regs)(struct ar8xxx_priv *priv);
90
91 const struct ar8xxx_mib_desc *mib_decs;
92 unsigned num_mibs;
93 unsigned mib_func;
94 };
95
96 enum ar8327_led_pattern {
97 AR8327_LED_PATTERN_OFF = 0,
98 AR8327_LED_PATTERN_BLINK,
99 AR8327_LED_PATTERN_ON,
100 AR8327_LED_PATTERN_RULE,
101 };
102
103 struct ar8327_led_entry {
104 unsigned reg;
105 unsigned shift;
106 };
107
108 struct ar8327_led {
109 struct led_classdev cdev;
110 struct ar8xxx_priv *sw_priv;
111
112 char *name;
113 bool active_low;
114 u8 led_num;
115 enum ar8327_led_mode mode;
116
117 struct mutex mutex;
118 spinlock_t lock;
119 struct work_struct led_work;
120 bool enable_hw_mode;
121 enum ar8327_led_pattern pattern;
122 };
123
124 struct ar8327_data {
125 u32 port0_status;
126 u32 port6_status;
127
128 struct ar8327_led **leds;
129 unsigned int num_leds;
130 };
131
132 struct ar8xxx_priv {
133 struct switch_dev dev;
134 struct mii_bus *mii_bus;
135 struct phy_device *phy;
136
137 u32 (*read)(struct ar8xxx_priv *priv, int reg);
138 void (*write)(struct ar8xxx_priv *priv, int reg, u32 val);
139 u32 (*rmw)(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val);
140
141 int (*get_port_link)(unsigned port);
142
143 const struct net_device_ops *ndo_old;
144 struct net_device_ops ndo;
145 struct mutex reg_mutex;
146 u8 chip_ver;
147 u8 chip_rev;
148 const struct ar8xxx_chip *chip;
149 void *chip_data;
150 bool initialized;
151 bool port4_phy;
152 char buf[2048];
153
154 bool init;
155 bool mii_lo_first;
156
157 struct mutex mib_lock;
158 struct delayed_work mib_work;
159 int mib_next_port;
160 u64 *mib_stats;
161
162 struct list_head list;
163 unsigned int use_count;
164
165 /* all fields below are cleared on reset */
166 bool vlan;
167 u16 vlan_id[AR8X16_MAX_VLANS];
168 u8 vlan_table[AR8X16_MAX_VLANS];
169 u8 vlan_tagged;
170 u16 pvid[AR8X16_MAX_PORTS];
171
172 /* mirroring */
173 bool mirror_rx;
174 bool mirror_tx;
175 int source_port;
176 int monitor_port;
177 };
178
179 #define MIB_DESC(_s , _o, _n) \
180 { \
181 .size = (_s), \
182 .offset = (_o), \
183 .name = (_n), \
184 }
185
186 static const struct ar8xxx_mib_desc ar8216_mibs[] = {
187 MIB_DESC(1, AR8216_STATS_RXBROAD, "RxBroad"),
188 MIB_DESC(1, AR8216_STATS_RXPAUSE, "RxPause"),
189 MIB_DESC(1, AR8216_STATS_RXMULTI, "RxMulti"),
190 MIB_DESC(1, AR8216_STATS_RXFCSERR, "RxFcsErr"),
191 MIB_DESC(1, AR8216_STATS_RXALIGNERR, "RxAlignErr"),
192 MIB_DESC(1, AR8216_STATS_RXRUNT, "RxRunt"),
193 MIB_DESC(1, AR8216_STATS_RXFRAGMENT, "RxFragment"),
194 MIB_DESC(1, AR8216_STATS_RX64BYTE, "Rx64Byte"),
195 MIB_DESC(1, AR8216_STATS_RX128BYTE, "Rx128Byte"),
196 MIB_DESC(1, AR8216_STATS_RX256BYTE, "Rx256Byte"),
197 MIB_DESC(1, AR8216_STATS_RX512BYTE, "Rx512Byte"),
198 MIB_DESC(1, AR8216_STATS_RX1024BYTE, "Rx1024Byte"),
199 MIB_DESC(1, AR8216_STATS_RXMAXBYTE, "RxMaxByte"),
200 MIB_DESC(1, AR8216_STATS_RXTOOLONG, "RxTooLong"),
201 MIB_DESC(2, AR8216_STATS_RXGOODBYTE, "RxGoodByte"),
202 MIB_DESC(2, AR8216_STATS_RXBADBYTE, "RxBadByte"),
203 MIB_DESC(1, AR8216_STATS_RXOVERFLOW, "RxOverFlow"),
204 MIB_DESC(1, AR8216_STATS_FILTERED, "Filtered"),
205 MIB_DESC(1, AR8216_STATS_TXBROAD, "TxBroad"),
206 MIB_DESC(1, AR8216_STATS_TXPAUSE, "TxPause"),
207 MIB_DESC(1, AR8216_STATS_TXMULTI, "TxMulti"),
208 MIB_DESC(1, AR8216_STATS_TXUNDERRUN, "TxUnderRun"),
209 MIB_DESC(1, AR8216_STATS_TX64BYTE, "Tx64Byte"),
210 MIB_DESC(1, AR8216_STATS_TX128BYTE, "Tx128Byte"),
211 MIB_DESC(1, AR8216_STATS_TX256BYTE, "Tx256Byte"),
212 MIB_DESC(1, AR8216_STATS_TX512BYTE, "Tx512Byte"),
213 MIB_DESC(1, AR8216_STATS_TX1024BYTE, "Tx1024Byte"),
214 MIB_DESC(1, AR8216_STATS_TXMAXBYTE, "TxMaxByte"),
215 MIB_DESC(1, AR8216_STATS_TXOVERSIZE, "TxOverSize"),
216 MIB_DESC(2, AR8216_STATS_TXBYTE, "TxByte"),
217 MIB_DESC(1, AR8216_STATS_TXCOLLISION, "TxCollision"),
218 MIB_DESC(1, AR8216_STATS_TXABORTCOL, "TxAbortCol"),
219 MIB_DESC(1, AR8216_STATS_TXMULTICOL, "TxMultiCol"),
220 MIB_DESC(1, AR8216_STATS_TXSINGLECOL, "TxSingleCol"),
221 MIB_DESC(1, AR8216_STATS_TXEXCDEFER, "TxExcDefer"),
222 MIB_DESC(1, AR8216_STATS_TXDEFER, "TxDefer"),
223 MIB_DESC(1, AR8216_STATS_TXLATECOL, "TxLateCol"),
224 };
225
226 static const struct ar8xxx_mib_desc ar8236_mibs[] = {
227 MIB_DESC(1, AR8236_STATS_RXBROAD, "RxBroad"),
228 MIB_DESC(1, AR8236_STATS_RXPAUSE, "RxPause"),
229 MIB_DESC(1, AR8236_STATS_RXMULTI, "RxMulti"),
230 MIB_DESC(1, AR8236_STATS_RXFCSERR, "RxFcsErr"),
231 MIB_DESC(1, AR8236_STATS_RXALIGNERR, "RxAlignErr"),
232 MIB_DESC(1, AR8236_STATS_RXRUNT, "RxRunt"),
233 MIB_DESC(1, AR8236_STATS_RXFRAGMENT, "RxFragment"),
234 MIB_DESC(1, AR8236_STATS_RX64BYTE, "Rx64Byte"),
235 MIB_DESC(1, AR8236_STATS_RX128BYTE, "Rx128Byte"),
236 MIB_DESC(1, AR8236_STATS_RX256BYTE, "Rx256Byte"),
237 MIB_DESC(1, AR8236_STATS_RX512BYTE, "Rx512Byte"),
238 MIB_DESC(1, AR8236_STATS_RX1024BYTE, "Rx1024Byte"),
239 MIB_DESC(1, AR8236_STATS_RX1518BYTE, "Rx1518Byte"),
240 MIB_DESC(1, AR8236_STATS_RXMAXBYTE, "RxMaxByte"),
241 MIB_DESC(1, AR8236_STATS_RXTOOLONG, "RxTooLong"),
242 MIB_DESC(2, AR8236_STATS_RXGOODBYTE, "RxGoodByte"),
243 MIB_DESC(2, AR8236_STATS_RXBADBYTE, "RxBadByte"),
244 MIB_DESC(1, AR8236_STATS_RXOVERFLOW, "RxOverFlow"),
245 MIB_DESC(1, AR8236_STATS_FILTERED, "Filtered"),
246 MIB_DESC(1, AR8236_STATS_TXBROAD, "TxBroad"),
247 MIB_DESC(1, AR8236_STATS_TXPAUSE, "TxPause"),
248 MIB_DESC(1, AR8236_STATS_TXMULTI, "TxMulti"),
249 MIB_DESC(1, AR8236_STATS_TXUNDERRUN, "TxUnderRun"),
250 MIB_DESC(1, AR8236_STATS_TX64BYTE, "Tx64Byte"),
251 MIB_DESC(1, AR8236_STATS_TX128BYTE, "Tx128Byte"),
252 MIB_DESC(1, AR8236_STATS_TX256BYTE, "Tx256Byte"),
253 MIB_DESC(1, AR8236_STATS_TX512BYTE, "Tx512Byte"),
254 MIB_DESC(1, AR8236_STATS_TX1024BYTE, "Tx1024Byte"),
255 MIB_DESC(1, AR8236_STATS_TX1518BYTE, "Tx1518Byte"),
256 MIB_DESC(1, AR8236_STATS_TXMAXBYTE, "TxMaxByte"),
257 MIB_DESC(1, AR8236_STATS_TXOVERSIZE, "TxOverSize"),
258 MIB_DESC(2, AR8236_STATS_TXBYTE, "TxByte"),
259 MIB_DESC(1, AR8236_STATS_TXCOLLISION, "TxCollision"),
260 MIB_DESC(1, AR8236_STATS_TXABORTCOL, "TxAbortCol"),
261 MIB_DESC(1, AR8236_STATS_TXMULTICOL, "TxMultiCol"),
262 MIB_DESC(1, AR8236_STATS_TXSINGLECOL, "TxSingleCol"),
263 MIB_DESC(1, AR8236_STATS_TXEXCDEFER, "TxExcDefer"),
264 MIB_DESC(1, AR8236_STATS_TXDEFER, "TxDefer"),
265 MIB_DESC(1, AR8236_STATS_TXLATECOL, "TxLateCol"),
266 };
267
268 static DEFINE_MUTEX(ar8xxx_dev_list_lock);
269 static LIST_HEAD(ar8xxx_dev_list);
270
271 static inline struct ar8xxx_priv *
272 swdev_to_ar8xxx(struct switch_dev *swdev)
273 {
274 return container_of(swdev, struct ar8xxx_priv, dev);
275 }
276
277 static inline bool ar8xxx_has_gige(struct ar8xxx_priv *priv)
278 {
279 return priv->chip->caps & AR8XXX_CAP_GIGE;
280 }
281
282 static inline bool ar8xxx_has_mib_counters(struct ar8xxx_priv *priv)
283 {
284 return priv->chip->caps & AR8XXX_CAP_MIB_COUNTERS;
285 }
286
287 static inline bool chip_is_ar8216(struct ar8xxx_priv *priv)
288 {
289 return priv->chip_ver == AR8XXX_VER_AR8216;
290 }
291
292 static inline bool chip_is_ar8236(struct ar8xxx_priv *priv)
293 {
294 return priv->chip_ver == AR8XXX_VER_AR8236;
295 }
296
297 static inline bool chip_is_ar8316(struct ar8xxx_priv *priv)
298 {
299 return priv->chip_ver == AR8XXX_VER_AR8316;
300 }
301
302 static inline bool chip_is_ar8327(struct ar8xxx_priv *priv)
303 {
304 return priv->chip_ver == AR8XXX_VER_AR8327;
305 }
306
307 static inline bool chip_is_ar8337(struct ar8xxx_priv *priv)
308 {
309 return priv->chip_ver == AR8XXX_VER_AR8337;
310 }
311
312 static inline void
313 split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
314 {
315 regaddr >>= 1;
316 *r1 = regaddr & 0x1e;
317
318 regaddr >>= 5;
319 *r2 = regaddr & 0x7;
320
321 regaddr >>= 3;
322 *page = regaddr & 0x1ff;
323 }
324
325 /* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */
326 static int
327 ar8xxx_phy_poll_reset(struct mii_bus *bus)
328 {
329 unsigned int sleep_msecs = 20;
330 int ret, elapsed, i;
331
332 for (elapsed = sleep_msecs; elapsed <= 600;
333 elapsed += sleep_msecs) {
334 msleep(sleep_msecs);
335 for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
336 ret = mdiobus_read(bus, i, MII_BMCR);
337 if (ret < 0)
338 return ret;
339 if (ret & BMCR_RESET)
340 break;
341 if (i == AR8XXX_NUM_PHYS - 1) {
342 usleep_range(1000, 2000);
343 return 0;
344 }
345 }
346 }
347 return -ETIMEDOUT;
348 }
349
350 static int
351 ar8xxx_phy_check_aneg(struct phy_device *phydev)
352 {
353 int ret;
354
355 if (phydev->autoneg != AUTONEG_ENABLE)
356 return 0;
357 /*
358 * BMCR_ANENABLE might have been cleared
359 * by phy_init_hw in certain kernel versions
360 * therefore check for it
361 */
362 ret = phy_read(phydev, MII_BMCR);
363 if (ret < 0)
364 return ret;
365 if (ret & BMCR_ANENABLE)
366 return 0;
367
368 dev_info(&phydev->dev, "ANEG disabled, re-enabling ...\n");
369 ret |= BMCR_ANENABLE | BMCR_ANRESTART;
370 return phy_write(phydev, MII_BMCR, ret);
371 }
372
373 static void
374 ar8xxx_phy_init(struct ar8xxx_priv *priv)
375 {
376 int i;
377 struct mii_bus *bus;
378
379 bus = priv->mii_bus;
380 for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
381 if (priv->chip->phy_fixup)
382 priv->chip->phy_fixup(priv, i);
383
384 /* initialize the port itself */
385 mdiobus_write(bus, i, MII_ADVERTISE,
386 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
387 if (ar8xxx_has_gige(priv))
388 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
389 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
390 }
391
392 ar8xxx_phy_poll_reset(bus);
393 }
394
395 static u32
396 ar8xxx_mii_read(struct ar8xxx_priv *priv, int reg)
397 {
398 struct mii_bus *bus = priv->mii_bus;
399 u16 r1, r2, page;
400 u16 lo, hi;
401
402 split_addr((u32) reg, &r1, &r2, &page);
403
404 mutex_lock(&bus->mdio_lock);
405
406 bus->write(bus, 0x18, 0, page);
407 usleep_range(1000, 2000); /* wait for the page switch to propagate */
408 lo = bus->read(bus, 0x10 | r2, r1);
409 hi = bus->read(bus, 0x10 | r2, r1 + 1);
410
411 mutex_unlock(&bus->mdio_lock);
412
413 return (hi << 16) | lo;
414 }
415
416 static void
417 ar8xxx_mii_write(struct ar8xxx_priv *priv, int reg, u32 val)
418 {
419 struct mii_bus *bus = priv->mii_bus;
420 u16 r1, r2, r3;
421 u16 lo, hi;
422
423 split_addr((u32) reg, &r1, &r2, &r3);
424 lo = val & 0xffff;
425 hi = (u16) (val >> 16);
426
427 mutex_lock(&bus->mdio_lock);
428
429 bus->write(bus, 0x18, 0, r3);
430 usleep_range(1000, 2000); /* wait for the page switch to propagate */
431 if (priv->mii_lo_first) {
432 bus->write(bus, 0x10 | r2, r1, lo);
433 bus->write(bus, 0x10 | r2, r1 + 1, hi);
434 } else {
435 bus->write(bus, 0x10 | r2, r1 + 1, hi);
436 bus->write(bus, 0x10 | r2, r1, lo);
437 }
438
439 mutex_unlock(&bus->mdio_lock);
440 }
441
442 static u32
443 ar8xxx_mii_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
444 {
445 struct mii_bus *bus = priv->mii_bus;
446 u16 r1, r2, page;
447 u16 lo, hi;
448 u32 ret;
449
450 split_addr((u32) reg, &r1, &r2, &page);
451
452 mutex_lock(&bus->mdio_lock);
453
454 bus->write(bus, 0x18, 0, page);
455 usleep_range(1000, 2000); /* wait for the page switch to propagate */
456
457 lo = bus->read(bus, 0x10 | r2, r1);
458 hi = bus->read(bus, 0x10 | r2, r1 + 1);
459
460 ret = hi << 16 | lo;
461 ret &= ~mask;
462 ret |= val;
463
464 lo = ret & 0xffff;
465 hi = (u16) (ret >> 16);
466
467 if (priv->mii_lo_first) {
468 bus->write(bus, 0x10 | r2, r1, lo);
469 bus->write(bus, 0x10 | r2, r1 + 1, hi);
470 } else {
471 bus->write(bus, 0x10 | r2, r1 + 1, hi);
472 bus->write(bus, 0x10 | r2, r1, lo);
473 }
474
475 mutex_unlock(&bus->mdio_lock);
476
477 return ret;
478 }
479
480
481 static void
482 ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,
483 u16 dbg_addr, u16 dbg_data)
484 {
485 struct mii_bus *bus = priv->mii_bus;
486
487 mutex_lock(&bus->mdio_lock);
488 bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
489 bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
490 mutex_unlock(&bus->mdio_lock);
491 }
492
493 static void
494 ar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 data)
495 {
496 struct mii_bus *bus = priv->mii_bus;
497
498 mutex_lock(&bus->mdio_lock);
499 bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
500 bus->write(bus, phy_addr, MII_ATH_MMD_DATA, data);
501 mutex_unlock(&bus->mdio_lock);
502 }
503
504 static inline u32
505 ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
506 {
507 return priv->rmw(priv, reg, mask, val);
508 }
509
510 static inline void
511 ar8xxx_reg_set(struct ar8xxx_priv *priv, int reg, u32 val)
512 {
513 priv->rmw(priv, reg, 0, val);
514 }
515
516 static int
517 ar8xxx_reg_wait(struct ar8xxx_priv *priv, u32 reg, u32 mask, u32 val,
518 unsigned timeout)
519 {
520 int i;
521
522 for (i = 0; i < timeout; i++) {
523 u32 t;
524
525 t = priv->read(priv, reg);
526 if ((t & mask) == val)
527 return 0;
528
529 usleep_range(1000, 2000);
530 }
531
532 return -ETIMEDOUT;
533 }
534
535 static int
536 ar8xxx_mib_op(struct ar8xxx_priv *priv, u32 op)
537 {
538 unsigned mib_func = priv->chip->mib_func;
539 int ret;
540
541 lockdep_assert_held(&priv->mib_lock);
542
543 /* Capture the hardware statistics for all ports */
544 ar8xxx_rmw(priv, mib_func, AR8216_MIB_FUNC, (op << AR8216_MIB_FUNC_S));
545
546 /* Wait for the capturing to complete. */
547 ret = ar8xxx_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);
548 if (ret)
549 goto out;
550
551 ret = 0;
552
553 out:
554 return ret;
555 }
556
557 static int
558 ar8xxx_mib_capture(struct ar8xxx_priv *priv)
559 {
560 return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_CAPTURE);
561 }
562
563 static int
564 ar8xxx_mib_flush(struct ar8xxx_priv *priv)
565 {
566 return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_FLUSH);
567 }
568
569 static void
570 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv *priv, int port, bool flush)
571 {
572 unsigned int base;
573 u64 *mib_stats;
574 int i;
575
576 WARN_ON(port >= priv->dev.ports);
577
578 lockdep_assert_held(&priv->mib_lock);
579
580 if (chip_is_ar8327(priv) || chip_is_ar8337(priv))
581 base = AR8327_REG_PORT_STATS_BASE(port);
582 else if (chip_is_ar8236(priv) ||
583 chip_is_ar8316(priv))
584 base = AR8236_REG_PORT_STATS_BASE(port);
585 else
586 base = AR8216_REG_PORT_STATS_BASE(port);
587
588 mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
589 for (i = 0; i < priv->chip->num_mibs; i++) {
590 const struct ar8xxx_mib_desc *mib;
591 u64 t;
592
593 mib = &priv->chip->mib_decs[i];
594 t = priv->read(priv, base + mib->offset);
595 if (mib->size == 2) {
596 u64 hi;
597
598 hi = priv->read(priv, base + mib->offset + 4);
599 t |= hi << 32;
600 }
601
602 if (flush)
603 mib_stats[i] = 0;
604 else
605 mib_stats[i] += t;
606 }
607 }
608
609 static void
610 ar8216_read_port_link(struct ar8xxx_priv *priv, int port,
611 struct switch_port_link *link)
612 {
613 u32 status;
614 u32 speed;
615
616 memset(link, '\0', sizeof(*link));
617
618 status = priv->chip->read_port_status(priv, port);
619
620 link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
621 if (link->aneg) {
622 link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
623 } else {
624 link->link = true;
625
626 if (priv->get_port_link) {
627 int err;
628
629 err = priv->get_port_link(port);
630 if (err >= 0)
631 link->link = !!err;
632 }
633 }
634
635 if (!link->link)
636 return;
637
638 link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
639 link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
640 link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
641
642 speed = (status & AR8216_PORT_STATUS_SPEED) >>
643 AR8216_PORT_STATUS_SPEED_S;
644
645 switch (speed) {
646 case AR8216_PORT_SPEED_10M:
647 link->speed = SWITCH_PORT_SPEED_10;
648 break;
649 case AR8216_PORT_SPEED_100M:
650 link->speed = SWITCH_PORT_SPEED_100;
651 break;
652 case AR8216_PORT_SPEED_1000M:
653 link->speed = SWITCH_PORT_SPEED_1000;
654 break;
655 default:
656 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
657 break;
658 }
659 }
660
661 static struct sk_buff *
662 ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)
663 {
664 struct ar8xxx_priv *priv = dev->phy_ptr;
665 unsigned char *buf;
666
667 if (unlikely(!priv))
668 goto error;
669
670 if (!priv->vlan)
671 goto send;
672
673 if (unlikely(skb_headroom(skb) < 2)) {
674 if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
675 goto error;
676 }
677
678 buf = skb_push(skb, 2);
679 buf[0] = 0x10;
680 buf[1] = 0x80;
681
682 send:
683 return skb;
684
685 error:
686 dev_kfree_skb_any(skb);
687 return NULL;
688 }
689
690 static void
691 ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)
692 {
693 struct ar8xxx_priv *priv;
694 unsigned char *buf;
695 int port, vlan;
696
697 priv = dev->phy_ptr;
698 if (!priv)
699 return;
700
701 /* don't strip the header if vlan mode is disabled */
702 if (!priv->vlan)
703 return;
704
705 /* strip header, get vlan id */
706 buf = skb->data;
707 skb_pull(skb, 2);
708
709 /* check for vlan header presence */
710 if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
711 return;
712
713 port = buf[0] & 0xf;
714
715 /* no need to fix up packets coming from a tagged source */
716 if (priv->vlan_tagged & (1 << port))
717 return;
718
719 /* lookup port vid from local table, the switch passes an invalid vlan id */
720 vlan = priv->vlan_id[priv->pvid[port]];
721
722 buf[14 + 2] &= 0xf0;
723 buf[14 + 2] |= vlan >> 8;
724 buf[15 + 2] = vlan & 0xff;
725 }
726
727 static int
728 ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
729 {
730 int timeout = 20;
731 u32 t = 0;
732
733 while (1) {
734 t = priv->read(priv, reg);
735 if ((t & mask) == val)
736 return 0;
737
738 if (timeout-- <= 0)
739 break;
740
741 udelay(10);
742 }
743
744 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
745 (unsigned int) reg, t, mask, val);
746 return -ETIMEDOUT;
747 }
748
749 static void
750 ar8216_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
751 {
752 if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
753 return;
754 if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
755 val &= AR8216_VTUDATA_MEMBER;
756 val |= AR8216_VTUDATA_VALID;
757 priv->write(priv, AR8216_REG_VTU_DATA, val);
758 }
759 op |= AR8216_VTU_ACTIVE;
760 priv->write(priv, AR8216_REG_VTU, op);
761 }
762
763 static void
764 ar8216_vtu_flush(struct ar8xxx_priv *priv)
765 {
766 ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
767 }
768
769 static void
770 ar8216_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
771 {
772 u32 op;
773
774 op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
775 ar8216_vtu_op(priv, op, port_mask);
776 }
777
778 static int
779 ar8216_atu_flush(struct ar8xxx_priv *priv)
780 {
781 int ret;
782
783 ret = ar8216_wait_bit(priv, AR8216_REG_ATU, AR8216_ATU_ACTIVE, 0);
784 if (!ret)
785 priv->write(priv, AR8216_REG_ATU, AR8216_ATU_OP_FLUSH);
786
787 return ret;
788 }
789
790 static u32
791 ar8216_read_port_status(struct ar8xxx_priv *priv, int port)
792 {
793 return priv->read(priv, AR8216_REG_PORT_STATUS(port));
794 }
795
796 static void
797 ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
798 {
799 u32 header;
800 u32 egress, ingress;
801 u32 pvid;
802
803 if (priv->vlan) {
804 pvid = priv->vlan_id[priv->pvid[port]];
805 if (priv->vlan_tagged & (1 << port))
806 egress = AR8216_OUT_ADD_VLAN;
807 else
808 egress = AR8216_OUT_STRIP_VLAN;
809 ingress = AR8216_IN_SECURE;
810 } else {
811 pvid = port;
812 egress = AR8216_OUT_KEEP;
813 ingress = AR8216_IN_PORT_ONLY;
814 }
815
816 if (chip_is_ar8216(priv) && priv->vlan && port == AR8216_PORT_CPU)
817 header = AR8216_PORT_CTRL_HEADER;
818 else
819 header = 0;
820
821 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
822 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
823 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
824 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
825 AR8216_PORT_CTRL_LEARN | header |
826 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
827 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
828
829 ar8xxx_rmw(priv, AR8216_REG_PORT_VLAN(port),
830 AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
831 AR8216_PORT_VLAN_DEFAULT_ID,
832 (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
833 (ingress << AR8216_PORT_VLAN_MODE_S) |
834 (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
835 }
836
837 static int
838 ar8216_hw_init(struct ar8xxx_priv *priv)
839 {
840 if (priv->initialized)
841 return 0;
842
843 ar8xxx_phy_init(priv);
844
845 priv->initialized = true;
846 return 0;
847 }
848
849 static void
850 ar8216_init_globals(struct ar8xxx_priv *priv)
851 {
852 /* standard atheros magic */
853 priv->write(priv, 0x38, 0xc000050e);
854
855 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
856 AR8216_GCTRL_MTU, 1518 + 8 + 2);
857 }
858
859 static void
860 ar8216_init_port(struct ar8xxx_priv *priv, int port)
861 {
862 /* Enable port learning and tx */
863 priv->write(priv, AR8216_REG_PORT_CTRL(port),
864 AR8216_PORT_CTRL_LEARN |
865 (4 << AR8216_PORT_CTRL_STATE_S));
866
867 priv->write(priv, AR8216_REG_PORT_VLAN(port), 0);
868
869 if (port == AR8216_PORT_CPU) {
870 priv->write(priv, AR8216_REG_PORT_STATUS(port),
871 AR8216_PORT_STATUS_LINK_UP |
872 (ar8xxx_has_gige(priv) ?
873 AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
874 AR8216_PORT_STATUS_TXMAC |
875 AR8216_PORT_STATUS_RXMAC |
876 (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_RXFLOW : 0) |
877 (chip_is_ar8316(priv) ? AR8216_PORT_STATUS_TXFLOW : 0) |
878 AR8216_PORT_STATUS_DUPLEX);
879 } else {
880 priv->write(priv, AR8216_REG_PORT_STATUS(port),
881 AR8216_PORT_STATUS_LINK_AUTO);
882 }
883 }
884
885 static const struct ar8xxx_chip ar8216_chip = {
886 .caps = AR8XXX_CAP_MIB_COUNTERS,
887
888 .hw_init = ar8216_hw_init,
889 .init_globals = ar8216_init_globals,
890 .init_port = ar8216_init_port,
891 .setup_port = ar8216_setup_port,
892 .read_port_status = ar8216_read_port_status,
893 .atu_flush = ar8216_atu_flush,
894 .vtu_flush = ar8216_vtu_flush,
895 .vtu_load_vlan = ar8216_vtu_load_vlan,
896 .set_mirror_regs = ar8216_set_mirror_regs,
897
898 .num_mibs = ARRAY_SIZE(ar8216_mibs),
899 .mib_decs = ar8216_mibs,
900 .mib_func = AR8216_REG_MIB_FUNC
901 };
902
903 static void
904 ar8236_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
905 {
906 u32 egress, ingress;
907 u32 pvid;
908
909 if (priv->vlan) {
910 pvid = priv->vlan_id[priv->pvid[port]];
911 if (priv->vlan_tagged & (1 << port))
912 egress = AR8216_OUT_ADD_VLAN;
913 else
914 egress = AR8216_OUT_STRIP_VLAN;
915 ingress = AR8216_IN_SECURE;
916 } else {
917 pvid = port;
918 egress = AR8216_OUT_KEEP;
919 ingress = AR8216_IN_PORT_ONLY;
920 }
921
922 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
923 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
924 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
925 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
926 AR8216_PORT_CTRL_LEARN |
927 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
928 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
929
930 ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN(port),
931 AR8236_PORT_VLAN_DEFAULT_ID,
932 (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
933
934 ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN2(port),
935 AR8236_PORT_VLAN2_VLAN_MODE |
936 AR8236_PORT_VLAN2_MEMBER,
937 (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
938 (members << AR8236_PORT_VLAN2_MEMBER_S));
939 }
940
941 static void
942 ar8236_init_globals(struct ar8xxx_priv *priv)
943 {
944 /* enable jumbo frames */
945 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
946 AR8316_GCTRL_MTU, 9018 + 8 + 2);
947
948 /* Enable MIB counters */
949 ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
950 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
951 AR8236_MIB_EN);
952 }
953
954 static const struct ar8xxx_chip ar8236_chip = {
955 .caps = AR8XXX_CAP_MIB_COUNTERS,
956 .hw_init = ar8216_hw_init,
957 .init_globals = ar8236_init_globals,
958 .init_port = ar8216_init_port,
959 .setup_port = ar8236_setup_port,
960 .read_port_status = ar8216_read_port_status,
961 .atu_flush = ar8216_atu_flush,
962 .vtu_flush = ar8216_vtu_flush,
963 .vtu_load_vlan = ar8216_vtu_load_vlan,
964 .set_mirror_regs = ar8216_set_mirror_regs,
965
966 .num_mibs = ARRAY_SIZE(ar8236_mibs),
967 .mib_decs = ar8236_mibs,
968 .mib_func = AR8216_REG_MIB_FUNC
969 };
970
971 static int
972 ar8316_hw_init(struct ar8xxx_priv *priv)
973 {
974 u32 val, newval;
975
976 val = priv->read(priv, AR8316_REG_POSTRIP);
977
978 if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
979 if (priv->port4_phy) {
980 /* value taken from Ubiquiti RouterStation Pro */
981 newval = 0x81461bea;
982 pr_info("ar8316: Using port 4 as PHY\n");
983 } else {
984 newval = 0x01261be2;
985 pr_info("ar8316: Using port 4 as switch port\n");
986 }
987 } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
988 /* value taken from AVM Fritz!Box 7390 sources */
989 newval = 0x010e5b71;
990 } else {
991 /* no known value for phy interface */
992 pr_err("ar8316: unsupported mii mode: %d.\n",
993 priv->phy->interface);
994 return -EINVAL;
995 }
996
997 if (val == newval)
998 goto out;
999
1000 priv->write(priv, AR8316_REG_POSTRIP, newval);
1001
1002 if (priv->port4_phy &&
1003 priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
1004 /* work around for phy4 rgmii mode */
1005 ar8xxx_phy_dbg_write(priv, 4, 0x12, 0x480c);
1006 /* rx delay */
1007 ar8xxx_phy_dbg_write(priv, 4, 0x0, 0x824e);
1008 /* tx delay */
1009 ar8xxx_phy_dbg_write(priv, 4, 0x5, 0x3d47);
1010 msleep(1000);
1011 }
1012
1013 ar8xxx_phy_init(priv);
1014
1015 out:
1016 priv->initialized = true;
1017 return 0;
1018 }
1019
1020 static void
1021 ar8316_init_globals(struct ar8xxx_priv *priv)
1022 {
1023 /* standard atheros magic */
1024 priv->write(priv, 0x38, 0xc000050e);
1025
1026 /* enable cpu port to receive multicast and broadcast frames */
1027 priv->write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
1028
1029 /* enable jumbo frames */
1030 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
1031 AR8316_GCTRL_MTU, 9018 + 8 + 2);
1032
1033 /* Enable MIB counters */
1034 ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
1035 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
1036 AR8236_MIB_EN);
1037 }
1038
1039 static const struct ar8xxx_chip ar8316_chip = {
1040 .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1041 .hw_init = ar8316_hw_init,
1042 .init_globals = ar8316_init_globals,
1043 .init_port = ar8216_init_port,
1044 .setup_port = ar8216_setup_port,
1045 .read_port_status = ar8216_read_port_status,
1046 .atu_flush = ar8216_atu_flush,
1047 .vtu_flush = ar8216_vtu_flush,
1048 .vtu_load_vlan = ar8216_vtu_load_vlan,
1049 .set_mirror_regs = ar8216_set_mirror_regs,
1050
1051 .num_mibs = ARRAY_SIZE(ar8236_mibs),
1052 .mib_decs = ar8236_mibs,
1053 .mib_func = AR8216_REG_MIB_FUNC
1054 };
1055
1056 static u32
1057 ar8327_get_pad_cfg(struct ar8327_pad_cfg *cfg)
1058 {
1059 u32 t;
1060
1061 if (!cfg)
1062 return 0;
1063
1064 t = 0;
1065 switch (cfg->mode) {
1066 case AR8327_PAD_NC:
1067 break;
1068
1069 case AR8327_PAD_MAC2MAC_MII:
1070 t = AR8327_PAD_MAC_MII_EN;
1071 if (cfg->rxclk_sel)
1072 t |= AR8327_PAD_MAC_MII_RXCLK_SEL;
1073 if (cfg->txclk_sel)
1074 t |= AR8327_PAD_MAC_MII_TXCLK_SEL;
1075 break;
1076
1077 case AR8327_PAD_MAC2MAC_GMII:
1078 t = AR8327_PAD_MAC_GMII_EN;
1079 if (cfg->rxclk_sel)
1080 t |= AR8327_PAD_MAC_GMII_RXCLK_SEL;
1081 if (cfg->txclk_sel)
1082 t |= AR8327_PAD_MAC_GMII_TXCLK_SEL;
1083 break;
1084
1085 case AR8327_PAD_MAC_SGMII:
1086 t = AR8327_PAD_SGMII_EN;
1087
1088 /*
1089 * WAR for the QUalcomm Atheros AP136 board.
1090 * It seems that RGMII TX/RX delay settings needs to be
1091 * applied for SGMII mode as well, The ethernet is not
1092 * reliable without this.
1093 */
1094 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
1095 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
1096 if (cfg->rxclk_delay_en)
1097 t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
1098 if (cfg->txclk_delay_en)
1099 t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
1100
1101 if (cfg->sgmii_delay_en)
1102 t |= AR8327_PAD_SGMII_DELAY_EN;
1103
1104 break;
1105
1106 case AR8327_PAD_MAC2PHY_MII:
1107 t = AR8327_PAD_PHY_MII_EN;
1108 if (cfg->rxclk_sel)
1109 t |= AR8327_PAD_PHY_MII_RXCLK_SEL;
1110 if (cfg->txclk_sel)
1111 t |= AR8327_PAD_PHY_MII_TXCLK_SEL;
1112 break;
1113
1114 case AR8327_PAD_MAC2PHY_GMII:
1115 t = AR8327_PAD_PHY_GMII_EN;
1116 if (cfg->pipe_rxclk_sel)
1117 t |= AR8327_PAD_PHY_GMII_PIPE_RXCLK_SEL;
1118 if (cfg->rxclk_sel)
1119 t |= AR8327_PAD_PHY_GMII_RXCLK_SEL;
1120 if (cfg->txclk_sel)
1121 t |= AR8327_PAD_PHY_GMII_TXCLK_SEL;
1122 break;
1123
1124 case AR8327_PAD_MAC_RGMII:
1125 t = AR8327_PAD_RGMII_EN;
1126 t |= cfg->txclk_delay_sel << AR8327_PAD_RGMII_TXCLK_DELAY_SEL_S;
1127 t |= cfg->rxclk_delay_sel << AR8327_PAD_RGMII_RXCLK_DELAY_SEL_S;
1128 if (cfg->rxclk_delay_en)
1129 t |= AR8327_PAD_RGMII_RXCLK_DELAY_EN;
1130 if (cfg->txclk_delay_en)
1131 t |= AR8327_PAD_RGMII_TXCLK_DELAY_EN;
1132 break;
1133
1134 case AR8327_PAD_PHY_GMII:
1135 t = AR8327_PAD_PHYX_GMII_EN;
1136 break;
1137
1138 case AR8327_PAD_PHY_RGMII:
1139 t = AR8327_PAD_PHYX_RGMII_EN;
1140 break;
1141
1142 case AR8327_PAD_PHY_MII:
1143 t = AR8327_PAD_PHYX_MII_EN;
1144 break;
1145 }
1146
1147 return t;
1148 }
1149
1150 static void
1151 ar8327_phy_fixup(struct ar8xxx_priv *priv, int phy)
1152 {
1153 switch (priv->chip_rev) {
1154 case 1:
1155 /* For 100M waveform */
1156 ar8xxx_phy_dbg_write(priv, phy, 0, 0x02ea);
1157 /* Turn on Gigabit clock */
1158 ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x68a0);
1159 break;
1160
1161 case 2:
1162 ar8xxx_phy_mmd_write(priv, phy, 0x7, 0x3c);
1163 ar8xxx_phy_mmd_write(priv, phy, 0x4007, 0x0);
1164 /* fallthrough */
1165 case 4:
1166 ar8xxx_phy_mmd_write(priv, phy, 0x3, 0x800d);
1167 ar8xxx_phy_mmd_write(priv, phy, 0x4003, 0x803f);
1168
1169 ar8xxx_phy_dbg_write(priv, phy, 0x3d, 0x6860);
1170 ar8xxx_phy_dbg_write(priv, phy, 0x5, 0x2c46);
1171 ar8xxx_phy_dbg_write(priv, phy, 0x3c, 0x6000);
1172 break;
1173 }
1174 }
1175
1176 static u32
1177 ar8327_get_port_init_status(struct ar8327_port_cfg *cfg)
1178 {
1179 u32 t;
1180
1181 if (!cfg->force_link)
1182 return AR8216_PORT_STATUS_LINK_AUTO;
1183
1184 t = AR8216_PORT_STATUS_TXMAC | AR8216_PORT_STATUS_RXMAC;
1185 t |= cfg->duplex ? AR8216_PORT_STATUS_DUPLEX : 0;
1186 t |= cfg->rxpause ? AR8216_PORT_STATUS_RXFLOW : 0;
1187 t |= cfg->txpause ? AR8216_PORT_STATUS_TXFLOW : 0;
1188
1189 switch (cfg->speed) {
1190 case AR8327_PORT_SPEED_10:
1191 t |= AR8216_PORT_SPEED_10M;
1192 break;
1193 case AR8327_PORT_SPEED_100:
1194 t |= AR8216_PORT_SPEED_100M;
1195 break;
1196 case AR8327_PORT_SPEED_1000:
1197 t |= AR8216_PORT_SPEED_1000M;
1198 break;
1199 }
1200
1201 return t;
1202 }
1203
1204 #define AR8327_LED_ENTRY(_num, _reg, _shift) \
1205 [_num] = { .reg = (_reg), .shift = (_shift) }
1206
1207 static const struct ar8327_led_entry
1208 ar8327_led_map[AR8327_NUM_LEDS] = {
1209 AR8327_LED_ENTRY(AR8327_LED_PHY0_0, 0, 14),
1210 AR8327_LED_ENTRY(AR8327_LED_PHY0_1, 1, 14),
1211 AR8327_LED_ENTRY(AR8327_LED_PHY0_2, 2, 14),
1212
1213 AR8327_LED_ENTRY(AR8327_LED_PHY1_0, 3, 8),
1214 AR8327_LED_ENTRY(AR8327_LED_PHY1_1, 3, 10),
1215 AR8327_LED_ENTRY(AR8327_LED_PHY1_2, 3, 12),
1216
1217 AR8327_LED_ENTRY(AR8327_LED_PHY2_0, 3, 14),
1218 AR8327_LED_ENTRY(AR8327_LED_PHY2_1, 3, 16),
1219 AR8327_LED_ENTRY(AR8327_LED_PHY2_2, 3, 18),
1220
1221 AR8327_LED_ENTRY(AR8327_LED_PHY3_0, 3, 20),
1222 AR8327_LED_ENTRY(AR8327_LED_PHY3_1, 3, 22),
1223 AR8327_LED_ENTRY(AR8327_LED_PHY3_2, 3, 24),
1224
1225 AR8327_LED_ENTRY(AR8327_LED_PHY4_0, 0, 30),
1226 AR8327_LED_ENTRY(AR8327_LED_PHY4_1, 1, 30),
1227 AR8327_LED_ENTRY(AR8327_LED_PHY4_2, 2, 30),
1228 };
1229
1230 static void
1231 ar8327_set_led_pattern(struct ar8xxx_priv *priv, unsigned int led_num,
1232 enum ar8327_led_pattern pattern)
1233 {
1234 const struct ar8327_led_entry *entry;
1235
1236 entry = &ar8327_led_map[led_num];
1237 ar8xxx_rmw(priv, AR8327_REG_LED_CTRL(entry->reg),
1238 (3 << entry->shift), pattern << entry->shift);
1239 }
1240
1241 static void
1242 ar8327_led_work_func(struct work_struct *work)
1243 {
1244 struct ar8327_led *aled;
1245 u8 pattern;
1246
1247 aled = container_of(work, struct ar8327_led, led_work);
1248
1249 spin_lock(&aled->lock);
1250 pattern = aled->pattern;
1251 spin_unlock(&aled->lock);
1252
1253 ar8327_set_led_pattern(aled->sw_priv, aled->led_num,
1254 pattern);
1255 }
1256
1257 static void
1258 ar8327_led_schedule_change(struct ar8327_led *aled, u8 pattern)
1259 {
1260 if (aled->pattern == pattern)
1261 return;
1262
1263 aled->pattern = pattern;
1264 schedule_work(&aled->led_work);
1265 }
1266
1267 static inline struct ar8327_led *
1268 led_cdev_to_ar8327_led(struct led_classdev *led_cdev)
1269 {
1270 return container_of(led_cdev, struct ar8327_led, cdev);
1271 }
1272
1273 static int
1274 ar8327_led_blink_set(struct led_classdev *led_cdev,
1275 unsigned long *delay_on,
1276 unsigned long *delay_off)
1277 {
1278 struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1279
1280 if (*delay_on == 0 && *delay_off == 0) {
1281 *delay_on = 125;
1282 *delay_off = 125;
1283 }
1284
1285 if (*delay_on != 125 || *delay_off != 125) {
1286 /*
1287 * The hardware only supports blinking at 4Hz. Fall back
1288 * to software implementation in other cases.
1289 */
1290 return -EINVAL;
1291 }
1292
1293 spin_lock(&aled->lock);
1294
1295 aled->enable_hw_mode = false;
1296 ar8327_led_schedule_change(aled, AR8327_LED_PATTERN_BLINK);
1297
1298 spin_unlock(&aled->lock);
1299
1300 return 0;
1301 }
1302
1303 static void
1304 ar8327_led_set_brightness(struct led_classdev *led_cdev,
1305 enum led_brightness brightness)
1306 {
1307 struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1308 u8 pattern;
1309 bool active;
1310
1311 active = (brightness != LED_OFF);
1312 active ^= aled->active_low;
1313
1314 pattern = (active) ? AR8327_LED_PATTERN_ON :
1315 AR8327_LED_PATTERN_OFF;
1316
1317 spin_lock(&aled->lock);
1318
1319 aled->enable_hw_mode = false;
1320 ar8327_led_schedule_change(aled, pattern);
1321
1322 spin_unlock(&aled->lock);
1323 }
1324
1325 static ssize_t
1326 ar8327_led_enable_hw_mode_show(struct device *dev,
1327 struct device_attribute *attr,
1328 char *buf)
1329 {
1330 struct led_classdev *led_cdev = dev_get_drvdata(dev);
1331 struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1332 ssize_t ret = 0;
1333
1334 spin_lock(&aled->lock);
1335 ret += sprintf(buf, "%d\n", aled->enable_hw_mode);
1336 spin_unlock(&aled->lock);
1337
1338 return ret;
1339 }
1340
1341 static ssize_t
1342 ar8327_led_enable_hw_mode_store(struct device *dev,
1343 struct device_attribute *attr,
1344 const char *buf,
1345 size_t size)
1346 {
1347 struct led_classdev *led_cdev = dev_get_drvdata(dev);
1348 struct ar8327_led *aled = led_cdev_to_ar8327_led(led_cdev);
1349 u8 pattern;
1350 u8 value;
1351 int ret;
1352
1353 ret = kstrtou8(buf, 10, &value);
1354 if (ret < 0)
1355 return -EINVAL;
1356
1357 spin_lock(&aled->lock);
1358
1359 aled->enable_hw_mode = !!value;
1360 if (aled->enable_hw_mode)
1361 pattern = AR8327_LED_PATTERN_RULE;
1362 else
1363 pattern = AR8327_LED_PATTERN_OFF;
1364
1365 ar8327_led_schedule_change(aled, pattern);
1366
1367 spin_unlock(&aled->lock);
1368
1369 return size;
1370 }
1371
1372 static DEVICE_ATTR(enable_hw_mode, S_IRUGO | S_IWUSR,
1373 ar8327_led_enable_hw_mode_show,
1374 ar8327_led_enable_hw_mode_store);
1375
1376 static int
1377 ar8327_led_register(struct ar8xxx_priv *priv, struct ar8327_led *aled)
1378 {
1379 int ret;
1380
1381 ret = led_classdev_register(NULL, &aled->cdev);
1382 if (ret < 0)
1383 return ret;
1384
1385 if (aled->mode == AR8327_LED_MODE_HW) {
1386 ret = device_create_file(aled->cdev.dev,
1387 &dev_attr_enable_hw_mode);
1388 if (ret)
1389 goto err_unregister;
1390 }
1391
1392 return 0;
1393
1394 err_unregister:
1395 led_classdev_unregister(&aled->cdev);
1396 return ret;
1397 }
1398
1399 static void
1400 ar8327_led_unregister(struct ar8327_led *aled)
1401 {
1402 if (aled->mode == AR8327_LED_MODE_HW)
1403 device_remove_file(aled->cdev.dev, &dev_attr_enable_hw_mode);
1404
1405 led_classdev_unregister(&aled->cdev);
1406 cancel_work_sync(&aled->led_work);
1407 }
1408
1409 static int
1410 ar8327_led_create(struct ar8xxx_priv *priv,
1411 const struct ar8327_led_info *led_info)
1412 {
1413 struct ar8327_data *data = priv->chip_data;
1414 struct ar8327_led *aled;
1415 int ret;
1416
1417 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
1418 return 0;
1419
1420 if (!led_info->name)
1421 return -EINVAL;
1422
1423 if (led_info->led_num >= AR8327_NUM_LEDS)
1424 return -EINVAL;
1425
1426 aled = kzalloc(sizeof(*aled) + strlen(led_info->name) + 1,
1427 GFP_KERNEL);
1428 if (!aled)
1429 return -ENOMEM;
1430
1431 aled->sw_priv = priv;
1432 aled->led_num = led_info->led_num;
1433 aled->active_low = led_info->active_low;
1434 aled->mode = led_info->mode;
1435
1436 if (aled->mode == AR8327_LED_MODE_HW)
1437 aled->enable_hw_mode = true;
1438
1439 aled->name = (char *)(aled + 1);
1440 strcpy(aled->name, led_info->name);
1441
1442 aled->cdev.name = aled->name;
1443 aled->cdev.brightness_set = ar8327_led_set_brightness;
1444 aled->cdev.blink_set = ar8327_led_blink_set;
1445 aled->cdev.default_trigger = led_info->default_trigger;
1446
1447 spin_lock_init(&aled->lock);
1448 mutex_init(&aled->mutex);
1449 INIT_WORK(&aled->led_work, ar8327_led_work_func);
1450
1451 ret = ar8327_led_register(priv, aled);
1452 if (ret)
1453 goto err_free;
1454
1455 data->leds[data->num_leds++] = aled;
1456
1457 return 0;
1458
1459 err_free:
1460 kfree(aled);
1461 return ret;
1462 }
1463
1464 static void
1465 ar8327_led_destroy(struct ar8327_led *aled)
1466 {
1467 ar8327_led_unregister(aled);
1468 kfree(aled);
1469 }
1470
1471 static void
1472 ar8327_leds_init(struct ar8xxx_priv *priv)
1473 {
1474 struct ar8327_data *data = priv->chip_data;
1475 unsigned i;
1476
1477 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
1478 return;
1479
1480 for (i = 0; i < data->num_leds; i++) {
1481 struct ar8327_led *aled;
1482
1483 aled = data->leds[i];
1484
1485 if (aled->enable_hw_mode)
1486 aled->pattern = AR8327_LED_PATTERN_RULE;
1487 else
1488 aled->pattern = AR8327_LED_PATTERN_OFF;
1489
1490 ar8327_set_led_pattern(priv, aled->led_num, aled->pattern);
1491 }
1492 }
1493
1494 static void
1495 ar8327_leds_cleanup(struct ar8xxx_priv *priv)
1496 {
1497 struct ar8327_data *data = priv->chip_data;
1498 unsigned i;
1499
1500 if (!IS_ENABLED(CONFIG_AR8216_PHY_LEDS))
1501 return;
1502
1503 for (i = 0; i < data->num_leds; i++) {
1504 struct ar8327_led *aled;
1505
1506 aled = data->leds[i];
1507 ar8327_led_destroy(aled);
1508 }
1509
1510 kfree(data->leds);
1511 }
1512
1513 static int
1514 ar8327_hw_config_pdata(struct ar8xxx_priv *priv,
1515 struct ar8327_platform_data *pdata)
1516 {
1517 struct ar8327_led_cfg *led_cfg;
1518 struct ar8327_data *data = priv->chip_data;
1519 u32 pos, new_pos;
1520 u32 t;
1521
1522 if (!pdata)
1523 return -EINVAL;
1524
1525 priv->get_port_link = pdata->get_port_link;
1526
1527 data->port0_status = ar8327_get_port_init_status(&pdata->port0_cfg);
1528 data->port6_status = ar8327_get_port_init_status(&pdata->port6_cfg);
1529
1530 t = ar8327_get_pad_cfg(pdata->pad0_cfg);
1531 if (chip_is_ar8337(priv))
1532 t |= AR8337_PAD_MAC06_EXCHANGE_EN;
1533
1534 priv->write(priv, AR8327_REG_PAD0_MODE, t);
1535 t = ar8327_get_pad_cfg(pdata->pad5_cfg);
1536 priv->write(priv, AR8327_REG_PAD5_MODE, t);
1537 t = ar8327_get_pad_cfg(pdata->pad6_cfg);
1538 priv->write(priv, AR8327_REG_PAD6_MODE, t);
1539
1540 pos = priv->read(priv, AR8327_REG_POWER_ON_STRIP);
1541 new_pos = pos;
1542
1543 led_cfg = pdata->led_cfg;
1544 if (led_cfg) {
1545 if (led_cfg->open_drain)
1546 new_pos |= AR8327_POWER_ON_STRIP_LED_OPEN_EN;
1547 else
1548 new_pos &= ~AR8327_POWER_ON_STRIP_LED_OPEN_EN;
1549
1550 priv->write(priv, AR8327_REG_LED_CTRL0, led_cfg->led_ctrl0);
1551 priv->write(priv, AR8327_REG_LED_CTRL1, led_cfg->led_ctrl1);
1552 priv->write(priv, AR8327_REG_LED_CTRL2, led_cfg->led_ctrl2);
1553 priv->write(priv, AR8327_REG_LED_CTRL3, led_cfg->led_ctrl3);
1554
1555 if (new_pos != pos)
1556 new_pos |= AR8327_POWER_ON_STRIP_POWER_ON_SEL;
1557 }
1558
1559 if (pdata->sgmii_cfg) {
1560 t = pdata->sgmii_cfg->sgmii_ctrl;
1561 if (priv->chip_rev == 1)
1562 t |= AR8327_SGMII_CTRL_EN_PLL |
1563 AR8327_SGMII_CTRL_EN_RX |
1564 AR8327_SGMII_CTRL_EN_TX;
1565 else
1566 t &= ~(AR8327_SGMII_CTRL_EN_PLL |
1567 AR8327_SGMII_CTRL_EN_RX |
1568 AR8327_SGMII_CTRL_EN_TX);
1569
1570 priv->write(priv, AR8327_REG_SGMII_CTRL, t);
1571
1572 if (pdata->sgmii_cfg->serdes_aen)
1573 new_pos &= ~AR8327_POWER_ON_STRIP_SERDES_AEN;
1574 else
1575 new_pos |= AR8327_POWER_ON_STRIP_SERDES_AEN;
1576 }
1577
1578 priv->write(priv, AR8327_REG_POWER_ON_STRIP, new_pos);
1579
1580 if (pdata->leds && pdata->num_leds) {
1581 int i;
1582
1583 data->leds = kzalloc(pdata->num_leds * sizeof(void *),
1584 GFP_KERNEL);
1585 if (!data->leds)
1586 return -ENOMEM;
1587
1588 for (i = 0; i < pdata->num_leds; i++)
1589 ar8327_led_create(priv, &pdata->leds[i]);
1590 }
1591
1592 return 0;
1593 }
1594
1595 #ifdef CONFIG_OF
1596 static int
1597 ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
1598 {
1599 struct ar8327_data *data = priv->chip_data;
1600 const __be32 *paddr;
1601 int len;
1602 int i;
1603
1604 paddr = of_get_property(np, "qca,ar8327-initvals", &len);
1605 if (!paddr || len < (2 * sizeof(*paddr)))
1606 return -EINVAL;
1607
1608 len /= sizeof(*paddr);
1609
1610 for (i = 0; i < len - 1; i += 2) {
1611 u32 reg;
1612 u32 val;
1613
1614 reg = be32_to_cpup(paddr + i);
1615 val = be32_to_cpup(paddr + i + 1);
1616
1617 switch (reg) {
1618 case AR8327_REG_PORT_STATUS(0):
1619 data->port0_status = val;
1620 break;
1621 case AR8327_REG_PORT_STATUS(6):
1622 data->port6_status = val;
1623 break;
1624 default:
1625 priv->write(priv, reg, val);
1626 break;
1627 }
1628 }
1629
1630 return 0;
1631 }
1632 #else
1633 static inline int
1634 ar8327_hw_config_of(struct ar8xxx_priv *priv, struct device_node *np)
1635 {
1636 return -EINVAL;
1637 }
1638 #endif
1639
1640 static int
1641 ar8327_hw_init(struct ar8xxx_priv *priv)
1642 {
1643 int ret;
1644
1645 priv->chip_data = kzalloc(sizeof(struct ar8327_data), GFP_KERNEL);
1646 if (!priv->chip_data)
1647 return -ENOMEM;
1648
1649 if (priv->phy->dev.of_node)
1650 ret = ar8327_hw_config_of(priv, priv->phy->dev.of_node);
1651 else
1652 ret = ar8327_hw_config_pdata(priv,
1653 priv->phy->dev.platform_data);
1654
1655 if (ret)
1656 return ret;
1657
1658 ar8327_leds_init(priv);
1659
1660 ar8xxx_phy_init(priv);
1661
1662 return 0;
1663 }
1664
1665 static void
1666 ar8327_cleanup(struct ar8xxx_priv *priv)
1667 {
1668 ar8327_leds_cleanup(priv);
1669 }
1670
1671 static void
1672 ar8327_init_globals(struct ar8xxx_priv *priv)
1673 {
1674 u32 t;
1675
1676 /* enable CPU port and disable mirror port */
1677 t = AR8327_FWD_CTRL0_CPU_PORT_EN |
1678 AR8327_FWD_CTRL0_MIRROR_PORT;
1679 priv->write(priv, AR8327_REG_FWD_CTRL0, t);
1680
1681 /* forward multicast and broadcast frames to CPU */
1682 t = (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_UC_FLOOD_S) |
1683 (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_MC_FLOOD_S) |
1684 (AR8327_PORTS_ALL << AR8327_FWD_CTRL1_BC_FLOOD_S);
1685 priv->write(priv, AR8327_REG_FWD_CTRL1, t);
1686
1687 /* enable jumbo frames */
1688 ar8xxx_rmw(priv, AR8327_REG_MAX_FRAME_SIZE,
1689 AR8327_MAX_FRAME_SIZE_MTU, 9018 + 8 + 2);
1690
1691 /* Enable MIB counters */
1692 ar8xxx_reg_set(priv, AR8327_REG_MODULE_EN,
1693 AR8327_MODULE_EN_MIB);
1694
1695 /* Disable EEE on all ports due to stability issues */
1696 t = priv->read(priv, AR8327_REG_EEE_CTRL);
1697 t |= AR8327_EEE_CTRL_DISABLE_PHY(0) |
1698 AR8327_EEE_CTRL_DISABLE_PHY(1) |
1699 AR8327_EEE_CTRL_DISABLE_PHY(2) |
1700 AR8327_EEE_CTRL_DISABLE_PHY(3) |
1701 AR8327_EEE_CTRL_DISABLE_PHY(4);
1702 priv->write(priv, AR8327_REG_EEE_CTRL, t);
1703 }
1704
1705 static void
1706 ar8327_init_port(struct ar8xxx_priv *priv, int port)
1707 {
1708 struct ar8327_data *data = priv->chip_data;
1709 u32 t;
1710
1711 if (port == AR8216_PORT_CPU)
1712 t = data->port0_status;
1713 else if (port == 6)
1714 t = data->port6_status;
1715 else
1716 t = AR8216_PORT_STATUS_LINK_AUTO;
1717
1718 priv->write(priv, AR8327_REG_PORT_STATUS(port), t);
1719 priv->write(priv, AR8327_REG_PORT_HEADER(port), 0);
1720
1721 t = 1 << AR8327_PORT_VLAN0_DEF_SVID_S;
1722 t |= 1 << AR8327_PORT_VLAN0_DEF_CVID_S;
1723 priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
1724
1725 t = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH << AR8327_PORT_VLAN1_OUT_MODE_S;
1726 priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
1727
1728 t = AR8327_PORT_LOOKUP_LEARN;
1729 t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1730 priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1731 }
1732
1733 static u32
1734 ar8327_read_port_status(struct ar8xxx_priv *priv, int port)
1735 {
1736 return priv->read(priv, AR8327_REG_PORT_STATUS(port));
1737 }
1738
1739 static int
1740 ar8327_atu_flush(struct ar8xxx_priv *priv)
1741 {
1742 int ret;
1743
1744 ret = ar8216_wait_bit(priv, AR8327_REG_ATU_FUNC,
1745 AR8327_ATU_FUNC_BUSY, 0);
1746 if (!ret)
1747 priv->write(priv, AR8327_REG_ATU_FUNC,
1748 AR8327_ATU_FUNC_OP_FLUSH);
1749
1750 return ret;
1751 }
1752
1753 static void
1754 ar8327_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
1755 {
1756 if (ar8216_wait_bit(priv, AR8327_REG_VTU_FUNC1,
1757 AR8327_VTU_FUNC1_BUSY, 0))
1758 return;
1759
1760 if ((op & AR8327_VTU_FUNC1_OP) == AR8327_VTU_FUNC1_OP_LOAD)
1761 priv->write(priv, AR8327_REG_VTU_FUNC0, val);
1762
1763 op |= AR8327_VTU_FUNC1_BUSY;
1764 priv->write(priv, AR8327_REG_VTU_FUNC1, op);
1765 }
1766
1767 static void
1768 ar8327_vtu_flush(struct ar8xxx_priv *priv)
1769 {
1770 ar8327_vtu_op(priv, AR8327_VTU_FUNC1_OP_FLUSH, 0);
1771 }
1772
1773 static void
1774 ar8327_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
1775 {
1776 u32 op;
1777 u32 val;
1778 int i;
1779
1780 op = AR8327_VTU_FUNC1_OP_LOAD | (vid << AR8327_VTU_FUNC1_VID_S);
1781 val = AR8327_VTU_FUNC0_VALID | AR8327_VTU_FUNC0_IVL;
1782 for (i = 0; i < AR8327_NUM_PORTS; i++) {
1783 u32 mode;
1784
1785 if ((port_mask & BIT(i)) == 0)
1786 mode = AR8327_VTU_FUNC0_EG_MODE_NOT;
1787 else if (priv->vlan == 0)
1788 mode = AR8327_VTU_FUNC0_EG_MODE_KEEP;
1789 else if ((priv->vlan_tagged & BIT(i)) || (priv->vlan_id[priv->pvid[i]] != vid))
1790 mode = AR8327_VTU_FUNC0_EG_MODE_TAG;
1791 else
1792 mode = AR8327_VTU_FUNC0_EG_MODE_UNTAG;
1793
1794 val |= mode << AR8327_VTU_FUNC0_EG_MODE_S(i);
1795 }
1796 ar8327_vtu_op(priv, op, val);
1797 }
1798
1799 static void
1800 ar8327_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
1801 {
1802 u32 t;
1803 u32 egress, ingress;
1804 u32 pvid = priv->vlan_id[priv->pvid[port]];
1805
1806 if (priv->vlan) {
1807 egress = AR8327_PORT_VLAN1_OUT_MODE_UNMOD;
1808 ingress = AR8216_IN_SECURE;
1809 } else {
1810 egress = AR8327_PORT_VLAN1_OUT_MODE_UNTOUCH;
1811 ingress = AR8216_IN_PORT_ONLY;
1812 }
1813
1814 t = pvid << AR8327_PORT_VLAN0_DEF_SVID_S;
1815 t |= pvid << AR8327_PORT_VLAN0_DEF_CVID_S;
1816 priv->write(priv, AR8327_REG_PORT_VLAN0(port), t);
1817
1818 t = AR8327_PORT_VLAN1_PORT_VLAN_PROP;
1819 t |= egress << AR8327_PORT_VLAN1_OUT_MODE_S;
1820 priv->write(priv, AR8327_REG_PORT_VLAN1(port), t);
1821
1822 t = members;
1823 t |= AR8327_PORT_LOOKUP_LEARN;
1824 t |= ingress << AR8327_PORT_LOOKUP_IN_MODE_S;
1825 t |= AR8216_PORT_STATE_FORWARD << AR8327_PORT_LOOKUP_STATE_S;
1826 priv->write(priv, AR8327_REG_PORT_LOOKUP(port), t);
1827 }
1828
1829 static const struct ar8xxx_chip ar8327_chip = {
1830 .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
1831 .config_at_probe = true,
1832 .hw_init = ar8327_hw_init,
1833 .cleanup = ar8327_cleanup,
1834 .init_globals = ar8327_init_globals,
1835 .init_port = ar8327_init_port,
1836 .setup_port = ar8327_setup_port,
1837 .read_port_status = ar8327_read_port_status,
1838 .atu_flush = ar8327_atu_flush,
1839 .vtu_flush = ar8327_vtu_flush,
1840 .vtu_load_vlan = ar8327_vtu_load_vlan,
1841 .phy_fixup = ar8327_phy_fixup,
1842 .set_mirror_regs = ar8327_set_mirror_regs,
1843
1844 .num_mibs = ARRAY_SIZE(ar8236_mibs),
1845 .mib_decs = ar8236_mibs,
1846 .mib_func = AR8327_REG_MIB_FUNC
1847 };
1848
1849 static int
1850 ar8xxx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1851 struct switch_val *val)
1852 {
1853 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1854 priv->vlan = !!val->value.i;
1855 return 0;
1856 }
1857
1858 static int
1859 ar8xxx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1860 struct switch_val *val)
1861 {
1862 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1863 val->value.i = priv->vlan;
1864 return 0;
1865 }
1866
1867
1868 static int
1869 ar8xxx_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
1870 {
1871 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1872
1873 /* make sure no invalid PVIDs get set */
1874
1875 if (vlan >= dev->vlans)
1876 return -EINVAL;
1877
1878 priv->pvid[port] = vlan;
1879 return 0;
1880 }
1881
1882 static int
1883 ar8xxx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
1884 {
1885 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1886 *vlan = priv->pvid[port];
1887 return 0;
1888 }
1889
1890 static int
1891 ar8xxx_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
1892 struct switch_val *val)
1893 {
1894 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1895 priv->vlan_id[val->port_vlan] = val->value.i;
1896 return 0;
1897 }
1898
1899 static int
1900 ar8xxx_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
1901 struct switch_val *val)
1902 {
1903 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1904 val->value.i = priv->vlan_id[val->port_vlan];
1905 return 0;
1906 }
1907
1908 static int
1909 ar8xxx_sw_get_port_link(struct switch_dev *dev, int port,
1910 struct switch_port_link *link)
1911 {
1912 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1913
1914 ar8216_read_port_link(priv, port, link);
1915 return 0;
1916 }
1917
1918 static int
1919 ar8xxx_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
1920 {
1921 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1922 u8 ports = priv->vlan_table[val->port_vlan];
1923 int i;
1924
1925 val->len = 0;
1926 for (i = 0; i < dev->ports; i++) {
1927 struct switch_port *p;
1928
1929 if (!(ports & (1 << i)))
1930 continue;
1931
1932 p = &val->value.ports[val->len++];
1933 p->id = i;
1934 if (priv->vlan_tagged & (1 << i))
1935 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1936 else
1937 p->flags = 0;
1938 }
1939 return 0;
1940 }
1941
1942 static int
1943 ar8327_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
1944 {
1945 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1946 u8 ports = priv->vlan_table[val->port_vlan];
1947 int i;
1948
1949 val->len = 0;
1950 for (i = 0; i < dev->ports; i++) {
1951 struct switch_port *p;
1952
1953 if (!(ports & (1 << i)))
1954 continue;
1955
1956 p = &val->value.ports[val->len++];
1957 p->id = i;
1958 if ((priv->vlan_tagged & (1 << i)) || (priv->pvid[i] != val->port_vlan))
1959 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1960 else
1961 p->flags = 0;
1962 }
1963 return 0;
1964 }
1965
1966 static int
1967 ar8xxx_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1968 {
1969 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1970 u8 *vt = &priv->vlan_table[val->port_vlan];
1971 int i, j;
1972
1973 *vt = 0;
1974 for (i = 0; i < val->len; i++) {
1975 struct switch_port *p = &val->value.ports[i];
1976
1977 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
1978 priv->vlan_tagged |= (1 << p->id);
1979 } else {
1980 priv->vlan_tagged &= ~(1 << p->id);
1981 priv->pvid[p->id] = val->port_vlan;
1982
1983 /* make sure that an untagged port does not
1984 * appear in other vlans */
1985 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
1986 if (j == val->port_vlan)
1987 continue;
1988 priv->vlan_table[j] &= ~(1 << p->id);
1989 }
1990 }
1991
1992 *vt |= 1 << p->id;
1993 }
1994 return 0;
1995 }
1996
1997 static int
1998 ar8327_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1999 {
2000 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2001 u8 *vt = &priv->vlan_table[val->port_vlan];
2002 int i;
2003
2004 *vt = 0;
2005 for (i = 0; i < val->len; i++) {
2006 struct switch_port *p = &val->value.ports[i];
2007
2008 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
2009 if (val->port_vlan == priv->pvid[p->id]) {
2010 priv->vlan_tagged |= (1 << p->id);
2011 }
2012 } else {
2013 priv->vlan_tagged &= ~(1 << p->id);
2014 priv->pvid[p->id] = val->port_vlan;
2015 }
2016
2017 *vt |= 1 << p->id;
2018 }
2019 return 0;
2020 }
2021
2022 static void
2023 ar8327_set_mirror_regs(struct ar8xxx_priv *priv)
2024 {
2025 int port;
2026
2027 /* reset all mirror registers */
2028 ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0,
2029 AR8327_FWD_CTRL0_MIRROR_PORT,
2030 (0xF << AR8327_FWD_CTRL0_MIRROR_PORT_S));
2031 for (port = 0; port < AR8327_NUM_PORTS; port++) {
2032 ar8xxx_rmw(priv, AR8327_REG_PORT_LOOKUP(port),
2033 AR8327_PORT_LOOKUP_ING_MIRROR_EN,
2034 0);
2035
2036 ar8xxx_rmw(priv, AR8327_REG_PORT_HOL_CTRL1(port),
2037 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN,
2038 0);
2039 }
2040
2041 /* now enable mirroring if necessary */
2042 if (priv->source_port >= AR8327_NUM_PORTS ||
2043 priv->monitor_port >= AR8327_NUM_PORTS ||
2044 priv->source_port == priv->monitor_port) {
2045 return;
2046 }
2047
2048 ar8xxx_rmw(priv, AR8327_REG_FWD_CTRL0,
2049 AR8327_FWD_CTRL0_MIRROR_PORT,
2050 (priv->monitor_port << AR8327_FWD_CTRL0_MIRROR_PORT_S));
2051
2052 if (priv->mirror_rx)
2053 ar8xxx_rmw(priv, AR8327_REG_PORT_LOOKUP(priv->source_port),
2054 AR8327_PORT_LOOKUP_ING_MIRROR_EN,
2055 AR8327_PORT_LOOKUP_ING_MIRROR_EN);
2056
2057 if (priv->mirror_tx)
2058 ar8xxx_rmw(priv, AR8327_REG_PORT_HOL_CTRL1(priv->source_port),
2059 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN,
2060 AR8327_PORT_HOL_CTRL1_EG_MIRROR_EN);
2061 }
2062
2063 static void
2064 ar8216_set_mirror_regs(struct ar8xxx_priv *priv)
2065 {
2066 int port;
2067
2068 /* reset all mirror registers */
2069 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
2070 AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
2071 (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
2072 for (port = 0; port < AR8216_NUM_PORTS; port++) {
2073 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
2074 AR8216_PORT_CTRL_MIRROR_RX,
2075 0);
2076
2077 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
2078 AR8216_PORT_CTRL_MIRROR_TX,
2079 0);
2080 }
2081
2082 /* now enable mirroring if necessary */
2083 if (priv->source_port >= AR8216_NUM_PORTS ||
2084 priv->monitor_port >= AR8216_NUM_PORTS ||
2085 priv->source_port == priv->monitor_port) {
2086 return;
2087 }
2088
2089 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
2090 AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
2091 (priv->monitor_port << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
2092
2093 if (priv->mirror_rx)
2094 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(priv->source_port),
2095 AR8216_PORT_CTRL_MIRROR_RX,
2096 AR8216_PORT_CTRL_MIRROR_RX);
2097
2098 if (priv->mirror_tx)
2099 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(priv->source_port),
2100 AR8216_PORT_CTRL_MIRROR_TX,
2101 AR8216_PORT_CTRL_MIRROR_TX);
2102 }
2103
2104 static int
2105 ar8xxx_sw_hw_apply(struct switch_dev *dev)
2106 {
2107 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2108 u8 portmask[AR8X16_MAX_PORTS];
2109 int i, j;
2110
2111 mutex_lock(&priv->reg_mutex);
2112 /* flush all vlan translation unit entries */
2113 priv->chip->vtu_flush(priv);
2114
2115 memset(portmask, 0, sizeof(portmask));
2116 if (!priv->init) {
2117 /* calculate the port destination masks and load vlans
2118 * into the vlan translation unit */
2119 for (j = 0; j < AR8X16_MAX_VLANS; j++) {
2120 u8 vp = priv->vlan_table[j];
2121
2122 if (!vp)
2123 continue;
2124
2125 for (i = 0; i < dev->ports; i++) {
2126 u8 mask = (1 << i);
2127 if (vp & mask)
2128 portmask[i] |= vp & ~mask;
2129 }
2130
2131 priv->chip->vtu_load_vlan(priv, priv->vlan_id[j],
2132 priv->vlan_table[j]);
2133 }
2134 } else {
2135 /* vlan disabled:
2136 * isolate all ports, but connect them to the cpu port */
2137 for (i = 0; i < dev->ports; i++) {
2138 if (i == AR8216_PORT_CPU)
2139 continue;
2140
2141 portmask[i] = 1 << AR8216_PORT_CPU;
2142 portmask[AR8216_PORT_CPU] |= (1 << i);
2143 }
2144 }
2145
2146 /* update the port destination mask registers and tag settings */
2147 for (i = 0; i < dev->ports; i++) {
2148 priv->chip->setup_port(priv, i, portmask[i]);
2149 }
2150
2151 priv->chip->set_mirror_regs(priv);
2152
2153 mutex_unlock(&priv->reg_mutex);
2154 return 0;
2155 }
2156
2157 static int
2158 ar8xxx_sw_reset_switch(struct switch_dev *dev)
2159 {
2160 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2161 int i;
2162
2163 mutex_lock(&priv->reg_mutex);
2164 memset(&priv->vlan, 0, sizeof(struct ar8xxx_priv) -
2165 offsetof(struct ar8xxx_priv, vlan));
2166
2167 for (i = 0; i < AR8X16_MAX_VLANS; i++)
2168 priv->vlan_id[i] = i;
2169
2170 /* Configure all ports */
2171 for (i = 0; i < dev->ports; i++)
2172 priv->chip->init_port(priv, i);
2173
2174 priv->mirror_rx = false;
2175 priv->mirror_tx = false;
2176 priv->source_port = 0;
2177 priv->monitor_port = 0;
2178
2179 priv->chip->init_globals(priv);
2180
2181 mutex_unlock(&priv->reg_mutex);
2182
2183 return ar8xxx_sw_hw_apply(dev);
2184 }
2185
2186 static int
2187 ar8xxx_sw_set_reset_mibs(struct switch_dev *dev,
2188 const struct switch_attr *attr,
2189 struct switch_val *val)
2190 {
2191 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2192 unsigned int len;
2193 int ret;
2194
2195 if (!ar8xxx_has_mib_counters(priv))
2196 return -EOPNOTSUPP;
2197
2198 mutex_lock(&priv->mib_lock);
2199
2200 len = priv->dev.ports * priv->chip->num_mibs *
2201 sizeof(*priv->mib_stats);
2202 memset(priv->mib_stats, '\0', len);
2203 ret = ar8xxx_mib_flush(priv);
2204 if (ret)
2205 goto unlock;
2206
2207 ret = 0;
2208
2209 unlock:
2210 mutex_unlock(&priv->mib_lock);
2211 return ret;
2212 }
2213
2214 static int
2215 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev *dev,
2216 const struct switch_attr *attr,
2217 struct switch_val *val)
2218 {
2219 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2220
2221 mutex_lock(&priv->reg_mutex);
2222 priv->mirror_rx = !!val->value.i;
2223 priv->chip->set_mirror_regs(priv);
2224 mutex_unlock(&priv->reg_mutex);
2225
2226 return 0;
2227 }
2228
2229 static int
2230 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev *dev,
2231 const struct switch_attr *attr,
2232 struct switch_val *val)
2233 {
2234 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2235 val->value.i = priv->mirror_rx;
2236 return 0;
2237 }
2238
2239 static int
2240 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev *dev,
2241 const struct switch_attr *attr,
2242 struct switch_val *val)
2243 {
2244 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2245
2246 mutex_lock(&priv->reg_mutex);
2247 priv->mirror_tx = !!val->value.i;
2248 priv->chip->set_mirror_regs(priv);
2249 mutex_unlock(&priv->reg_mutex);
2250
2251 return 0;
2252 }
2253
2254 static int
2255 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev *dev,
2256 const struct switch_attr *attr,
2257 struct switch_val *val)
2258 {
2259 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2260 val->value.i = priv->mirror_tx;
2261 return 0;
2262 }
2263
2264 static int
2265 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev *dev,
2266 const struct switch_attr *attr,
2267 struct switch_val *val)
2268 {
2269 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2270
2271 mutex_lock(&priv->reg_mutex);
2272 priv->monitor_port = val->value.i;
2273 priv->chip->set_mirror_regs(priv);
2274 mutex_unlock(&priv->reg_mutex);
2275
2276 return 0;
2277 }
2278
2279 static int
2280 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev *dev,
2281 const struct switch_attr *attr,
2282 struct switch_val *val)
2283 {
2284 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2285 val->value.i = priv->monitor_port;
2286 return 0;
2287 }
2288
2289 static int
2290 ar8xxx_sw_set_mirror_source_port(struct switch_dev *dev,
2291 const struct switch_attr *attr,
2292 struct switch_val *val)
2293 {
2294 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2295
2296 mutex_lock(&priv->reg_mutex);
2297 priv->source_port = val->value.i;
2298 priv->chip->set_mirror_regs(priv);
2299 mutex_unlock(&priv->reg_mutex);
2300
2301 return 0;
2302 }
2303
2304 static int
2305 ar8xxx_sw_get_mirror_source_port(struct switch_dev *dev,
2306 const struct switch_attr *attr,
2307 struct switch_val *val)
2308 {
2309 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2310 val->value.i = priv->source_port;
2311 return 0;
2312 }
2313
2314 static int
2315 ar8xxx_sw_set_port_reset_mib(struct switch_dev *dev,
2316 const struct switch_attr *attr,
2317 struct switch_val *val)
2318 {
2319 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2320 int port;
2321 int ret;
2322
2323 if (!ar8xxx_has_mib_counters(priv))
2324 return -EOPNOTSUPP;
2325
2326 port = val->port_vlan;
2327 if (port >= dev->ports)
2328 return -EINVAL;
2329
2330 mutex_lock(&priv->mib_lock);
2331 ret = ar8xxx_mib_capture(priv);
2332 if (ret)
2333 goto unlock;
2334
2335 ar8xxx_mib_fetch_port_stat(priv, port, true);
2336
2337 ret = 0;
2338
2339 unlock:
2340 mutex_unlock(&priv->mib_lock);
2341 return ret;
2342 }
2343
2344 static int
2345 ar8xxx_sw_get_port_mib(struct switch_dev *dev,
2346 const struct switch_attr *attr,
2347 struct switch_val *val)
2348 {
2349 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
2350 const struct ar8xxx_chip *chip = priv->chip;
2351 u64 *mib_stats;
2352 int port;
2353 int ret;
2354 char *buf = priv->buf;
2355 int i, len = 0;
2356
2357 if (!ar8xxx_has_mib_counters(priv))
2358 return -EOPNOTSUPP;
2359
2360 port = val->port_vlan;
2361 if (port >= dev->ports)
2362 return -EINVAL;
2363
2364 mutex_lock(&priv->mib_lock);
2365 ret = ar8xxx_mib_capture(priv);
2366 if (ret)
2367 goto unlock;
2368
2369 ar8xxx_mib_fetch_port_stat(priv, port, false);
2370
2371 len += snprintf(buf + len, sizeof(priv->buf) - len,
2372 "Port %d MIB counters\n",
2373 port);
2374
2375 mib_stats = &priv->mib_stats[port * chip->num_mibs];
2376 for (i = 0; i < chip->num_mibs; i++)
2377 len += snprintf(buf + len, sizeof(priv->buf) - len,
2378 "%-12s: %llu\n",
2379 chip->mib_decs[i].name,
2380 mib_stats[i]);
2381
2382 val->value.s = buf;
2383 val->len = len;
2384
2385 ret = 0;
2386
2387 unlock:
2388 mutex_unlock(&priv->mib_lock);
2389 return ret;
2390 }
2391
2392 static struct switch_attr ar8xxx_sw_attr_globals[] = {
2393 {
2394 .type = SWITCH_TYPE_INT,
2395 .name = "enable_vlan",
2396 .description = "Enable VLAN mode",
2397 .set = ar8xxx_sw_set_vlan,
2398 .get = ar8xxx_sw_get_vlan,
2399 .max = 1
2400 },
2401 {
2402 .type = SWITCH_TYPE_NOVAL,
2403 .name = "reset_mibs",
2404 .description = "Reset all MIB counters",
2405 .set = ar8xxx_sw_set_reset_mibs,
2406 },
2407 {
2408 .type = SWITCH_TYPE_INT,
2409 .name = "enable_mirror_rx",
2410 .description = "Enable mirroring of RX packets",
2411 .set = ar8xxx_sw_set_mirror_rx_enable,
2412 .get = ar8xxx_sw_get_mirror_rx_enable,
2413 .max = 1
2414 },
2415 {
2416 .type = SWITCH_TYPE_INT,
2417 .name = "enable_mirror_tx",
2418 .description = "Enable mirroring of TX packets",
2419 .set = ar8xxx_sw_set_mirror_tx_enable,
2420 .get = ar8xxx_sw_get_mirror_tx_enable,
2421 .max = 1
2422 },
2423 {
2424 .type = SWITCH_TYPE_INT,
2425 .name = "mirror_monitor_port",
2426 .description = "Mirror monitor port",
2427 .set = ar8xxx_sw_set_mirror_monitor_port,
2428 .get = ar8xxx_sw_get_mirror_monitor_port,
2429 .max = AR8216_NUM_PORTS - 1
2430 },
2431 {
2432 .type = SWITCH_TYPE_INT,
2433 .name = "mirror_source_port",
2434 .description = "Mirror source port",
2435 .set = ar8xxx_sw_set_mirror_source_port,
2436 .get = ar8xxx_sw_get_mirror_source_port,
2437 .max = AR8216_NUM_PORTS - 1
2438 },
2439 };
2440
2441 static struct switch_attr ar8327_sw_attr_globals[] = {
2442 {
2443 .type = SWITCH_TYPE_INT,
2444 .name = "enable_vlan",
2445 .description = "Enable VLAN mode",
2446 .set = ar8xxx_sw_set_vlan,
2447 .get = ar8xxx_sw_get_vlan,
2448 .max = 1
2449 },
2450 {
2451 .type = SWITCH_TYPE_NOVAL,
2452 .name = "reset_mibs",
2453 .description = "Reset all MIB counters",
2454 .set = ar8xxx_sw_set_reset_mibs,
2455 },
2456 {
2457 .type = SWITCH_TYPE_INT,
2458 .name = "enable_mirror_rx",
2459 .description = "Enable mirroring of RX packets",
2460 .set = ar8xxx_sw_set_mirror_rx_enable,
2461 .get = ar8xxx_sw_get_mirror_rx_enable,
2462 .max = 1
2463 },
2464 {
2465 .type = SWITCH_TYPE_INT,
2466 .name = "enable_mirror_tx",
2467 .description = "Enable mirroring of TX packets",
2468 .set = ar8xxx_sw_set_mirror_tx_enable,
2469 .get = ar8xxx_sw_get_mirror_tx_enable,
2470 .max = 1
2471 },
2472 {
2473 .type = SWITCH_TYPE_INT,
2474 .name = "mirror_monitor_port",
2475 .description = "Mirror monitor port",
2476 .set = ar8xxx_sw_set_mirror_monitor_port,
2477 .get = ar8xxx_sw_get_mirror_monitor_port,
2478 .max = AR8327_NUM_PORTS - 1
2479 },
2480 {
2481 .type = SWITCH_TYPE_INT,
2482 .name = "mirror_source_port",
2483 .description = "Mirror source port",
2484 .set = ar8xxx_sw_set_mirror_source_port,
2485 .get = ar8xxx_sw_get_mirror_source_port,
2486 .max = AR8327_NUM_PORTS - 1
2487 },
2488 };
2489
2490 static struct switch_attr ar8xxx_sw_attr_port[] = {
2491 {
2492 .type = SWITCH_TYPE_NOVAL,
2493 .name = "reset_mib",
2494 .description = "Reset single port MIB counters",
2495 .set = ar8xxx_sw_set_port_reset_mib,
2496 },
2497 {
2498 .type = SWITCH_TYPE_STRING,
2499 .name = "mib",
2500 .description = "Get port's MIB counters",
2501 .set = NULL,
2502 .get = ar8xxx_sw_get_port_mib,
2503 },
2504 };
2505
2506 static struct switch_attr ar8xxx_sw_attr_vlan[] = {
2507 {
2508 .type = SWITCH_TYPE_INT,
2509 .name = "vid",
2510 .description = "VLAN ID (0-4094)",
2511 .set = ar8xxx_sw_set_vid,
2512 .get = ar8xxx_sw_get_vid,
2513 .max = 4094,
2514 },
2515 };
2516
2517 static const struct switch_dev_ops ar8xxx_sw_ops = {
2518 .attr_global = {
2519 .attr = ar8xxx_sw_attr_globals,
2520 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_globals),
2521 },
2522 .attr_port = {
2523 .attr = ar8xxx_sw_attr_port,
2524 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
2525 },
2526 .attr_vlan = {
2527 .attr = ar8xxx_sw_attr_vlan,
2528 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
2529 },
2530 .get_port_pvid = ar8xxx_sw_get_pvid,
2531 .set_port_pvid = ar8xxx_sw_set_pvid,
2532 .get_vlan_ports = ar8xxx_sw_get_ports,
2533 .set_vlan_ports = ar8xxx_sw_set_ports,
2534 .apply_config = ar8xxx_sw_hw_apply,
2535 .reset_switch = ar8xxx_sw_reset_switch,
2536 .get_port_link = ar8xxx_sw_get_port_link,
2537 };
2538
2539 static const struct switch_dev_ops ar8327_sw_ops = {
2540 .attr_global = {
2541 .attr = ar8327_sw_attr_globals,
2542 .n_attr = ARRAY_SIZE(ar8327_sw_attr_globals),
2543 },
2544 .attr_port = {
2545 .attr = ar8xxx_sw_attr_port,
2546 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
2547 },
2548 .attr_vlan = {
2549 .attr = ar8xxx_sw_attr_vlan,
2550 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
2551 },
2552 .get_port_pvid = ar8xxx_sw_get_pvid,
2553 .set_port_pvid = ar8xxx_sw_set_pvid,
2554 .get_vlan_ports = ar8327_sw_get_ports,
2555 .set_vlan_ports = ar8327_sw_set_ports,
2556 .apply_config = ar8xxx_sw_hw_apply,
2557 .reset_switch = ar8xxx_sw_reset_switch,
2558 .get_port_link = ar8xxx_sw_get_port_link,
2559 };
2560
2561 static int
2562 ar8xxx_id_chip(struct ar8xxx_priv *priv)
2563 {
2564 u32 val;
2565 u16 id;
2566 int i;
2567
2568 val = priv->read(priv, AR8216_REG_CTRL);
2569 if (val == ~0)
2570 return -ENODEV;
2571
2572 id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
2573 for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
2574 u16 t;
2575
2576 val = priv->read(priv, AR8216_REG_CTRL);
2577 if (val == ~0)
2578 return -ENODEV;
2579
2580 t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
2581 if (t != id)
2582 return -ENODEV;
2583 }
2584
2585 priv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S;
2586 priv->chip_rev = (id & AR8216_CTRL_REVISION);
2587
2588 switch (priv->chip_ver) {
2589 case AR8XXX_VER_AR8216:
2590 priv->chip = &ar8216_chip;
2591 break;
2592 case AR8XXX_VER_AR8236:
2593 priv->chip = &ar8236_chip;
2594 break;
2595 case AR8XXX_VER_AR8316:
2596 priv->chip = &ar8316_chip;
2597 break;
2598 case AR8XXX_VER_AR8327:
2599 priv->mii_lo_first = true;
2600 priv->chip = &ar8327_chip;
2601 break;
2602 case AR8XXX_VER_AR8337:
2603 priv->mii_lo_first = true;
2604 priv->chip = &ar8327_chip;
2605 break;
2606 default:
2607 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
2608 priv->chip_ver, priv->chip_rev);
2609
2610 return -ENODEV;
2611 }
2612
2613 return 0;
2614 }
2615
2616 static void
2617 ar8xxx_mib_work_func(struct work_struct *work)
2618 {
2619 struct ar8xxx_priv *priv;
2620 int err;
2621
2622 priv = container_of(work, struct ar8xxx_priv, mib_work.work);
2623
2624 mutex_lock(&priv->mib_lock);
2625
2626 err = ar8xxx_mib_capture(priv);
2627 if (err)
2628 goto next_port;
2629
2630 ar8xxx_mib_fetch_port_stat(priv, priv->mib_next_port, false);
2631
2632 next_port:
2633 priv->mib_next_port++;
2634 if (priv->mib_next_port >= priv->dev.ports)
2635 priv->mib_next_port = 0;
2636
2637 mutex_unlock(&priv->mib_lock);
2638 schedule_delayed_work(&priv->mib_work,
2639 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
2640 }
2641
2642 static int
2643 ar8xxx_mib_init(struct ar8xxx_priv *priv)
2644 {
2645 unsigned int len;
2646
2647 if (!ar8xxx_has_mib_counters(priv))
2648 return 0;
2649
2650 BUG_ON(!priv->chip->mib_decs || !priv->chip->num_mibs);
2651
2652 len = priv->dev.ports * priv->chip->num_mibs *
2653 sizeof(*priv->mib_stats);
2654 priv->mib_stats = kzalloc(len, GFP_KERNEL);
2655
2656 if (!priv->mib_stats)
2657 return -ENOMEM;
2658
2659 return 0;
2660 }
2661
2662 static void
2663 ar8xxx_mib_start(struct ar8xxx_priv *priv)
2664 {
2665 if (!ar8xxx_has_mib_counters(priv))
2666 return;
2667
2668 schedule_delayed_work(&priv->mib_work,
2669 msecs_to_jiffies(AR8XXX_MIB_WORK_DELAY));
2670 }
2671
2672 static void
2673 ar8xxx_mib_stop(struct ar8xxx_priv *priv)
2674 {
2675 if (!ar8xxx_has_mib_counters(priv))
2676 return;
2677
2678 cancel_delayed_work(&priv->mib_work);
2679 }
2680
2681 static struct ar8xxx_priv *
2682 ar8xxx_create(void)
2683 {
2684 struct ar8xxx_priv *priv;
2685
2686 priv = kzalloc(sizeof(struct ar8xxx_priv), GFP_KERNEL);
2687 if (priv == NULL)
2688 return NULL;
2689
2690 mutex_init(&priv->reg_mutex);
2691 mutex_init(&priv->mib_lock);
2692 INIT_DELAYED_WORK(&priv->mib_work, ar8xxx_mib_work_func);
2693
2694 return priv;
2695 }
2696
2697 static void
2698 ar8xxx_free(struct ar8xxx_priv *priv)
2699 {
2700 if (priv->chip && priv->chip->cleanup)
2701 priv->chip->cleanup(priv);
2702
2703 kfree(priv->chip_data);
2704 kfree(priv->mib_stats);
2705 kfree(priv);
2706 }
2707
2708 static struct ar8xxx_priv *
2709 ar8xxx_create_mii(struct mii_bus *bus)
2710 {
2711 struct ar8xxx_priv *priv;
2712
2713 priv = ar8xxx_create();
2714 if (priv) {
2715 priv->mii_bus = bus;
2716 priv->read = ar8xxx_mii_read;
2717 priv->write = ar8xxx_mii_write;
2718 priv->rmw = ar8xxx_mii_rmw;
2719 }
2720
2721 return priv;
2722 }
2723
2724 static int
2725 ar8xxx_probe_switch(struct ar8xxx_priv *priv)
2726 {
2727 struct switch_dev *swdev;
2728 int ret;
2729
2730 ret = ar8xxx_id_chip(priv);
2731 if (ret)
2732 return ret;
2733
2734 swdev = &priv->dev;
2735 swdev->cpu_port = AR8216_PORT_CPU;
2736 swdev->ops = &ar8xxx_sw_ops;
2737
2738 if (chip_is_ar8316(priv)) {
2739 swdev->name = "Atheros AR8316";
2740 swdev->vlans = AR8X16_MAX_VLANS;
2741 swdev->ports = AR8216_NUM_PORTS;
2742 } else if (chip_is_ar8236(priv)) {
2743 swdev->name = "Atheros AR8236";
2744 swdev->vlans = AR8216_NUM_VLANS;
2745 swdev->ports = AR8216_NUM_PORTS;
2746 } else if (chip_is_ar8327(priv)) {
2747 swdev->name = "Atheros AR8327";
2748 swdev->vlans = AR8X16_MAX_VLANS;
2749 swdev->ports = AR8327_NUM_PORTS;
2750 swdev->ops = &ar8327_sw_ops;
2751 } else if (chip_is_ar8337(priv)) {
2752 swdev->name = "Atheros AR8337";
2753 swdev->vlans = AR8X16_MAX_VLANS;
2754 swdev->ports = AR8327_NUM_PORTS;
2755 swdev->ops = &ar8327_sw_ops;
2756 } else {
2757 swdev->name = "Atheros AR8216";
2758 swdev->vlans = AR8216_NUM_VLANS;
2759 swdev->ports = AR8216_NUM_PORTS;
2760 }
2761
2762 ret = ar8xxx_mib_init(priv);
2763 if (ret)
2764 return ret;
2765
2766 return 0;
2767 }
2768
2769 static int
2770 ar8xxx_start(struct ar8xxx_priv *priv)
2771 {
2772 int ret;
2773
2774 priv->init = true;
2775
2776 ret = priv->chip->hw_init(priv);
2777 if (ret)
2778 return ret;
2779
2780 ret = ar8xxx_sw_reset_switch(&priv->dev);
2781 if (ret)
2782 return ret;
2783
2784 priv->init = false;
2785
2786 ar8xxx_mib_start(priv);
2787
2788 return 0;
2789 }
2790
2791 static int
2792 ar8xxx_phy_config_init(struct phy_device *phydev)
2793 {
2794 struct ar8xxx_priv *priv = phydev->priv;
2795 struct net_device *dev = phydev->attached_dev;
2796 int ret;
2797
2798 if (WARN_ON(!priv))
2799 return -ENODEV;
2800
2801 if (priv->chip->config_at_probe)
2802 return ar8xxx_phy_check_aneg(phydev);
2803
2804 priv->phy = phydev;
2805
2806 if (phydev->addr != 0) {
2807 if (chip_is_ar8316(priv)) {
2808 /* switch device has been initialized, reinit */
2809 priv->dev.ports = (AR8216_NUM_PORTS - 1);
2810 priv->initialized = false;
2811 priv->port4_phy = true;
2812 ar8316_hw_init(priv);
2813 return 0;
2814 }
2815
2816 return 0;
2817 }
2818
2819 ret = ar8xxx_start(priv);
2820 if (ret)
2821 return ret;
2822
2823 /* VID fixup only needed on ar8216 */
2824 if (chip_is_ar8216(priv)) {
2825 dev->phy_ptr = priv;
2826 dev->priv_flags |= IFF_NO_IP_ALIGN;
2827 dev->eth_mangle_rx = ar8216_mangle_rx;
2828 dev->eth_mangle_tx = ar8216_mangle_tx;
2829 }
2830
2831 return 0;
2832 }
2833
2834 static int
2835 ar8xxx_phy_read_status(struct phy_device *phydev)
2836 {
2837 struct ar8xxx_priv *priv = phydev->priv;
2838 struct switch_port_link link;
2839 int ret;
2840
2841 if (phydev->addr != 0)
2842 return genphy_read_status(phydev);
2843
2844 ar8216_read_port_link(priv, phydev->addr, &link);
2845 phydev->link = !!link.link;
2846 if (!phydev->link)
2847 return 0;
2848
2849 switch (link.speed) {
2850 case SWITCH_PORT_SPEED_10:
2851 phydev->speed = SPEED_10;
2852 break;
2853 case SWITCH_PORT_SPEED_100:
2854 phydev->speed = SPEED_100;
2855 break;
2856 case SWITCH_PORT_SPEED_1000:
2857 phydev->speed = SPEED_1000;
2858 break;
2859 default:
2860 phydev->speed = 0;
2861 }
2862 phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
2863
2864 /* flush the address translation unit */
2865 mutex_lock(&priv->reg_mutex);
2866 ret = priv->chip->atu_flush(priv);
2867 mutex_unlock(&priv->reg_mutex);
2868
2869 phydev->state = PHY_RUNNING;
2870 netif_carrier_on(phydev->attached_dev);
2871 phydev->adjust_link(phydev->attached_dev);
2872
2873 return ret;
2874 }
2875
2876 static int
2877 ar8xxx_phy_config_aneg(struct phy_device *phydev)
2878 {
2879 if (phydev->addr == 0)
2880 return 0;
2881
2882 return genphy_config_aneg(phydev);
2883 }
2884
2885 static const u32 ar8xxx_phy_ids[] = {
2886 0x004dd033,
2887 0x004dd034, /* AR8327 */
2888 0x004dd036, /* AR8337 */
2889 0x004dd041,
2890 0x004dd042,
2891 0x004dd043, /* AR8236 */
2892 };
2893
2894 static bool
2895 ar8xxx_phy_match(u32 phy_id)
2896 {
2897 int i;
2898
2899 for (i = 0; i < ARRAY_SIZE(ar8xxx_phy_ids); i++)
2900 if (phy_id == ar8xxx_phy_ids[i])
2901 return true;
2902
2903 return false;
2904 }
2905
2906 static bool
2907 ar8xxx_is_possible(struct mii_bus *bus)
2908 {
2909 unsigned i;
2910
2911 for (i = 0; i < 4; i++) {
2912 u32 phy_id;
2913
2914 phy_id = mdiobus_read(bus, i, MII_PHYSID1) << 16;
2915 phy_id |= mdiobus_read(bus, i, MII_PHYSID2);
2916 if (!ar8xxx_phy_match(phy_id)) {
2917 pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
2918 dev_name(&bus->dev), i, phy_id);
2919 return false;
2920 }
2921 }
2922
2923 return true;
2924 }
2925
2926 static int
2927 ar8xxx_phy_probe(struct phy_device *phydev)
2928 {
2929 struct ar8xxx_priv *priv;
2930 struct switch_dev *swdev;
2931 int ret;
2932
2933 /* skip PHYs at unused adresses */
2934 if (phydev->addr != 0 && phydev->addr != 4)
2935 return -ENODEV;
2936
2937 if (!ar8xxx_is_possible(phydev->bus))
2938 return -ENODEV;
2939
2940 mutex_lock(&ar8xxx_dev_list_lock);
2941 list_for_each_entry(priv, &ar8xxx_dev_list, list)
2942 if (priv->mii_bus == phydev->bus)
2943 goto found;
2944
2945 priv = ar8xxx_create_mii(phydev->bus);
2946 if (priv == NULL) {
2947 ret = -ENOMEM;
2948 goto unlock;
2949 }
2950
2951 ret = ar8xxx_probe_switch(priv);
2952 if (ret)
2953 goto free_priv;
2954
2955 swdev = &priv->dev;
2956 swdev->alias = dev_name(&priv->mii_bus->dev);
2957 ret = register_switch(swdev, NULL);
2958 if (ret)
2959 goto free_priv;
2960
2961 pr_info("%s: %s rev. %u switch registered on %s\n",
2962 swdev->devname, swdev->name, priv->chip_rev,
2963 dev_name(&priv->mii_bus->dev));
2964
2965 found:
2966 priv->use_count++;
2967
2968 if (phydev->addr == 0) {
2969 if (ar8xxx_has_gige(priv)) {
2970 phydev->supported = SUPPORTED_1000baseT_Full;
2971 phydev->advertising = ADVERTISED_1000baseT_Full;
2972 } else {
2973 phydev->supported = SUPPORTED_100baseT_Full;
2974 phydev->advertising = ADVERTISED_100baseT_Full;
2975 }
2976
2977 if (priv->chip->config_at_probe) {
2978 priv->phy = phydev;
2979
2980 ret = ar8xxx_start(priv);
2981 if (ret)
2982 goto err_unregister_switch;
2983 }
2984 } else {
2985 if (ar8xxx_has_gige(priv)) {
2986 phydev->supported |= SUPPORTED_1000baseT_Full;
2987 phydev->advertising |= ADVERTISED_1000baseT_Full;
2988 }
2989 }
2990
2991 phydev->priv = priv;
2992
2993 list_add(&priv->list, &ar8xxx_dev_list);
2994
2995 mutex_unlock(&ar8xxx_dev_list_lock);
2996
2997 return 0;
2998
2999 err_unregister_switch:
3000 if (--priv->use_count)
3001 goto unlock;
3002
3003 unregister_switch(&priv->dev);
3004
3005 free_priv:
3006 ar8xxx_free(priv);
3007 unlock:
3008 mutex_unlock(&ar8xxx_dev_list_lock);
3009 return ret;
3010 }
3011
3012 static void
3013 ar8xxx_phy_detach(struct phy_device *phydev)
3014 {
3015 struct net_device *dev = phydev->attached_dev;
3016
3017 if (!dev)
3018 return;
3019
3020 dev->phy_ptr = NULL;
3021 dev->priv_flags &= ~IFF_NO_IP_ALIGN;
3022 dev->eth_mangle_rx = NULL;
3023 dev->eth_mangle_tx = NULL;
3024 }
3025
3026 static void
3027 ar8xxx_phy_remove(struct phy_device *phydev)
3028 {
3029 struct ar8xxx_priv *priv = phydev->priv;
3030
3031 if (WARN_ON(!priv))
3032 return;
3033
3034 phydev->priv = NULL;
3035 if (--priv->use_count > 0)
3036 return;
3037
3038 mutex_lock(&ar8xxx_dev_list_lock);
3039 list_del(&priv->list);
3040 mutex_unlock(&ar8xxx_dev_list_lock);
3041
3042 unregister_switch(&priv->dev);
3043 ar8xxx_mib_stop(priv);
3044 ar8xxx_free(priv);
3045 }
3046
3047 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)
3048 static int
3049 ar8xxx_phy_soft_reset(struct phy_device *phydev)
3050 {
3051 /* we don't need an extra reset */
3052 return 0;
3053 }
3054 #endif
3055
3056 static struct phy_driver ar8xxx_phy_driver = {
3057 .phy_id = 0x004d0000,
3058 .name = "Atheros AR8216/AR8236/AR8316",
3059 .phy_id_mask = 0xffff0000,
3060 .features = PHY_BASIC_FEATURES,
3061 .probe = ar8xxx_phy_probe,
3062 .remove = ar8xxx_phy_remove,
3063 .detach = ar8xxx_phy_detach,
3064 .config_init = ar8xxx_phy_config_init,
3065 .config_aneg = ar8xxx_phy_config_aneg,
3066 .read_status = ar8xxx_phy_read_status,
3067 #if LINUX_VERSION_CODE >= KERNEL_VERSION(3,14,0)
3068 .soft_reset = ar8xxx_phy_soft_reset,
3069 #endif
3070 .driver = { .owner = THIS_MODULE },
3071 };
3072
3073 int __init
3074 ar8xxx_init(void)
3075 {
3076 return phy_driver_register(&ar8xxx_phy_driver);
3077 }
3078
3079 void __exit
3080 ar8xxx_exit(void)
3081 {
3082 phy_driver_unregister(&ar8xxx_phy_driver);
3083 }
3084
3085 module_init(ar8xxx_init);
3086 module_exit(ar8xxx_exit);
3087 MODULE_LICENSE("GPL");
3088
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