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[openwrt/staging/chunkeey.git] / target / linux / generic / files / drivers / net / phy / ar8216.c
1 /*
2 * ar8216.c: AR8216 switch driver
3 *
4 * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
5 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License
9 * as published by the Free Software Foundation; either version 2
10 * of the License, or (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18 #include <linux/if.h>
19 #include <linux/module.h>
20 #include <linux/init.h>
21 #include <linux/list.h>
22 #include <linux/if_ether.h>
23 #include <linux/skbuff.h>
24 #include <linux/netdevice.h>
25 #include <linux/netlink.h>
26 #include <linux/of_device.h>
27 #include <linux/of_mdio.h>
28 #include <linux/of_net.h>
29 #include <linux/bitops.h>
30 #include <net/genetlink.h>
31 #include <linux/switch.h>
32 #include <linux/delay.h>
33 #include <linux/phy.h>
34 #include <linux/etherdevice.h>
35 #include <linux/lockdep.h>
36 #include <linux/ar8216_platform.h>
37 #include <linux/workqueue.h>
38 #include <linux/version.h>
39
40 #include "ar8216.h"
41
42 extern const struct ar8xxx_chip ar8327_chip;
43 extern const struct ar8xxx_chip ar8337_chip;
44
45 #define MIB_DESC_BASIC(_s , _o, _n) \
46 { \
47 .size = (_s), \
48 .offset = (_o), \
49 .name = (_n), \
50 .type = AR8XXX_MIB_BASIC, \
51 }
52
53 #define MIB_DESC_EXT(_s , _o, _n) \
54 { \
55 .size = (_s), \
56 .offset = (_o), \
57 .name = (_n), \
58 .type = AR8XXX_MIB_EXTENDED, \
59 }
60
61 static const struct ar8xxx_mib_desc ar8216_mibs[] = {
62 MIB_DESC_EXT(1, AR8216_STATS_RXBROAD, "RxBroad"),
63 MIB_DESC_EXT(1, AR8216_STATS_RXPAUSE, "RxPause"),
64 MIB_DESC_EXT(1, AR8216_STATS_RXMULTI, "RxMulti"),
65 MIB_DESC_EXT(1, AR8216_STATS_RXFCSERR, "RxFcsErr"),
66 MIB_DESC_EXT(1, AR8216_STATS_RXALIGNERR, "RxAlignErr"),
67 MIB_DESC_EXT(1, AR8216_STATS_RXRUNT, "RxRunt"),
68 MIB_DESC_EXT(1, AR8216_STATS_RXFRAGMENT, "RxFragment"),
69 MIB_DESC_EXT(1, AR8216_STATS_RX64BYTE, "Rx64Byte"),
70 MIB_DESC_EXT(1, AR8216_STATS_RX128BYTE, "Rx128Byte"),
71 MIB_DESC_EXT(1, AR8216_STATS_RX256BYTE, "Rx256Byte"),
72 MIB_DESC_EXT(1, AR8216_STATS_RX512BYTE, "Rx512Byte"),
73 MIB_DESC_EXT(1, AR8216_STATS_RX1024BYTE, "Rx1024Byte"),
74 MIB_DESC_EXT(1, AR8216_STATS_RXMAXBYTE, "RxMaxByte"),
75 MIB_DESC_EXT(1, AR8216_STATS_RXTOOLONG, "RxTooLong"),
76 MIB_DESC_BASIC(2, AR8216_STATS_RXGOODBYTE, "RxGoodByte"),
77 MIB_DESC_EXT(2, AR8216_STATS_RXBADBYTE, "RxBadByte"),
78 MIB_DESC_EXT(1, AR8216_STATS_RXOVERFLOW, "RxOverFlow"),
79 MIB_DESC_EXT(1, AR8216_STATS_FILTERED, "Filtered"),
80 MIB_DESC_EXT(1, AR8216_STATS_TXBROAD, "TxBroad"),
81 MIB_DESC_EXT(1, AR8216_STATS_TXPAUSE, "TxPause"),
82 MIB_DESC_EXT(1, AR8216_STATS_TXMULTI, "TxMulti"),
83 MIB_DESC_EXT(1, AR8216_STATS_TXUNDERRUN, "TxUnderRun"),
84 MIB_DESC_EXT(1, AR8216_STATS_TX64BYTE, "Tx64Byte"),
85 MIB_DESC_EXT(1, AR8216_STATS_TX128BYTE, "Tx128Byte"),
86 MIB_DESC_EXT(1, AR8216_STATS_TX256BYTE, "Tx256Byte"),
87 MIB_DESC_EXT(1, AR8216_STATS_TX512BYTE, "Tx512Byte"),
88 MIB_DESC_EXT(1, AR8216_STATS_TX1024BYTE, "Tx1024Byte"),
89 MIB_DESC_EXT(1, AR8216_STATS_TXMAXBYTE, "TxMaxByte"),
90 MIB_DESC_EXT(1, AR8216_STATS_TXOVERSIZE, "TxOverSize"),
91 MIB_DESC_BASIC(2, AR8216_STATS_TXBYTE, "TxByte"),
92 MIB_DESC_EXT(1, AR8216_STATS_TXCOLLISION, "TxCollision"),
93 MIB_DESC_EXT(1, AR8216_STATS_TXABORTCOL, "TxAbortCol"),
94 MIB_DESC_EXT(1, AR8216_STATS_TXMULTICOL, "TxMultiCol"),
95 MIB_DESC_EXT(1, AR8216_STATS_TXSINGLECOL, "TxSingleCol"),
96 MIB_DESC_EXT(1, AR8216_STATS_TXEXCDEFER, "TxExcDefer"),
97 MIB_DESC_EXT(1, AR8216_STATS_TXDEFER, "TxDefer"),
98 MIB_DESC_EXT(1, AR8216_STATS_TXLATECOL, "TxLateCol"),
99 };
100
101 const struct ar8xxx_mib_desc ar8236_mibs[39] = {
102 MIB_DESC_EXT(1, AR8236_STATS_RXBROAD, "RxBroad"),
103 MIB_DESC_EXT(1, AR8236_STATS_RXPAUSE, "RxPause"),
104 MIB_DESC_EXT(1, AR8236_STATS_RXMULTI, "RxMulti"),
105 MIB_DESC_EXT(1, AR8236_STATS_RXFCSERR, "RxFcsErr"),
106 MIB_DESC_EXT(1, AR8236_STATS_RXALIGNERR, "RxAlignErr"),
107 MIB_DESC_EXT(1, AR8236_STATS_RXRUNT, "RxRunt"),
108 MIB_DESC_EXT(1, AR8236_STATS_RXFRAGMENT, "RxFragment"),
109 MIB_DESC_EXT(1, AR8236_STATS_RX64BYTE, "Rx64Byte"),
110 MIB_DESC_EXT(1, AR8236_STATS_RX128BYTE, "Rx128Byte"),
111 MIB_DESC_EXT(1, AR8236_STATS_RX256BYTE, "Rx256Byte"),
112 MIB_DESC_EXT(1, AR8236_STATS_RX512BYTE, "Rx512Byte"),
113 MIB_DESC_EXT(1, AR8236_STATS_RX1024BYTE, "Rx1024Byte"),
114 MIB_DESC_EXT(1, AR8236_STATS_RX1518BYTE, "Rx1518Byte"),
115 MIB_DESC_EXT(1, AR8236_STATS_RXMAXBYTE, "RxMaxByte"),
116 MIB_DESC_EXT(1, AR8236_STATS_RXTOOLONG, "RxTooLong"),
117 MIB_DESC_BASIC(2, AR8236_STATS_RXGOODBYTE, "RxGoodByte"),
118 MIB_DESC_EXT(2, AR8236_STATS_RXBADBYTE, "RxBadByte"),
119 MIB_DESC_EXT(1, AR8236_STATS_RXOVERFLOW, "RxOverFlow"),
120 MIB_DESC_EXT(1, AR8236_STATS_FILTERED, "Filtered"),
121 MIB_DESC_EXT(1, AR8236_STATS_TXBROAD, "TxBroad"),
122 MIB_DESC_EXT(1, AR8236_STATS_TXPAUSE, "TxPause"),
123 MIB_DESC_EXT(1, AR8236_STATS_TXMULTI, "TxMulti"),
124 MIB_DESC_EXT(1, AR8236_STATS_TXUNDERRUN, "TxUnderRun"),
125 MIB_DESC_EXT(1, AR8236_STATS_TX64BYTE, "Tx64Byte"),
126 MIB_DESC_EXT(1, AR8236_STATS_TX128BYTE, "Tx128Byte"),
127 MIB_DESC_EXT(1, AR8236_STATS_TX256BYTE, "Tx256Byte"),
128 MIB_DESC_EXT(1, AR8236_STATS_TX512BYTE, "Tx512Byte"),
129 MIB_DESC_EXT(1, AR8236_STATS_TX1024BYTE, "Tx1024Byte"),
130 MIB_DESC_EXT(1, AR8236_STATS_TX1518BYTE, "Tx1518Byte"),
131 MIB_DESC_EXT(1, AR8236_STATS_TXMAXBYTE, "TxMaxByte"),
132 MIB_DESC_EXT(1, AR8236_STATS_TXOVERSIZE, "TxOverSize"),
133 MIB_DESC_BASIC(2, AR8236_STATS_TXBYTE, "TxByte"),
134 MIB_DESC_EXT(1, AR8236_STATS_TXCOLLISION, "TxCollision"),
135 MIB_DESC_EXT(1, AR8236_STATS_TXABORTCOL, "TxAbortCol"),
136 MIB_DESC_EXT(1, AR8236_STATS_TXMULTICOL, "TxMultiCol"),
137 MIB_DESC_EXT(1, AR8236_STATS_TXSINGLECOL, "TxSingleCol"),
138 MIB_DESC_EXT(1, AR8236_STATS_TXEXCDEFER, "TxExcDefer"),
139 MIB_DESC_EXT(1, AR8236_STATS_TXDEFER, "TxDefer"),
140 MIB_DESC_EXT(1, AR8236_STATS_TXLATECOL, "TxLateCol"),
141 };
142
143 static DEFINE_MUTEX(ar8xxx_dev_list_lock);
144 static LIST_HEAD(ar8xxx_dev_list);
145
146 static void
147 ar8xxx_mib_start(struct ar8xxx_priv *priv);
148 static void
149 ar8xxx_mib_stop(struct ar8xxx_priv *priv);
150
151 /* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */
152 static int
153 ar8xxx_phy_poll_reset(struct mii_bus *bus)
154 {
155 unsigned int sleep_msecs = 20;
156 int ret, elapsed, i;
157
158 for (elapsed = sleep_msecs; elapsed <= 600;
159 elapsed += sleep_msecs) {
160 msleep(sleep_msecs);
161 for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
162 ret = mdiobus_read(bus, i, MII_BMCR);
163 if (ret < 0)
164 return ret;
165 if (ret & BMCR_RESET)
166 break;
167 if (i == AR8XXX_NUM_PHYS - 1) {
168 usleep_range(1000, 2000);
169 return 0;
170 }
171 }
172 }
173 return -ETIMEDOUT;
174 }
175
176 static int
177 ar8xxx_phy_check_aneg(struct phy_device *phydev)
178 {
179 int ret;
180
181 if (phydev->autoneg != AUTONEG_ENABLE)
182 return 0;
183 /*
184 * BMCR_ANENABLE might have been cleared
185 * by phy_init_hw in certain kernel versions
186 * therefore check for it
187 */
188 ret = phy_read(phydev, MII_BMCR);
189 if (ret < 0)
190 return ret;
191 if (ret & BMCR_ANENABLE)
192 return 0;
193
194 dev_info(&phydev->mdio.dev, "ANEG disabled, re-enabling ...\n");
195 ret |= BMCR_ANENABLE | BMCR_ANRESTART;
196 return phy_write(phydev, MII_BMCR, ret);
197 }
198
199 void
200 ar8xxx_phy_init(struct ar8xxx_priv *priv)
201 {
202 int i;
203 struct mii_bus *bus;
204
205 bus = priv->sw_mii_bus ?: priv->mii_bus;
206 for (i = 0; i < AR8XXX_NUM_PHYS; i++) {
207 if (priv->chip->phy_fixup)
208 priv->chip->phy_fixup(priv, i);
209
210 /* initialize the port itself */
211 mdiobus_write(bus, i, MII_ADVERTISE,
212 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
213 if (ar8xxx_has_gige(priv))
214 mdiobus_write(bus, i, MII_CTRL1000, ADVERTISE_1000FULL);
215 mdiobus_write(bus, i, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
216 }
217
218 ar8xxx_phy_poll_reset(bus);
219 }
220
221 u32
222 ar8xxx_mii_read32(struct ar8xxx_priv *priv, int phy_id, int regnum)
223 {
224 struct mii_bus *bus = priv->mii_bus;
225 u16 lo, hi;
226
227 lo = bus->read(bus, phy_id, regnum);
228 hi = bus->read(bus, phy_id, regnum + 1);
229
230 return (hi << 16) | lo;
231 }
232
233 void
234 ar8xxx_mii_write32(struct ar8xxx_priv *priv, int phy_id, int regnum, u32 val)
235 {
236 struct mii_bus *bus = priv->mii_bus;
237 u16 lo, hi;
238
239 lo = val & 0xffff;
240 hi = (u16) (val >> 16);
241
242 if (priv->chip->mii_lo_first)
243 {
244 bus->write(bus, phy_id, regnum, lo);
245 bus->write(bus, phy_id, regnum + 1, hi);
246 } else {
247 bus->write(bus, phy_id, regnum + 1, hi);
248 bus->write(bus, phy_id, regnum, lo);
249 }
250 }
251
252 u32
253 ar8xxx_read(struct ar8xxx_priv *priv, int reg)
254 {
255 struct mii_bus *bus = priv->mii_bus;
256 u16 r1, r2, page;
257 u32 val;
258
259 split_addr((u32) reg, &r1, &r2, &page);
260
261 mutex_lock(&bus->mdio_lock);
262
263 bus->write(bus, 0x18, 0, page);
264 wait_for_page_switch();
265 val = ar8xxx_mii_read32(priv, 0x10 | r2, r1);
266
267 mutex_unlock(&bus->mdio_lock);
268
269 return val;
270 }
271
272 void
273 ar8xxx_write(struct ar8xxx_priv *priv, int reg, u32 val)
274 {
275 struct mii_bus *bus = priv->mii_bus;
276 u16 r1, r2, page;
277
278 split_addr((u32) reg, &r1, &r2, &page);
279
280 mutex_lock(&bus->mdio_lock);
281
282 bus->write(bus, 0x18, 0, page);
283 wait_for_page_switch();
284 ar8xxx_mii_write32(priv, 0x10 | r2, r1, val);
285
286 mutex_unlock(&bus->mdio_lock);
287 }
288
289 u32
290 ar8xxx_rmw(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
291 {
292 struct mii_bus *bus = priv->mii_bus;
293 u16 r1, r2, page;
294 u32 ret;
295
296 split_addr((u32) reg, &r1, &r2, &page);
297
298 mutex_lock(&bus->mdio_lock);
299
300 bus->write(bus, 0x18, 0, page);
301 wait_for_page_switch();
302
303 ret = ar8xxx_mii_read32(priv, 0x10 | r2, r1);
304 ret &= ~mask;
305 ret |= val;
306 ar8xxx_mii_write32(priv, 0x10 | r2, r1, ret);
307
308 mutex_unlock(&bus->mdio_lock);
309
310 return ret;
311 }
312 void
313 ar8xxx_phy_dbg_read(struct ar8xxx_priv *priv, int phy_addr,
314 u16 dbg_addr, u16 *dbg_data)
315 {
316 struct mii_bus *bus = priv->mii_bus;
317
318 mutex_lock(&bus->mdio_lock);
319 bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
320 *dbg_data = bus->read(bus, phy_addr, MII_ATH_DBG_DATA);
321 mutex_unlock(&bus->mdio_lock);
322 }
323
324 void
325 ar8xxx_phy_dbg_write(struct ar8xxx_priv *priv, int phy_addr,
326 u16 dbg_addr, u16 dbg_data)
327 {
328 struct mii_bus *bus = priv->mii_bus;
329
330 mutex_lock(&bus->mdio_lock);
331 bus->write(bus, phy_addr, MII_ATH_DBG_ADDR, dbg_addr);
332 bus->write(bus, phy_addr, MII_ATH_DBG_DATA, dbg_data);
333 mutex_unlock(&bus->mdio_lock);
334 }
335
336 static inline void
337 ar8xxx_phy_mmd_prep(struct mii_bus *bus, int phy_addr, u16 addr, u16 reg)
338 {
339 bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr);
340 bus->write(bus, phy_addr, MII_ATH_MMD_DATA, reg);
341 bus->write(bus, phy_addr, MII_ATH_MMD_ADDR, addr | 0x4000);
342 }
343
344 void
345 ar8xxx_phy_mmd_write(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 reg, u16 data)
346 {
347 struct mii_bus *bus = priv->mii_bus;
348
349 mutex_lock(&bus->mdio_lock);
350 ar8xxx_phy_mmd_prep(bus, phy_addr, addr, reg);
351 bus->write(bus, phy_addr, MII_ATH_MMD_DATA, data);
352 mutex_unlock(&bus->mdio_lock);
353 }
354
355 u16
356 ar8xxx_phy_mmd_read(struct ar8xxx_priv *priv, int phy_addr, u16 addr, u16 reg)
357 {
358 struct mii_bus *bus = priv->mii_bus;
359 u16 data;
360
361 mutex_lock(&bus->mdio_lock);
362 ar8xxx_phy_mmd_prep(bus, phy_addr, addr, reg);
363 data = bus->read(bus, phy_addr, MII_ATH_MMD_DATA);
364 mutex_unlock(&bus->mdio_lock);
365
366 return data;
367 }
368
369 static int
370 ar8xxx_reg_wait(struct ar8xxx_priv *priv, u32 reg, u32 mask, u32 val,
371 unsigned timeout)
372 {
373 int i;
374
375 for (i = 0; i < timeout; i++) {
376 u32 t;
377
378 t = ar8xxx_read(priv, reg);
379 if ((t & mask) == val)
380 return 0;
381
382 usleep_range(1000, 2000);
383 cond_resched();
384 }
385
386 return -ETIMEDOUT;
387 }
388
389 static int
390 ar8xxx_mib_op(struct ar8xxx_priv *priv, u32 op)
391 {
392 unsigned mib_func = priv->chip->mib_func;
393 int ret;
394
395 lockdep_assert_held(&priv->mib_lock);
396
397 /* Capture the hardware statistics for all ports */
398 ar8xxx_rmw(priv, mib_func, AR8216_MIB_FUNC, (op << AR8216_MIB_FUNC_S));
399
400 /* Wait for the capturing to complete. */
401 ret = ar8xxx_reg_wait(priv, mib_func, AR8216_MIB_BUSY, 0, 10);
402 if (ret)
403 goto out;
404
405 ret = 0;
406
407 out:
408 return ret;
409 }
410
411 static int
412 ar8xxx_mib_capture(struct ar8xxx_priv *priv)
413 {
414 return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_CAPTURE);
415 }
416
417 static int
418 ar8xxx_mib_flush(struct ar8xxx_priv *priv)
419 {
420 return ar8xxx_mib_op(priv, AR8216_MIB_FUNC_FLUSH);
421 }
422
423 static void
424 ar8xxx_mib_fetch_port_stat(struct ar8xxx_priv *priv, int port, bool flush)
425 {
426 unsigned int base;
427 u64 *mib_stats;
428 int i;
429
430 WARN_ON(port >= priv->dev.ports);
431
432 lockdep_assert_held(&priv->mib_lock);
433
434 base = priv->chip->reg_port_stats_start +
435 priv->chip->reg_port_stats_length * port;
436
437 mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
438 for (i = 0; i < priv->chip->num_mibs; i++) {
439 const struct ar8xxx_mib_desc *mib;
440 u64 t;
441
442 mib = &priv->chip->mib_decs[i];
443 if (mib->type > priv->mib_type)
444 continue;
445 t = ar8xxx_read(priv, base + mib->offset);
446 if (mib->size == 2) {
447 u64 hi;
448
449 hi = ar8xxx_read(priv, base + mib->offset + 4);
450 t |= hi << 32;
451 }
452
453 if (flush)
454 mib_stats[i] = 0;
455 else
456 mib_stats[i] += t;
457 cond_resched();
458 }
459 }
460
461 static void
462 ar8216_read_port_link(struct ar8xxx_priv *priv, int port,
463 struct switch_port_link *link)
464 {
465 u32 status;
466 u32 speed;
467
468 memset(link, '\0', sizeof(*link));
469
470 status = priv->chip->read_port_status(priv, port);
471
472 link->aneg = !!(status & AR8216_PORT_STATUS_LINK_AUTO);
473 if (link->aneg) {
474 link->link = !!(status & AR8216_PORT_STATUS_LINK_UP);
475 } else {
476 link->link = true;
477
478 if (priv->get_port_link) {
479 int err;
480
481 err = priv->get_port_link(port);
482 if (err >= 0)
483 link->link = !!err;
484 }
485 }
486
487 if (!link->link)
488 return;
489
490 link->duplex = !!(status & AR8216_PORT_STATUS_DUPLEX);
491 link->tx_flow = !!(status & AR8216_PORT_STATUS_TXFLOW);
492 link->rx_flow = !!(status & AR8216_PORT_STATUS_RXFLOW);
493
494 if (link->aneg && link->duplex && priv->chip->read_port_eee_status)
495 link->eee = priv->chip->read_port_eee_status(priv, port);
496
497 speed = (status & AR8216_PORT_STATUS_SPEED) >>
498 AR8216_PORT_STATUS_SPEED_S;
499
500 switch (speed) {
501 case AR8216_PORT_SPEED_10M:
502 link->speed = SWITCH_PORT_SPEED_10;
503 break;
504 case AR8216_PORT_SPEED_100M:
505 link->speed = SWITCH_PORT_SPEED_100;
506 break;
507 case AR8216_PORT_SPEED_1000M:
508 link->speed = SWITCH_PORT_SPEED_1000;
509 break;
510 default:
511 link->speed = SWITCH_PORT_SPEED_UNKNOWN;
512 break;
513 }
514 }
515
516 #ifdef CONFIG_ETHERNET_PACKET_MANGLE
517
518 static struct sk_buff *
519 ar8216_mangle_tx(struct net_device *dev, struct sk_buff *skb)
520 {
521 struct ar8xxx_priv *priv = dev->phy_ptr;
522 unsigned char *buf;
523
524 if (unlikely(!priv))
525 goto error;
526
527 if (!priv->vlan)
528 goto send;
529
530 if (unlikely(skb_headroom(skb) < 2)) {
531 if (pskb_expand_head(skb, 2, 0, GFP_ATOMIC) < 0)
532 goto error;
533 }
534
535 buf = skb_push(skb, 2);
536 buf[0] = 0x10;
537 buf[1] = 0x80;
538
539 send:
540 return skb;
541
542 error:
543 dev_kfree_skb_any(skb);
544 return NULL;
545 }
546
547 static void
548 ar8216_mangle_rx(struct net_device *dev, struct sk_buff *skb)
549 {
550 struct ar8xxx_priv *priv;
551 unsigned char *buf;
552 int port, vlan;
553
554 priv = dev->phy_ptr;
555 if (!priv)
556 return;
557
558 /* don't strip the header if vlan mode is disabled */
559 if (!priv->vlan)
560 return;
561
562 /* strip header, get vlan id */
563 buf = skb->data;
564 skb_pull(skb, 2);
565
566 /* check for vlan header presence */
567 if ((buf[12 + 2] != 0x81) || (buf[13 + 2] != 0x00))
568 return;
569
570 port = buf[0] & 0x7;
571
572 /* no need to fix up packets coming from a tagged source */
573 if (priv->vlan_tagged & (1 << port))
574 return;
575
576 /* lookup port vid from local table, the switch passes an invalid vlan id */
577 vlan = priv->vlan_id[priv->pvid[port]];
578
579 buf[14 + 2] &= 0xf0;
580 buf[14 + 2] |= vlan >> 8;
581 buf[15 + 2] = vlan & 0xff;
582 }
583
584 #endif
585
586 int
587 ar8216_wait_bit(struct ar8xxx_priv *priv, int reg, u32 mask, u32 val)
588 {
589 int timeout = 20;
590 u32 t = 0;
591
592 while (1) {
593 t = ar8xxx_read(priv, reg);
594 if ((t & mask) == val)
595 return 0;
596
597 if (timeout-- <= 0)
598 break;
599
600 udelay(10);
601 cond_resched();
602 }
603
604 pr_err("ar8216: timeout on reg %08x: %08x & %08x != %08x\n",
605 (unsigned int) reg, t, mask, val);
606 return -ETIMEDOUT;
607 }
608
609 static void
610 ar8216_vtu_op(struct ar8xxx_priv *priv, u32 op, u32 val)
611 {
612 if (ar8216_wait_bit(priv, AR8216_REG_VTU, AR8216_VTU_ACTIVE, 0))
613 return;
614 if ((op & AR8216_VTU_OP) == AR8216_VTU_OP_LOAD) {
615 val &= AR8216_VTUDATA_MEMBER;
616 val |= AR8216_VTUDATA_VALID;
617 ar8xxx_write(priv, AR8216_REG_VTU_DATA, val);
618 }
619 op |= AR8216_VTU_ACTIVE;
620 ar8xxx_write(priv, AR8216_REG_VTU, op);
621 }
622
623 static void
624 ar8216_vtu_flush(struct ar8xxx_priv *priv)
625 {
626 ar8216_vtu_op(priv, AR8216_VTU_OP_FLUSH, 0);
627 }
628
629 static void
630 ar8216_vtu_load_vlan(struct ar8xxx_priv *priv, u32 vid, u32 port_mask)
631 {
632 u32 op;
633
634 op = AR8216_VTU_OP_LOAD | (vid << AR8216_VTU_VID_S);
635 ar8216_vtu_op(priv, op, port_mask);
636 }
637
638 static int
639 ar8216_atu_flush(struct ar8xxx_priv *priv)
640 {
641 int ret;
642
643 ret = ar8216_wait_bit(priv, AR8216_REG_ATU_FUNC0, AR8216_ATU_ACTIVE, 0);
644 if (!ret)
645 ar8xxx_write(priv, AR8216_REG_ATU_FUNC0, AR8216_ATU_OP_FLUSH |
646 AR8216_ATU_ACTIVE);
647
648 return ret;
649 }
650
651 static int
652 ar8216_atu_flush_port(struct ar8xxx_priv *priv, int port)
653 {
654 u32 t;
655 int ret;
656
657 ret = ar8216_wait_bit(priv, AR8216_REG_ATU_FUNC0, AR8216_ATU_ACTIVE, 0);
658 if (!ret) {
659 t = (port << AR8216_ATU_PORT_NUM_S) | AR8216_ATU_OP_FLUSH_PORT;
660 t |= AR8216_ATU_ACTIVE;
661 ar8xxx_write(priv, AR8216_REG_ATU_FUNC0, t);
662 }
663
664 return ret;
665 }
666
667 static u32
668 ar8216_read_port_status(struct ar8xxx_priv *priv, int port)
669 {
670 return ar8xxx_read(priv, AR8216_REG_PORT_STATUS(port));
671 }
672
673 static void
674 __ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 members,
675 bool ath_hdr_en)
676 {
677 u32 header;
678 u32 egress, ingress;
679 u32 pvid;
680
681 if (priv->vlan) {
682 pvid = priv->vlan_id[priv->pvid[port]];
683 if (priv->vlan_tagged & (1 << port))
684 egress = AR8216_OUT_ADD_VLAN;
685 else
686 egress = AR8216_OUT_STRIP_VLAN;
687 ingress = AR8216_IN_SECURE;
688 } else {
689 pvid = port;
690 egress = AR8216_OUT_KEEP;
691 ingress = AR8216_IN_PORT_ONLY;
692 }
693
694 header = ath_hdr_en ? AR8216_PORT_CTRL_HEADER : 0;
695
696 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
697 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
698 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
699 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
700 AR8216_PORT_CTRL_LEARN | header |
701 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
702 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
703
704 ar8xxx_rmw(priv, AR8216_REG_PORT_VLAN(port),
705 AR8216_PORT_VLAN_DEST_PORTS | AR8216_PORT_VLAN_MODE |
706 AR8216_PORT_VLAN_DEFAULT_ID,
707 (members << AR8216_PORT_VLAN_DEST_PORTS_S) |
708 (ingress << AR8216_PORT_VLAN_MODE_S) |
709 (pvid << AR8216_PORT_VLAN_DEFAULT_ID_S));
710 }
711
712 static void
713 ar8216_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
714 {
715 return __ar8216_setup_port(priv, port, members,
716 chip_is_ar8216(priv) && priv->vlan &&
717 port == AR8216_PORT_CPU);
718 }
719
720 static int
721 ar8216_hw_init(struct ar8xxx_priv *priv)
722 {
723 if (priv->initialized)
724 return 0;
725
726 ar8xxx_write(priv, AR8216_REG_CTRL, AR8216_CTRL_RESET);
727 ar8xxx_reg_wait(priv, AR8216_REG_CTRL, AR8216_CTRL_RESET, 0, 1000);
728
729 ar8xxx_phy_init(priv);
730
731 priv->initialized = true;
732 return 0;
733 }
734
735 static void
736 ar8216_init_globals(struct ar8xxx_priv *priv)
737 {
738 /* standard atheros magic */
739 ar8xxx_write(priv, 0x38, 0xc000050e);
740
741 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
742 AR8216_GCTRL_MTU, 1518 + 8 + 2);
743 }
744
745 static void
746 __ar8216_init_port(struct ar8xxx_priv *priv, int port,
747 bool cpu_ge, bool flow_en)
748 {
749 /* Enable port learning and tx */
750 ar8xxx_write(priv, AR8216_REG_PORT_CTRL(port),
751 AR8216_PORT_CTRL_LEARN |
752 (4 << AR8216_PORT_CTRL_STATE_S));
753
754 ar8xxx_write(priv, AR8216_REG_PORT_VLAN(port), 0);
755
756 if (port == AR8216_PORT_CPU) {
757 ar8xxx_write(priv, AR8216_REG_PORT_STATUS(port),
758 AR8216_PORT_STATUS_LINK_UP |
759 (cpu_ge ? AR8216_PORT_SPEED_1000M : AR8216_PORT_SPEED_100M) |
760 AR8216_PORT_STATUS_TXMAC |
761 AR8216_PORT_STATUS_RXMAC |
762 (flow_en ? AR8216_PORT_STATUS_RXFLOW : 0) |
763 (flow_en ? AR8216_PORT_STATUS_TXFLOW : 0) |
764 AR8216_PORT_STATUS_DUPLEX);
765 } else {
766 ar8xxx_write(priv, AR8216_REG_PORT_STATUS(port),
767 AR8216_PORT_STATUS_LINK_AUTO);
768 }
769 }
770
771 static void
772 ar8216_init_port(struct ar8xxx_priv *priv, int port)
773 {
774 __ar8216_init_port(priv, port, ar8xxx_has_gige(priv),
775 chip_is_ar8316(priv));
776 }
777
778 static void
779 ar8216_wait_atu_ready(struct ar8xxx_priv *priv, u16 r2, u16 r1)
780 {
781 int timeout = 20;
782
783 while (ar8xxx_mii_read32(priv, r2, r1) & AR8216_ATU_ACTIVE && --timeout) {
784 udelay(10);
785 cond_resched();
786 }
787
788 if (!timeout)
789 pr_err("ar8216: timeout waiting for atu to become ready\n");
790 }
791
792 static void ar8216_get_arl_entry(struct ar8xxx_priv *priv,
793 struct arl_entry *a, u32 *status, enum arl_op op)
794 {
795 struct mii_bus *bus = priv->mii_bus;
796 u16 r2, page;
797 u16 r1_func0, r1_func1, r1_func2;
798 u32 t, val0, val1, val2;
799
800 split_addr(AR8216_REG_ATU_FUNC0, &r1_func0, &r2, &page);
801 r2 |= 0x10;
802
803 r1_func1 = (AR8216_REG_ATU_FUNC1 >> 1) & 0x1e;
804 r1_func2 = (AR8216_REG_ATU_FUNC2 >> 1) & 0x1e;
805
806 switch (op) {
807 case AR8XXX_ARL_INITIALIZE:
808 /* all ATU registers are on the same page
809 * therefore set page only once
810 */
811 bus->write(bus, 0x18, 0, page);
812 wait_for_page_switch();
813
814 ar8216_wait_atu_ready(priv, r2, r1_func0);
815
816 ar8xxx_mii_write32(priv, r2, r1_func0, AR8216_ATU_OP_GET_NEXT);
817 ar8xxx_mii_write32(priv, r2, r1_func1, 0);
818 ar8xxx_mii_write32(priv, r2, r1_func2, 0);
819 break;
820 case AR8XXX_ARL_GET_NEXT:
821 t = ar8xxx_mii_read32(priv, r2, r1_func0);
822 t |= AR8216_ATU_ACTIVE;
823 ar8xxx_mii_write32(priv, r2, r1_func0, t);
824 ar8216_wait_atu_ready(priv, r2, r1_func0);
825
826 val0 = ar8xxx_mii_read32(priv, r2, r1_func0);
827 val1 = ar8xxx_mii_read32(priv, r2, r1_func1);
828 val2 = ar8xxx_mii_read32(priv, r2, r1_func2);
829
830 *status = (val2 & AR8216_ATU_STATUS) >> AR8216_ATU_STATUS_S;
831 if (!*status)
832 break;
833
834 a->portmap = (val2 & AR8216_ATU_PORTS) >> AR8216_ATU_PORTS_S;
835 a->mac[0] = (val0 & AR8216_ATU_ADDR5) >> AR8216_ATU_ADDR5_S;
836 a->mac[1] = (val0 & AR8216_ATU_ADDR4) >> AR8216_ATU_ADDR4_S;
837 a->mac[2] = (val1 & AR8216_ATU_ADDR3) >> AR8216_ATU_ADDR3_S;
838 a->mac[3] = (val1 & AR8216_ATU_ADDR2) >> AR8216_ATU_ADDR2_S;
839 a->mac[4] = (val1 & AR8216_ATU_ADDR1) >> AR8216_ATU_ADDR1_S;
840 a->mac[5] = (val1 & AR8216_ATU_ADDR0) >> AR8216_ATU_ADDR0_S;
841 break;
842 }
843 }
844
845 static int
846 ar8216_phy_read(struct ar8xxx_priv *priv, int addr, int regnum)
847 {
848 u32 t, val = 0xffff;
849 int err;
850
851 if (addr >= AR8216_NUM_PORTS)
852 return 0xffff;
853 t = (regnum << AR8216_MDIO_CTRL_REG_ADDR_S) |
854 (addr << AR8216_MDIO_CTRL_PHY_ADDR_S) |
855 AR8216_MDIO_CTRL_MASTER_EN |
856 AR8216_MDIO_CTRL_BUSY |
857 AR8216_MDIO_CTRL_CMD_READ;
858
859 ar8xxx_write(priv, AR8216_REG_MDIO_CTRL, t);
860 err = ar8xxx_reg_wait(priv, AR8216_REG_MDIO_CTRL,
861 AR8216_MDIO_CTRL_BUSY, 0, 5);
862 if (!err)
863 val = ar8xxx_read(priv, AR8216_REG_MDIO_CTRL);
864
865 return val & AR8216_MDIO_CTRL_DATA_M;
866 }
867
868 static int
869 ar8216_phy_write(struct ar8xxx_priv *priv, int addr, int regnum, u16 val)
870 {
871 u32 t;
872 int ret;
873
874 if (addr >= AR8216_NUM_PORTS)
875 return -EINVAL;
876
877 t = (addr << AR8216_MDIO_CTRL_PHY_ADDR_S) |
878 (regnum << AR8216_MDIO_CTRL_REG_ADDR_S) |
879 AR8216_MDIO_CTRL_MASTER_EN |
880 AR8216_MDIO_CTRL_BUSY |
881 AR8216_MDIO_CTRL_CMD_WRITE |
882 val;
883
884 ar8xxx_write(priv, AR8216_REG_MDIO_CTRL, t);
885 ret = ar8xxx_reg_wait(priv, AR8216_REG_MDIO_CTRL,
886 AR8216_MDIO_CTRL_BUSY, 0, 5);
887
888 return ret;
889 }
890
891 static int
892 ar8229_hw_init(struct ar8xxx_priv *priv)
893 {
894 #if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 5, 0)
895 phy_interface_t phy_if_mode;
896 #else
897 int phy_if_mode;
898 #endif
899
900 if (priv->initialized)
901 return 0;
902
903 ar8xxx_write(priv, AR8216_REG_CTRL, AR8216_CTRL_RESET);
904 ar8xxx_reg_wait(priv, AR8216_REG_CTRL, AR8216_CTRL_RESET, 0, 1000);
905
906 #if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 5, 0)
907 of_get_phy_mode(priv->pdev->of_node, &phy_if_mode);
908 #else
909 phy_if_mode = of_get_phy_mode(priv->pdev->of_node);
910 #endif
911
912 if (phy_if_mode == PHY_INTERFACE_MODE_GMII) {
913 ar8xxx_write(priv, AR8229_REG_OPER_MODE0,
914 AR8229_OPER_MODE0_MAC_GMII_EN);
915 } else if (phy_if_mode == PHY_INTERFACE_MODE_MII) {
916 ar8xxx_write(priv, AR8229_REG_OPER_MODE0,
917 AR8229_OPER_MODE0_PHY_MII_EN);
918 } else {
919 pr_err("ar8229: unsupported mii mode\n");
920 return -EINVAL;
921 }
922
923 if (priv->port4_phy) {
924 ar8xxx_write(priv, AR8229_REG_OPER_MODE1,
925 AR8229_REG_OPER_MODE1_PHY4_MII_EN);
926 /* disable port5 to prevent mii conflict */
927 ar8xxx_write(priv, AR8216_REG_PORT_STATUS(5), 0);
928 }
929
930 ar8xxx_phy_init(priv);
931
932 priv->initialized = true;
933 return 0;
934 }
935
936 static void
937 ar8229_init_globals(struct ar8xxx_priv *priv)
938 {
939
940 /* Enable CPU port, and disable mirror port */
941 ar8xxx_write(priv, AR8216_REG_GLOBAL_CPUPORT,
942 AR8216_GLOBAL_CPUPORT_EN |
943 (15 << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
944
945 /* Setup TAG priority mapping */
946 ar8xxx_write(priv, AR8216_REG_TAG_PRIORITY, 0xfa50);
947
948 /* Enable aging, MAC replacing */
949 ar8xxx_write(priv, AR8216_REG_ATU_CTRL,
950 0x2b /* 5 min age time */ |
951 AR8216_ATU_CTRL_AGE_EN |
952 AR8216_ATU_CTRL_LEARN_CHANGE);
953
954 /* Enable ARP frame acknowledge */
955 ar8xxx_reg_set(priv, AR8229_REG_QM_CTRL,
956 AR8229_QM_CTRL_ARP_EN);
957
958 /*
959 * Enable Broadcast/unknown multicast and unicast frames
960 * transmitted to the CPU port.
961 */
962 ar8xxx_reg_set(priv, AR8216_REG_FLOOD_MASK,
963 AR8229_FLOOD_MASK_BC_DP(0) |
964 AR8229_FLOOD_MASK_MC_DP(0) |
965 AR8229_FLOOD_MASK_UC_DP(0));
966
967 /* setup MTU */
968 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
969 AR8236_GCTRL_MTU, AR8236_GCTRL_MTU);
970
971 /* Enable MIB counters */
972 ar8xxx_reg_set(priv, AR8216_REG_MIB_FUNC,
973 AR8236_MIB_EN);
974
975 /* setup Service TAG */
976 ar8xxx_rmw(priv, AR8216_REG_SERVICE_TAG, AR8216_SERVICE_TAG_M, 0);
977 }
978
979 static void
980 ar8229_init_port(struct ar8xxx_priv *priv, int port)
981 {
982 __ar8216_init_port(priv, port, true, true);
983 }
984
985
986 static int
987 ar7240sw_hw_init(struct ar8xxx_priv *priv)
988 {
989 if (priv->initialized)
990 return 0;
991
992 ar8xxx_write(priv, AR8216_REG_CTRL, AR8216_CTRL_RESET);
993 ar8xxx_reg_wait(priv, AR8216_REG_CTRL, AR8216_CTRL_RESET, 0, 1000);
994
995 priv->port4_phy = 1;
996 /* disable port5 to prevent mii conflict */
997 ar8xxx_write(priv, AR8216_REG_PORT_STATUS(5), 0);
998
999 ar8xxx_phy_init(priv);
1000
1001 priv->initialized = true;
1002 return 0;
1003 }
1004
1005 static void
1006 ar7240sw_init_globals(struct ar8xxx_priv *priv)
1007 {
1008
1009 /* Enable CPU port, and disable mirror port */
1010 ar8xxx_write(priv, AR8216_REG_GLOBAL_CPUPORT,
1011 AR8216_GLOBAL_CPUPORT_EN |
1012 (15 << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
1013
1014 /* Setup TAG priority mapping */
1015 ar8xxx_write(priv, AR8216_REG_TAG_PRIORITY, 0xfa50);
1016
1017 /* Enable ARP frame acknowledge, aging, MAC replacing */
1018 ar8xxx_write(priv, AR8216_REG_ATU_CTRL,
1019 AR8216_ATU_CTRL_RESERVED |
1020 0x2b /* 5 min age time */ |
1021 AR8216_ATU_CTRL_AGE_EN |
1022 AR8216_ATU_CTRL_ARP_EN |
1023 AR8216_ATU_CTRL_LEARN_CHANGE);
1024
1025 /* Enable Broadcast frames transmitted to the CPU */
1026 ar8xxx_reg_set(priv, AR8216_REG_FLOOD_MASK,
1027 AR8216_FM_CPU_BROADCAST_EN);
1028
1029 /* setup MTU */
1030 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
1031 AR8216_GCTRL_MTU,
1032 AR8216_GCTRL_MTU);
1033
1034 /* setup Service TAG */
1035 ar8xxx_rmw(priv, AR8216_REG_SERVICE_TAG, AR8216_SERVICE_TAG_M, 0);
1036 }
1037
1038 static void
1039 ar7240sw_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
1040 {
1041 return __ar8216_setup_port(priv, port, members, false);
1042 }
1043
1044 static void
1045 ar8236_setup_port(struct ar8xxx_priv *priv, int port, u32 members)
1046 {
1047 u32 egress, ingress;
1048 u32 pvid;
1049
1050 if (priv->vlan) {
1051 pvid = priv->vlan_id[priv->pvid[port]];
1052 if (priv->vlan_tagged & (1 << port))
1053 egress = AR8216_OUT_ADD_VLAN;
1054 else
1055 egress = AR8216_OUT_STRIP_VLAN;
1056 ingress = AR8216_IN_SECURE;
1057 } else {
1058 pvid = port;
1059 egress = AR8216_OUT_KEEP;
1060 ingress = AR8216_IN_PORT_ONLY;
1061 }
1062
1063 ar8xxx_rmw(priv, AR8216_REG_PORT_CTRL(port),
1064 AR8216_PORT_CTRL_LEARN | AR8216_PORT_CTRL_VLAN_MODE |
1065 AR8216_PORT_CTRL_SINGLE_VLAN | AR8216_PORT_CTRL_STATE |
1066 AR8216_PORT_CTRL_HEADER | AR8216_PORT_CTRL_LEARN_LOCK,
1067 AR8216_PORT_CTRL_LEARN |
1068 (egress << AR8216_PORT_CTRL_VLAN_MODE_S) |
1069 (AR8216_PORT_STATE_FORWARD << AR8216_PORT_CTRL_STATE_S));
1070
1071 ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN(port),
1072 AR8236_PORT_VLAN_DEFAULT_ID,
1073 (pvid << AR8236_PORT_VLAN_DEFAULT_ID_S));
1074
1075 ar8xxx_rmw(priv, AR8236_REG_PORT_VLAN2(port),
1076 AR8236_PORT_VLAN2_VLAN_MODE |
1077 AR8236_PORT_VLAN2_MEMBER,
1078 (ingress << AR8236_PORT_VLAN2_VLAN_MODE_S) |
1079 (members << AR8236_PORT_VLAN2_MEMBER_S));
1080 }
1081
1082 static void
1083 ar8236_init_globals(struct ar8xxx_priv *priv)
1084 {
1085 /* enable jumbo frames */
1086 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
1087 AR8316_GCTRL_MTU, 9018 + 8 + 2);
1088
1089 /* enable cpu port to receive arp frames */
1090 ar8xxx_reg_set(priv, AR8216_REG_ATU_CTRL,
1091 AR8236_ATU_CTRL_RES);
1092
1093 /*
1094 * Enable Broadcast/unknown multicast and unicast frames
1095 * transmitted to the CPU port.
1096 */
1097 ar8xxx_reg_set(priv, AR8216_REG_FLOOD_MASK,
1098 AR8229_FLOOD_MASK_BC_DP(0) |
1099 AR8229_FLOOD_MASK_MC_DP(0) |
1100 AR8229_FLOOD_MASK_UC_DP(0));
1101
1102 /* Enable MIB counters */
1103 ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
1104 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
1105 AR8236_MIB_EN);
1106 }
1107
1108 static int
1109 ar8316_hw_init(struct ar8xxx_priv *priv)
1110 {
1111 u32 val, newval;
1112
1113 val = ar8xxx_read(priv, AR8316_REG_POSTRIP);
1114
1115 if (priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
1116 if (priv->port4_phy) {
1117 /* value taken from Ubiquiti RouterStation Pro */
1118 newval = 0x81461bea;
1119 pr_info("ar8316: Using port 4 as PHY\n");
1120 } else {
1121 newval = 0x01261be2;
1122 pr_info("ar8316: Using port 4 as switch port\n");
1123 }
1124 } else if (priv->phy->interface == PHY_INTERFACE_MODE_GMII) {
1125 /* value taken from AVM Fritz!Box 7390 sources */
1126 newval = 0x010e5b71;
1127 } else {
1128 /* no known value for phy interface */
1129 pr_err("ar8316: unsupported mii mode: %d.\n",
1130 priv->phy->interface);
1131 return -EINVAL;
1132 }
1133
1134 if (val == newval)
1135 goto out;
1136
1137 ar8xxx_write(priv, AR8316_REG_POSTRIP, newval);
1138
1139 if (priv->port4_phy &&
1140 priv->phy->interface == PHY_INTERFACE_MODE_RGMII) {
1141 /* work around for phy4 rgmii mode */
1142 ar8xxx_phy_dbg_write(priv, 4, 0x12, 0x480c);
1143 /* rx delay */
1144 ar8xxx_phy_dbg_write(priv, 4, 0x0, 0x824e);
1145 /* tx delay */
1146 ar8xxx_phy_dbg_write(priv, 4, 0x5, 0x3d47);
1147 msleep(1000);
1148 }
1149
1150 ar8xxx_phy_init(priv);
1151
1152 out:
1153 priv->initialized = true;
1154 return 0;
1155 }
1156
1157 static void
1158 ar8316_init_globals(struct ar8xxx_priv *priv)
1159 {
1160 /* standard atheros magic */
1161 ar8xxx_write(priv, 0x38, 0xc000050e);
1162
1163 /* enable cpu port to receive multicast and broadcast frames */
1164 ar8xxx_write(priv, AR8216_REG_FLOOD_MASK, 0x003f003f);
1165
1166 /* enable jumbo frames */
1167 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CTRL,
1168 AR8316_GCTRL_MTU, 9018 + 8 + 2);
1169
1170 /* Enable MIB counters */
1171 ar8xxx_rmw(priv, AR8216_REG_MIB_FUNC, AR8216_MIB_FUNC | AR8236_MIB_EN,
1172 (AR8216_MIB_FUNC_NO_OP << AR8216_MIB_FUNC_S) |
1173 AR8236_MIB_EN);
1174 }
1175
1176 int
1177 ar8xxx_sw_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1178 struct switch_val *val)
1179 {
1180 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1181 priv->vlan = !!val->value.i;
1182 return 0;
1183 }
1184
1185 int
1186 ar8xxx_sw_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
1187 struct switch_val *val)
1188 {
1189 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1190 val->value.i = priv->vlan;
1191 return 0;
1192 }
1193
1194
1195 int
1196 ar8xxx_sw_set_pvid(struct switch_dev *dev, int port, int vlan)
1197 {
1198 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1199
1200 /* make sure no invalid PVIDs get set */
1201
1202 if (vlan < 0 || vlan >= dev->vlans ||
1203 port < 0 || port >= AR8X16_MAX_PORTS)
1204 return -EINVAL;
1205
1206 priv->pvid[port] = vlan;
1207 return 0;
1208 }
1209
1210 int
1211 ar8xxx_sw_get_pvid(struct switch_dev *dev, int port, int *vlan)
1212 {
1213 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1214
1215 if (port < 0 || port >= AR8X16_MAX_PORTS)
1216 return -EINVAL;
1217
1218 *vlan = priv->pvid[port];
1219 return 0;
1220 }
1221
1222 static int
1223 ar8xxx_sw_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
1224 struct switch_val *val)
1225 {
1226 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1227
1228 if (val->port_vlan >= dev->vlans)
1229 return -EINVAL;
1230
1231 priv->vlan_id[val->port_vlan] = val->value.i;
1232 return 0;
1233 }
1234
1235 static int
1236 ar8xxx_sw_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
1237 struct switch_val *val)
1238 {
1239 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1240 val->value.i = priv->vlan_id[val->port_vlan];
1241 return 0;
1242 }
1243
1244 int
1245 ar8xxx_sw_get_port_link(struct switch_dev *dev, int port,
1246 struct switch_port_link *link)
1247 {
1248 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1249
1250 ar8216_read_port_link(priv, port, link);
1251 return 0;
1252 }
1253
1254 static int
1255 ar8xxx_sw_get_ports(struct switch_dev *dev, struct switch_val *val)
1256 {
1257 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1258 u8 ports;
1259 int i;
1260
1261 if (val->port_vlan >= dev->vlans)
1262 return -EINVAL;
1263
1264 ports = priv->vlan_table[val->port_vlan];
1265 val->len = 0;
1266 for (i = 0; i < dev->ports; i++) {
1267 struct switch_port *p;
1268
1269 if (!(ports & (1 << i)))
1270 continue;
1271
1272 p = &val->value.ports[val->len++];
1273 p->id = i;
1274 if (priv->vlan_tagged & (1 << i))
1275 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
1276 else
1277 p->flags = 0;
1278 }
1279 return 0;
1280 }
1281
1282 static int
1283 ar8xxx_sw_set_ports(struct switch_dev *dev, struct switch_val *val)
1284 {
1285 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1286 u8 *vt = &priv->vlan_table[val->port_vlan];
1287 int i, j;
1288
1289 *vt = 0;
1290 for (i = 0; i < val->len; i++) {
1291 struct switch_port *p = &val->value.ports[i];
1292
1293 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED)) {
1294 priv->vlan_tagged |= (1 << p->id);
1295 } else {
1296 priv->vlan_tagged &= ~(1 << p->id);
1297 priv->pvid[p->id] = val->port_vlan;
1298
1299 /* make sure that an untagged port does not
1300 * appear in other vlans */
1301 for (j = 0; j < dev->vlans; j++) {
1302 if (j == val->port_vlan)
1303 continue;
1304 priv->vlan_table[j] &= ~(1 << p->id);
1305 }
1306 }
1307
1308 *vt |= 1 << p->id;
1309 }
1310 return 0;
1311 }
1312
1313 static void
1314 ar8216_set_mirror_regs(struct ar8xxx_priv *priv)
1315 {
1316 int port;
1317
1318 /* reset all mirror registers */
1319 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
1320 AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
1321 (0xF << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
1322 for (port = 0; port < AR8216_NUM_PORTS; port++) {
1323 ar8xxx_reg_clear(priv, AR8216_REG_PORT_CTRL(port),
1324 AR8216_PORT_CTRL_MIRROR_RX);
1325
1326 ar8xxx_reg_clear(priv, AR8216_REG_PORT_CTRL(port),
1327 AR8216_PORT_CTRL_MIRROR_TX);
1328 }
1329
1330 /* now enable mirroring if necessary */
1331 if (priv->source_port >= AR8216_NUM_PORTS ||
1332 priv->monitor_port >= AR8216_NUM_PORTS ||
1333 priv->source_port == priv->monitor_port) {
1334 return;
1335 }
1336
1337 ar8xxx_rmw(priv, AR8216_REG_GLOBAL_CPUPORT,
1338 AR8216_GLOBAL_CPUPORT_MIRROR_PORT,
1339 (priv->monitor_port << AR8216_GLOBAL_CPUPORT_MIRROR_PORT_S));
1340
1341 if (priv->mirror_rx)
1342 ar8xxx_reg_set(priv, AR8216_REG_PORT_CTRL(priv->source_port),
1343 AR8216_PORT_CTRL_MIRROR_RX);
1344
1345 if (priv->mirror_tx)
1346 ar8xxx_reg_set(priv, AR8216_REG_PORT_CTRL(priv->source_port),
1347 AR8216_PORT_CTRL_MIRROR_TX);
1348 }
1349
1350 static inline u32
1351 ar8xxx_age_time_val(int age_time)
1352 {
1353 return (age_time + AR8XXX_REG_ARL_CTRL_AGE_TIME_SECS / 2) /
1354 AR8XXX_REG_ARL_CTRL_AGE_TIME_SECS;
1355 }
1356
1357 static inline void
1358 ar8xxx_set_age_time(struct ar8xxx_priv *priv, int reg)
1359 {
1360 u32 age_time = ar8xxx_age_time_val(priv->arl_age_time);
1361 ar8xxx_rmw(priv, reg, AR8216_ATU_CTRL_AGE_TIME, age_time << AR8216_ATU_CTRL_AGE_TIME_S);
1362 }
1363
1364 int
1365 ar8xxx_sw_hw_apply(struct switch_dev *dev)
1366 {
1367 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1368 const struct ar8xxx_chip *chip = priv->chip;
1369 u8 portmask[AR8X16_MAX_PORTS];
1370 int i, j;
1371
1372 mutex_lock(&priv->reg_mutex);
1373 /* flush all vlan translation unit entries */
1374 priv->chip->vtu_flush(priv);
1375
1376 memset(portmask, 0, sizeof(portmask));
1377 if (!priv->init) {
1378 /* calculate the port destination masks and load vlans
1379 * into the vlan translation unit */
1380 for (j = 0; j < dev->vlans; j++) {
1381 u8 vp = priv->vlan_table[j];
1382
1383 if (!vp)
1384 continue;
1385
1386 for (i = 0; i < dev->ports; i++) {
1387 u8 mask = (1 << i);
1388 if (vp & mask)
1389 portmask[i] |= vp & ~mask;
1390 }
1391
1392 chip->vtu_load_vlan(priv, priv->vlan_id[j],
1393 priv->vlan_table[j]);
1394 }
1395 } else {
1396 /* vlan disabled:
1397 * isolate all ports, but connect them to the cpu port */
1398 for (i = 0; i < dev->ports; i++) {
1399 if (i == AR8216_PORT_CPU)
1400 continue;
1401
1402 portmask[i] = 1 << AR8216_PORT_CPU;
1403 portmask[AR8216_PORT_CPU] |= (1 << i);
1404 }
1405 }
1406
1407 /* update the port destination mask registers and tag settings */
1408 for (i = 0; i < dev->ports; i++) {
1409 chip->setup_port(priv, i, portmask[i]);
1410 }
1411
1412 chip->set_mirror_regs(priv);
1413
1414 /* set age time */
1415 if (chip->reg_arl_ctrl)
1416 ar8xxx_set_age_time(priv, chip->reg_arl_ctrl);
1417
1418 mutex_unlock(&priv->reg_mutex);
1419 return 0;
1420 }
1421
1422 int
1423 ar8xxx_sw_reset_switch(struct switch_dev *dev)
1424 {
1425 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1426 const struct ar8xxx_chip *chip = priv->chip;
1427 int i;
1428
1429 mutex_lock(&priv->reg_mutex);
1430 memset(&priv->vlan, 0, sizeof(struct ar8xxx_priv) -
1431 offsetof(struct ar8xxx_priv, vlan));
1432
1433 for (i = 0; i < dev->vlans; i++)
1434 priv->vlan_id[i] = i;
1435
1436 /* Configure all ports */
1437 for (i = 0; i < dev->ports; i++)
1438 chip->init_port(priv, i);
1439
1440 priv->mirror_rx = false;
1441 priv->mirror_tx = false;
1442 priv->source_port = 0;
1443 priv->monitor_port = 0;
1444 priv->arl_age_time = AR8XXX_DEFAULT_ARL_AGE_TIME;
1445
1446 chip->init_globals(priv);
1447 chip->atu_flush(priv);
1448
1449 mutex_unlock(&priv->reg_mutex);
1450
1451 return chip->sw_hw_apply(dev);
1452 }
1453
1454 int
1455 ar8xxx_sw_set_reset_mibs(struct switch_dev *dev,
1456 const struct switch_attr *attr,
1457 struct switch_val *val)
1458 {
1459 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1460 unsigned int len;
1461 int ret;
1462
1463 if (!ar8xxx_has_mib_counters(priv))
1464 return -EOPNOTSUPP;
1465
1466 mutex_lock(&priv->mib_lock);
1467
1468 len = priv->dev.ports * priv->chip->num_mibs *
1469 sizeof(*priv->mib_stats);
1470 memset(priv->mib_stats, '\0', len);
1471 ret = ar8xxx_mib_flush(priv);
1472 if (ret)
1473 goto unlock;
1474
1475 ret = 0;
1476
1477 unlock:
1478 mutex_unlock(&priv->mib_lock);
1479 return ret;
1480 }
1481
1482 int
1483 ar8xxx_sw_set_mib_poll_interval(struct switch_dev *dev,
1484 const struct switch_attr *attr,
1485 struct switch_val *val)
1486 {
1487 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1488
1489 if (!ar8xxx_has_mib_counters(priv))
1490 return -EOPNOTSUPP;
1491
1492 ar8xxx_mib_stop(priv);
1493 priv->mib_poll_interval = val->value.i;
1494 ar8xxx_mib_start(priv);
1495
1496 return 0;
1497 }
1498
1499 int
1500 ar8xxx_sw_get_mib_poll_interval(struct switch_dev *dev,
1501 const struct switch_attr *attr,
1502 struct switch_val *val)
1503 {
1504 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1505
1506 if (!ar8xxx_has_mib_counters(priv))
1507 return -EOPNOTSUPP;
1508 val->value.i = priv->mib_poll_interval;
1509 return 0;
1510 }
1511
1512 int
1513 ar8xxx_sw_set_mib_type(struct switch_dev *dev,
1514 const struct switch_attr *attr,
1515 struct switch_val *val)
1516 {
1517 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1518
1519 if (!ar8xxx_has_mib_counters(priv))
1520 return -EOPNOTSUPP;
1521 priv->mib_type = val->value.i;
1522 return 0;
1523 }
1524
1525 int
1526 ar8xxx_sw_get_mib_type(struct switch_dev *dev,
1527 const struct switch_attr *attr,
1528 struct switch_val *val)
1529 {
1530 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1531
1532 if (!ar8xxx_has_mib_counters(priv))
1533 return -EOPNOTSUPP;
1534 val->value.i = priv->mib_type;
1535 return 0;
1536 }
1537
1538 int
1539 ar8xxx_sw_set_mirror_rx_enable(struct switch_dev *dev,
1540 const struct switch_attr *attr,
1541 struct switch_val *val)
1542 {
1543 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1544
1545 mutex_lock(&priv->reg_mutex);
1546 priv->mirror_rx = !!val->value.i;
1547 priv->chip->set_mirror_regs(priv);
1548 mutex_unlock(&priv->reg_mutex);
1549
1550 return 0;
1551 }
1552
1553 int
1554 ar8xxx_sw_get_mirror_rx_enable(struct switch_dev *dev,
1555 const struct switch_attr *attr,
1556 struct switch_val *val)
1557 {
1558 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1559 val->value.i = priv->mirror_rx;
1560 return 0;
1561 }
1562
1563 int
1564 ar8xxx_sw_set_mirror_tx_enable(struct switch_dev *dev,
1565 const struct switch_attr *attr,
1566 struct switch_val *val)
1567 {
1568 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1569
1570 mutex_lock(&priv->reg_mutex);
1571 priv->mirror_tx = !!val->value.i;
1572 priv->chip->set_mirror_regs(priv);
1573 mutex_unlock(&priv->reg_mutex);
1574
1575 return 0;
1576 }
1577
1578 int
1579 ar8xxx_sw_get_mirror_tx_enable(struct switch_dev *dev,
1580 const struct switch_attr *attr,
1581 struct switch_val *val)
1582 {
1583 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1584 val->value.i = priv->mirror_tx;
1585 return 0;
1586 }
1587
1588 int
1589 ar8xxx_sw_set_mirror_monitor_port(struct switch_dev *dev,
1590 const struct switch_attr *attr,
1591 struct switch_val *val)
1592 {
1593 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1594
1595 mutex_lock(&priv->reg_mutex);
1596 priv->monitor_port = val->value.i;
1597 priv->chip->set_mirror_regs(priv);
1598 mutex_unlock(&priv->reg_mutex);
1599
1600 return 0;
1601 }
1602
1603 int
1604 ar8xxx_sw_get_mirror_monitor_port(struct switch_dev *dev,
1605 const struct switch_attr *attr,
1606 struct switch_val *val)
1607 {
1608 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1609 val->value.i = priv->monitor_port;
1610 return 0;
1611 }
1612
1613 int
1614 ar8xxx_sw_set_mirror_source_port(struct switch_dev *dev,
1615 const struct switch_attr *attr,
1616 struct switch_val *val)
1617 {
1618 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1619
1620 mutex_lock(&priv->reg_mutex);
1621 priv->source_port = val->value.i;
1622 priv->chip->set_mirror_regs(priv);
1623 mutex_unlock(&priv->reg_mutex);
1624
1625 return 0;
1626 }
1627
1628 int
1629 ar8xxx_sw_get_mirror_source_port(struct switch_dev *dev,
1630 const struct switch_attr *attr,
1631 struct switch_val *val)
1632 {
1633 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1634 val->value.i = priv->source_port;
1635 return 0;
1636 }
1637
1638 int
1639 ar8xxx_sw_set_port_reset_mib(struct switch_dev *dev,
1640 const struct switch_attr *attr,
1641 struct switch_val *val)
1642 {
1643 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1644 int port;
1645 int ret;
1646
1647 if (!ar8xxx_has_mib_counters(priv))
1648 return -EOPNOTSUPP;
1649
1650 port = val->port_vlan;
1651 if (port >= dev->ports)
1652 return -EINVAL;
1653
1654 mutex_lock(&priv->mib_lock);
1655 ret = ar8xxx_mib_capture(priv);
1656 if (ret)
1657 goto unlock;
1658
1659 ar8xxx_mib_fetch_port_stat(priv, port, true);
1660
1661 ret = 0;
1662
1663 unlock:
1664 mutex_unlock(&priv->mib_lock);
1665 return ret;
1666 }
1667
1668 static void
1669 ar8xxx_byte_to_str(char *buf, int len, u64 byte)
1670 {
1671 unsigned long b;
1672 const char *unit;
1673
1674 if (byte >= 0x40000000) { /* 1 GiB */
1675 b = byte * 10 / 0x40000000;
1676 unit = "GiB";
1677 } else if (byte >= 0x100000) { /* 1 MiB */
1678 b = byte * 10 / 0x100000;
1679 unit = "MiB";
1680 } else if (byte >= 0x400) { /* 1 KiB */
1681 b = byte * 10 / 0x400;
1682 unit = "KiB";
1683 } else {
1684 b = byte;
1685 unit = "Byte";
1686 }
1687 if (strcmp(unit, "Byte"))
1688 snprintf(buf, len, "%lu.%lu %s", b / 10, b % 10, unit);
1689 else
1690 snprintf(buf, len, "%lu %s", b, unit);
1691 }
1692
1693 int
1694 ar8xxx_sw_get_port_mib(struct switch_dev *dev,
1695 const struct switch_attr *attr,
1696 struct switch_val *val)
1697 {
1698 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1699 const struct ar8xxx_chip *chip = priv->chip;
1700 u64 *mib_stats, mib_data;
1701 unsigned int port;
1702 int ret;
1703 char *buf = priv->buf;
1704 char buf1[64];
1705 const char *mib_name;
1706 int i, len = 0;
1707 bool mib_stats_empty = true;
1708
1709 if (!ar8xxx_has_mib_counters(priv) || !priv->mib_poll_interval)
1710 return -EOPNOTSUPP;
1711
1712 port = val->port_vlan;
1713 if (port >= dev->ports)
1714 return -EINVAL;
1715
1716 mutex_lock(&priv->mib_lock);
1717 ret = ar8xxx_mib_capture(priv);
1718 if (ret)
1719 goto unlock;
1720
1721 ar8xxx_mib_fetch_port_stat(priv, port, false);
1722
1723 len += snprintf(buf + len, sizeof(priv->buf) - len,
1724 "MIB counters\n");
1725
1726 mib_stats = &priv->mib_stats[port * chip->num_mibs];
1727 for (i = 0; i < chip->num_mibs; i++) {
1728 if (chip->mib_decs[i].type > priv->mib_type)
1729 continue;
1730 mib_name = chip->mib_decs[i].name;
1731 mib_data = mib_stats[i];
1732 len += snprintf(buf + len, sizeof(priv->buf) - len,
1733 "%-12s: %llu\n", mib_name, mib_data);
1734 if ((!strcmp(mib_name, "TxByte") ||
1735 !strcmp(mib_name, "RxGoodByte")) &&
1736 mib_data >= 1024) {
1737 ar8xxx_byte_to_str(buf1, sizeof(buf1), mib_data);
1738 --len; /* discard newline at the end of buf */
1739 len += snprintf(buf + len, sizeof(priv->buf) - len,
1740 " (%s)\n", buf1);
1741 }
1742 if (mib_stats_empty && mib_data)
1743 mib_stats_empty = false;
1744 }
1745
1746 if (mib_stats_empty)
1747 len = snprintf(buf, sizeof(priv->buf), "No MIB data");
1748
1749 val->value.s = buf;
1750 val->len = len;
1751
1752 ret = 0;
1753
1754 unlock:
1755 mutex_unlock(&priv->mib_lock);
1756 return ret;
1757 }
1758
1759 int
1760 ar8xxx_sw_set_arl_age_time(struct switch_dev *dev, const struct switch_attr *attr,
1761 struct switch_val *val)
1762 {
1763 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1764 int age_time = val->value.i;
1765 u32 age_time_val;
1766
1767 if (age_time < 0)
1768 return -EINVAL;
1769
1770 age_time_val = ar8xxx_age_time_val(age_time);
1771 if (age_time_val == 0 || age_time_val > 0xffff)
1772 return -EINVAL;
1773
1774 priv->arl_age_time = age_time;
1775 return 0;
1776 }
1777
1778 int
1779 ar8xxx_sw_get_arl_age_time(struct switch_dev *dev, const struct switch_attr *attr,
1780 struct switch_val *val)
1781 {
1782 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1783 val->value.i = priv->arl_age_time;
1784 return 0;
1785 }
1786
1787 int
1788 ar8xxx_sw_get_arl_table(struct switch_dev *dev,
1789 const struct switch_attr *attr,
1790 struct switch_val *val)
1791 {
1792 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1793 struct mii_bus *bus = priv->mii_bus;
1794 const struct ar8xxx_chip *chip = priv->chip;
1795 char *buf = priv->arl_buf;
1796 int i, j, k, len = 0;
1797 struct arl_entry *a, *a1;
1798 u32 status;
1799
1800 if (!chip->get_arl_entry)
1801 return -EOPNOTSUPP;
1802
1803 mutex_lock(&priv->reg_mutex);
1804 mutex_lock(&bus->mdio_lock);
1805
1806 chip->get_arl_entry(priv, NULL, NULL, AR8XXX_ARL_INITIALIZE);
1807
1808 for(i = 0; i < AR8XXX_NUM_ARL_RECORDS; ++i) {
1809 a = &priv->arl_table[i];
1810 duplicate:
1811 chip->get_arl_entry(priv, a, &status, AR8XXX_ARL_GET_NEXT);
1812
1813 if (!status)
1814 break;
1815
1816 /* avoid duplicates
1817 * ARL table can include multiple valid entries
1818 * per MAC, just with differing status codes
1819 */
1820 for (j = 0; j < i; ++j) {
1821 a1 = &priv->arl_table[j];
1822 if (!memcmp(a->mac, a1->mac, sizeof(a->mac))) {
1823 /* ignore ports already seen in former entry */
1824 a->portmap &= ~a1->portmap;
1825 if (!a->portmap)
1826 goto duplicate;
1827 }
1828 }
1829 }
1830
1831 mutex_unlock(&bus->mdio_lock);
1832
1833 len += snprintf(buf + len, sizeof(priv->arl_buf) - len,
1834 "address resolution table\n");
1835
1836 if (i == AR8XXX_NUM_ARL_RECORDS)
1837 len += snprintf(buf + len, sizeof(priv->arl_buf) - len,
1838 "Too many entries found, displaying the first %d only!\n",
1839 AR8XXX_NUM_ARL_RECORDS);
1840
1841 for (j = 0; j < priv->dev.ports; ++j) {
1842 for (k = 0; k < i; ++k) {
1843 a = &priv->arl_table[k];
1844 if (!(a->portmap & BIT(j)))
1845 continue;
1846 len += snprintf(buf + len, sizeof(priv->arl_buf) - len,
1847 "Port %d: MAC %02x:%02x:%02x:%02x:%02x:%02x\n",
1848 j,
1849 a->mac[5], a->mac[4], a->mac[3],
1850 a->mac[2], a->mac[1], a->mac[0]);
1851 }
1852 }
1853
1854 val->value.s = buf;
1855 val->len = len;
1856
1857 mutex_unlock(&priv->reg_mutex);
1858
1859 return 0;
1860 }
1861
1862 int
1863 ar8xxx_sw_set_flush_arl_table(struct switch_dev *dev,
1864 const struct switch_attr *attr,
1865 struct switch_val *val)
1866 {
1867 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1868 int ret;
1869
1870 mutex_lock(&priv->reg_mutex);
1871 ret = priv->chip->atu_flush(priv);
1872 mutex_unlock(&priv->reg_mutex);
1873
1874 return ret;
1875 }
1876
1877 int
1878 ar8xxx_sw_set_flush_port_arl_table(struct switch_dev *dev,
1879 const struct switch_attr *attr,
1880 struct switch_val *val)
1881 {
1882 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1883 int port, ret;
1884
1885 port = val->port_vlan;
1886 if (port >= dev->ports)
1887 return -EINVAL;
1888
1889 mutex_lock(&priv->reg_mutex);
1890 ret = priv->chip->atu_flush_port(priv, port);
1891 mutex_unlock(&priv->reg_mutex);
1892
1893 return ret;
1894 }
1895
1896 int
1897 ar8xxx_sw_get_port_stats(struct switch_dev *dev, int port,
1898 struct switch_port_stats *stats)
1899 {
1900 struct ar8xxx_priv *priv = swdev_to_ar8xxx(dev);
1901 u64 *mib_stats;
1902
1903 if (!ar8xxx_has_mib_counters(priv) || !priv->mib_poll_interval)
1904 return -EOPNOTSUPP;
1905
1906 if (!(priv->chip->mib_rxb_id || priv->chip->mib_txb_id))
1907 return -EOPNOTSUPP;
1908
1909 if (port >= dev->ports)
1910 return -EINVAL;
1911
1912 mutex_lock(&priv->mib_lock);
1913
1914 mib_stats = &priv->mib_stats[port * priv->chip->num_mibs];
1915
1916 stats->tx_bytes = mib_stats[priv->chip->mib_txb_id];
1917 stats->rx_bytes = mib_stats[priv->chip->mib_rxb_id];
1918
1919 mutex_unlock(&priv->mib_lock);
1920 return 0;
1921 }
1922
1923 static int
1924 ar8xxx_phy_read(struct mii_bus *bus, int phy_addr, int reg_addr)
1925 {
1926 struct ar8xxx_priv *priv = bus->priv;
1927 return priv->chip->phy_read(priv, phy_addr, reg_addr);
1928 }
1929
1930 static int
1931 ar8xxx_phy_write(struct mii_bus *bus, int phy_addr, int reg_addr,
1932 u16 reg_val)
1933 {
1934 struct ar8xxx_priv *priv = bus->priv;
1935 return priv->chip->phy_write(priv, phy_addr, reg_addr, reg_val);
1936 }
1937
1938 static const struct switch_attr ar8xxx_sw_attr_globals[] = {
1939 {
1940 .type = SWITCH_TYPE_INT,
1941 .name = "enable_vlan",
1942 .description = "Enable VLAN mode",
1943 .set = ar8xxx_sw_set_vlan,
1944 .get = ar8xxx_sw_get_vlan,
1945 .max = 1
1946 },
1947 {
1948 .type = SWITCH_TYPE_NOVAL,
1949 .name = "reset_mibs",
1950 .description = "Reset all MIB counters",
1951 .set = ar8xxx_sw_set_reset_mibs,
1952 },
1953 {
1954 .type = SWITCH_TYPE_INT,
1955 .name = "ar8xxx_mib_poll_interval",
1956 .description = "MIB polling interval in msecs (0 to disable)",
1957 .set = ar8xxx_sw_set_mib_poll_interval,
1958 .get = ar8xxx_sw_get_mib_poll_interval
1959 },
1960 {
1961 .type = SWITCH_TYPE_INT,
1962 .name = "ar8xxx_mib_type",
1963 .description = "MIB type (0=basic 1=extended)",
1964 .set = ar8xxx_sw_set_mib_type,
1965 .get = ar8xxx_sw_get_mib_type
1966 },
1967 {
1968 .type = SWITCH_TYPE_INT,
1969 .name = "enable_mirror_rx",
1970 .description = "Enable mirroring of RX packets",
1971 .set = ar8xxx_sw_set_mirror_rx_enable,
1972 .get = ar8xxx_sw_get_mirror_rx_enable,
1973 .max = 1
1974 },
1975 {
1976 .type = SWITCH_TYPE_INT,
1977 .name = "enable_mirror_tx",
1978 .description = "Enable mirroring of TX packets",
1979 .set = ar8xxx_sw_set_mirror_tx_enable,
1980 .get = ar8xxx_sw_get_mirror_tx_enable,
1981 .max = 1
1982 },
1983 {
1984 .type = SWITCH_TYPE_INT,
1985 .name = "mirror_monitor_port",
1986 .description = "Mirror monitor port",
1987 .set = ar8xxx_sw_set_mirror_monitor_port,
1988 .get = ar8xxx_sw_get_mirror_monitor_port,
1989 .max = AR8216_NUM_PORTS - 1
1990 },
1991 {
1992 .type = SWITCH_TYPE_INT,
1993 .name = "mirror_source_port",
1994 .description = "Mirror source port",
1995 .set = ar8xxx_sw_set_mirror_source_port,
1996 .get = ar8xxx_sw_get_mirror_source_port,
1997 .max = AR8216_NUM_PORTS - 1
1998 },
1999 {
2000 .type = SWITCH_TYPE_STRING,
2001 .name = "arl_table",
2002 .description = "Get ARL table",
2003 .set = NULL,
2004 .get = ar8xxx_sw_get_arl_table,
2005 },
2006 {
2007 .type = SWITCH_TYPE_NOVAL,
2008 .name = "flush_arl_table",
2009 .description = "Flush ARL table",
2010 .set = ar8xxx_sw_set_flush_arl_table,
2011 },
2012 };
2013
2014 const struct switch_attr ar8xxx_sw_attr_port[] = {
2015 {
2016 .type = SWITCH_TYPE_NOVAL,
2017 .name = "reset_mib",
2018 .description = "Reset single port MIB counters",
2019 .set = ar8xxx_sw_set_port_reset_mib,
2020 },
2021 {
2022 .type = SWITCH_TYPE_STRING,
2023 .name = "mib",
2024 .description = "Get port's MIB counters",
2025 .set = NULL,
2026 .get = ar8xxx_sw_get_port_mib,
2027 },
2028 {
2029 .type = SWITCH_TYPE_NOVAL,
2030 .name = "flush_arl_table",
2031 .description = "Flush port's ARL table entries",
2032 .set = ar8xxx_sw_set_flush_port_arl_table,
2033 },
2034 };
2035
2036 const struct switch_attr ar8xxx_sw_attr_vlan[1] = {
2037 {
2038 .type = SWITCH_TYPE_INT,
2039 .name = "vid",
2040 .description = "VLAN ID (0-4094)",
2041 .set = ar8xxx_sw_set_vid,
2042 .get = ar8xxx_sw_get_vid,
2043 .max = 4094,
2044 },
2045 };
2046
2047 static const struct switch_dev_ops ar8xxx_sw_ops = {
2048 .attr_global = {
2049 .attr = ar8xxx_sw_attr_globals,
2050 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_globals),
2051 },
2052 .attr_port = {
2053 .attr = ar8xxx_sw_attr_port,
2054 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_port),
2055 },
2056 .attr_vlan = {
2057 .attr = ar8xxx_sw_attr_vlan,
2058 .n_attr = ARRAY_SIZE(ar8xxx_sw_attr_vlan),
2059 },
2060 .get_port_pvid = ar8xxx_sw_get_pvid,
2061 .set_port_pvid = ar8xxx_sw_set_pvid,
2062 .get_vlan_ports = ar8xxx_sw_get_ports,
2063 .set_vlan_ports = ar8xxx_sw_set_ports,
2064 .apply_config = ar8xxx_sw_hw_apply,
2065 .reset_switch = ar8xxx_sw_reset_switch,
2066 .get_port_link = ar8xxx_sw_get_port_link,
2067 .get_port_stats = ar8xxx_sw_get_port_stats,
2068 };
2069
2070 static const struct ar8xxx_chip ar7240sw_chip = {
2071 .caps = AR8XXX_CAP_MIB_COUNTERS,
2072
2073 .reg_port_stats_start = 0x20000,
2074 .reg_port_stats_length = 0x100,
2075 .reg_arl_ctrl = AR8216_REG_ATU_CTRL,
2076
2077 .name = "Atheros AR724X/AR933X built-in",
2078 .ports = AR7240SW_NUM_PORTS,
2079 .vlans = AR8216_NUM_VLANS,
2080 .swops = &ar8xxx_sw_ops,
2081
2082 .hw_init = ar7240sw_hw_init,
2083 .init_globals = ar7240sw_init_globals,
2084 .init_port = ar8229_init_port,
2085 .phy_read = ar8216_phy_read,
2086 .phy_write = ar8216_phy_write,
2087 .setup_port = ar7240sw_setup_port,
2088 .read_port_status = ar8216_read_port_status,
2089 .atu_flush = ar8216_atu_flush,
2090 .atu_flush_port = ar8216_atu_flush_port,
2091 .vtu_flush = ar8216_vtu_flush,
2092 .vtu_load_vlan = ar8216_vtu_load_vlan,
2093 .set_mirror_regs = ar8216_set_mirror_regs,
2094 .get_arl_entry = ar8216_get_arl_entry,
2095 .sw_hw_apply = ar8xxx_sw_hw_apply,
2096
2097 .num_mibs = ARRAY_SIZE(ar8236_mibs),
2098 .mib_decs = ar8236_mibs,
2099 .mib_func = AR8216_REG_MIB_FUNC,
2100 .mib_rxb_id = AR8236_MIB_RXB_ID,
2101 .mib_txb_id = AR8236_MIB_TXB_ID,
2102 };
2103
2104 static const struct ar8xxx_chip ar8216_chip = {
2105 .caps = AR8XXX_CAP_MIB_COUNTERS,
2106
2107 .reg_port_stats_start = 0x19000,
2108 .reg_port_stats_length = 0xa0,
2109 .reg_arl_ctrl = AR8216_REG_ATU_CTRL,
2110
2111 .name = "Atheros AR8216",
2112 .ports = AR8216_NUM_PORTS,
2113 .vlans = AR8216_NUM_VLANS,
2114 .swops = &ar8xxx_sw_ops,
2115
2116 .hw_init = ar8216_hw_init,
2117 .init_globals = ar8216_init_globals,
2118 .init_port = ar8216_init_port,
2119 .setup_port = ar8216_setup_port,
2120 .read_port_status = ar8216_read_port_status,
2121 .atu_flush = ar8216_atu_flush,
2122 .atu_flush_port = ar8216_atu_flush_port,
2123 .vtu_flush = ar8216_vtu_flush,
2124 .vtu_load_vlan = ar8216_vtu_load_vlan,
2125 .set_mirror_regs = ar8216_set_mirror_regs,
2126 .get_arl_entry = ar8216_get_arl_entry,
2127 .sw_hw_apply = ar8xxx_sw_hw_apply,
2128
2129 .num_mibs = ARRAY_SIZE(ar8216_mibs),
2130 .mib_decs = ar8216_mibs,
2131 .mib_func = AR8216_REG_MIB_FUNC,
2132 .mib_rxb_id = AR8216_MIB_RXB_ID,
2133 .mib_txb_id = AR8216_MIB_TXB_ID,
2134 };
2135
2136 static const struct ar8xxx_chip ar8229_chip = {
2137 .caps = AR8XXX_CAP_MIB_COUNTERS,
2138
2139 .reg_port_stats_start = 0x20000,
2140 .reg_port_stats_length = 0x100,
2141 .reg_arl_ctrl = AR8216_REG_ATU_CTRL,
2142
2143 .name = "Atheros AR8229",
2144 .ports = AR8216_NUM_PORTS,
2145 .vlans = AR8216_NUM_VLANS,
2146 .swops = &ar8xxx_sw_ops,
2147
2148 .hw_init = ar8229_hw_init,
2149 .init_globals = ar8229_init_globals,
2150 .init_port = ar8229_init_port,
2151 .phy_read = ar8216_phy_read,
2152 .phy_write = ar8216_phy_write,
2153 .setup_port = ar8236_setup_port,
2154 .read_port_status = ar8216_read_port_status,
2155 .atu_flush = ar8216_atu_flush,
2156 .atu_flush_port = ar8216_atu_flush_port,
2157 .vtu_flush = ar8216_vtu_flush,
2158 .vtu_load_vlan = ar8216_vtu_load_vlan,
2159 .set_mirror_regs = ar8216_set_mirror_regs,
2160 .get_arl_entry = ar8216_get_arl_entry,
2161 .sw_hw_apply = ar8xxx_sw_hw_apply,
2162
2163 .num_mibs = ARRAY_SIZE(ar8236_mibs),
2164 .mib_decs = ar8236_mibs,
2165 .mib_func = AR8216_REG_MIB_FUNC,
2166 .mib_rxb_id = AR8236_MIB_RXB_ID,
2167 .mib_txb_id = AR8236_MIB_TXB_ID,
2168 };
2169
2170 static const struct ar8xxx_chip ar8236_chip = {
2171 .caps = AR8XXX_CAP_MIB_COUNTERS,
2172
2173 .reg_port_stats_start = 0x20000,
2174 .reg_port_stats_length = 0x100,
2175 .reg_arl_ctrl = AR8216_REG_ATU_CTRL,
2176
2177 .name = "Atheros AR8236",
2178 .ports = AR8216_NUM_PORTS,
2179 .vlans = AR8216_NUM_VLANS,
2180 .swops = &ar8xxx_sw_ops,
2181
2182 .hw_init = ar8216_hw_init,
2183 .init_globals = ar8236_init_globals,
2184 .init_port = ar8216_init_port,
2185 .setup_port = ar8236_setup_port,
2186 .read_port_status = ar8216_read_port_status,
2187 .atu_flush = ar8216_atu_flush,
2188 .atu_flush_port = ar8216_atu_flush_port,
2189 .vtu_flush = ar8216_vtu_flush,
2190 .vtu_load_vlan = ar8216_vtu_load_vlan,
2191 .set_mirror_regs = ar8216_set_mirror_regs,
2192 .get_arl_entry = ar8216_get_arl_entry,
2193 .sw_hw_apply = ar8xxx_sw_hw_apply,
2194
2195 .num_mibs = ARRAY_SIZE(ar8236_mibs),
2196 .mib_decs = ar8236_mibs,
2197 .mib_func = AR8216_REG_MIB_FUNC,
2198 .mib_rxb_id = AR8236_MIB_RXB_ID,
2199 .mib_txb_id = AR8236_MIB_TXB_ID,
2200 };
2201
2202 static const struct ar8xxx_chip ar8316_chip = {
2203 .caps = AR8XXX_CAP_GIGE | AR8XXX_CAP_MIB_COUNTERS,
2204
2205 .reg_port_stats_start = 0x20000,
2206 .reg_port_stats_length = 0x100,
2207 .reg_arl_ctrl = AR8216_REG_ATU_CTRL,
2208
2209 .name = "Atheros AR8316",
2210 .ports = AR8216_NUM_PORTS,
2211 .vlans = AR8X16_MAX_VLANS,
2212 .swops = &ar8xxx_sw_ops,
2213
2214 .hw_init = ar8316_hw_init,
2215 .init_globals = ar8316_init_globals,
2216 .init_port = ar8216_init_port,
2217 .setup_port = ar8216_setup_port,
2218 .read_port_status = ar8216_read_port_status,
2219 .atu_flush = ar8216_atu_flush,
2220 .atu_flush_port = ar8216_atu_flush_port,
2221 .vtu_flush = ar8216_vtu_flush,
2222 .vtu_load_vlan = ar8216_vtu_load_vlan,
2223 .set_mirror_regs = ar8216_set_mirror_regs,
2224 .get_arl_entry = ar8216_get_arl_entry,
2225 .sw_hw_apply = ar8xxx_sw_hw_apply,
2226
2227 .num_mibs = ARRAY_SIZE(ar8236_mibs),
2228 .mib_decs = ar8236_mibs,
2229 .mib_func = AR8216_REG_MIB_FUNC,
2230 .mib_rxb_id = AR8236_MIB_RXB_ID,
2231 .mib_txb_id = AR8236_MIB_TXB_ID,
2232 };
2233
2234 static int
2235 ar8xxx_read_id(struct ar8xxx_priv *priv)
2236 {
2237 u32 val;
2238 u16 id;
2239 int i;
2240
2241 val = ar8xxx_read(priv, AR8216_REG_CTRL);
2242 if (val == ~0)
2243 return -ENODEV;
2244
2245 id = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
2246 for (i = 0; i < AR8X16_PROBE_RETRIES; i++) {
2247 u16 t;
2248
2249 val = ar8xxx_read(priv, AR8216_REG_CTRL);
2250 if (val == ~0)
2251 return -ENODEV;
2252
2253 t = val & (AR8216_CTRL_REVISION | AR8216_CTRL_VERSION);
2254 if (t != id)
2255 return -ENODEV;
2256 }
2257
2258 priv->chip_ver = (id & AR8216_CTRL_VERSION) >> AR8216_CTRL_VERSION_S;
2259 priv->chip_rev = (id & AR8216_CTRL_REVISION);
2260 return 0;
2261 }
2262
2263 static int
2264 ar8xxx_id_chip(struct ar8xxx_priv *priv)
2265 {
2266 int ret;
2267
2268 ret = ar8xxx_read_id(priv);
2269 if(ret)
2270 return ret;
2271
2272 switch (priv->chip_ver) {
2273 case AR8XXX_VER_AR8216:
2274 priv->chip = &ar8216_chip;
2275 break;
2276 case AR8XXX_VER_AR8236:
2277 priv->chip = &ar8236_chip;
2278 break;
2279 case AR8XXX_VER_AR8316:
2280 priv->chip = &ar8316_chip;
2281 break;
2282 case AR8XXX_VER_AR8327:
2283 priv->chip = &ar8327_chip;
2284 break;
2285 case AR8XXX_VER_AR8337:
2286 priv->chip = &ar8337_chip;
2287 break;
2288 default:
2289 pr_err("ar8216: Unknown Atheros device [ver=%d, rev=%d]\n",
2290 priv->chip_ver, priv->chip_rev);
2291
2292 return -ENODEV;
2293 }
2294
2295 return 0;
2296 }
2297
2298 static void
2299 ar8xxx_mib_work_func(struct work_struct *work)
2300 {
2301 struct ar8xxx_priv *priv;
2302 int err, i;
2303
2304 priv = container_of(work, struct ar8xxx_priv, mib_work.work);
2305
2306 mutex_lock(&priv->mib_lock);
2307
2308 err = ar8xxx_mib_capture(priv);
2309 if (err)
2310 goto next_attempt;
2311
2312 for (i = 0; i < priv->dev.ports; i++)
2313 ar8xxx_mib_fetch_port_stat(priv, i, false);
2314
2315 next_attempt:
2316 mutex_unlock(&priv->mib_lock);
2317 schedule_delayed_work(&priv->mib_work,
2318 msecs_to_jiffies(priv->mib_poll_interval));
2319 }
2320
2321 static int
2322 ar8xxx_mib_init(struct ar8xxx_priv *priv)
2323 {
2324 unsigned int len;
2325
2326 if (!ar8xxx_has_mib_counters(priv))
2327 return 0;
2328
2329 BUG_ON(!priv->chip->mib_decs || !priv->chip->num_mibs);
2330
2331 len = priv->dev.ports * priv->chip->num_mibs *
2332 sizeof(*priv->mib_stats);
2333 priv->mib_stats = kzalloc(len, GFP_KERNEL);
2334
2335 if (!priv->mib_stats)
2336 return -ENOMEM;
2337
2338 return 0;
2339 }
2340
2341 static void
2342 ar8xxx_mib_start(struct ar8xxx_priv *priv)
2343 {
2344 if (!ar8xxx_has_mib_counters(priv) || !priv->mib_poll_interval)
2345 return;
2346
2347 schedule_delayed_work(&priv->mib_work,
2348 msecs_to_jiffies(priv->mib_poll_interval));
2349 }
2350
2351 static void
2352 ar8xxx_mib_stop(struct ar8xxx_priv *priv)
2353 {
2354 if (!ar8xxx_has_mib_counters(priv) || !priv->mib_poll_interval)
2355 return;
2356
2357 cancel_delayed_work_sync(&priv->mib_work);
2358 }
2359
2360 static struct ar8xxx_priv *
2361 ar8xxx_create(void)
2362 {
2363 struct ar8xxx_priv *priv;
2364
2365 priv = kzalloc(sizeof(struct ar8xxx_priv), GFP_KERNEL);
2366 if (priv == NULL)
2367 return NULL;
2368
2369 mutex_init(&priv->reg_mutex);
2370 mutex_init(&priv->mib_lock);
2371 INIT_DELAYED_WORK(&priv->mib_work, ar8xxx_mib_work_func);
2372
2373 return priv;
2374 }
2375
2376 static void
2377 ar8xxx_free(struct ar8xxx_priv *priv)
2378 {
2379 if (priv->chip && priv->chip->cleanup)
2380 priv->chip->cleanup(priv);
2381
2382 kfree(priv->chip_data);
2383 kfree(priv->mib_stats);
2384 kfree(priv);
2385 }
2386
2387 static int
2388 ar8xxx_probe_switch(struct ar8xxx_priv *priv)
2389 {
2390 const struct ar8xxx_chip *chip;
2391 struct switch_dev *swdev;
2392 int ret;
2393
2394 chip = priv->chip;
2395
2396 swdev = &priv->dev;
2397 swdev->cpu_port = AR8216_PORT_CPU;
2398 swdev->name = chip->name;
2399 swdev->vlans = chip->vlans;
2400 swdev->ports = chip->ports;
2401 swdev->ops = chip->swops;
2402
2403 ret = ar8xxx_mib_init(priv);
2404 if (ret)
2405 return ret;
2406
2407 return 0;
2408 }
2409
2410 static int
2411 ar8xxx_start(struct ar8xxx_priv *priv)
2412 {
2413 int ret;
2414
2415 priv->init = true;
2416
2417 ret = priv->chip->hw_init(priv);
2418 if (ret)
2419 return ret;
2420
2421 ret = ar8xxx_sw_reset_switch(&priv->dev);
2422 if (ret)
2423 return ret;
2424
2425 priv->init = false;
2426
2427 ar8xxx_mib_start(priv);
2428
2429 return 0;
2430 }
2431
2432 static int
2433 ar8xxx_phy_config_init(struct phy_device *phydev)
2434 {
2435 struct ar8xxx_priv *priv = phydev->priv;
2436 #ifdef CONFIG_ETHERNET_PACKET_MANGLE
2437 struct net_device *dev = phydev->attached_dev;
2438 #endif
2439 int ret;
2440
2441 if (WARN_ON(!priv))
2442 return -ENODEV;
2443
2444 if (priv->chip->config_at_probe)
2445 return ar8xxx_phy_check_aneg(phydev);
2446
2447 priv->phy = phydev;
2448
2449 if (phydev->mdio.addr != 0) {
2450 if (chip_is_ar8316(priv)) {
2451 /* switch device has been initialized, reinit */
2452 priv->dev.ports = (AR8216_NUM_PORTS - 1);
2453 priv->initialized = false;
2454 priv->port4_phy = true;
2455 ar8316_hw_init(priv);
2456 return 0;
2457 }
2458
2459 return 0;
2460 }
2461
2462 ret = ar8xxx_start(priv);
2463 if (ret)
2464 return ret;
2465
2466 #ifdef CONFIG_ETHERNET_PACKET_MANGLE
2467 /* VID fixup only needed on ar8216 */
2468 if (chip_is_ar8216(priv)) {
2469 dev->phy_ptr = priv;
2470 #if LINUX_VERSION_CODE >= KERNEL_VERSION(5,15,0)
2471 dev->extra_priv_flags |= IFF_NO_IP_ALIGN;
2472 #else
2473 dev->priv_flags |= IFF_NO_IP_ALIGN;
2474 #endif
2475 dev->eth_mangle_rx = ar8216_mangle_rx;
2476 dev->eth_mangle_tx = ar8216_mangle_tx;
2477 }
2478 #endif
2479
2480 return 0;
2481 }
2482
2483 static bool
2484 ar8xxx_check_link_states(struct ar8xxx_priv *priv)
2485 {
2486 bool link_new, changed = false;
2487 u32 status;
2488 int i;
2489
2490 mutex_lock(&priv->reg_mutex);
2491
2492 for (i = 0; i < priv->dev.ports; i++) {
2493 status = priv->chip->read_port_status(priv, i);
2494 link_new = !!(status & AR8216_PORT_STATUS_LINK_UP);
2495 if (link_new == priv->link_up[i])
2496 continue;
2497
2498 priv->link_up[i] = link_new;
2499 changed = true;
2500 /* flush ARL entries for this port if it went down*/
2501 if (!link_new)
2502 priv->chip->atu_flush_port(priv, i);
2503 dev_info(&priv->phy->mdio.dev, "Port %d is %s\n",
2504 i, link_new ? "up" : "down");
2505 }
2506
2507 mutex_unlock(&priv->reg_mutex);
2508
2509 return changed;
2510 }
2511
2512 static int
2513 ar8xxx_phy_read_status(struct phy_device *phydev)
2514 {
2515 struct ar8xxx_priv *priv = phydev->priv;
2516 struct switch_port_link link;
2517
2518 /* check for switch port link changes */
2519 ar8xxx_check_link_states(priv);
2520
2521 if (phydev->mdio.addr != 0)
2522 return genphy_read_status(phydev);
2523
2524 ar8216_read_port_link(priv, phydev->mdio.addr, &link);
2525 phydev->link = !!link.link;
2526 if (!phydev->link)
2527 return 0;
2528
2529 switch (link.speed) {
2530 case SWITCH_PORT_SPEED_10:
2531 phydev->speed = SPEED_10;
2532 break;
2533 case SWITCH_PORT_SPEED_100:
2534 phydev->speed = SPEED_100;
2535 break;
2536 case SWITCH_PORT_SPEED_1000:
2537 phydev->speed = SPEED_1000;
2538 break;
2539 default:
2540 phydev->speed = 0;
2541 }
2542 phydev->duplex = link.duplex ? DUPLEX_FULL : DUPLEX_HALF;
2543
2544 phydev->state = PHY_RUNNING;
2545 netif_carrier_on(phydev->attached_dev);
2546 if (phydev->adjust_link)
2547 phydev->adjust_link(phydev->attached_dev);
2548
2549 return 0;
2550 }
2551
2552 static int
2553 ar8xxx_phy_config_aneg(struct phy_device *phydev)
2554 {
2555 if (phydev->mdio.addr == 0)
2556 return 0;
2557
2558 return genphy_config_aneg(phydev);
2559 }
2560
2561 static int
2562 ar8xxx_get_features(struct phy_device *phydev)
2563 {
2564 struct ar8xxx_priv *priv = phydev->priv;
2565
2566 linkmode_copy(phydev->supported, PHY_BASIC_FEATURES);
2567 if (ar8xxx_has_gige(priv))
2568 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, phydev->supported);
2569
2570 return 0;
2571 }
2572
2573 static const u32 ar8xxx_phy_ids[] = {
2574 0x004dd033,
2575 0x004dd034, /* AR8327 */
2576 0x004dd036, /* AR8337 */
2577 0x004dd041,
2578 0x004dd042,
2579 0x004dd043, /* AR8236 */
2580 };
2581
2582 static bool
2583 ar8xxx_phy_match(u32 phy_id)
2584 {
2585 int i;
2586
2587 for (i = 0; i < ARRAY_SIZE(ar8xxx_phy_ids); i++)
2588 if (phy_id == ar8xxx_phy_ids[i])
2589 return true;
2590
2591 return false;
2592 }
2593
2594 static bool
2595 ar8xxx_is_possible(struct mii_bus *bus)
2596 {
2597 unsigned int i, found_phys = 0;
2598
2599 for (i = 0; i < 5; i++) {
2600 u32 phy_id;
2601
2602 phy_id = mdiobus_read(bus, i, MII_PHYSID1) << 16;
2603 phy_id |= mdiobus_read(bus, i, MII_PHYSID2);
2604 if (ar8xxx_phy_match(phy_id)) {
2605 found_phys++;
2606 } else if (phy_id) {
2607 pr_debug("ar8xxx: unknown PHY at %s:%02x id:%08x\n",
2608 dev_name(&bus->dev), i, phy_id);
2609 }
2610 }
2611 return !!found_phys;
2612 }
2613
2614 static int
2615 ar8xxx_phy_probe(struct phy_device *phydev)
2616 {
2617 struct ar8xxx_priv *priv;
2618 struct switch_dev *swdev;
2619 int ret;
2620
2621 /* skip PHYs at unused adresses */
2622 if (phydev->mdio.addr != 0 && phydev->mdio.addr != 3 && phydev->mdio.addr != 4)
2623 return -ENODEV;
2624
2625 if (!ar8xxx_is_possible(phydev->mdio.bus))
2626 return -ENODEV;
2627
2628 mutex_lock(&ar8xxx_dev_list_lock);
2629 list_for_each_entry(priv, &ar8xxx_dev_list, list)
2630 if (priv->mii_bus == phydev->mdio.bus)
2631 goto found;
2632
2633 priv = ar8xxx_create();
2634 if (priv == NULL) {
2635 ret = -ENOMEM;
2636 goto unlock;
2637 }
2638
2639 priv->mii_bus = phydev->mdio.bus;
2640 priv->pdev = &phydev->mdio.dev;
2641
2642 ret = of_property_read_u32(priv->pdev->of_node, "qca,mib-poll-interval",
2643 &priv->mib_poll_interval);
2644 if (ret)
2645 priv->mib_poll_interval = 0;
2646
2647 ret = ar8xxx_id_chip(priv);
2648 if (ret)
2649 goto free_priv;
2650
2651 ret = ar8xxx_probe_switch(priv);
2652 if (ret)
2653 goto free_priv;
2654
2655 swdev = &priv->dev;
2656 swdev->alias = dev_name(&priv->mii_bus->dev);
2657 ret = register_switch(swdev, NULL);
2658 if (ret)
2659 goto free_priv;
2660
2661 pr_info("%s: %s rev. %u switch registered on %s\n",
2662 swdev->devname, swdev->name, priv->chip_rev,
2663 dev_name(&priv->mii_bus->dev));
2664
2665 list_add(&priv->list, &ar8xxx_dev_list);
2666
2667 found:
2668 priv->use_count++;
2669
2670 if (phydev->mdio.addr == 0 && priv->chip->config_at_probe) {
2671 priv->phy = phydev;
2672
2673 ret = ar8xxx_start(priv);
2674 if (ret)
2675 goto err_unregister_switch;
2676 } else if (priv->chip->phy_rgmii_set) {
2677 priv->chip->phy_rgmii_set(priv, phydev);
2678 }
2679
2680 phydev->priv = priv;
2681
2682 mutex_unlock(&ar8xxx_dev_list_lock);
2683
2684 return 0;
2685
2686 err_unregister_switch:
2687 if (--priv->use_count)
2688 goto unlock;
2689
2690 unregister_switch(&priv->dev);
2691
2692 free_priv:
2693 ar8xxx_free(priv);
2694 unlock:
2695 mutex_unlock(&ar8xxx_dev_list_lock);
2696 return ret;
2697 }
2698
2699 static void
2700 ar8xxx_phy_detach(struct phy_device *phydev)
2701 {
2702 struct net_device *dev = phydev->attached_dev;
2703
2704 if (!dev)
2705 return;
2706
2707 #ifdef CONFIG_ETHERNET_PACKET_MANGLE
2708 dev->phy_ptr = NULL;
2709 #if LINUX_VERSION_CODE >= KERNEL_VERSION(5,15,0)
2710 dev->extra_priv_flags &= ~IFF_NO_IP_ALIGN;
2711 #else
2712 dev->priv_flags &= ~IFF_NO_IP_ALIGN;
2713 #endif
2714 dev->eth_mangle_rx = NULL;
2715 dev->eth_mangle_tx = NULL;
2716 #endif
2717 }
2718
2719 static void
2720 ar8xxx_phy_remove(struct phy_device *phydev)
2721 {
2722 struct ar8xxx_priv *priv = phydev->priv;
2723
2724 if (WARN_ON(!priv))
2725 return;
2726
2727 phydev->priv = NULL;
2728
2729 mutex_lock(&ar8xxx_dev_list_lock);
2730
2731 if (--priv->use_count > 0) {
2732 mutex_unlock(&ar8xxx_dev_list_lock);
2733 return;
2734 }
2735
2736 list_del(&priv->list);
2737 mutex_unlock(&ar8xxx_dev_list_lock);
2738
2739 unregister_switch(&priv->dev);
2740 ar8xxx_mib_stop(priv);
2741 ar8xxx_free(priv);
2742 }
2743
2744 static struct phy_driver ar8xxx_phy_driver[] = {
2745 {
2746 .phy_id = 0x004d0000,
2747 .name = "Atheros AR8216/AR8236/AR8316",
2748 .phy_id_mask = 0xffff0000,
2749 .probe = ar8xxx_phy_probe,
2750 .remove = ar8xxx_phy_remove,
2751 .detach = ar8xxx_phy_detach,
2752 .config_init = ar8xxx_phy_config_init,
2753 .config_aneg = ar8xxx_phy_config_aneg,
2754 .read_status = ar8xxx_phy_read_status,
2755 .get_features = ar8xxx_get_features,
2756 }
2757 };
2758
2759 static const struct of_device_id ar8xxx_mdiodev_of_match[] = {
2760 {
2761 .compatible = "qca,ar7240sw",
2762 .data = &ar7240sw_chip,
2763 }, {
2764 .compatible = "qca,ar8229",
2765 .data = &ar8229_chip,
2766 }, {
2767 .compatible = "qca,ar8236",
2768 .data = &ar8236_chip,
2769 }, {
2770 .compatible = "qca,ar8327",
2771 .data = &ar8327_chip,
2772 },
2773 { /* sentinel */ },
2774 };
2775
2776 static int
2777 ar8xxx_mdiodev_probe(struct mdio_device *mdiodev)
2778 {
2779 const struct of_device_id *match;
2780 struct ar8xxx_priv *priv;
2781 struct switch_dev *swdev;
2782 struct device_node *mdio_node;
2783 int ret;
2784
2785 match = of_match_device(ar8xxx_mdiodev_of_match, &mdiodev->dev);
2786 if (!match)
2787 return -EINVAL;
2788
2789 priv = ar8xxx_create();
2790 if (priv == NULL)
2791 return -ENOMEM;
2792
2793 priv->mii_bus = mdiodev->bus;
2794 priv->pdev = &mdiodev->dev;
2795 priv->chip = (const struct ar8xxx_chip *) match->data;
2796
2797 ret = of_property_read_u32(priv->pdev->of_node, "qca,mib-poll-interval",
2798 &priv->mib_poll_interval);
2799 if (ret)
2800 priv->mib_poll_interval = 0;
2801
2802 ret = ar8xxx_read_id(priv);
2803 if (ret)
2804 goto free_priv;
2805
2806 ret = ar8xxx_probe_switch(priv);
2807 if (ret)
2808 goto free_priv;
2809
2810 if (priv->chip->phy_read && priv->chip->phy_write) {
2811 priv->sw_mii_bus = devm_mdiobus_alloc(&mdiodev->dev);
2812 priv->sw_mii_bus->name = "ar8xxx-mdio";
2813 priv->sw_mii_bus->read = ar8xxx_phy_read;
2814 priv->sw_mii_bus->write = ar8xxx_phy_write;
2815 priv->sw_mii_bus->priv = priv;
2816 priv->sw_mii_bus->parent = &mdiodev->dev;
2817 snprintf(priv->sw_mii_bus->id, MII_BUS_ID_SIZE, "%s",
2818 dev_name(&mdiodev->dev));
2819 mdio_node = of_get_child_by_name(priv->pdev->of_node, "mdio-bus");
2820 ret = of_mdiobus_register(priv->sw_mii_bus, mdio_node);
2821 if (ret)
2822 goto free_priv;
2823 }
2824
2825 swdev = &priv->dev;
2826 swdev->alias = dev_name(&mdiodev->dev);
2827
2828 if (of_property_read_bool(priv->pdev->of_node, "qca,phy4-mii-enable")) {
2829 priv->port4_phy = true;
2830 swdev->ports--;
2831 }
2832
2833 ret = register_switch(swdev, NULL);
2834 if (ret)
2835 goto free_priv;
2836
2837 pr_info("%s: %s rev. %u switch registered on %s\n",
2838 swdev->devname, swdev->name, priv->chip_rev,
2839 dev_name(&priv->mii_bus->dev));
2840
2841 mutex_lock(&ar8xxx_dev_list_lock);
2842 list_add(&priv->list, &ar8xxx_dev_list);
2843 mutex_unlock(&ar8xxx_dev_list_lock);
2844
2845 priv->use_count++;
2846
2847 ret = ar8xxx_start(priv);
2848 if (ret)
2849 goto err_unregister_switch;
2850
2851 dev_set_drvdata(&mdiodev->dev, priv);
2852
2853 return 0;
2854
2855 err_unregister_switch:
2856 if (--priv->use_count)
2857 return ret;
2858
2859 unregister_switch(&priv->dev);
2860
2861 free_priv:
2862 ar8xxx_free(priv);
2863 return ret;
2864 }
2865
2866 static void
2867 ar8xxx_mdiodev_remove(struct mdio_device *mdiodev)
2868 {
2869 struct ar8xxx_priv *priv = dev_get_drvdata(&mdiodev->dev);
2870
2871 if (WARN_ON(!priv))
2872 return;
2873
2874 mutex_lock(&ar8xxx_dev_list_lock);
2875
2876 if (--priv->use_count > 0) {
2877 mutex_unlock(&ar8xxx_dev_list_lock);
2878 return;
2879 }
2880
2881 list_del(&priv->list);
2882 mutex_unlock(&ar8xxx_dev_list_lock);
2883
2884 unregister_switch(&priv->dev);
2885 ar8xxx_mib_stop(priv);
2886 if(priv->sw_mii_bus)
2887 mdiobus_unregister(priv->sw_mii_bus);
2888 ar8xxx_free(priv);
2889 }
2890
2891 static struct mdio_driver ar8xxx_mdio_driver = {
2892 .probe = ar8xxx_mdiodev_probe,
2893 .remove = ar8xxx_mdiodev_remove,
2894 .mdiodrv.driver = {
2895 .name = "ar8xxx-switch",
2896 .of_match_table = ar8xxx_mdiodev_of_match,
2897 },
2898 };
2899
2900 static int __init ar8216_init(void)
2901 {
2902 int ret;
2903
2904 ret = phy_drivers_register(ar8xxx_phy_driver,
2905 ARRAY_SIZE(ar8xxx_phy_driver),
2906 THIS_MODULE);
2907 if (ret)
2908 return ret;
2909
2910 ret = mdio_driver_register(&ar8xxx_mdio_driver);
2911 if (ret)
2912 phy_drivers_unregister(ar8xxx_phy_driver,
2913 ARRAY_SIZE(ar8xxx_phy_driver));
2914
2915 return ret;
2916 }
2917 module_init(ar8216_init);
2918
2919 static void __exit ar8216_exit(void)
2920 {
2921 mdio_driver_unregister(&ar8xxx_mdio_driver);
2922 phy_drivers_unregister(ar8xxx_phy_driver,
2923 ARRAY_SIZE(ar8xxx_phy_driver));
2924 }
2925 module_exit(ar8216_exit);
2926
2927 MODULE_LICENSE("GPL");
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