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253ebff835a6e092ee2b58bc862fbd8f1ced1caa
[openwrt/staging/chunkeey.git] / target / linux / generic / files / drivers / net / phy / mvsw61xx.c
1 /*
2 * Marvell 88E61xx switch driver
3 *
4 * Copyright (c) 2014 Claudio Leite <leitec@staticky.com>
5 * Copyright (c) 2014 Nikita Nazarenko <nnazarenko@radiofid.com>
6 *
7 * Based on code (c) 2008 Felix Fietkau <nbd@nbd.name>
8 *
9 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License v2 as published by the
11 * Free Software Foundation
12 */
13
14 #include <linux/kernel.h>
15 #include <linux/module.h>
16 #include <linux/init.h>
17 #include <linux/list.h>
18 #include <linux/mii.h>
19 #include <linux/phy.h>
20 #include <linux/of.h>
21 #include <linux/of_mdio.h>
22 #include <linux/delay.h>
23 #include <linux/switch.h>
24 #include <linux/device.h>
25 #include <linux/platform_device.h>
26
27 #include "mvsw61xx.h"
28
29 MODULE_DESCRIPTION("Marvell 88E61xx Switch driver");
30 MODULE_AUTHOR("Claudio Leite <leitec@staticky.com>");
31 MODULE_AUTHOR("Nikita Nazarenko <nnazarenko@radiofid.com>");
32 MODULE_LICENSE("GPL v2");
33 MODULE_ALIAS("platform:mvsw61xx");
34
35 /*
36 * Register access is done through direct or indirect addressing,
37 * depending on how the switch is physically connected.
38 *
39 * Direct addressing: all port and global registers directly
40 * accessible via an address/register pair
41 *
42 * Indirect addressing: switch is mapped at a single address,
43 * port and global registers accessible via a single command/data
44 * register pair
45 */
46
47 static int
48 mvsw61xx_wait_mask_raw(struct mii_bus *bus, int addr,
49 int reg, u16 mask, u16 val)
50 {
51 int i = 100;
52 u16 r;
53
54 do {
55 r = bus->read(bus, addr, reg);
56 if ((r & mask) == val)
57 return 0;
58 } while (--i > 0);
59
60 return -ETIMEDOUT;
61 }
62
63 static u16
64 r16(struct mii_bus *bus, bool indirect, int base_addr, int addr, int reg)
65 {
66 u16 ind_addr;
67
68 if (!indirect)
69 return bus->read(bus, addr, reg);
70
71 /* Indirect read: First, make sure switch is free */
72 mvsw61xx_wait_mask_raw(bus, base_addr, MV_INDIRECT_REG_CMD,
73 MV_INDIRECT_INPROGRESS, 0);
74
75 /* Load address and request read */
76 ind_addr = MV_INDIRECT_READ | (addr << MV_INDIRECT_ADDR_S) | reg;
77 bus->write(bus, base_addr, MV_INDIRECT_REG_CMD,
78 ind_addr);
79
80 /* Wait until it's ready */
81 mvsw61xx_wait_mask_raw(bus, base_addr, MV_INDIRECT_REG_CMD,
82 MV_INDIRECT_INPROGRESS, 0);
83
84 /* Read the requested data */
85 return bus->read(bus, base_addr, MV_INDIRECT_REG_DATA);
86 }
87
88 static void
89 w16(struct mii_bus *bus, bool indirect, int base_addr, int addr,
90 int reg, u16 val)
91 {
92 u16 ind_addr;
93
94 if (!indirect) {
95 bus->write(bus, addr, reg, val);
96 return;
97 }
98
99 /* Indirect write: First, make sure switch is free */
100 mvsw61xx_wait_mask_raw(bus, base_addr, MV_INDIRECT_REG_CMD,
101 MV_INDIRECT_INPROGRESS, 0);
102
103 /* Load the data to be written */
104 bus->write(bus, base_addr, MV_INDIRECT_REG_DATA, val);
105
106 /* Wait again for switch to be free */
107 mvsw61xx_wait_mask_raw(bus, base_addr, MV_INDIRECT_REG_CMD,
108 MV_INDIRECT_INPROGRESS, 0);
109
110 /* Load address, and issue write command */
111 ind_addr = MV_INDIRECT_WRITE | (addr << MV_INDIRECT_ADDR_S) | reg;
112 bus->write(bus, base_addr, MV_INDIRECT_REG_CMD,
113 ind_addr);
114 }
115
116 /* swconfig support */
117
118 static inline u16
119 sr16(struct switch_dev *dev, int addr, int reg)
120 {
121 struct mvsw61xx_state *state = get_state(dev);
122
123 return r16(state->bus, state->is_indirect, state->base_addr, addr, reg);
124 }
125
126 static inline void
127 sw16(struct switch_dev *dev, int addr, int reg, u16 val)
128 {
129 struct mvsw61xx_state *state = get_state(dev);
130
131 w16(state->bus, state->is_indirect, state->base_addr, addr, reg, val);
132 }
133
134 static int
135 mvsw61xx_wait_mask_s(struct switch_dev *dev, int addr,
136 int reg, u16 mask, u16 val)
137 {
138 int i = 100;
139 u16 r;
140
141 do {
142 r = sr16(dev, addr, reg) & mask;
143 if (r == val)
144 return 0;
145 } while (--i > 0);
146
147 return -ETIMEDOUT;
148 }
149
150 static int
151 mvsw61xx_mdio_read(struct switch_dev *dev, int addr, int reg)
152 {
153 sw16(dev, MV_GLOBAL2REG(SMI_OP),
154 MV_INDIRECT_READ | (addr << MV_INDIRECT_ADDR_S) | reg);
155
156 if (mvsw61xx_wait_mask_s(dev, MV_GLOBAL2REG(SMI_OP),
157 MV_INDIRECT_INPROGRESS, 0) < 0)
158 return -ETIMEDOUT;
159
160 return sr16(dev, MV_GLOBAL2REG(SMI_DATA));
161 }
162
163 static int
164 mvsw61xx_mdio_write(struct switch_dev *dev, int addr, int reg, u16 val)
165 {
166 sw16(dev, MV_GLOBAL2REG(SMI_DATA), val);
167
168 sw16(dev, MV_GLOBAL2REG(SMI_OP),
169 MV_INDIRECT_WRITE | (addr << MV_INDIRECT_ADDR_S) | reg);
170
171 return mvsw61xx_wait_mask_s(dev, MV_GLOBAL2REG(SMI_OP),
172 MV_INDIRECT_INPROGRESS, 0) < 0;
173 }
174
175 static int
176 mvsw61xx_mdio_page_read(struct switch_dev *dev, int port, int page, int reg)
177 {
178 int ret;
179
180 mvsw61xx_mdio_write(dev, port, MII_MV_PAGE, page);
181 ret = mvsw61xx_mdio_read(dev, port, reg);
182 mvsw61xx_mdio_write(dev, port, MII_MV_PAGE, 0);
183
184 return ret;
185 }
186
187 static void
188 mvsw61xx_mdio_page_write(struct switch_dev *dev, int port, int page, int reg,
189 u16 val)
190 {
191 mvsw61xx_mdio_write(dev, port, MII_MV_PAGE, page);
192 mvsw61xx_mdio_write(dev, port, reg, val);
193 mvsw61xx_mdio_write(dev, port, MII_MV_PAGE, 0);
194 }
195
196 static int
197 mvsw61xx_get_port_mask(struct switch_dev *dev,
198 const struct switch_attr *attr, struct switch_val *val)
199 {
200 struct mvsw61xx_state *state = get_state(dev);
201 char *buf = state->buf;
202 int port, len, i;
203 u16 reg;
204
205 port = val->port_vlan;
206 reg = sr16(dev, MV_PORTREG(VLANMAP, port)) & MV_PORTS_MASK;
207
208 len = sprintf(buf, "0x%04x: ", reg);
209
210 for (i = 0; i < MV_PORTS; i++) {
211 if (reg & (1 << i))
212 len += sprintf(buf + len, "%d ", i);
213 else if (i == port)
214 len += sprintf(buf + len, "(%d) ", i);
215 }
216
217 val->value.s = buf;
218
219 return 0;
220 }
221
222 static int
223 mvsw61xx_get_port_qmode(struct switch_dev *dev,
224 const struct switch_attr *attr, struct switch_val *val)
225 {
226 struct mvsw61xx_state *state = get_state(dev);
227
228 val->value.i = state->ports[val->port_vlan].qmode;
229
230 return 0;
231 }
232
233 static int
234 mvsw61xx_set_port_qmode(struct switch_dev *dev,
235 const struct switch_attr *attr, struct switch_val *val)
236 {
237 struct mvsw61xx_state *state = get_state(dev);
238
239 state->ports[val->port_vlan].qmode = val->value.i;
240
241 return 0;
242 }
243
244 static int
245 mvsw61xx_get_port_pvid(struct switch_dev *dev, int port, int *val)
246 {
247 struct mvsw61xx_state *state = get_state(dev);
248
249 *val = state->ports[port].pvid;
250
251 return 0;
252 }
253
254 static int
255 mvsw61xx_set_port_pvid(struct switch_dev *dev, int port, int val)
256 {
257 struct mvsw61xx_state *state = get_state(dev);
258
259 if (val < 0 || val >= MV_VLANS)
260 return -EINVAL;
261
262 state->ports[port].pvid = (u16)val;
263
264 return 0;
265 }
266
267 static int
268 mvsw61xx_get_port_link(struct switch_dev *dev, int port,
269 struct switch_port_link *link)
270 {
271 u16 status, speed;
272
273 status = sr16(dev, MV_PORTREG(STATUS, port));
274
275 link->link = status & MV_PORT_STATUS_LINK;
276 if (!link->link)
277 return 0;
278
279 link->duplex = status & MV_PORT_STATUS_FDX;
280
281 speed = (status & MV_PORT_STATUS_SPEED_MASK) >>
282 MV_PORT_STATUS_SPEED_SHIFT;
283
284 switch (speed) {
285 case MV_PORT_STATUS_SPEED_10:
286 link->speed = SWITCH_PORT_SPEED_10;
287 break;
288 case MV_PORT_STATUS_SPEED_100:
289 link->speed = SWITCH_PORT_SPEED_100;
290 break;
291 case MV_PORT_STATUS_SPEED_1000:
292 link->speed = SWITCH_PORT_SPEED_1000;
293 break;
294 }
295
296 return 0;
297 }
298
299 static int mvsw61xx_get_vlan_ports(struct switch_dev *dev,
300 struct switch_val *val)
301 {
302 struct mvsw61xx_state *state = get_state(dev);
303 int i, j, mode, vno;
304
305 vno = val->port_vlan;
306
307 if (vno <= 0 || vno >= dev->vlans)
308 return -EINVAL;
309
310 for (i = 0, j = 0; i < dev->ports; i++) {
311 if (state->vlans[vno].mask & (1 << i)) {
312 val->value.ports[j].id = i;
313
314 mode = (state->vlans[vno].port_mode >> (i * 4)) & 0xf;
315 if (mode == MV_VTUCTL_EGRESS_TAGGED)
316 val->value.ports[j].flags =
317 (1 << SWITCH_PORT_FLAG_TAGGED);
318 else
319 val->value.ports[j].flags = 0;
320
321 j++;
322 }
323 }
324
325 val->len = j;
326
327 return 0;
328 }
329
330 static int mvsw61xx_set_vlan_ports(struct switch_dev *dev,
331 struct switch_val *val)
332 {
333 struct mvsw61xx_state *state = get_state(dev);
334 int i, mode, pno, vno;
335
336 vno = val->port_vlan;
337
338 if (vno <= 0 || vno >= dev->vlans)
339 return -EINVAL;
340
341 state->vlans[vno].mask = 0;
342 state->vlans[vno].port_mode = 0;
343 state->vlans[vno].port_sstate = 0;
344
345 if(state->vlans[vno].vid == 0)
346 state->vlans[vno].vid = vno;
347
348 for (i = 0; i < val->len; i++) {
349 pno = val->value.ports[i].id;
350
351 state->vlans[vno].mask |= (1 << pno);
352 if (val->value.ports[i].flags &
353 (1 << SWITCH_PORT_FLAG_TAGGED))
354 mode = MV_VTUCTL_EGRESS_TAGGED;
355 else
356 mode = MV_VTUCTL_EGRESS_UNTAGGED;
357
358 state->vlans[vno].port_mode |= mode << (pno * 4);
359 state->vlans[vno].port_sstate |=
360 MV_STUCTL_STATE_FORWARDING << (pno * 4 + 2);
361 }
362
363 /*
364 * DISCARD is nonzero, so it must be explicitly
365 * set on ports not in the VLAN.
366 */
367 for (i = 0; i < dev->ports; i++)
368 if (!(state->vlans[vno].mask & (1 << i)))
369 state->vlans[vno].port_mode |=
370 MV_VTUCTL_DISCARD << (i * 4);
371
372 return 0;
373 }
374
375 static int mvsw61xx_get_vlan_port_based(struct switch_dev *dev,
376 const struct switch_attr *attr, struct switch_val *val)
377 {
378 struct mvsw61xx_state *state = get_state(dev);
379 int vno = val->port_vlan;
380
381 if (vno <= 0 || vno >= dev->vlans)
382 return -EINVAL;
383
384 if (state->vlans[vno].port_based)
385 val->value.i = 1;
386 else
387 val->value.i = 0;
388
389 return 0;
390 }
391
392 static int mvsw61xx_set_vlan_port_based(struct switch_dev *dev,
393 const struct switch_attr *attr, struct switch_val *val)
394 {
395 struct mvsw61xx_state *state = get_state(dev);
396 int vno = val->port_vlan;
397
398 if (vno <= 0 || vno >= dev->vlans)
399 return -EINVAL;
400
401 if (val->value.i == 1)
402 state->vlans[vno].port_based = true;
403 else
404 state->vlans[vno].port_based = false;
405
406 return 0;
407 }
408
409 static int mvsw61xx_get_vid(struct switch_dev *dev,
410 const struct switch_attr *attr, struct switch_val *val)
411 {
412 struct mvsw61xx_state *state = get_state(dev);
413 int vno = val->port_vlan;
414
415 if (vno <= 0 || vno >= dev->vlans)
416 return -EINVAL;
417
418 val->value.i = state->vlans[vno].vid;
419
420 return 0;
421 }
422
423 static int mvsw61xx_set_vid(struct switch_dev *dev,
424 const struct switch_attr *attr, struct switch_val *val)
425 {
426 struct mvsw61xx_state *state = get_state(dev);
427 int vno = val->port_vlan;
428
429 if (vno <= 0 || vno >= dev->vlans)
430 return -EINVAL;
431
432 state->vlans[vno].vid = val->value.i;
433
434 return 0;
435 }
436
437 static int mvsw61xx_get_enable_vlan(struct switch_dev *dev,
438 const struct switch_attr *attr, struct switch_val *val)
439 {
440 struct mvsw61xx_state *state = get_state(dev);
441
442 val->value.i = state->vlan_enabled;
443
444 return 0;
445 }
446
447 static int mvsw61xx_set_enable_vlan(struct switch_dev *dev,
448 const struct switch_attr *attr, struct switch_val *val)
449 {
450 struct mvsw61xx_state *state = get_state(dev);
451
452 state->vlan_enabled = val->value.i;
453
454 return 0;
455 }
456
457 static int mvsw61xx_get_mirror_rx_enable(struct switch_dev *dev,
458 const struct switch_attr *attr, struct switch_val *val)
459 {
460 struct mvsw61xx_state *state = get_state(dev);
461
462 val->value.i = state->mirror_rx;
463
464 return 0;
465 }
466
467 static int mvsw61xx_set_mirror_rx_enable(struct switch_dev *dev,
468 const struct switch_attr *attr, struct switch_val *val)
469 {
470 struct mvsw61xx_state *state = get_state(dev);
471
472 state->mirror_rx = val->value.i;
473
474 return 0;
475 }
476
477 static int mvsw61xx_get_mirror_tx_enable(struct switch_dev *dev,
478 const struct switch_attr *attr, struct switch_val *val)
479 {
480 struct mvsw61xx_state *state = get_state(dev);
481
482 val->value.i = state->mirror_tx;
483
484 return 0;
485 }
486
487 static int mvsw61xx_set_mirror_tx_enable(struct switch_dev *dev,
488 const struct switch_attr *attr, struct switch_val *val)
489 {
490 struct mvsw61xx_state *state = get_state(dev);
491
492 state->mirror_tx = val->value.i;
493
494 return 0;
495 }
496
497 static int mvsw61xx_get_mirror_monitor_port(struct switch_dev *dev,
498 const struct switch_attr *attr, struct switch_val *val)
499 {
500 struct mvsw61xx_state *state = get_state(dev);
501
502 val->value.i = state->monitor_port;
503
504 return 0;
505 }
506
507 static int mvsw61xx_set_mirror_monitor_port(struct switch_dev *dev,
508 const struct switch_attr *attr, struct switch_val *val)
509 {
510 struct mvsw61xx_state *state = get_state(dev);
511
512 state->monitor_port = val->value.i;
513
514 return 0;
515 }
516
517 static int mvsw61xx_get_mirror_source_port(struct switch_dev *dev,
518 const struct switch_attr *attr, struct switch_val *val)
519 {
520 struct mvsw61xx_state *state = get_state(dev);
521
522 val->value.i = state->source_port;
523
524 return 0;
525 }
526
527 static int mvsw61xx_set_mirror_source_port(struct switch_dev *dev,
528 const struct switch_attr *attr, struct switch_val *val)
529 {
530 struct mvsw61xx_state *state = get_state(dev);
531
532 state->source_port = val->value.i;
533
534 return 0;
535 }
536
537 static int mvsw61xx_vtu_program(struct switch_dev *dev)
538 {
539 struct mvsw61xx_state *state = get_state(dev);
540 u16 v1, v2, s1, s2;
541 int i;
542
543 /* Flush */
544 mvsw61xx_wait_mask_s(dev, MV_GLOBALREG(VTU_OP),
545 MV_VTUOP_INPROGRESS, 0);
546 sw16(dev, MV_GLOBALREG(VTU_OP),
547 MV_VTUOP_INPROGRESS | MV_VTUOP_PURGE);
548
549 /* Write VLAN table */
550 for (i = 1; i < dev->vlans; i++) {
551 if (state->vlans[i].mask == 0 ||
552 state->vlans[i].vid == 0 ||
553 state->vlans[i].port_based == true)
554 continue;
555
556 mvsw61xx_wait_mask_s(dev, MV_GLOBALREG(VTU_OP),
557 MV_VTUOP_INPROGRESS, 0);
558
559 /* Write per-VLAN port state into STU */
560 s1 = (u16) (state->vlans[i].port_sstate & 0xffff);
561 s2 = (u16) ((state->vlans[i].port_sstate >> 16) & 0xffff);
562
563 sw16(dev, MV_GLOBALREG(VTU_VID), MV_VTU_VID_VALID);
564 sw16(dev, MV_GLOBALREG(VTU_SID), i);
565 sw16(dev, MV_GLOBALREG(VTU_DATA1), s1);
566 sw16(dev, MV_GLOBALREG(VTU_DATA2), s2);
567 sw16(dev, MV_GLOBALREG(VTU_DATA3), 0);
568
569 sw16(dev, MV_GLOBALREG(VTU_OP),
570 MV_VTUOP_INPROGRESS | MV_VTUOP_STULOAD);
571 mvsw61xx_wait_mask_s(dev, MV_GLOBALREG(VTU_OP),
572 MV_VTUOP_INPROGRESS, 0);
573
574 /* Write VLAN information into VTU */
575 v1 = (u16) (state->vlans[i].port_mode & 0xffff);
576 v2 = (u16) ((state->vlans[i].port_mode >> 16) & 0xffff);
577
578 sw16(dev, MV_GLOBALREG(VTU_VID),
579 MV_VTU_VID_VALID | state->vlans[i].vid);
580 sw16(dev, MV_GLOBALREG(VTU_SID), i);
581 sw16(dev, MV_GLOBALREG(VTU_FID), i);
582 sw16(dev, MV_GLOBALREG(VTU_DATA1), v1);
583 sw16(dev, MV_GLOBALREG(VTU_DATA2), v2);
584 sw16(dev, MV_GLOBALREG(VTU_DATA3), 0);
585
586 sw16(dev, MV_GLOBALREG(VTU_OP),
587 MV_VTUOP_INPROGRESS | MV_VTUOP_LOAD);
588 mvsw61xx_wait_mask_s(dev, MV_GLOBALREG(VTU_OP),
589 MV_VTUOP_INPROGRESS, 0);
590 }
591
592 return 0;
593 }
594
595 static void mvsw61xx_vlan_port_config(struct switch_dev *dev, int vno)
596 {
597 struct mvsw61xx_state *state = get_state(dev);
598 int i, mode;
599
600 for (i = 0; i < dev->ports; i++) {
601 if (!(state->vlans[vno].mask & (1 << i)))
602 continue;
603
604 mode = (state->vlans[vno].port_mode >> (i * 4)) & 0xf;
605
606 if(mode != MV_VTUCTL_EGRESS_TAGGED)
607 state->ports[i].pvid = state->vlans[vno].vid;
608
609 if (state->vlans[vno].port_based) {
610 state->ports[i].mask |= state->vlans[vno].mask;
611 state->ports[i].fdb = vno;
612 }
613 else
614 state->ports[i].qmode = MV_8021Q_MODE_SECURE;
615 }
616 }
617
618 static int mvsw61xx_update_state(struct switch_dev *dev)
619 {
620 struct mvsw61xx_state *state = get_state(dev);
621 int i;
622 u16 reg;
623
624 if (!state->registered)
625 return -EINVAL;
626
627 /*
628 * Set 802.1q-only mode if vlan_enabled is true.
629 *
630 * Without this, even if 802.1q is enabled for
631 * a port/VLAN, it still depends on the port-based
632 * VLAN mask being set.
633 *
634 * With this setting, port-based VLANs are still
635 * functional, provided the VID is not in the VTU.
636 */
637 reg = sr16(dev, MV_GLOBAL2REG(SDET_POLARITY));
638
639 if (state->vlan_enabled)
640 reg |= MV_8021Q_VLAN_ONLY;
641 else
642 reg &= ~MV_8021Q_VLAN_ONLY;
643
644 sw16(dev, MV_GLOBAL2REG(SDET_POLARITY), reg);
645
646 /*
647 * Set port-based VLAN masks on each port
648 * based only on VLAN definitions known to
649 * the driver (i.e. in state).
650 *
651 * This means any pre-existing port mapping is
652 * wiped out once our driver is initialized.
653 */
654 for (i = 0; i < dev->ports; i++) {
655 state->ports[i].mask = 0;
656 state->ports[i].qmode = MV_8021Q_MODE_DISABLE;
657 }
658
659 for (i = 0; i < dev->vlans; i++)
660 mvsw61xx_vlan_port_config(dev, i);
661
662 for (i = 0; i < dev->ports; i++) {
663 reg = sr16(dev, MV_PORTREG(VLANID, i)) & ~MV_PVID_MASK;
664 reg |= state->ports[i].pvid;
665 sw16(dev, MV_PORTREG(VLANID, i), reg);
666
667 state->ports[i].mask &= ~(1 << i);
668
669 /* set default forwarding DB number and port mask */
670 reg = sr16(dev, MV_PORTREG(CONTROL1, i)) & ~MV_FDB_HI_MASK;
671 reg |= (state->ports[i].fdb >> MV_FDB_HI_SHIFT) &
672 MV_FDB_HI_MASK;
673 sw16(dev, MV_PORTREG(CONTROL1, i), reg);
674
675 reg = ((state->ports[i].fdb & 0xf) << MV_FDB_LO_SHIFT) |
676 state->ports[i].mask;
677 sw16(dev, MV_PORTREG(VLANMAP, i), reg);
678
679 reg = sr16(dev, MV_PORTREG(CONTROL2, i)) &
680 ~MV_8021Q_MODE_MASK;
681 reg |= state->ports[i].qmode << MV_8021Q_MODE_SHIFT;
682 sw16(dev, MV_PORTREG(CONTROL2, i), reg);
683 }
684
685 mvsw61xx_vtu_program(dev);
686
687 /* port mirroring */
688 /* reset all mirror registers */
689 for (i = 0; i < dev->ports; i++) {
690 reg = sr16(dev, MV_PORTREG(CONTROL2, i));
691 reg &= ~(MV_MIRROR_RX_SRC_MASK | MV_MIRROR_TX_SRC_MASK);
692 sw16(dev, MV_PORTREG(CONTROL2, i), reg);
693 }
694 reg = sr16(dev, MV_GLOBALREG(MONITOR_CTRL));
695 reg |= MV_MIRROR_RX_DEST_MASK | MV_MIRROR_TX_DEST_MASK;
696 sw16(dev, MV_GLOBALREG(MONITOR_CTRL), reg);
697
698 /* now enable mirroring if necessary */
699 if (state->mirror_rx) {
700 /* set ingress monitor source */
701 reg = sr16(dev, MV_PORTREG(CONTROL2, state->source_port)) & ~MV_MIRROR_RX_SRC_MASK;
702 reg |= state->mirror_rx << MV_MIRROR_RX_SRC_SHIFT;
703 sw16(dev, MV_PORTREG(CONTROL2, state->source_port), reg);
704 /* set ingress monitor destination */
705 reg = sr16(dev, MV_GLOBALREG(MONITOR_CTRL)) & ~MV_MIRROR_RX_DEST_MASK;
706 reg |= state->monitor_port << MV_MIRROR_RX_DEST_SHIFT;
707 sw16(dev, MV_GLOBALREG(MONITOR_CTRL), reg);
708 }
709
710 if (state->mirror_tx) {
711 /* set egress monitor source */
712 reg = sr16(dev, MV_PORTREG(CONTROL2, state->source_port)) & ~MV_MIRROR_TX_SRC_MASK;
713 reg |= state->mirror_tx << MV_MIRROR_TX_SRC_SHIFT;
714 sw16(dev, MV_PORTREG(CONTROL2, state->source_port), reg);
715 /* set egress monitor destination */
716 reg = sr16(dev, MV_GLOBALREG(MONITOR_CTRL)) & ~MV_MIRROR_TX_DEST_MASK;
717 reg |= state->monitor_port << MV_MIRROR_TX_DEST_SHIFT;
718 sw16(dev, MV_GLOBALREG(MONITOR_CTRL), reg);
719 }
720
721 return 0;
722 }
723
724 static int mvsw61xx_apply(struct switch_dev *dev)
725 {
726 return mvsw61xx_update_state(dev);
727 }
728
729 static void mvsw61xx_enable_serdes(struct switch_dev *dev)
730 {
731 int bmcr = mvsw61xx_mdio_page_read(dev, MV_REG_FIBER_SERDES,
732 MV_PAGE_FIBER_SERDES, MII_BMCR);
733 if (bmcr < 0)
734 return;
735
736 if (bmcr & BMCR_PDOWN)
737 mvsw61xx_mdio_page_write(dev, MV_REG_FIBER_SERDES,
738 MV_PAGE_FIBER_SERDES, MII_BMCR,
739 bmcr & ~BMCR_PDOWN);
740 }
741
742 static int _mvsw61xx_reset(struct switch_dev *dev, bool full)
743 {
744 struct mvsw61xx_state *state = get_state(dev);
745 int i;
746 u16 reg;
747
748 /* Disable all ports before reset */
749 for (i = 0; i < dev->ports; i++) {
750 reg = sr16(dev, MV_PORTREG(CONTROL, i)) &
751 ~MV_PORTCTRL_FORWARDING;
752 sw16(dev, MV_PORTREG(CONTROL, i), reg);
753 }
754
755 reg = sr16(dev, MV_GLOBALREG(CONTROL)) | MV_CONTROL_RESET;
756
757 sw16(dev, MV_GLOBALREG(CONTROL), reg);
758 if (mvsw61xx_wait_mask_s(dev, MV_GLOBALREG(CONTROL),
759 MV_CONTROL_RESET, 0) < 0)
760 return -ETIMEDOUT;
761
762 for (i = 0; i < dev->ports; i++) {
763 state->ports[i].fdb = 0;
764 state->ports[i].qmode = 0;
765 state->ports[i].mask = 0;
766 state->ports[i].pvid = 0;
767
768 /* Force flow control off */
769 reg = sr16(dev, MV_PORTREG(PHYCTL, i)) & ~MV_PHYCTL_FC_MASK;
770 reg |= MV_PHYCTL_FC_DISABLE;
771 sw16(dev, MV_PORTREG(PHYCTL, i), reg);
772
773 /* Set port association vector */
774 sw16(dev, MV_PORTREG(ASSOC, i), (1 << i));
775
776 /* power up phys */
777 if (full && i < 5) {
778 mvsw61xx_mdio_write(dev, i, MII_MV_SPEC_CTRL,
779 MV_SPEC_MDI_CROSS_AUTO |
780 MV_SPEC_ENERGY_DETECT |
781 MV_SPEC_DOWNSHIFT_COUNTER);
782 mvsw61xx_mdio_write(dev, i, MII_BMCR, BMCR_RESET |
783 BMCR_ANENABLE | BMCR_FULLDPLX |
784 BMCR_SPEED1000);
785 }
786
787 /* enable SerDes if necessary */
788 if (full && i >= 5 && state->model == MV_IDENT_VALUE_6176) {
789 u16 sts = sr16(dev, MV_PORTREG(STATUS, i));
790 u16 mode = sts & MV_PORT_STATUS_CMODE_MASK;
791
792 if (mode == MV_PORT_STATUS_CMODE_100BASE_X ||
793 mode == MV_PORT_STATUS_CMODE_1000BASE_X ||
794 mode == MV_PORT_STATUS_CMODE_SGMII) {
795 mvsw61xx_enable_serdes(dev);
796 }
797 }
798 }
799
800 for (i = 0; i < dev->vlans; i++) {
801 state->vlans[i].port_based = false;
802 state->vlans[i].mask = 0;
803 state->vlans[i].vid = 0;
804 state->vlans[i].port_mode = 0;
805 state->vlans[i].port_sstate = 0;
806 }
807
808 state->vlan_enabled = 0;
809
810 state->mirror_rx = false;
811 state->mirror_tx = false;
812 state->source_port = 0;
813 state->monitor_port = 0;
814
815 mvsw61xx_update_state(dev);
816
817 /* Re-enable ports */
818 for (i = 0; i < dev->ports; i++) {
819 reg = sr16(dev, MV_PORTREG(CONTROL, i)) |
820 MV_PORTCTRL_FORWARDING;
821 sw16(dev, MV_PORTREG(CONTROL, i), reg);
822 }
823
824 return 0;
825 }
826
827 static int mvsw61xx_reset(struct switch_dev *dev)
828 {
829 return _mvsw61xx_reset(dev, false);
830 }
831
832 enum {
833 MVSW61XX_VLAN_PORT_BASED,
834 MVSW61XX_VLAN_ID,
835 };
836
837 enum {
838 MVSW61XX_PORT_MASK,
839 MVSW61XX_PORT_QMODE,
840 };
841
842 static const struct switch_attr mvsw61xx_global[] = {
843 {
844 .type = SWITCH_TYPE_INT,
845 .name = "enable_vlan",
846 .description = "Enable 802.1q VLAN support",
847 .get = mvsw61xx_get_enable_vlan,
848 .set = mvsw61xx_set_enable_vlan,
849 },
850 {
851 .type = SWITCH_TYPE_INT,
852 .name = "enable_mirror_rx",
853 .description = "Enable mirroring of RX packets",
854 .set = mvsw61xx_set_mirror_rx_enable,
855 .get = mvsw61xx_get_mirror_rx_enable,
856 .max = 1
857 },
858 {
859 .type = SWITCH_TYPE_INT,
860 .name = "enable_mirror_tx",
861 .description = "Enable mirroring of TX packets",
862 .set = mvsw61xx_set_mirror_tx_enable,
863 .get = mvsw61xx_get_mirror_tx_enable,
864 .max = 1
865 },
866 {
867 .type = SWITCH_TYPE_INT,
868 .name = "mirror_monitor_port",
869 .description = "Mirror monitor port",
870 .set = mvsw61xx_set_mirror_monitor_port,
871 .get = mvsw61xx_get_mirror_monitor_port,
872 .max = MV_PORTS - 1
873 },
874 {
875 .type = SWITCH_TYPE_INT,
876 .name = "mirror_source_port",
877 .description = "Mirror source port",
878 .set = mvsw61xx_set_mirror_source_port,
879 .get = mvsw61xx_get_mirror_source_port,
880 .max = MV_PORTS - 1
881 },
882 };
883
884 static const struct switch_attr mvsw61xx_vlan[] = {
885 [MVSW61XX_VLAN_PORT_BASED] = {
886 .id = MVSW61XX_VLAN_PORT_BASED,
887 .type = SWITCH_TYPE_INT,
888 .name = "port_based",
889 .description = "Use port-based (non-802.1q) VLAN only",
890 .get = mvsw61xx_get_vlan_port_based,
891 .set = mvsw61xx_set_vlan_port_based,
892 },
893 [MVSW61XX_VLAN_ID] = {
894 .id = MVSW61XX_VLAN_ID,
895 .type = SWITCH_TYPE_INT,
896 .name = "vid",
897 .description = "Get/set VLAN ID",
898 .get = mvsw61xx_get_vid,
899 .set = mvsw61xx_set_vid,
900 },
901 };
902
903 static const struct switch_attr mvsw61xx_port[] = {
904 [MVSW61XX_PORT_MASK] = {
905 .id = MVSW61XX_PORT_MASK,
906 .type = SWITCH_TYPE_STRING,
907 .description = "Port-based VLAN mask",
908 .name = "mask",
909 .get = mvsw61xx_get_port_mask,
910 .set = NULL,
911 },
912 [MVSW61XX_PORT_QMODE] = {
913 .id = MVSW61XX_PORT_QMODE,
914 .type = SWITCH_TYPE_INT,
915 .description = "802.1q mode: 0=off/1=fallback/2=check/3=secure",
916 .name = "qmode",
917 .get = mvsw61xx_get_port_qmode,
918 .set = mvsw61xx_set_port_qmode,
919 },
920 };
921
922 static const struct switch_dev_ops mvsw61xx_ops = {
923 .attr_global = {
924 .attr = mvsw61xx_global,
925 .n_attr = ARRAY_SIZE(mvsw61xx_global),
926 },
927 .attr_vlan = {
928 .attr = mvsw61xx_vlan,
929 .n_attr = ARRAY_SIZE(mvsw61xx_vlan),
930 },
931 .attr_port = {
932 .attr = mvsw61xx_port,
933 .n_attr = ARRAY_SIZE(mvsw61xx_port),
934 },
935 .get_port_link = mvsw61xx_get_port_link,
936 .get_port_pvid = mvsw61xx_get_port_pvid,
937 .set_port_pvid = mvsw61xx_set_port_pvid,
938 .get_vlan_ports = mvsw61xx_get_vlan_ports,
939 .set_vlan_ports = mvsw61xx_set_vlan_ports,
940 .apply_config = mvsw61xx_apply,
941 .reset_switch = mvsw61xx_reset,
942 };
943
944 /* end swconfig stuff */
945
946 static int mvsw61xx_probe(struct platform_device *pdev)
947 {
948 struct mvsw61xx_state *state;
949 struct device_node *np = pdev->dev.of_node;
950 struct device_node *mdio;
951 char *model_str;
952 u32 val;
953 int err;
954
955 state = kzalloc(sizeof(*state), GFP_KERNEL);
956 if (!state)
957 return -ENOMEM;
958
959 mdio = of_parse_phandle(np, "mii-bus", 0);
960 if (!mdio) {
961 dev_err(&pdev->dev, "Couldn't get MII bus handle\n");
962 err = -ENODEV;
963 goto out_err;
964 }
965
966 state->bus = of_mdio_find_bus(mdio);
967 if (!state->bus) {
968 dev_err(&pdev->dev, "Couldn't find MII bus from handle\n");
969 err = -ENODEV;
970 goto out_err;
971 }
972
973 state->is_indirect = of_property_read_bool(np, "is-indirect");
974
975 if (state->is_indirect) {
976 if (of_property_read_u32(np, "reg", &val)) {
977 dev_err(&pdev->dev, "Switch address not specified\n");
978 err = -ENODEV;
979 goto out_err;
980 }
981
982 state->base_addr = val;
983 } else {
984 state->base_addr = MV_BASE;
985 }
986
987 state->model = r16(state->bus, state->is_indirect, state->base_addr,
988 MV_PORTREG(IDENT, 0)) & MV_IDENT_MASK;
989
990 switch(state->model) {
991 case MV_IDENT_VALUE_6171:
992 model_str = MV_IDENT_STR_6171;
993 break;
994 case MV_IDENT_VALUE_6172:
995 model_str = MV_IDENT_STR_6172;
996 break;
997 case MV_IDENT_VALUE_6176:
998 model_str = MV_IDENT_STR_6176;
999 break;
1000 case MV_IDENT_VALUE_6352:
1001 model_str = MV_IDENT_STR_6352;
1002 break;
1003 default:
1004 dev_err(&pdev->dev, "No compatible switch found at 0x%02x\n",
1005 state->base_addr);
1006 err = -ENODEV;
1007 goto out_err;
1008 }
1009
1010 platform_set_drvdata(pdev, state);
1011 dev_info(&pdev->dev, "Found %s at %s:%02x\n", model_str,
1012 state->bus->id, state->base_addr);
1013
1014 dev_info(&pdev->dev, "Using %sdirect addressing\n",
1015 (state->is_indirect ? "in" : ""));
1016
1017 if (of_property_read_u32(np, "cpu-port-0", &val)) {
1018 dev_err(&pdev->dev, "CPU port not set\n");
1019 err = -ENODEV;
1020 goto out_err;
1021 }
1022
1023 state->cpu_port0 = val;
1024
1025 if (!of_property_read_u32(np, "cpu-port-1", &val))
1026 state->cpu_port1 = val;
1027 else
1028 state->cpu_port1 = -1;
1029
1030 state->dev.vlans = MV_VLANS;
1031 state->dev.cpu_port = state->cpu_port0;
1032 state->dev.ports = MV_PORTS;
1033 state->dev.name = model_str;
1034 state->dev.ops = &mvsw61xx_ops;
1035 state->dev.alias = dev_name(&pdev->dev);
1036
1037 _mvsw61xx_reset(&state->dev, true);
1038
1039 err = register_switch(&state->dev, NULL);
1040 if (err < 0)
1041 goto out_err;
1042
1043 state->registered = true;
1044
1045 return 0;
1046 out_err:
1047 kfree(state);
1048 return err;
1049 }
1050
1051 static int
1052 mvsw61xx_remove(struct platform_device *pdev)
1053 {
1054 struct mvsw61xx_state *state = platform_get_drvdata(pdev);
1055
1056 if (state->registered)
1057 unregister_switch(&state->dev);
1058
1059 kfree(state);
1060
1061 return 0;
1062 }
1063
1064 static const struct of_device_id mvsw61xx_match[] = {
1065 { .compatible = "marvell,88e6171" },
1066 { .compatible = "marvell,88e6172" },
1067 { .compatible = "marvell,88e6176" },
1068 { .compatible = "marvell,88e6352" },
1069 { }
1070 };
1071 MODULE_DEVICE_TABLE(of, mvsw61xx_match);
1072
1073 static struct platform_driver mvsw61xx_driver = {
1074 .probe = mvsw61xx_probe,
1075 .remove = mvsw61xx_remove,
1076 .driver = {
1077 .name = "mvsw61xx",
1078 .of_match_table = of_match_ptr(mvsw61xx_match),
1079 .owner = THIS_MODULE,
1080 },
1081 };
1082
1083 static int __init mvsw61xx_module_init(void)
1084 {
1085 return platform_driver_register(&mvsw61xx_driver);
1086 }
1087 late_initcall(mvsw61xx_module_init);
1088
1089 static void __exit mvsw61xx_module_exit(void)
1090 {
1091 platform_driver_unregister(&mvsw61xx_driver);
1092 }
1093 module_exit(mvsw61xx_module_exit);
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