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generic: rtl8366: move common VLAN handling functions to rtl8366_smi.c
[openwrt/openwrt.git] / target / linux / generic / files / drivers / net / phy / rtl8366s.c
1 /*
2 * Platform driver for the Realtek RTL8366S ethernet switch
3 *
4 * Copyright (C) 2009-2010 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (C) 2010 Antti Seppälä <a.seppala@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
10 */
11
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/init.h>
15 #include <linux/platform_device.h>
16 #include <linux/delay.h>
17 #include <linux/skbuff.h>
18 #include <linux/switch.h>
19 #include <linux/rtl8366s.h>
20
21 #include "rtl8366_smi.h"
22
23 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
24 #include <linux/debugfs.h>
25 #endif
26
27 #define RTL8366S_DRIVER_DESC "Realtek RTL8366S ethernet switch driver"
28 #define RTL8366S_DRIVER_VER "0.2.2"
29
30 #define RTL8366S_PHY_NO_MAX 4
31 #define RTL8366S_PHY_PAGE_MAX 7
32 #define RTL8366S_PHY_ADDR_MAX 31
33
34 #define RTL8366S_CHIP_GLOBAL_CTRL_REG 0x0000
35 #define RTL8366S_CHIP_CTRL_VLAN (1 << 13)
36
37 /* Switch Global Configuration register */
38 #define RTL8366S_SGCR 0x0000
39 #define RTL8366S_SGCR_EN_BC_STORM_CTRL BIT(0)
40 #define RTL8366S_SGCR_MAX_LENGTH(_x) (_x << 4)
41 #define RTL8366S_SGCR_MAX_LENGTH_MASK RTL8366S_SGCR_MAX_LENGTH(0x3)
42 #define RTL8366S_SGCR_MAX_LENGTH_1522 RTL8366S_SGCR_MAX_LENGTH(0x0)
43 #define RTL8366S_SGCR_MAX_LENGTH_1536 RTL8366S_SGCR_MAX_LENGTH(0x1)
44 #define RTL8366S_SGCR_MAX_LENGTH_1552 RTL8366S_SGCR_MAX_LENGTH(0x2)
45 #define RTL8366S_SGCR_MAX_LENGTH_16000 RTL8366S_SGCR_MAX_LENGTH(0x3)
46
47 /* Port Enable Control register */
48 #define RTL8366S_PECR 0x0001
49
50 /* Switch Security Control registers */
51 #define RTL8366S_SSCR0 0x0002
52 #define RTL8366S_SSCR1 0x0003
53 #define RTL8366S_SSCR2 0x0004
54 #define RTL8366S_SSCR2_DROP_UNKNOWN_DA BIT(0)
55
56 #define RTL8366S_RESET_CTRL_REG 0x0100
57 #define RTL8366S_CHIP_CTRL_RESET_HW 1
58 #define RTL8366S_CHIP_CTRL_RESET_SW (1 << 1)
59
60 #define RTL8366S_CHIP_VERSION_CTRL_REG 0x0104
61 #define RTL8366S_CHIP_VERSION_MASK 0xf
62 #define RTL8366S_CHIP_ID_REG 0x0105
63 #define RTL8366S_CHIP_ID_8366 0x8366
64
65 /* PHY registers control */
66 #define RTL8366S_PHY_ACCESS_CTRL_REG 0x8028
67 #define RTL8366S_PHY_ACCESS_DATA_REG 0x8029
68
69 #define RTL8366S_PHY_CTRL_READ 1
70 #define RTL8366S_PHY_CTRL_WRITE 0
71
72 #define RTL8366S_PHY_REG_MASK 0x1f
73 #define RTL8366S_PHY_PAGE_OFFSET 5
74 #define RTL8366S_PHY_PAGE_MASK (0x7 << 5)
75 #define RTL8366S_PHY_NO_OFFSET 9
76 #define RTL8366S_PHY_NO_MASK (0x1f << 9)
77
78 /* LED control registers */
79 #define RTL8366S_LED_BLINKRATE_REG 0x0420
80 #define RTL8366S_LED_BLINKRATE_BIT 0
81 #define RTL8366S_LED_BLINKRATE_MASK 0x0007
82
83 #define RTL8366S_LED_CTRL_REG 0x0421
84 #define RTL8366S_LED_0_1_CTRL_REG 0x0422
85 #define RTL8366S_LED_2_3_CTRL_REG 0x0423
86
87 #define RTL8366S_MIB_COUNT 33
88 #define RTL8366S_GLOBAL_MIB_COUNT 1
89 #define RTL8366S_MIB_COUNTER_PORT_OFFSET 0x0040
90 #define RTL8366S_MIB_COUNTER_BASE 0x1000
91 #define RTL8366S_MIB_COUNTER_PORT_OFFSET2 0x0008
92 #define RTL8366S_MIB_COUNTER_BASE2 0x1180
93 #define RTL8366S_MIB_CTRL_REG 0x11F0
94 #define RTL8366S_MIB_CTRL_USER_MASK 0x01FF
95 #define RTL8366S_MIB_CTRL_BUSY_MASK 0x0001
96 #define RTL8366S_MIB_CTRL_RESET_MASK 0x0002
97
98 #define RTL8366S_MIB_CTRL_GLOBAL_RESET_MASK 0x0004
99 #define RTL8366S_MIB_CTRL_PORT_RESET_BIT 0x0003
100 #define RTL8366S_MIB_CTRL_PORT_RESET_MASK 0x01FC
101
102
103 #define RTL8366S_PORT_VLAN_CTRL_BASE 0x0058
104 #define RTL8366S_PORT_VLAN_CTRL_REG(_p) \
105 (RTL8366S_PORT_VLAN_CTRL_BASE + (_p) / 4)
106 #define RTL8366S_PORT_VLAN_CTRL_MASK 0xf
107 #define RTL8366S_PORT_VLAN_CTRL_SHIFT(_p) (4 * ((_p) % 4))
108
109
110 #define RTL8366S_VLAN_TABLE_READ_BASE 0x018B
111 #define RTL8366S_VLAN_TABLE_WRITE_BASE 0x0185
112
113 #define RTL8366S_VLAN_TB_CTRL_REG 0x010F
114
115 #define RTL8366S_TABLE_ACCESS_CTRL_REG 0x0180
116 #define RTL8366S_TABLE_VLAN_READ_CTRL 0x0E01
117 #define RTL8366S_TABLE_VLAN_WRITE_CTRL 0x0F01
118
119 #define RTL8366S_VLAN_MEMCONF_BASE 0x0016
120
121
122 #define RTL8366S_PORT_LINK_STATUS_BASE 0x0060
123 #define RTL8366S_PORT_STATUS_SPEED_MASK 0x0003
124 #define RTL8366S_PORT_STATUS_DUPLEX_MASK 0x0004
125 #define RTL8366S_PORT_STATUS_LINK_MASK 0x0010
126 #define RTL8366S_PORT_STATUS_TXPAUSE_MASK 0x0020
127 #define RTL8366S_PORT_STATUS_RXPAUSE_MASK 0x0040
128 #define RTL8366S_PORT_STATUS_AN_MASK 0x0080
129
130
131 #define RTL8366S_PORT_NUM_CPU 5
132 #define RTL8366S_NUM_PORTS 6
133 #define RTL8366S_NUM_VLANS 16
134 #define RTL8366S_NUM_LEDGROUPS 4
135 #define RTL8366S_NUM_VIDS 4096
136 #define RTL8366S_PRIORITYMAX 7
137 #define RTL8366S_FIDMAX 7
138
139
140 #define RTL8366S_PORT_1 (1 << 0) /* In userspace port 0 */
141 #define RTL8366S_PORT_2 (1 << 1) /* In userspace port 1 */
142 #define RTL8366S_PORT_3 (1 << 2) /* In userspace port 2 */
143 #define RTL8366S_PORT_4 (1 << 3) /* In userspace port 3 */
144
145 #define RTL8366S_PORT_UNKNOWN (1 << 4) /* No known connection */
146 #define RTL8366S_PORT_CPU (1 << 5) /* CPU port */
147
148 #define RTL8366S_PORT_ALL (RTL8366S_PORT_1 | \
149 RTL8366S_PORT_2 | \
150 RTL8366S_PORT_3 | \
151 RTL8366S_PORT_4 | \
152 RTL8366S_PORT_UNKNOWN | \
153 RTL8366S_PORT_CPU)
154
155 #define RTL8366S_PORT_ALL_BUT_CPU (RTL8366S_PORT_1 | \
156 RTL8366S_PORT_2 | \
157 RTL8366S_PORT_3 | \
158 RTL8366S_PORT_4 | \
159 RTL8366S_PORT_UNKNOWN)
160
161 #define RTL8366S_PORT_ALL_EXTERNAL (RTL8366S_PORT_1 | \
162 RTL8366S_PORT_2 | \
163 RTL8366S_PORT_3 | \
164 RTL8366S_PORT_4)
165
166 #define RTL8366S_PORT_ALL_INTERNAL (RTL8366S_PORT_UNKNOWN | \
167 RTL8366S_PORT_CPU)
168
169 struct rtl8366s {
170 struct device *parent;
171 struct rtl8366_smi smi;
172 struct switch_dev dev;
173 char buf[4096];
174 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
175 struct dentry *debugfs_root;
176 #endif
177 };
178
179 struct rtl8366s_vlan_mc {
180 u16 reserved2:1;
181 u16 priority:3;
182 u16 vid:12;
183
184 u16 reserved1:1;
185 u16 fid:3;
186 u16 untag:6;
187 u16 member:6;
188 };
189
190 struct rtl8366s_vlan_4k {
191 u16 reserved1:4;
192 u16 vid:12;
193
194 u16 reserved2:1;
195 u16 fid:3;
196 u16 untag:6;
197 u16 member:6;
198 };
199
200 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
201 u16 g_dbg_reg;
202 #endif
203
204 struct mib_counter {
205 unsigned base;
206 unsigned offset;
207 unsigned length;
208 const char *name;
209 };
210
211 static struct mib_counter rtl8366s_mib_counters[RTL8366S_MIB_COUNT] = {
212 { 0, 0, 4, "IfInOctets" },
213 { 0, 4, 4, "EtherStatsOctets" },
214 { 0, 8, 2, "EtherStatsUnderSizePkts" },
215 { 0, 10, 2, "EtherFragments" },
216 { 0, 12, 2, "EtherStatsPkts64Octets" },
217 { 0, 14, 2, "EtherStatsPkts65to127Octets" },
218 { 0, 16, 2, "EtherStatsPkts128to255Octets" },
219 { 0, 18, 2, "EtherStatsPkts256to511Octets" },
220 { 0, 20, 2, "EtherStatsPkts512to1023Octets" },
221 { 0, 22, 2, "EtherStatsPkts1024to1518Octets" },
222 { 0, 24, 2, "EtherOversizeStats" },
223 { 0, 26, 2, "EtherStatsJabbers" },
224 { 0, 28, 2, "IfInUcastPkts" },
225 { 0, 30, 2, "EtherStatsMulticastPkts" },
226 { 0, 32, 2, "EtherStatsBroadcastPkts" },
227 { 0, 34, 2, "EtherStatsDropEvents" },
228 { 0, 36, 2, "Dot3StatsFCSErrors" },
229 { 0, 38, 2, "Dot3StatsSymbolErrors" },
230 { 0, 40, 2, "Dot3InPauseFrames" },
231 { 0, 42, 2, "Dot3ControlInUnknownOpcodes" },
232 { 0, 44, 4, "IfOutOctets" },
233 { 0, 48, 2, "Dot3StatsSingleCollisionFrames" },
234 { 0, 50, 2, "Dot3StatMultipleCollisionFrames" },
235 { 0, 52, 2, "Dot3sDeferredTransmissions" },
236 { 0, 54, 2, "Dot3StatsLateCollisions" },
237 { 0, 56, 2, "EtherStatsCollisions" },
238 { 0, 58, 2, "Dot3StatsExcessiveCollisions" },
239 { 0, 60, 2, "Dot3OutPauseFrames" },
240 { 0, 62, 2, "Dot1dBasePortDelayExceededDiscards" },
241
242 /*
243 * The following counters are accessible at a different
244 * base address.
245 */
246 { 1, 0, 2, "Dot1dTpPortInDiscards" },
247 { 1, 2, 2, "IfOutUcastPkts" },
248 { 1, 4, 2, "IfOutMulticastPkts" },
249 { 1, 6, 2, "IfOutBroadcastPkts" },
250 };
251
252 #define REG_WR(_smi, _reg, _val) \
253 do { \
254 err = rtl8366_smi_write_reg(_smi, _reg, _val); \
255 if (err) \
256 return err; \
257 } while (0)
258
259 #define REG_RMW(_smi, _reg, _mask, _val) \
260 do { \
261 err = rtl8366_smi_rmwr(_smi, _reg, _mask, _val); \
262 if (err) \
263 return err; \
264 } while (0)
265
266 static inline struct rtl8366s *smi_to_rtl8366s(struct rtl8366_smi *smi)
267 {
268 return container_of(smi, struct rtl8366s, smi);
269 }
270
271 static inline struct rtl8366s *sw_to_rtl8366s(struct switch_dev *sw)
272 {
273 return container_of(sw, struct rtl8366s, dev);
274 }
275
276 static inline struct rtl8366_smi *sw_to_rtl8366_smi(struct switch_dev *sw)
277 {
278 struct rtl8366s *rtl = sw_to_rtl8366s(sw);
279 return &rtl->smi;
280 }
281
282 static int rtl8366s_reset_chip(struct rtl8366_smi *smi)
283 {
284 int timeout = 10;
285 u32 data;
286
287 rtl8366_smi_write_reg(smi, RTL8366S_RESET_CTRL_REG,
288 RTL8366S_CHIP_CTRL_RESET_HW);
289 do {
290 msleep(1);
291 if (rtl8366_smi_read_reg(smi, RTL8366S_RESET_CTRL_REG, &data))
292 return -EIO;
293
294 if (!(data & RTL8366S_CHIP_CTRL_RESET_HW))
295 break;
296 } while (--timeout);
297
298 if (!timeout) {
299 printk("Timeout waiting for the switch to reset\n");
300 return -EIO;
301 }
302
303 return 0;
304 }
305
306 static int rtl8366s_hw_init(struct rtl8366_smi *smi)
307 {
308 int err;
309
310 /* set maximum packet length to 1536 bytes */
311 REG_RMW(smi, RTL8366S_SGCR, RTL8366S_SGCR_MAX_LENGTH_MASK,
312 RTL8366S_SGCR_MAX_LENGTH_1536);
313
314 /* enable all ports */
315 REG_WR(smi, RTL8366S_PECR, 0);
316
317 /* disable learning for all ports */
318 REG_WR(smi, RTL8366S_SSCR0, RTL8366S_PORT_ALL);
319
320 /* disable auto ageing for all ports */
321 REG_WR(smi, RTL8366S_SSCR1, RTL8366S_PORT_ALL);
322
323 /* don't drop packets whose DA has not been learned */
324 REG_RMW(smi, RTL8366S_SSCR2, RTL8366S_SSCR2_DROP_UNKNOWN_DA, 0);
325
326 return 0;
327 }
328
329 static int rtl8366s_read_phy_reg(struct rtl8366_smi *smi,
330 u32 phy_no, u32 page, u32 addr, u32 *data)
331 {
332 u32 reg;
333 int ret;
334
335 if (phy_no > RTL8366S_PHY_NO_MAX)
336 return -EINVAL;
337
338 if (page > RTL8366S_PHY_PAGE_MAX)
339 return -EINVAL;
340
341 if (addr > RTL8366S_PHY_ADDR_MAX)
342 return -EINVAL;
343
344 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
345 RTL8366S_PHY_CTRL_READ);
346 if (ret)
347 return ret;
348
349 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
350 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
351 (addr & RTL8366S_PHY_REG_MASK);
352
353 ret = rtl8366_smi_write_reg(smi, reg, 0);
354 if (ret)
355 return ret;
356
357 ret = rtl8366_smi_read_reg(smi, RTL8366S_PHY_ACCESS_DATA_REG, data);
358 if (ret)
359 return ret;
360
361 return 0;
362 }
363
364 static int rtl8366s_write_phy_reg(struct rtl8366_smi *smi,
365 u32 phy_no, u32 page, u32 addr, u32 data)
366 {
367 u32 reg;
368 int ret;
369
370 if (phy_no > RTL8366S_PHY_NO_MAX)
371 return -EINVAL;
372
373 if (page > RTL8366S_PHY_PAGE_MAX)
374 return -EINVAL;
375
376 if (addr > RTL8366S_PHY_ADDR_MAX)
377 return -EINVAL;
378
379 ret = rtl8366_smi_write_reg(smi, RTL8366S_PHY_ACCESS_CTRL_REG,
380 RTL8366S_PHY_CTRL_WRITE);
381 if (ret)
382 return ret;
383
384 reg = 0x8000 | (1 << (phy_no + RTL8366S_PHY_NO_OFFSET)) |
385 ((page << RTL8366S_PHY_PAGE_OFFSET) & RTL8366S_PHY_PAGE_MASK) |
386 (addr & RTL8366S_PHY_REG_MASK);
387
388 ret = rtl8366_smi_write_reg(smi, reg, data);
389 if (ret)
390 return ret;
391
392 return 0;
393 }
394
395 static int rtl8366_get_mib_counter(struct rtl8366_smi *smi, int counter,
396 int port, unsigned long long *val)
397 {
398 int i;
399 int err;
400 u32 addr, data;
401 u64 mibvalue;
402
403 if (port > RTL8366S_NUM_PORTS || counter >= RTL8366S_MIB_COUNT)
404 return -EINVAL;
405
406 switch (rtl8366s_mib_counters[counter].base) {
407 case 0:
408 addr = RTL8366S_MIB_COUNTER_BASE +
409 RTL8366S_MIB_COUNTER_PORT_OFFSET * port;
410 break;
411
412 case 1:
413 addr = RTL8366S_MIB_COUNTER_BASE2 +
414 RTL8366S_MIB_COUNTER_PORT_OFFSET2 * port;
415 break;
416
417 default:
418 return -EINVAL;
419 }
420
421 addr += rtl8366s_mib_counters[counter].offset;
422
423 /*
424 * Writing access counter address first
425 * then ASIC will prepare 64bits counter wait for being retrived
426 */
427 data = 0; /* writing data will be discard by ASIC */
428 err = rtl8366_smi_write_reg(smi, addr, data);
429 if (err)
430 return err;
431
432 /* read MIB control register */
433 err = rtl8366_smi_read_reg(smi, RTL8366S_MIB_CTRL_REG, &data);
434 if (err)
435 return err;
436
437 if (data & RTL8366S_MIB_CTRL_BUSY_MASK)
438 return -EBUSY;
439
440 if (data & RTL8366S_MIB_CTRL_RESET_MASK)
441 return -EIO;
442
443 mibvalue = 0;
444 for (i = rtl8366s_mib_counters[counter].length; i > 0; i--) {
445 err = rtl8366_smi_read_reg(smi, addr + (i - 1), &data);
446 if (err)
447 return err;
448
449 mibvalue = (mibvalue << 16) | (data & 0xFFFF);
450 }
451
452 *val = mibvalue;
453 return 0;
454 }
455
456 static int rtl8366s_get_vlan_4k(struct rtl8366_smi *smi, u32 vid,
457 struct rtl8366_vlan_4k *vlan4k)
458 {
459 struct rtl8366s_vlan_4k vlan4k_priv;
460 int err;
461 u32 data;
462 u16 *tableaddr;
463
464 memset(vlan4k, '\0', sizeof(struct rtl8366_vlan_4k));
465 vlan4k_priv.vid = vid;
466
467 if (vid >= RTL8366S_NUM_VIDS)
468 return -EINVAL;
469
470 tableaddr = (u16 *)&vlan4k_priv;
471
472 /* write VID */
473 data = *tableaddr;
474 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
475 if (err)
476 return err;
477
478 /* write table access control word */
479 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
480 RTL8366S_TABLE_VLAN_READ_CTRL);
481 if (err)
482 return err;
483
484 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE, &data);
485 if (err)
486 return err;
487
488 *tableaddr = data;
489 tableaddr++;
490
491 err = rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TABLE_READ_BASE + 1,
492 &data);
493 if (err)
494 return err;
495
496 *tableaddr = data;
497
498 vlan4k->vid = vid;
499 vlan4k->untag = vlan4k_priv.untag;
500 vlan4k->member = vlan4k_priv.member;
501 vlan4k->fid = vlan4k_priv.fid;
502
503 return 0;
504 }
505
506 static int rtl8366s_set_vlan_4k(struct rtl8366_smi *smi,
507 const struct rtl8366_vlan_4k *vlan4k)
508 {
509 struct rtl8366s_vlan_4k vlan4k_priv;
510 int err;
511 u32 data;
512 u16 *tableaddr;
513
514 if (vlan4k->vid >= RTL8366S_NUM_VIDS ||
515 vlan4k->member > RTL8366S_PORT_ALL ||
516 vlan4k->untag > RTL8366S_PORT_ALL ||
517 vlan4k->fid > RTL8366S_FIDMAX)
518 return -EINVAL;
519
520 vlan4k_priv.vid = vlan4k->vid;
521 vlan4k_priv.untag = vlan4k->untag;
522 vlan4k_priv.member = vlan4k->member;
523 vlan4k_priv.fid = vlan4k->fid;
524
525 tableaddr = (u16 *)&vlan4k_priv;
526
527 data = *tableaddr;
528
529 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE, data);
530 if (err)
531 return err;
532
533 tableaddr++;
534
535 data = *tableaddr;
536
537 err = rtl8366_smi_write_reg(smi, RTL8366S_VLAN_TABLE_WRITE_BASE + 1,
538 data);
539 if (err)
540 return err;
541
542 /* write table access control word */
543 err = rtl8366_smi_write_reg(smi, RTL8366S_TABLE_ACCESS_CTRL_REG,
544 RTL8366S_TABLE_VLAN_WRITE_CTRL);
545
546 return err;
547 }
548
549 static int rtl8366s_get_vlan_mc(struct rtl8366_smi *smi, u32 index,
550 struct rtl8366_vlan_mc *vlanmc)
551 {
552 struct rtl8366s_vlan_mc vlanmc_priv;
553 int err;
554 u32 addr;
555 u32 data;
556 u16 *tableaddr;
557
558 memset(vlanmc, '\0', sizeof(struct rtl8366_vlan_mc));
559
560 if (index >= RTL8366S_NUM_VLANS)
561 return -EINVAL;
562
563 tableaddr = (u16 *)&vlanmc_priv;
564
565 addr = RTL8366S_VLAN_MEMCONF_BASE + (index << 1);
566 err = rtl8366_smi_read_reg(smi, addr, &data);
567 if (err)
568 return err;
569
570 *tableaddr = data;
571 tableaddr++;
572
573 addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index << 1);
574 err = rtl8366_smi_read_reg(smi, addr, &data);
575 if (err)
576 return err;
577
578 *tableaddr = data;
579
580 vlanmc->vid = vlanmc_priv.vid;
581 vlanmc->priority = vlanmc_priv.priority;
582 vlanmc->untag = vlanmc_priv.untag;
583 vlanmc->member = vlanmc_priv.member;
584 vlanmc->fid = vlanmc_priv.fid;
585
586 return 0;
587 }
588
589 static int rtl8366s_set_vlan_mc(struct rtl8366_smi *smi, u32 index,
590 const struct rtl8366_vlan_mc *vlanmc)
591 {
592 struct rtl8366s_vlan_mc vlanmc_priv;
593 int err;
594 u32 addr;
595 u32 data;
596 u16 *tableaddr;
597
598 if (index >= RTL8366S_NUM_VLANS ||
599 vlanmc->vid >= RTL8366S_NUM_VIDS ||
600 vlanmc->priority > RTL8366S_PRIORITYMAX ||
601 vlanmc->member > RTL8366S_PORT_ALL ||
602 vlanmc->untag > RTL8366S_PORT_ALL ||
603 vlanmc->fid > RTL8366S_FIDMAX)
604 return -EINVAL;
605
606 vlanmc_priv.vid = vlanmc->vid;
607 vlanmc_priv.priority = vlanmc->priority;
608 vlanmc_priv.untag = vlanmc->untag;
609 vlanmc_priv.member = vlanmc->member;
610 vlanmc_priv.fid = vlanmc->fid;
611
612 addr = RTL8366S_VLAN_MEMCONF_BASE + (index << 1);
613
614 tableaddr = (u16 *)&vlanmc_priv;
615 data = *tableaddr;
616
617 err = rtl8366_smi_write_reg(smi, addr, data);
618 if (err)
619 return err;
620
621 addr = RTL8366S_VLAN_MEMCONF_BASE + 1 + (index << 1);
622
623 tableaddr++;
624 data = *tableaddr;
625
626 err = rtl8366_smi_write_reg(smi, addr, data);
627 if (err)
628 return err;
629
630 return 0;
631 }
632
633 static int rtl8366s_get_mc_index(struct rtl8366_smi *smi, int port, int *val)
634 {
635 u32 data;
636 int err;
637
638 if (port >= RTL8366S_NUM_PORTS)
639 return -EINVAL;
640
641 err = rtl8366_smi_read_reg(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
642 &data);
643 if (err)
644 return err;
645
646 *val = (data >> RTL8366S_PORT_VLAN_CTRL_SHIFT(port)) &
647 RTL8366S_PORT_VLAN_CTRL_MASK;
648
649 return 0;
650 }
651
652 static int rtl8366s_set_mc_index(struct rtl8366_smi *smi, int port, int index)
653 {
654 if (port >= RTL8366S_NUM_PORTS || index >= RTL8366S_NUM_VLANS)
655 return -EINVAL;
656
657 return rtl8366_smi_rmwr(smi, RTL8366S_PORT_VLAN_CTRL_REG(port),
658 RTL8366S_PORT_VLAN_CTRL_MASK <<
659 RTL8366S_PORT_VLAN_CTRL_SHIFT(port),
660 (index & RTL8366S_PORT_VLAN_CTRL_MASK) <<
661 RTL8366S_PORT_VLAN_CTRL_SHIFT(port));
662 }
663
664 static int rtl8366s_vlan_set_vlan(struct rtl8366_smi *smi, int enable)
665 {
666 return rtl8366_smi_rmwr(smi, RTL8366S_CHIP_GLOBAL_CTRL_REG,
667 RTL8366S_CHIP_CTRL_VLAN,
668 (enable) ? RTL8366S_CHIP_CTRL_VLAN : 0);
669 }
670
671 static int rtl8366s_vlan_set_4ktable(struct rtl8366_smi *smi, int enable)
672 {
673 return rtl8366_smi_rmwr(smi, RTL8366S_VLAN_TB_CTRL_REG,
674 1, (enable) ? 1 : 0);
675 }
676
677 #ifdef CONFIG_RTL8366S_PHY_DEBUG_FS
678 static int rtl8366s_debugfs_open(struct inode *inode, struct file *file)
679 {
680 file->private_data = inode->i_private;
681 return 0;
682 }
683
684 static ssize_t rtl8366s_read_debugfs_mibs(struct file *file,
685 char __user *user_buf,
686 size_t count, loff_t *ppos)
687 {
688 struct rtl8366s *rtl = (struct rtl8366s *)file->private_data;
689 struct rtl8366_smi *smi = &rtl->smi;
690 int i, j, len = 0;
691 char *buf = rtl->buf;
692
693 len += snprintf(buf + len, sizeof(rtl->buf) - len,
694 "%-36s %12s %12s %12s %12s %12s %12s\n",
695 "Counter",
696 "Port 0", "Port 1", "Port 2",
697 "Port 3", "Port 4", "Port 5");
698
699 for (i = 0; i < ARRAY_SIZE(rtl8366s_mib_counters); ++i) {
700 len += snprintf(buf + len, sizeof(rtl->buf) - len, "%-36s ",
701 rtl8366s_mib_counters[i].name);
702 for (j = 0; j < RTL8366S_NUM_PORTS; ++j) {
703 unsigned long long counter = 0;
704
705 if (!rtl8366_get_mib_counter(smi, i, j, &counter))
706 len += snprintf(buf + len,
707 sizeof(rtl->buf) - len,
708 "%12llu ", counter);
709 else
710 len += snprintf(buf + len,
711 sizeof(rtl->buf) - len,
712 "%12s ", "error");
713 }
714 len += snprintf(buf + len, sizeof(rtl->buf) - len, "\n");
715 }
716
717 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
718 }
719
720 static ssize_t rtl8366s_read_debugfs_vlan_mc(struct file *file,
721 char __user *user_buf,
722 size_t count, loff_t *ppos)
723 {
724 struct rtl8366s *rtl = (struct rtl8366s *)file->private_data;
725 struct rtl8366_smi *smi = &rtl->smi;
726 int i, len = 0;
727 char *buf = rtl->buf;
728
729 len += snprintf(buf + len, sizeof(rtl->buf) - len,
730 "%2s %6s %4s %6s %6s %3s\n",
731 "id", "vid","prio", "member", "untag", "fid");
732
733 for (i = 0; i < RTL8366S_NUM_VLANS; ++i) {
734 struct rtl8366_vlan_mc vlanmc;
735
736 rtl8366s_get_vlan_mc(smi, i, &vlanmc);
737
738 len += snprintf(buf + len, sizeof(rtl->buf) - len,
739 "%2d %6d %4d 0x%04x 0x%04x %3d\n",
740 i, vlanmc.vid, vlanmc.priority,
741 vlanmc.member, vlanmc.untag, vlanmc.fid);
742 }
743
744 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
745 }
746
747 static ssize_t rtl8366s_read_debugfs_reg(struct file *file,
748 char __user *user_buf,
749 size_t count, loff_t *ppos)
750 {
751 struct rtl8366s *rtl = (struct rtl8366s *)file->private_data;
752 struct rtl8366_smi *smi = &rtl->smi;
753 u32 t, reg = g_dbg_reg;
754 int err, len = 0;
755 char *buf = rtl->buf;
756
757 memset(buf, '\0', sizeof(rtl->buf));
758
759 err = rtl8366_smi_read_reg(smi, reg, &t);
760 if (err) {
761 len += snprintf(buf, sizeof(rtl->buf),
762 "Read failed (reg: 0x%04x)\n", reg);
763 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
764 }
765
766 len += snprintf(buf, sizeof(rtl->buf), "reg = 0x%04x, val = 0x%04x\n",
767 reg, t);
768
769 return simple_read_from_buffer(user_buf, count, ppos, buf, len);
770 }
771
772 static ssize_t rtl8366s_write_debugfs_reg(struct file *file,
773 const char __user *user_buf,
774 size_t count, loff_t *ppos)
775 {
776 struct rtl8366s *rtl = (struct rtl8366s *)file->private_data;
777 struct rtl8366_smi *smi = &rtl->smi;
778 unsigned long data;
779 u32 reg = g_dbg_reg;
780 int err;
781 size_t len;
782 char *buf = rtl->buf;
783
784 len = min(count, sizeof(rtl->buf) - 1);
785 if (copy_from_user(buf, user_buf, len)) {
786 dev_err(rtl->parent, "copy from user failed\n");
787 return -EFAULT;
788 }
789
790 buf[len] = '\0';
791 if (len > 0 && buf[len - 1] == '\n')
792 buf[len - 1] = '\0';
793
794
795 if (strict_strtoul(buf, 16, &data)) {
796 dev_err(rtl->parent, "Invalid reg value %s\n", buf);
797 } else {
798 err = rtl8366_smi_write_reg(smi, reg, data);
799 if (err) {
800 dev_err(rtl->parent,
801 "writing reg 0x%04x val 0x%04lx failed\n",
802 reg, data);
803 }
804 }
805
806 return count;
807 }
808
809 static const struct file_operations fops_rtl8366s_regs = {
810 .read = rtl8366s_read_debugfs_reg,
811 .write = rtl8366s_write_debugfs_reg,
812 .open = rtl8366s_debugfs_open,
813 .owner = THIS_MODULE
814 };
815
816 static const struct file_operations fops_rtl8366s_vlan_mc = {
817 .read = rtl8366s_read_debugfs_vlan_mc,
818 .open = rtl8366s_debugfs_open,
819 .owner = THIS_MODULE
820 };
821
822 static const struct file_operations fops_rtl8366s_mibs = {
823 .read = rtl8366s_read_debugfs_mibs,
824 .open = rtl8366s_debugfs_open,
825 .owner = THIS_MODULE
826 };
827
828 static void rtl8366s_debugfs_init(struct rtl8366s *rtl)
829 {
830 struct dentry *node;
831 struct dentry *root;
832
833 if (!rtl->debugfs_root)
834 rtl->debugfs_root = debugfs_create_dir("rtl8366s", NULL);
835
836 if (!rtl->debugfs_root) {
837 dev_err(rtl->parent, "Unable to create debugfs dir\n");
838 return;
839 }
840 root = rtl->debugfs_root;
841
842 node = debugfs_create_x16("reg", S_IRUGO | S_IWUSR, root, &g_dbg_reg);
843 if (!node) {
844 dev_err(rtl->parent, "Creating debugfs file '%s' failed\n",
845 "reg");
846 return;
847 }
848
849 node = debugfs_create_file("val", S_IRUGO | S_IWUSR, root, rtl,
850 &fops_rtl8366s_regs);
851 if (!node) {
852 dev_err(rtl->parent, "Creating debugfs file '%s' failed\n",
853 "val");
854 return;
855 }
856
857 node = debugfs_create_file("vlan_mc", S_IRUSR, root, rtl,
858 &fops_rtl8366s_vlan_mc);
859 if (!node) {
860 dev_err(rtl->parent, "Creating debugfs file '%s' failed\n",
861 "vlan_mc");
862 return;
863 }
864
865 node = debugfs_create_file("mibs", S_IRUSR, root, rtl,
866 &fops_rtl8366s_mibs);
867 if (!node) {
868 dev_err(rtl->parent, "Creating debugfs file '%s' failed\n",
869 "mibs");
870 return;
871 }
872 }
873
874 static void rtl8366s_debugfs_remove(struct rtl8366s *rtl)
875 {
876 if (rtl->debugfs_root) {
877 debugfs_remove_recursive(rtl->debugfs_root);
878 rtl->debugfs_root = NULL;
879 }
880 }
881
882 #else
883 static inline void rtl8366s_debugfs_init(struct rtl8366s *rtl) {}
884 static inline void rtl8366s_debugfs_remove(struct rtl8366s *rtl) {}
885 #endif /* CONFIG_RTL8366S_PHY_DEBUG_FS */
886
887 static int rtl8366s_sw_reset_mibs(struct switch_dev *dev,
888 const struct switch_attr *attr,
889 struct switch_val *val)
890 {
891 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
892 int err = 0;
893
894 if (val->value.i == 1)
895 err = rtl8366_smi_rmwr(smi, RTL8366S_MIB_CTRL_REG, 0, (1 << 2));
896
897 return err;
898 }
899
900 static int rtl8366s_sw_get_vlan_enable(struct switch_dev *dev,
901 const struct switch_attr *attr,
902 struct switch_val *val)
903 {
904 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
905 u32 data;
906
907 if (attr->ofs == 1) {
908 rtl8366_smi_read_reg(smi, RTL8366S_CHIP_GLOBAL_CTRL_REG, &data);
909
910 if (data & RTL8366S_CHIP_CTRL_VLAN)
911 val->value.i = 1;
912 else
913 val->value.i = 0;
914 } else if (attr->ofs == 2) {
915 rtl8366_smi_read_reg(smi, RTL8366S_VLAN_TB_CTRL_REG, &data);
916
917 if (data & 0x0001)
918 val->value.i = 1;
919 else
920 val->value.i = 0;
921 }
922
923 return 0;
924 }
925
926 static int rtl8366s_sw_get_blinkrate(struct switch_dev *dev,
927 const struct switch_attr *attr,
928 struct switch_val *val)
929 {
930 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
931 u32 data;
932
933 rtl8366_smi_read_reg(smi, RTL8366S_LED_BLINKRATE_REG, &data);
934
935 val->value.i = (data & (RTL8366S_LED_BLINKRATE_MASK));
936
937 return 0;
938 }
939
940 static int rtl8366s_sw_set_blinkrate(struct switch_dev *dev,
941 const struct switch_attr *attr,
942 struct switch_val *val)
943 {
944 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
945
946 if (val->value.i >= 6)
947 return -EINVAL;
948
949 return rtl8366_smi_rmwr(smi, RTL8366S_LED_BLINKRATE_REG,
950 RTL8366S_LED_BLINKRATE_MASK,
951 val->value.i);
952 }
953
954 static int rtl8366s_sw_set_vlan_enable(struct switch_dev *dev,
955 const struct switch_attr *attr,
956 struct switch_val *val)
957 {
958 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
959
960 if (attr->ofs == 1)
961 return rtl8366s_vlan_set_vlan(smi, val->value.i);
962 else
963 return rtl8366s_vlan_set_4ktable(smi, val->value.i);
964 }
965
966 static const char *rtl8366s_speed_str(unsigned speed)
967 {
968 switch (speed) {
969 case 0:
970 return "10baseT";
971 case 1:
972 return "100baseT";
973 case 2:
974 return "1000baseT";
975 }
976
977 return "unknown";
978 }
979
980 static int rtl8366s_sw_get_port_link(struct switch_dev *dev,
981 const struct switch_attr *attr,
982 struct switch_val *val)
983 {
984 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
985 struct rtl8366_smi *smi = &rtl->smi;
986 u32 len = 0, data = 0;
987
988 if (val->port_vlan >= RTL8366S_NUM_PORTS)
989 return -EINVAL;
990
991 memset(rtl->buf, '\0', sizeof(rtl->buf));
992 rtl8366_smi_read_reg(smi, RTL8366S_PORT_LINK_STATUS_BASE +
993 (val->port_vlan / 2), &data);
994
995 if (val->port_vlan % 2)
996 data = data >> 8;
997
998 if (data & RTL8366S_PORT_STATUS_LINK_MASK) {
999 len = snprintf(rtl->buf, sizeof(rtl->buf),
1000 "port:%d link:up speed:%s %s-duplex %s%s%s",
1001 val->port_vlan,
1002 rtl8366s_speed_str(data &
1003 RTL8366S_PORT_STATUS_SPEED_MASK),
1004 (data & RTL8366S_PORT_STATUS_DUPLEX_MASK) ?
1005 "full" : "half",
1006 (data & RTL8366S_PORT_STATUS_TXPAUSE_MASK) ?
1007 "tx-pause ": "",
1008 (data & RTL8366S_PORT_STATUS_RXPAUSE_MASK) ?
1009 "rx-pause " : "",
1010 (data & RTL8366S_PORT_STATUS_AN_MASK) ?
1011 "nway ": "");
1012 } else {
1013 len = snprintf(rtl->buf, sizeof(rtl->buf), "port:%d link: down",
1014 val->port_vlan);
1015 }
1016
1017 val->value.s = rtl->buf;
1018 val->len = len;
1019
1020 return 0;
1021 }
1022
1023 static int rtl8366s_sw_get_vlan_info(struct switch_dev *dev,
1024 const struct switch_attr *attr,
1025 struct switch_val *val)
1026 {
1027 int i;
1028 u32 len = 0;
1029 struct rtl8366_vlan_4k vlan4k;
1030 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1031 struct rtl8366_smi *smi = &rtl->smi;
1032 char *buf = rtl->buf;
1033 int err;
1034
1035 if (val->port_vlan == 0 || val->port_vlan >= RTL8366S_NUM_VLANS)
1036 return -EINVAL;
1037
1038 memset(buf, '\0', sizeof(rtl->buf));
1039
1040 err = rtl8366s_get_vlan_4k(smi, val->port_vlan, &vlan4k);
1041 if (err)
1042 return err;
1043
1044 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1045 "VLAN %d: Ports: '", vlan4k.vid);
1046
1047 for (i = 0; i < RTL8366S_NUM_PORTS; i++) {
1048 if (!(vlan4k.member & (1 << i)))
1049 continue;
1050
1051 len += snprintf(buf + len, sizeof(rtl->buf) - len, "%d%s", i,
1052 (vlan4k.untag & (1 << i)) ? "" : "t");
1053 }
1054
1055 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1056 "', members=%04x, untag=%04x, fid=%u",
1057 vlan4k.member, vlan4k.untag, vlan4k.fid);
1058
1059 val->value.s = buf;
1060 val->len = len;
1061
1062 return 0;
1063 }
1064
1065 static int rtl8366s_sw_set_port_led(struct switch_dev *dev,
1066 const struct switch_attr *attr,
1067 struct switch_val *val)
1068 {
1069 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1070 u32 data;
1071 u32 mask;
1072 u32 reg;
1073
1074 if (val->port_vlan >= RTL8366S_NUM_PORTS ||
1075 (1 << val->port_vlan) == RTL8366S_PORT_UNKNOWN)
1076 return -EINVAL;
1077
1078 if (val->port_vlan == RTL8366S_PORT_NUM_CPU) {
1079 reg = RTL8366S_LED_BLINKRATE_REG;
1080 mask = 0xF << 4;
1081 data = val->value.i << 4;
1082 } else {
1083 reg = RTL8366S_LED_CTRL_REG;
1084 mask = 0xF << (val->port_vlan * 4),
1085 data = val->value.i << (val->port_vlan * 4);
1086 }
1087
1088 return rtl8366_smi_rmwr(smi, RTL8366S_LED_BLINKRATE_REG, mask, data);
1089 }
1090
1091 static int rtl8366s_sw_get_port_led(struct switch_dev *dev,
1092 const struct switch_attr *attr,
1093 struct switch_val *val)
1094 {
1095 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1096 u32 data = 0;
1097
1098 if (val->port_vlan >= RTL8366S_NUM_LEDGROUPS)
1099 return -EINVAL;
1100
1101 rtl8366_smi_read_reg(smi, RTL8366S_LED_CTRL_REG, &data);
1102 val->value.i = (data >> (val->port_vlan * 4)) & 0x000F;
1103
1104 return 0;
1105 }
1106
1107 static int rtl8366s_sw_reset_port_mibs(struct switch_dev *dev,
1108 const struct switch_attr *attr,
1109 struct switch_val *val)
1110 {
1111 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1112
1113 if (val->port_vlan >= RTL8366S_NUM_PORTS)
1114 return -EINVAL;
1115
1116
1117 return rtl8366_smi_rmwr(smi, RTL8366S_MIB_CTRL_REG,
1118 0, (1 << (val->port_vlan + 3)));
1119 }
1120
1121 static int rtl8366s_sw_get_port_mib(struct switch_dev *dev,
1122 const struct switch_attr *attr,
1123 struct switch_val *val)
1124 {
1125 struct rtl8366s *rtl = sw_to_rtl8366s(dev);
1126 struct rtl8366_smi *smi = &rtl->smi;
1127 int i, len = 0;
1128 unsigned long long counter = 0;
1129 char *buf = rtl->buf;
1130
1131 if (val->port_vlan >= RTL8366S_NUM_PORTS)
1132 return -EINVAL;
1133
1134 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1135 "Port %d MIB counters\n",
1136 val->port_vlan);
1137
1138 for (i = 0; i < ARRAY_SIZE(rtl8366s_mib_counters); ++i) {
1139 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1140 "%-36s: ", rtl8366s_mib_counters[i].name);
1141 if (!rtl8366_get_mib_counter(smi, i, val->port_vlan, &counter))
1142 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1143 "%llu\n", counter);
1144 else
1145 len += snprintf(buf + len, sizeof(rtl->buf) - len,
1146 "%s\n", "error");
1147 }
1148
1149 val->value.s = buf;
1150 val->len = len;
1151 return 0;
1152 }
1153
1154 static int rtl8366s_sw_get_vlan_ports(struct switch_dev *dev,
1155 struct switch_val *val)
1156 {
1157 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1158 struct switch_port *port;
1159 struct rtl8366_vlan_4k vlan4k;
1160 int i;
1161
1162 if (val->port_vlan == 0 || val->port_vlan >= RTL8366S_NUM_VLANS)
1163 return -EINVAL;
1164
1165 rtl8366s_get_vlan_4k(smi, val->port_vlan, &vlan4k);
1166
1167 port = &val->value.ports[0];
1168 val->len = 0;
1169 for (i = 0; i < RTL8366S_NUM_PORTS; i++) {
1170 if (!(vlan4k.member & BIT(i)))
1171 continue;
1172
1173 port->id = i;
1174 port->flags = (vlan4k.untag & BIT(i)) ?
1175 0 : BIT(SWITCH_PORT_FLAG_TAGGED);
1176 val->len++;
1177 port++;
1178 }
1179 return 0;
1180 }
1181
1182 static int rtl8366s_sw_set_vlan_ports(struct switch_dev *dev,
1183 struct switch_val *val)
1184 {
1185 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1186 struct switch_port *port;
1187 u32 member = 0;
1188 u32 untag = 0;
1189 int i;
1190
1191 if (val->port_vlan == 0 || val->port_vlan >= RTL8366S_NUM_VLANS)
1192 return -EINVAL;
1193
1194 port = &val->value.ports[0];
1195 for (i = 0; i < val->len; i++, port++) {
1196 member |= BIT(port->id);
1197
1198 if (!(port->flags & BIT(SWITCH_PORT_FLAG_TAGGED)))
1199 untag |= BIT(port->id);
1200 }
1201
1202 return rtl8366_set_vlan(smi, val->port_vlan, member, untag, 0);
1203 }
1204
1205 static int rtl8366s_sw_get_port_pvid(struct switch_dev *dev, int port, int *val)
1206 {
1207 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1208 return rtl8366_get_pvid(smi, port, val);
1209 }
1210
1211 static int rtl8366s_sw_set_port_pvid(struct switch_dev *dev, int port, int val)
1212 {
1213 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1214 return rtl8366_set_pvid(smi, port, val);
1215 }
1216
1217 static int rtl8366s_sw_reset_switch(struct switch_dev *dev)
1218 {
1219 struct rtl8366_smi *smi = sw_to_rtl8366_smi(dev);
1220 int err;
1221
1222 err = rtl8366s_reset_chip(smi);
1223 if (err)
1224 return err;
1225
1226 err = rtl8366s_hw_init(smi);
1227 if (err)
1228 return err;
1229
1230 return rtl8366_reset_vlan(smi);
1231 }
1232
1233 static struct switch_attr rtl8366s_globals[] = {
1234 {
1235 .type = SWITCH_TYPE_INT,
1236 .name = "enable_vlan",
1237 .description = "Enable VLAN mode",
1238 .set = rtl8366s_sw_set_vlan_enable,
1239 .get = rtl8366s_sw_get_vlan_enable,
1240 .max = 1,
1241 .ofs = 1
1242 }, {
1243 .type = SWITCH_TYPE_INT,
1244 .name = "enable_vlan4k",
1245 .description = "Enable VLAN 4K mode",
1246 .set = rtl8366s_sw_set_vlan_enable,
1247 .get = rtl8366s_sw_get_vlan_enable,
1248 .max = 1,
1249 .ofs = 2
1250 }, {
1251 .type = SWITCH_TYPE_INT,
1252 .name = "reset_mibs",
1253 .description = "Reset all MIB counters",
1254 .set = rtl8366s_sw_reset_mibs,
1255 .get = NULL,
1256 .max = 1
1257 }, {
1258 .type = SWITCH_TYPE_INT,
1259 .name = "blinkrate",
1260 .description = "Get/Set LED blinking rate (0 = 43ms, 1 = 84ms,"
1261 " 2 = 120ms, 3 = 170ms, 4 = 340ms, 5 = 670ms)",
1262 .set = rtl8366s_sw_set_blinkrate,
1263 .get = rtl8366s_sw_get_blinkrate,
1264 .max = 5
1265 },
1266 };
1267
1268 static struct switch_attr rtl8366s_port[] = {
1269 {
1270 .type = SWITCH_TYPE_STRING,
1271 .name = "link",
1272 .description = "Get port link information",
1273 .max = 1,
1274 .set = NULL,
1275 .get = rtl8366s_sw_get_port_link,
1276 }, {
1277 .type = SWITCH_TYPE_INT,
1278 .name = "reset_mib",
1279 .description = "Reset single port MIB counters",
1280 .max = 1,
1281 .set = rtl8366s_sw_reset_port_mibs,
1282 .get = NULL,
1283 }, {
1284 .type = SWITCH_TYPE_STRING,
1285 .name = "mib",
1286 .description = "Get MIB counters for port",
1287 .max = 33,
1288 .set = NULL,
1289 .get = rtl8366s_sw_get_port_mib,
1290 }, {
1291 .type = SWITCH_TYPE_INT,
1292 .name = "led",
1293 .description = "Get/Set port group (0 - 3) led mode (0 - 15)",
1294 .max = 15,
1295 .set = rtl8366s_sw_set_port_led,
1296 .get = rtl8366s_sw_get_port_led,
1297 },
1298 };
1299
1300 static struct switch_attr rtl8366s_vlan[] = {
1301 {
1302 .type = SWITCH_TYPE_STRING,
1303 .name = "info",
1304 .description = "Get vlan information",
1305 .max = 1,
1306 .set = NULL,
1307 .get = rtl8366s_sw_get_vlan_info,
1308 },
1309 };
1310
1311 /* template */
1312 static struct switch_dev rtl8366_switch_dev = {
1313 .name = "RTL8366S",
1314 .cpu_port = RTL8366S_PORT_NUM_CPU,
1315 .ports = RTL8366S_NUM_PORTS,
1316 .vlans = RTL8366S_NUM_VLANS,
1317 .attr_global = {
1318 .attr = rtl8366s_globals,
1319 .n_attr = ARRAY_SIZE(rtl8366s_globals),
1320 },
1321 .attr_port = {
1322 .attr = rtl8366s_port,
1323 .n_attr = ARRAY_SIZE(rtl8366s_port),
1324 },
1325 .attr_vlan = {
1326 .attr = rtl8366s_vlan,
1327 .n_attr = ARRAY_SIZE(rtl8366s_vlan),
1328 },
1329
1330 .get_vlan_ports = rtl8366s_sw_get_vlan_ports,
1331 .set_vlan_ports = rtl8366s_sw_set_vlan_ports,
1332 .get_port_pvid = rtl8366s_sw_get_port_pvid,
1333 .set_port_pvid = rtl8366s_sw_set_port_pvid,
1334 .reset_switch = rtl8366s_sw_reset_switch,
1335 };
1336
1337 static int rtl8366s_switch_init(struct rtl8366s *rtl)
1338 {
1339 struct switch_dev *dev = &rtl->dev;
1340 int err;
1341
1342 memcpy(dev, &rtl8366_switch_dev, sizeof(struct switch_dev));
1343 dev->priv = rtl;
1344 dev->devname = dev_name(rtl->parent);
1345
1346 err = register_switch(dev, NULL);
1347 if (err)
1348 dev_err(rtl->parent, "switch registration failed\n");
1349
1350 return err;
1351 }
1352
1353 static void rtl8366s_switch_cleanup(struct rtl8366s *rtl)
1354 {
1355 unregister_switch(&rtl->dev);
1356 }
1357
1358 static int rtl8366s_mii_read(struct mii_bus *bus, int addr, int reg)
1359 {
1360 struct rtl8366_smi *smi = bus->priv;
1361 u32 val = 0;
1362 int err;
1363
1364 err = rtl8366s_read_phy_reg(smi, addr, 0, reg, &val);
1365 if (err)
1366 return 0xffff;
1367
1368 return val;
1369 }
1370
1371 static int rtl8366s_mii_write(struct mii_bus *bus, int addr, int reg, u16 val)
1372 {
1373 struct rtl8366_smi *smi = bus->priv;
1374 u32 t;
1375 int err;
1376
1377 err = rtl8366s_write_phy_reg(smi, addr, 0, reg, val);
1378 /* flush write */
1379 (void) rtl8366s_read_phy_reg(smi, addr, 0, reg, &t);
1380
1381 return err;
1382 }
1383
1384 static int rtl8366s_mii_bus_match(struct mii_bus *bus)
1385 {
1386 return (bus->read == rtl8366s_mii_read &&
1387 bus->write == rtl8366s_mii_write);
1388 }
1389
1390 static int rtl8366s_setup(struct rtl8366s *rtl)
1391 {
1392 struct rtl8366_smi *smi = &rtl->smi;
1393 int ret;
1394
1395 rtl8366s_debugfs_init(rtl);
1396
1397 ret = rtl8366s_reset_chip(smi);
1398 if (ret)
1399 return ret;
1400
1401 ret = rtl8366s_hw_init(smi);
1402 return ret;
1403 }
1404
1405 static int rtl8366s_detect(struct rtl8366_smi *smi)
1406 {
1407 u32 chip_id = 0;
1408 u32 chip_ver = 0;
1409 int ret;
1410
1411 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_ID_REG, &chip_id);
1412 if (ret) {
1413 dev_err(smi->parent, "unable to read chip id\n");
1414 return ret;
1415 }
1416
1417 switch (chip_id) {
1418 case RTL8366S_CHIP_ID_8366:
1419 break;
1420 default:
1421 dev_err(smi->parent, "unknown chip id (%04x)\n", chip_id);
1422 return -ENODEV;
1423 }
1424
1425 ret = rtl8366_smi_read_reg(smi, RTL8366S_CHIP_VERSION_CTRL_REG,
1426 &chip_ver);
1427 if (ret) {
1428 dev_err(smi->parent, "unable to read chip version\n");
1429 return ret;
1430 }
1431
1432 dev_info(smi->parent, "RTL%04x ver. %u chip found\n",
1433 chip_id, chip_ver & RTL8366S_CHIP_VERSION_MASK);
1434
1435 return 0;
1436 }
1437
1438 static struct rtl8366_smi_ops rtl8366s_smi_ops = {
1439 .detect = rtl8366s_detect,
1440 .mii_read = rtl8366s_mii_read,
1441 .mii_write = rtl8366s_mii_write,
1442
1443 .get_vlan_mc = rtl8366s_get_vlan_mc,
1444 .set_vlan_mc = rtl8366s_set_vlan_mc,
1445 .get_vlan_4k = rtl8366s_get_vlan_4k,
1446 .set_vlan_4k = rtl8366s_set_vlan_4k,
1447 .get_mc_index = rtl8366s_get_mc_index,
1448 .set_mc_index = rtl8366s_set_mc_index,
1449 };
1450
1451 static int __init rtl8366s_probe(struct platform_device *pdev)
1452 {
1453 static int rtl8366_smi_version_printed;
1454 struct rtl8366s_platform_data *pdata;
1455 struct rtl8366s *rtl;
1456 struct rtl8366_smi *smi;
1457 int err;
1458
1459 if (!rtl8366_smi_version_printed++)
1460 printk(KERN_NOTICE RTL8366S_DRIVER_DESC
1461 " version " RTL8366S_DRIVER_VER"\n");
1462
1463 pdata = pdev->dev.platform_data;
1464 if (!pdata) {
1465 dev_err(&pdev->dev, "no platform data specified\n");
1466 err = -EINVAL;
1467 goto err_out;
1468 }
1469
1470 rtl = kzalloc(sizeof(*rtl), GFP_KERNEL);
1471 if (!rtl) {
1472 dev_err(&pdev->dev, "no memory for private data\n");
1473 err = -ENOMEM;
1474 goto err_out;
1475 }
1476
1477 rtl->parent = &pdev->dev;
1478
1479 smi = &rtl->smi;
1480 smi->parent = &pdev->dev;
1481 smi->gpio_sda = pdata->gpio_sda;
1482 smi->gpio_sck = pdata->gpio_sck;
1483 smi->ops = &rtl8366s_smi_ops;
1484 smi->cpu_port = RTL8366S_PORT_NUM_CPU;
1485 smi->num_ports = RTL8366S_NUM_PORTS;
1486 smi->num_vlan_mc = RTL8366S_NUM_VLANS;
1487
1488 err = rtl8366_smi_init(smi);
1489 if (err)
1490 goto err_free_rtl;
1491
1492 platform_set_drvdata(pdev, rtl);
1493
1494 err = rtl8366s_setup(rtl);
1495 if (err)
1496 goto err_clear_drvdata;
1497
1498 err = rtl8366s_switch_init(rtl);
1499 if (err)
1500 goto err_clear_drvdata;
1501
1502 return 0;
1503
1504 err_clear_drvdata:
1505 platform_set_drvdata(pdev, NULL);
1506 rtl8366_smi_cleanup(smi);
1507 err_free_rtl:
1508 kfree(rtl);
1509 err_out:
1510 return err;
1511 }
1512
1513 static int rtl8366s_phy_config_init(struct phy_device *phydev)
1514 {
1515 if (!rtl8366s_mii_bus_match(phydev->bus))
1516 return -EINVAL;
1517
1518 return 0;
1519 }
1520
1521 static int rtl8366s_phy_config_aneg(struct phy_device *phydev)
1522 {
1523 return 0;
1524 }
1525
1526 static struct phy_driver rtl8366s_phy_driver = {
1527 .phy_id = 0x001cc960,
1528 .name = "Realtek RTL8366S",
1529 .phy_id_mask = 0x1ffffff0,
1530 .features = PHY_GBIT_FEATURES,
1531 .config_aneg = rtl8366s_phy_config_aneg,
1532 .config_init = rtl8366s_phy_config_init,
1533 .read_status = genphy_read_status,
1534 .driver = {
1535 .owner = THIS_MODULE,
1536 },
1537 };
1538
1539 static int __devexit rtl8366s_remove(struct platform_device *pdev)
1540 {
1541 struct rtl8366s *rtl = platform_get_drvdata(pdev);
1542
1543 if (rtl) {
1544 rtl8366s_switch_cleanup(rtl);
1545 rtl8366s_debugfs_remove(rtl);
1546 platform_set_drvdata(pdev, NULL);
1547 rtl8366_smi_cleanup(&rtl->smi);
1548 kfree(rtl);
1549 }
1550
1551 return 0;
1552 }
1553
1554 static struct platform_driver rtl8366s_driver = {
1555 .driver = {
1556 .name = RTL8366S_DRIVER_NAME,
1557 .owner = THIS_MODULE,
1558 },
1559 .probe = rtl8366s_probe,
1560 .remove = __devexit_p(rtl8366s_remove),
1561 };
1562
1563 static int __init rtl8366s_module_init(void)
1564 {
1565 int ret;
1566 ret = platform_driver_register(&rtl8366s_driver);
1567 if (ret)
1568 return ret;
1569
1570 ret = phy_driver_register(&rtl8366s_phy_driver);
1571 if (ret)
1572 goto err_platform_unregister;
1573
1574 return 0;
1575
1576 err_platform_unregister:
1577 platform_driver_unregister(&rtl8366s_driver);
1578 return ret;
1579 }
1580 module_init(rtl8366s_module_init);
1581
1582 static void __exit rtl8366s_module_exit(void)
1583 {
1584 phy_driver_unregister(&rtl8366s_phy_driver);
1585 platform_driver_unregister(&rtl8366s_driver);
1586 }
1587 module_exit(rtl8366s_module_exit);
1588
1589 MODULE_DESCRIPTION(RTL8366S_DRIVER_DESC);
1590 MODULE_VERSION(RTL8366S_DRIVER_VER);
1591 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
1592 MODULE_AUTHOR("Antti Seppälä <a.seppala@gmail.com>");
1593 MODULE_LICENSE("GPL v2");
1594 MODULE_ALIAS("platform:" RTL8366S_DRIVER_NAME);
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