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b91f11d5811e625319342dd421d653073626fe5e
[openwrt/svn-archive/archive.git] / target / linux / generic / patches-2.6.30 / 941-ssb_update.patch
1 --- a/drivers/ssb/Kconfig
2 +++ b/drivers/ssb/Kconfig
3 @@ -66,6 +66,20 @@ config SSB_PCMCIAHOST
4
5 If unsure, say N
6
7 +config SSB_SDIOHOST_POSSIBLE
8 + bool
9 + depends on SSB && (MMC = y || MMC = SSB)
10 + default y
11 +
12 +config SSB_SDIOHOST
13 + bool "Support for SSB on SDIO-bus host"
14 + depends on SSB_SDIOHOST_POSSIBLE
15 + help
16 + Support for a Sonics Silicon Backplane on top
17 + of a SDIO device.
18 +
19 + If unsure, say N
20 +
21 config SSB_SILENT
22 bool "No SSB kernel messages"
23 depends on SSB && EMBEDDED
24 --- a/drivers/ssb/Makefile
25 +++ b/drivers/ssb/Makefile
26 @@ -6,6 +6,7 @@ ssb-$(CONFIG_SSB_SPROM) += sprom.o
27 # host support
28 ssb-$(CONFIG_SSB_PCIHOST) += pci.o pcihost_wrapper.o
29 ssb-$(CONFIG_SSB_PCMCIAHOST) += pcmcia.o
30 +ssb-$(CONFIG_SSB_SDIOHOST) += sdio.o
31
32 # built-in drivers
33 ssb-y += driver_chipcommon.o
34 --- a/drivers/ssb/b43_pci_bridge.c
35 +++ b/drivers/ssb/b43_pci_bridge.c
36 @@ -5,12 +5,13 @@
37 * because of its small size we include it in the SSB core
38 * instead of creating a standalone module.
39 *
40 - * Copyright 2007 Michael Buesch <mb@bu3sch.de>
41 + * Copyright 2007 Michael Buesch <m@bues.ch>
42 *
43 * Licensed under the GNU/GPL. See COPYING for details.
44 */
45
46 #include <linux/pci.h>
47 +#include <linux/module.h>
48 #include <linux/ssb/ssb.h>
49
50 #include "ssb_private.h"
51 @@ -24,6 +25,7 @@ static const struct pci_device_id b43_pc
52 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4312) },
53 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4315) },
54 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4318) },
55 + { PCI_DEVICE(PCI_VENDOR_ID_BCM_GVC, 0x4318) },
56 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4319) },
57 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4320) },
58 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4321) },
59 --- a/drivers/ssb/driver_chipcommon.c
60 +++ b/drivers/ssb/driver_chipcommon.c
61 @@ -3,7 +3,7 @@
62 * Broadcom ChipCommon core driver
63 *
64 * Copyright 2005, Broadcom Corporation
65 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
66 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
67 *
68 * Licensed under the GNU/GPL. See COPYING for details.
69 */
70 @@ -46,40 +46,66 @@ void ssb_chipco_set_clockmode(struct ssb
71 if (!ccdev)
72 return;
73 bus = ccdev->bus;
74 +
75 + /* We support SLOW only on 6..9 */
76 + if (ccdev->id.revision >= 10 && mode == SSB_CLKMODE_SLOW)
77 + mode = SSB_CLKMODE_DYNAMIC;
78 +
79 + if (cc->capabilities & SSB_CHIPCO_CAP_PMU)
80 + return; /* PMU controls clockmode, separated function needed */
81 + SSB_WARN_ON(ccdev->id.revision >= 20);
82 +
83 /* chipcommon cores prior to rev6 don't support dynamic clock control */
84 if (ccdev->id.revision < 6)
85 return;
86 - /* chipcommon cores rev10 are a whole new ball game */
87 +
88 + /* ChipCommon cores rev10+ need testing */
89 if (ccdev->id.revision >= 10)
90 return;
91 +
92 if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
93 return;
94
95 switch (mode) {
96 - case SSB_CLKMODE_SLOW:
97 + case SSB_CLKMODE_SLOW: /* For revs 6..9 only */
98 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
99 tmp |= SSB_CHIPCO_SLOWCLKCTL_FSLOW;
100 chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
101 break;
102 case SSB_CLKMODE_FAST:
103 - ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */
104 - tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
105 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
106 - tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL;
107 - chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
108 + if (ccdev->id.revision < 10) {
109 + ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */
110 + tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
111 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
112 + tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL;
113 + chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
114 + } else {
115 + chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
116 + (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) |
117 + SSB_CHIPCO_SYSCLKCTL_FORCEHT));
118 + /* udelay(150); TODO: not available in early init */
119 + }
120 break;
121 case SSB_CLKMODE_DYNAMIC:
122 - tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
123 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
124 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL;
125 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
126 - if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) != SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL)
127 - tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
128 - chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
129 -
130 - /* for dynamic control, we have to release our xtal_pu "force on" */
131 - if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL)
132 - ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0);
133 + if (ccdev->id.revision < 10) {
134 + tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
135 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
136 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL;
137 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
138 + if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) !=
139 + SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL)
140 + tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
141 + chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
142 +
143 + /* For dynamic control, we have to release our xtal_pu
144 + * "force on" */
145 + if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL)
146 + ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0);
147 + } else {
148 + chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
149 + (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) &
150 + ~SSB_CHIPCO_SYSCLKCTL_FORCEHT));
151 + }
152 break;
153 default:
154 SSB_WARN_ON(1);
155 @@ -209,6 +235,24 @@ static void chipco_powercontrol_init(str
156 }
157 }
158
159 +/* http://bcm-v4.sipsolutions.net/802.11/PmuFastPwrupDelay */
160 +static u16 pmu_fast_powerup_delay(struct ssb_chipcommon *cc)
161 +{
162 + struct ssb_bus *bus = cc->dev->bus;
163 +
164 + switch (bus->chip_id) {
165 + case 0x4312:
166 + case 0x4322:
167 + case 0x4328:
168 + return 7000;
169 + case 0x4325:
170 + /* TODO: */
171 + default:
172 + return 15000;
173 + }
174 +}
175 +
176 +/* http://bcm-v4.sipsolutions.net/802.11/ClkctlFastPwrupDelay */
177 static void calc_fast_powerup_delay(struct ssb_chipcommon *cc)
178 {
179 struct ssb_bus *bus = cc->dev->bus;
180 @@ -218,6 +262,12 @@ static void calc_fast_powerup_delay(stru
181
182 if (bus->bustype != SSB_BUSTYPE_PCI)
183 return;
184 +
185 + if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
186 + cc->fast_pwrup_delay = pmu_fast_powerup_delay(cc);
187 + return;
188 + }
189 +
190 if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
191 return;
192
193 @@ -233,6 +283,15 @@ void ssb_chipcommon_init(struct ssb_chip
194 {
195 if (!cc->dev)
196 return; /* We don't have a ChipCommon */
197 + if (cc->dev->id.revision >= 11)
198 + cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT);
199 + ssb_dprintk(KERN_INFO PFX "chipcommon status is 0x%x\n", cc->status);
200 +
201 + if (cc->dev->id.revision >= 20) {
202 + chipco_write32(cc, SSB_CHIPCO_GPIOPULLUP, 0);
203 + chipco_write32(cc, SSB_CHIPCO_GPIOPULLDOWN, 0);
204 + }
205 +
206 ssb_pmu_init(cc);
207 chipco_powercontrol_init(cc);
208 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
209 @@ -370,6 +429,7 @@ u32 ssb_chipco_gpio_control(struct ssb_c
210 {
211 return chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
212 }
213 +EXPORT_SYMBOL(ssb_chipco_gpio_control);
214
215 u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value)
216 {
217 --- a/drivers/ssb/driver_chipcommon_pmu.c
218 +++ b/drivers/ssb/driver_chipcommon_pmu.c
219 @@ -2,7 +2,7 @@
220 * Sonics Silicon Backplane
221 * Broadcom ChipCommon Power Management Unit driver
222 *
223 - * Copyright 2009, Michael Buesch <mb@bu3sch.de>
224 + * Copyright 2009, Michael Buesch <m@bues.ch>
225 * Copyright 2007, Broadcom Corporation
226 *
227 * Licensed under the GNU/GPL. See COPYING for details.
228 @@ -12,6 +12,9 @@
229 #include <linux/ssb/ssb_regs.h>
230 #include <linux/ssb/ssb_driver_chipcommon.h>
231 #include <linux/delay.h>
232 +#ifdef CONFIG_BCM47XX
233 +#include <asm/mach-bcm47xx/nvram.h>
234 +#endif
235
236 #include "ssb_private.h"
237
238 @@ -28,6 +31,21 @@ static void ssb_chipco_pll_write(struct
239 chipco_write32(cc, SSB_CHIPCO_PLLCTL_DATA, value);
240 }
241
242 +static void ssb_chipco_regctl_maskset(struct ssb_chipcommon *cc,
243 + u32 offset, u32 mask, u32 set)
244 +{
245 + u32 value;
246 +
247 + chipco_read32(cc, SSB_CHIPCO_REGCTL_ADDR);
248 + chipco_write32(cc, SSB_CHIPCO_REGCTL_ADDR, offset);
249 + chipco_read32(cc, SSB_CHIPCO_REGCTL_ADDR);
250 + value = chipco_read32(cc, SSB_CHIPCO_REGCTL_DATA);
251 + value &= mask;
252 + value |= set;
253 + chipco_write32(cc, SSB_CHIPCO_REGCTL_DATA, value);
254 + chipco_read32(cc, SSB_CHIPCO_REGCTL_DATA);
255 +}
256 +
257 struct pmu0_plltab_entry {
258 u16 freq; /* Crystal frequency in kHz.*/
259 u8 xf; /* Crystal frequency value for PMU control */
260 @@ -76,10 +94,6 @@ static void ssb_pmu0_pllinit_r0(struct s
261 u32 pmuctl, tmp, pllctl;
262 unsigned int i;
263
264 - if ((bus->chip_id == 0x5354) && !crystalfreq) {
265 - /* The 5354 crystal freq is 25MHz */
266 - crystalfreq = 25000;
267 - }
268 if (crystalfreq)
269 e = pmu0_plltab_find_entry(crystalfreq);
270 if (!e)
271 @@ -305,7 +319,11 @@ static void ssb_pmu_pll_init(struct ssb_
272 u32 crystalfreq = 0; /* in kHz. 0 = keep default freq. */
273
274 if (bus->bustype == SSB_BUSTYPE_SSB) {
275 - /* TODO: The user may override the crystal frequency. */
276 +#ifdef CONFIG_BCM47XX
277 + char buf[20];
278 + if (nvram_getenv("xtalfreq", buf, sizeof(buf)) >= 0)
279 + crystalfreq = simple_strtoul(buf, NULL, 0);
280 +#endif
281 }
282
283 switch (bus->chip_id) {
284 @@ -314,9 +332,19 @@ static void ssb_pmu_pll_init(struct ssb_
285 ssb_pmu1_pllinit_r0(cc, crystalfreq);
286 break;
287 case 0x4328:
288 + ssb_pmu0_pllinit_r0(cc, crystalfreq);
289 + break;
290 case 0x5354:
291 + if (crystalfreq == 0)
292 + crystalfreq = 25000;
293 ssb_pmu0_pllinit_r0(cc, crystalfreq);
294 break;
295 + case 0x4322:
296 + if (cc->pmu.rev == 2) {
297 + chipco_write32(cc, SSB_CHIPCO_PLLCTL_ADDR, 0x0000000A);
298 + chipco_write32(cc, SSB_CHIPCO_PLLCTL_DATA, 0x380005C0);
299 + }
300 + break;
301 default:
302 ssb_printk(KERN_ERR PFX
303 "ERROR: PLL init unknown for device %04X\n",
304 @@ -396,12 +424,15 @@ static void ssb_pmu_resources_init(struc
305 u32 min_msk = 0, max_msk = 0;
306 unsigned int i;
307 const struct pmu_res_updown_tab_entry *updown_tab = NULL;
308 - unsigned int updown_tab_size;
309 + unsigned int updown_tab_size = 0;
310 const struct pmu_res_depend_tab_entry *depend_tab = NULL;
311 - unsigned int depend_tab_size;
312 + unsigned int depend_tab_size = 0;
313
314 switch (bus->chip_id) {
315 case 0x4312:
316 + min_msk = 0xCBB;
317 + break;
318 + case 0x4322:
319 /* We keep the default settings:
320 * min_msk = 0xCBB
321 * max_msk = 0x7FFFF
322 @@ -480,9 +511,9 @@ static void ssb_pmu_resources_init(struc
323 chipco_write32(cc, SSB_CHIPCO_PMU_MAXRES_MSK, max_msk);
324 }
325
326 +/* http://bcm-v4.sipsolutions.net/802.11/SSB/PmuInit */
327 void ssb_pmu_init(struct ssb_chipcommon *cc)
328 {
329 - struct ssb_bus *bus = cc->dev->bus;
330 u32 pmucap;
331
332 if (!(cc->capabilities & SSB_CHIPCO_CAP_PMU))
333 @@ -494,15 +525,122 @@ void ssb_pmu_init(struct ssb_chipcommon
334 ssb_dprintk(KERN_DEBUG PFX "Found rev %u PMU (capabilities 0x%08X)\n",
335 cc->pmu.rev, pmucap);
336
337 - if (cc->pmu.rev >= 1) {
338 - if ((bus->chip_id == 0x4325) && (bus->chip_rev < 2)) {
339 - chipco_mask32(cc, SSB_CHIPCO_PMU_CTL,
340 - ~SSB_CHIPCO_PMU_CTL_NOILPONW);
341 - } else {
342 - chipco_set32(cc, SSB_CHIPCO_PMU_CTL,
343 - SSB_CHIPCO_PMU_CTL_NOILPONW);
344 - }
345 - }
346 + if (cc->pmu.rev == 1)
347 + chipco_mask32(cc, SSB_CHIPCO_PMU_CTL,
348 + ~SSB_CHIPCO_PMU_CTL_NOILPONW);
349 + else
350 + chipco_set32(cc, SSB_CHIPCO_PMU_CTL,
351 + SSB_CHIPCO_PMU_CTL_NOILPONW);
352 ssb_pmu_pll_init(cc);
353 ssb_pmu_resources_init(cc);
354 }
355 +
356 +void ssb_pmu_set_ldo_voltage(struct ssb_chipcommon *cc,
357 + enum ssb_pmu_ldo_volt_id id, u32 voltage)
358 +{
359 + struct ssb_bus *bus = cc->dev->bus;
360 + u32 addr, shift, mask;
361 +
362 + switch (bus->chip_id) {
363 + case 0x4328:
364 + case 0x5354:
365 + switch (id) {
366 + case LDO_VOLT1:
367 + addr = 2;
368 + shift = 25;
369 + mask = 0xF;
370 + break;
371 + case LDO_VOLT2:
372 + addr = 3;
373 + shift = 1;
374 + mask = 0xF;
375 + break;
376 + case LDO_VOLT3:
377 + addr = 3;
378 + shift = 9;
379 + mask = 0xF;
380 + break;
381 + case LDO_PAREF:
382 + addr = 3;
383 + shift = 17;
384 + mask = 0x3F;
385 + break;
386 + default:
387 + SSB_WARN_ON(1);
388 + return;
389 + }
390 + break;
391 + case 0x4312:
392 + if (SSB_WARN_ON(id != LDO_PAREF))
393 + return;
394 + addr = 0;
395 + shift = 21;
396 + mask = 0x3F;
397 + break;
398 + default:
399 + return;
400 + }
401 +
402 + ssb_chipco_regctl_maskset(cc, addr, ~(mask << shift),
403 + (voltage & mask) << shift);
404 +}
405 +
406 +void ssb_pmu_set_ldo_paref(struct ssb_chipcommon *cc, bool on)
407 +{
408 + struct ssb_bus *bus = cc->dev->bus;
409 + int ldo;
410 +
411 + switch (bus->chip_id) {
412 + case 0x4312:
413 + ldo = SSB_PMURES_4312_PA_REF_LDO;
414 + break;
415 + case 0x4328:
416 + ldo = SSB_PMURES_4328_PA_REF_LDO;
417 + break;
418 + case 0x5354:
419 + ldo = SSB_PMURES_5354_PA_REF_LDO;
420 + break;
421 + default:
422 + return;
423 + }
424 +
425 + if (on)
426 + chipco_set32(cc, SSB_CHIPCO_PMU_MINRES_MSK, 1 << ldo);
427 + else
428 + chipco_mask32(cc, SSB_CHIPCO_PMU_MINRES_MSK, ~(1 << ldo));
429 + chipco_read32(cc, SSB_CHIPCO_PMU_MINRES_MSK); //SPEC FIXME found via mmiotrace - dummy read?
430 +}
431 +
432 +EXPORT_SYMBOL(ssb_pmu_set_ldo_voltage);
433 +EXPORT_SYMBOL(ssb_pmu_set_ldo_paref);
434 +
435 +u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc)
436 +{
437 + struct ssb_bus *bus = cc->dev->bus;
438 +
439 + switch (bus->chip_id) {
440 + case 0x5354:
441 + /* 5354 chip uses a non programmable PLL of frequency 240MHz */
442 + return 240000000;
443 + default:
444 + ssb_printk(KERN_ERR PFX
445 + "ERROR: PMU cpu clock unknown for device %04X\n",
446 + bus->chip_id);
447 + return 0;
448 + }
449 +}
450 +
451 +u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc)
452 +{
453 + struct ssb_bus *bus = cc->dev->bus;
454 +
455 + switch (bus->chip_id) {
456 + case 0x5354:
457 + return 120000000;
458 + default:
459 + ssb_printk(KERN_ERR PFX
460 + "ERROR: PMU controlclock unknown for device %04X\n",
461 + bus->chip_id);
462 + return 0;
463 + }
464 +}
465 --- a/drivers/ssb/driver_gige.c
466 +++ b/drivers/ssb/driver_gige.c
467 @@ -3,7 +3,7 @@
468 * Broadcom Gigabit Ethernet core driver
469 *
470 * Copyright 2008, Broadcom Corporation
471 - * Copyright 2008, Michael Buesch <mb@bu3sch.de>
472 + * Copyright 2008, Michael Buesch <m@bues.ch>
473 *
474 * Licensed under the GNU/GPL. See COPYING for details.
475 */
476 @@ -12,6 +12,7 @@
477 #include <linux/ssb/ssb_driver_gige.h>
478 #include <linux/pci.h>
479 #include <linux/pci_regs.h>
480 +#include <linux/slab.h>
481
482
483 /*
484 @@ -105,8 +106,9 @@ void gige_pcicfg_write32(struct ssb_gige
485 gige_write32(dev, SSB_GIGE_PCICFG + offset, value);
486 }
487
488 -static int ssb_gige_pci_read_config(struct pci_bus *bus, unsigned int devfn,
489 - int reg, int size, u32 *val)
490 +static int __devinit ssb_gige_pci_read_config(struct pci_bus *bus,
491 + unsigned int devfn, int reg,
492 + int size, u32 *val)
493 {
494 struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
495 unsigned long flags;
496 @@ -135,8 +137,9 @@ static int ssb_gige_pci_read_config(stru
497 return PCIBIOS_SUCCESSFUL;
498 }
499
500 -static int ssb_gige_pci_write_config(struct pci_bus *bus, unsigned int devfn,
501 - int reg, int size, u32 val)
502 +static int __devinit ssb_gige_pci_write_config(struct pci_bus *bus,
503 + unsigned int devfn, int reg,
504 + int size, u32 val)
505 {
506 struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
507 unsigned long flags;
508 @@ -165,7 +168,8 @@ static int ssb_gige_pci_write_config(str
509 return PCIBIOS_SUCCESSFUL;
510 }
511
512 -static int ssb_gige_probe(struct ssb_device *sdev, const struct ssb_device_id *id)
513 +static int __devinit ssb_gige_probe(struct ssb_device *sdev,
514 + const struct ssb_device_id *id)
515 {
516 struct ssb_gige *dev;
517 u32 base, tmslow, tmshigh;
518 --- a/drivers/ssb/driver_mipscore.c
519 +++ b/drivers/ssb/driver_mipscore.c
520 @@ -3,7 +3,7 @@
521 * Broadcom MIPS core driver
522 *
523 * Copyright 2005, Broadcom Corporation
524 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
525 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
526 *
527 * Licensed under the GNU/GPL. See COPYING for details.
528 */
529 @@ -49,29 +49,54 @@ static const u32 ipsflag_irq_shift[] = {
530
531 static inline u32 ssb_irqflag(struct ssb_device *dev)
532 {
533 - return ssb_read32(dev, SSB_TPSFLAG) & SSB_TPSFLAG_BPFLAG;
534 + u32 tpsflag = ssb_read32(dev, SSB_TPSFLAG);
535 + if (tpsflag)
536 + return ssb_read32(dev, SSB_TPSFLAG) & SSB_TPSFLAG_BPFLAG;
537 + else
538 + /* not irq supported */
539 + return 0x3f;
540 +}
541 +
542 +static struct ssb_device *find_device(struct ssb_device *rdev, int irqflag)
543 +{
544 + struct ssb_bus *bus = rdev->bus;
545 + int i;
546 + for (i = 0; i < bus->nr_devices; i++) {
547 + struct ssb_device *dev;
548 + dev = &(bus->devices[i]);
549 + if (ssb_irqflag(dev) == irqflag)
550 + return dev;
551 + }
552 + return NULL;
553 }
554
555 /* Get the MIPS IRQ assignment for a specified device.
556 * If unassigned, 0 is returned.
557 + * If disabled, 5 is returned.
558 + * If not supported, 6 is returned.
559 */
560 unsigned int ssb_mips_irq(struct ssb_device *dev)
561 {
562 struct ssb_bus *bus = dev->bus;
563 + struct ssb_device *mdev = bus->mipscore.dev;
564 u32 irqflag;
565 u32 ipsflag;
566 u32 tmp;
567 unsigned int irq;
568
569 irqflag = ssb_irqflag(dev);
570 + if (irqflag == 0x3f)
571 + return 6;
572 ipsflag = ssb_read32(bus->mipscore.dev, SSB_IPSFLAG);
573 for (irq = 1; irq <= 4; irq++) {
574 tmp = ((ipsflag & ipsflag_irq_mask[irq]) >> ipsflag_irq_shift[irq]);
575 if (tmp == irqflag)
576 break;
577 }
578 - if (irq == 5)
579 - irq = 0;
580 + if (irq == 5) {
581 + if ((1 << irqflag) & ssb_read32(mdev, SSB_INTVEC))
582 + irq = 0;
583 + }
584
585 return irq;
586 }
587 @@ -97,25 +122,56 @@ static void set_irq(struct ssb_device *d
588 struct ssb_device *mdev = bus->mipscore.dev;
589 u32 irqflag = ssb_irqflag(dev);
590
591 + BUG_ON(oldirq == 6);
592 +
593 dev->irq = irq + 2;
594
595 - ssb_dprintk(KERN_INFO PFX
596 - "set_irq: core 0x%04x, irq %d => %d\n",
597 - dev->id.coreid, oldirq, irq);
598 /* clear the old irq */
599 if (oldirq == 0)
600 ssb_write32(mdev, SSB_INTVEC, (~(1 << irqflag) & ssb_read32(mdev, SSB_INTVEC)));
601 - else
602 + else if (oldirq != 5)
603 clear_irq(bus, oldirq);
604
605 /* assign the new one */
606 if (irq == 0) {
607 ssb_write32(mdev, SSB_INTVEC, ((1 << irqflag) | ssb_read32(mdev, SSB_INTVEC)));
608 } else {
609 + u32 ipsflag = ssb_read32(mdev, SSB_IPSFLAG);
610 + if ((ipsflag & ipsflag_irq_mask[irq]) != ipsflag_irq_mask[irq]) {
611 + u32 oldipsflag = (ipsflag & ipsflag_irq_mask[irq]) >> ipsflag_irq_shift[irq];
612 + struct ssb_device *olddev = find_device(dev, oldipsflag);
613 + if (olddev)
614 + set_irq(olddev, 0);
615 + }
616 irqflag <<= ipsflag_irq_shift[irq];
617 - irqflag |= (ssb_read32(mdev, SSB_IPSFLAG) & ~ipsflag_irq_mask[irq]);
618 + irqflag |= (ipsflag & ~ipsflag_irq_mask[irq]);
619 ssb_write32(mdev, SSB_IPSFLAG, irqflag);
620 }
621 + ssb_dprintk(KERN_INFO PFX
622 + "set_irq: core 0x%04x, irq %d => %d\n",
623 + dev->id.coreid, oldirq+2, irq+2);
624 +}
625 +
626 +static void print_irq(struct ssb_device *dev, unsigned int irq)
627 +{
628 + int i;
629 + static const char *irq_name[] = {"2(S)", "3", "4", "5", "6", "D", "I"};
630 + ssb_dprintk(KERN_INFO PFX
631 + "core 0x%04x, irq :", dev->id.coreid);
632 + for (i = 0; i <= 6; i++) {
633 + ssb_dprintk(" %s%s", irq_name[i], i==irq?"*":" ");
634 + }
635 + ssb_dprintk("\n");
636 +}
637 +
638 +static void dump_irq(struct ssb_bus *bus)
639 +{
640 + int i;
641 + for (i = 0; i < bus->nr_devices; i++) {
642 + struct ssb_device *dev;
643 + dev = &(bus->devices[i]);
644 + print_irq(dev, ssb_mips_irq(dev));
645 + }
646 }
647
648 static void ssb_mips_serial_init(struct ssb_mipscore *mcore)
649 @@ -152,6 +208,9 @@ u32 ssb_cpu_clock(struct ssb_mipscore *m
650 struct ssb_bus *bus = mcore->dev->bus;
651 u32 pll_type, n, m, rate = 0;
652
653 + if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
654 + return ssb_pmu_get_cpu_clock(&bus->chipco);
655 +
656 if (bus->extif.dev) {
657 ssb_extif_get_clockcontrol(&bus->extif, &pll_type, &n, &m);
658 } else if (bus->chipco.dev) {
659 @@ -197,17 +256,23 @@ void ssb_mipscore_init(struct ssb_mipsco
660
661 /* Assign IRQs to all cores on the bus, start with irq line 2, because serial usually takes 1 */
662 for (irq = 2, i = 0; i < bus->nr_devices; i++) {
663 + int mips_irq;
664 dev = &(bus->devices[i]);
665 - dev->irq = ssb_mips_irq(dev) + 2;
666 + mips_irq = ssb_mips_irq(dev);
667 + if (mips_irq > 4)
668 + dev->irq = 0;
669 + else
670 + dev->irq = mips_irq + 2;
671 + if (dev->irq > 5)
672 + continue;
673 switch (dev->id.coreid) {
674 case SSB_DEV_USB11_HOST:
675 /* shouldn't need a separate irq line for non-4710, most of them have a proper
676 * external usb controller on the pci */
677 if ((bus->chip_id == 0x4710) && (irq <= 4)) {
678 set_irq(dev, irq++);
679 - break;
680 }
681 - /* fallthrough */
682 + break;
683 case SSB_DEV_PCI:
684 case SSB_DEV_ETHERNET:
685 case SSB_DEV_ETHERNET_GBIT:
686 @@ -218,8 +283,14 @@ void ssb_mipscore_init(struct ssb_mipsco
687 set_irq(dev, irq++);
688 break;
689 }
690 + /* fallthrough */
691 + case SSB_DEV_EXTIF:
692 + set_irq(dev, 0);
693 + break;
694 }
695 }
696 + ssb_dprintk(KERN_INFO PFX "after irq reconfiguration\n");
697 + dump_irq(bus);
698
699 ssb_mips_serial_init(mcore);
700 ssb_mips_flash_detect(mcore);
701 --- a/drivers/ssb/driver_pcicore.c
702 +++ b/drivers/ssb/driver_pcicore.c
703 @@ -3,7 +3,7 @@
704 * Broadcom PCI-core driver
705 *
706 * Copyright 2005, Broadcom Corporation
707 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
708 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
709 *
710 * Licensed under the GNU/GPL. See COPYING for details.
711 */
712 @@ -15,6 +15,11 @@
713
714 #include "ssb_private.h"
715
716 +static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address);
717 +static void ssb_pcie_write(struct ssb_pcicore *pc, u32 address, u32 data);
718 +static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address);
719 +static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
720 + u8 address, u16 data);
721
722 static inline
723 u32 pcicore_read32(struct ssb_pcicore *pc, u16 offset)
724 @@ -69,7 +74,7 @@ static u32 get_cfgspace_addr(struct ssb_
725 u32 tmp;
726
727 /* We do only have one cardbus device behind the bridge. */
728 - if (pc->cardbusmode && (dev >= 1))
729 + if (pc->cardbusmode && (dev > 1))
730 goto out;
731
732 if (bus == 0) {
733 @@ -246,20 +251,12 @@ static struct pci_controller ssb_pcicore
734 .pci_ops = &ssb_pcicore_pciops,
735 .io_resource = &ssb_pcicore_io_resource,
736 .mem_resource = &ssb_pcicore_mem_resource,
737 - .mem_offset = 0x24000000,
738 };
739
740 -static u32 ssb_pcicore_pcibus_iobase = 0x100;
741 -static u32 ssb_pcicore_pcibus_membase = SSB_PCI_DMA;
742 -
743 /* This function is called when doing a pci_enable_device().
744 * We must first check if the device is a device on the PCI-core bridge. */
745 int ssb_pcicore_plat_dev_init(struct pci_dev *d)
746 {
747 - struct resource *res;
748 - int pos, size;
749 - u32 *base;
750 -
751 if (d->bus->ops != &ssb_pcicore_pciops) {
752 /* This is not a device on the PCI-core bridge. */
753 return -ENODEV;
754 @@ -268,27 +265,6 @@ int ssb_pcicore_plat_dev_init(struct pci
755 ssb_printk(KERN_INFO "PCI: Fixing up device %s\n",
756 pci_name(d));
757
758 - /* Fix up resource bases */
759 - for (pos = 0; pos < 6; pos++) {
760 - res = &d->resource[pos];
761 - if (res->flags & IORESOURCE_IO)
762 - base = &ssb_pcicore_pcibus_iobase;
763 - else
764 - base = &ssb_pcicore_pcibus_membase;
765 - res->flags |= IORESOURCE_PCI_FIXED;
766 - if (res->end) {
767 - size = res->end - res->start + 1;
768 - if (*base & (size - 1))
769 - *base = (*base + size) & ~(size - 1);
770 - res->start = *base;
771 - res->end = res->start + size - 1;
772 - *base += size;
773 - pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
774 - }
775 - /* Fix up PCI bridge BAR0 only */
776 - if (d->bus->number == 0 && PCI_SLOT(d->devfn) == 0)
777 - break;
778 - }
779 /* Fix up interrupt lines */
780 d->irq = ssb_mips_irq(extpci_core->dev) + 2;
781 pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
782 @@ -338,7 +314,7 @@ int ssb_pcicore_pcibios_map_irq(const st
783 return ssb_mips_irq(extpci_core->dev) + 2;
784 }
785
786 -static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
787 +static void __devinit ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
788 {
789 u32 val;
790
791 @@ -403,7 +379,7 @@ static void ssb_pcicore_init_hostmode(st
792 register_pci_controller(&ssb_pcicore_controller);
793 }
794
795 -static int pcicore_is_in_hostmode(struct ssb_pcicore *pc)
796 +static int __devinit pcicore_is_in_hostmode(struct ssb_pcicore *pc)
797 {
798 struct ssb_bus *bus = pc->dev->bus;
799 u16 chipid_top;
800 @@ -432,25 +408,137 @@ static int pcicore_is_in_hostmode(struct
801 }
802 #endif /* CONFIG_SSB_PCICORE_HOSTMODE */
803
804 +/**************************************************
805 + * Workarounds.
806 + **************************************************/
807 +
808 +static void __devinit ssb_pcicore_fix_sprom_core_index(struct ssb_pcicore *pc)
809 +{
810 + u16 tmp = pcicore_read16(pc, SSB_PCICORE_SPROM(0));
811 + if (((tmp & 0xF000) >> 12) != pc->dev->core_index) {
812 + tmp &= ~0xF000;
813 + tmp |= (pc->dev->core_index << 12);
814 + pcicore_write16(pc, SSB_PCICORE_SPROM(0), tmp);
815 + }
816 +}
817 +
818 +static u8 ssb_pcicore_polarity_workaround(struct ssb_pcicore *pc)
819 +{
820 + return (ssb_pcie_read(pc, 0x204) & 0x10) ? 0xC0 : 0x80;
821 +}
822 +
823 +static void ssb_pcicore_serdes_workaround(struct ssb_pcicore *pc)
824 +{
825 + const u8 serdes_pll_device = 0x1D;
826 + const u8 serdes_rx_device = 0x1F;
827 + u16 tmp;
828 +
829 + ssb_pcie_mdio_write(pc, serdes_rx_device, 1 /* Control */,
830 + ssb_pcicore_polarity_workaround(pc));
831 + tmp = ssb_pcie_mdio_read(pc, serdes_pll_device, 1 /* Control */);
832 + if (tmp & 0x4000)
833 + ssb_pcie_mdio_write(pc, serdes_pll_device, 1, tmp & ~0x4000);
834 +}
835 +
836 +static void ssb_pcicore_pci_setup_workarounds(struct ssb_pcicore *pc)
837 +{
838 + struct ssb_device *pdev = pc->dev;
839 + struct ssb_bus *bus = pdev->bus;
840 + u32 tmp;
841 +
842 + tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
843 + tmp |= SSB_PCICORE_SBTOPCI_PREF;
844 + tmp |= SSB_PCICORE_SBTOPCI_BURST;
845 + pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
846 +
847 + if (pdev->id.revision < 5) {
848 + tmp = ssb_read32(pdev, SSB_IMCFGLO);
849 + tmp &= ~SSB_IMCFGLO_SERTO;
850 + tmp |= 2;
851 + tmp &= ~SSB_IMCFGLO_REQTO;
852 + tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT;
853 + ssb_write32(pdev, SSB_IMCFGLO, tmp);
854 + ssb_commit_settings(bus);
855 + } else if (pdev->id.revision >= 11) {
856 + tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
857 + tmp |= SSB_PCICORE_SBTOPCI_MRM;
858 + pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
859 + }
860 +}
861 +
862 +static void ssb_pcicore_pcie_setup_workarounds(struct ssb_pcicore *pc)
863 +{
864 + u32 tmp;
865 + u8 rev = pc->dev->id.revision;
866 +
867 + if (rev == 0 || rev == 1) {
868 + /* TLP Workaround register. */
869 + tmp = ssb_pcie_read(pc, 0x4);
870 + tmp |= 0x8;
871 + ssb_pcie_write(pc, 0x4, tmp);
872 + }
873 + if (rev == 1) {
874 + /* DLLP Link Control register. */
875 + tmp = ssb_pcie_read(pc, 0x100);
876 + tmp |= 0x40;
877 + ssb_pcie_write(pc, 0x100, tmp);
878 + }
879 +
880 + if (rev == 0) {
881 + const u8 serdes_rx_device = 0x1F;
882 +
883 + ssb_pcie_mdio_write(pc, serdes_rx_device,
884 + 2 /* Timer */, 0x8128);
885 + ssb_pcie_mdio_write(pc, serdes_rx_device,
886 + 6 /* CDR */, 0x0100);
887 + ssb_pcie_mdio_write(pc, serdes_rx_device,
888 + 7 /* CDR BW */, 0x1466);
889 + } else if (rev == 3 || rev == 4 || rev == 5) {
890 + /* TODO: DLLP Power Management Threshold */
891 + ssb_pcicore_serdes_workaround(pc);
892 + /* TODO: ASPM */
893 + } else if (rev == 7) {
894 + /* TODO: No PLL down */
895 + }
896 +
897 + if (rev >= 6) {
898 + /* Miscellaneous Configuration Fixup */
899 + tmp = pcicore_read16(pc, SSB_PCICORE_SPROM(5));
900 + if (!(tmp & 0x8000))
901 + pcicore_write16(pc, SSB_PCICORE_SPROM(5),
902 + tmp | 0x8000);
903 + }
904 +}
905
906 /**************************************************
907 * Generic and Clientmode operation code.
908 **************************************************/
909
910 -static void ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)
911 +static void __devinit ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)
912 {
913 + struct ssb_device *pdev = pc->dev;
914 + struct ssb_bus *bus = pdev->bus;
915 +
916 + if (bus->bustype == SSB_BUSTYPE_PCI)
917 + ssb_pcicore_fix_sprom_core_index(pc);
918 +
919 /* Disable PCI interrupts. */
920 - ssb_write32(pc->dev, SSB_INTVEC, 0);
921 + ssb_write32(pdev, SSB_INTVEC, 0);
922 +
923 + /* Additional PCIe always once-executed workarounds */
924 + if (pc->dev->id.coreid == SSB_DEV_PCIE) {
925 + ssb_pcicore_serdes_workaround(pc);
926 + /* TODO: ASPM */
927 + /* TODO: Clock Request Update */
928 + }
929 }
930
931 -void ssb_pcicore_init(struct ssb_pcicore *pc)
932 +void __devinit ssb_pcicore_init(struct ssb_pcicore *pc)
933 {
934 struct ssb_device *dev = pc->dev;
935 - struct ssb_bus *bus;
936
937 if (!dev)
938 return;
939 - bus = dev->bus;
940 if (!ssb_device_is_enabled(dev))
941 ssb_device_enable(dev, 0);
942
943 @@ -475,58 +563,104 @@ static void ssb_pcie_write(struct ssb_pc
944 pcicore_write32(pc, 0x134, data);
945 }
946
947 -static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
948 - u8 address, u16 data)
949 +static void ssb_pcie_mdio_set_phy(struct ssb_pcicore *pc, u8 phy)
950 {
951 const u16 mdio_control = 0x128;
952 const u16 mdio_data = 0x12C;
953 u32 v;
954 int i;
955
956 + v = (1 << 30); /* Start of Transaction */
957 + v |= (1 << 28); /* Write Transaction */
958 + v |= (1 << 17); /* Turnaround */
959 + v |= (0x1F << 18);
960 + v |= (phy << 4);
961 + pcicore_write32(pc, mdio_data, v);
962 +
963 + udelay(10);
964 + for (i = 0; i < 200; i++) {
965 + v = pcicore_read32(pc, mdio_control);
966 + if (v & 0x100 /* Trans complete */)
967 + break;
968 + msleep(1);
969 + }
970 +}
971 +
972 +static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address)
973 +{
974 + const u16 mdio_control = 0x128;
975 + const u16 mdio_data = 0x12C;
976 + int max_retries = 10;
977 + u16 ret = 0;
978 + u32 v;
979 + int i;
980 +
981 v = 0x80; /* Enable Preamble Sequence */
982 v |= 0x2; /* MDIO Clock Divisor */
983 pcicore_write32(pc, mdio_control, v);
984
985 + if (pc->dev->id.revision >= 10) {
986 + max_retries = 200;
987 + ssb_pcie_mdio_set_phy(pc, device);
988 + }
989 +
990 v = (1 << 30); /* Start of Transaction */
991 - v |= (1 << 28); /* Write Transaction */
992 + v |= (1 << 29); /* Read Transaction */
993 v |= (1 << 17); /* Turnaround */
994 - v |= (u32)device << 22;
995 + if (pc->dev->id.revision < 10)
996 + v |= (u32)device << 22;
997 v |= (u32)address << 18;
998 - v |= data;
999 pcicore_write32(pc, mdio_data, v);
1000 /* Wait for the device to complete the transaction */
1001 udelay(10);
1002 - for (i = 0; i < 10; i++) {
1003 + for (i = 0; i < max_retries; i++) {
1004 v = pcicore_read32(pc, mdio_control);
1005 - if (v & 0x100 /* Trans complete */)
1006 + if (v & 0x100 /* Trans complete */) {
1007 + udelay(10);
1008 + ret = pcicore_read32(pc, mdio_data);
1009 break;
1010 + }
1011 msleep(1);
1012 }
1013 pcicore_write32(pc, mdio_control, 0);
1014 + return ret;
1015 }
1016
1017 -static void ssb_broadcast_value(struct ssb_device *dev,
1018 - u32 address, u32 data)
1019 +static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
1020 + u8 address, u16 data)
1021 {
1022 - /* This is used for both, PCI and ChipCommon core, so be careful. */
1023 - BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
1024 - BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
1025 + const u16 mdio_control = 0x128;
1026 + const u16 mdio_data = 0x12C;
1027 + int max_retries = 10;
1028 + u32 v;
1029 + int i;
1030
1031 - ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address);
1032 - ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */
1033 - ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data);
1034 - ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */
1035 -}
1036 + v = 0x80; /* Enable Preamble Sequence */
1037 + v |= 0x2; /* MDIO Clock Divisor */
1038 + pcicore_write32(pc, mdio_control, v);
1039
1040 -static void ssb_commit_settings(struct ssb_bus *bus)
1041 -{
1042 - struct ssb_device *dev;
1043 + if (pc->dev->id.revision >= 10) {
1044 + max_retries = 200;
1045 + ssb_pcie_mdio_set_phy(pc, device);
1046 + }
1047
1048 - dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
1049 - if (WARN_ON(!dev))
1050 - return;
1051 - /* This forces an update of the cached registers. */
1052 - ssb_broadcast_value(dev, 0xFD8, 0);
1053 + v = (1 << 30); /* Start of Transaction */
1054 + v |= (1 << 28); /* Write Transaction */
1055 + v |= (1 << 17); /* Turnaround */
1056 + if (pc->dev->id.revision < 10)
1057 + v |= (u32)device << 22;
1058 + v |= (u32)address << 18;
1059 + v |= data;
1060 + pcicore_write32(pc, mdio_data, v);
1061 + /* Wait for the device to complete the transaction */
1062 + udelay(10);
1063 + for (i = 0; i < max_retries; i++) {
1064 + v = pcicore_read32(pc, mdio_control);
1065 + if (v & 0x100 /* Trans complete */)
1066 + break;
1067 + msleep(1);
1068 + }
1069 + pcicore_write32(pc, mdio_control, 0);
1070 }
1071
1072 int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
1073 @@ -551,13 +685,13 @@ int ssb_pcicore_dev_irqvecs_enable(struc
1074 might_sleep_if(pdev->id.coreid != SSB_DEV_PCI);
1075
1076 /* Enable interrupts for this device. */
1077 - if (bus->host_pci &&
1078 - ((pdev->id.revision >= 6) || (pdev->id.coreid == SSB_DEV_PCIE))) {
1079 + if ((pdev->id.revision >= 6) || (pdev->id.coreid == SSB_DEV_PCIE)) {
1080 u32 coremask;
1081
1082 /* Calculate the "coremask" for the device. */
1083 coremask = (1 << dev->core_index);
1084
1085 + SSB_WARN_ON(bus->bustype != SSB_BUSTYPE_PCI);
1086 err = pci_read_config_dword(bus->host_pci, SSB_PCI_IRQMASK, &tmp);
1087 if (err)
1088 goto out;
1089 @@ -579,48 +713,10 @@ int ssb_pcicore_dev_irqvecs_enable(struc
1090 if (pc->setup_done)
1091 goto out;
1092 if (pdev->id.coreid == SSB_DEV_PCI) {
1093 - tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
1094 - tmp |= SSB_PCICORE_SBTOPCI_PREF;
1095 - tmp |= SSB_PCICORE_SBTOPCI_BURST;
1096 - pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
1097 -
1098 - if (pdev->id.revision < 5) {
1099 - tmp = ssb_read32(pdev, SSB_IMCFGLO);
1100 - tmp &= ~SSB_IMCFGLO_SERTO;
1101 - tmp |= 2;
1102 - tmp &= ~SSB_IMCFGLO_REQTO;
1103 - tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT;
1104 - ssb_write32(pdev, SSB_IMCFGLO, tmp);
1105 - ssb_commit_settings(bus);
1106 - } else if (pdev->id.revision >= 11) {
1107 - tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
1108 - tmp |= SSB_PCICORE_SBTOPCI_MRM;
1109 - pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
1110 - }
1111 + ssb_pcicore_pci_setup_workarounds(pc);
1112 } else {
1113 WARN_ON(pdev->id.coreid != SSB_DEV_PCIE);
1114 - //TODO: Better make defines for all these magic PCIE values.
1115 - if ((pdev->id.revision == 0) || (pdev->id.revision == 1)) {
1116 - /* TLP Workaround register. */
1117 - tmp = ssb_pcie_read(pc, 0x4);
1118 - tmp |= 0x8;
1119 - ssb_pcie_write(pc, 0x4, tmp);
1120 - }
1121 - if (pdev->id.revision == 0) {
1122 - const u8 serdes_rx_device = 0x1F;
1123 -
1124 - ssb_pcie_mdio_write(pc, serdes_rx_device,
1125 - 2 /* Timer */, 0x8128);
1126 - ssb_pcie_mdio_write(pc, serdes_rx_device,
1127 - 6 /* CDR */, 0x0100);
1128 - ssb_pcie_mdio_write(pc, serdes_rx_device,
1129 - 7 /* CDR BW */, 0x1466);
1130 - } else if (pdev->id.revision == 1) {
1131 - /* DLLP Link Control register. */
1132 - tmp = ssb_pcie_read(pc, 0x100);
1133 - tmp |= 0x40;
1134 - ssb_pcie_write(pc, 0x100, tmp);
1135 - }
1136 + ssb_pcicore_pcie_setup_workarounds(pc);
1137 }
1138 pc->setup_done = 1;
1139 out:
1140 --- a/drivers/ssb/main.c
1141 +++ b/drivers/ssb/main.c
1142 @@ -3,7 +3,7 @@
1143 * Subsystem core
1144 *
1145 * Copyright 2005, Broadcom Corporation
1146 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
1147 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
1148 *
1149 * Licensed under the GNU/GPL. See COPYING for details.
1150 */
1151 @@ -12,11 +12,14 @@
1152
1153 #include <linux/delay.h>
1154 #include <linux/io.h>
1155 +#include <linux/module.h>
1156 #include <linux/ssb/ssb.h>
1157 #include <linux/ssb/ssb_regs.h>
1158 #include <linux/ssb/ssb_driver_gige.h>
1159 #include <linux/dma-mapping.h>
1160 #include <linux/pci.h>
1161 +#include <linux/mmc/sdio_func.h>
1162 +#include <linux/slab.h>
1163
1164 #include <pcmcia/cs_types.h>
1165 #include <pcmcia/cs.h>
1166 @@ -88,6 +91,25 @@ found:
1167 }
1168 #endif /* CONFIG_SSB_PCMCIAHOST */
1169
1170 +#ifdef CONFIG_SSB_SDIOHOST
1171 +struct ssb_bus *ssb_sdio_func_to_bus(struct sdio_func *func)
1172 +{
1173 + struct ssb_bus *bus;
1174 +
1175 + ssb_buses_lock();
1176 + list_for_each_entry(bus, &buses, list) {
1177 + if (bus->bustype == SSB_BUSTYPE_SDIO &&
1178 + bus->host_sdio == func)
1179 + goto found;
1180 + }
1181 + bus = NULL;
1182 +found:
1183 + ssb_buses_unlock();
1184 +
1185 + return bus;
1186 +}
1187 +#endif /* CONFIG_SSB_SDIOHOST */
1188 +
1189 int ssb_for_each_bus_call(unsigned long data,
1190 int (*func)(struct ssb_bus *bus, unsigned long data))
1191 {
1192 @@ -190,90 +212,78 @@ int ssb_bus_suspend(struct ssb_bus *bus)
1193 EXPORT_SYMBOL(ssb_bus_suspend);
1194
1195 #ifdef CONFIG_SSB_SPROM
1196 -int ssb_devices_freeze(struct ssb_bus *bus)
1197 +/** ssb_devices_freeze - Freeze all devices on the bus.
1198 + *
1199 + * After freezing no device driver will be handling a device
1200 + * on this bus anymore. ssb_devices_thaw() must be called after
1201 + * a successful freeze to reactivate the devices.
1202 + *
1203 + * @bus: The bus.
1204 + * @ctx: Context structure. Pass this to ssb_devices_thaw().
1205 + */
1206 +int ssb_devices_freeze(struct ssb_bus *bus, struct ssb_freeze_context *ctx)
1207 {
1208 - struct ssb_device *dev;
1209 - struct ssb_driver *drv;
1210 - int err = 0;
1211 - int i;
1212 - pm_message_t state = PMSG_FREEZE;
1213 + struct ssb_device *sdev;
1214 + struct ssb_driver *sdrv;
1215 + unsigned int i;
1216 +
1217 + memset(ctx, 0, sizeof(*ctx));
1218 + ctx->bus = bus;
1219 + SSB_WARN_ON(bus->nr_devices > ARRAY_SIZE(ctx->device_frozen));
1220
1221 - /* First check that we are capable to freeze all devices. */
1222 for (i = 0; i < bus->nr_devices; i++) {
1223 - dev = &(bus->devices[i]);
1224 - if (!dev->dev ||
1225 - !dev->dev->driver ||
1226 - !device_is_registered(dev->dev))
1227 - continue;
1228 - drv = drv_to_ssb_drv(dev->dev->driver);
1229 - if (!drv)
1230 + sdev = ssb_device_get(&bus->devices[i]);
1231 +
1232 + if (!sdev->dev || !sdev->dev->driver ||
1233 + !device_is_registered(sdev->dev)) {
1234 + ssb_device_put(sdev);
1235 continue;
1236 - if (!drv->suspend) {
1237 - /* Nope, can't suspend this one. */
1238 - return -EOPNOTSUPP;
1239 }
1240 - }
1241 - /* Now suspend all devices */
1242 - for (i = 0; i < bus->nr_devices; i++) {
1243 - dev = &(bus->devices[i]);
1244 - if (!dev->dev ||
1245 - !dev->dev->driver ||
1246 - !device_is_registered(dev->dev))
1247 - continue;
1248 - drv = drv_to_ssb_drv(dev->dev->driver);
1249 - if (!drv)
1250 + sdrv = drv_to_ssb_drv(sdev->dev->driver);
1251 + if (SSB_WARN_ON(!sdrv->remove))
1252 continue;
1253 - err = drv->suspend(dev, state);
1254 - if (err) {
1255 - ssb_printk(KERN_ERR PFX "Failed to freeze device %s\n",
1256 - dev_name(dev->dev));
1257 - goto err_unwind;
1258 - }
1259 + sdrv->remove(sdev);
1260 + ctx->device_frozen[i] = 1;
1261 }
1262
1263 return 0;
1264 -err_unwind:
1265 - for (i--; i >= 0; i--) {
1266 - dev = &(bus->devices[i]);
1267 - if (!dev->dev ||
1268 - !dev->dev->driver ||
1269 - !device_is_registered(dev->dev))
1270 - continue;
1271 - drv = drv_to_ssb_drv(dev->dev->driver);
1272 - if (!drv)
1273 - continue;
1274 - if (drv->resume)
1275 - drv->resume(dev);
1276 - }
1277 - return err;
1278 }
1279
1280 -int ssb_devices_thaw(struct ssb_bus *bus)
1281 +/** ssb_devices_thaw - Unfreeze all devices on the bus.
1282 + *
1283 + * This will re-attach the device drivers and re-init the devices.
1284 + *
1285 + * @ctx: The context structure from ssb_devices_freeze()
1286 + */
1287 +int ssb_devices_thaw(struct ssb_freeze_context *ctx)
1288 {
1289 - struct ssb_device *dev;
1290 - struct ssb_driver *drv;
1291 - int err;
1292 - int i;
1293 + struct ssb_bus *bus = ctx->bus;
1294 + struct ssb_device *sdev;
1295 + struct ssb_driver *sdrv;
1296 + unsigned int i;
1297 + int err, result = 0;
1298
1299 for (i = 0; i < bus->nr_devices; i++) {
1300 - dev = &(bus->devices[i]);
1301 - if (!dev->dev ||
1302 - !dev->dev->driver ||
1303 - !device_is_registered(dev->dev))
1304 + if (!ctx->device_frozen[i])
1305 continue;
1306 - drv = drv_to_ssb_drv(dev->dev->driver);
1307 - if (!drv)
1308 + sdev = &bus->devices[i];
1309 +
1310 + if (SSB_WARN_ON(!sdev->dev || !sdev->dev->driver))
1311 continue;
1312 - if (SSB_WARN_ON(!drv->resume))
1313 + sdrv = drv_to_ssb_drv(sdev->dev->driver);
1314 + if (SSB_WARN_ON(!sdrv || !sdrv->probe))
1315 continue;
1316 - err = drv->resume(dev);
1317 +
1318 + err = sdrv->probe(sdev, &sdev->id);
1319 if (err) {
1320 ssb_printk(KERN_ERR PFX "Failed to thaw device %s\n",
1321 - dev_name(dev->dev));
1322 + dev_name(sdev->dev));
1323 + result = err;
1324 }
1325 + ssb_device_put(sdev);
1326 }
1327
1328 - return 0;
1329 + return result;
1330 }
1331 #endif /* CONFIG_SSB_SPROM */
1332
1333 @@ -360,6 +370,35 @@ static int ssb_device_uevent(struct devi
1334 ssb_dev->id.revision);
1335 }
1336
1337 +#define ssb_config_attr(attrib, field, format_string) \
1338 +static ssize_t \
1339 +attrib##_show(struct device *dev, struct device_attribute *attr, char *buf) \
1340 +{ \
1341 + return sprintf(buf, format_string, dev_to_ssb_dev(dev)->field); \
1342 +}
1343 +
1344 +ssb_config_attr(core_num, core_index, "%u\n")
1345 +ssb_config_attr(coreid, id.coreid, "0x%04x\n")
1346 +ssb_config_attr(vendor, id.vendor, "0x%04x\n")
1347 +ssb_config_attr(revision, id.revision, "%u\n")
1348 +ssb_config_attr(irq, irq, "%u\n")
1349 +static ssize_t
1350 +name_show(struct device *dev, struct device_attribute *attr, char *buf)
1351 +{
1352 + return sprintf(buf, "%s\n",
1353 + ssb_core_name(dev_to_ssb_dev(dev)->id.coreid));
1354 +}
1355 +
1356 +static struct device_attribute ssb_device_attrs[] = {
1357 + __ATTR_RO(name),
1358 + __ATTR_RO(core_num),
1359 + __ATTR_RO(coreid),
1360 + __ATTR_RO(vendor),
1361 + __ATTR_RO(revision),
1362 + __ATTR_RO(irq),
1363 + __ATTR_NULL,
1364 +};
1365 +
1366 static struct bus_type ssb_bustype = {
1367 .name = "ssb",
1368 .match = ssb_bus_match,
1369 @@ -369,6 +408,7 @@ static struct bus_type ssb_bustype = {
1370 .suspend = ssb_device_suspend,
1371 .resume = ssb_device_resume,
1372 .uevent = ssb_device_uevent,
1373 + .dev_attrs = ssb_device_attrs,
1374 };
1375
1376 static void ssb_buses_lock(void)
1377 @@ -461,6 +501,7 @@ static int ssb_devices_register(struct s
1378 #ifdef CONFIG_SSB_PCIHOST
1379 sdev->irq = bus->host_pci->irq;
1380 dev->parent = &bus->host_pci->dev;
1381 + sdev->dma_dev = dev->parent;
1382 #endif
1383 break;
1384 case SSB_BUSTYPE_PCMCIA:
1385 @@ -469,8 +510,14 @@ static int ssb_devices_register(struct s
1386 dev->parent = &bus->host_pcmcia->dev;
1387 #endif
1388 break;
1389 + case SSB_BUSTYPE_SDIO:
1390 +#ifdef CONFIG_SSB_SDIOHOST
1391 + dev->parent = &bus->host_sdio->dev;
1392 +#endif
1393 + break;
1394 case SSB_BUSTYPE_SSB:
1395 dev->dma_mask = &dev->coherent_dma_mask;
1396 + sdev->dma_dev = dev;
1397 break;
1398 }
1399
1400 @@ -497,7 +544,7 @@ error:
1401 }
1402
1403 /* Needs ssb_buses_lock() */
1404 -static int ssb_attach_queued_buses(void)
1405 +static int __devinit ssb_attach_queued_buses(void)
1406 {
1407 struct ssb_bus *bus, *n;
1408 int err = 0;
1409 @@ -708,9 +755,9 @@ out:
1410 return err;
1411 }
1412
1413 -static int ssb_bus_register(struct ssb_bus *bus,
1414 - ssb_invariants_func_t get_invariants,
1415 - unsigned long baseaddr)
1416 +static int __devinit ssb_bus_register(struct ssb_bus *bus,
1417 + ssb_invariants_func_t get_invariants,
1418 + unsigned long baseaddr)
1419 {
1420 int err;
1421
1422 @@ -724,12 +771,18 @@ static int ssb_bus_register(struct ssb_b
1423 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
1424 if (err)
1425 goto out;
1426 +
1427 + /* Init SDIO-host device (if any), before the scan */
1428 + err = ssb_sdio_init(bus);
1429 + if (err)
1430 + goto err_disable_xtal;
1431 +
1432 ssb_buses_lock();
1433 bus->busnumber = next_busnumber;
1434 /* Scan for devices (cores) */
1435 err = ssb_bus_scan(bus, baseaddr);
1436 if (err)
1437 - goto err_disable_xtal;
1438 + goto err_sdio_exit;
1439
1440 /* Init PCI-host device (if any) */
1441 err = ssb_pci_init(bus);
1442 @@ -776,6 +829,8 @@ err_pci_exit:
1443 ssb_pci_exit(bus);
1444 err_unmap:
1445 ssb_iounmap(bus);
1446 +err_sdio_exit:
1447 + ssb_sdio_exit(bus);
1448 err_disable_xtal:
1449 ssb_buses_unlock();
1450 ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
1451 @@ -783,8 +838,8 @@ err_disable_xtal:
1452 }
1453
1454 #ifdef CONFIG_SSB_PCIHOST
1455 -int ssb_bus_pcibus_register(struct ssb_bus *bus,
1456 - struct pci_dev *host_pci)
1457 +int __devinit ssb_bus_pcibus_register(struct ssb_bus *bus,
1458 + struct pci_dev *host_pci)
1459 {
1460 int err;
1461
1462 @@ -796,6 +851,9 @@ int ssb_bus_pcibus_register(struct ssb_b
1463 if (!err) {
1464 ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
1465 "PCI device %s\n", dev_name(&host_pci->dev));
1466 + } else {
1467 + ssb_printk(KERN_ERR PFX "Failed to register PCI version"
1468 + " of SSB with error %d\n", err);
1469 }
1470
1471 return err;
1472 @@ -804,9 +862,9 @@ EXPORT_SYMBOL(ssb_bus_pcibus_register);
1473 #endif /* CONFIG_SSB_PCIHOST */
1474
1475 #ifdef CONFIG_SSB_PCMCIAHOST
1476 -int ssb_bus_pcmciabus_register(struct ssb_bus *bus,
1477 - struct pcmcia_device *pcmcia_dev,
1478 - unsigned long baseaddr)
1479 +int __devinit ssb_bus_pcmciabus_register(struct ssb_bus *bus,
1480 + struct pcmcia_device *pcmcia_dev,
1481 + unsigned long baseaddr)
1482 {
1483 int err;
1484
1485 @@ -825,9 +883,32 @@ int ssb_bus_pcmciabus_register(struct ss
1486 EXPORT_SYMBOL(ssb_bus_pcmciabus_register);
1487 #endif /* CONFIG_SSB_PCMCIAHOST */
1488
1489 -int ssb_bus_ssbbus_register(struct ssb_bus *bus,
1490 - unsigned long baseaddr,
1491 - ssb_invariants_func_t get_invariants)
1492 +#ifdef CONFIG_SSB_SDIOHOST
1493 +int __devinit ssb_bus_sdiobus_register(struct ssb_bus *bus,
1494 + struct sdio_func *func,
1495 + unsigned int quirks)
1496 +{
1497 + int err;
1498 +
1499 + bus->bustype = SSB_BUSTYPE_SDIO;
1500 + bus->host_sdio = func;
1501 + bus->ops = &ssb_sdio_ops;
1502 + bus->quirks = quirks;
1503 +
1504 + err = ssb_bus_register(bus, ssb_sdio_get_invariants, ~0);
1505 + if (!err) {
1506 + ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
1507 + "SDIO device %s\n", sdio_func_id(func));
1508 + }
1509 +
1510 + return err;
1511 +}
1512 +EXPORT_SYMBOL(ssb_bus_sdiobus_register);
1513 +#endif /* CONFIG_SSB_PCMCIAHOST */
1514 +
1515 +int __devinit ssb_bus_ssbbus_register(struct ssb_bus *bus,
1516 + unsigned long baseaddr,
1517 + ssb_invariants_func_t get_invariants)
1518 {
1519 int err;
1520
1521 @@ -908,8 +989,8 @@ u32 ssb_calc_clock_rate(u32 plltype, u32
1522 switch (plltype) {
1523 case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
1524 if (m & SSB_CHIPCO_CLK_T6_MMASK)
1525 - return SSB_CHIPCO_CLK_T6_M0;
1526 - return SSB_CHIPCO_CLK_T6_M1;
1527 + return SSB_CHIPCO_CLK_T6_M1;
1528 + return SSB_CHIPCO_CLK_T6_M0;
1529 case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
1530 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
1531 case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
1532 @@ -999,6 +1080,9 @@ u32 ssb_clockspeed(struct ssb_bus *bus)
1533 u32 plltype;
1534 u32 clkctl_n, clkctl_m;
1535
1536 + if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
1537 + return ssb_pmu_get_controlclock(&bus->chipco);
1538 +
1539 if (ssb_extif_available(&bus->extif))
1540 ssb_extif_get_clockcontrol(&bus->extif, &plltype,
1541 &clkctl_n, &clkctl_m);
1542 @@ -1024,23 +1108,22 @@ static u32 ssb_tmslow_reject_bitmask(str
1543 {
1544 u32 rev = ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_SSBREV;
1545
1546 - /* The REJECT bit changed position in TMSLOW between
1547 - * Backplane revisions. */
1548 + /* The REJECT bit seems to be different for Backplane rev 2.3 */
1549 switch (rev) {
1550 case SSB_IDLOW_SSBREV_22:
1551 - return SSB_TMSLOW_REJECT_22;
1552 + case SSB_IDLOW_SSBREV_24:
1553 + case SSB_IDLOW_SSBREV_26:
1554 + return SSB_TMSLOW_REJECT;
1555 case SSB_IDLOW_SSBREV_23:
1556 return SSB_TMSLOW_REJECT_23;
1557 - case SSB_IDLOW_SSBREV_24: /* TODO - find the proper REJECT bits */
1558 - case SSB_IDLOW_SSBREV_25: /* same here */
1559 - case SSB_IDLOW_SSBREV_26: /* same here */
1560 + case SSB_IDLOW_SSBREV_25: /* TODO - find the proper REJECT bit */
1561 case SSB_IDLOW_SSBREV_27: /* same here */
1562 - return SSB_TMSLOW_REJECT_23; /* this is a guess */
1563 + return SSB_TMSLOW_REJECT; /* this is a guess */
1564 default:
1565 printk(KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
1566 WARN_ON(1);
1567 }
1568 - return (SSB_TMSLOW_REJECT_22 | SSB_TMSLOW_REJECT_23);
1569 + return (SSB_TMSLOW_REJECT | SSB_TMSLOW_REJECT_23);
1570 }
1571
1572 int ssb_device_is_enabled(struct ssb_device *dev)
1573 @@ -1099,10 +1182,10 @@ void ssb_device_enable(struct ssb_device
1574 }
1575 EXPORT_SYMBOL(ssb_device_enable);
1576
1577 -/* Wait for a bit in a register to get set or unset.
1578 +/* Wait for bitmask in a register to get set or cleared.
1579 * timeout is in units of ten-microseconds */
1580 -static int ssb_wait_bit(struct ssb_device *dev, u16 reg, u32 bitmask,
1581 - int timeout, int set)
1582 +static int ssb_wait_bits(struct ssb_device *dev, u16 reg, u32 bitmask,
1583 + int timeout, int set)
1584 {
1585 int i;
1586 u32 val;
1587 @@ -1110,7 +1193,7 @@ static int ssb_wait_bit(struct ssb_devic
1588 for (i = 0; i < timeout; i++) {
1589 val = ssb_read32(dev, reg);
1590 if (set) {
1591 - if (val & bitmask)
1592 + if ((val & bitmask) == bitmask)
1593 return 0;
1594 } else {
1595 if (!(val & bitmask))
1596 @@ -1127,20 +1210,38 @@ static int ssb_wait_bit(struct ssb_devic
1597
1598 void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags)
1599 {
1600 - u32 reject;
1601 + u32 reject, val;
1602
1603 if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_RESET)
1604 return;
1605
1606 reject = ssb_tmslow_reject_bitmask(dev);
1607 - ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK);
1608 - ssb_wait_bit(dev, SSB_TMSLOW, reject, 1000, 1);
1609 - ssb_wait_bit(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
1610 - ssb_write32(dev, SSB_TMSLOW,
1611 - SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
1612 - reject | SSB_TMSLOW_RESET |
1613 - core_specific_flags);
1614 - ssb_flush_tmslow(dev);
1615 +
1616 + if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_CLOCK) {
1617 + ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK);
1618 + ssb_wait_bits(dev, SSB_TMSLOW, reject, 1000, 1);
1619 + ssb_wait_bits(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
1620 +
1621 + if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
1622 + val = ssb_read32(dev, SSB_IMSTATE);
1623 + val |= SSB_IMSTATE_REJECT;
1624 + ssb_write32(dev, SSB_IMSTATE, val);
1625 + ssb_wait_bits(dev, SSB_IMSTATE, SSB_IMSTATE_BUSY, 1000,
1626 + 0);
1627 + }
1628 +
1629 + ssb_write32(dev, SSB_TMSLOW,
1630 + SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
1631 + reject | SSB_TMSLOW_RESET |
1632 + core_specific_flags);
1633 + ssb_flush_tmslow(dev);
1634 +
1635 + if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
1636 + val = ssb_read32(dev, SSB_IMSTATE);
1637 + val &= ~SSB_IMSTATE_REJECT;
1638 + ssb_write32(dev, SSB_IMSTATE, val);
1639 + }
1640 + }
1641
1642 ssb_write32(dev, SSB_TMSLOW,
1643 reject | SSB_TMSLOW_RESET |
1644 @@ -1149,13 +1250,34 @@ void ssb_device_disable(struct ssb_devic
1645 }
1646 EXPORT_SYMBOL(ssb_device_disable);
1647
1648 +/* Some chipsets need routing known for PCIe and 64-bit DMA */
1649 +static bool ssb_dma_translation_special_bit(struct ssb_device *dev)
1650 +{
1651 + u16 chip_id = dev->bus->chip_id;
1652 +
1653 + if (dev->id.coreid == SSB_DEV_80211) {
1654 + return (chip_id == 0x4322 || chip_id == 43221 ||
1655 + chip_id == 43231 || chip_id == 43222);
1656 + }
1657 +
1658 + return 0;
1659 +}
1660 +
1661 u32 ssb_dma_translation(struct ssb_device *dev)
1662 {
1663 switch (dev->bus->bustype) {
1664 case SSB_BUSTYPE_SSB:
1665 return 0;
1666 case SSB_BUSTYPE_PCI:
1667 - return SSB_PCI_DMA;
1668 + if (dev->bus->host_pci->is_pcie &&
1669 + ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_DMA64) {
1670 + return SSB_PCIE_DMA_H32;
1671 + } else {
1672 + if (ssb_dma_translation_special_bit(dev))
1673 + return SSB_PCIE_DMA_H32;
1674 + else
1675 + return SSB_PCI_DMA;
1676 + }
1677 default:
1678 __ssb_dma_not_implemented(dev);
1679 }
1680 @@ -1272,20 +1394,20 @@ EXPORT_SYMBOL(ssb_bus_may_powerdown);
1681
1682 int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl)
1683 {
1684 - struct ssb_chipcommon *cc;
1685 int err;
1686 enum ssb_clkmode mode;
1687
1688 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
1689 if (err)
1690 goto error;
1691 - cc = &bus->chipco;
1692 - mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
1693 - ssb_chipco_set_clockmode(cc, mode);
1694
1695 #ifdef CONFIG_SSB_DEBUG
1696 bus->powered_up = 1;
1697 #endif
1698 +
1699 + mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
1700 + ssb_chipco_set_clockmode(&bus->chipco, mode);
1701 +
1702 return 0;
1703 error:
1704 ssb_printk(KERN_ERR PFX "Bus powerup failed\n");
1705 @@ -1293,6 +1415,37 @@ error:
1706 }
1707 EXPORT_SYMBOL(ssb_bus_powerup);
1708
1709 +static void ssb_broadcast_value(struct ssb_device *dev,
1710 + u32 address, u32 data)
1711 +{
1712 +#ifdef CONFIG_SSB_DRIVER_PCICORE
1713 + /* This is used for both, PCI and ChipCommon core, so be careful. */
1714 + BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
1715 + BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
1716 +#endif
1717 +
1718 + ssb_write32(dev, SSB_CHIPCO_BCAST_ADDR, address);
1719 + ssb_read32(dev, SSB_CHIPCO_BCAST_ADDR); /* flush */
1720 + ssb_write32(dev, SSB_CHIPCO_BCAST_DATA, data);
1721 + ssb_read32(dev, SSB_CHIPCO_BCAST_DATA); /* flush */
1722 +}
1723 +
1724 +void ssb_commit_settings(struct ssb_bus *bus)
1725 +{
1726 + struct ssb_device *dev;
1727 +
1728 +#ifdef CONFIG_SSB_DRIVER_PCICORE
1729 + dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
1730 +#else
1731 + dev = bus->chipco.dev;
1732 +#endif
1733 + if (WARN_ON(!dev))
1734 + return;
1735 + /* This forces an update of the cached registers. */
1736 + ssb_broadcast_value(dev, 0xFD8, 0);
1737 +}
1738 +EXPORT_SYMBOL(ssb_commit_settings);
1739 +
1740 u32 ssb_admatch_base(u32 adm)
1741 {
1742 u32 base = 0;
1743 @@ -1358,8 +1511,10 @@ static int __init ssb_modinit(void)
1744 ssb_buses_lock();
1745 err = ssb_attach_queued_buses();
1746 ssb_buses_unlock();
1747 - if (err)
1748 + if (err) {
1749 bus_unregister(&ssb_bustype);
1750 + goto out;
1751 + }
1752
1753 err = b43_pci_ssb_bridge_init();
1754 if (err) {
1755 @@ -1375,7 +1530,7 @@ static int __init ssb_modinit(void)
1756 /* don't fail SSB init because of this */
1757 err = 0;
1758 }
1759 -
1760 +out:
1761 return err;
1762 }
1763 /* ssb must be initialized after PCI but before the ssb drivers.
1764 --- a/drivers/ssb/pci.c
1765 +++ b/drivers/ssb/pci.c
1766 @@ -1,7 +1,7 @@
1767 /*
1768 * Sonics Silicon Backplane PCI-Hostbus related functions.
1769 *
1770 - * Copyright (C) 2005-2006 Michael Buesch <mb@bu3sch.de>
1771 + * Copyright (C) 2005-2006 Michael Buesch <m@bues.ch>
1772 * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
1773 * Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
1774 * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
1775 @@ -17,6 +17,7 @@
1776
1777 #include <linux/ssb/ssb.h>
1778 #include <linux/ssb/ssb_regs.h>
1779 +#include <linux/slab.h>
1780 #include <linux/pci.h>
1781 #include <linux/delay.h>
1782
1783 @@ -167,10 +168,16 @@ err_pci:
1784 }
1785
1786 /* Get the word-offset for a SSB_SPROM_XXX define. */
1787 -#define SPOFF(offset) (((offset) - SSB_SPROM_BASE) / sizeof(u16))
1788 +#define SPOFF(offset) ((offset) / sizeof(u16))
1789 /* Helper to extract some _offset, which is one of the SSB_SPROM_XXX defines. */
1790 -#define SPEX(_outvar, _offset, _mask, _shift) \
1791 +#define SPEX16(_outvar, _offset, _mask, _shift) \
1792 out->_outvar = ((in[SPOFF(_offset)] & (_mask)) >> (_shift))
1793 +#define SPEX32(_outvar, _offset, _mask, _shift) \
1794 + out->_outvar = ((((u32)in[SPOFF((_offset)+2)] << 16 | \
1795 + in[SPOFF(_offset)]) & (_mask)) >> (_shift))
1796 +#define SPEX(_outvar, _offset, _mask, _shift) \
1797 + SPEX16(_outvar, _offset, _mask, _shift)
1798 +
1799
1800 static inline u8 ssb_crc8(u8 crc, u8 data)
1801 {
1802 @@ -247,7 +254,7 @@ static int sprom_do_read(struct ssb_bus
1803 int i;
1804
1805 for (i = 0; i < bus->sprom_size; i++)
1806 - sprom[i] = ioread16(bus->mmio + SSB_SPROM_BASE + (i * 2));
1807 + sprom[i] = ioread16(bus->mmio + bus->sprom_offset + (i * 2));
1808
1809 return 0;
1810 }
1811 @@ -278,7 +285,7 @@ static int sprom_do_write(struct ssb_bus
1812 ssb_printk("75%%");
1813 else if (i % 2)
1814 ssb_printk(".");
1815 - writew(sprom[i], bus->mmio + SSB_SPROM_BASE + (i * 2));
1816 + writew(sprom[i], bus->mmio + bus->sprom_offset + (i * 2));
1817 mmiowb();
1818 msleep(20);
1819 }
1820 @@ -324,7 +331,6 @@ static void sprom_extract_r123(struct ss
1821 {
1822 int i;
1823 u16 v;
1824 - s8 gain;
1825 u16 loc[3];
1826
1827 if (out->revision == 3) /* rev 3 moved MAC */
1828 @@ -383,20 +389,52 @@ static void sprom_extract_r123(struct ss
1829 SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0);
1830
1831 /* Extract the antenna gain values. */
1832 - gain = r123_extract_antgain(out->revision, in,
1833 - SSB_SPROM1_AGAIN_BG,
1834 - SSB_SPROM1_AGAIN_BG_SHIFT);
1835 - out->antenna_gain.ghz24.a0 = gain;
1836 - out->antenna_gain.ghz24.a1 = gain;
1837 - out->antenna_gain.ghz24.a2 = gain;
1838 - out->antenna_gain.ghz24.a3 = gain;
1839 - gain = r123_extract_antgain(out->revision, in,
1840 - SSB_SPROM1_AGAIN_A,
1841 - SSB_SPROM1_AGAIN_A_SHIFT);
1842 - out->antenna_gain.ghz5.a0 = gain;
1843 - out->antenna_gain.ghz5.a1 = gain;
1844 - out->antenna_gain.ghz5.a2 = gain;
1845 - out->antenna_gain.ghz5.a3 = gain;
1846 + out->antenna_gain.a0 = r123_extract_antgain(out->revision, in,
1847 + SSB_SPROM1_AGAIN_BG,
1848 + SSB_SPROM1_AGAIN_BG_SHIFT);
1849 + out->antenna_gain.a1 = r123_extract_antgain(out->revision, in,
1850 + SSB_SPROM1_AGAIN_A,
1851 + SSB_SPROM1_AGAIN_A_SHIFT);
1852 +}
1853 +
1854 +/* Revs 4 5 and 8 have partially shared layout */
1855 +static void sprom_extract_r458(struct ssb_sprom *out, const u16 *in)
1856 +{
1857 + SPEX(txpid2g[0], SSB_SPROM4_TXPID2G01,
1858 + SSB_SPROM4_TXPID2G0, SSB_SPROM4_TXPID2G0_SHIFT);
1859 + SPEX(txpid2g[1], SSB_SPROM4_TXPID2G01,
1860 + SSB_SPROM4_TXPID2G1, SSB_SPROM4_TXPID2G1_SHIFT);
1861 + SPEX(txpid2g[2], SSB_SPROM4_TXPID2G23,
1862 + SSB_SPROM4_TXPID2G2, SSB_SPROM4_TXPID2G2_SHIFT);
1863 + SPEX(txpid2g[3], SSB_SPROM4_TXPID2G23,
1864 + SSB_SPROM4_TXPID2G3, SSB_SPROM4_TXPID2G3_SHIFT);
1865 +
1866 + SPEX(txpid5gl[0], SSB_SPROM4_TXPID5GL01,
1867 + SSB_SPROM4_TXPID5GL0, SSB_SPROM4_TXPID5GL0_SHIFT);
1868 + SPEX(txpid5gl[1], SSB_SPROM4_TXPID5GL01,
1869 + SSB_SPROM4_TXPID5GL1, SSB_SPROM4_TXPID5GL1_SHIFT);
1870 + SPEX(txpid5gl[2], SSB_SPROM4_TXPID5GL23,
1871 + SSB_SPROM4_TXPID5GL2, SSB_SPROM4_TXPID5GL2_SHIFT);
1872 + SPEX(txpid5gl[3], SSB_SPROM4_TXPID5GL23,
1873 + SSB_SPROM4_TXPID5GL3, SSB_SPROM4_TXPID5GL3_SHIFT);
1874 +
1875 + SPEX(txpid5g[0], SSB_SPROM4_TXPID5G01,
1876 + SSB_SPROM4_TXPID5G0, SSB_SPROM4_TXPID5G0_SHIFT);
1877 + SPEX(txpid5g[1], SSB_SPROM4_TXPID5G01,
1878 + SSB_SPROM4_TXPID5G1, SSB_SPROM4_TXPID5G1_SHIFT);
1879 + SPEX(txpid5g[2], SSB_SPROM4_TXPID5G23,
1880 + SSB_SPROM4_TXPID5G2, SSB_SPROM4_TXPID5G2_SHIFT);
1881 + SPEX(txpid5g[3], SSB_SPROM4_TXPID5G23,
1882 + SSB_SPROM4_TXPID5G3, SSB_SPROM4_TXPID5G3_SHIFT);
1883 +
1884 + SPEX(txpid5gh[0], SSB_SPROM4_TXPID5GH01,
1885 + SSB_SPROM4_TXPID5GH0, SSB_SPROM4_TXPID5GH0_SHIFT);
1886 + SPEX(txpid5gh[1], SSB_SPROM4_TXPID5GH01,
1887 + SSB_SPROM4_TXPID5GH1, SSB_SPROM4_TXPID5GH1_SHIFT);
1888 + SPEX(txpid5gh[2], SSB_SPROM4_TXPID5GH23,
1889 + SSB_SPROM4_TXPID5GH2, SSB_SPROM4_TXPID5GH2_SHIFT);
1890 + SPEX(txpid5gh[3], SSB_SPROM4_TXPID5GH23,
1891 + SSB_SPROM4_TXPID5GH3, SSB_SPROM4_TXPID5GH3_SHIFT);
1892 }
1893
1894 static void sprom_extract_r45(struct ssb_sprom *out, const u16 *in)
1895 @@ -421,10 +459,14 @@ static void sprom_extract_r45(struct ssb
1896 SPEX(country_code, SSB_SPROM4_CCODE, 0xFFFF, 0);
1897 SPEX(boardflags_lo, SSB_SPROM4_BFLLO, 0xFFFF, 0);
1898 SPEX(boardflags_hi, SSB_SPROM4_BFLHI, 0xFFFF, 0);
1899 + SPEX(boardflags2_lo, SSB_SPROM4_BFL2LO, 0xFFFF, 0);
1900 + SPEX(boardflags2_hi, SSB_SPROM4_BFL2HI, 0xFFFF, 0);
1901 } else {
1902 SPEX(country_code, SSB_SPROM5_CCODE, 0xFFFF, 0);
1903 SPEX(boardflags_lo, SSB_SPROM5_BFLLO, 0xFFFF, 0);
1904 SPEX(boardflags_hi, SSB_SPROM5_BFLHI, 0xFFFF, 0);
1905 + SPEX(boardflags2_lo, SSB_SPROM5_BFL2LO, 0xFFFF, 0);
1906 + SPEX(boardflags2_hi, SSB_SPROM5_BFL2HI, 0xFFFF, 0);
1907 }
1908 SPEX(ant_available_a, SSB_SPROM4_ANTAVAIL, SSB_SPROM4_ANTAVAIL_A,
1909 SSB_SPROM4_ANTAVAIL_A_SHIFT);
1910 @@ -453,16 +495,16 @@ static void sprom_extract_r45(struct ssb
1911 }
1912
1913 /* Extract the antenna gain values. */
1914 - SPEX(antenna_gain.ghz24.a0, SSB_SPROM4_AGAIN01,
1915 + SPEX(antenna_gain.a0, SSB_SPROM4_AGAIN01,
1916 SSB_SPROM4_AGAIN0, SSB_SPROM4_AGAIN0_SHIFT);
1917 - SPEX(antenna_gain.ghz24.a1, SSB_SPROM4_AGAIN01,
1918 + SPEX(antenna_gain.a1, SSB_SPROM4_AGAIN01,
1919 SSB_SPROM4_AGAIN1, SSB_SPROM4_AGAIN1_SHIFT);
1920 - SPEX(antenna_gain.ghz24.a2, SSB_SPROM4_AGAIN23,
1921 + SPEX(antenna_gain.a2, SSB_SPROM4_AGAIN23,
1922 SSB_SPROM4_AGAIN2, SSB_SPROM4_AGAIN2_SHIFT);
1923 - SPEX(antenna_gain.ghz24.a3, SSB_SPROM4_AGAIN23,
1924 + SPEX(antenna_gain.a3, SSB_SPROM4_AGAIN23,
1925 SSB_SPROM4_AGAIN3, SSB_SPROM4_AGAIN3_SHIFT);
1926 - memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
1927 - sizeof(out->antenna_gain.ghz5));
1928 +
1929 + sprom_extract_r458(out, in);
1930
1931 /* TODO - get remaining rev 4 stuff needed */
1932 }
1933 @@ -470,16 +512,24 @@ static void sprom_extract_r45(struct ssb
1934 static void sprom_extract_r8(struct ssb_sprom *out, const u16 *in)
1935 {
1936 int i;
1937 - u16 v;
1938 + u16 v, o;
1939 + u16 pwr_info_offset[] = {
1940 + SSB_SROM8_PWR_INFO_CORE0, SSB_SROM8_PWR_INFO_CORE1,
1941 + SSB_SROM8_PWR_INFO_CORE2, SSB_SROM8_PWR_INFO_CORE3
1942 + };
1943 + BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
1944 + ARRAY_SIZE(out->core_pwr_info));
1945
1946 /* extract the MAC address */
1947 for (i = 0; i < 3; i++) {
1948 - v = in[SPOFF(SSB_SPROM1_IL0MAC) + i];
1949 + v = in[SPOFF(SSB_SPROM8_IL0MAC) + i];
1950 *(((__be16 *)out->il0mac) + i) = cpu_to_be16(v);
1951 }
1952 SPEX(country_code, SSB_SPROM8_CCODE, 0xFFFF, 0);
1953 SPEX(boardflags_lo, SSB_SPROM8_BFLLO, 0xFFFF, 0);
1954 SPEX(boardflags_hi, SSB_SPROM8_BFLHI, 0xFFFF, 0);
1955 + SPEX(boardflags2_lo, SSB_SPROM8_BFL2LO, 0xFFFF, 0);
1956 + SPEX(boardflags2_hi, SSB_SPROM8_BFL2HI, 0xFFFF, 0);
1957 SPEX(ant_available_a, SSB_SPROM8_ANTAVAIL, SSB_SPROM8_ANTAVAIL_A,
1958 SSB_SPROM8_ANTAVAIL_A_SHIFT);
1959 SPEX(ant_available_bg, SSB_SPROM8_ANTAVAIL, SSB_SPROM8_ANTAVAIL_BG,
1960 @@ -490,24 +540,122 @@ static void sprom_extract_r8(struct ssb_
1961 SPEX(maxpwr_a, SSB_SPROM8_MAXP_A, SSB_SPROM8_MAXP_A_MASK, 0);
1962 SPEX(itssi_a, SSB_SPROM8_MAXP_A, SSB_SPROM8_ITSSI_A,
1963 SSB_SPROM8_ITSSI_A_SHIFT);
1964 + SPEX(maxpwr_ah, SSB_SPROM8_MAXP_AHL, SSB_SPROM8_MAXP_AH_MASK, 0);
1965 + SPEX(maxpwr_al, SSB_SPROM8_MAXP_AHL, SSB_SPROM8_MAXP_AL_MASK,
1966 + SSB_SPROM8_MAXP_AL_SHIFT);
1967 SPEX(gpio0, SSB_SPROM8_GPIOA, SSB_SPROM8_GPIOA_P0, 0);
1968 SPEX(gpio1, SSB_SPROM8_GPIOA, SSB_SPROM8_GPIOA_P1,
1969 SSB_SPROM8_GPIOA_P1_SHIFT);
1970 SPEX(gpio2, SSB_SPROM8_GPIOB, SSB_SPROM8_GPIOB_P2, 0);
1971 SPEX(gpio3, SSB_SPROM8_GPIOB, SSB_SPROM8_GPIOB_P3,
1972 SSB_SPROM8_GPIOB_P3_SHIFT);
1973 + SPEX(tri2g, SSB_SPROM8_TRI25G, SSB_SPROM8_TRI2G, 0);
1974 + SPEX(tri5g, SSB_SPROM8_TRI25G, SSB_SPROM8_TRI5G,
1975 + SSB_SPROM8_TRI5G_SHIFT);
1976 + SPEX(tri5gl, SSB_SPROM8_TRI5GHL, SSB_SPROM8_TRI5GL, 0);
1977 + SPEX(tri5gh, SSB_SPROM8_TRI5GHL, SSB_SPROM8_TRI5GH,
1978 + SSB_SPROM8_TRI5GH_SHIFT);
1979 + SPEX(rxpo2g, SSB_SPROM8_RXPO, SSB_SPROM8_RXPO2G, 0);
1980 + SPEX(rxpo5g, SSB_SPROM8_RXPO, SSB_SPROM8_RXPO5G,
1981 + SSB_SPROM8_RXPO5G_SHIFT);
1982 + SPEX(rssismf2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISMF2G, 0);
1983 + SPEX(rssismc2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISMC2G,
1984 + SSB_SPROM8_RSSISMC2G_SHIFT);
1985 + SPEX(rssisav2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISAV2G,
1986 + SSB_SPROM8_RSSISAV2G_SHIFT);
1987 + SPEX(bxa2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_BXA2G,
1988 + SSB_SPROM8_BXA2G_SHIFT);
1989 + SPEX(rssismf5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISMF5G, 0);
1990 + SPEX(rssismc5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISMC5G,
1991 + SSB_SPROM8_RSSISMC5G_SHIFT);
1992 + SPEX(rssisav5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISAV5G,
1993 + SSB_SPROM8_RSSISAV5G_SHIFT);
1994 + SPEX(bxa5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_BXA5G,
1995 + SSB_SPROM8_BXA5G_SHIFT);
1996 + SPEX(pa0b0, SSB_SPROM8_PA0B0, 0xFFFF, 0);
1997 + SPEX(pa0b1, SSB_SPROM8_PA0B1, 0xFFFF, 0);
1998 + SPEX(pa0b2, SSB_SPROM8_PA0B2, 0xFFFF, 0);
1999 + SPEX(pa1b0, SSB_SPROM8_PA1B0, 0xFFFF, 0);
2000 + SPEX(pa1b1, SSB_SPROM8_PA1B1, 0xFFFF, 0);
2001 + SPEX(pa1b2, SSB_SPROM8_PA1B2, 0xFFFF, 0);
2002 + SPEX(pa1lob0, SSB_SPROM8_PA1LOB0, 0xFFFF, 0);
2003 + SPEX(pa1lob1, SSB_SPROM8_PA1LOB1, 0xFFFF, 0);
2004 + SPEX(pa1lob2, SSB_SPROM8_PA1LOB2, 0xFFFF, 0);
2005 + SPEX(pa1hib0, SSB_SPROM8_PA1HIB0, 0xFFFF, 0);
2006 + SPEX(pa1hib1, SSB_SPROM8_PA1HIB1, 0xFFFF, 0);
2007 + SPEX(pa1hib2, SSB_SPROM8_PA1HIB2, 0xFFFF, 0);
2008 + SPEX(cck2gpo, SSB_SPROM8_CCK2GPO, 0xFFFF, 0);
2009 + SPEX32(ofdm2gpo, SSB_SPROM8_OFDM2GPO, 0xFFFFFFFF, 0);
2010 + SPEX32(ofdm5glpo, SSB_SPROM8_OFDM5GLPO, 0xFFFFFFFF, 0);
2011 + SPEX32(ofdm5gpo, SSB_SPROM8_OFDM5GPO, 0xFFFFFFFF, 0);
2012 + SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, 0xFFFFFFFF, 0);
2013
2014 /* Extract the antenna gain values. */
2015 - SPEX(antenna_gain.ghz24.a0, SSB_SPROM8_AGAIN01,
2016 + SPEX(antenna_gain.a0, SSB_SPROM8_AGAIN01,
2017 SSB_SPROM8_AGAIN0, SSB_SPROM8_AGAIN0_SHIFT);
2018 - SPEX(antenna_gain.ghz24.a1, SSB_SPROM8_AGAIN01,
2019 + SPEX(antenna_gain.a1, SSB_SPROM8_AGAIN01,
2020 SSB_SPROM8_AGAIN1, SSB_SPROM8_AGAIN1_SHIFT);
2021 - SPEX(antenna_gain.ghz24.a2, SSB_SPROM8_AGAIN23,
2022 + SPEX(antenna_gain.a2, SSB_SPROM8_AGAIN23,
2023 SSB_SPROM8_AGAIN2, SSB_SPROM8_AGAIN2_SHIFT);
2024 - SPEX(antenna_gain.ghz24.a3, SSB_SPROM8_AGAIN23,
2025 + SPEX(antenna_gain.a3, SSB_SPROM8_AGAIN23,
2026 SSB_SPROM8_AGAIN3, SSB_SPROM8_AGAIN3_SHIFT);
2027 - memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
2028 - sizeof(out->antenna_gain.ghz5));
2029 +
2030 + /* Extract cores power info info */
2031 + for (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) {
2032 + o = pwr_info_offset[i];
2033 + SPEX(core_pwr_info[i].itssi_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
2034 + SSB_SPROM8_2G_ITSSI, SSB_SPROM8_2G_ITSSI_SHIFT);
2035 + SPEX(core_pwr_info[i].maxpwr_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
2036 + SSB_SPROM8_2G_MAXP, 0);
2037 +
2038 + SPEX(core_pwr_info[i].pa_2g[0], o + SSB_SROM8_2G_PA_0, ~0, 0);
2039 + SPEX(core_pwr_info[i].pa_2g[1], o + SSB_SROM8_2G_PA_1, ~0, 0);
2040 + SPEX(core_pwr_info[i].pa_2g[2], o + SSB_SROM8_2G_PA_2, ~0, 0);
2041 +
2042 + SPEX(core_pwr_info[i].itssi_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
2043 + SSB_SPROM8_5G_ITSSI, SSB_SPROM8_5G_ITSSI_SHIFT);
2044 + SPEX(core_pwr_info[i].maxpwr_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
2045 + SSB_SPROM8_5G_MAXP, 0);
2046 + SPEX(core_pwr_info[i].maxpwr_5gh, o + SSB_SPROM8_5GHL_MAXP,
2047 + SSB_SPROM8_5GH_MAXP, 0);
2048 + SPEX(core_pwr_info[i].maxpwr_5gl, o + SSB_SPROM8_5GHL_MAXP,
2049 + SSB_SPROM8_5GL_MAXP, SSB_SPROM8_5GL_MAXP_SHIFT);
2050 +
2051 + SPEX(core_pwr_info[i].pa_5gl[0], o + SSB_SROM8_5GL_PA_0, ~0, 0);
2052 + SPEX(core_pwr_info[i].pa_5gl[1], o + SSB_SROM8_5GL_PA_1, ~0, 0);
2053 + SPEX(core_pwr_info[i].pa_5gl[2], o + SSB_SROM8_5GL_PA_2, ~0, 0);
2054 + SPEX(core_pwr_info[i].pa_5g[0], o + SSB_SROM8_5G_PA_0, ~0, 0);
2055 + SPEX(core_pwr_info[i].pa_5g[1], o + SSB_SROM8_5G_PA_1, ~0, 0);
2056 + SPEX(core_pwr_info[i].pa_5g[2], o + SSB_SROM8_5G_PA_2, ~0, 0);
2057 + SPEX(core_pwr_info[i].pa_5gh[0], o + SSB_SROM8_5GH_PA_0, ~0, 0);
2058 + SPEX(core_pwr_info[i].pa_5gh[1], o + SSB_SROM8_5GH_PA_1, ~0, 0);
2059 + SPEX(core_pwr_info[i].pa_5gh[2], o + SSB_SROM8_5GH_PA_2, ~0, 0);
2060 + }
2061 +
2062 + /* Extract FEM info */
2063 + SPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G,
2064 + SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
2065 + SPEX(fem.ghz2.extpa_gain, SSB_SPROM8_FEM2G,
2066 + SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
2067 + SPEX(fem.ghz2.pdet_range, SSB_SPROM8_FEM2G,
2068 + SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);
2069 + SPEX(fem.ghz2.tr_iso, SSB_SPROM8_FEM2G,
2070 + SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);
2071 + SPEX(fem.ghz2.antswlut, SSB_SPROM8_FEM2G,
2072 + SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
2073 +
2074 + SPEX(fem.ghz5.tssipos, SSB_SPROM8_FEM5G,
2075 + SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
2076 + SPEX(fem.ghz5.extpa_gain, SSB_SPROM8_FEM5G,
2077 + SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
2078 + SPEX(fem.ghz5.pdet_range, SSB_SPROM8_FEM5G,
2079 + SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);
2080 + SPEX(fem.ghz5.tr_iso, SSB_SPROM8_FEM5G,
2081 + SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);
2082 + SPEX(fem.ghz5.antswlut, SSB_SPROM8_FEM5G,
2083 + SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
2084 +
2085 + sprom_extract_r458(out, in);
2086
2087 /* TODO - get remaining rev 8 stuff needed */
2088 }
2089 @@ -521,36 +669,34 @@ static int sprom_extract(struct ssb_bus
2090 ssb_dprintk(KERN_DEBUG PFX "SPROM revision %d detected.\n", out->revision);
2091 memset(out->et0mac, 0xFF, 6); /* preset et0 and et1 mac */
2092 memset(out->et1mac, 0xFF, 6);
2093 +
2094 if ((bus->chip_id & 0xFF00) == 0x4400) {
2095 /* Workaround: The BCM44XX chip has a stupid revision
2096 * number stored in the SPROM.
2097 * Always extract r1. */
2098 out->revision = 1;
2099 + ssb_dprintk(KERN_DEBUG PFX "SPROM treated as revision %d\n", out->revision);
2100 + }
2101 +
2102 + switch (out->revision) {
2103 + case 1:
2104 + case 2:
2105 + case 3:
2106 sprom_extract_r123(out, in);
2107 - } else if (bus->chip_id == 0x4321) {
2108 - /* the BCM4328 has a chipid == 0x4321 and a rev 4 SPROM */
2109 - out->revision = 4;
2110 + break;
2111 + case 4:
2112 + case 5:
2113 sprom_extract_r45(out, in);
2114 - } else {
2115 - switch (out->revision) {
2116 - case 1:
2117 - case 2:
2118 - case 3:
2119 - sprom_extract_r123(out, in);
2120 - break;
2121 - case 4:
2122 - case 5:
2123 - sprom_extract_r45(out, in);
2124 - break;
2125 - case 8:
2126 - sprom_extract_r8(out, in);
2127 - break;
2128 - default:
2129 - ssb_printk(KERN_WARNING PFX "Unsupported SPROM"
2130 - " revision %d detected. Will extract"
2131 - " v1\n", out->revision);
2132 - sprom_extract_r123(out, in);
2133 - }
2134 + break;
2135 + case 8:
2136 + sprom_extract_r8(out, in);
2137 + break;
2138 + default:
2139 + ssb_printk(KERN_WARNING PFX "Unsupported SPROM"
2140 + " revision %d detected. Will extract"
2141 + " v1\n", out->revision);
2142 + out->revision = 1;
2143 + sprom_extract_r123(out, in);
2144 }
2145
2146 if (out->boardflags_lo == 0xFFFF)
2147 @@ -564,13 +710,34 @@ static int sprom_extract(struct ssb_bus
2148 static int ssb_pci_sprom_get(struct ssb_bus *bus,
2149 struct ssb_sprom *sprom)
2150 {
2151 - const struct ssb_sprom *fallback;
2152 - int err = -ENOMEM;
2153 + int err;
2154 u16 *buf;
2155
2156 + if (!ssb_is_sprom_available(bus)) {
2157 + ssb_printk(KERN_ERR PFX "No SPROM available!\n");
2158 + return -ENODEV;
2159 + }
2160 + if (bus->chipco.dev) { /* can be unavailable! */
2161 + /*
2162 + * get SPROM offset: SSB_SPROM_BASE1 except for
2163 + * chipcommon rev >= 31 or chip ID is 0x4312 and
2164 + * chipcommon status & 3 == 2
2165 + */
2166 + if (bus->chipco.dev->id.revision >= 31)
2167 + bus->sprom_offset = SSB_SPROM_BASE31;
2168 + else if (bus->chip_id == 0x4312 &&
2169 + (bus->chipco.status & 0x03) == 2)
2170 + bus->sprom_offset = SSB_SPROM_BASE31;
2171 + else
2172 + bus->sprom_offset = SSB_SPROM_BASE1;
2173 + } else {
2174 + bus->sprom_offset = SSB_SPROM_BASE1;
2175 + }
2176 + ssb_dprintk(KERN_INFO PFX "SPROM offset is 0x%x\n", bus->sprom_offset);
2177 +
2178 buf = kcalloc(SSB_SPROMSIZE_WORDS_R123, sizeof(u16), GFP_KERNEL);
2179 if (!buf)
2180 - goto out;
2181 + return -ENOMEM;
2182 bus->sprom_size = SSB_SPROMSIZE_WORDS_R123;
2183 sprom_do_read(bus, buf);
2184 err = sprom_check_crc(buf, bus->sprom_size);
2185 @@ -580,17 +747,24 @@ static int ssb_pci_sprom_get(struct ssb_
2186 buf = kcalloc(SSB_SPROMSIZE_WORDS_R4, sizeof(u16),
2187 GFP_KERNEL);
2188 if (!buf)
2189 - goto out;
2190 + return -ENOMEM;
2191 bus->sprom_size = SSB_SPROMSIZE_WORDS_R4;
2192 sprom_do_read(bus, buf);
2193 err = sprom_check_crc(buf, bus->sprom_size);
2194 if (err) {
2195 /* All CRC attempts failed.
2196 * Maybe there is no SPROM on the device?
2197 - * If we have a fallback, use that. */
2198 - fallback = ssb_get_fallback_sprom();
2199 - if (fallback) {
2200 - memcpy(sprom, fallback, sizeof(*sprom));
2201 + * Now we ask the arch code if there is some sprom
2202 + * available for this device in some other storage */
2203 + err = ssb_fill_sprom_with_fallback(bus, sprom);
2204 + if (err) {
2205 + ssb_printk(KERN_WARNING PFX "WARNING: Using"
2206 + " fallback SPROM failed (err %d)\n",
2207 + err);
2208 + } else {
2209 + ssb_dprintk(KERN_DEBUG PFX "Using SPROM"
2210 + " revision %d provided by"
2211 + " platform.\n", sprom->revision);
2212 err = 0;
2213 goto out_free;
2214 }
2215 @@ -602,19 +776,15 @@ static int ssb_pci_sprom_get(struct ssb_
2216
2217 out_free:
2218 kfree(buf);
2219 -out:
2220 return err;
2221 }
2222
2223 static void ssb_pci_get_boardinfo(struct ssb_bus *bus,
2224 struct ssb_boardinfo *bi)
2225 {
2226 - pci_read_config_word(bus->host_pci, PCI_SUBSYSTEM_VENDOR_ID,
2227 - &bi->vendor);
2228 - pci_read_config_word(bus->host_pci, PCI_SUBSYSTEM_ID,
2229 - &bi->type);
2230 - pci_read_config_word(bus->host_pci, PCI_REVISION_ID,
2231 - &bi->rev);
2232 + bi->vendor = bus->host_pci->subsystem_vendor;
2233 + bi->type = bus->host_pci->subsystem_device;
2234 + bi->rev = bus->host_pci->revision;
2235 }
2236
2237 int ssb_pci_get_invariants(struct ssb_bus *bus,
2238 --- a/drivers/ssb/pcihost_wrapper.c
2239 +++ b/drivers/ssb/pcihost_wrapper.c
2240 @@ -6,12 +6,13 @@
2241 * Copyright (c) 2005 Stefano Brivio <st3@riseup.net>
2242 * Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
2243 * Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
2244 - * Copyright (c) 2005-2007 Michael Buesch <mbuesch@freenet.de>
2245 + * Copyright (c) 2005-2007 Michael Buesch <m@bues.ch>
2246 *
2247 * Licensed under the GNU/GPL. See COPYING for details.
2248 */
2249
2250 #include <linux/pci.h>
2251 +#include <linux/slab.h>
2252 #include <linux/ssb/ssb.h>
2253
2254
2255 @@ -52,12 +53,13 @@ static int ssb_pcihost_resume(struct pci
2256 # define ssb_pcihost_resume NULL
2257 #endif /* CONFIG_PM */
2258
2259 -static int ssb_pcihost_probe(struct pci_dev *dev,
2260 - const struct pci_device_id *id)
2261 +static int __devinit ssb_pcihost_probe(struct pci_dev *dev,
2262 + const struct pci_device_id *id)
2263 {
2264 struct ssb_bus *ssb;
2265 int err = -ENOMEM;
2266 const char *name;
2267 + u32 val;
2268
2269 ssb = kzalloc(sizeof(*ssb), GFP_KERNEL);
2270 if (!ssb)
2271 @@ -73,6 +75,12 @@ static int ssb_pcihost_probe(struct pci_
2272 goto err_pci_disable;
2273 pci_set_master(dev);
2274
2275 + /* Disable the RETRY_TIMEOUT register (0x41) to keep
2276 + * PCI Tx retries from interfering with C3 CPU state */
2277 + pci_read_config_dword(dev, 0x40, &val);
2278 + if ((val & 0x0000ff00) != 0)
2279 + pci_write_config_dword(dev, 0x40, val & 0xffff00ff);
2280 +
2281 err = ssb_bus_pcibus_register(ssb, dev);
2282 if (err)
2283 goto err_pci_release_regions;
2284 @@ -102,7 +110,7 @@ static void ssb_pcihost_remove(struct pc
2285 pci_set_drvdata(dev, NULL);
2286 }
2287
2288 -int ssb_pcihost_register(struct pci_driver *driver)
2289 +int __devinit ssb_pcihost_register(struct pci_driver *driver)
2290 {
2291 driver->probe = ssb_pcihost_probe;
2292 driver->remove = ssb_pcihost_remove;
2293 --- a/drivers/ssb/pcmcia.c
2294 +++ b/drivers/ssb/pcmcia.c
2295 @@ -3,7 +3,7 @@
2296 * PCMCIA-Hostbus related functions
2297 *
2298 * Copyright 2006 Johannes Berg <johannes@sipsolutions.net>
2299 - * Copyright 2007-2008 Michael Buesch <mb@bu3sch.de>
2300 + * Copyright 2007-2008 Michael Buesch <m@bues.ch>
2301 *
2302 * Licensed under the GNU/GPL. See COPYING for details.
2303 */
2304 @@ -583,7 +583,7 @@ static int ssb_pcmcia_sprom_write_all(st
2305 ssb_printk(".");
2306 err = ssb_pcmcia_sprom_write(bus, i, sprom[i]);
2307 if (err) {
2308 - ssb_printk("\n" KERN_NOTICE PFX
2309 + ssb_printk(KERN_NOTICE PFX
2310 "Failed to write to SPROM.\n");
2311 failed = 1;
2312 break;
2313 @@ -591,7 +591,7 @@ static int ssb_pcmcia_sprom_write_all(st
2314 }
2315 err = ssb_pcmcia_sprom_command(bus, SSB_PCMCIA_SPROMCTL_WRITEDIS);
2316 if (err) {
2317 - ssb_printk("\n" KERN_NOTICE PFX
2318 + ssb_printk(KERN_NOTICE PFX
2319 "Could not disable SPROM write access.\n");
2320 failed = 1;
2321 }
2322 @@ -617,134 +617,136 @@ static int ssb_pcmcia_sprom_check_crc(co
2323 } \
2324 } while (0)
2325
2326 -int ssb_pcmcia_get_invariants(struct ssb_bus *bus,
2327 - struct ssb_init_invariants *iv)
2328 +static int ssb_pcmcia_get_mac(struct pcmcia_device *p_dev,
2329 + tuple_t *tuple,
2330 + void *priv)
2331 +{
2332 + struct ssb_sprom *sprom = priv;
2333 +
2334 + if (tuple->TupleData[0] != CISTPL_FUNCE_LAN_NODE_ID)
2335 + return -EINVAL;
2336 + if (tuple->TupleDataLen != ETH_ALEN + 2)
2337 + return -EINVAL;
2338 + if (tuple->TupleData[1] != ETH_ALEN)
2339 + return -EINVAL;
2340 + memcpy(sprom->il0mac, &tuple->TupleData[2], ETH_ALEN);
2341 + return 0;
2342 +};
2343 +
2344 +static int ssb_pcmcia_do_get_invariants(struct pcmcia_device *p_dev,
2345 + tuple_t *tuple,
2346 + void *priv)
2347 {
2348 - tuple_t tuple;
2349 - int res;
2350 - unsigned char buf[32];
2351 + struct ssb_init_invariants *iv = priv;
2352 struct ssb_sprom *sprom = &iv->sprom;
2353 struct ssb_boardinfo *bi = &iv->boardinfo;
2354 const char *error_description;
2355
2356 + GOTO_ERROR_ON(tuple->TupleDataLen < 1, "VEN tpl < 1");
2357 + switch (tuple->TupleData[0]) {
2358 + case SSB_PCMCIA_CIS_ID:
2359 + GOTO_ERROR_ON((tuple->TupleDataLen != 5) &&
2360 + (tuple->TupleDataLen != 7),
2361 + "id tpl size");
2362 + bi->vendor = tuple->TupleData[1] |
2363 + ((u16)tuple->TupleData[2] << 8);
2364 + break;
2365 + case SSB_PCMCIA_CIS_BOARDREV:
2366 + GOTO_ERROR_ON(tuple->TupleDataLen != 2,
2367 + "boardrev tpl size");
2368 + sprom->board_rev = tuple->TupleData[1];
2369 + break;
2370 + case SSB_PCMCIA_CIS_PA:
2371 + GOTO_ERROR_ON((tuple->TupleDataLen != 9) &&
2372 + (tuple->TupleDataLen != 10),
2373 + "pa tpl size");
2374 + sprom->pa0b0 = tuple->TupleData[1] |
2375 + ((u16)tuple->TupleData[2] << 8);
2376 + sprom->pa0b1 = tuple->TupleData[3] |
2377 + ((u16)tuple->TupleData[4] << 8);
2378 + sprom->pa0b2 = tuple->TupleData[5] |
2379 + ((u16)tuple->TupleData[6] << 8);
2380 + sprom->itssi_a = tuple->TupleData[7];
2381 + sprom->itssi_bg = tuple->TupleData[7];
2382 + sprom->maxpwr_a = tuple->TupleData[8];
2383 + sprom->maxpwr_bg = tuple->TupleData[8];
2384 + break;
2385 + case SSB_PCMCIA_CIS_OEMNAME:
2386 + /* We ignore this. */
2387 + break;
2388 + case SSB_PCMCIA_CIS_CCODE:
2389 + GOTO_ERROR_ON(tuple->TupleDataLen != 2,
2390 + "ccode tpl size");
2391 + sprom->country_code = tuple->TupleData[1];
2392 + break;
2393 + case SSB_PCMCIA_CIS_ANTENNA:
2394 + GOTO_ERROR_ON(tuple->TupleDataLen != 2,
2395 + "ant tpl size");
2396 + sprom->ant_available_a = tuple->TupleData[1];
2397 + sprom->ant_available_bg = tuple->TupleData[1];
2398 + break;
2399 + case SSB_PCMCIA_CIS_ANTGAIN:
2400 + GOTO_ERROR_ON(tuple->TupleDataLen != 2,
2401 + "antg tpl size");
2402 + sprom->antenna_gain.a0 = tuple->TupleData[1];
2403 + sprom->antenna_gain.a1 = tuple->TupleData[1];
2404 + sprom->antenna_gain.a2 = tuple->TupleData[1];
2405 + sprom->antenna_gain.a3 = tuple->TupleData[1];
2406 + break;
2407 + case SSB_PCMCIA_CIS_BFLAGS:
2408 + GOTO_ERROR_ON((tuple->TupleDataLen != 3) &&
2409 + (tuple->TupleDataLen != 5),
2410 + "bfl tpl size");
2411 + sprom->boardflags_lo = tuple->TupleData[1] |
2412 + ((u16)tuple->TupleData[2] << 8);
2413 + break;
2414 + case SSB_PCMCIA_CIS_LEDS:
2415 + GOTO_ERROR_ON(tuple->TupleDataLen != 5,
2416 + "leds tpl size");
2417 + sprom->gpio0 = tuple->TupleData[1];
2418 + sprom->gpio1 = tuple->TupleData[2];
2419 + sprom->gpio2 = tuple->TupleData[3];
2420 + sprom->gpio3 = tuple->TupleData[4];
2421 + break;
2422 + }
2423 + return -ENOSPC; /* continue with next entry */
2424 +
2425 +error:
2426 + ssb_printk(KERN_ERR PFX
2427 + "PCMCIA: Failed to fetch device invariants: %s\n",
2428 + error_description);
2429 + return -ENODEV;
2430 +}
2431 +
2432 +
2433 +int ssb_pcmcia_get_invariants(struct ssb_bus *bus,
2434 + struct ssb_init_invariants *iv)
2435 +{
2436 + struct ssb_sprom *sprom = &iv->sprom;
2437 + int res;
2438 +
2439 memset(sprom, 0xFF, sizeof(*sprom));
2440 sprom->revision = 1;
2441 sprom->boardflags_lo = 0;
2442 sprom->boardflags_hi = 0;
2443
2444 /* First fetch the MAC address. */
2445 - memset(&tuple, 0, sizeof(tuple));
2446 - tuple.DesiredTuple = CISTPL_FUNCE;
2447 - tuple.TupleData = buf;
2448 - tuple.TupleDataMax = sizeof(buf);
2449 - res = pcmcia_get_first_tuple(bus->host_pcmcia, &tuple);
2450 - GOTO_ERROR_ON(res != 0, "MAC first tpl");
2451 - res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple);
2452 - GOTO_ERROR_ON(res != 0, "MAC first tpl data");
2453 - while (1) {
2454 - GOTO_ERROR_ON(tuple.TupleDataLen < 1, "MAC tpl < 1");
2455 - if (tuple.TupleData[0] == CISTPL_FUNCE_LAN_NODE_ID)
2456 - break;
2457 - res = pcmcia_get_next_tuple(bus->host_pcmcia, &tuple);
2458 - GOTO_ERROR_ON(res != 0, "MAC next tpl");
2459 - res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple);
2460 - GOTO_ERROR_ON(res != 0, "MAC next tpl data");
2461 + res = pcmcia_loop_tuple(bus->host_pcmcia, CISTPL_FUNCE,
2462 + ssb_pcmcia_get_mac, sprom);
2463 + if (res != 0) {
2464 + ssb_printk(KERN_ERR PFX
2465 + "PCMCIA: Failed to fetch MAC address\n");
2466 + return -ENODEV;
2467 }
2468 - GOTO_ERROR_ON(tuple.TupleDataLen != ETH_ALEN + 2, "MAC tpl size");
2469 - memcpy(sprom->il0mac, &tuple.TupleData[2], ETH_ALEN);
2470
2471 /* Fetch the vendor specific tuples. */
2472 - memset(&tuple, 0, sizeof(tuple));
2473 - tuple.DesiredTuple = SSB_PCMCIA_CIS;
2474 - tuple.TupleData = buf;
2475 - tuple.TupleDataMax = sizeof(buf);
2476 - res = pcmcia_get_first_tuple(bus->host_pcmcia, &tuple);
2477 - GOTO_ERROR_ON(res != 0, "VEN first tpl");
2478 - res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple);
2479 - GOTO_ERROR_ON(res != 0, "VEN first tpl data");
2480 - while (1) {
2481 - GOTO_ERROR_ON(tuple.TupleDataLen < 1, "VEN tpl < 1");
2482 - switch (tuple.TupleData[0]) {
2483 - case SSB_PCMCIA_CIS_ID:
2484 - GOTO_ERROR_ON((tuple.TupleDataLen != 5) &&
2485 - (tuple.TupleDataLen != 7),
2486 - "id tpl size");
2487 - bi->vendor = tuple.TupleData[1] |
2488 - ((u16)tuple.TupleData[2] << 8);
2489 - break;
2490 - case SSB_PCMCIA_CIS_BOARDREV:
2491 - GOTO_ERROR_ON(tuple.TupleDataLen != 2,
2492 - "boardrev tpl size");
2493 - sprom->board_rev = tuple.TupleData[1];
2494 - break;
2495 - case SSB_PCMCIA_CIS_PA:
2496 - GOTO_ERROR_ON(tuple.TupleDataLen != 9,
2497 - "pa tpl size");
2498 - sprom->pa0b0 = tuple.TupleData[1] |
2499 - ((u16)tuple.TupleData[2] << 8);
2500 - sprom->pa0b1 = tuple.TupleData[3] |
2501 - ((u16)tuple.TupleData[4] << 8);
2502 - sprom->pa0b2 = tuple.TupleData[5] |
2503 - ((u16)tuple.TupleData[6] << 8);
2504 - sprom->itssi_a = tuple.TupleData[7];
2505 - sprom->itssi_bg = tuple.TupleData[7];
2506 - sprom->maxpwr_a = tuple.TupleData[8];
2507 - sprom->maxpwr_bg = tuple.TupleData[8];
2508 - break;
2509 - case SSB_PCMCIA_CIS_OEMNAME:
2510 - /* We ignore this. */
2511 - break;
2512 - case SSB_PCMCIA_CIS_CCODE:
2513 - GOTO_ERROR_ON(tuple.TupleDataLen != 2,
2514 - "ccode tpl size");
2515 - sprom->country_code = tuple.TupleData[1];
2516 - break;
2517 - case SSB_PCMCIA_CIS_ANTENNA:
2518 - GOTO_ERROR_ON(tuple.TupleDataLen != 2,
2519 - "ant tpl size");
2520 - sprom->ant_available_a = tuple.TupleData[1];
2521 - sprom->ant_available_bg = tuple.TupleData[1];
2522 - break;
2523 - case SSB_PCMCIA_CIS_ANTGAIN:
2524 - GOTO_ERROR_ON(tuple.TupleDataLen != 2,
2525 - "antg tpl size");
2526 - sprom->antenna_gain.ghz24.a0 = tuple.TupleData[1];
2527 - sprom->antenna_gain.ghz24.a1 = tuple.TupleData[1];
2528 - sprom->antenna_gain.ghz24.a2 = tuple.TupleData[1];
2529 - sprom->antenna_gain.ghz24.a3 = tuple.TupleData[1];
2530 - sprom->antenna_gain.ghz5.a0 = tuple.TupleData[1];
2531 - sprom->antenna_gain.ghz5.a1 = tuple.TupleData[1];
2532 - sprom->antenna_gain.ghz5.a2 = tuple.TupleData[1];
2533 - sprom->antenna_gain.ghz5.a3 = tuple.TupleData[1];
2534 - break;
2535 - case SSB_PCMCIA_CIS_BFLAGS:
2536 - GOTO_ERROR_ON(tuple.TupleDataLen != 3,
2537 - "bfl tpl size");
2538 - sprom->boardflags_lo = tuple.TupleData[1] |
2539 - ((u16)tuple.TupleData[2] << 8);
2540 - break;
2541 - case SSB_PCMCIA_CIS_LEDS:
2542 - GOTO_ERROR_ON(tuple.TupleDataLen != 5,
2543 - "leds tpl size");
2544 - sprom->gpio0 = tuple.TupleData[1];
2545 - sprom->gpio1 = tuple.TupleData[2];
2546 - sprom->gpio2 = tuple.TupleData[3];
2547 - sprom->gpio3 = tuple.TupleData[4];
2548 - break;
2549 - }
2550 - res = pcmcia_get_next_tuple(bus->host_pcmcia, &tuple);
2551 - if (res == -ENOSPC)
2552 - break;
2553 - GOTO_ERROR_ON(res != 0, "VEN next tpl");
2554 - res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple);
2555 - GOTO_ERROR_ON(res != 0, "VEN next tpl data");
2556 - }
2557 + res = pcmcia_loop_tuple(bus->host_pcmcia, SSB_PCMCIA_CIS,
2558 + ssb_pcmcia_do_get_invariants, iv);
2559 + if ((res == 0) || (res == -ENOSPC))
2560 + return 0;
2561
2562 - return 0;
2563 -error:
2564 ssb_printk(KERN_ERR PFX
2565 - "PCMCIA: Failed to fetch device invariants: %s\n",
2566 - error_description);
2567 + "PCMCIA: Failed to fetch device invariants\n");
2568 return -ENODEV;
2569 }
2570
2571 --- a/drivers/ssb/scan.c
2572 +++ b/drivers/ssb/scan.c
2573 @@ -2,7 +2,7 @@
2574 * Sonics Silicon Backplane
2575 * Bus scanning
2576 *
2577 - * Copyright (C) 2005-2007 Michael Buesch <mb@bu3sch.de>
2578 + * Copyright (C) 2005-2007 Michael Buesch <m@bues.ch>
2579 * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
2580 * Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
2581 * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
2582 @@ -162,6 +162,8 @@ static u8 chipid_to_nrcores(u16 chipid)
2583 static u32 scan_read32(struct ssb_bus *bus, u8 current_coreidx,
2584 u16 offset)
2585 {
2586 + u32 lo, hi;
2587 +
2588 switch (bus->bustype) {
2589 case SSB_BUSTYPE_SSB:
2590 offset += current_coreidx * SSB_CORE_SIZE;
2591 @@ -174,7 +176,12 @@ static u32 scan_read32(struct ssb_bus *b
2592 offset -= 0x800;
2593 } else
2594 ssb_pcmcia_switch_segment(bus, 0);
2595 - break;
2596 + lo = readw(bus->mmio + offset);
2597 + hi = readw(bus->mmio + offset + 2);
2598 + return lo | (hi << 16);
2599 + case SSB_BUSTYPE_SDIO:
2600 + offset += current_coreidx * SSB_CORE_SIZE;
2601 + return ssb_sdio_scan_read32(bus, offset);
2602 }
2603 return readl(bus->mmio + offset);
2604 }
2605 @@ -188,6 +195,8 @@ static int scan_switchcore(struct ssb_bu
2606 return ssb_pci_switch_coreidx(bus, coreidx);
2607 case SSB_BUSTYPE_PCMCIA:
2608 return ssb_pcmcia_switch_coreidx(bus, coreidx);
2609 + case SSB_BUSTYPE_SDIO:
2610 + return ssb_sdio_scan_switch_coreidx(bus, coreidx);
2611 }
2612 return 0;
2613 }
2614 @@ -206,6 +215,8 @@ void ssb_iounmap(struct ssb_bus *bus)
2615 SSB_BUG_ON(1); /* Can't reach this code. */
2616 #endif
2617 break;
2618 + case SSB_BUSTYPE_SDIO:
2619 + break;
2620 }
2621 bus->mmio = NULL;
2622 bus->mapped_device = NULL;
2623 @@ -230,6 +241,10 @@ static void __iomem *ssb_ioremap(struct
2624 SSB_BUG_ON(1); /* Can't reach this code. */
2625 #endif
2626 break;
2627 + case SSB_BUSTYPE_SDIO:
2628 + /* Nothing to ioremap in the SDIO case, just fake it */
2629 + mmio = (void __iomem *)baseaddr;
2630 + break;
2631 }
2632
2633 return mmio;
2634 @@ -245,7 +260,10 @@ static int we_support_multiple_80211_cor
2635 #ifdef CONFIG_SSB_PCIHOST
2636 if (bus->bustype == SSB_BUSTYPE_PCI) {
2637 if (bus->host_pci->vendor == PCI_VENDOR_ID_BROADCOM &&
2638 - bus->host_pci->device == 0x4324)
2639 + ((bus->host_pci->device == 0x4313) ||
2640 + (bus->host_pci->device == 0x431A) ||
2641 + (bus->host_pci->device == 0x4321) ||
2642 + (bus->host_pci->device == 0x4324)))
2643 return 1;
2644 }
2645 #endif /* CONFIG_SSB_PCIHOST */
2646 @@ -294,8 +312,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
2647 } else {
2648 if (bus->bustype == SSB_BUSTYPE_PCI) {
2649 bus->chip_id = pcidev_to_chipid(bus->host_pci);
2650 - pci_read_config_word(bus->host_pci, PCI_REVISION_ID,
2651 - &bus->chip_rev);
2652 + bus->chip_rev = bus->host_pci->revision;
2653 bus->chip_package = 0;
2654 } else {
2655 bus->chip_id = 0x4710;
2656 @@ -303,6 +320,9 @@ int ssb_bus_scan(struct ssb_bus *bus,
2657 bus->chip_package = 0;
2658 }
2659 }
2660 + ssb_printk(KERN_INFO PFX "Found chip with id 0x%04X, rev 0x%02X and "
2661 + "package 0x%02X\n", bus->chip_id, bus->chip_rev,
2662 + bus->chip_package);
2663 if (!bus->nr_devices)
2664 bus->nr_devices = chipid_to_nrcores(bus->chip_id);
2665 if (bus->nr_devices > ARRAY_SIZE(bus->devices)) {
2666 @@ -339,7 +359,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
2667 dev->bus = bus;
2668 dev->ops = bus->ops;
2669
2670 - ssb_dprintk(KERN_INFO PFX
2671 + printk(KERN_DEBUG PFX
2672 "Core %d found: %s "
2673 "(cc 0x%03X, rev 0x%02X, vendor 0x%04X)\n",
2674 i, ssb_core_name(dev->id.coreid),
2675 @@ -407,6 +427,16 @@ int ssb_bus_scan(struct ssb_bus *bus,
2676 bus->pcicore.dev = dev;
2677 #endif /* CONFIG_SSB_DRIVER_PCICORE */
2678 break;
2679 + case SSB_DEV_ETHERNET:
2680 + if (bus->bustype == SSB_BUSTYPE_PCI) {
2681 + if (bus->host_pci->vendor == PCI_VENDOR_ID_BROADCOM &&
2682 + (bus->host_pci->device & 0xFF00) == 0x4300) {
2683 + /* This is a dangling ethernet core on a
2684 + * wireless device. Ignore it. */
2685 + continue;
2686 + }
2687 + }
2688 + break;
2689 default:
2690 break;
2691 }
2692 --- /dev/null
2693 +++ b/drivers/ssb/sdio.c
2694 @@ -0,0 +1,606 @@
2695 +/*
2696 + * Sonics Silicon Backplane
2697 + * SDIO-Hostbus related functions
2698 + *
2699 + * Copyright 2009 Albert Herranz <albert_herranz@yahoo.es>
2700 + *
2701 + * Based on drivers/ssb/pcmcia.c
2702 + * Copyright 2006 Johannes Berg <johannes@sipsolutions.net>
2703 + * Copyright 2007-2008 Michael Buesch <m@bues.ch>
2704 + *
2705 + * Licensed under the GNU/GPL. See COPYING for details.
2706 + *
2707 + */
2708 +
2709 +#include <linux/ssb/ssb.h>
2710 +#include <linux/delay.h>
2711 +#include <linux/io.h>
2712 +#include <linux/etherdevice.h>
2713 +#include <linux/mmc/sdio_func.h>
2714 +
2715 +#include "ssb_private.h"
2716 +
2717 +/* Define the following to 1 to enable a printk on each coreswitch. */
2718 +#define SSB_VERBOSE_SDIOCORESWITCH_DEBUG 0
2719 +
2720 +
2721 +/* Hardware invariants CIS tuples */
2722 +#define SSB_SDIO_CIS 0x80
2723 +#define SSB_SDIO_CIS_SROMREV 0x00
2724 +#define SSB_SDIO_CIS_ID 0x01
2725 +#define SSB_SDIO_CIS_BOARDREV 0x02
2726 +#define SSB_SDIO_CIS_PA 0x03
2727 +#define SSB_SDIO_CIS_PA_PA0B0_LO 0
2728 +#define SSB_SDIO_CIS_PA_PA0B0_HI 1
2729 +#define SSB_SDIO_CIS_PA_PA0B1_LO 2
2730 +#define SSB_SDIO_CIS_PA_PA0B1_HI 3
2731 +#define SSB_SDIO_CIS_PA_PA0B2_LO 4
2732 +#define SSB_SDIO_CIS_PA_PA0B2_HI 5
2733 +#define SSB_SDIO_CIS_PA_ITSSI 6
2734 +#define SSB_SDIO_CIS_PA_MAXPOW 7
2735 +#define SSB_SDIO_CIS_OEMNAME 0x04
2736 +#define SSB_SDIO_CIS_CCODE 0x05
2737 +#define SSB_SDIO_CIS_ANTENNA 0x06
2738 +#define SSB_SDIO_CIS_ANTGAIN 0x07
2739 +#define SSB_SDIO_CIS_BFLAGS 0x08
2740 +#define SSB_SDIO_CIS_LEDS 0x09
2741 +
2742 +#define CISTPL_FUNCE_LAN_NODE_ID 0x04 /* same as in PCMCIA */
2743 +
2744 +
2745 +/*
2746 + * Function 1 miscellaneous registers.
2747 + *
2748 + * Definitions match src/include/sbsdio.h from the
2749 + * Android Open Source Project
2750 + * http://android.git.kernel.org/?p=platform/system/wlan/broadcom.git
2751 + *
2752 + */
2753 +#define SBSDIO_FUNC1_SBADDRLOW 0x1000a /* SB Address window Low (b15) */
2754 +#define SBSDIO_FUNC1_SBADDRMID 0x1000b /* SB Address window Mid (b23-b16) */
2755 +#define SBSDIO_FUNC1_SBADDRHIGH 0x1000c /* SB Address window High (b24-b31) */
2756 +
2757 +/* valid bits in SBSDIO_FUNC1_SBADDRxxx regs */
2758 +#define SBSDIO_SBADDRLOW_MASK 0x80 /* Valid address bits in SBADDRLOW */
2759 +#define SBSDIO_SBADDRMID_MASK 0xff /* Valid address bits in SBADDRMID */
2760 +#define SBSDIO_SBADDRHIGH_MASK 0xff /* Valid address bits in SBADDRHIGH */
2761 +
2762 +#define SBSDIO_SB_OFT_ADDR_MASK 0x7FFF /* sb offset addr is <= 15 bits, 32k */
2763 +
2764 +/* REVISIT: this flag doesn't seem to matter */
2765 +#define SBSDIO_SB_ACCESS_2_4B_FLAG 0x8000 /* forces 32-bit SB access */
2766 +
2767 +
2768 +/*
2769 + * Address map within the SDIO function address space (128K).
2770 + *
2771 + * Start End Description
2772 + * ------- ------- ------------------------------------------
2773 + * 0x00000 0x0ffff selected backplane address window (64K)
2774 + * 0x10000 0x1ffff backplane control registers (max 64K)
2775 + *
2776 + * The current address window is configured by writing to registers
2777 + * SBADDRLOW, SBADDRMID and SBADDRHIGH.
2778 + *
2779 + * In order to access the contents of a 32-bit Silicon Backplane address
2780 + * the backplane address window must be first loaded with the highest
2781 + * 16 bits of the target address. Then, an access must be done to the
2782 + * SDIO function address space using the lower 15 bits of the address.
2783 + * Bit 15 of the address must be set when doing 32 bit accesses.
2784 + *
2785 + * 10987654321098765432109876543210
2786 + * WWWWWWWWWWWWWWWWW SB Address Window
2787 + * OOOOOOOOOOOOOOOO Offset within SB Address Window
2788 + * a 32-bit access flag
2789 + */
2790 +
2791 +
2792 +/*
2793 + * SSB I/O via SDIO.
2794 + *
2795 + * NOTE: SDIO address @addr is 17 bits long (SDIO address space is 128K).
2796 + */
2797 +
2798 +static inline struct device *ssb_sdio_dev(struct ssb_bus *bus)
2799 +{
2800 + return &bus->host_sdio->dev;
2801 +}
2802 +
2803 +/* host claimed */
2804 +static int ssb_sdio_writeb(struct ssb_bus *bus, unsigned int addr, u8 val)
2805 +{
2806 + int error = 0;
2807 +
2808 + sdio_writeb(bus->host_sdio, val, addr, &error);
2809 + if (unlikely(error)) {
2810 + dev_dbg(ssb_sdio_dev(bus), "%08X <- %02x, error %d\n",
2811 + addr, val, error);
2812 + }
2813 +
2814 + return error;
2815 +}
2816 +
2817 +#if 0
2818 +static u8 ssb_sdio_readb(struct ssb_bus *bus, unsigned int addr)
2819 +{
2820 + u8 val;
2821 + int error = 0;
2822 +
2823 + val = sdio_readb(bus->host_sdio, addr, &error);
2824 + if (unlikely(error)) {
2825 + dev_dbg(ssb_sdio_dev(bus), "%08X -> %02x, error %d\n",
2826 + addr, val, error);
2827 + }
2828 +
2829 + return val;
2830 +}
2831 +#endif
2832 +
2833 +/* host claimed */
2834 +static int ssb_sdio_set_sbaddr_window(struct ssb_bus *bus, u32 address)
2835 +{
2836 + int error;
2837 +
2838 + error = ssb_sdio_writeb(bus, SBSDIO_FUNC1_SBADDRLOW,
2839 + (address >> 8) & SBSDIO_SBADDRLOW_MASK);
2840 + if (error)
2841 + goto out;
2842 + error = ssb_sdio_writeb(bus, SBSDIO_FUNC1_SBADDRMID,
2843 + (address >> 16) & SBSDIO_SBADDRMID_MASK);
2844 + if (error)
2845 + goto out;
2846 + error = ssb_sdio_writeb(bus, SBSDIO_FUNC1_SBADDRHIGH,
2847 + (address >> 24) & SBSDIO_SBADDRHIGH_MASK);
2848 + if (error)
2849 + goto out;
2850 + bus->sdio_sbaddr = address;
2851 +out:
2852 + if (error) {
2853 + dev_dbg(ssb_sdio_dev(bus), "failed to set address window"
2854 + " to 0x%08x, error %d\n", address, error);
2855 + }
2856 +
2857 + return error;
2858 +}
2859 +
2860 +/* for enumeration use only */
2861 +u32 ssb_sdio_scan_read32(struct ssb_bus *bus, u16 offset)
2862 +{
2863 + u32 val;
2864 + int error;
2865 +
2866 + sdio_claim_host(bus->host_sdio);
2867 + val = sdio_readl(bus->host_sdio, offset, &error);
2868 + sdio_release_host(bus->host_sdio);
2869 + if (unlikely(error)) {
2870 + dev_dbg(ssb_sdio_dev(bus), "%04X:%04X > %08x, error %d\n",
2871 + bus->sdio_sbaddr >> 16, offset, val, error);
2872 + }
2873 +
2874 + return val;
2875 +}
2876 +
2877 +/* for enumeration use only */
2878 +int ssb_sdio_scan_switch_coreidx(struct ssb_bus *bus, u8 coreidx)
2879 +{
2880 + u32 sbaddr;
2881 + int error;
2882 +
2883 + sbaddr = (coreidx * SSB_CORE_SIZE) + SSB_ENUM_BASE;
2884 + sdio_claim_host(bus->host_sdio);
2885 + error = ssb_sdio_set_sbaddr_window(bus, sbaddr);
2886 + sdio_release_host(bus->host_sdio);
2887 + if (error) {
2888 + dev_err(ssb_sdio_dev(bus), "failed to switch to core %u,"
2889 + " error %d\n", coreidx, error);
2890 + goto out;
2891 + }
2892 +out:
2893 + return error;
2894 +}
2895 +
2896 +/* host must be already claimed */
2897 +int ssb_sdio_switch_core(struct ssb_bus *bus, struct ssb_device *dev)
2898 +{
2899 + u8 coreidx = dev->core_index;
2900 + u32 sbaddr;
2901 + int error = 0;
2902 +
2903 + sbaddr = (coreidx * SSB_CORE_SIZE) + SSB_ENUM_BASE;
2904 + if (unlikely(bus->sdio_sbaddr != sbaddr)) {
2905 +#if SSB_VERBOSE_SDIOCORESWITCH_DEBUG
2906 + dev_info(ssb_sdio_dev(bus),
2907 + "switching to %s core, index %d\n",
2908 + ssb_core_name(dev->id.coreid), coreidx);
2909 +#endif
2910 + error = ssb_sdio_set_sbaddr_window(bus, sbaddr);
2911 + if (error) {
2912 + dev_dbg(ssb_sdio_dev(bus), "failed to switch to"
2913 + " core %u, error %d\n", coreidx, error);
2914 + goto out;
2915 + }
2916 + bus->mapped_device = dev;
2917 + }
2918 +
2919 +out:
2920 + return error;
2921 +}
2922 +
2923 +static u8 ssb_sdio_read8(struct ssb_device *dev, u16 offset)
2924 +{
2925 + struct ssb_bus *bus = dev->bus;
2926 + u8 val = 0xff;
2927 + int error = 0;
2928 +
2929 + sdio_claim_host(bus->host_sdio);
2930 + if (unlikely(ssb_sdio_switch_core(bus, dev)))
2931 + goto out;
2932 + offset |= bus->sdio_sbaddr & 0xffff;
2933 + offset &= SBSDIO_SB_OFT_ADDR_MASK;
2934 + val = sdio_readb(bus->host_sdio, offset, &error);
2935 + if (error) {
2936 + dev_dbg(ssb_sdio_dev(bus), "%04X:%04X > %02x, error %d\n",
2937 + bus->sdio_sbaddr >> 16, offset, val, error);
2938 + }
2939 +out:
2940 + sdio_release_host(bus->host_sdio);
2941 +
2942 + return val;
2943 +}
2944 +
2945 +static u16 ssb_sdio_read16(struct ssb_device *dev, u16 offset)
2946 +{
2947 + struct ssb_bus *bus = dev->bus;
2948 + u16 val = 0xffff;
2949 + int error = 0;
2950 +
2951 + sdio_claim_host(bus->host_sdio);
2952 + if (unlikely(ssb_sdio_switch_core(bus, dev)))
2953 + goto out;
2954 + offset |= bus->sdio_sbaddr & 0xffff;
2955 + offset &= SBSDIO_SB_OFT_ADDR_MASK;
2956 + val = sdio_readw(bus->host_sdio, offset, &error);
2957 + if (error) {
2958 + dev_dbg(ssb_sdio_dev(bus), "%04X:%04X > %04x, error %d\n",
2959 + bus->sdio_sbaddr >> 16, offset, val, error);
2960 + }
2961 +out:
2962 + sdio_release_host(bus->host_sdio);
2963 +
2964 + return val;
2965 +}
2966 +
2967 +static u32 ssb_sdio_read32(struct ssb_device *dev, u16 offset)
2968 +{
2969 + struct ssb_bus *bus = dev->bus;
2970 + u32 val = 0xffffffff;
2971 + int error = 0;
2972 +
2973 + sdio_claim_host(bus->host_sdio);
2974 + if (unlikely(ssb_sdio_switch_core(bus, dev)))
2975 + goto out;
2976 + offset |= bus->sdio_sbaddr & 0xffff;
2977 + offset &= SBSDIO_SB_OFT_ADDR_MASK;
2978 + offset |= SBSDIO_SB_ACCESS_2_4B_FLAG; /* 32 bit data access */
2979 + val = sdio_readl(bus->host_sdio, offset, &error);
2980 + if (error) {
2981 + dev_dbg(ssb_sdio_dev(bus), "%04X:%04X > %08x, error %d\n",
2982 + bus->sdio_sbaddr >> 16, offset, val, error);
2983 + }
2984 +out:
2985 + sdio_release_host(bus->host_sdio);
2986 +
2987 + return val;
2988 +}
2989 +
2990 +#ifdef CONFIG_SSB_BLOCKIO
2991 +static void ssb_sdio_block_read(struct ssb_device *dev, void *buffer,
2992 + size_t count, u16 offset, u8 reg_width)
2993 +{
2994 + size_t saved_count = count;
2995 + struct ssb_bus *bus = dev->bus;
2996 + int error = 0;
2997 +
2998 + sdio_claim_host(bus->host_sdio);
2999 + if (unlikely(ssb_sdio_switch_core(bus, dev))) {
3000 + error = -EIO;
3001 + memset(buffer, 0xff, count);
3002 + goto err_out;
3003 + }
3004 + offset |= bus->sdio_sbaddr & 0xffff;
3005 + offset &= SBSDIO_SB_OFT_ADDR_MASK;
3006 +
3007 + switch (reg_width) {
3008 + case sizeof(u8): {
3009 + error = sdio_readsb(bus->host_sdio, buffer, offset, count);
3010 + break;
3011 + }
3012 + case sizeof(u16): {
3013 + SSB_WARN_ON(count & 1);
3014 + error = sdio_readsb(bus->host_sdio, buffer, offset, count);
3015 + break;
3016 + }
3017 + case sizeof(u32): {
3018 + SSB_WARN_ON(count & 3);
3019 + offset |= SBSDIO_SB_ACCESS_2_4B_FLAG; /* 32 bit data access */
3020 + error = sdio_readsb(bus->host_sdio, buffer, offset, count);
3021 + break;
3022 + }
3023 + default:
3024 + SSB_WARN_ON(1);
3025 + }
3026 + if (!error)
3027 + goto out;
3028 +
3029 +err_out:
3030 + dev_dbg(ssb_sdio_dev(bus), "%04X:%04X (width=%u, len=%zu), error %d\n",
3031 + bus->sdio_sbaddr >> 16, offset, reg_width, saved_count, error);
3032 +out:
3033 + sdio_release_host(bus->host_sdio);
3034 +}
3035 +#endif /* CONFIG_SSB_BLOCKIO */
3036 +
3037 +static void ssb_sdio_write8(struct ssb_device *dev, u16 offset, u8 val)
3038 +{
3039 + struct ssb_bus *bus = dev->bus;
3040 + int error = 0;
3041 +
3042 + sdio_claim_host(bus->host_sdio);
3043 + if (unlikely(ssb_sdio_switch_core(bus, dev)))
3044 + goto out;
3045 + offset |= bus->sdio_sbaddr & 0xffff;
3046 + offset &= SBSDIO_SB_OFT_ADDR_MASK;
3047 + sdio_writeb(bus->host_sdio, val, offset, &error);
3048 + if (error) {
3049 + dev_dbg(ssb_sdio_dev(bus), "%04X:%04X < %02x, error %d\n",
3050 + bus->sdio_sbaddr >> 16, offset, val, error);
3051 + }
3052 +out:
3053 + sdio_release_host(bus->host_sdio);
3054 +}
3055 +
3056 +static void ssb_sdio_write16(struct ssb_device *dev, u16 offset, u16 val)
3057 +{
3058 + struct ssb_bus *bus = dev->bus;
3059 + int error = 0;
3060 +
3061 + sdio_claim_host(bus->host_sdio);
3062 + if (unlikely(ssb_sdio_switch_core(bus, dev)))
3063 + goto out;
3064 + offset |= bus->sdio_sbaddr & 0xffff;
3065 + offset &= SBSDIO_SB_OFT_ADDR_MASK;
3066 + sdio_writew(bus->host_sdio, val, offset, &error);
3067 + if (error) {
3068 + dev_dbg(ssb_sdio_dev(bus), "%04X:%04X < %04x, error %d\n",
3069 + bus->sdio_sbaddr >> 16, offset, val, error);
3070 + }
3071 +out:
3072 + sdio_release_host(bus->host_sdio);
3073 +}
3074 +
3075 +static void ssb_sdio_write32(struct ssb_device *dev, u16 offset, u32 val)
3076 +{
3077 + struct ssb_bus *bus = dev->bus;
3078 + int error = 0;
3079 +
3080 + sdio_claim_host(bus->host_sdio);
3081 + if (unlikely(ssb_sdio_switch_core(bus, dev)))
3082 + goto out;
3083 + offset |= bus->sdio_sbaddr & 0xffff;
3084 + offset &= SBSDIO_SB_OFT_ADDR_MASK;
3085 + offset |= SBSDIO_SB_ACCESS_2_4B_FLAG; /* 32 bit data access */
3086 + sdio_writel(bus->host_sdio, val, offset, &error);
3087 + if (error) {
3088 + dev_dbg(ssb_sdio_dev(bus), "%04X:%04X < %08x, error %d\n",
3089 + bus->sdio_sbaddr >> 16, offset, val, error);
3090 + }
3091 + if (bus->quirks & SSB_QUIRK_SDIO_READ_AFTER_WRITE32)
3092 + sdio_readl(bus->host_sdio, 0, &error);
3093 +out:
3094 + sdio_release_host(bus->host_sdio);
3095 +}
3096 +
3097 +#ifdef CONFIG_SSB_BLOCKIO
3098 +static void ssb_sdio_block_write(struct ssb_device *dev, const void *buffer,
3099 + size_t count, u16 offset, u8 reg_width)
3100 +{
3101 + size_t saved_count = count;
3102 + struct ssb_bus *bus = dev->bus;
3103 + int error = 0;
3104 +
3105 + sdio_claim_host(bus->host_sdio);
3106 + if (unlikely(ssb_sdio_switch_core(bus, dev))) {
3107 + error = -EIO;
3108 + memset((void *)buffer, 0xff, count);
3109 + goto err_out;
3110 + }
3111 + offset |= bus->sdio_sbaddr & 0xffff;
3112 + offset &= SBSDIO_SB_OFT_ADDR_MASK;
3113 +
3114 + switch (reg_width) {
3115 + case sizeof(u8):
3116 + error = sdio_writesb(bus->host_sdio, offset,
3117 + (void *)buffer, count);
3118 + break;
3119 + case sizeof(u16):
3120 + SSB_WARN_ON(count & 1);
3121 + error = sdio_writesb(bus->host_sdio, offset,
3122 + (void *)buffer, count);
3123 + break;
3124 + case sizeof(u32):
3125 + SSB_WARN_ON(count & 3);
3126 + offset |= SBSDIO_SB_ACCESS_2_4B_FLAG; /* 32 bit data access */
3127 + error = sdio_writesb(bus->host_sdio, offset,
3128 + (void *)buffer, count);
3129 + break;
3130 + default:
3131 + SSB_WARN_ON(1);
3132 + }
3133 + if (!error)
3134 + goto out;
3135 +
3136 +err_out:
3137 + dev_dbg(ssb_sdio_dev(bus), "%04X:%04X (width=%u, len=%zu), error %d\n",
3138 + bus->sdio_sbaddr >> 16, offset, reg_width, saved_count, error);
3139 +out:
3140 + sdio_release_host(bus->host_sdio);
3141 +}
3142 +
3143 +#endif /* CONFIG_SSB_BLOCKIO */
3144 +
3145 +/* Not "static", as it's used in main.c */
3146 +const struct ssb_bus_ops ssb_sdio_ops = {
3147 + .read8 = ssb_sdio_read8,
3148 + .read16 = ssb_sdio_read16,
3149 + .read32 = ssb_sdio_read32,
3150 + .write8 = ssb_sdio_write8,
3151 + .write16 = ssb_sdio_write16,
3152 + .write32 = ssb_sdio_write32,
3153 +#ifdef CONFIG_SSB_BLOCKIO
3154 + .block_read = ssb_sdio_block_read,
3155 + .block_write = ssb_sdio_block_write,
3156 +#endif
3157 +};
3158 +
3159 +#define GOTO_ERROR_ON(condition, description) do { \
3160 + if (unlikely(condition)) { \
3161 + error_description = description; \
3162 + goto error; \
3163 + } \
3164 + } while (0)
3165 +
3166 +int ssb_sdio_get_invariants(struct ssb_bus *bus,
3167 + struct ssb_init_invariants *iv)
3168 +{
3169 + struct ssb_sprom *sprom = &iv->sprom;
3170 + struct ssb_boardinfo *bi = &iv->boardinfo;
3171 + const char *error_description = "none";
3172 + struct sdio_func_tuple *tuple;
3173 + void *mac;
3174 +
3175 + memset(sprom, 0xFF, sizeof(*sprom));
3176 + sprom->boardflags_lo = 0;
3177 + sprom->boardflags_hi = 0;
3178 +
3179 + tuple = bus->host_sdio->tuples;
3180 + while (tuple) {
3181 + switch (tuple->code) {
3182 + case 0x22: /* extended function */
3183 + switch (tuple->data[0]) {
3184 + case CISTPL_FUNCE_LAN_NODE_ID:
3185 + GOTO_ERROR_ON((tuple->size != 7) &&
3186 + (tuple->data[1] != 6),
3187 + "mac tpl size");
3188 + /* fetch the MAC address. */
3189 + mac = tuple->data + 2;
3190 + memcpy(sprom->il0mac, mac, ETH_ALEN);
3191 + memcpy(sprom->et1mac, mac, ETH_ALEN);
3192 + break;
3193 + default:
3194 + break;
3195 + }
3196 + break;
3197 + case 0x80: /* vendor specific tuple */
3198 + switch (tuple->data[0]) {
3199 + case SSB_SDIO_CIS_SROMREV:
3200 + GOTO_ERROR_ON(tuple->size != 2,
3201 + "sromrev tpl size");
3202 + sprom->revision = tuple->data[1];
3203 + break;
3204 + case SSB_SDIO_CIS_ID:
3205 + GOTO_ERROR_ON((tuple->size != 5) &&
3206 + (tuple->size != 7),
3207 + "id tpl size");
3208 + bi->vendor = tuple->data[1] |
3209 + (tuple->data[2]<<8);
3210 + break;
3211 + case SSB_SDIO_CIS_BOARDREV:
3212 + GOTO_ERROR_ON(tuple->size != 2,
3213 + "boardrev tpl size");
3214 + sprom->board_rev = tuple->data[1];
3215 + break;
3216 + case SSB_SDIO_CIS_PA:
3217 + GOTO_ERROR_ON((tuple->size != 9) &&
3218 + (tuple->size != 10),
3219 + "pa tpl size");
3220 + sprom->pa0b0 = tuple->data[1] |
3221 + ((u16)tuple->data[2] << 8);
3222 + sprom->pa0b1 = tuple->data[3] |
3223 + ((u16)tuple->data[4] << 8);
3224 + sprom->pa0b2 = tuple->data[5] |
3225 + ((u16)tuple->data[6] << 8);
3226 + sprom->itssi_a = tuple->data[7];
3227 + sprom->itssi_bg = tuple->data[7];
3228 + sprom->maxpwr_a = tuple->data[8];
3229 + sprom->maxpwr_bg = tuple->data[8];
3230 + break;
3231 + case SSB_SDIO_CIS_OEMNAME:
3232 + /* Not present */
3233 + break;
3234 + case SSB_SDIO_CIS_CCODE:
3235 + GOTO_ERROR_ON(tuple->size != 2,
3236 + "ccode tpl size");
3237 + sprom->country_code = tuple->data[1];
3238 + break;
3239 + case SSB_SDIO_CIS_ANTENNA:
3240 + GOTO_ERROR_ON(tuple->size != 2,
3241 + "ant tpl size");
3242 + sprom->ant_available_a = tuple->data[1];
3243 + sprom->ant_available_bg = tuple->data[1];
3244 + break;
3245 + case SSB_SDIO_CIS_ANTGAIN:
3246 + GOTO_ERROR_ON(tuple->size != 2,
3247 + "antg tpl size");
3248 + sprom->antenna_gain.a0 = tuple->data[1];
3249 + sprom->antenna_gain.a1 = tuple->data[1];
3250 + sprom->antenna_gain.a2 = tuple->data[1];
3251 + sprom->antenna_gain.a3 = tuple->data[1];
3252 + break;
3253 + case SSB_SDIO_CIS_BFLAGS:
3254 + GOTO_ERROR_ON((tuple->size != 3) &&
3255 + (tuple->size != 5),
3256 + "bfl tpl size");
3257 + sprom->boardflags_lo = tuple->data[1] |
3258 + ((u16)tuple->data[2] << 8);
3259 + break;
3260 + case SSB_SDIO_CIS_LEDS:
3261 + GOTO_ERROR_ON(tuple->size != 5,
3262 + "leds tpl size");
3263 + sprom->gpio0 = tuple->data[1];
3264 + sprom->gpio1 = tuple->data[2];
3265 + sprom->gpio2 = tuple->data[3];
3266 + sprom->gpio3 = tuple->data[4];
3267 + break;
3268 + default:
3269 + break;
3270 + }
3271 + break;
3272 + default:
3273 + break;
3274 + }
3275 + tuple = tuple->next;
3276 + }
3277 +
3278 + return 0;
3279 +error:
3280 + dev_err(ssb_sdio_dev(bus), "failed to fetch device invariants: %s\n",
3281 + error_description);
3282 + return -ENODEV;
3283 +}
3284 +
3285 +void ssb_sdio_exit(struct ssb_bus *bus)
3286 +{
3287 + if (bus->bustype != SSB_BUSTYPE_SDIO)
3288 + return;
3289 + /* Nothing to do here. */
3290 +}
3291 +
3292 +int ssb_sdio_init(struct ssb_bus *bus)
3293 +{
3294 + if (bus->bustype != SSB_BUSTYPE_SDIO)
3295 + return 0;
3296 +
3297 + bus->sdio_sbaddr = ~0;
3298 +
3299 + return 0;
3300 +}
3301 --- a/drivers/ssb/sprom.c
3302 +++ b/drivers/ssb/sprom.c
3303 @@ -2,7 +2,7 @@
3304 * Sonics Silicon Backplane
3305 * Common SPROM support routines
3306 *
3307 - * Copyright (C) 2005-2008 Michael Buesch <mb@bu3sch.de>
3308 + * Copyright (C) 2005-2008 Michael Buesch <m@bues.ch>
3309 * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
3310 * Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
3311 * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
3312 @@ -13,8 +13,11 @@
3313
3314 #include "ssb_private.h"
3315
3316 +#include <linux/ctype.h>
3317 +#include <linux/slab.h>
3318
3319 -static const struct ssb_sprom *fallback_sprom;
3320 +
3321 +static int(*get_fallback_sprom)(struct ssb_bus *dev, struct ssb_sprom *out);
3322
3323
3324 static int sprom2hex(const u16 *sprom, char *buf, size_t buf_len,
3325 @@ -33,17 +36,27 @@ static int sprom2hex(const u16 *sprom, c
3326 static int hex2sprom(u16 *sprom, const char *dump, size_t len,
3327 size_t sprom_size_words)
3328 {
3329 - char tmp[5] = { 0 };
3330 - int cnt = 0;
3331 + char c, tmp[5] = { 0 };
3332 + int err, cnt = 0;
3333 unsigned long parsed;
3334
3335 - if (len < sprom_size_words * 2)
3336 + /* Strip whitespace at the end. */
3337 + while (len) {
3338 + c = dump[len - 1];
3339 + if (!isspace(c) && c != '\0')
3340 + break;
3341 + len--;
3342 + }
3343 + /* Length must match exactly. */
3344 + if (len != sprom_size_words * 4)
3345 return -EINVAL;
3346
3347 while (cnt < sprom_size_words) {
3348 memcpy(tmp, dump, 4);
3349 dump += 4;
3350 - parsed = simple_strtoul(tmp, NULL, 16);
3351 + err = strict_strtoul(tmp, 16, &parsed);
3352 + if (err)
3353 + return err;
3354 sprom[cnt++] = swab16((u16)parsed);
3355 }
3356
3357 @@ -90,6 +103,7 @@ ssize_t ssb_attr_sprom_store(struct ssb_
3358 u16 *sprom;
3359 int res = 0, err = -ENOMEM;
3360 size_t sprom_size_words = bus->sprom_size;
3361 + struct ssb_freeze_context freeze;
3362
3363 sprom = kcalloc(bus->sprom_size, sizeof(u16), GFP_KERNEL);
3364 if (!sprom)
3365 @@ -111,18 +125,13 @@ ssize_t ssb_attr_sprom_store(struct ssb_
3366 err = -ERESTARTSYS;
3367 if (mutex_lock_interruptible(&bus->sprom_mutex))
3368 goto out_kfree;
3369 - err = ssb_devices_freeze(bus);
3370 - if (err == -EOPNOTSUPP) {
3371 - ssb_printk(KERN_ERR PFX "SPROM write: Could not freeze devices. "
3372 - "No suspend support. Is CONFIG_PM enabled?\n");
3373 - goto out_unlock;
3374 - }
3375 + err = ssb_devices_freeze(bus, &freeze);
3376 if (err) {
3377 ssb_printk(KERN_ERR PFX "SPROM write: Could not freeze all devices\n");
3378 goto out_unlock;
3379 }
3380 res = sprom_write(bus, sprom);
3381 - err = ssb_devices_thaw(bus);
3382 + err = ssb_devices_thaw(&freeze);
3383 if (err)
3384 ssb_printk(KERN_ERR PFX "SPROM write: Could not thaw all devices\n");
3385 out_unlock:
3386 @@ -136,34 +145,56 @@ out:
3387 }
3388
3389 /**
3390 - * ssb_arch_set_fallback_sprom - Set a fallback SPROM for use if no SPROM is found.
3391 - *
3392 - * @sprom: The SPROM data structure to register.
3393 - *
3394 - * With this function the architecture implementation may register a fallback
3395 - * SPROM data structure. The fallback is only used for PCI based SSB devices,
3396 - * where no valid SPROM can be found in the shadow registers.
3397 + * ssb_arch_register_fallback_sprom - Registers a method providing a
3398 + * fallback SPROM if no SPROM is found.
3399 *
3400 - * This function is useful for weird architectures that have a half-assed SSB device
3401 - * hardwired to their PCI bus.
3402 + * @sprom_callback: The callback function.
3403 *
3404 - * Note that it does only work with PCI attached SSB devices. PCMCIA devices currently
3405 - * don't use this fallback.
3406 - * Architectures must provide the SPROM for native SSB devices anyway,
3407 - * so the fallback also isn't used for native devices.
3408 + * With this function the architecture implementation may register a
3409 + * callback handler which fills the SPROM data structure. The fallback is
3410 + * only used for PCI based SSB devices, where no valid SPROM can be found
3411 + * in the shadow registers.
3412 + *
3413 + * This function is useful for weird architectures that have a half-assed
3414 + * SSB device hardwired to their PCI bus.
3415 + *
3416 + * Note that it does only work with PCI attached SSB devices. PCMCIA
3417 + * devices currently don't use this fallback.
3418 + * Architectures must provide the SPROM for native SSB devices anyway, so
3419 + * the fallback also isn't used for native devices.
3420 *
3421 - * This function is available for architecture code, only. So it is not exported.
3422 + * This function is available for architecture code, only. So it is not
3423 + * exported.
3424 */
3425 -int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom)
3426 +int ssb_arch_register_fallback_sprom(int (*sprom_callback)(struct ssb_bus *bus,
3427 + struct ssb_sprom *out))
3428 {
3429 - if (fallback_sprom)
3430 + if (get_fallback_sprom)
3431 return -EEXIST;
3432 - fallback_sprom = sprom;
3433 + get_fallback_sprom = sprom_callback;
3434
3435 return 0;
3436 }
3437
3438 -const struct ssb_sprom *ssb_get_fallback_sprom(void)
3439 +int ssb_fill_sprom_with_fallback(struct ssb_bus *bus, struct ssb_sprom *out)
3440 {
3441 - return fallback_sprom;
3442 + if (!get_fallback_sprom)
3443 + return -ENOENT;
3444 +
3445 + return get_fallback_sprom(bus, out);
3446 +}
3447 +
3448 +/* http://bcm-v4.sipsolutions.net/802.11/IsSpromAvailable */
3449 +bool ssb_is_sprom_available(struct ssb_bus *bus)
3450 +{
3451 + /* status register only exists on chipcomon rev >= 11 and we need check
3452 + for >= 31 only */
3453 + /* this routine differs from specs as we do not access SPROM directly
3454 + on PCMCIA */
3455 + if (bus->bustype == SSB_BUSTYPE_PCI &&
3456 + bus->chipco.dev && /* can be unavailable! */
3457 + bus->chipco.dev->id.revision >= 31)
3458 + return bus->chipco.capabilities & SSB_CHIPCO_CAP_SPROM;
3459 +
3460 + return true;
3461 }
3462 --- a/drivers/ssb/ssb_private.h
3463 +++ b/drivers/ssb/ssb_private.h
3464 @@ -114,6 +114,46 @@ static inline int ssb_pcmcia_init(struct
3465 }
3466 #endif /* CONFIG_SSB_PCMCIAHOST */
3467
3468 +/* sdio.c */
3469 +#ifdef CONFIG_SSB_SDIOHOST
3470 +extern int ssb_sdio_get_invariants(struct ssb_bus *bus,
3471 + struct ssb_init_invariants *iv);
3472 +
3473 +extern u32 ssb_sdio_scan_read32(struct ssb_bus *bus, u16 offset);
3474 +extern int ssb_sdio_switch_core(struct ssb_bus *bus, struct ssb_device *dev);
3475 +extern int ssb_sdio_scan_switch_coreidx(struct ssb_bus *bus, u8 coreidx);
3476 +extern int ssb_sdio_hardware_setup(struct ssb_bus *bus);
3477 +extern void ssb_sdio_exit(struct ssb_bus *bus);
3478 +extern int ssb_sdio_init(struct ssb_bus *bus);
3479 +
3480 +extern const struct ssb_bus_ops ssb_sdio_ops;
3481 +#else /* CONFIG_SSB_SDIOHOST */
3482 +static inline u32 ssb_sdio_scan_read32(struct ssb_bus *bus, u16 offset)
3483 +{
3484 + return 0;
3485 +}
3486 +static inline int ssb_sdio_switch_core(struct ssb_bus *bus,
3487 + struct ssb_device *dev)
3488 +{
3489 + return 0;
3490 +}
3491 +static inline int ssb_sdio_scan_switch_coreidx(struct ssb_bus *bus, u8 coreidx)
3492 +{
3493 + return 0;
3494 +}
3495 +static inline int ssb_sdio_hardware_setup(struct ssb_bus *bus)
3496 +{
3497 + return 0;
3498 +}
3499 +static inline void ssb_sdio_exit(struct ssb_bus *bus)
3500 +{
3501 +}
3502 +static inline int ssb_sdio_init(struct ssb_bus *bus)
3503 +{
3504 + return 0;
3505 +}
3506 +#endif /* CONFIG_SSB_SDIOHOST */
3507 +
3508
3509 /* scan.c */
3510 extern const char *ssb_core_name(u16 coreid);
3511 @@ -131,24 +171,33 @@ ssize_t ssb_attr_sprom_store(struct ssb_
3512 const char *buf, size_t count,
3513 int (*sprom_check_crc)(const u16 *sprom, size_t size),
3514 int (*sprom_write)(struct ssb_bus *bus, const u16 *sprom));
3515 -extern const struct ssb_sprom *ssb_get_fallback_sprom(void);
3516 +extern int ssb_fill_sprom_with_fallback(struct ssb_bus *bus,
3517 + struct ssb_sprom *out);
3518
3519
3520 /* core.c */
3521 extern u32 ssb_calc_clock_rate(u32 plltype, u32 n, u32 m);
3522 -extern int ssb_devices_freeze(struct ssb_bus *bus);
3523 -extern int ssb_devices_thaw(struct ssb_bus *bus);
3524 extern struct ssb_bus *ssb_pci_dev_to_bus(struct pci_dev *pdev);
3525 int ssb_for_each_bus_call(unsigned long data,
3526 int (*func)(struct ssb_bus *bus, unsigned long data));
3527 extern struct ssb_bus *ssb_pcmcia_dev_to_bus(struct pcmcia_device *pdev);
3528
3529 +struct ssb_freeze_context {
3530 + /* Pointer to the bus */
3531 + struct ssb_bus *bus;
3532 + /* Boolean list to indicate whether a device is frozen on this bus. */
3533 + bool device_frozen[SSB_MAX_NR_CORES];
3534 +};
3535 +extern int ssb_devices_freeze(struct ssb_bus *bus, struct ssb_freeze_context *ctx);
3536 +extern int ssb_devices_thaw(struct ssb_freeze_context *ctx);
3537 +
3538 +
3539
3540 /* b43_pci_bridge.c */
3541 #ifdef CONFIG_SSB_B43_PCI_BRIDGE
3542 extern int __init b43_pci_ssb_bridge_init(void);
3543 extern void __exit b43_pci_ssb_bridge_exit(void);
3544 -#else /* CONFIG_SSB_B43_PCI_BRIDGR */
3545 +#else /* CONFIG_SSB_B43_PCI_BRIDGE */
3546 static inline int b43_pci_ssb_bridge_init(void)
3547 {
3548 return 0;
3549 @@ -156,6 +205,10 @@ static inline int b43_pci_ssb_bridge_ini
3550 static inline void b43_pci_ssb_bridge_exit(void)
3551 {
3552 }
3553 -#endif /* CONFIG_SSB_PCIHOST */
3554 +#endif /* CONFIG_SSB_B43_PCI_BRIDGE */
3555 +
3556 +/* driver_chipcommon_pmu.c */
3557 +extern u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc);
3558 +extern u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc);
3559
3560 #endif /* LINUX_SSB_PRIVATE_H_ */
3561 --- a/include/linux/pci_ids.h
3562 +++ b/include/linux/pci_ids.h
3563 @@ -2034,6 +2034,7 @@
3564 #define PCI_DEVICE_ID_AFAVLAB_P030 0x2182
3565 #define PCI_SUBDEVICE_ID_AFAVLAB_P061 0x2150
3566
3567 +#define PCI_VENDOR_ID_BCM_GVC 0x14a4
3568 #define PCI_VENDOR_ID_BROADCOM 0x14e4
3569 #define PCI_DEVICE_ID_TIGON3_5752 0x1600
3570 #define PCI_DEVICE_ID_TIGON3_5752M 0x1601
3571 --- a/include/linux/ssb/ssb.h
3572 +++ b/include/linux/ssb/ssb.h
3573 @@ -16,6 +16,12 @@ struct pcmcia_device;
3574 struct ssb_bus;
3575 struct ssb_driver;
3576
3577 +struct ssb_sprom_core_pwr_info {
3578 + u8 itssi_2g, itssi_5g;
3579 + u8 maxpwr_2g, maxpwr_5gl, maxpwr_5g, maxpwr_5gh;
3580 + u16 pa_2g[4], pa_5gl[4], pa_5g[4], pa_5gh[4];
3581 +};
3582 +
3583 struct ssb_sprom {
3584 u8 revision;
3585 u8 il0mac[6]; /* MAC address for 802.11b/g */
3586 @@ -25,47 +31,164 @@ struct ssb_sprom {
3587 u8 et1phyaddr; /* MII address for enet1 */
3588 u8 et0mdcport; /* MDIO for enet0 */
3589 u8 et1mdcport; /* MDIO for enet1 */
3590 - u8 board_rev; /* Board revision number from SPROM. */
3591 + u16 board_rev; /* Board revision number from SPROM. */
3592 + u16 board_num; /* Board number from SPROM. */
3593 + u16 board_type; /* Board type from SPROM. */
3594 u8 country_code; /* Country Code */
3595 - u8 ant_available_a; /* A-PHY antenna available bits (up to 4) */
3596 - u8 ant_available_bg; /* B/G-PHY antenna available bits (up to 4) */
3597 + char alpha2[2]; /* Country Code as two chars like EU or US */
3598 + u8 leddc_on_time; /* LED Powersave Duty Cycle On Count */
3599 + u8 leddc_off_time; /* LED Powersave Duty Cycle Off Count */
3600 + u8 ant_available_a; /* 2GHz antenna available bits (up to 4) */
3601 + u8 ant_available_bg; /* 5GHz antenna available bits (up to 4) */
3602 u16 pa0b0;
3603 u16 pa0b1;
3604 u16 pa0b2;
3605 u16 pa1b0;
3606 u16 pa1b1;
3607 u16 pa1b2;
3608 + u16 pa1lob0;
3609 + u16 pa1lob1;
3610 + u16 pa1lob2;
3611 + u16 pa1hib0;
3612 + u16 pa1hib1;
3613 + u16 pa1hib2;
3614 u8 gpio0; /* GPIO pin 0 */
3615 u8 gpio1; /* GPIO pin 1 */
3616 u8 gpio2; /* GPIO pin 2 */
3617 u8 gpio3; /* GPIO pin 3 */
3618 - u16 maxpwr_a; /* A-PHY Amplifier Max Power (in dBm Q5.2) */
3619 - u16 maxpwr_bg; /* B/G-PHY Amplifier Max Power (in dBm Q5.2) */
3620 + u8 maxpwr_bg; /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */
3621 + u8 maxpwr_al; /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */
3622 + u8 maxpwr_a; /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */
3623 + u8 maxpwr_ah; /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */
3624 u8 itssi_a; /* Idle TSSI Target for A-PHY */
3625 u8 itssi_bg; /* Idle TSSI Target for B/G-PHY */
3626 - u16 boardflags_lo; /* Boardflags (low 16 bits) */
3627 - u16 boardflags_hi; /* Boardflags (high 16 bits) */
3628 + u8 tri2g; /* 2.4GHz TX isolation */
3629 + u8 tri5gl; /* 5.2GHz TX isolation */
3630 + u8 tri5g; /* 5.3GHz TX isolation */
3631 + u8 tri5gh; /* 5.8GHz TX isolation */
3632 + u8 txpid2g[4]; /* 2GHz TX power index */
3633 + u8 txpid5gl[4]; /* 4.9 - 5.1GHz TX power index */
3634 + u8 txpid5g[4]; /* 5.1 - 5.5GHz TX power index */
3635 + u8 txpid5gh[4]; /* 5.5 - ...GHz TX power index */
3636 + s8 rxpo2g; /* 2GHz RX power offset */
3637 + s8 rxpo5g; /* 5GHz RX power offset */
3638 + u8 rssisav2g; /* 2GHz RSSI params */
3639 + u8 rssismc2g;
3640 + u8 rssismf2g;
3641 + u8 bxa2g; /* 2GHz BX arch */
3642 + u8 rssisav5g; /* 5GHz RSSI params */
3643 + u8 rssismc5g;
3644 + u8 rssismf5g;
3645 + u8 bxa5g; /* 5GHz BX arch */
3646 + u16 cck2gpo; /* CCK power offset */
3647 + u32 ofdm2gpo; /* 2.4GHz OFDM power offset */
3648 + u32 ofdm5glpo; /* 5.2GHz OFDM power offset */
3649 + u32 ofdm5gpo; /* 5.3GHz OFDM power offset */
3650 + u32 ofdm5ghpo; /* 5.8GHz OFDM power offset */
3651 + u16 boardflags_lo; /* Board flags (bits 0-15) */
3652 + u16 boardflags_hi; /* Board flags (bits 16-31) */
3653 + u16 boardflags2_lo; /* Board flags (bits 32-47) */
3654 + u16 boardflags2_hi; /* Board flags (bits 48-63) */
3655 + /* TODO store board flags in a single u64 */
3656 +
3657 + struct ssb_sprom_core_pwr_info core_pwr_info[4];
3658
3659 /* Antenna gain values for up to 4 antennas
3660 * on each band. Values in dBm/4 (Q5.2). Negative gain means the
3661 * loss in the connectors is bigger than the gain. */
3662 struct {
3663 - struct {
3664 - s8 a0, a1, a2, a3;
3665 - } ghz24; /* 2.4GHz band */
3666 - struct {
3667 - s8 a0, a1, a2, a3;
3668 - } ghz5; /* 5GHz band */
3669 + s8 a0, a1, a2, a3;
3670 } antenna_gain;
3671
3672 - /* TODO - add any parameters needed from rev 2, 3, or 4 SPROMs */
3673 + struct {
3674 + struct {
3675 + u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
3676 + } ghz2;
3677 + struct {
3678 + u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
3679 + } ghz5;
3680 + } fem;
3681 +
3682 + u16 mcs2gpo[8];
3683 + u16 mcs5gpo[8];
3684 + u16 mcs5glpo[8];
3685 + u16 mcs5ghpo[8];
3686 + u8 opo;
3687 +
3688 + u8 rxgainerr2ga[3];
3689 + u8 rxgainerr5gla[3];
3690 + u8 rxgainerr5gma[3];
3691 + u8 rxgainerr5gha[3];
3692 + u8 rxgainerr5gua[3];
3693 +
3694 + u8 noiselvl2ga[3];
3695 + u8 noiselvl5gla[3];
3696 + u8 noiselvl5gma[3];
3697 + u8 noiselvl5gha[3];
3698 + u8 noiselvl5gua[3];
3699 +
3700 + u8 regrev;
3701 + u8 txchain;
3702 + u8 rxchain;
3703 + u8 antswitch;
3704 + u16 cddpo;
3705 + u16 stbcpo;
3706 + u16 bw40po;
3707 + u16 bwduppo;
3708 +
3709 + u8 tempthresh;
3710 + u8 tempoffset;
3711 + u16 rawtempsense;
3712 + u8 measpower;
3713 + u8 tempsense_slope;
3714 + u8 tempcorrx;
3715 + u8 tempsense_option;
3716 + u8 freqoffset_corr;
3717 + u8 iqcal_swp_dis;
3718 + u8 hw_iqcal_en;
3719 + u8 elna2g;
3720 + u8 elna5g;
3721 + u8 phycal_tempdelta;
3722 + u8 temps_period;
3723 + u8 temps_hysteresis;
3724 + u8 measpower1;
3725 + u8 measpower2;
3726 + u8 pcieingress_war;
3727 +
3728 + /* power per rate from sromrev 9 */
3729 + u16 cckbw202gpo;
3730 + u16 cckbw20ul2gpo;
3731 + u32 legofdmbw202gpo;
3732 + u32 legofdmbw20ul2gpo;
3733 + u32 legofdmbw205glpo;
3734 + u32 legofdmbw20ul5glpo;
3735 + u32 legofdmbw205gmpo;
3736 + u32 legofdmbw20ul5gmpo;
3737 + u32 legofdmbw205ghpo;
3738 + u32 legofdmbw20ul5ghpo;
3739 + u32 mcsbw202gpo;
3740 + u32 mcsbw20ul2gpo;
3741 + u32 mcsbw402gpo;
3742 + u32 mcsbw205glpo;
3743 + u32 mcsbw20ul5glpo;
3744 + u32 mcsbw405glpo;
3745 + u32 mcsbw205gmpo;
3746 + u32 mcsbw20ul5gmpo;
3747 + u32 mcsbw405gmpo;
3748 + u32 mcsbw205ghpo;
3749 + u32 mcsbw20ul5ghpo;
3750 + u32 mcsbw405ghpo;
3751 + u16 mcs32po;
3752 + u16 legofdm40duppo;
3753 + u8 sar2g;
3754 + u8 sar5g;
3755 };
3756
3757 /* Information about the PCB the circuitry is soldered on. */
3758 struct ssb_boardinfo {
3759 u16 vendor;
3760 u16 type;
3761 - u16 rev;
3762 + u8 rev;
3763 };
3764
3765
3766 @@ -137,7 +260,7 @@ struct ssb_device {
3767 * is an optimization. */
3768 const struct ssb_bus_ops *ops;
3769
3770 - struct device *dev;
3771 + struct device *dev, *dma_dev;
3772
3773 struct ssb_bus *bus;
3774 struct ssb_device_id id;
3775 @@ -195,10 +318,9 @@ struct ssb_driver {
3776 #define drv_to_ssb_drv(_drv) container_of(_drv, struct ssb_driver, drv)
3777
3778 extern int __ssb_driver_register(struct ssb_driver *drv, struct module *owner);
3779 -static inline int ssb_driver_register(struct ssb_driver *drv)
3780 -{
3781 - return __ssb_driver_register(drv, THIS_MODULE);
3782 -}
3783 +#define ssb_driver_register(drv) \
3784 + __ssb_driver_register(drv, THIS_MODULE)
3785 +
3786 extern void ssb_driver_unregister(struct ssb_driver *drv);
3787
3788
3789 @@ -208,6 +330,7 @@ enum ssb_bustype {
3790 SSB_BUSTYPE_SSB, /* This SSB bus is the system bus */
3791 SSB_BUSTYPE_PCI, /* SSB is connected to PCI bus */
3792 SSB_BUSTYPE_PCMCIA, /* SSB is connected to PCMCIA bus */
3793 + SSB_BUSTYPE_SDIO, /* SSB is connected to SDIO bus */
3794 };
3795
3796 /* board_vendor */
3797 @@ -238,20 +361,33 @@ struct ssb_bus {
3798
3799 const struct ssb_bus_ops *ops;
3800
3801 - /* The core in the basic address register window. (PCI bus only) */
3802 + /* The core currently mapped into the MMIO window.
3803 + * Not valid on all host-buses. So don't use outside of SSB. */
3804 struct ssb_device *mapped_device;
3805 - /* Currently mapped PCMCIA segment. (bustype == SSB_BUSTYPE_PCMCIA only) */
3806 - u8 mapped_pcmcia_seg;
3807 + union {
3808 + /* Currently mapped PCMCIA segment. (bustype == SSB_BUSTYPE_PCMCIA only) */
3809 + u8 mapped_pcmcia_seg;
3810 + /* Current SSB base address window for SDIO. */
3811 + u32 sdio_sbaddr;
3812 + };
3813 /* Lock for core and segment switching.
3814 * On PCMCIA-host busses this is used to protect the whole MMIO access. */
3815 spinlock_t bar_lock;
3816
3817 - /* The bus this backplane is running on. */
3818 + /* The host-bus this backplane is running on. */
3819 enum ssb_bustype bustype;
3820 - /* Pointer to the PCI bus (only valid if bustype == SSB_BUSTYPE_PCI). */
3821 - struct pci_dev *host_pci;
3822 - /* Pointer to the PCMCIA device (only if bustype == SSB_BUSTYPE_PCMCIA). */
3823 - struct pcmcia_device *host_pcmcia;
3824 + /* Pointers to the host-bus. Check bustype before using any of these pointers. */
3825 + union {
3826 + /* Pointer to the PCI bus (only valid if bustype == SSB_BUSTYPE_PCI). */
3827 + struct pci_dev *host_pci;
3828 + /* Pointer to the PCMCIA device (only if bustype == SSB_BUSTYPE_PCMCIA). */
3829 + struct pcmcia_device *host_pcmcia;
3830 + /* Pointer to the SDIO device (only if bustype == SSB_BUSTYPE_SDIO). */
3831 + struct sdio_func *host_sdio;
3832 + };
3833 +
3834 + /* See enum ssb_quirks */
3835 + unsigned int quirks;
3836
3837 #ifdef CONFIG_SSB_SPROM
3838 /* Mutex to protect the SPROM writing. */
3839 @@ -260,7 +396,8 @@ struct ssb_bus {
3840
3841 /* ID information about the Chip. */
3842 u16 chip_id;
3843 - u16 chip_rev;
3844 + u8 chip_rev;
3845 + u16 sprom_offset;
3846 u16 sprom_size; /* number of words in sprom */
3847 u8 chip_package;
3848
3849 @@ -306,6 +443,11 @@ struct ssb_bus {
3850 #endif /* DEBUG */
3851 };
3852
3853 +enum ssb_quirks {
3854 + /* SDIO connected card requires performing a read after writing a 32-bit value */
3855 + SSB_QUIRK_SDIO_READ_AFTER_WRITE32 = (1 << 0),
3856 +};
3857 +
3858 /* The initialization-invariants. */
3859 struct ssb_init_invariants {
3860 /* Versioning information about the PCB. */
3861 @@ -336,12 +478,23 @@ extern int ssb_bus_pcmciabus_register(st
3862 struct pcmcia_device *pcmcia_dev,
3863 unsigned long baseaddr);
3864 #endif /* CONFIG_SSB_PCMCIAHOST */
3865 +#ifdef CONFIG_SSB_SDIOHOST
3866 +extern int ssb_bus_sdiobus_register(struct ssb_bus *bus,
3867 + struct sdio_func *sdio_func,
3868 + unsigned int quirks);
3869 +#endif /* CONFIG_SSB_SDIOHOST */
3870 +
3871
3872 extern void ssb_bus_unregister(struct ssb_bus *bus);
3873
3874 +/* Does the device have an SPROM? */
3875 +extern bool ssb_is_sprom_available(struct ssb_bus *bus);
3876 +
3877 /* Set a fallback SPROM.
3878 * See kdoc at the function definition for complete documentation. */
3879 -extern int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom);
3880 +extern int ssb_arch_register_fallback_sprom(
3881 + int (*sprom_callback)(struct ssb_bus *bus,
3882 + struct ssb_sprom *out));
3883
3884 /* Suspend a SSB bus.
3885 * Call this from the parent bus suspend routine. */
3886 @@ -612,6 +765,7 @@ extern int ssb_bus_may_powerdown(struct
3887 * Otherwise static always-on powercontrol will be used. */
3888 extern int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl);
3889
3890 +extern void ssb_commit_settings(struct ssb_bus *bus);
3891
3892 /* Various helper functions */
3893 extern u32 ssb_admatch_base(u32 adm);
3894 --- a/include/linux/ssb/ssb_driver_chipcommon.h
3895 +++ b/include/linux/ssb/ssb_driver_chipcommon.h
3896 @@ -8,7 +8,7 @@
3897 * gpio interface, extbus, and support for serial and parallel flashes.
3898 *
3899 * Copyright 2005, Broadcom Corporation
3900 - * Copyright 2006, Michael Buesch <mb@bu3sch.de>
3901 + * Copyright 2006, Michael Buesch <m@bues.ch>
3902 *
3903 * Licensed under the GPL version 2. See COPYING for details.
3904 */
3905 @@ -53,6 +53,7 @@
3906 #define SSB_CHIPCO_CAP_64BIT 0x08000000 /* 64-bit Backplane */
3907 #define SSB_CHIPCO_CAP_PMU 0x10000000 /* PMU available (rev >= 20) */
3908 #define SSB_CHIPCO_CAP_ECI 0x20000000 /* ECI available (rev >= 20) */
3909 +#define SSB_CHIPCO_CAP_SPROM 0x40000000 /* SPROM present */
3910 #define SSB_CHIPCO_CORECTL 0x0008
3911 #define SSB_CHIPCO_CORECTL_UARTCLK0 0x00000001 /* Drive UART with internal clock */
3912 #define SSB_CHIPCO_CORECTL_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
3913 @@ -122,6 +123,8 @@
3914 #define SSB_CHIPCO_FLASHDATA 0x0048
3915 #define SSB_CHIPCO_BCAST_ADDR 0x0050
3916 #define SSB_CHIPCO_BCAST_DATA 0x0054
3917 +#define SSB_CHIPCO_GPIOPULLUP 0x0058 /* Rev >= 20 only */
3918 +#define SSB_CHIPCO_GPIOPULLDOWN 0x005C /* Rev >= 20 only */
3919 #define SSB_CHIPCO_GPIOIN 0x0060
3920 #define SSB_CHIPCO_GPIOOUT 0x0064
3921 #define SSB_CHIPCO_GPIOOUTEN 0x0068
3922 @@ -130,6 +133,9 @@
3923 #define SSB_CHIPCO_GPIOIRQ 0x0074
3924 #define SSB_CHIPCO_WATCHDOG 0x0080
3925 #define SSB_CHIPCO_GPIOTIMER 0x0088 /* LED powersave (corerev >= 16) */
3926 +#define SSB_CHIPCO_GPIOTIMER_OFFTIME 0x0000FFFF
3927 +#define SSB_CHIPCO_GPIOTIMER_OFFTIME_SHIFT 0
3928 +#define SSB_CHIPCO_GPIOTIMER_ONTIME 0xFFFF0000
3929 #define SSB_CHIPCO_GPIOTIMER_ONTIME_SHIFT 16
3930 #define SSB_CHIPCO_GPIOTOUTM 0x008C /* LED powersave (corerev >= 16) */
3931 #define SSB_CHIPCO_CLOCK_N 0x0090
3932 @@ -188,8 +194,10 @@
3933 #define SSB_CHIPCO_CLKCTLST_HAVEALPREQ 0x00000008 /* ALP available request */
3934 #define SSB_CHIPCO_CLKCTLST_HAVEHTREQ 0x00000010 /* HT available request */
3935 #define SSB_CHIPCO_CLKCTLST_HWCROFF 0x00000020 /* Force HW clock request off */
3936 -#define SSB_CHIPCO_CLKCTLST_HAVEHT 0x00010000 /* HT available */
3937 -#define SSB_CHIPCO_CLKCTLST_HAVEALP 0x00020000 /* APL available */
3938 +#define SSB_CHIPCO_CLKCTLST_HAVEALP 0x00010000 /* ALP available */
3939 +#define SSB_CHIPCO_CLKCTLST_HAVEHT 0x00020000 /* HT available */
3940 +#define SSB_CHIPCO_CLKCTLST_4328A0_HAVEHT 0x00010000 /* 4328a0 has reversed bits */
3941 +#define SSB_CHIPCO_CLKCTLST_4328A0_HAVEALP 0x00020000 /* 4328a0 has reversed bits */
3942 #define SSB_CHIPCO_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */
3943 #define SSB_CHIPCO_UART0_DATA 0x0300
3944 #define SSB_CHIPCO_UART0_IMR 0x0304
3945 @@ -385,6 +393,7 @@
3946
3947
3948 /** Chip specific Chip-Status register contents. */
3949 +#define SSB_CHIPCO_CHST_4322_SPROM_EXISTS 0x00000040 /* SPROM present */
3950 #define SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL 0x00000003
3951 #define SSB_CHIPCO_CHST_4325_DEFCIS_SEL 0 /* OTP is powered up, use def. CIS, no SPROM */
3952 #define SSB_CHIPCO_CHST_4325_SPROM_SEL 1 /* OTP is powered up, SPROM is present */
3953 @@ -398,6 +407,18 @@
3954 #define SSB_CHIPCO_CHST_4325_RCAL_VALUE_SHIFT 4
3955 #define SSB_CHIPCO_CHST_4325_PMUTOP_2B 0x00000200 /* 1 for 2b, 0 for to 2a */
3956
3957 +/** Macros to determine SPROM presence based on Chip-Status register. */
3958 +#define SSB_CHIPCO_CHST_4312_SPROM_PRESENT(status) \
3959 + ((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
3960 + SSB_CHIPCO_CHST_4325_OTP_SEL)
3961 +#define SSB_CHIPCO_CHST_4322_SPROM_PRESENT(status) \
3962 + (status & SSB_CHIPCO_CHST_4322_SPROM_EXISTS)
3963 +#define SSB_CHIPCO_CHST_4325_SPROM_PRESENT(status) \
3964 + (((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
3965 + SSB_CHIPCO_CHST_4325_DEFCIS_SEL) && \
3966 + ((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
3967 + SSB_CHIPCO_CHST_4325_OTP_SEL))
3968 +
3969
3970
3971 /** Clockcontrol masks and values **/
3972 @@ -564,6 +585,7 @@ struct ssb_chipcommon_pmu {
3973 struct ssb_chipcommon {
3974 struct ssb_device *dev;
3975 u32 capabilities;
3976 + u32 status;
3977 /* Fast Powerup Delay constant */
3978 u16 fast_pwrup_delay;
3979 struct ssb_chipcommon_pmu pmu;
3980 @@ -629,5 +651,15 @@ extern int ssb_chipco_serial_init(struct
3981 /* PMU support */
3982 extern void ssb_pmu_init(struct ssb_chipcommon *cc);
3983
3984 +enum ssb_pmu_ldo_volt_id {
3985 + LDO_PAREF = 0,
3986 + LDO_VOLT1,
3987 + LDO_VOLT2,
3988 + LDO_VOLT3,
3989 +};
3990 +
3991 +void ssb_pmu_set_ldo_voltage(struct ssb_chipcommon *cc,
3992 + enum ssb_pmu_ldo_volt_id id, u32 voltage);
3993 +void ssb_pmu_set_ldo_paref(struct ssb_chipcommon *cc, bool on);
3994
3995 #endif /* LINUX_SSB_CHIPCO_H_ */
3996 --- a/include/linux/ssb/ssb_regs.h
3997 +++ b/include/linux/ssb/ssb_regs.h
3998 @@ -85,6 +85,8 @@
3999 #define SSB_IMSTATE_AP_RSV 0x00000030 /* Reserved */
4000 #define SSB_IMSTATE_IBE 0x00020000 /* In Band Error */
4001 #define SSB_IMSTATE_TO 0x00040000 /* Timeout */
4002 +#define SSB_IMSTATE_BUSY 0x01800000 /* Busy (Backplane rev >= 2.3 only) */
4003 +#define SSB_IMSTATE_REJECT 0x02000000 /* Reject (Backplane rev >= 2.3 only) */
4004 #define SSB_INTVEC 0x0F94 /* SB Interrupt Mask */
4005 #define SSB_INTVEC_PCI 0x00000001 /* Enable interrupts for PCI */
4006 #define SSB_INTVEC_ENET0 0x00000002 /* Enable interrupts for enet 0 */
4007 @@ -95,7 +97,7 @@
4008 #define SSB_INTVEC_ENET1 0x00000040 /* Enable interrupts for enet 1 */
4009 #define SSB_TMSLOW 0x0F98 /* SB Target State Low */
4010 #define SSB_TMSLOW_RESET 0x00000001 /* Reset */
4011 -#define SSB_TMSLOW_REJECT_22 0x00000002 /* Reject (Backplane rev 2.2) */
4012 +#define SSB_TMSLOW_REJECT 0x00000002 /* Reject (Standard Backplane) */
4013 #define SSB_TMSLOW_REJECT_23 0x00000004 /* Reject (Backplane rev 2.3) */
4014 #define SSB_TMSLOW_CLOCK 0x00010000 /* Clock Enable */
4015 #define SSB_TMSLOW_FGC 0x00020000 /* Force Gated Clocks On */
4016 @@ -162,7 +164,7 @@
4017
4018 /* SPROM shadow area. If not otherwise noted, fields are
4019 * two bytes wide. Note that the SPROM can _only_ be read
4020 - * in two-byte quantinies.
4021 + * in two-byte quantities.
4022 */
4023 #define SSB_SPROMSIZE_WORDS 64
4024 #define SSB_SPROMSIZE_BYTES (SSB_SPROMSIZE_WORDS * sizeof(u16))
4025 @@ -170,26 +172,27 @@
4026 #define SSB_SPROMSIZE_WORDS_R4 220
4027 #define SSB_SPROMSIZE_BYTES_R123 (SSB_SPROMSIZE_WORDS_R123 * sizeof(u16))
4028 #define SSB_SPROMSIZE_BYTES_R4 (SSB_SPROMSIZE_WORDS_R4 * sizeof(u16))
4029 -#define SSB_SPROM_BASE 0x1000
4030 -#define SSB_SPROM_REVISION 0x107E
4031 +#define SSB_SPROM_BASE1 0x1000
4032 +#define SSB_SPROM_BASE31 0x0800
4033 +#define SSB_SPROM_REVISION 0x007E
4034 #define SSB_SPROM_REVISION_REV 0x00FF /* SPROM Revision number */
4035 #define SSB_SPROM_REVISION_CRC 0xFF00 /* SPROM CRC8 value */
4036 #define SSB_SPROM_REVISION_CRC_SHIFT 8
4037
4038 /* SPROM Revision 1 */
4039 -#define SSB_SPROM1_SPID 0x1004 /* Subsystem Product ID for PCI */
4040 -#define SSB_SPROM1_SVID 0x1006 /* Subsystem Vendor ID for PCI */
4041 -#define SSB_SPROM1_PID 0x1008 /* Product ID for PCI */
4042 -#define SSB_SPROM1_IL0MAC 0x1048 /* 6 bytes MAC address for 802.11b/g */
4043 -#define SSB_SPROM1_ET0MAC 0x104E /* 6 bytes MAC address for Ethernet */
4044 -#define SSB_SPROM1_ET1MAC 0x1054 /* 6 bytes MAC address for 802.11a */
4045 -#define SSB_SPROM1_ETHPHY 0x105A /* Ethernet PHY settings */
4046 +#define SSB_SPROM1_SPID 0x0004 /* Subsystem Product ID for PCI */
4047 +#define SSB_SPROM1_SVID 0x0006 /* Subsystem Vendor ID for PCI */
4048 +#define SSB_SPROM1_PID 0x0008 /* Product ID for PCI */
4049 +#define SSB_SPROM1_IL0MAC 0x0048 /* 6 bytes MAC address for 802.11b/g */
4050 +#define SSB_SPROM1_ET0MAC 0x004E /* 6 bytes MAC address for Ethernet */
4051 +#define SSB_SPROM1_ET1MAC 0x0054 /* 6 bytes MAC address for 802.11a */
4052 +#define SSB_SPROM1_ETHPHY 0x005A /* Ethernet PHY settings */
4053 #define SSB_SPROM1_ETHPHY_ET0A 0x001F /* MII Address for enet0 */
4054 #define SSB_SPROM1_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */
4055 #define SSB_SPROM1_ETHPHY_ET1A_SHIFT 5
4056 #define SSB_SPROM1_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */
4057 #define SSB_SPROM1_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */
4058 -#define SSB_SPROM1_BINF 0x105C /* Board info */
4059 +#define SSB_SPROM1_BINF 0x005C /* Board info */
4060 #define SSB_SPROM1_BINF_BREV 0x00FF /* Board Revision */
4061 #define SSB_SPROM1_BINF_CCODE 0x0F00 /* Country Code */
4062 #define SSB_SPROM1_BINF_CCODE_SHIFT 8
4063 @@ -197,63 +200,63 @@
4064 #define SSB_SPROM1_BINF_ANTBG_SHIFT 12
4065 #define SSB_SPROM1_BINF_ANTA 0xC000 /* Available A-PHY antennas */
4066 #define SSB_SPROM1_BINF_ANTA_SHIFT 14
4067 -#define SSB_SPROM1_PA0B0 0x105E
4068 -#define SSB_SPROM1_PA0B1 0x1060
4069 -#define SSB_SPROM1_PA0B2 0x1062
4070 -#define SSB_SPROM1_GPIOA 0x1064 /* General Purpose IO pins 0 and 1 */
4071 +#define SSB_SPROM1_PA0B0 0x005E
4072 +#define SSB_SPROM1_PA0B1 0x0060
4073 +#define SSB_SPROM1_PA0B2 0x0062
4074 +#define SSB_SPROM1_GPIOA 0x0064 /* General Purpose IO pins 0 and 1 */
4075 #define SSB_SPROM1_GPIOA_P0 0x00FF /* Pin 0 */
4076 #define SSB_SPROM1_GPIOA_P1 0xFF00 /* Pin 1 */
4077 #define SSB_SPROM1_GPIOA_P1_SHIFT 8
4078 -#define SSB_SPROM1_GPIOB 0x1066 /* General Purpuse IO pins 2 and 3 */
4079 +#define SSB_SPROM1_GPIOB 0x0066 /* General Purpuse IO pins 2 and 3 */
4080 #define SSB_SPROM1_GPIOB_P2 0x00FF /* Pin 2 */
4081 #define SSB_SPROM1_GPIOB_P3 0xFF00 /* Pin 3 */
4082 #define SSB_SPROM1_GPIOB_P3_SHIFT 8
4083 -#define SSB_SPROM1_MAXPWR 0x1068 /* Power Amplifier Max Power */
4084 +#define SSB_SPROM1_MAXPWR 0x0068 /* Power Amplifier Max Power */
4085 #define SSB_SPROM1_MAXPWR_BG 0x00FF /* B-PHY and G-PHY (in dBm Q5.2) */
4086 #define SSB_SPROM1_MAXPWR_A 0xFF00 /* A-PHY (in dBm Q5.2) */
4087 #define SSB_SPROM1_MAXPWR_A_SHIFT 8
4088 -#define SSB_SPROM1_PA1B0 0x106A
4089 -#define SSB_SPROM1_PA1B1 0x106C
4090 -#define SSB_SPROM1_PA1B2 0x106E
4091 -#define SSB_SPROM1_ITSSI 0x1070 /* Idle TSSI Target */
4092 +#define SSB_SPROM1_PA1B0 0x006A
4093 +#define SSB_SPROM1_PA1B1 0x006C
4094 +#define SSB_SPROM1_PA1B2 0x006E
4095 +#define SSB_SPROM1_ITSSI 0x0070 /* Idle TSSI Target */
4096 #define SSB_SPROM1_ITSSI_BG 0x00FF /* B-PHY and G-PHY*/
4097 #define SSB_SPROM1_ITSSI_A 0xFF00 /* A-PHY */
4098 #define SSB_SPROM1_ITSSI_A_SHIFT 8
4099 -#define SSB_SPROM1_BFLLO 0x1072 /* Boardflags (low 16 bits) */
4100 -#define SSB_SPROM1_AGAIN 0x1074 /* Antenna Gain (in dBm Q5.2) */
4101 +#define SSB_SPROM1_BFLLO 0x0072 /* Boardflags (low 16 bits) */
4102 +#define SSB_SPROM1_AGAIN 0x0074 /* Antenna Gain (in dBm Q5.2) */
4103 #define SSB_SPROM1_AGAIN_BG 0x00FF /* B-PHY and G-PHY */
4104 #define SSB_SPROM1_AGAIN_BG_SHIFT 0
4105 #define SSB_SPROM1_AGAIN_A 0xFF00 /* A-PHY */
4106 #define SSB_SPROM1_AGAIN_A_SHIFT 8
4107
4108 /* SPROM Revision 2 (inherits from rev 1) */
4109 -#define SSB_SPROM2_BFLHI 0x1038 /* Boardflags (high 16 bits) */
4110 -#define SSB_SPROM2_MAXP_A 0x103A /* A-PHY Max Power */
4111 +#define SSB_SPROM2_BFLHI 0x0038 /* Boardflags (high 16 bits) */
4112 +#define SSB_SPROM2_MAXP_A 0x003A /* A-PHY Max Power */
4113 #define SSB_SPROM2_MAXP_A_HI 0x00FF /* Max Power High */
4114 #define SSB_SPROM2_MAXP_A_LO 0xFF00 /* Max Power Low */
4115 #define SSB_SPROM2_MAXP_A_LO_SHIFT 8
4116 -#define SSB_SPROM2_PA1LOB0 0x103C /* A-PHY PowerAmplifier Low Settings */
4117 -#define SSB_SPROM2_PA1LOB1 0x103E /* A-PHY PowerAmplifier Low Settings */
4118 -#define SSB_SPROM2_PA1LOB2 0x1040 /* A-PHY PowerAmplifier Low Settings */
4119 -#define SSB_SPROM2_PA1HIB0 0x1042 /* A-PHY PowerAmplifier High Settings */
4120 -#define SSB_SPROM2_PA1HIB1 0x1044 /* A-PHY PowerAmplifier High Settings */
4121 -#define SSB_SPROM2_PA1HIB2 0x1046 /* A-PHY PowerAmplifier High Settings */
4122 -#define SSB_SPROM2_OPO 0x1078 /* OFDM Power Offset from CCK Level */
4123 +#define SSB_SPROM2_PA1LOB0 0x003C /* A-PHY PowerAmplifier Low Settings */
4124 +#define SSB_SPROM2_PA1LOB1 0x003E /* A-PHY PowerAmplifier Low Settings */
4125 +#define SSB_SPROM2_PA1LOB2 0x0040 /* A-PHY PowerAmplifier Low Settings */
4126 +#define SSB_SPROM2_PA1HIB0 0x0042 /* A-PHY PowerAmplifier High Settings */
4127 +#define SSB_SPROM2_PA1HIB1 0x0044 /* A-PHY PowerAmplifier High Settings */
4128 +#define SSB_SPROM2_PA1HIB2 0x0046 /* A-PHY PowerAmplifier High Settings */
4129 +#define SSB_SPROM2_OPO 0x0078 /* OFDM Power Offset from CCK Level */
4130 #define SSB_SPROM2_OPO_VALUE 0x00FF
4131 #define SSB_SPROM2_OPO_UNUSED 0xFF00
4132 -#define SSB_SPROM2_CCODE 0x107C /* Two char Country Code */
4133 +#define SSB_SPROM2_CCODE 0x007C /* Two char Country Code */
4134
4135 /* SPROM Revision 3 (inherits most data from rev 2) */
4136 -#define SSB_SPROM3_IL0MAC 0x104A /* 6 bytes MAC address for 802.11b/g */
4137 -#define SSB_SPROM3_OFDMAPO 0x102C /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
4138 -#define SSB_SPROM3_OFDMALPO 0x1030 /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
4139 -#define SSB_SPROM3_OFDMAHPO 0x1034 /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
4140 -#define SSB_SPROM3_GPIOLDC 0x1042 /* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */
4141 +#define SSB_SPROM3_OFDMAPO 0x002C /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
4142 +#define SSB_SPROM3_OFDMALPO 0x0030 /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
4143 +#define SSB_SPROM3_OFDMAHPO 0x0034 /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
4144 +#define SSB_SPROM3_GPIOLDC 0x0042 /* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */
4145 #define SSB_SPROM3_GPIOLDC_OFF 0x0000FF00 /* Off Count */
4146 #define SSB_SPROM3_GPIOLDC_OFF_SHIFT 8
4147 #define SSB_SPROM3_GPIOLDC_ON 0x00FF0000 /* On Count */
4148 #define SSB_SPROM3_GPIOLDC_ON_SHIFT 16
4149 -#define SSB_SPROM3_CCKPO 0x1078 /* CCK Power Offset */
4150 +#define SSB_SPROM3_IL0MAC 0x004A /* 6 bytes MAC address for 802.11b/g */
4151 +#define SSB_SPROM3_CCKPO 0x0078 /* CCK Power Offset */
4152 #define SSB_SPROM3_CCKPO_1M 0x000F /* 1M Rate PO */
4153 #define SSB_SPROM3_CCKPO_2M 0x00F0 /* 2M Rate PO */
4154 #define SSB_SPROM3_CCKPO_2M_SHIFT 4
4155 @@ -264,104 +267,291 @@
4156 #define SSB_SPROM3_OFDMGPO 0x107A /* G-PHY OFDM Power Offset (4 bytes, BigEndian) */
4157
4158 /* SPROM Revision 4 */
4159 -#define SSB_SPROM4_IL0MAC 0x104C /* 6 byte MAC address for a/b/g/n */
4160 -#define SSB_SPROM4_ETHPHY 0x105A /* Ethernet PHY settings ?? */
4161 +#define SSB_SPROM4_BFLLO 0x0044 /* Boardflags (low 16 bits) */
4162 +#define SSB_SPROM4_BFLHI 0x0046 /* Board Flags Hi */
4163 +#define SSB_SPROM4_BFL2LO 0x0048 /* Board flags 2 (low 16 bits) */
4164 +#define SSB_SPROM4_BFL2HI 0x004A /* Board flags 2 Hi */
4165 +#define SSB_SPROM4_IL0MAC 0x004C /* 6 byte MAC address for a/b/g/n */
4166 +#define SSB_SPROM4_CCODE 0x0052 /* Country Code (2 bytes) */
4167 +#define SSB_SPROM4_GPIOA 0x0056 /* Gen. Purpose IO # 0 and 1 */
4168 +#define SSB_SPROM4_GPIOA_P0 0x00FF /* Pin 0 */
4169 +#define SSB_SPROM4_GPIOA_P1 0xFF00 /* Pin 1 */
4170 +#define SSB_SPROM4_GPIOA_P1_SHIFT 8
4171 +#define SSB_SPROM4_GPIOB 0x0058 /* Gen. Purpose IO # 2 and 3 */
4172 +#define SSB_SPROM4_GPIOB_P2 0x00FF /* Pin 2 */
4173 +#define SSB_SPROM4_GPIOB_P3 0xFF00 /* Pin 3 */
4174 +#define SSB_SPROM4_GPIOB_P3_SHIFT 8
4175 +#define SSB_SPROM4_ETHPHY 0x005A /* Ethernet PHY settings ?? */
4176 #define SSB_SPROM4_ETHPHY_ET0A 0x001F /* MII Address for enet0 */
4177 #define SSB_SPROM4_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */
4178 #define SSB_SPROM4_ETHPHY_ET1A_SHIFT 5
4179 #define SSB_SPROM4_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */
4180 #define SSB_SPROM4_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */
4181 -#define SSB_SPROM4_CCODE 0x1052 /* Country Code (2 bytes) */
4182 -#define SSB_SPROM4_ANTAVAIL 0x105D /* Antenna available bitfields */
4183 -#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */
4184 -#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0
4185 -#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */
4186 -#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8
4187 -#define SSB_SPROM4_BFLLO 0x1044 /* Boardflags (low 16 bits) */
4188 -#define SSB_SPROM4_AGAIN01 0x105E /* Antenna Gain (in dBm Q5.2) */
4189 +#define SSB_SPROM4_ANTAVAIL 0x005D /* Antenna available bitfields */
4190 +#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */
4191 +#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0
4192 +#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */
4193 +#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8
4194 +#define SSB_SPROM4_AGAIN01 0x005E /* Antenna Gain (in dBm Q5.2) */
4195 #define SSB_SPROM4_AGAIN0 0x00FF /* Antenna 0 */
4196 #define SSB_SPROM4_AGAIN0_SHIFT 0
4197 #define SSB_SPROM4_AGAIN1 0xFF00 /* Antenna 1 */
4198 #define SSB_SPROM4_AGAIN1_SHIFT 8
4199 -#define SSB_SPROM4_AGAIN23 0x1060
4200 +#define SSB_SPROM4_AGAIN23 0x0060
4201 #define SSB_SPROM4_AGAIN2 0x00FF /* Antenna 2 */
4202 #define SSB_SPROM4_AGAIN2_SHIFT 0
4203 #define SSB_SPROM4_AGAIN3 0xFF00 /* Antenna 3 */
4204 #define SSB_SPROM4_AGAIN3_SHIFT 8
4205 -#define SSB_SPROM4_BFLHI 0x1046 /* Board Flags Hi */
4206 -#define SSB_SPROM4_MAXP_BG 0x1080 /* Max Power BG in path 1 */
4207 +#define SSB_SPROM4_TXPID2G01 0x0062 /* TX Power Index 2GHz */
4208 +#define SSB_SPROM4_TXPID2G0 0x00FF
4209 +#define SSB_SPROM4_TXPID2G0_SHIFT 0
4210 +#define SSB_SPROM4_TXPID2G1 0xFF00
4211 +#define SSB_SPROM4_TXPID2G1_SHIFT 8
4212 +#define SSB_SPROM4_TXPID2G23 0x0064 /* TX Power Index 2GHz */
4213 +#define SSB_SPROM4_TXPID2G2 0x00FF
4214 +#define SSB_SPROM4_TXPID2G2_SHIFT 0
4215 +#define SSB_SPROM4_TXPID2G3 0xFF00
4216 +#define SSB_SPROM4_TXPID2G3_SHIFT 8
4217 +#define SSB_SPROM4_TXPID5G01 0x0066 /* TX Power Index 5GHz middle subband */
4218 +#define SSB_SPROM4_TXPID5G0 0x00FF
4219 +#define SSB_SPROM4_TXPID5G0_SHIFT 0
4220 +#define SSB_SPROM4_TXPID5G1 0xFF00
4221 +#define SSB_SPROM4_TXPID5G1_SHIFT 8
4222 +#define SSB_SPROM4_TXPID5G23 0x0068 /* TX Power Index 5GHz middle subband */
4223 +#define SSB_SPROM4_TXPID5G2 0x00FF
4224 +#define SSB_SPROM4_TXPID5G2_SHIFT 0
4225 +#define SSB_SPROM4_TXPID5G3 0xFF00
4226 +#define SSB_SPROM4_TXPID5G3_SHIFT 8
4227 +#define SSB_SPROM4_TXPID5GL01 0x006A /* TX Power Index 5GHz low subband */
4228 +#define SSB_SPROM4_TXPID5GL0 0x00FF
4229 +#define SSB_SPROM4_TXPID5GL0_SHIFT 0
4230 +#define SSB_SPROM4_TXPID5GL1 0xFF00
4231 +#define SSB_SPROM4_TXPID5GL1_SHIFT 8
4232 +#define SSB_SPROM4_TXPID5GL23 0x006C /* TX Power Index 5GHz low subband */
4233 +#define SSB_SPROM4_TXPID5GL2 0x00FF
4234 +#define SSB_SPROM4_TXPID5GL2_SHIFT 0
4235 +#define SSB_SPROM4_TXPID5GL3 0xFF00
4236 +#define SSB_SPROM4_TXPID5GL3_SHIFT 8
4237 +#define SSB_SPROM4_TXPID5GH01 0x006E /* TX Power Index 5GHz high subband */
4238 +#define SSB_SPROM4_TXPID5GH0 0x00FF
4239 +#define SSB_SPROM4_TXPID5GH0_SHIFT 0
4240 +#define SSB_SPROM4_TXPID5GH1 0xFF00
4241 +#define SSB_SPROM4_TXPID5GH1_SHIFT 8
4242 +#define SSB_SPROM4_TXPID5GH23 0x0070 /* TX Power Index 5GHz high subband */
4243 +#define SSB_SPROM4_TXPID5GH2 0x00FF
4244 +#define SSB_SPROM4_TXPID5GH2_SHIFT 0
4245 +#define SSB_SPROM4_TXPID5GH3 0xFF00
4246 +#define SSB_SPROM4_TXPID5GH3_SHIFT 8
4247 +#define SSB_SPROM4_MAXP_BG 0x0080 /* Max Power BG in path 1 */
4248 #define SSB_SPROM4_MAXP_BG_MASK 0x00FF /* Mask for Max Power BG */
4249 #define SSB_SPROM4_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
4250 #define SSB_SPROM4_ITSSI_BG_SHIFT 8
4251 -#define SSB_SPROM4_MAXP_A 0x108A /* Max Power A in path 1 */
4252 +#define SSB_SPROM4_MAXP_A 0x008A /* Max Power A in path 1 */
4253 #define SSB_SPROM4_MAXP_A_MASK 0x00FF /* Mask for Max Power A */
4254 #define SSB_SPROM4_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */
4255 #define SSB_SPROM4_ITSSI_A_SHIFT 8
4256 -#define SSB_SPROM4_GPIOA 0x1056 /* Gen. Purpose IO # 0 and 1 */
4257 -#define SSB_SPROM4_GPIOA_P0 0x00FF /* Pin 0 */
4258 -#define SSB_SPROM4_GPIOA_P1 0xFF00 /* Pin 1 */
4259 -#define SSB_SPROM4_GPIOA_P1_SHIFT 8
4260 -#define SSB_SPROM4_GPIOB 0x1058 /* Gen. Purpose IO # 2 and 3 */
4261 -#define SSB_SPROM4_GPIOB_P2 0x00FF /* Pin 2 */
4262 -#define SSB_SPROM4_GPIOB_P3 0xFF00 /* Pin 3 */
4263 -#define SSB_SPROM4_GPIOB_P3_SHIFT 8
4264 -#define SSB_SPROM4_PA0B0 0x1082 /* The paXbY locations are */
4265 -#define SSB_SPROM4_PA0B1 0x1084 /* only guesses */
4266 -#define SSB_SPROM4_PA0B2 0x1086
4267 -#define SSB_SPROM4_PA1B0 0x108E
4268 -#define SSB_SPROM4_PA1B1 0x1090
4269 -#define SSB_SPROM4_PA1B2 0x1092
4270 +#define SSB_SPROM4_PA0B0 0x0082 /* The paXbY locations are */
4271 +#define SSB_SPROM4_PA0B1 0x0084 /* only guesses */
4272 +#define SSB_SPROM4_PA0B2 0x0086
4273 +#define SSB_SPROM4_PA1B0 0x008E
4274 +#define SSB_SPROM4_PA1B1 0x0090
4275 +#define SSB_SPROM4_PA1B2 0x0092
4276
4277 /* SPROM Revision 5 (inherits most data from rev 4) */
4278 -#define SSB_SPROM5_BFLLO 0x104A /* Boardflags (low 16 bits) */
4279 -#define SSB_SPROM5_BFLHI 0x104C /* Board Flags Hi */
4280 -#define SSB_SPROM5_IL0MAC 0x1052 /* 6 byte MAC address for a/b/g/n */
4281 -#define SSB_SPROM5_CCODE 0x1044 /* Country Code (2 bytes) */
4282 -#define SSB_SPROM5_GPIOA 0x1076 /* Gen. Purpose IO # 0 and 1 */
4283 +#define SSB_SPROM5_CCODE 0x0044 /* Country Code (2 bytes) */
4284 +#define SSB_SPROM5_BFLLO 0x004A /* Boardflags (low 16 bits) */
4285 +#define SSB_SPROM5_BFLHI 0x004C /* Board Flags Hi */
4286 +#define SSB_SPROM5_BFL2LO 0x004E /* Board flags 2 (low 16 bits) */
4287 +#define SSB_SPROM5_BFL2HI 0x0050 /* Board flags 2 Hi */
4288 +#define SSB_SPROM5_IL0MAC 0x0052 /* 6 byte MAC address for a/b/g/n */
4289 +#define SSB_SPROM5_GPIOA 0x0076 /* Gen. Purpose IO # 0 and 1 */
4290 #define SSB_SPROM5_GPIOA_P0 0x00FF /* Pin 0 */
4291 #define SSB_SPROM5_GPIOA_P1 0xFF00 /* Pin 1 */
4292 #define SSB_SPROM5_GPIOA_P1_SHIFT 8
4293 -#define SSB_SPROM5_GPIOB 0x1078 /* Gen. Purpose IO # 2 and 3 */
4294 +#define SSB_SPROM5_GPIOB 0x0078 /* Gen. Purpose IO # 2 and 3 */
4295 #define SSB_SPROM5_GPIOB_P2 0x00FF /* Pin 2 */
4296 #define SSB_SPROM5_GPIOB_P3 0xFF00 /* Pin 3 */
4297 #define SSB_SPROM5_GPIOB_P3_SHIFT 8
4298
4299 /* SPROM Revision 8 */
4300 -#define SSB_SPROM8_BFLLO 0x1084 /* Boardflags (low 16 bits) */
4301 -#define SSB_SPROM8_BFLHI 0x1086 /* Boardflags Hi */
4302 -#define SSB_SPROM8_IL0MAC 0x108C /* 6 byte MAC address */
4303 -#define SSB_SPROM8_CCODE 0x1092 /* 2 byte country code */
4304 -#define SSB_SPROM8_ANTAVAIL 0x109C /* Antenna available bitfields*/
4305 -#define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
4306 -#define SSB_SPROM8_ANTAVAIL_A_SHIFT 8
4307 -#define SSB_SPROM8_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */
4308 -#define SSB_SPROM8_ANTAVAIL_BG_SHIFT 0
4309 -#define SSB_SPROM8_AGAIN01 0x109E /* Antenna Gain (in dBm Q5.2) */
4310 +#define SSB_SPROM8_BOARDREV 0x0082 /* Board revision */
4311 +#define SSB_SPROM8_BFLLO 0x0084 /* Board flags (bits 0-15) */
4312 +#define SSB_SPROM8_BFLHI 0x0086 /* Board flags (bits 16-31) */
4313 +#define SSB_SPROM8_BFL2LO 0x0088 /* Board flags (bits 32-47) */
4314 +#define SSB_SPROM8_BFL2HI 0x008A /* Board flags (bits 48-63) */
4315 +#define SSB_SPROM8_IL0MAC 0x008C /* 6 byte MAC address */
4316 +#define SSB_SPROM8_CCODE 0x0092 /* 2 byte country code */
4317 +#define SSB_SPROM8_GPIOA 0x0096 /*Gen. Purpose IO # 0 and 1 */
4318 +#define SSB_SPROM8_GPIOA_P0 0x00FF /* Pin 0 */
4319 +#define SSB_SPROM8_GPIOA_P1 0xFF00 /* Pin 1 */
4320 +#define SSB_SPROM8_GPIOA_P1_SHIFT 8
4321 +#define SSB_SPROM8_GPIOB 0x0098 /* Gen. Purpose IO # 2 and 3 */
4322 +#define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */
4323 +#define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */
4324 +#define SSB_SPROM8_GPIOB_P3_SHIFT 8
4325 +#define SSB_SPROM8_ANTAVAIL 0x009C /* Antenna available bitfields*/
4326 +#define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
4327 +#define SSB_SPROM8_ANTAVAIL_A_SHIFT 8
4328 +#define SSB_SPROM8_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */
4329 +#define SSB_SPROM8_ANTAVAIL_BG_SHIFT 0
4330 +#define SSB_SPROM8_AGAIN01 0x009E /* Antenna Gain (in dBm Q5.2) */
4331 #define SSB_SPROM8_AGAIN0 0x00FF /* Antenna 0 */
4332 #define SSB_SPROM8_AGAIN0_SHIFT 0
4333 #define SSB_SPROM8_AGAIN1 0xFF00 /* Antenna 1 */
4334 #define SSB_SPROM8_AGAIN1_SHIFT 8
4335 -#define SSB_SPROM8_AGAIN23 0x10A0
4336 +#define SSB_SPROM8_AGAIN23 0x00A0
4337 #define SSB_SPROM8_AGAIN2 0x00FF /* Antenna 2 */
4338 #define SSB_SPROM8_AGAIN2_SHIFT 0
4339 #define SSB_SPROM8_AGAIN3 0xFF00 /* Antenna 3 */
4340 #define SSB_SPROM8_AGAIN3_SHIFT 8
4341 -#define SSB_SPROM8_GPIOA 0x1096 /*Gen. Purpose IO # 0 and 1 */
4342 -#define SSB_SPROM8_GPIOA_P0 0x00FF /* Pin 0 */
4343 -#define SSB_SPROM8_GPIOA_P1 0xFF00 /* Pin 1 */
4344 -#define SSB_SPROM8_GPIOA_P1_SHIFT 8
4345 -#define SSB_SPROM8_GPIOB 0x1098 /* Gen. Purpose IO # 2 and 3 */
4346 -#define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */
4347 -#define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */
4348 -#define SSB_SPROM8_GPIOB_P3_SHIFT 8
4349 -#define SSB_SPROM8_MAXP_BG 0x10C0 /* Max Power BG in path 1 */
4350 -#define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power BG */
4351 +#define SSB_SPROM8_RSSIPARM2G 0x00A4 /* RSSI params for 2GHz */
4352 +#define SSB_SPROM8_RSSISMF2G 0x000F
4353 +#define SSB_SPROM8_RSSISMC2G 0x00F0
4354 +#define SSB_SPROM8_RSSISMC2G_SHIFT 4
4355 +#define SSB_SPROM8_RSSISAV2G 0x0700
4356 +#define SSB_SPROM8_RSSISAV2G_SHIFT 8
4357 +#define SSB_SPROM8_BXA2G 0x1800
4358 +#define SSB_SPROM8_BXA2G_SHIFT 11
4359 +#define SSB_SPROM8_RSSIPARM5G 0x00A6 /* RSSI params for 5GHz */
4360 +#define SSB_SPROM8_RSSISMF5G 0x000F
4361 +#define SSB_SPROM8_RSSISMC5G 0x00F0
4362 +#define SSB_SPROM8_RSSISMC5G_SHIFT 4
4363 +#define SSB_SPROM8_RSSISAV5G 0x0700
4364 +#define SSB_SPROM8_RSSISAV5G_SHIFT 8
4365 +#define SSB_SPROM8_BXA5G 0x1800
4366 +#define SSB_SPROM8_BXA5G_SHIFT 11
4367 +#define SSB_SPROM8_TRI25G 0x00A8 /* TX isolation 2.4&5.3GHz */
4368 +#define SSB_SPROM8_TRI2G 0x00FF /* TX isolation 2.4GHz */
4369 +#define SSB_SPROM8_TRI5G 0xFF00 /* TX isolation 5.3GHz */
4370 +#define SSB_SPROM8_TRI5G_SHIFT 8
4371 +#define SSB_SPROM8_TRI5GHL 0x00AA /* TX isolation 5.2/5.8GHz */
4372 +#define SSB_SPROM8_TRI5GL 0x00FF /* TX isolation 5.2GHz */
4373 +#define SSB_SPROM8_TRI5GH 0xFF00 /* TX isolation 5.8GHz */
4374 +#define SSB_SPROM8_TRI5GH_SHIFT 8
4375 +#define SSB_SPROM8_RXPO 0x00AC /* RX power offsets */
4376 +#define SSB_SPROM8_RXPO2G 0x00FF /* 2GHz RX power offset */
4377 +#define SSB_SPROM8_RXPO5G 0xFF00 /* 5GHz RX power offset */
4378 +#define SSB_SPROM8_RXPO5G_SHIFT 8
4379 +#define SSB_SPROM8_FEM2G 0x00AE
4380 +#define SSB_SPROM8_FEM5G 0x00B0
4381 +#define SSB_SROM8_FEM_TSSIPOS 0x0001
4382 +#define SSB_SROM8_FEM_TSSIPOS_SHIFT 0
4383 +#define SSB_SROM8_FEM_EXTPA_GAIN 0x0006
4384 +#define SSB_SROM8_FEM_EXTPA_GAIN_SHIFT 1
4385 +#define SSB_SROM8_FEM_PDET_RANGE 0x00F8
4386 +#define SSB_SROM8_FEM_PDET_RANGE_SHIFT 3
4387 +#define SSB_SROM8_FEM_TR_ISO 0x0700
4388 +#define SSB_SROM8_FEM_TR_ISO_SHIFT 8
4389 +#define SSB_SROM8_FEM_ANTSWLUT 0xF800
4390 +#define SSB_SROM8_FEM_ANTSWLUT_SHIFT 11
4391 +#define SSB_SPROM8_THERMAL 0x00B2
4392 +#define SSB_SPROM8_MPWR_RAWTS 0x00B4
4393 +#define SSB_SPROM8_TS_SLP_OPT_CORRX 0x00B6
4394 +#define SSB_SPROM8_FOC_HWIQ_IQSWP 0x00B8
4395 +#define SSB_SPROM8_PHYCAL_TEMPDELTA 0x00BA
4396 +
4397 +/* There are 4 blocks with power info sharing the same layout */
4398 +#define SSB_SROM8_PWR_INFO_CORE0 0x00C0
4399 +#define SSB_SROM8_PWR_INFO_CORE1 0x00E0
4400 +#define SSB_SROM8_PWR_INFO_CORE2 0x0100
4401 +#define SSB_SROM8_PWR_INFO_CORE3 0x0120
4402 +
4403 +#define SSB_SROM8_2G_MAXP_ITSSI 0x00
4404 +#define SSB_SPROM8_2G_MAXP 0x00FF
4405 +#define SSB_SPROM8_2G_ITSSI 0xFF00
4406 +#define SSB_SPROM8_2G_ITSSI_SHIFT 8
4407 +#define SSB_SROM8_2G_PA_0 0x02 /* 2GHz power amp settings */
4408 +#define SSB_SROM8_2G_PA_1 0x04
4409 +#define SSB_SROM8_2G_PA_2 0x06
4410 +#define SSB_SROM8_5G_MAXP_ITSSI 0x08 /* 5GHz ITSSI and 5.3GHz Max Power */
4411 +#define SSB_SPROM8_5G_MAXP 0x00FF
4412 +#define SSB_SPROM8_5G_ITSSI 0xFF00
4413 +#define SSB_SPROM8_5G_ITSSI_SHIFT 8
4414 +#define SSB_SPROM8_5GHL_MAXP 0x0A /* 5.2GHz and 5.8GHz Max Power */
4415 +#define SSB_SPROM8_5GH_MAXP 0x00FF
4416 +#define SSB_SPROM8_5GL_MAXP 0xFF00
4417 +#define SSB_SPROM8_5GL_MAXP_SHIFT 8
4418 +#define SSB_SROM8_5G_PA_0 0x0C /* 5.3GHz power amp settings */
4419 +#define SSB_SROM8_5G_PA_1 0x0E
4420 +#define SSB_SROM8_5G_PA_2 0x10
4421 +#define SSB_SROM8_5GL_PA_0 0x12 /* 5.2GHz power amp settings */
4422 +#define SSB_SROM8_5GL_PA_1 0x14
4423 +#define SSB_SROM8_5GL_PA_2 0x16
4424 +#define SSB_SROM8_5GH_PA_0 0x18 /* 5.8GHz power amp settings */
4425 +#define SSB_SROM8_5GH_PA_1 0x1A
4426 +#define SSB_SROM8_5GH_PA_2 0x1C
4427 +
4428 +/* TODO: Make it deprecated */
4429 +#define SSB_SPROM8_MAXP_BG 0x00C0 /* Max Power 2GHz in path 1 */
4430 +#define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */
4431 #define SSB_SPROM8_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
4432 #define SSB_SPROM8_ITSSI_BG_SHIFT 8
4433 -#define SSB_SPROM8_MAXP_A 0x10C8 /* Max Power A in path 1 */
4434 -#define SSB_SPROM8_MAXP_A_MASK 0x00FF /* Mask for Max Power A */
4435 +#define SSB_SPROM8_PA0B0 0x00C2 /* 2GHz power amp settings */
4436 +#define SSB_SPROM8_PA0B1 0x00C4
4437 +#define SSB_SPROM8_PA0B2 0x00C6
4438 +#define SSB_SPROM8_MAXP_A 0x00C8 /* Max Power 5.3GHz */
4439 +#define SSB_SPROM8_MAXP_A_MASK 0x00FF /* Mask for Max Power 5.3GHz */
4440 #define SSB_SPROM8_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */
4441 #define SSB_SPROM8_ITSSI_A_SHIFT 8
4442 +#define SSB_SPROM8_MAXP_AHL 0x00CA /* Max Power 5.2/5.8GHz */
4443 +#define SSB_SPROM8_MAXP_AH_MASK 0x00FF /* Mask for Max Power 5.8GHz */
4444 +#define SSB_SPROM8_MAXP_AL_MASK 0xFF00 /* Mask for Max Power 5.2GHz */
4445 +#define SSB_SPROM8_MAXP_AL_SHIFT 8
4446 +#define SSB_SPROM8_PA1B0 0x00CC /* 5.3GHz power amp settings */
4447 +#define SSB_SPROM8_PA1B1 0x00CE
4448 +#define SSB_SPROM8_PA1B2 0x00D0
4449 +#define SSB_SPROM8_PA1LOB0 0x00D2 /* 5.2GHz power amp settings */
4450 +#define SSB_SPROM8_PA1LOB1 0x00D4
4451 +#define SSB_SPROM8_PA1LOB2 0x00D6
4452 +#define SSB_SPROM8_PA1HIB0 0x00D8 /* 5.8GHz power amp settings */
4453 +#define SSB_SPROM8_PA1HIB1 0x00DA
4454 +#define SSB_SPROM8_PA1HIB2 0x00DC
4455 +
4456 +#define SSB_SPROM8_CCK2GPO 0x0140 /* CCK power offset */
4457 +#define SSB_SPROM8_OFDM2GPO 0x0142 /* 2.4GHz OFDM power offset */
4458 +#define SSB_SPROM8_OFDM5GPO 0x0146 /* 5.3GHz OFDM power offset */
4459 +#define SSB_SPROM8_OFDM5GLPO 0x014A /* 5.2GHz OFDM power offset */
4460 +#define SSB_SPROM8_OFDM5GHPO 0x014E /* 5.8GHz OFDM power offset */
4461 +
4462 +/* Values for boardflags_lo read from SPROM */
4463 +#define SSB_BFL_BTCOEXIST 0x0001 /* implements Bluetooth coexistance */
4464 +#define SSB_BFL_PACTRL 0x0002 /* GPIO 9 controlling the PA */
4465 +#define SSB_BFL_AIRLINEMODE 0x0004 /* implements GPIO 13 radio disable indication */
4466 +#define SSB_BFL_RSSI 0x0008 /* software calculates nrssi slope. */
4467 +#define SSB_BFL_ENETSPI 0x0010 /* has ephy roboswitch spi */
4468 +#define SSB_BFL_XTAL_NOSLOW 0x0020 /* no slow clock available */
4469 +#define SSB_BFL_CCKHIPWR 0x0040 /* can do high power CCK transmission */
4470 +#define SSB_BFL_ENETADM 0x0080 /* has ADMtek switch */
4471 +#define SSB_BFL_ENETVLAN 0x0100 /* can do vlan */
4472 +#define SSB_BFL_AFTERBURNER 0x0200 /* supports Afterburner mode */
4473 +#define SSB_BFL_NOPCI 0x0400 /* board leaves PCI floating */
4474 +#define SSB_BFL_FEM 0x0800 /* supports the Front End Module */
4475 +#define SSB_BFL_EXTLNA 0x1000 /* has an external LNA */
4476 +#define SSB_BFL_HGPA 0x2000 /* had high gain PA */
4477 +#define SSB_BFL_BTCMOD 0x4000 /* BFL_BTCOEXIST is given in alternate GPIOs */
4478 +#define SSB_BFL_ALTIQ 0x8000 /* alternate I/Q settings */
4479 +
4480 +/* Values for boardflags_hi read from SPROM */
4481 +#define SSB_BFH_NOPA 0x0001 /* has no PA */
4482 +#define SSB_BFH_RSSIINV 0x0002 /* RSSI uses positive slope (not TSSI) */
4483 +#define SSB_BFH_PAREF 0x0004 /* uses the PARef LDO */
4484 +#define SSB_BFH_3TSWITCH 0x0008 /* uses a triple throw switch shared with bluetooth */
4485 +#define SSB_BFH_PHASESHIFT 0x0010 /* can support phase shifter */
4486 +#define SSB_BFH_BUCKBOOST 0x0020 /* has buck/booster */
4487 +#define SSB_BFH_FEM_BT 0x0040 /* has FEM and switch to share antenna with bluetooth */
4488 +
4489 +/* Values for boardflags2_lo read from SPROM */
4490 +#define SSB_BFL2_RXBB_INT_REG_DIS 0x0001 /* external RX BB regulator present */
4491 +#define SSB_BFL2_APLL_WAR 0x0002 /* alternative A-band PLL settings implemented */
4492 +#define SSB_BFL2_TXPWRCTRL_EN 0x0004 /* permits enabling TX Power Control */
4493 +#define SSB_BFL2_2X4_DIV 0x0008 /* 2x4 diversity switch */
4494 +#define SSB_BFL2_5G_PWRGAIN 0x0010 /* supports 5G band power gain */
4495 +#define SSB_BFL2_PCIEWAR_OVR 0x0020 /* overrides ASPM and Clkreq settings */
4496 +#define SSB_BFL2_CAESERS_BRD 0x0040 /* is Caesers board (unused) */
4497 +#define SSB_BFL2_BTC3WIRE 0x0080 /* used 3-wire bluetooth coexist */
4498 +#define SSB_BFL2_SKWRKFEM_BRD 0x0100 /* 4321mcm93 uses Skyworks FEM */
4499 +#define SSB_BFL2_SPUR_WAR 0x0200 /* has a workaround for clock-harmonic spurs */
4500 +#define SSB_BFL2_GPLL_WAR 0x0400 /* altenative G-band PLL settings implemented */
4501
4502 /* Values for SSB_SPROM1_BINF_CCODE */
4503 enum {
4504 --- a/drivers/ssb/driver_extif.c
4505 +++ b/drivers/ssb/driver_extif.c
4506 @@ -3,7 +3,7 @@
4507 * Broadcom EXTIF core driver
4508 *
4509 * Copyright 2005, Broadcom Corporation
4510 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
4511 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
4512 * Copyright 2006, 2007, Felix Fietkau <nbd@openwrt.org>
4513 * Copyright 2007, Aurelien Jarno <aurelien@aurel32.net>
4514 *
4515 --- a/drivers/ssb/embedded.c
4516 +++ b/drivers/ssb/embedded.c
4517 @@ -3,7 +3,7 @@
4518 * Embedded systems support code
4519 *
4520 * Copyright 2005-2008, Broadcom Corporation
4521 - * Copyright 2006-2008, Michael Buesch <mb@bu3sch.de>
4522 + * Copyright 2006-2008, Michael Buesch <m@bues.ch>
4523 *
4524 * Licensed under the GNU/GPL. See COPYING for details.
4525 */
4526 --- a/include/linux/ssb/ssb_driver_gige.h
4527 +++ b/include/linux/ssb/ssb_driver_gige.h
4528 @@ -2,6 +2,7 @@
4529 #define LINUX_SSB_DRIVER_GIGE_H_
4530
4531 #include <linux/ssb/ssb.h>
4532 +#include <linux/bug.h>
4533 #include <linux/pci.h>
4534 #include <linux/spinlock.h>
4535
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