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kernel: add a recent upstream commit (post-3.3) to the ssb update patch, required...
[openwrt/svn-archive/archive.git] / target / linux / generic / patches-2.6.30 / 941-ssb_update.patch
1 --- a/drivers/ssb/Kconfig
2 +++ b/drivers/ssb/Kconfig
3 @@ -66,6 +66,20 @@ config SSB_PCMCIAHOST
4
5 If unsure, say N
6
7 +config SSB_SDIOHOST_POSSIBLE
8 + bool
9 + depends on SSB && (MMC = y || MMC = SSB)
10 + default y
11 +
12 +config SSB_SDIOHOST
13 + bool "Support for SSB on SDIO-bus host"
14 + depends on SSB_SDIOHOST_POSSIBLE
15 + help
16 + Support for a Sonics Silicon Backplane on top
17 + of a SDIO device.
18 +
19 + If unsure, say N
20 +
21 config SSB_SILENT
22 bool "No SSB kernel messages"
23 depends on SSB && EMBEDDED
24 --- a/drivers/ssb/Makefile
25 +++ b/drivers/ssb/Makefile
26 @@ -6,6 +6,7 @@ ssb-$(CONFIG_SSB_SPROM) += sprom.o
27 # host support
28 ssb-$(CONFIG_SSB_PCIHOST) += pci.o pcihost_wrapper.o
29 ssb-$(CONFIG_SSB_PCMCIAHOST) += pcmcia.o
30 +ssb-$(CONFIG_SSB_SDIOHOST) += sdio.o
31
32 # built-in drivers
33 ssb-y += driver_chipcommon.o
34 --- a/drivers/ssb/b43_pci_bridge.c
35 +++ b/drivers/ssb/b43_pci_bridge.c
36 @@ -5,12 +5,13 @@
37 * because of its small size we include it in the SSB core
38 * instead of creating a standalone module.
39 *
40 - * Copyright 2007 Michael Buesch <mb@bu3sch.de>
41 + * Copyright 2007 Michael Buesch <m@bues.ch>
42 *
43 * Licensed under the GNU/GPL. See COPYING for details.
44 */
45
46 #include <linux/pci.h>
47 +#include <linux/module.h>
48 #include <linux/ssb/ssb.h>
49
50 #include "ssb_private.h"
51 @@ -24,6 +25,7 @@ static const struct pci_device_id b43_pc
52 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4312) },
53 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4315) },
54 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4318) },
55 + { PCI_DEVICE(PCI_VENDOR_ID_BCM_GVC, 0x4318) },
56 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4319) },
57 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4320) },
58 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4321) },
59 --- a/drivers/ssb/driver_chipcommon.c
60 +++ b/drivers/ssb/driver_chipcommon.c
61 @@ -3,7 +3,7 @@
62 * Broadcom ChipCommon core driver
63 *
64 * Copyright 2005, Broadcom Corporation
65 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
66 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
67 *
68 * Licensed under the GNU/GPL. See COPYING for details.
69 */
70 @@ -46,40 +46,66 @@ void ssb_chipco_set_clockmode(struct ssb
71 if (!ccdev)
72 return;
73 bus = ccdev->bus;
74 +
75 + /* We support SLOW only on 6..9 */
76 + if (ccdev->id.revision >= 10 && mode == SSB_CLKMODE_SLOW)
77 + mode = SSB_CLKMODE_DYNAMIC;
78 +
79 + if (cc->capabilities & SSB_CHIPCO_CAP_PMU)
80 + return; /* PMU controls clockmode, separated function needed */
81 + SSB_WARN_ON(ccdev->id.revision >= 20);
82 +
83 /* chipcommon cores prior to rev6 don't support dynamic clock control */
84 if (ccdev->id.revision < 6)
85 return;
86 - /* chipcommon cores rev10 are a whole new ball game */
87 +
88 + /* ChipCommon cores rev10+ need testing */
89 if (ccdev->id.revision >= 10)
90 return;
91 +
92 if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
93 return;
94
95 switch (mode) {
96 - case SSB_CLKMODE_SLOW:
97 + case SSB_CLKMODE_SLOW: /* For revs 6..9 only */
98 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
99 tmp |= SSB_CHIPCO_SLOWCLKCTL_FSLOW;
100 chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
101 break;
102 case SSB_CLKMODE_FAST:
103 - ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */
104 - tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
105 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
106 - tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL;
107 - chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
108 + if (ccdev->id.revision < 10) {
109 + ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */
110 + tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
111 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
112 + tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL;
113 + chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
114 + } else {
115 + chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
116 + (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) |
117 + SSB_CHIPCO_SYSCLKCTL_FORCEHT));
118 + /* udelay(150); TODO: not available in early init */
119 + }
120 break;
121 case SSB_CLKMODE_DYNAMIC:
122 - tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
123 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
124 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL;
125 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
126 - if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) != SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL)
127 - tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
128 - chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
129 -
130 - /* for dynamic control, we have to release our xtal_pu "force on" */
131 - if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL)
132 - ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0);
133 + if (ccdev->id.revision < 10) {
134 + tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
135 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
136 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL;
137 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
138 + if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) !=
139 + SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL)
140 + tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
141 + chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
142 +
143 + /* For dynamic control, we have to release our xtal_pu
144 + * "force on" */
145 + if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL)
146 + ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0);
147 + } else {
148 + chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
149 + (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) &
150 + ~SSB_CHIPCO_SYSCLKCTL_FORCEHT));
151 + }
152 break;
153 default:
154 SSB_WARN_ON(1);
155 @@ -209,6 +235,24 @@ static void chipco_powercontrol_init(str
156 }
157 }
158
159 +/* http://bcm-v4.sipsolutions.net/802.11/PmuFastPwrupDelay */
160 +static u16 pmu_fast_powerup_delay(struct ssb_chipcommon *cc)
161 +{
162 + struct ssb_bus *bus = cc->dev->bus;
163 +
164 + switch (bus->chip_id) {
165 + case 0x4312:
166 + case 0x4322:
167 + case 0x4328:
168 + return 7000;
169 + case 0x4325:
170 + /* TODO: */
171 + default:
172 + return 15000;
173 + }
174 +}
175 +
176 +/* http://bcm-v4.sipsolutions.net/802.11/ClkctlFastPwrupDelay */
177 static void calc_fast_powerup_delay(struct ssb_chipcommon *cc)
178 {
179 struct ssb_bus *bus = cc->dev->bus;
180 @@ -218,6 +262,12 @@ static void calc_fast_powerup_delay(stru
181
182 if (bus->bustype != SSB_BUSTYPE_PCI)
183 return;
184 +
185 + if (cc->capabilities & SSB_CHIPCO_CAP_PMU) {
186 + cc->fast_pwrup_delay = pmu_fast_powerup_delay(cc);
187 + return;
188 + }
189 +
190 if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
191 return;
192
193 @@ -233,6 +283,15 @@ void ssb_chipcommon_init(struct ssb_chip
194 {
195 if (!cc->dev)
196 return; /* We don't have a ChipCommon */
197 + if (cc->dev->id.revision >= 11)
198 + cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT);
199 + ssb_dprintk(KERN_INFO PFX "chipcommon status is 0x%x\n", cc->status);
200 +
201 + if (cc->dev->id.revision >= 20) {
202 + chipco_write32(cc, SSB_CHIPCO_GPIOPULLUP, 0);
203 + chipco_write32(cc, SSB_CHIPCO_GPIOPULLDOWN, 0);
204 + }
205 +
206 ssb_pmu_init(cc);
207 chipco_powercontrol_init(cc);
208 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
209 @@ -370,6 +429,7 @@ u32 ssb_chipco_gpio_control(struct ssb_c
210 {
211 return chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value);
212 }
213 +EXPORT_SYMBOL(ssb_chipco_gpio_control);
214
215 u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value)
216 {
217 --- a/drivers/ssb/driver_chipcommon_pmu.c
218 +++ b/drivers/ssb/driver_chipcommon_pmu.c
219 @@ -2,7 +2,7 @@
220 * Sonics Silicon Backplane
221 * Broadcom ChipCommon Power Management Unit driver
222 *
223 - * Copyright 2009, Michael Buesch <mb@bu3sch.de>
224 + * Copyright 2009, Michael Buesch <m@bues.ch>
225 * Copyright 2007, Broadcom Corporation
226 *
227 * Licensed under the GNU/GPL. See COPYING for details.
228 @@ -28,6 +28,21 @@ static void ssb_chipco_pll_write(struct
229 chipco_write32(cc, SSB_CHIPCO_PLLCTL_DATA, value);
230 }
231
232 +static void ssb_chipco_regctl_maskset(struct ssb_chipcommon *cc,
233 + u32 offset, u32 mask, u32 set)
234 +{
235 + u32 value;
236 +
237 + chipco_read32(cc, SSB_CHIPCO_REGCTL_ADDR);
238 + chipco_write32(cc, SSB_CHIPCO_REGCTL_ADDR, offset);
239 + chipco_read32(cc, SSB_CHIPCO_REGCTL_ADDR);
240 + value = chipco_read32(cc, SSB_CHIPCO_REGCTL_DATA);
241 + value &= mask;
242 + value |= set;
243 + chipco_write32(cc, SSB_CHIPCO_REGCTL_DATA, value);
244 + chipco_read32(cc, SSB_CHIPCO_REGCTL_DATA);
245 +}
246 +
247 struct pmu0_plltab_entry {
248 u16 freq; /* Crystal frequency in kHz.*/
249 u8 xf; /* Crystal frequency value for PMU control */
250 @@ -317,6 +332,12 @@ static void ssb_pmu_pll_init(struct ssb_
251 case 0x5354:
252 ssb_pmu0_pllinit_r0(cc, crystalfreq);
253 break;
254 + case 0x4322:
255 + if (cc->pmu.rev == 2) {
256 + chipco_write32(cc, SSB_CHIPCO_PLLCTL_ADDR, 0x0000000A);
257 + chipco_write32(cc, SSB_CHIPCO_PLLCTL_DATA, 0x380005C0);
258 + }
259 + break;
260 default:
261 ssb_printk(KERN_ERR PFX
262 "ERROR: PLL init unknown for device %04X\n",
263 @@ -396,12 +417,15 @@ static void ssb_pmu_resources_init(struc
264 u32 min_msk = 0, max_msk = 0;
265 unsigned int i;
266 const struct pmu_res_updown_tab_entry *updown_tab = NULL;
267 - unsigned int updown_tab_size;
268 + unsigned int updown_tab_size = 0;
269 const struct pmu_res_depend_tab_entry *depend_tab = NULL;
270 - unsigned int depend_tab_size;
271 + unsigned int depend_tab_size = 0;
272
273 switch (bus->chip_id) {
274 case 0x4312:
275 + min_msk = 0xCBB;
276 + break;
277 + case 0x4322:
278 /* We keep the default settings:
279 * min_msk = 0xCBB
280 * max_msk = 0x7FFFF
281 @@ -480,9 +504,9 @@ static void ssb_pmu_resources_init(struc
282 chipco_write32(cc, SSB_CHIPCO_PMU_MAXRES_MSK, max_msk);
283 }
284
285 +/* http://bcm-v4.sipsolutions.net/802.11/SSB/PmuInit */
286 void ssb_pmu_init(struct ssb_chipcommon *cc)
287 {
288 - struct ssb_bus *bus = cc->dev->bus;
289 u32 pmucap;
290
291 if (!(cc->capabilities & SSB_CHIPCO_CAP_PMU))
292 @@ -494,15 +518,91 @@ void ssb_pmu_init(struct ssb_chipcommon
293 ssb_dprintk(KERN_DEBUG PFX "Found rev %u PMU (capabilities 0x%08X)\n",
294 cc->pmu.rev, pmucap);
295
296 - if (cc->pmu.rev >= 1) {
297 - if ((bus->chip_id == 0x4325) && (bus->chip_rev < 2)) {
298 - chipco_mask32(cc, SSB_CHIPCO_PMU_CTL,
299 - ~SSB_CHIPCO_PMU_CTL_NOILPONW);
300 - } else {
301 - chipco_set32(cc, SSB_CHIPCO_PMU_CTL,
302 - SSB_CHIPCO_PMU_CTL_NOILPONW);
303 - }
304 - }
305 + if (cc->pmu.rev == 1)
306 + chipco_mask32(cc, SSB_CHIPCO_PMU_CTL,
307 + ~SSB_CHIPCO_PMU_CTL_NOILPONW);
308 + else
309 + chipco_set32(cc, SSB_CHIPCO_PMU_CTL,
310 + SSB_CHIPCO_PMU_CTL_NOILPONW);
311 ssb_pmu_pll_init(cc);
312 ssb_pmu_resources_init(cc);
313 }
314 +
315 +void ssb_pmu_set_ldo_voltage(struct ssb_chipcommon *cc,
316 + enum ssb_pmu_ldo_volt_id id, u32 voltage)
317 +{
318 + struct ssb_bus *bus = cc->dev->bus;
319 + u32 addr, shift, mask;
320 +
321 + switch (bus->chip_id) {
322 + case 0x4328:
323 + case 0x5354:
324 + switch (id) {
325 + case LDO_VOLT1:
326 + addr = 2;
327 + shift = 25;
328 + mask = 0xF;
329 + break;
330 + case LDO_VOLT2:
331 + addr = 3;
332 + shift = 1;
333 + mask = 0xF;
334 + break;
335 + case LDO_VOLT3:
336 + addr = 3;
337 + shift = 9;
338 + mask = 0xF;
339 + break;
340 + case LDO_PAREF:
341 + addr = 3;
342 + shift = 17;
343 + mask = 0x3F;
344 + break;
345 + default:
346 + SSB_WARN_ON(1);
347 + return;
348 + }
349 + break;
350 + case 0x4312:
351 + if (SSB_WARN_ON(id != LDO_PAREF))
352 + return;
353 + addr = 0;
354 + shift = 21;
355 + mask = 0x3F;
356 + break;
357 + default:
358 + return;
359 + }
360 +
361 + ssb_chipco_regctl_maskset(cc, addr, ~(mask << shift),
362 + (voltage & mask) << shift);
363 +}
364 +
365 +void ssb_pmu_set_ldo_paref(struct ssb_chipcommon *cc, bool on)
366 +{
367 + struct ssb_bus *bus = cc->dev->bus;
368 + int ldo;
369 +
370 + switch (bus->chip_id) {
371 + case 0x4312:
372 + ldo = SSB_PMURES_4312_PA_REF_LDO;
373 + break;
374 + case 0x4328:
375 + ldo = SSB_PMURES_4328_PA_REF_LDO;
376 + break;
377 + case 0x5354:
378 + ldo = SSB_PMURES_5354_PA_REF_LDO;
379 + break;
380 + default:
381 + return;
382 + }
383 +
384 + if (on)
385 + chipco_set32(cc, SSB_CHIPCO_PMU_MINRES_MSK, 1 << ldo);
386 + else
387 + chipco_mask32(cc, SSB_CHIPCO_PMU_MINRES_MSK, ~(1 << ldo));
388 + chipco_read32(cc, SSB_CHIPCO_PMU_MINRES_MSK); //SPEC FIXME found via mmiotrace - dummy read?
389 +}
390 +
391 +EXPORT_SYMBOL(ssb_pmu_set_ldo_voltage);
392 +EXPORT_SYMBOL(ssb_pmu_set_ldo_paref);
393 --- a/drivers/ssb/driver_gige.c
394 +++ b/drivers/ssb/driver_gige.c
395 @@ -3,7 +3,7 @@
396 * Broadcom Gigabit Ethernet core driver
397 *
398 * Copyright 2008, Broadcom Corporation
399 - * Copyright 2008, Michael Buesch <mb@bu3sch.de>
400 + * Copyright 2008, Michael Buesch <m@bues.ch>
401 *
402 * Licensed under the GNU/GPL. See COPYING for details.
403 */
404 @@ -12,6 +12,7 @@
405 #include <linux/ssb/ssb_driver_gige.h>
406 #include <linux/pci.h>
407 #include <linux/pci_regs.h>
408 +#include <linux/slab.h>
409
410
411 /*
412 @@ -105,8 +106,9 @@ void gige_pcicfg_write32(struct ssb_gige
413 gige_write32(dev, SSB_GIGE_PCICFG + offset, value);
414 }
415
416 -static int ssb_gige_pci_read_config(struct pci_bus *bus, unsigned int devfn,
417 - int reg, int size, u32 *val)
418 +static int __devinit ssb_gige_pci_read_config(struct pci_bus *bus,
419 + unsigned int devfn, int reg,
420 + int size, u32 *val)
421 {
422 struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
423 unsigned long flags;
424 @@ -135,8 +137,9 @@ static int ssb_gige_pci_read_config(stru
425 return PCIBIOS_SUCCESSFUL;
426 }
427
428 -static int ssb_gige_pci_write_config(struct pci_bus *bus, unsigned int devfn,
429 - int reg, int size, u32 val)
430 +static int __devinit ssb_gige_pci_write_config(struct pci_bus *bus,
431 + unsigned int devfn, int reg,
432 + int size, u32 val)
433 {
434 struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
435 unsigned long flags;
436 @@ -165,7 +168,8 @@ static int ssb_gige_pci_write_config(str
437 return PCIBIOS_SUCCESSFUL;
438 }
439
440 -static int ssb_gige_probe(struct ssb_device *sdev, const struct ssb_device_id *id)
441 +static int __devinit ssb_gige_probe(struct ssb_device *sdev,
442 + const struct ssb_device_id *id)
443 {
444 struct ssb_gige *dev;
445 u32 base, tmslow, tmshigh;
446 --- a/drivers/ssb/driver_mipscore.c
447 +++ b/drivers/ssb/driver_mipscore.c
448 @@ -3,7 +3,7 @@
449 * Broadcom MIPS core driver
450 *
451 * Copyright 2005, Broadcom Corporation
452 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
453 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
454 *
455 * Licensed under the GNU/GPL. See COPYING for details.
456 */
457 @@ -49,29 +49,54 @@ static const u32 ipsflag_irq_shift[] = {
458
459 static inline u32 ssb_irqflag(struct ssb_device *dev)
460 {
461 - return ssb_read32(dev, SSB_TPSFLAG) & SSB_TPSFLAG_BPFLAG;
462 + u32 tpsflag = ssb_read32(dev, SSB_TPSFLAG);
463 + if (tpsflag)
464 + return ssb_read32(dev, SSB_TPSFLAG) & SSB_TPSFLAG_BPFLAG;
465 + else
466 + /* not irq supported */
467 + return 0x3f;
468 +}
469 +
470 +static struct ssb_device *find_device(struct ssb_device *rdev, int irqflag)
471 +{
472 + struct ssb_bus *bus = rdev->bus;
473 + int i;
474 + for (i = 0; i < bus->nr_devices; i++) {
475 + struct ssb_device *dev;
476 + dev = &(bus->devices[i]);
477 + if (ssb_irqflag(dev) == irqflag)
478 + return dev;
479 + }
480 + return NULL;
481 }
482
483 /* Get the MIPS IRQ assignment for a specified device.
484 * If unassigned, 0 is returned.
485 + * If disabled, 5 is returned.
486 + * If not supported, 6 is returned.
487 */
488 unsigned int ssb_mips_irq(struct ssb_device *dev)
489 {
490 struct ssb_bus *bus = dev->bus;
491 + struct ssb_device *mdev = bus->mipscore.dev;
492 u32 irqflag;
493 u32 ipsflag;
494 u32 tmp;
495 unsigned int irq;
496
497 irqflag = ssb_irqflag(dev);
498 + if (irqflag == 0x3f)
499 + return 6;
500 ipsflag = ssb_read32(bus->mipscore.dev, SSB_IPSFLAG);
501 for (irq = 1; irq <= 4; irq++) {
502 tmp = ((ipsflag & ipsflag_irq_mask[irq]) >> ipsflag_irq_shift[irq]);
503 if (tmp == irqflag)
504 break;
505 }
506 - if (irq == 5)
507 - irq = 0;
508 + if (irq == 5) {
509 + if ((1 << irqflag) & ssb_read32(mdev, SSB_INTVEC))
510 + irq = 0;
511 + }
512
513 return irq;
514 }
515 @@ -97,25 +122,56 @@ static void set_irq(struct ssb_device *d
516 struct ssb_device *mdev = bus->mipscore.dev;
517 u32 irqflag = ssb_irqflag(dev);
518
519 + BUG_ON(oldirq == 6);
520 +
521 dev->irq = irq + 2;
522
523 - ssb_dprintk(KERN_INFO PFX
524 - "set_irq: core 0x%04x, irq %d => %d\n",
525 - dev->id.coreid, oldirq, irq);
526 /* clear the old irq */
527 if (oldirq == 0)
528 ssb_write32(mdev, SSB_INTVEC, (~(1 << irqflag) & ssb_read32(mdev, SSB_INTVEC)));
529 - else
530 + else if (oldirq != 5)
531 clear_irq(bus, oldirq);
532
533 /* assign the new one */
534 if (irq == 0) {
535 ssb_write32(mdev, SSB_INTVEC, ((1 << irqflag) | ssb_read32(mdev, SSB_INTVEC)));
536 } else {
537 + u32 ipsflag = ssb_read32(mdev, SSB_IPSFLAG);
538 + if ((ipsflag & ipsflag_irq_mask[irq]) != ipsflag_irq_mask[irq]) {
539 + u32 oldipsflag = (ipsflag & ipsflag_irq_mask[irq]) >> ipsflag_irq_shift[irq];
540 + struct ssb_device *olddev = find_device(dev, oldipsflag);
541 + if (olddev)
542 + set_irq(olddev, 0);
543 + }
544 irqflag <<= ipsflag_irq_shift[irq];
545 - irqflag |= (ssb_read32(mdev, SSB_IPSFLAG) & ~ipsflag_irq_mask[irq]);
546 + irqflag |= (ipsflag & ~ipsflag_irq_mask[irq]);
547 ssb_write32(mdev, SSB_IPSFLAG, irqflag);
548 }
549 + ssb_dprintk(KERN_INFO PFX
550 + "set_irq: core 0x%04x, irq %d => %d\n",
551 + dev->id.coreid, oldirq+2, irq+2);
552 +}
553 +
554 +static void print_irq(struct ssb_device *dev, unsigned int irq)
555 +{
556 + int i;
557 + static const char *irq_name[] = {"2(S)", "3", "4", "5", "6", "D", "I"};
558 + ssb_dprintk(KERN_INFO PFX
559 + "core 0x%04x, irq :", dev->id.coreid);
560 + for (i = 0; i <= 6; i++) {
561 + ssb_dprintk(" %s%s", irq_name[i], i==irq?"*":" ");
562 + }
563 + ssb_dprintk("\n");
564 +}
565 +
566 +static void dump_irq(struct ssb_bus *bus)
567 +{
568 + int i;
569 + for (i = 0; i < bus->nr_devices; i++) {
570 + struct ssb_device *dev;
571 + dev = &(bus->devices[i]);
572 + print_irq(dev, ssb_mips_irq(dev));
573 + }
574 }
575
576 static void ssb_mips_serial_init(struct ssb_mipscore *mcore)
577 @@ -197,17 +253,23 @@ void ssb_mipscore_init(struct ssb_mipsco
578
579 /* Assign IRQs to all cores on the bus, start with irq line 2, because serial usually takes 1 */
580 for (irq = 2, i = 0; i < bus->nr_devices; i++) {
581 + int mips_irq;
582 dev = &(bus->devices[i]);
583 - dev->irq = ssb_mips_irq(dev) + 2;
584 + mips_irq = ssb_mips_irq(dev);
585 + if (mips_irq > 4)
586 + dev->irq = 0;
587 + else
588 + dev->irq = mips_irq + 2;
589 + if (dev->irq > 5)
590 + continue;
591 switch (dev->id.coreid) {
592 case SSB_DEV_USB11_HOST:
593 /* shouldn't need a separate irq line for non-4710, most of them have a proper
594 * external usb controller on the pci */
595 if ((bus->chip_id == 0x4710) && (irq <= 4)) {
596 set_irq(dev, irq++);
597 - break;
598 }
599 - /* fallthrough */
600 + break;
601 case SSB_DEV_PCI:
602 case SSB_DEV_ETHERNET:
603 case SSB_DEV_ETHERNET_GBIT:
604 @@ -218,8 +280,14 @@ void ssb_mipscore_init(struct ssb_mipsco
605 set_irq(dev, irq++);
606 break;
607 }
608 + /* fallthrough */
609 + case SSB_DEV_EXTIF:
610 + set_irq(dev, 0);
611 + break;
612 }
613 }
614 + ssb_dprintk(KERN_INFO PFX "after irq reconfiguration\n");
615 + dump_irq(bus);
616
617 ssb_mips_serial_init(mcore);
618 ssb_mips_flash_detect(mcore);
619 --- a/drivers/ssb/driver_pcicore.c
620 +++ b/drivers/ssb/driver_pcicore.c
621 @@ -3,7 +3,7 @@
622 * Broadcom PCI-core driver
623 *
624 * Copyright 2005, Broadcom Corporation
625 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
626 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
627 *
628 * Licensed under the GNU/GPL. See COPYING for details.
629 */
630 @@ -15,6 +15,11 @@
631
632 #include "ssb_private.h"
633
634 +static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address);
635 +static void ssb_pcie_write(struct ssb_pcicore *pc, u32 address, u32 data);
636 +static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address);
637 +static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
638 + u8 address, u16 data);
639
640 static inline
641 u32 pcicore_read32(struct ssb_pcicore *pc, u16 offset)
642 @@ -246,20 +251,12 @@ static struct pci_controller ssb_pcicore
643 .pci_ops = &ssb_pcicore_pciops,
644 .io_resource = &ssb_pcicore_io_resource,
645 .mem_resource = &ssb_pcicore_mem_resource,
646 - .mem_offset = 0x24000000,
647 };
648
649 -static u32 ssb_pcicore_pcibus_iobase = 0x100;
650 -static u32 ssb_pcicore_pcibus_membase = SSB_PCI_DMA;
651 -
652 /* This function is called when doing a pci_enable_device().
653 * We must first check if the device is a device on the PCI-core bridge. */
654 int ssb_pcicore_plat_dev_init(struct pci_dev *d)
655 {
656 - struct resource *res;
657 - int pos, size;
658 - u32 *base;
659 -
660 if (d->bus->ops != &ssb_pcicore_pciops) {
661 /* This is not a device on the PCI-core bridge. */
662 return -ENODEV;
663 @@ -268,27 +265,6 @@ int ssb_pcicore_plat_dev_init(struct pci
664 ssb_printk(KERN_INFO "PCI: Fixing up device %s\n",
665 pci_name(d));
666
667 - /* Fix up resource bases */
668 - for (pos = 0; pos < 6; pos++) {
669 - res = &d->resource[pos];
670 - if (res->flags & IORESOURCE_IO)
671 - base = &ssb_pcicore_pcibus_iobase;
672 - else
673 - base = &ssb_pcicore_pcibus_membase;
674 - res->flags |= IORESOURCE_PCI_FIXED;
675 - if (res->end) {
676 - size = res->end - res->start + 1;
677 - if (*base & (size - 1))
678 - *base = (*base + size) & ~(size - 1);
679 - res->start = *base;
680 - res->end = res->start + size - 1;
681 - *base += size;
682 - pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start);
683 - }
684 - /* Fix up PCI bridge BAR0 only */
685 - if (d->bus->number == 0 && PCI_SLOT(d->devfn) == 0)
686 - break;
687 - }
688 /* Fix up interrupt lines */
689 d->irq = ssb_mips_irq(extpci_core->dev) + 2;
690 pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq);
691 @@ -338,7 +314,7 @@ int ssb_pcicore_pcibios_map_irq(const st
692 return ssb_mips_irq(extpci_core->dev) + 2;
693 }
694
695 -static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
696 +static void __devinit ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
697 {
698 u32 val;
699
700 @@ -403,7 +379,7 @@ static void ssb_pcicore_init_hostmode(st
701 register_pci_controller(&ssb_pcicore_controller);
702 }
703
704 -static int pcicore_is_in_hostmode(struct ssb_pcicore *pc)
705 +static int __devinit pcicore_is_in_hostmode(struct ssb_pcicore *pc)
706 {
707 struct ssb_bus *bus = pc->dev->bus;
708 u16 chipid_top;
709 @@ -432,25 +408,137 @@ static int pcicore_is_in_hostmode(struct
710 }
711 #endif /* CONFIG_SSB_PCICORE_HOSTMODE */
712
713 +/**************************************************
714 + * Workarounds.
715 + **************************************************/
716 +
717 +static void __devinit ssb_pcicore_fix_sprom_core_index(struct ssb_pcicore *pc)
718 +{
719 + u16 tmp = pcicore_read16(pc, SSB_PCICORE_SPROM(0));
720 + if (((tmp & 0xF000) >> 12) != pc->dev->core_index) {
721 + tmp &= ~0xF000;
722 + tmp |= (pc->dev->core_index << 12);
723 + pcicore_write16(pc, SSB_PCICORE_SPROM(0), tmp);
724 + }
725 +}
726 +
727 +static u8 ssb_pcicore_polarity_workaround(struct ssb_pcicore *pc)
728 +{
729 + return (ssb_pcie_read(pc, 0x204) & 0x10) ? 0xC0 : 0x80;
730 +}
731 +
732 +static void ssb_pcicore_serdes_workaround(struct ssb_pcicore *pc)
733 +{
734 + const u8 serdes_pll_device = 0x1D;
735 + const u8 serdes_rx_device = 0x1F;
736 + u16 tmp;
737 +
738 + ssb_pcie_mdio_write(pc, serdes_rx_device, 1 /* Control */,
739 + ssb_pcicore_polarity_workaround(pc));
740 + tmp = ssb_pcie_mdio_read(pc, serdes_pll_device, 1 /* Control */);
741 + if (tmp & 0x4000)
742 + ssb_pcie_mdio_write(pc, serdes_pll_device, 1, tmp & ~0x4000);
743 +}
744 +
745 +static void ssb_pcicore_pci_setup_workarounds(struct ssb_pcicore *pc)
746 +{
747 + struct ssb_device *pdev = pc->dev;
748 + struct ssb_bus *bus = pdev->bus;
749 + u32 tmp;
750 +
751 + tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
752 + tmp |= SSB_PCICORE_SBTOPCI_PREF;
753 + tmp |= SSB_PCICORE_SBTOPCI_BURST;
754 + pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
755 +
756 + if (pdev->id.revision < 5) {
757 + tmp = ssb_read32(pdev, SSB_IMCFGLO);
758 + tmp &= ~SSB_IMCFGLO_SERTO;
759 + tmp |= 2;
760 + tmp &= ~SSB_IMCFGLO_REQTO;
761 + tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT;
762 + ssb_write32(pdev, SSB_IMCFGLO, tmp);
763 + ssb_commit_settings(bus);
764 + } else if (pdev->id.revision >= 11) {
765 + tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
766 + tmp |= SSB_PCICORE_SBTOPCI_MRM;
767 + pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
768 + }
769 +}
770 +
771 +static void ssb_pcicore_pcie_setup_workarounds(struct ssb_pcicore *pc)
772 +{
773 + u32 tmp;
774 + u8 rev = pc->dev->id.revision;
775 +
776 + if (rev == 0 || rev == 1) {
777 + /* TLP Workaround register. */
778 + tmp = ssb_pcie_read(pc, 0x4);
779 + tmp |= 0x8;
780 + ssb_pcie_write(pc, 0x4, tmp);
781 + }
782 + if (rev == 1) {
783 + /* DLLP Link Control register. */
784 + tmp = ssb_pcie_read(pc, 0x100);
785 + tmp |= 0x40;
786 + ssb_pcie_write(pc, 0x100, tmp);
787 + }
788 +
789 + if (rev == 0) {
790 + const u8 serdes_rx_device = 0x1F;
791 +
792 + ssb_pcie_mdio_write(pc, serdes_rx_device,
793 + 2 /* Timer */, 0x8128);
794 + ssb_pcie_mdio_write(pc, serdes_rx_device,
795 + 6 /* CDR */, 0x0100);
796 + ssb_pcie_mdio_write(pc, serdes_rx_device,
797 + 7 /* CDR BW */, 0x1466);
798 + } else if (rev == 3 || rev == 4 || rev == 5) {
799 + /* TODO: DLLP Power Management Threshold */
800 + ssb_pcicore_serdes_workaround(pc);
801 + /* TODO: ASPM */
802 + } else if (rev == 7) {
803 + /* TODO: No PLL down */
804 + }
805 +
806 + if (rev >= 6) {
807 + /* Miscellaneous Configuration Fixup */
808 + tmp = pcicore_read16(pc, SSB_PCICORE_SPROM(5));
809 + if (!(tmp & 0x8000))
810 + pcicore_write16(pc, SSB_PCICORE_SPROM(5),
811 + tmp | 0x8000);
812 + }
813 +}
814
815 /**************************************************
816 * Generic and Clientmode operation code.
817 **************************************************/
818
819 -static void ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)
820 +static void __devinit ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)
821 {
822 + struct ssb_device *pdev = pc->dev;
823 + struct ssb_bus *bus = pdev->bus;
824 +
825 + if (bus->bustype == SSB_BUSTYPE_PCI)
826 + ssb_pcicore_fix_sprom_core_index(pc);
827 +
828 /* Disable PCI interrupts. */
829 - ssb_write32(pc->dev, SSB_INTVEC, 0);
830 + ssb_write32(pdev, SSB_INTVEC, 0);
831 +
832 + /* Additional PCIe always once-executed workarounds */
833 + if (pc->dev->id.coreid == SSB_DEV_PCIE) {
834 + ssb_pcicore_serdes_workaround(pc);
835 + /* TODO: ASPM */
836 + /* TODO: Clock Request Update */
837 + }
838 }
839
840 -void ssb_pcicore_init(struct ssb_pcicore *pc)
841 +void __devinit ssb_pcicore_init(struct ssb_pcicore *pc)
842 {
843 struct ssb_device *dev = pc->dev;
844 - struct ssb_bus *bus;
845
846 if (!dev)
847 return;
848 - bus = dev->bus;
849 if (!ssb_device_is_enabled(dev))
850 ssb_device_enable(dev, 0);
851
852 @@ -475,58 +563,104 @@ static void ssb_pcie_write(struct ssb_pc
853 pcicore_write32(pc, 0x134, data);
854 }
855
856 -static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
857 - u8 address, u16 data)
858 +static void ssb_pcie_mdio_set_phy(struct ssb_pcicore *pc, u8 phy)
859 {
860 const u16 mdio_control = 0x128;
861 const u16 mdio_data = 0x12C;
862 u32 v;
863 int i;
864
865 + v = (1 << 30); /* Start of Transaction */
866 + v |= (1 << 28); /* Write Transaction */
867 + v |= (1 << 17); /* Turnaround */
868 + v |= (0x1F << 18);
869 + v |= (phy << 4);
870 + pcicore_write32(pc, mdio_data, v);
871 +
872 + udelay(10);
873 + for (i = 0; i < 200; i++) {
874 + v = pcicore_read32(pc, mdio_control);
875 + if (v & 0x100 /* Trans complete */)
876 + break;
877 + msleep(1);
878 + }
879 +}
880 +
881 +static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address)
882 +{
883 + const u16 mdio_control = 0x128;
884 + const u16 mdio_data = 0x12C;
885 + int max_retries = 10;
886 + u16 ret = 0;
887 + u32 v;
888 + int i;
889 +
890 v = 0x80; /* Enable Preamble Sequence */
891 v |= 0x2; /* MDIO Clock Divisor */
892 pcicore_write32(pc, mdio_control, v);
893
894 + if (pc->dev->id.revision >= 10) {
895 + max_retries = 200;
896 + ssb_pcie_mdio_set_phy(pc, device);
897 + }
898 +
899 v = (1 << 30); /* Start of Transaction */
900 - v |= (1 << 28); /* Write Transaction */
901 + v |= (1 << 29); /* Read Transaction */
902 v |= (1 << 17); /* Turnaround */
903 - v |= (u32)device << 22;
904 + if (pc->dev->id.revision < 10)
905 + v |= (u32)device << 22;
906 v |= (u32)address << 18;
907 - v |= data;
908 pcicore_write32(pc, mdio_data, v);
909 /* Wait for the device to complete the transaction */
910 udelay(10);
911 - for (i = 0; i < 10; i++) {
912 + for (i = 0; i < max_retries; i++) {
913 v = pcicore_read32(pc, mdio_control);
914 - if (v & 0x100 /* Trans complete */)
915 + if (v & 0x100 /* Trans complete */) {
916 + udelay(10);
917 + ret = pcicore_read32(pc, mdio_data);
918 break;
919 + }
920 msleep(1);
921 }
922 pcicore_write32(pc, mdio_control, 0);
923 + return ret;
924 }
925
926 -static void ssb_broadcast_value(struct ssb_device *dev,
927 - u32 address, u32 data)
928 +static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
929 + u8 address, u16 data)
930 {
931 - /* This is used for both, PCI and ChipCommon core, so be careful. */
932 - BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
933 - BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
934 + const u16 mdio_control = 0x128;
935 + const u16 mdio_data = 0x12C;
936 + int max_retries = 10;
937 + u32 v;
938 + int i;
939
940 - ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address);
941 - ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */
942 - ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data);
943 - ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */
944 -}
945 + v = 0x80; /* Enable Preamble Sequence */
946 + v |= 0x2; /* MDIO Clock Divisor */
947 + pcicore_write32(pc, mdio_control, v);
948
949 -static void ssb_commit_settings(struct ssb_bus *bus)
950 -{
951 - struct ssb_device *dev;
952 + if (pc->dev->id.revision >= 10) {
953 + max_retries = 200;
954 + ssb_pcie_mdio_set_phy(pc, device);
955 + }
956
957 - dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
958 - if (WARN_ON(!dev))
959 - return;
960 - /* This forces an update of the cached registers. */
961 - ssb_broadcast_value(dev, 0xFD8, 0);
962 + v = (1 << 30); /* Start of Transaction */
963 + v |= (1 << 28); /* Write Transaction */
964 + v |= (1 << 17); /* Turnaround */
965 + if (pc->dev->id.revision < 10)
966 + v |= (u32)device << 22;
967 + v |= (u32)address << 18;
968 + v |= data;
969 + pcicore_write32(pc, mdio_data, v);
970 + /* Wait for the device to complete the transaction */
971 + udelay(10);
972 + for (i = 0; i < max_retries; i++) {
973 + v = pcicore_read32(pc, mdio_control);
974 + if (v & 0x100 /* Trans complete */)
975 + break;
976 + msleep(1);
977 + }
978 + pcicore_write32(pc, mdio_control, 0);
979 }
980
981 int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
982 @@ -551,13 +685,13 @@ int ssb_pcicore_dev_irqvecs_enable(struc
983 might_sleep_if(pdev->id.coreid != SSB_DEV_PCI);
984
985 /* Enable interrupts for this device. */
986 - if (bus->host_pci &&
987 - ((pdev->id.revision >= 6) || (pdev->id.coreid == SSB_DEV_PCIE))) {
988 + if ((pdev->id.revision >= 6) || (pdev->id.coreid == SSB_DEV_PCIE)) {
989 u32 coremask;
990
991 /* Calculate the "coremask" for the device. */
992 coremask = (1 << dev->core_index);
993
994 + SSB_WARN_ON(bus->bustype != SSB_BUSTYPE_PCI);
995 err = pci_read_config_dword(bus->host_pci, SSB_PCI_IRQMASK, &tmp);
996 if (err)
997 goto out;
998 @@ -579,48 +713,10 @@ int ssb_pcicore_dev_irqvecs_enable(struc
999 if (pc->setup_done)
1000 goto out;
1001 if (pdev->id.coreid == SSB_DEV_PCI) {
1002 - tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
1003 - tmp |= SSB_PCICORE_SBTOPCI_PREF;
1004 - tmp |= SSB_PCICORE_SBTOPCI_BURST;
1005 - pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
1006 -
1007 - if (pdev->id.revision < 5) {
1008 - tmp = ssb_read32(pdev, SSB_IMCFGLO);
1009 - tmp &= ~SSB_IMCFGLO_SERTO;
1010 - tmp |= 2;
1011 - tmp &= ~SSB_IMCFGLO_REQTO;
1012 - tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT;
1013 - ssb_write32(pdev, SSB_IMCFGLO, tmp);
1014 - ssb_commit_settings(bus);
1015 - } else if (pdev->id.revision >= 11) {
1016 - tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
1017 - tmp |= SSB_PCICORE_SBTOPCI_MRM;
1018 - pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
1019 - }
1020 + ssb_pcicore_pci_setup_workarounds(pc);
1021 } else {
1022 WARN_ON(pdev->id.coreid != SSB_DEV_PCIE);
1023 - //TODO: Better make defines for all these magic PCIE values.
1024 - if ((pdev->id.revision == 0) || (pdev->id.revision == 1)) {
1025 - /* TLP Workaround register. */
1026 - tmp = ssb_pcie_read(pc, 0x4);
1027 - tmp |= 0x8;
1028 - ssb_pcie_write(pc, 0x4, tmp);
1029 - }
1030 - if (pdev->id.revision == 0) {
1031 - const u8 serdes_rx_device = 0x1F;
1032 -
1033 - ssb_pcie_mdio_write(pc, serdes_rx_device,
1034 - 2 /* Timer */, 0x8128);
1035 - ssb_pcie_mdio_write(pc, serdes_rx_device,
1036 - 6 /* CDR */, 0x0100);
1037 - ssb_pcie_mdio_write(pc, serdes_rx_device,
1038 - 7 /* CDR BW */, 0x1466);
1039 - } else if (pdev->id.revision == 1) {
1040 - /* DLLP Link Control register. */
1041 - tmp = ssb_pcie_read(pc, 0x100);
1042 - tmp |= 0x40;
1043 - ssb_pcie_write(pc, 0x100, tmp);
1044 - }
1045 + ssb_pcicore_pcie_setup_workarounds(pc);
1046 }
1047 pc->setup_done = 1;
1048 out:
1049 --- a/drivers/ssb/main.c
1050 +++ b/drivers/ssb/main.c
1051 @@ -3,7 +3,7 @@
1052 * Subsystem core
1053 *
1054 * Copyright 2005, Broadcom Corporation
1055 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
1056 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
1057 *
1058 * Licensed under the GNU/GPL. See COPYING for details.
1059 */
1060 @@ -12,11 +12,14 @@
1061
1062 #include <linux/delay.h>
1063 #include <linux/io.h>
1064 +#include <linux/module.h>
1065 #include <linux/ssb/ssb.h>
1066 #include <linux/ssb/ssb_regs.h>
1067 #include <linux/ssb/ssb_driver_gige.h>
1068 #include <linux/dma-mapping.h>
1069 #include <linux/pci.h>
1070 +#include <linux/mmc/sdio_func.h>
1071 +#include <linux/slab.h>
1072
1073 #include <pcmcia/cs_types.h>
1074 #include <pcmcia/cs.h>
1075 @@ -88,6 +91,25 @@ found:
1076 }
1077 #endif /* CONFIG_SSB_PCMCIAHOST */
1078
1079 +#ifdef CONFIG_SSB_SDIOHOST
1080 +struct ssb_bus *ssb_sdio_func_to_bus(struct sdio_func *func)
1081 +{
1082 + struct ssb_bus *bus;
1083 +
1084 + ssb_buses_lock();
1085 + list_for_each_entry(bus, &buses, list) {
1086 + if (bus->bustype == SSB_BUSTYPE_SDIO &&
1087 + bus->host_sdio == func)
1088 + goto found;
1089 + }
1090 + bus = NULL;
1091 +found:
1092 + ssb_buses_unlock();
1093 +
1094 + return bus;
1095 +}
1096 +#endif /* CONFIG_SSB_SDIOHOST */
1097 +
1098 int ssb_for_each_bus_call(unsigned long data,
1099 int (*func)(struct ssb_bus *bus, unsigned long data))
1100 {
1101 @@ -120,6 +142,19 @@ static void ssb_device_put(struct ssb_de
1102 put_device(dev->dev);
1103 }
1104
1105 +static inline struct ssb_driver *ssb_driver_get(struct ssb_driver *drv)
1106 +{
1107 + if (drv)
1108 + get_driver(&drv->drv);
1109 + return drv;
1110 +}
1111 +
1112 +static inline void ssb_driver_put(struct ssb_driver *drv)
1113 +{
1114 + if (drv)
1115 + put_driver(&drv->drv);
1116 +}
1117 +
1118 static int ssb_device_resume(struct device *dev)
1119 {
1120 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
1121 @@ -190,90 +225,81 @@ int ssb_bus_suspend(struct ssb_bus *bus)
1122 EXPORT_SYMBOL(ssb_bus_suspend);
1123
1124 #ifdef CONFIG_SSB_SPROM
1125 -int ssb_devices_freeze(struct ssb_bus *bus)
1126 +/** ssb_devices_freeze - Freeze all devices on the bus.
1127 + *
1128 + * After freezing no device driver will be handling a device
1129 + * on this bus anymore. ssb_devices_thaw() must be called after
1130 + * a successful freeze to reactivate the devices.
1131 + *
1132 + * @bus: The bus.
1133 + * @ctx: Context structure. Pass this to ssb_devices_thaw().
1134 + */
1135 +int ssb_devices_freeze(struct ssb_bus *bus, struct ssb_freeze_context *ctx)
1136 {
1137 - struct ssb_device *dev;
1138 - struct ssb_driver *drv;
1139 - int err = 0;
1140 - int i;
1141 - pm_message_t state = PMSG_FREEZE;
1142 + struct ssb_device *sdev;
1143 + struct ssb_driver *sdrv;
1144 + unsigned int i;
1145 +
1146 + memset(ctx, 0, sizeof(*ctx));
1147 + ctx->bus = bus;
1148 + SSB_WARN_ON(bus->nr_devices > ARRAY_SIZE(ctx->device_frozen));
1149
1150 - /* First check that we are capable to freeze all devices. */
1151 for (i = 0; i < bus->nr_devices; i++) {
1152 - dev = &(bus->devices[i]);
1153 - if (!dev->dev ||
1154 - !dev->dev->driver ||
1155 - !device_is_registered(dev->dev))
1156 - continue;
1157 - drv = drv_to_ssb_drv(dev->dev->driver);
1158 - if (!drv)
1159 + sdev = ssb_device_get(&bus->devices[i]);
1160 +
1161 + if (!sdev->dev || !sdev->dev->driver ||
1162 + !device_is_registered(sdev->dev)) {
1163 + ssb_device_put(sdev);
1164 continue;
1165 - if (!drv->suspend) {
1166 - /* Nope, can't suspend this one. */
1167 - return -EOPNOTSUPP;
1168 }
1169 - }
1170 - /* Now suspend all devices */
1171 - for (i = 0; i < bus->nr_devices; i++) {
1172 - dev = &(bus->devices[i]);
1173 - if (!dev->dev ||
1174 - !dev->dev->driver ||
1175 - !device_is_registered(dev->dev))
1176 - continue;
1177 - drv = drv_to_ssb_drv(dev->dev->driver);
1178 - if (!drv)
1179 + sdrv = ssb_driver_get(drv_to_ssb_drv(sdev->dev->driver));
1180 + if (!sdrv || SSB_WARN_ON(!sdrv->remove)) {
1181 + ssb_device_put(sdev);
1182 continue;
1183 - err = drv->suspend(dev, state);
1184 - if (err) {
1185 - ssb_printk(KERN_ERR PFX "Failed to freeze device %s\n",
1186 - dev_name(dev->dev));
1187 - goto err_unwind;
1188 }
1189 + sdrv->remove(sdev);
1190 + ctx->device_frozen[i] = 1;
1191 }
1192
1193 return 0;
1194 -err_unwind:
1195 - for (i--; i >= 0; i--) {
1196 - dev = &(bus->devices[i]);
1197 - if (!dev->dev ||
1198 - !dev->dev->driver ||
1199 - !device_is_registered(dev->dev))
1200 - continue;
1201 - drv = drv_to_ssb_drv(dev->dev->driver);
1202 - if (!drv)
1203 - continue;
1204 - if (drv->resume)
1205 - drv->resume(dev);
1206 - }
1207 - return err;
1208 }
1209
1210 -int ssb_devices_thaw(struct ssb_bus *bus)
1211 +/** ssb_devices_thaw - Unfreeze all devices on the bus.
1212 + *
1213 + * This will re-attach the device drivers and re-init the devices.
1214 + *
1215 + * @ctx: The context structure from ssb_devices_freeze()
1216 + */
1217 +int ssb_devices_thaw(struct ssb_freeze_context *ctx)
1218 {
1219 - struct ssb_device *dev;
1220 - struct ssb_driver *drv;
1221 - int err;
1222 - int i;
1223 + struct ssb_bus *bus = ctx->bus;
1224 + struct ssb_device *sdev;
1225 + struct ssb_driver *sdrv;
1226 + unsigned int i;
1227 + int err, result = 0;
1228
1229 for (i = 0; i < bus->nr_devices; i++) {
1230 - dev = &(bus->devices[i]);
1231 - if (!dev->dev ||
1232 - !dev->dev->driver ||
1233 - !device_is_registered(dev->dev))
1234 + if (!ctx->device_frozen[i])
1235 continue;
1236 - drv = drv_to_ssb_drv(dev->dev->driver);
1237 - if (!drv)
1238 + sdev = &bus->devices[i];
1239 +
1240 + if (SSB_WARN_ON(!sdev->dev || !sdev->dev->driver))
1241 continue;
1242 - if (SSB_WARN_ON(!drv->resume))
1243 + sdrv = drv_to_ssb_drv(sdev->dev->driver);
1244 + if (SSB_WARN_ON(!sdrv || !sdrv->probe))
1245 continue;
1246 - err = drv->resume(dev);
1247 +
1248 + err = sdrv->probe(sdev, &sdev->id);
1249 if (err) {
1250 ssb_printk(KERN_ERR PFX "Failed to thaw device %s\n",
1251 - dev_name(dev->dev));
1252 + dev_name(sdev->dev));
1253 + result = err;
1254 }
1255 + ssb_driver_put(sdrv);
1256 + ssb_device_put(sdev);
1257 }
1258
1259 - return 0;
1260 + return result;
1261 }
1262 #endif /* CONFIG_SSB_SPROM */
1263
1264 @@ -360,6 +386,35 @@ static int ssb_device_uevent(struct devi
1265 ssb_dev->id.revision);
1266 }
1267
1268 +#define ssb_config_attr(attrib, field, format_string) \
1269 +static ssize_t \
1270 +attrib##_show(struct device *dev, struct device_attribute *attr, char *buf) \
1271 +{ \
1272 + return sprintf(buf, format_string, dev_to_ssb_dev(dev)->field); \
1273 +}
1274 +
1275 +ssb_config_attr(core_num, core_index, "%u\n")
1276 +ssb_config_attr(coreid, id.coreid, "0x%04x\n")
1277 +ssb_config_attr(vendor, id.vendor, "0x%04x\n")
1278 +ssb_config_attr(revision, id.revision, "%u\n")
1279 +ssb_config_attr(irq, irq, "%u\n")
1280 +static ssize_t
1281 +name_show(struct device *dev, struct device_attribute *attr, char *buf)
1282 +{
1283 + return sprintf(buf, "%s\n",
1284 + ssb_core_name(dev_to_ssb_dev(dev)->id.coreid));
1285 +}
1286 +
1287 +static struct device_attribute ssb_device_attrs[] = {
1288 + __ATTR_RO(name),
1289 + __ATTR_RO(core_num),
1290 + __ATTR_RO(coreid),
1291 + __ATTR_RO(vendor),
1292 + __ATTR_RO(revision),
1293 + __ATTR_RO(irq),
1294 + __ATTR_NULL,
1295 +};
1296 +
1297 static struct bus_type ssb_bustype = {
1298 .name = "ssb",
1299 .match = ssb_bus_match,
1300 @@ -369,6 +424,7 @@ static struct bus_type ssb_bustype = {
1301 .suspend = ssb_device_suspend,
1302 .resume = ssb_device_resume,
1303 .uevent = ssb_device_uevent,
1304 + .dev_attrs = ssb_device_attrs,
1305 };
1306
1307 static void ssb_buses_lock(void)
1308 @@ -461,6 +517,7 @@ static int ssb_devices_register(struct s
1309 #ifdef CONFIG_SSB_PCIHOST
1310 sdev->irq = bus->host_pci->irq;
1311 dev->parent = &bus->host_pci->dev;
1312 + sdev->dma_dev = dev->parent;
1313 #endif
1314 break;
1315 case SSB_BUSTYPE_PCMCIA:
1316 @@ -469,8 +526,14 @@ static int ssb_devices_register(struct s
1317 dev->parent = &bus->host_pcmcia->dev;
1318 #endif
1319 break;
1320 + case SSB_BUSTYPE_SDIO:
1321 +#ifdef CONFIG_SSB_SDIOHOST
1322 + dev->parent = &bus->host_sdio->dev;
1323 +#endif
1324 + break;
1325 case SSB_BUSTYPE_SSB:
1326 dev->dma_mask = &dev->coherent_dma_mask;
1327 + sdev->dma_dev = dev;
1328 break;
1329 }
1330
1331 @@ -497,7 +560,7 @@ error:
1332 }
1333
1334 /* Needs ssb_buses_lock() */
1335 -static int ssb_attach_queued_buses(void)
1336 +static int __devinit ssb_attach_queued_buses(void)
1337 {
1338 struct ssb_bus *bus, *n;
1339 int err = 0;
1340 @@ -708,9 +771,9 @@ out:
1341 return err;
1342 }
1343
1344 -static int ssb_bus_register(struct ssb_bus *bus,
1345 - ssb_invariants_func_t get_invariants,
1346 - unsigned long baseaddr)
1347 +static int __devinit ssb_bus_register(struct ssb_bus *bus,
1348 + ssb_invariants_func_t get_invariants,
1349 + unsigned long baseaddr)
1350 {
1351 int err;
1352
1353 @@ -724,12 +787,18 @@ static int ssb_bus_register(struct ssb_b
1354 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
1355 if (err)
1356 goto out;
1357 +
1358 + /* Init SDIO-host device (if any), before the scan */
1359 + err = ssb_sdio_init(bus);
1360 + if (err)
1361 + goto err_disable_xtal;
1362 +
1363 ssb_buses_lock();
1364 bus->busnumber = next_busnumber;
1365 /* Scan for devices (cores) */
1366 err = ssb_bus_scan(bus, baseaddr);
1367 if (err)
1368 - goto err_disable_xtal;
1369 + goto err_sdio_exit;
1370
1371 /* Init PCI-host device (if any) */
1372 err = ssb_pci_init(bus);
1373 @@ -776,6 +845,8 @@ err_pci_exit:
1374 ssb_pci_exit(bus);
1375 err_unmap:
1376 ssb_iounmap(bus);
1377 +err_sdio_exit:
1378 + ssb_sdio_exit(bus);
1379 err_disable_xtal:
1380 ssb_buses_unlock();
1381 ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
1382 @@ -783,8 +854,8 @@ err_disable_xtal:
1383 }
1384
1385 #ifdef CONFIG_SSB_PCIHOST
1386 -int ssb_bus_pcibus_register(struct ssb_bus *bus,
1387 - struct pci_dev *host_pci)
1388 +int __devinit ssb_bus_pcibus_register(struct ssb_bus *bus,
1389 + struct pci_dev *host_pci)
1390 {
1391 int err;
1392
1393 @@ -796,6 +867,9 @@ int ssb_bus_pcibus_register(struct ssb_b
1394 if (!err) {
1395 ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
1396 "PCI device %s\n", dev_name(&host_pci->dev));
1397 + } else {
1398 + ssb_printk(KERN_ERR PFX "Failed to register PCI version"
1399 + " of SSB with error %d\n", err);
1400 }
1401
1402 return err;
1403 @@ -804,9 +878,9 @@ EXPORT_SYMBOL(ssb_bus_pcibus_register);
1404 #endif /* CONFIG_SSB_PCIHOST */
1405
1406 #ifdef CONFIG_SSB_PCMCIAHOST
1407 -int ssb_bus_pcmciabus_register(struct ssb_bus *bus,
1408 - struct pcmcia_device *pcmcia_dev,
1409 - unsigned long baseaddr)
1410 +int __devinit ssb_bus_pcmciabus_register(struct ssb_bus *bus,
1411 + struct pcmcia_device *pcmcia_dev,
1412 + unsigned long baseaddr)
1413 {
1414 int err;
1415
1416 @@ -825,9 +899,32 @@ int ssb_bus_pcmciabus_register(struct ss
1417 EXPORT_SYMBOL(ssb_bus_pcmciabus_register);
1418 #endif /* CONFIG_SSB_PCMCIAHOST */
1419
1420 -int ssb_bus_ssbbus_register(struct ssb_bus *bus,
1421 - unsigned long baseaddr,
1422 - ssb_invariants_func_t get_invariants)
1423 +#ifdef CONFIG_SSB_SDIOHOST
1424 +int __devinit ssb_bus_sdiobus_register(struct ssb_bus *bus,
1425 + struct sdio_func *func,
1426 + unsigned int quirks)
1427 +{
1428 + int err;
1429 +
1430 + bus->bustype = SSB_BUSTYPE_SDIO;
1431 + bus->host_sdio = func;
1432 + bus->ops = &ssb_sdio_ops;
1433 + bus->quirks = quirks;
1434 +
1435 + err = ssb_bus_register(bus, ssb_sdio_get_invariants, ~0);
1436 + if (!err) {
1437 + ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
1438 + "SDIO device %s\n", sdio_func_id(func));
1439 + }
1440 +
1441 + return err;
1442 +}
1443 +EXPORT_SYMBOL(ssb_bus_sdiobus_register);
1444 +#endif /* CONFIG_SSB_PCMCIAHOST */
1445 +
1446 +int __devinit ssb_bus_ssbbus_register(struct ssb_bus *bus,
1447 + unsigned long baseaddr,
1448 + ssb_invariants_func_t get_invariants)
1449 {
1450 int err;
1451
1452 @@ -908,8 +1005,8 @@ u32 ssb_calc_clock_rate(u32 plltype, u32
1453 switch (plltype) {
1454 case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
1455 if (m & SSB_CHIPCO_CLK_T6_MMASK)
1456 - return SSB_CHIPCO_CLK_T6_M0;
1457 - return SSB_CHIPCO_CLK_T6_M1;
1458 + return SSB_CHIPCO_CLK_T6_M1;
1459 + return SSB_CHIPCO_CLK_T6_M0;
1460 case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
1461 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
1462 case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
1463 @@ -1024,23 +1121,22 @@ static u32 ssb_tmslow_reject_bitmask(str
1464 {
1465 u32 rev = ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_SSBREV;
1466
1467 - /* The REJECT bit changed position in TMSLOW between
1468 - * Backplane revisions. */
1469 + /* The REJECT bit seems to be different for Backplane rev 2.3 */
1470 switch (rev) {
1471 case SSB_IDLOW_SSBREV_22:
1472 - return SSB_TMSLOW_REJECT_22;
1473 + case SSB_IDLOW_SSBREV_24:
1474 + case SSB_IDLOW_SSBREV_26:
1475 + return SSB_TMSLOW_REJECT;
1476 case SSB_IDLOW_SSBREV_23:
1477 return SSB_TMSLOW_REJECT_23;
1478 - case SSB_IDLOW_SSBREV_24: /* TODO - find the proper REJECT bits */
1479 - case SSB_IDLOW_SSBREV_25: /* same here */
1480 - case SSB_IDLOW_SSBREV_26: /* same here */
1481 + case SSB_IDLOW_SSBREV_25: /* TODO - find the proper REJECT bit */
1482 case SSB_IDLOW_SSBREV_27: /* same here */
1483 - return SSB_TMSLOW_REJECT_23; /* this is a guess */
1484 + return SSB_TMSLOW_REJECT; /* this is a guess */
1485 default:
1486 printk(KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
1487 WARN_ON(1);
1488 }
1489 - return (SSB_TMSLOW_REJECT_22 | SSB_TMSLOW_REJECT_23);
1490 + return (SSB_TMSLOW_REJECT | SSB_TMSLOW_REJECT_23);
1491 }
1492
1493 int ssb_device_is_enabled(struct ssb_device *dev)
1494 @@ -1099,10 +1195,10 @@ void ssb_device_enable(struct ssb_device
1495 }
1496 EXPORT_SYMBOL(ssb_device_enable);
1497
1498 -/* Wait for a bit in a register to get set or unset.
1499 +/* Wait for bitmask in a register to get set or cleared.
1500 * timeout is in units of ten-microseconds */
1501 -static int ssb_wait_bit(struct ssb_device *dev, u16 reg, u32 bitmask,
1502 - int timeout, int set)
1503 +static int ssb_wait_bits(struct ssb_device *dev, u16 reg, u32 bitmask,
1504 + int timeout, int set)
1505 {
1506 int i;
1507 u32 val;
1508 @@ -1110,7 +1206,7 @@ static int ssb_wait_bit(struct ssb_devic
1509 for (i = 0; i < timeout; i++) {
1510 val = ssb_read32(dev, reg);
1511 if (set) {
1512 - if (val & bitmask)
1513 + if ((val & bitmask) == bitmask)
1514 return 0;
1515 } else {
1516 if (!(val & bitmask))
1517 @@ -1127,20 +1223,38 @@ static int ssb_wait_bit(struct ssb_devic
1518
1519 void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags)
1520 {
1521 - u32 reject;
1522 + u32 reject, val;
1523
1524 if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_RESET)
1525 return;
1526
1527 reject = ssb_tmslow_reject_bitmask(dev);
1528 - ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK);
1529 - ssb_wait_bit(dev, SSB_TMSLOW, reject, 1000, 1);
1530 - ssb_wait_bit(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
1531 - ssb_write32(dev, SSB_TMSLOW,
1532 - SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
1533 - reject | SSB_TMSLOW_RESET |
1534 - core_specific_flags);
1535 - ssb_flush_tmslow(dev);
1536 +
1537 + if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_CLOCK) {
1538 + ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK);
1539 + ssb_wait_bits(dev, SSB_TMSLOW, reject, 1000, 1);
1540 + ssb_wait_bits(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
1541 +
1542 + if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
1543 + val = ssb_read32(dev, SSB_IMSTATE);
1544 + val |= SSB_IMSTATE_REJECT;
1545 + ssb_write32(dev, SSB_IMSTATE, val);
1546 + ssb_wait_bits(dev, SSB_IMSTATE, SSB_IMSTATE_BUSY, 1000,
1547 + 0);
1548 + }
1549 +
1550 + ssb_write32(dev, SSB_TMSLOW,
1551 + SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
1552 + reject | SSB_TMSLOW_RESET |
1553 + core_specific_flags);
1554 + ssb_flush_tmslow(dev);
1555 +
1556 + if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
1557 + val = ssb_read32(dev, SSB_IMSTATE);
1558 + val &= ~SSB_IMSTATE_REJECT;
1559 + ssb_write32(dev, SSB_IMSTATE, val);
1560 + }
1561 + }
1562
1563 ssb_write32(dev, SSB_TMSLOW,
1564 reject | SSB_TMSLOW_RESET |
1565 @@ -1149,13 +1263,34 @@ void ssb_device_disable(struct ssb_devic
1566 }
1567 EXPORT_SYMBOL(ssb_device_disable);
1568
1569 +/* Some chipsets need routing known for PCIe and 64-bit DMA */
1570 +static bool ssb_dma_translation_special_bit(struct ssb_device *dev)
1571 +{
1572 + u16 chip_id = dev->bus->chip_id;
1573 +
1574 + if (dev->id.coreid == SSB_DEV_80211) {
1575 + return (chip_id == 0x4322 || chip_id == 43221 ||
1576 + chip_id == 43231 || chip_id == 43222);
1577 + }
1578 +
1579 + return 0;
1580 +}
1581 +
1582 u32 ssb_dma_translation(struct ssb_device *dev)
1583 {
1584 switch (dev->bus->bustype) {
1585 case SSB_BUSTYPE_SSB:
1586 return 0;
1587 case SSB_BUSTYPE_PCI:
1588 - return SSB_PCI_DMA;
1589 + if (dev->bus->host_pci->is_pcie &&
1590 + ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_DMA64) {
1591 + return SSB_PCIE_DMA_H32;
1592 + } else {
1593 + if (ssb_dma_translation_special_bit(dev))
1594 + return SSB_PCIE_DMA_H32;
1595 + else
1596 + return SSB_PCI_DMA;
1597 + }
1598 default:
1599 __ssb_dma_not_implemented(dev);
1600 }
1601 @@ -1272,20 +1407,20 @@ EXPORT_SYMBOL(ssb_bus_may_powerdown);
1602
1603 int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl)
1604 {
1605 - struct ssb_chipcommon *cc;
1606 int err;
1607 enum ssb_clkmode mode;
1608
1609 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
1610 if (err)
1611 goto error;
1612 - cc = &bus->chipco;
1613 - mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
1614 - ssb_chipco_set_clockmode(cc, mode);
1615
1616 #ifdef CONFIG_SSB_DEBUG
1617 bus->powered_up = 1;
1618 #endif
1619 +
1620 + mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
1621 + ssb_chipco_set_clockmode(&bus->chipco, mode);
1622 +
1623 return 0;
1624 error:
1625 ssb_printk(KERN_ERR PFX "Bus powerup failed\n");
1626 @@ -1293,6 +1428,37 @@ error:
1627 }
1628 EXPORT_SYMBOL(ssb_bus_powerup);
1629
1630 +static void ssb_broadcast_value(struct ssb_device *dev,
1631 + u32 address, u32 data)
1632 +{
1633 +#ifdef CONFIG_SSB_DRIVER_PCICORE
1634 + /* This is used for both, PCI and ChipCommon core, so be careful. */
1635 + BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
1636 + BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
1637 +#endif
1638 +
1639 + ssb_write32(dev, SSB_CHIPCO_BCAST_ADDR, address);
1640 + ssb_read32(dev, SSB_CHIPCO_BCAST_ADDR); /* flush */
1641 + ssb_write32(dev, SSB_CHIPCO_BCAST_DATA, data);
1642 + ssb_read32(dev, SSB_CHIPCO_BCAST_DATA); /* flush */
1643 +}
1644 +
1645 +void ssb_commit_settings(struct ssb_bus *bus)
1646 +{
1647 + struct ssb_device *dev;
1648 +
1649 +#ifdef CONFIG_SSB_DRIVER_PCICORE
1650 + dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
1651 +#else
1652 + dev = bus->chipco.dev;
1653 +#endif
1654 + if (WARN_ON(!dev))
1655 + return;
1656 + /* This forces an update of the cached registers. */
1657 + ssb_broadcast_value(dev, 0xFD8, 0);
1658 +}
1659 +EXPORT_SYMBOL(ssb_commit_settings);
1660 +
1661 u32 ssb_admatch_base(u32 adm)
1662 {
1663 u32 base = 0;
1664 @@ -1358,8 +1524,10 @@ static int __init ssb_modinit(void)
1665 ssb_buses_lock();
1666 err = ssb_attach_queued_buses();
1667 ssb_buses_unlock();
1668 - if (err)
1669 + if (err) {
1670 bus_unregister(&ssb_bustype);
1671 + goto out;
1672 + }
1673
1674 err = b43_pci_ssb_bridge_init();
1675 if (err) {
1676 @@ -1375,7 +1543,7 @@ static int __init ssb_modinit(void)
1677 /* don't fail SSB init because of this */
1678 err = 0;
1679 }
1680 -
1681 +out:
1682 return err;
1683 }
1684 /* ssb must be initialized after PCI but before the ssb drivers.
1685 --- a/drivers/ssb/pci.c
1686 +++ b/drivers/ssb/pci.c
1687 @@ -1,7 +1,7 @@
1688 /*
1689 * Sonics Silicon Backplane PCI-Hostbus related functions.
1690 *
1691 - * Copyright (C) 2005-2006 Michael Buesch <mb@bu3sch.de>
1692 + * Copyright (C) 2005-2006 Michael Buesch <m@bues.ch>
1693 * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
1694 * Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
1695 * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
1696 @@ -17,6 +17,7 @@
1697
1698 #include <linux/ssb/ssb.h>
1699 #include <linux/ssb/ssb_regs.h>
1700 +#include <linux/slab.h>
1701 #include <linux/pci.h>
1702 #include <linux/delay.h>
1703
1704 @@ -167,10 +168,16 @@ err_pci:
1705 }
1706
1707 /* Get the word-offset for a SSB_SPROM_XXX define. */
1708 -#define SPOFF(offset) (((offset) - SSB_SPROM_BASE) / sizeof(u16))
1709 +#define SPOFF(offset) ((offset) / sizeof(u16))
1710 /* Helper to extract some _offset, which is one of the SSB_SPROM_XXX defines. */
1711 -#define SPEX(_outvar, _offset, _mask, _shift) \
1712 +#define SPEX16(_outvar, _offset, _mask, _shift) \
1713 out->_outvar = ((in[SPOFF(_offset)] & (_mask)) >> (_shift))
1714 +#define SPEX32(_outvar, _offset, _mask, _shift) \
1715 + out->_outvar = ((((u32)in[SPOFF((_offset)+2)] << 16 | \
1716 + in[SPOFF(_offset)]) & (_mask)) >> (_shift))
1717 +#define SPEX(_outvar, _offset, _mask, _shift) \
1718 + SPEX16(_outvar, _offset, _mask, _shift)
1719 +
1720
1721 static inline u8 ssb_crc8(u8 crc, u8 data)
1722 {
1723 @@ -247,7 +254,7 @@ static int sprom_do_read(struct ssb_bus
1724 int i;
1725
1726 for (i = 0; i < bus->sprom_size; i++)
1727 - sprom[i] = ioread16(bus->mmio + SSB_SPROM_BASE + (i * 2));
1728 + sprom[i] = ioread16(bus->mmio + bus->sprom_offset + (i * 2));
1729
1730 return 0;
1731 }
1732 @@ -278,7 +285,7 @@ static int sprom_do_write(struct ssb_bus
1733 ssb_printk("75%%");
1734 else if (i % 2)
1735 ssb_printk(".");
1736 - writew(sprom[i], bus->mmio + SSB_SPROM_BASE + (i * 2));
1737 + writew(sprom[i], bus->mmio + bus->sprom_offset + (i * 2));
1738 mmiowb();
1739 msleep(20);
1740 }
1741 @@ -399,6 +406,46 @@ static void sprom_extract_r123(struct ss
1742 out->antenna_gain.ghz5.a3 = gain;
1743 }
1744
1745 +/* Revs 4 5 and 8 have partially shared layout */
1746 +static void sprom_extract_r458(struct ssb_sprom *out, const u16 *in)
1747 +{
1748 + SPEX(txpid2g[0], SSB_SPROM4_TXPID2G01,
1749 + SSB_SPROM4_TXPID2G0, SSB_SPROM4_TXPID2G0_SHIFT);
1750 + SPEX(txpid2g[1], SSB_SPROM4_TXPID2G01,
1751 + SSB_SPROM4_TXPID2G1, SSB_SPROM4_TXPID2G1_SHIFT);
1752 + SPEX(txpid2g[2], SSB_SPROM4_TXPID2G23,
1753 + SSB_SPROM4_TXPID2G2, SSB_SPROM4_TXPID2G2_SHIFT);
1754 + SPEX(txpid2g[3], SSB_SPROM4_TXPID2G23,
1755 + SSB_SPROM4_TXPID2G3, SSB_SPROM4_TXPID2G3_SHIFT);
1756 +
1757 + SPEX(txpid5gl[0], SSB_SPROM4_TXPID5GL01,
1758 + SSB_SPROM4_TXPID5GL0, SSB_SPROM4_TXPID5GL0_SHIFT);
1759 + SPEX(txpid5gl[1], SSB_SPROM4_TXPID5GL01,
1760 + SSB_SPROM4_TXPID5GL1, SSB_SPROM4_TXPID5GL1_SHIFT);
1761 + SPEX(txpid5gl[2], SSB_SPROM4_TXPID5GL23,
1762 + SSB_SPROM4_TXPID5GL2, SSB_SPROM4_TXPID5GL2_SHIFT);
1763 + SPEX(txpid5gl[3], SSB_SPROM4_TXPID5GL23,
1764 + SSB_SPROM4_TXPID5GL3, SSB_SPROM4_TXPID5GL3_SHIFT);
1765 +
1766 + SPEX(txpid5g[0], SSB_SPROM4_TXPID5G01,
1767 + SSB_SPROM4_TXPID5G0, SSB_SPROM4_TXPID5G0_SHIFT);
1768 + SPEX(txpid5g[1], SSB_SPROM4_TXPID5G01,
1769 + SSB_SPROM4_TXPID5G1, SSB_SPROM4_TXPID5G1_SHIFT);
1770 + SPEX(txpid5g[2], SSB_SPROM4_TXPID5G23,
1771 + SSB_SPROM4_TXPID5G2, SSB_SPROM4_TXPID5G2_SHIFT);
1772 + SPEX(txpid5g[3], SSB_SPROM4_TXPID5G23,
1773 + SSB_SPROM4_TXPID5G3, SSB_SPROM4_TXPID5G3_SHIFT);
1774 +
1775 + SPEX(txpid5gh[0], SSB_SPROM4_TXPID5GH01,
1776 + SSB_SPROM4_TXPID5GH0, SSB_SPROM4_TXPID5GH0_SHIFT);
1777 + SPEX(txpid5gh[1], SSB_SPROM4_TXPID5GH01,
1778 + SSB_SPROM4_TXPID5GH1, SSB_SPROM4_TXPID5GH1_SHIFT);
1779 + SPEX(txpid5gh[2], SSB_SPROM4_TXPID5GH23,
1780 + SSB_SPROM4_TXPID5GH2, SSB_SPROM4_TXPID5GH2_SHIFT);
1781 + SPEX(txpid5gh[3], SSB_SPROM4_TXPID5GH23,
1782 + SSB_SPROM4_TXPID5GH3, SSB_SPROM4_TXPID5GH3_SHIFT);
1783 +}
1784 +
1785 static void sprom_extract_r45(struct ssb_sprom *out, const u16 *in)
1786 {
1787 int i;
1788 @@ -421,10 +468,14 @@ static void sprom_extract_r45(struct ssb
1789 SPEX(country_code, SSB_SPROM4_CCODE, 0xFFFF, 0);
1790 SPEX(boardflags_lo, SSB_SPROM4_BFLLO, 0xFFFF, 0);
1791 SPEX(boardflags_hi, SSB_SPROM4_BFLHI, 0xFFFF, 0);
1792 + SPEX(boardflags2_lo, SSB_SPROM4_BFL2LO, 0xFFFF, 0);
1793 + SPEX(boardflags2_hi, SSB_SPROM4_BFL2HI, 0xFFFF, 0);
1794 } else {
1795 SPEX(country_code, SSB_SPROM5_CCODE, 0xFFFF, 0);
1796 SPEX(boardflags_lo, SSB_SPROM5_BFLLO, 0xFFFF, 0);
1797 SPEX(boardflags_hi, SSB_SPROM5_BFLHI, 0xFFFF, 0);
1798 + SPEX(boardflags2_lo, SSB_SPROM5_BFL2LO, 0xFFFF, 0);
1799 + SPEX(boardflags2_hi, SSB_SPROM5_BFL2HI, 0xFFFF, 0);
1800 }
1801 SPEX(ant_available_a, SSB_SPROM4_ANTAVAIL, SSB_SPROM4_ANTAVAIL_A,
1802 SSB_SPROM4_ANTAVAIL_A_SHIFT);
1803 @@ -464,22 +515,32 @@ static void sprom_extract_r45(struct ssb
1804 memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
1805 sizeof(out->antenna_gain.ghz5));
1806
1807 + sprom_extract_r458(out, in);
1808 +
1809 /* TODO - get remaining rev 4 stuff needed */
1810 }
1811
1812 static void sprom_extract_r8(struct ssb_sprom *out, const u16 *in)
1813 {
1814 int i;
1815 - u16 v;
1816 + u16 v, o;
1817 + u16 pwr_info_offset[] = {
1818 + SSB_SROM8_PWR_INFO_CORE0, SSB_SROM8_PWR_INFO_CORE1,
1819 + SSB_SROM8_PWR_INFO_CORE2, SSB_SROM8_PWR_INFO_CORE3
1820 + };
1821 + BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
1822 + ARRAY_SIZE(out->core_pwr_info));
1823
1824 /* extract the MAC address */
1825 for (i = 0; i < 3; i++) {
1826 - v = in[SPOFF(SSB_SPROM1_IL0MAC) + i];
1827 + v = in[SPOFF(SSB_SPROM8_IL0MAC) + i];
1828 *(((__be16 *)out->il0mac) + i) = cpu_to_be16(v);
1829 }
1830 SPEX(country_code, SSB_SPROM8_CCODE, 0xFFFF, 0);
1831 SPEX(boardflags_lo, SSB_SPROM8_BFLLO, 0xFFFF, 0);
1832 SPEX(boardflags_hi, SSB_SPROM8_BFLHI, 0xFFFF, 0);
1833 + SPEX(boardflags2_lo, SSB_SPROM8_BFL2LO, 0xFFFF, 0);
1834 + SPEX(boardflags2_hi, SSB_SPROM8_BFL2HI, 0xFFFF, 0);
1835 SPEX(ant_available_a, SSB_SPROM8_ANTAVAIL, SSB_SPROM8_ANTAVAIL_A,
1836 SSB_SPROM8_ANTAVAIL_A_SHIFT);
1837 SPEX(ant_available_bg, SSB_SPROM8_ANTAVAIL, SSB_SPROM8_ANTAVAIL_BG,
1838 @@ -490,12 +551,55 @@ static void sprom_extract_r8(struct ssb_
1839 SPEX(maxpwr_a, SSB_SPROM8_MAXP_A, SSB_SPROM8_MAXP_A_MASK, 0);
1840 SPEX(itssi_a, SSB_SPROM8_MAXP_A, SSB_SPROM8_ITSSI_A,
1841 SSB_SPROM8_ITSSI_A_SHIFT);
1842 + SPEX(maxpwr_ah, SSB_SPROM8_MAXP_AHL, SSB_SPROM8_MAXP_AH_MASK, 0);
1843 + SPEX(maxpwr_al, SSB_SPROM8_MAXP_AHL, SSB_SPROM8_MAXP_AL_MASK,
1844 + SSB_SPROM8_MAXP_AL_SHIFT);
1845 SPEX(gpio0, SSB_SPROM8_GPIOA, SSB_SPROM8_GPIOA_P0, 0);
1846 SPEX(gpio1, SSB_SPROM8_GPIOA, SSB_SPROM8_GPIOA_P1,
1847 SSB_SPROM8_GPIOA_P1_SHIFT);
1848 SPEX(gpio2, SSB_SPROM8_GPIOB, SSB_SPROM8_GPIOB_P2, 0);
1849 SPEX(gpio3, SSB_SPROM8_GPIOB, SSB_SPROM8_GPIOB_P3,
1850 SSB_SPROM8_GPIOB_P3_SHIFT);
1851 + SPEX(tri2g, SSB_SPROM8_TRI25G, SSB_SPROM8_TRI2G, 0);
1852 + SPEX(tri5g, SSB_SPROM8_TRI25G, SSB_SPROM8_TRI5G,
1853 + SSB_SPROM8_TRI5G_SHIFT);
1854 + SPEX(tri5gl, SSB_SPROM8_TRI5GHL, SSB_SPROM8_TRI5GL, 0);
1855 + SPEX(tri5gh, SSB_SPROM8_TRI5GHL, SSB_SPROM8_TRI5GH,
1856 + SSB_SPROM8_TRI5GH_SHIFT);
1857 + SPEX(rxpo2g, SSB_SPROM8_RXPO, SSB_SPROM8_RXPO2G, 0);
1858 + SPEX(rxpo5g, SSB_SPROM8_RXPO, SSB_SPROM8_RXPO5G,
1859 + SSB_SPROM8_RXPO5G_SHIFT);
1860 + SPEX(rssismf2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISMF2G, 0);
1861 + SPEX(rssismc2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISMC2G,
1862 + SSB_SPROM8_RSSISMC2G_SHIFT);
1863 + SPEX(rssisav2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_RSSISAV2G,
1864 + SSB_SPROM8_RSSISAV2G_SHIFT);
1865 + SPEX(bxa2g, SSB_SPROM8_RSSIPARM2G, SSB_SPROM8_BXA2G,
1866 + SSB_SPROM8_BXA2G_SHIFT);
1867 + SPEX(rssismf5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISMF5G, 0);
1868 + SPEX(rssismc5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISMC5G,
1869 + SSB_SPROM8_RSSISMC5G_SHIFT);
1870 + SPEX(rssisav5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_RSSISAV5G,
1871 + SSB_SPROM8_RSSISAV5G_SHIFT);
1872 + SPEX(bxa5g, SSB_SPROM8_RSSIPARM5G, SSB_SPROM8_BXA5G,
1873 + SSB_SPROM8_BXA5G_SHIFT);
1874 + SPEX(pa0b0, SSB_SPROM8_PA0B0, 0xFFFF, 0);
1875 + SPEX(pa0b1, SSB_SPROM8_PA0B1, 0xFFFF, 0);
1876 + SPEX(pa0b2, SSB_SPROM8_PA0B2, 0xFFFF, 0);
1877 + SPEX(pa1b0, SSB_SPROM8_PA1B0, 0xFFFF, 0);
1878 + SPEX(pa1b1, SSB_SPROM8_PA1B1, 0xFFFF, 0);
1879 + SPEX(pa1b2, SSB_SPROM8_PA1B2, 0xFFFF, 0);
1880 + SPEX(pa1lob0, SSB_SPROM8_PA1LOB0, 0xFFFF, 0);
1881 + SPEX(pa1lob1, SSB_SPROM8_PA1LOB1, 0xFFFF, 0);
1882 + SPEX(pa1lob2, SSB_SPROM8_PA1LOB2, 0xFFFF, 0);
1883 + SPEX(pa1hib0, SSB_SPROM8_PA1HIB0, 0xFFFF, 0);
1884 + SPEX(pa1hib1, SSB_SPROM8_PA1HIB1, 0xFFFF, 0);
1885 + SPEX(pa1hib2, SSB_SPROM8_PA1HIB2, 0xFFFF, 0);
1886 + SPEX(cck2gpo, SSB_SPROM8_CCK2GPO, 0xFFFF, 0);
1887 + SPEX32(ofdm2gpo, SSB_SPROM8_OFDM2GPO, 0xFFFFFFFF, 0);
1888 + SPEX32(ofdm5glpo, SSB_SPROM8_OFDM5GLPO, 0xFFFFFFFF, 0);
1889 + SPEX32(ofdm5gpo, SSB_SPROM8_OFDM5GPO, 0xFFFFFFFF, 0);
1890 + SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, 0xFFFFFFFF, 0);
1891
1892 /* Extract the antenna gain values. */
1893 SPEX(antenna_gain.ghz24.a0, SSB_SPROM8_AGAIN01,
1894 @@ -509,6 +613,63 @@ static void sprom_extract_r8(struct ssb_
1895 memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
1896 sizeof(out->antenna_gain.ghz5));
1897
1898 + /* Extract cores power info info */
1899 + for (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) {
1900 + o = pwr_info_offset[i];
1901 + SPEX(core_pwr_info[i].itssi_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
1902 + SSB_SPROM8_2G_ITSSI, SSB_SPROM8_2G_ITSSI_SHIFT);
1903 + SPEX(core_pwr_info[i].maxpwr_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
1904 + SSB_SPROM8_2G_MAXP, 0);
1905 +
1906 + SPEX(core_pwr_info[i].pa_2g[0], o + SSB_SROM8_2G_PA_0, ~0, 0);
1907 + SPEX(core_pwr_info[i].pa_2g[1], o + SSB_SROM8_2G_PA_1, ~0, 0);
1908 + SPEX(core_pwr_info[i].pa_2g[2], o + SSB_SROM8_2G_PA_2, ~0, 0);
1909 +
1910 + SPEX(core_pwr_info[i].itssi_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
1911 + SSB_SPROM8_5G_ITSSI, SSB_SPROM8_5G_ITSSI_SHIFT);
1912 + SPEX(core_pwr_info[i].maxpwr_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
1913 + SSB_SPROM8_5G_MAXP, 0);
1914 + SPEX(core_pwr_info[i].maxpwr_5gh, o + SSB_SPROM8_5GHL_MAXP,
1915 + SSB_SPROM8_5GH_MAXP, 0);
1916 + SPEX(core_pwr_info[i].maxpwr_5gl, o + SSB_SPROM8_5GHL_MAXP,
1917 + SSB_SPROM8_5GL_MAXP, SSB_SPROM8_5GL_MAXP_SHIFT);
1918 +
1919 + SPEX(core_pwr_info[i].pa_5gl[0], o + SSB_SROM8_5GL_PA_0, ~0, 0);
1920 + SPEX(core_pwr_info[i].pa_5gl[1], o + SSB_SROM8_5GL_PA_1, ~0, 0);
1921 + SPEX(core_pwr_info[i].pa_5gl[2], o + SSB_SROM8_5GL_PA_2, ~0, 0);
1922 + SPEX(core_pwr_info[i].pa_5g[0], o + SSB_SROM8_5G_PA_0, ~0, 0);
1923 + SPEX(core_pwr_info[i].pa_5g[1], o + SSB_SROM8_5G_PA_1, ~0, 0);
1924 + SPEX(core_pwr_info[i].pa_5g[2], o + SSB_SROM8_5G_PA_2, ~0, 0);
1925 + SPEX(core_pwr_info[i].pa_5gh[0], o + SSB_SROM8_5GH_PA_0, ~0, 0);
1926 + SPEX(core_pwr_info[i].pa_5gh[1], o + SSB_SROM8_5GH_PA_1, ~0, 0);
1927 + SPEX(core_pwr_info[i].pa_5gh[2], o + SSB_SROM8_5GH_PA_2, ~0, 0);
1928 + }
1929 +
1930 + /* Extract FEM info */
1931 + SPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G,
1932 + SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
1933 + SPEX(fem.ghz2.extpa_gain, SSB_SPROM8_FEM2G,
1934 + SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
1935 + SPEX(fem.ghz2.pdet_range, SSB_SPROM8_FEM2G,
1936 + SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);
1937 + SPEX(fem.ghz2.tr_iso, SSB_SPROM8_FEM2G,
1938 + SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);
1939 + SPEX(fem.ghz2.antswlut, SSB_SPROM8_FEM2G,
1940 + SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
1941 +
1942 + SPEX(fem.ghz5.tssipos, SSB_SPROM8_FEM5G,
1943 + SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
1944 + SPEX(fem.ghz5.extpa_gain, SSB_SPROM8_FEM5G,
1945 + SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
1946 + SPEX(fem.ghz5.pdet_range, SSB_SPROM8_FEM5G,
1947 + SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);
1948 + SPEX(fem.ghz5.tr_iso, SSB_SPROM8_FEM5G,
1949 + SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);
1950 + SPEX(fem.ghz5.antswlut, SSB_SPROM8_FEM5G,
1951 + SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
1952 +
1953 + sprom_extract_r458(out, in);
1954 +
1955 /* TODO - get remaining rev 8 stuff needed */
1956 }
1957
1958 @@ -521,36 +682,34 @@ static int sprom_extract(struct ssb_bus
1959 ssb_dprintk(KERN_DEBUG PFX "SPROM revision %d detected.\n", out->revision);
1960 memset(out->et0mac, 0xFF, 6); /* preset et0 and et1 mac */
1961 memset(out->et1mac, 0xFF, 6);
1962 +
1963 if ((bus->chip_id & 0xFF00) == 0x4400) {
1964 /* Workaround: The BCM44XX chip has a stupid revision
1965 * number stored in the SPROM.
1966 * Always extract r1. */
1967 out->revision = 1;
1968 + ssb_dprintk(KERN_DEBUG PFX "SPROM treated as revision %d\n", out->revision);
1969 + }
1970 +
1971 + switch (out->revision) {
1972 + case 1:
1973 + case 2:
1974 + case 3:
1975 sprom_extract_r123(out, in);
1976 - } else if (bus->chip_id == 0x4321) {
1977 - /* the BCM4328 has a chipid == 0x4321 and a rev 4 SPROM */
1978 - out->revision = 4;
1979 + break;
1980 + case 4:
1981 + case 5:
1982 sprom_extract_r45(out, in);
1983 - } else {
1984 - switch (out->revision) {
1985 - case 1:
1986 - case 2:
1987 - case 3:
1988 - sprom_extract_r123(out, in);
1989 - break;
1990 - case 4:
1991 - case 5:
1992 - sprom_extract_r45(out, in);
1993 - break;
1994 - case 8:
1995 - sprom_extract_r8(out, in);
1996 - break;
1997 - default:
1998 - ssb_printk(KERN_WARNING PFX "Unsupported SPROM"
1999 - " revision %d detected. Will extract"
2000 - " v1\n", out->revision);
2001 - sprom_extract_r123(out, in);
2002 - }
2003 + break;
2004 + case 8:
2005 + sprom_extract_r8(out, in);
2006 + break;
2007 + default:
2008 + ssb_printk(KERN_WARNING PFX "Unsupported SPROM"
2009 + " revision %d detected. Will extract"
2010 + " v1\n", out->revision);
2011 + out->revision = 1;
2012 + sprom_extract_r123(out, in);
2013 }
2014
2015 if (out->boardflags_lo == 0xFFFF)
2016 @@ -564,13 +723,34 @@ static int sprom_extract(struct ssb_bus
2017 static int ssb_pci_sprom_get(struct ssb_bus *bus,
2018 struct ssb_sprom *sprom)
2019 {
2020 - const struct ssb_sprom *fallback;
2021 - int err = -ENOMEM;
2022 + int err;
2023 u16 *buf;
2024
2025 + if (!ssb_is_sprom_available(bus)) {
2026 + ssb_printk(KERN_ERR PFX "No SPROM available!\n");
2027 + return -ENODEV;
2028 + }
2029 + if (bus->chipco.dev) { /* can be unavailable! */
2030 + /*
2031 + * get SPROM offset: SSB_SPROM_BASE1 except for
2032 + * chipcommon rev >= 31 or chip ID is 0x4312 and
2033 + * chipcommon status & 3 == 2
2034 + */
2035 + if (bus->chipco.dev->id.revision >= 31)
2036 + bus->sprom_offset = SSB_SPROM_BASE31;
2037 + else if (bus->chip_id == 0x4312 &&
2038 + (bus->chipco.status & 0x03) == 2)
2039 + bus->sprom_offset = SSB_SPROM_BASE31;
2040 + else
2041 + bus->sprom_offset = SSB_SPROM_BASE1;
2042 + } else {
2043 + bus->sprom_offset = SSB_SPROM_BASE1;
2044 + }
2045 + ssb_dprintk(KERN_INFO PFX "SPROM offset is 0x%x\n", bus->sprom_offset);
2046 +
2047 buf = kcalloc(SSB_SPROMSIZE_WORDS_R123, sizeof(u16), GFP_KERNEL);
2048 if (!buf)
2049 - goto out;
2050 + return -ENOMEM;
2051 bus->sprom_size = SSB_SPROMSIZE_WORDS_R123;
2052 sprom_do_read(bus, buf);
2053 err = sprom_check_crc(buf, bus->sprom_size);
2054 @@ -580,17 +760,24 @@ static int ssb_pci_sprom_get(struct ssb_
2055 buf = kcalloc(SSB_SPROMSIZE_WORDS_R4, sizeof(u16),
2056 GFP_KERNEL);
2057 if (!buf)
2058 - goto out;
2059 + return -ENOMEM;
2060 bus->sprom_size = SSB_SPROMSIZE_WORDS_R4;
2061 sprom_do_read(bus, buf);
2062 err = sprom_check_crc(buf, bus->sprom_size);
2063 if (err) {
2064 /* All CRC attempts failed.
2065 * Maybe there is no SPROM on the device?
2066 - * If we have a fallback, use that. */
2067 - fallback = ssb_get_fallback_sprom();
2068 - if (fallback) {
2069 - memcpy(sprom, fallback, sizeof(*sprom));
2070 + * Now we ask the arch code if there is some sprom
2071 + * available for this device in some other storage */
2072 + err = ssb_fill_sprom_with_fallback(bus, sprom);
2073 + if (err) {
2074 + ssb_printk(KERN_WARNING PFX "WARNING: Using"
2075 + " fallback SPROM failed (err %d)\n",
2076 + err);
2077 + } else {
2078 + ssb_dprintk(KERN_DEBUG PFX "Using SPROM"
2079 + " revision %d provided by"
2080 + " platform.\n", sprom->revision);
2081 err = 0;
2082 goto out_free;
2083 }
2084 @@ -602,19 +789,15 @@ static int ssb_pci_sprom_get(struct ssb_
2085
2086 out_free:
2087 kfree(buf);
2088 -out:
2089 return err;
2090 }
2091
2092 static void ssb_pci_get_boardinfo(struct ssb_bus *bus,
2093 struct ssb_boardinfo *bi)
2094 {
2095 - pci_read_config_word(bus->host_pci, PCI_SUBSYSTEM_VENDOR_ID,
2096 - &bi->vendor);
2097 - pci_read_config_word(bus->host_pci, PCI_SUBSYSTEM_ID,
2098 - &bi->type);
2099 - pci_read_config_word(bus->host_pci, PCI_REVISION_ID,
2100 - &bi->rev);
2101 + bi->vendor = bus->host_pci->subsystem_vendor;
2102 + bi->type = bus->host_pci->subsystem_device;
2103 + bi->rev = bus->host_pci->revision;
2104 }
2105
2106 int ssb_pci_get_invariants(struct ssb_bus *bus,
2107 --- a/drivers/ssb/pcihost_wrapper.c
2108 +++ b/drivers/ssb/pcihost_wrapper.c
2109 @@ -6,12 +6,13 @@
2110 * Copyright (c) 2005 Stefano Brivio <st3@riseup.net>
2111 * Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
2112 * Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
2113 - * Copyright (c) 2005-2007 Michael Buesch <mbuesch@freenet.de>
2114 + * Copyright (c) 2005-2007 Michael Buesch <m@bues.ch>
2115 *
2116 * Licensed under the GNU/GPL. See COPYING for details.
2117 */
2118
2119 #include <linux/pci.h>
2120 +#include <linux/slab.h>
2121 #include <linux/ssb/ssb.h>
2122
2123
2124 @@ -52,12 +53,13 @@ static int ssb_pcihost_resume(struct pci
2125 # define ssb_pcihost_resume NULL
2126 #endif /* CONFIG_PM */
2127
2128 -static int ssb_pcihost_probe(struct pci_dev *dev,
2129 - const struct pci_device_id *id)
2130 +static int __devinit ssb_pcihost_probe(struct pci_dev *dev,
2131 + const struct pci_device_id *id)
2132 {
2133 struct ssb_bus *ssb;
2134 int err = -ENOMEM;
2135 const char *name;
2136 + u32 val;
2137
2138 ssb = kzalloc(sizeof(*ssb), GFP_KERNEL);
2139 if (!ssb)
2140 @@ -73,6 +75,12 @@ static int ssb_pcihost_probe(struct pci_
2141 goto err_pci_disable;
2142 pci_set_master(dev);
2143
2144 + /* Disable the RETRY_TIMEOUT register (0x41) to keep
2145 + * PCI Tx retries from interfering with C3 CPU state */
2146 + pci_read_config_dword(dev, 0x40, &val);
2147 + if ((val & 0x0000ff00) != 0)
2148 + pci_write_config_dword(dev, 0x40, val & 0xffff00ff);
2149 +
2150 err = ssb_bus_pcibus_register(ssb, dev);
2151 if (err)
2152 goto err_pci_release_regions;
2153 @@ -102,7 +110,7 @@ static void ssb_pcihost_remove(struct pc
2154 pci_set_drvdata(dev, NULL);
2155 }
2156
2157 -int ssb_pcihost_register(struct pci_driver *driver)
2158 +int __devinit ssb_pcihost_register(struct pci_driver *driver)
2159 {
2160 driver->probe = ssb_pcihost_probe;
2161 driver->remove = ssb_pcihost_remove;
2162 --- a/drivers/ssb/pcmcia.c
2163 +++ b/drivers/ssb/pcmcia.c
2164 @@ -3,7 +3,7 @@
2165 * PCMCIA-Hostbus related functions
2166 *
2167 * Copyright 2006 Johannes Berg <johannes@sipsolutions.net>
2168 - * Copyright 2007-2008 Michael Buesch <mb@bu3sch.de>
2169 + * Copyright 2007-2008 Michael Buesch <m@bues.ch>
2170 *
2171 * Licensed under the GNU/GPL. See COPYING for details.
2172 */
2173 @@ -583,7 +583,7 @@ static int ssb_pcmcia_sprom_write_all(st
2174 ssb_printk(".");
2175 err = ssb_pcmcia_sprom_write(bus, i, sprom[i]);
2176 if (err) {
2177 - ssb_printk("\n" KERN_NOTICE PFX
2178 + ssb_printk(KERN_NOTICE PFX
2179 "Failed to write to SPROM.\n");
2180 failed = 1;
2181 break;
2182 @@ -591,7 +591,7 @@ static int ssb_pcmcia_sprom_write_all(st
2183 }
2184 err = ssb_pcmcia_sprom_command(bus, SSB_PCMCIA_SPROMCTL_WRITEDIS);
2185 if (err) {
2186 - ssb_printk("\n" KERN_NOTICE PFX
2187 + ssb_printk(KERN_NOTICE PFX
2188 "Could not disable SPROM write access.\n");
2189 failed = 1;
2190 }
2191 @@ -617,134 +617,140 @@ static int ssb_pcmcia_sprom_check_crc(co
2192 } \
2193 } while (0)
2194
2195 -int ssb_pcmcia_get_invariants(struct ssb_bus *bus,
2196 - struct ssb_init_invariants *iv)
2197 +static int ssb_pcmcia_get_mac(struct pcmcia_device *p_dev,
2198 + tuple_t *tuple,
2199 + void *priv)
2200 +{
2201 + struct ssb_sprom *sprom = priv;
2202 +
2203 + if (tuple->TupleData[0] != CISTPL_FUNCE_LAN_NODE_ID)
2204 + return -EINVAL;
2205 + if (tuple->TupleDataLen != ETH_ALEN + 2)
2206 + return -EINVAL;
2207 + if (tuple->TupleData[1] != ETH_ALEN)
2208 + return -EINVAL;
2209 + memcpy(sprom->il0mac, &tuple->TupleData[2], ETH_ALEN);
2210 + return 0;
2211 +};
2212 +
2213 +static int ssb_pcmcia_do_get_invariants(struct pcmcia_device *p_dev,
2214 + tuple_t *tuple,
2215 + void *priv)
2216 {
2217 - tuple_t tuple;
2218 - int res;
2219 - unsigned char buf[32];
2220 + struct ssb_init_invariants *iv = priv;
2221 struct ssb_sprom *sprom = &iv->sprom;
2222 struct ssb_boardinfo *bi = &iv->boardinfo;
2223 const char *error_description;
2224
2225 + GOTO_ERROR_ON(tuple->TupleDataLen < 1, "VEN tpl < 1");
2226 + switch (tuple->TupleData[0]) {
2227 + case SSB_PCMCIA_CIS_ID:
2228 + GOTO_ERROR_ON((tuple->TupleDataLen != 5) &&
2229 + (tuple->TupleDataLen != 7),
2230 + "id tpl size");
2231 + bi->vendor = tuple->TupleData[1] |
2232 + ((u16)tuple->TupleData[2] << 8);
2233 + break;
2234 + case SSB_PCMCIA_CIS_BOARDREV:
2235 + GOTO_ERROR_ON(tuple->TupleDataLen != 2,
2236 + "boardrev tpl size");
2237 + sprom->board_rev = tuple->TupleData[1];
2238 + break;
2239 + case SSB_PCMCIA_CIS_PA:
2240 + GOTO_ERROR_ON((tuple->TupleDataLen != 9) &&
2241 + (tuple->TupleDataLen != 10),
2242 + "pa tpl size");
2243 + sprom->pa0b0 = tuple->TupleData[1] |
2244 + ((u16)tuple->TupleData[2] << 8);
2245 + sprom->pa0b1 = tuple->TupleData[3] |
2246 + ((u16)tuple->TupleData[4] << 8);
2247 + sprom->pa0b2 = tuple->TupleData[5] |
2248 + ((u16)tuple->TupleData[6] << 8);
2249 + sprom->itssi_a = tuple->TupleData[7];
2250 + sprom->itssi_bg = tuple->TupleData[7];
2251 + sprom->maxpwr_a = tuple->TupleData[8];
2252 + sprom->maxpwr_bg = tuple->TupleData[8];
2253 + break;
2254 + case SSB_PCMCIA_CIS_OEMNAME:
2255 + /* We ignore this. */
2256 + break;
2257 + case SSB_PCMCIA_CIS_CCODE:
2258 + GOTO_ERROR_ON(tuple->TupleDataLen != 2,
2259 + "ccode tpl size");
2260 + sprom->country_code = tuple->TupleData[1];
2261 + break;
2262 + case SSB_PCMCIA_CIS_ANTENNA:
2263 + GOTO_ERROR_ON(tuple->TupleDataLen != 2,
2264 + "ant tpl size");
2265 + sprom->ant_available_a = tuple->TupleData[1];
2266 + sprom->ant_available_bg = tuple->TupleData[1];
2267 + break;
2268 + case SSB_PCMCIA_CIS_ANTGAIN:
2269 + GOTO_ERROR_ON(tuple->TupleDataLen != 2,
2270 + "antg tpl size");
2271 + sprom->antenna_gain.ghz24.a0 = tuple->TupleData[1];
2272 + sprom->antenna_gain.ghz24.a1 = tuple->TupleData[1];
2273 + sprom->antenna_gain.ghz24.a2 = tuple->TupleData[1];
2274 + sprom->antenna_gain.ghz24.a3 = tuple->TupleData[1];
2275 + sprom->antenna_gain.ghz5.a0 = tuple->TupleData[1];
2276 + sprom->antenna_gain.ghz5.a1 = tuple->TupleData[1];
2277 + sprom->antenna_gain.ghz5.a2 = tuple->TupleData[1];
2278 + sprom->antenna_gain.ghz5.a3 = tuple->TupleData[1];
2279 + break;
2280 + case SSB_PCMCIA_CIS_BFLAGS:
2281 + GOTO_ERROR_ON((tuple->TupleDataLen != 3) &&
2282 + (tuple->TupleDataLen != 5),
2283 + "bfl tpl size");
2284 + sprom->boardflags_lo = tuple->TupleData[1] |
2285 + ((u16)tuple->TupleData[2] << 8);
2286 + break;
2287 + case SSB_PCMCIA_CIS_LEDS:
2288 + GOTO_ERROR_ON(tuple->TupleDataLen != 5,
2289 + "leds tpl size");
2290 + sprom->gpio0 = tuple->TupleData[1];
2291 + sprom->gpio1 = tuple->TupleData[2];
2292 + sprom->gpio2 = tuple->TupleData[3];
2293 + sprom->gpio3 = tuple->TupleData[4];
2294 + break;
2295 + }
2296 + return -ENOSPC; /* continue with next entry */
2297 +
2298 +error:
2299 + ssb_printk(KERN_ERR PFX
2300 + "PCMCIA: Failed to fetch device invariants: %s\n",
2301 + error_description);
2302 + return -ENODEV;
2303 +}
2304 +
2305 +
2306 +int ssb_pcmcia_get_invariants(struct ssb_bus *bus,
2307 + struct ssb_init_invariants *iv)
2308 +{
2309 + struct ssb_sprom *sprom = &iv->sprom;
2310 + int res;
2311 +
2312 memset(sprom, 0xFF, sizeof(*sprom));
2313 sprom->revision = 1;
2314 sprom->boardflags_lo = 0;
2315 sprom->boardflags_hi = 0;
2316
2317 /* First fetch the MAC address. */
2318 - memset(&tuple, 0, sizeof(tuple));
2319 - tuple.DesiredTuple = CISTPL_FUNCE;
2320 - tuple.TupleData = buf;
2321 - tuple.TupleDataMax = sizeof(buf);
2322 - res = pcmcia_get_first_tuple(bus->host_pcmcia, &tuple);
2323 - GOTO_ERROR_ON(res != 0, "MAC first tpl");
2324 - res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple);
2325 - GOTO_ERROR_ON(res != 0, "MAC first tpl data");
2326 - while (1) {
2327 - GOTO_ERROR_ON(tuple.TupleDataLen < 1, "MAC tpl < 1");
2328 - if (tuple.TupleData[0] == CISTPL_FUNCE_LAN_NODE_ID)
2329 - break;
2330 - res = pcmcia_get_next_tuple(bus->host_pcmcia, &tuple);
2331 - GOTO_ERROR_ON(res != 0, "MAC next tpl");
2332 - res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple);
2333 - GOTO_ERROR_ON(res != 0, "MAC next tpl data");
2334 + res = pcmcia_loop_tuple(bus->host_pcmcia, CISTPL_FUNCE,
2335 + ssb_pcmcia_get_mac, sprom);
2336 + if (res != 0) {
2337 + ssb_printk(KERN_ERR PFX
2338 + "PCMCIA: Failed to fetch MAC address\n");
2339 + return -ENODEV;
2340 }
2341 - GOTO_ERROR_ON(tuple.TupleDataLen != ETH_ALEN + 2, "MAC tpl size");
2342 - memcpy(sprom->il0mac, &tuple.TupleData[2], ETH_ALEN);
2343
2344 /* Fetch the vendor specific tuples. */
2345 - memset(&tuple, 0, sizeof(tuple));
2346 - tuple.DesiredTuple = SSB_PCMCIA_CIS;
2347 - tuple.TupleData = buf;
2348 - tuple.TupleDataMax = sizeof(buf);
2349 - res = pcmcia_get_first_tuple(bus->host_pcmcia, &tuple);
2350 - GOTO_ERROR_ON(res != 0, "VEN first tpl");
2351 - res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple);
2352 - GOTO_ERROR_ON(res != 0, "VEN first tpl data");
2353 - while (1) {
2354 - GOTO_ERROR_ON(tuple.TupleDataLen < 1, "VEN tpl < 1");
2355 - switch (tuple.TupleData[0]) {
2356 - case SSB_PCMCIA_CIS_ID:
2357 - GOTO_ERROR_ON((tuple.TupleDataLen != 5) &&
2358 - (tuple.TupleDataLen != 7),
2359 - "id tpl size");
2360 - bi->vendor = tuple.TupleData[1] |
2361 - ((u16)tuple.TupleData[2] << 8);
2362 - break;
2363 - case SSB_PCMCIA_CIS_BOARDREV:
2364 - GOTO_ERROR_ON(tuple.TupleDataLen != 2,
2365 - "boardrev tpl size");
2366 - sprom->board_rev = tuple.TupleData[1];
2367 - break;
2368 - case SSB_PCMCIA_CIS_PA:
2369 - GOTO_ERROR_ON(tuple.TupleDataLen != 9,
2370 - "pa tpl size");
2371 - sprom->pa0b0 = tuple.TupleData[1] |
2372 - ((u16)tuple.TupleData[2] << 8);
2373 - sprom->pa0b1 = tuple.TupleData[3] |
2374 - ((u16)tuple.TupleData[4] << 8);
2375 - sprom->pa0b2 = tuple.TupleData[5] |
2376 - ((u16)tuple.TupleData[6] << 8);
2377 - sprom->itssi_a = tuple.TupleData[7];
2378 - sprom->itssi_bg = tuple.TupleData[7];
2379 - sprom->maxpwr_a = tuple.TupleData[8];
2380 - sprom->maxpwr_bg = tuple.TupleData[8];
2381 - break;
2382 - case SSB_PCMCIA_CIS_OEMNAME:
2383 - /* We ignore this. */
2384 - break;
2385 - case SSB_PCMCIA_CIS_CCODE:
2386 - GOTO_ERROR_ON(tuple.TupleDataLen != 2,
2387 - "ccode tpl size");
2388 - sprom->country_code = tuple.TupleData[1];
2389 - break;
2390 - case SSB_PCMCIA_CIS_ANTENNA:
2391 - GOTO_ERROR_ON(tuple.TupleDataLen != 2,
2392 - "ant tpl size");
2393 - sprom->ant_available_a = tuple.TupleData[1];
2394 - sprom->ant_available_bg = tuple.TupleData[1];
2395 - break;
2396 - case SSB_PCMCIA_CIS_ANTGAIN:
2397 - GOTO_ERROR_ON(tuple.TupleDataLen != 2,
2398 - "antg tpl size");
2399 - sprom->antenna_gain.ghz24.a0 = tuple.TupleData[1];
2400 - sprom->antenna_gain.ghz24.a1 = tuple.TupleData[1];
2401 - sprom->antenna_gain.ghz24.a2 = tuple.TupleData[1];
2402 - sprom->antenna_gain.ghz24.a3 = tuple.TupleData[1];
2403 - sprom->antenna_gain.ghz5.a0 = tuple.TupleData[1];
2404 - sprom->antenna_gain.ghz5.a1 = tuple.TupleData[1];
2405 - sprom->antenna_gain.ghz5.a2 = tuple.TupleData[1];
2406 - sprom->antenna_gain.ghz5.a3 = tuple.TupleData[1];
2407 - break;
2408 - case SSB_PCMCIA_CIS_BFLAGS:
2409 - GOTO_ERROR_ON(tuple.TupleDataLen != 3,
2410 - "bfl tpl size");
2411 - sprom->boardflags_lo = tuple.TupleData[1] |
2412 - ((u16)tuple.TupleData[2] << 8);
2413 - break;
2414 - case SSB_PCMCIA_CIS_LEDS:
2415 - GOTO_ERROR_ON(tuple.TupleDataLen != 5,
2416 - "leds tpl size");
2417 - sprom->gpio0 = tuple.TupleData[1];
2418 - sprom->gpio1 = tuple.TupleData[2];
2419 - sprom->gpio2 = tuple.TupleData[3];
2420 - sprom->gpio3 = tuple.TupleData[4];
2421 - break;
2422 - }
2423 - res = pcmcia_get_next_tuple(bus->host_pcmcia, &tuple);
2424 - if (res == -ENOSPC)
2425 - break;
2426 - GOTO_ERROR_ON(res != 0, "VEN next tpl");
2427 - res = pcmcia_get_tuple_data(bus->host_pcmcia, &tuple);
2428 - GOTO_ERROR_ON(res != 0, "VEN next tpl data");
2429 - }
2430 + res = pcmcia_loop_tuple(bus->host_pcmcia, SSB_PCMCIA_CIS,
2431 + ssb_pcmcia_do_get_invariants, iv);
2432 + if ((res == 0) || (res == -ENOSPC))
2433 + return 0;
2434
2435 - return 0;
2436 -error:
2437 ssb_printk(KERN_ERR PFX
2438 - "PCMCIA: Failed to fetch device invariants: %s\n",
2439 - error_description);
2440 + "PCMCIA: Failed to fetch device invariants\n");
2441 return -ENODEV;
2442 }
2443
2444 --- a/drivers/ssb/scan.c
2445 +++ b/drivers/ssb/scan.c
2446 @@ -2,7 +2,7 @@
2447 * Sonics Silicon Backplane
2448 * Bus scanning
2449 *
2450 - * Copyright (C) 2005-2007 Michael Buesch <mb@bu3sch.de>
2451 + * Copyright (C) 2005-2007 Michael Buesch <m@bues.ch>
2452 * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
2453 * Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
2454 * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
2455 @@ -162,6 +162,8 @@ static u8 chipid_to_nrcores(u16 chipid)
2456 static u32 scan_read32(struct ssb_bus *bus, u8 current_coreidx,
2457 u16 offset)
2458 {
2459 + u32 lo, hi;
2460 +
2461 switch (bus->bustype) {
2462 case SSB_BUSTYPE_SSB:
2463 offset += current_coreidx * SSB_CORE_SIZE;
2464 @@ -174,7 +176,12 @@ static u32 scan_read32(struct ssb_bus *b
2465 offset -= 0x800;
2466 } else
2467 ssb_pcmcia_switch_segment(bus, 0);
2468 - break;
2469 + lo = readw(bus->mmio + offset);
2470 + hi = readw(bus->mmio + offset + 2);
2471 + return lo | (hi << 16);
2472 + case SSB_BUSTYPE_SDIO:
2473 + offset += current_coreidx * SSB_CORE_SIZE;
2474 + return ssb_sdio_scan_read32(bus, offset);
2475 }
2476 return readl(bus->mmio + offset);
2477 }
2478 @@ -188,6 +195,8 @@ static int scan_switchcore(struct ssb_bu
2479 return ssb_pci_switch_coreidx(bus, coreidx);
2480 case SSB_BUSTYPE_PCMCIA:
2481 return ssb_pcmcia_switch_coreidx(bus, coreidx);
2482 + case SSB_BUSTYPE_SDIO:
2483 + return ssb_sdio_scan_switch_coreidx(bus, coreidx);
2484 }
2485 return 0;
2486 }
2487 @@ -206,6 +215,8 @@ void ssb_iounmap(struct ssb_bus *bus)
2488 SSB_BUG_ON(1); /* Can't reach this code. */
2489 #endif
2490 break;
2491 + case SSB_BUSTYPE_SDIO:
2492 + break;
2493 }
2494 bus->mmio = NULL;
2495 bus->mapped_device = NULL;
2496 @@ -230,6 +241,10 @@ static void __iomem *ssb_ioremap(struct
2497 SSB_BUG_ON(1); /* Can't reach this code. */
2498 #endif
2499 break;
2500 + case SSB_BUSTYPE_SDIO:
2501 + /* Nothing to ioremap in the SDIO case, just fake it */
2502 + mmio = (void __iomem *)baseaddr;
2503 + break;
2504 }
2505
2506 return mmio;
2507 @@ -245,7 +260,10 @@ static int we_support_multiple_80211_cor
2508 #ifdef CONFIG_SSB_PCIHOST
2509 if (bus->bustype == SSB_BUSTYPE_PCI) {
2510 if (bus->host_pci->vendor == PCI_VENDOR_ID_BROADCOM &&
2511 - bus->host_pci->device == 0x4324)
2512 + ((bus->host_pci->device == 0x4313) ||
2513 + (bus->host_pci->device == 0x431A) ||
2514 + (bus->host_pci->device == 0x4321) ||
2515 + (bus->host_pci->device == 0x4324)))
2516 return 1;
2517 }
2518 #endif /* CONFIG_SSB_PCIHOST */
2519 @@ -294,8 +312,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
2520 } else {
2521 if (bus->bustype == SSB_BUSTYPE_PCI) {
2522 bus->chip_id = pcidev_to_chipid(bus->host_pci);
2523 - pci_read_config_word(bus->host_pci, PCI_REVISION_ID,
2524 - &bus->chip_rev);
2525 + bus->chip_rev = bus->host_pci->revision;
2526 bus->chip_package = 0;
2527 } else {
2528 bus->chip_id = 0x4710;
2529 @@ -339,7 +356,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
2530 dev->bus = bus;
2531 dev->ops = bus->ops;
2532
2533 - ssb_dprintk(KERN_INFO PFX
2534 + printk(KERN_DEBUG PFX
2535 "Core %d found: %s "
2536 "(cc 0x%03X, rev 0x%02X, vendor 0x%04X)\n",
2537 i, ssb_core_name(dev->id.coreid),
2538 @@ -407,6 +424,16 @@ int ssb_bus_scan(struct ssb_bus *bus,
2539 bus->pcicore.dev = dev;
2540 #endif /* CONFIG_SSB_DRIVER_PCICORE */
2541 break;
2542 + case SSB_DEV_ETHERNET:
2543 + if (bus->bustype == SSB_BUSTYPE_PCI) {
2544 + if (bus->host_pci->vendor == PCI_VENDOR_ID_BROADCOM &&
2545 + (bus->host_pci->device & 0xFF00) == 0x4300) {
2546 + /* This is a dangling ethernet core on a
2547 + * wireless device. Ignore it. */
2548 + continue;
2549 + }
2550 + }
2551 + break;
2552 default:
2553 break;
2554 }
2555 --- /dev/null
2556 +++ b/drivers/ssb/sdio.c
2557 @@ -0,0 +1,610 @@
2558 +/*
2559 + * Sonics Silicon Backplane
2560 + * SDIO-Hostbus related functions
2561 + *
2562 + * Copyright 2009 Albert Herranz <albert_herranz@yahoo.es>
2563 + *
2564 + * Based on drivers/ssb/pcmcia.c
2565 + * Copyright 2006 Johannes Berg <johannes@sipsolutions.net>
2566 + * Copyright 2007-2008 Michael Buesch <m@bues.ch>
2567 + *
2568 + * Licensed under the GNU/GPL. See COPYING for details.
2569 + *
2570 + */
2571 +
2572 +#include <linux/ssb/ssb.h>
2573 +#include <linux/delay.h>
2574 +#include <linux/io.h>
2575 +#include <linux/etherdevice.h>
2576 +#include <linux/mmc/sdio_func.h>
2577 +
2578 +#include "ssb_private.h"
2579 +
2580 +/* Define the following to 1 to enable a printk on each coreswitch. */
2581 +#define SSB_VERBOSE_SDIOCORESWITCH_DEBUG 0
2582 +
2583 +
2584 +/* Hardware invariants CIS tuples */
2585 +#define SSB_SDIO_CIS 0x80
2586 +#define SSB_SDIO_CIS_SROMREV 0x00
2587 +#define SSB_SDIO_CIS_ID 0x01
2588 +#define SSB_SDIO_CIS_BOARDREV 0x02
2589 +#define SSB_SDIO_CIS_PA 0x03
2590 +#define SSB_SDIO_CIS_PA_PA0B0_LO 0
2591 +#define SSB_SDIO_CIS_PA_PA0B0_HI 1
2592 +#define SSB_SDIO_CIS_PA_PA0B1_LO 2
2593 +#define SSB_SDIO_CIS_PA_PA0B1_HI 3
2594 +#define SSB_SDIO_CIS_PA_PA0B2_LO 4
2595 +#define SSB_SDIO_CIS_PA_PA0B2_HI 5
2596 +#define SSB_SDIO_CIS_PA_ITSSI 6
2597 +#define SSB_SDIO_CIS_PA_MAXPOW 7
2598 +#define SSB_SDIO_CIS_OEMNAME 0x04
2599 +#define SSB_SDIO_CIS_CCODE 0x05
2600 +#define SSB_SDIO_CIS_ANTENNA 0x06
2601 +#define SSB_SDIO_CIS_ANTGAIN 0x07
2602 +#define SSB_SDIO_CIS_BFLAGS 0x08
2603 +#define SSB_SDIO_CIS_LEDS 0x09
2604 +
2605 +#define CISTPL_FUNCE_LAN_NODE_ID 0x04 /* same as in PCMCIA */
2606 +
2607 +
2608 +/*
2609 + * Function 1 miscellaneous registers.
2610 + *
2611 + * Definitions match src/include/sbsdio.h from the
2612 + * Android Open Source Project
2613 + * http://android.git.kernel.org/?p=platform/system/wlan/broadcom.git
2614 + *
2615 + */
2616 +#define SBSDIO_FUNC1_SBADDRLOW 0x1000a /* SB Address window Low (b15) */
2617 +#define SBSDIO_FUNC1_SBADDRMID 0x1000b /* SB Address window Mid (b23-b16) */
2618 +#define SBSDIO_FUNC1_SBADDRHIGH 0x1000c /* SB Address window High (b24-b31) */
2619 +
2620 +/* valid bits in SBSDIO_FUNC1_SBADDRxxx regs */
2621 +#define SBSDIO_SBADDRLOW_MASK 0x80 /* Valid address bits in SBADDRLOW */
2622 +#define SBSDIO_SBADDRMID_MASK 0xff /* Valid address bits in SBADDRMID */
2623 +#define SBSDIO_SBADDRHIGH_MASK 0xff /* Valid address bits in SBADDRHIGH */
2624 +
2625 +#define SBSDIO_SB_OFT_ADDR_MASK 0x7FFF /* sb offset addr is <= 15 bits, 32k */
2626 +
2627 +/* REVISIT: this flag doesn't seem to matter */
2628 +#define SBSDIO_SB_ACCESS_2_4B_FLAG 0x8000 /* forces 32-bit SB access */
2629 +
2630 +
2631 +/*
2632 + * Address map within the SDIO function address space (128K).
2633 + *
2634 + * Start End Description
2635 + * ------- ------- ------------------------------------------
2636 + * 0x00000 0x0ffff selected backplane address window (64K)
2637 + * 0x10000 0x1ffff backplane control registers (max 64K)
2638 + *
2639 + * The current address window is configured by writing to registers
2640 + * SBADDRLOW, SBADDRMID and SBADDRHIGH.
2641 + *
2642 + * In order to access the contents of a 32-bit Silicon Backplane address
2643 + * the backplane address window must be first loaded with the highest
2644 + * 16 bits of the target address. Then, an access must be done to the
2645 + * SDIO function address space using the lower 15 bits of the address.
2646 + * Bit 15 of the address must be set when doing 32 bit accesses.
2647 + *
2648 + * 10987654321098765432109876543210
2649 + * WWWWWWWWWWWWWWWWW SB Address Window
2650 + * OOOOOOOOOOOOOOOO Offset within SB Address Window
2651 + * a 32-bit access flag
2652 + */
2653 +
2654 +
2655 +/*
2656 + * SSB I/O via SDIO.
2657 + *
2658 + * NOTE: SDIO address @addr is 17 bits long (SDIO address space is 128K).
2659 + */
2660 +
2661 +static inline struct device *ssb_sdio_dev(struct ssb_bus *bus)
2662 +{
2663 + return &bus->host_sdio->dev;
2664 +}
2665 +
2666 +/* host claimed */
2667 +static int ssb_sdio_writeb(struct ssb_bus *bus, unsigned int addr, u8 val)
2668 +{
2669 + int error = 0;
2670 +
2671 + sdio_writeb(bus->host_sdio, val, addr, &error);
2672 + if (unlikely(error)) {
2673 + dev_dbg(ssb_sdio_dev(bus), "%08X <- %02x, error %d\n",
2674 + addr, val, error);
2675 + }
2676 +
2677 + return error;
2678 +}
2679 +
2680 +#if 0
2681 +static u8 ssb_sdio_readb(struct ssb_bus *bus, unsigned int addr)
2682 +{
2683 + u8 val;
2684 + int error = 0;
2685 +
2686 + val = sdio_readb(bus->host_sdio, addr, &error);
2687 + if (unlikely(error)) {
2688 + dev_dbg(ssb_sdio_dev(bus), "%08X -> %02x, error %d\n",
2689 + addr, val, error);
2690 + }
2691 +
2692 + return val;
2693 +}
2694 +#endif
2695 +
2696 +/* host claimed */
2697 +static int ssb_sdio_set_sbaddr_window(struct ssb_bus *bus, u32 address)
2698 +{
2699 + int error;
2700 +
2701 + error = ssb_sdio_writeb(bus, SBSDIO_FUNC1_SBADDRLOW,
2702 + (address >> 8) & SBSDIO_SBADDRLOW_MASK);
2703 + if (error)
2704 + goto out;
2705 + error = ssb_sdio_writeb(bus, SBSDIO_FUNC1_SBADDRMID,
2706 + (address >> 16) & SBSDIO_SBADDRMID_MASK);
2707 + if (error)
2708 + goto out;
2709 + error = ssb_sdio_writeb(bus, SBSDIO_FUNC1_SBADDRHIGH,
2710 + (address >> 24) & SBSDIO_SBADDRHIGH_MASK);
2711 + if (error)
2712 + goto out;
2713 + bus->sdio_sbaddr = address;
2714 +out:
2715 + if (error) {
2716 + dev_dbg(ssb_sdio_dev(bus), "failed to set address window"
2717 + " to 0x%08x, error %d\n", address, error);
2718 + }
2719 +
2720 + return error;
2721 +}
2722 +
2723 +/* for enumeration use only */
2724 +u32 ssb_sdio_scan_read32(struct ssb_bus *bus, u16 offset)
2725 +{
2726 + u32 val;
2727 + int error;
2728 +
2729 + sdio_claim_host(bus->host_sdio);
2730 + val = sdio_readl(bus->host_sdio, offset, &error);
2731 + sdio_release_host(bus->host_sdio);
2732 + if (unlikely(error)) {
2733 + dev_dbg(ssb_sdio_dev(bus), "%04X:%04X > %08x, error %d\n",
2734 + bus->sdio_sbaddr >> 16, offset, val, error);
2735 + }
2736 +
2737 + return val;
2738 +}
2739 +
2740 +/* for enumeration use only */
2741 +int ssb_sdio_scan_switch_coreidx(struct ssb_bus *bus, u8 coreidx)
2742 +{
2743 + u32 sbaddr;
2744 + int error;
2745 +
2746 + sbaddr = (coreidx * SSB_CORE_SIZE) + SSB_ENUM_BASE;
2747 + sdio_claim_host(bus->host_sdio);
2748 + error = ssb_sdio_set_sbaddr_window(bus, sbaddr);
2749 + sdio_release_host(bus->host_sdio);
2750 + if (error) {
2751 + dev_err(ssb_sdio_dev(bus), "failed to switch to core %u,"
2752 + " error %d\n", coreidx, error);
2753 + goto out;
2754 + }
2755 +out:
2756 + return error;
2757 +}
2758 +
2759 +/* host must be already claimed */
2760 +int ssb_sdio_switch_core(struct ssb_bus *bus, struct ssb_device *dev)
2761 +{
2762 + u8 coreidx = dev->core_index;
2763 + u32 sbaddr;
2764 + int error = 0;
2765 +
2766 + sbaddr = (coreidx * SSB_CORE_SIZE) + SSB_ENUM_BASE;
2767 + if (unlikely(bus->sdio_sbaddr != sbaddr)) {
2768 +#if SSB_VERBOSE_SDIOCORESWITCH_DEBUG
2769 + dev_info(ssb_sdio_dev(bus),
2770 + "switching to %s core, index %d\n",
2771 + ssb_core_name(dev->id.coreid), coreidx);
2772 +#endif
2773 + error = ssb_sdio_set_sbaddr_window(bus, sbaddr);
2774 + if (error) {
2775 + dev_dbg(ssb_sdio_dev(bus), "failed to switch to"
2776 + " core %u, error %d\n", coreidx, error);
2777 + goto out;
2778 + }
2779 + bus->mapped_device = dev;
2780 + }
2781 +
2782 +out:
2783 + return error;
2784 +}
2785 +
2786 +static u8 ssb_sdio_read8(struct ssb_device *dev, u16 offset)
2787 +{
2788 + struct ssb_bus *bus = dev->bus;
2789 + u8 val = 0xff;
2790 + int error = 0;
2791 +
2792 + sdio_claim_host(bus->host_sdio);
2793 + if (unlikely(ssb_sdio_switch_core(bus, dev)))
2794 + goto out;
2795 + offset |= bus->sdio_sbaddr & 0xffff;
2796 + offset &= SBSDIO_SB_OFT_ADDR_MASK;
2797 + val = sdio_readb(bus->host_sdio, offset, &error);
2798 + if (error) {
2799 + dev_dbg(ssb_sdio_dev(bus), "%04X:%04X > %02x, error %d\n",
2800 + bus->sdio_sbaddr >> 16, offset, val, error);
2801 + }
2802 +out:
2803 + sdio_release_host(bus->host_sdio);
2804 +
2805 + return val;
2806 +}
2807 +
2808 +static u16 ssb_sdio_read16(struct ssb_device *dev, u16 offset)
2809 +{
2810 + struct ssb_bus *bus = dev->bus;
2811 + u16 val = 0xffff;
2812 + int error = 0;
2813 +
2814 + sdio_claim_host(bus->host_sdio);
2815 + if (unlikely(ssb_sdio_switch_core(bus, dev)))
2816 + goto out;
2817 + offset |= bus->sdio_sbaddr & 0xffff;
2818 + offset &= SBSDIO_SB_OFT_ADDR_MASK;
2819 + val = sdio_readw(bus->host_sdio, offset, &error);
2820 + if (error) {
2821 + dev_dbg(ssb_sdio_dev(bus), "%04X:%04X > %04x, error %d\n",
2822 + bus->sdio_sbaddr >> 16, offset, val, error);
2823 + }
2824 +out:
2825 + sdio_release_host(bus->host_sdio);
2826 +
2827 + return val;
2828 +}
2829 +
2830 +static u32 ssb_sdio_read32(struct ssb_device *dev, u16 offset)
2831 +{
2832 + struct ssb_bus *bus = dev->bus;
2833 + u32 val = 0xffffffff;
2834 + int error = 0;
2835 +
2836 + sdio_claim_host(bus->host_sdio);
2837 + if (unlikely(ssb_sdio_switch_core(bus, dev)))
2838 + goto out;
2839 + offset |= bus->sdio_sbaddr & 0xffff;
2840 + offset &= SBSDIO_SB_OFT_ADDR_MASK;
2841 + offset |= SBSDIO_SB_ACCESS_2_4B_FLAG; /* 32 bit data access */
2842 + val = sdio_readl(bus->host_sdio, offset, &error);
2843 + if (error) {
2844 + dev_dbg(ssb_sdio_dev(bus), "%04X:%04X > %08x, error %d\n",
2845 + bus->sdio_sbaddr >> 16, offset, val, error);
2846 + }
2847 +out:
2848 + sdio_release_host(bus->host_sdio);
2849 +
2850 + return val;
2851 +}
2852 +
2853 +#ifdef CONFIG_SSB_BLOCKIO
2854 +static void ssb_sdio_block_read(struct ssb_device *dev, void *buffer,
2855 + size_t count, u16 offset, u8 reg_width)
2856 +{
2857 + size_t saved_count = count;
2858 + struct ssb_bus *bus = dev->bus;
2859 + int error = 0;
2860 +
2861 + sdio_claim_host(bus->host_sdio);
2862 + if (unlikely(ssb_sdio_switch_core(bus, dev))) {
2863 + error = -EIO;
2864 + memset(buffer, 0xff, count);
2865 + goto err_out;
2866 + }
2867 + offset |= bus->sdio_sbaddr & 0xffff;
2868 + offset &= SBSDIO_SB_OFT_ADDR_MASK;
2869 +
2870 + switch (reg_width) {
2871 + case sizeof(u8): {
2872 + error = sdio_readsb(bus->host_sdio, buffer, offset, count);
2873 + break;
2874 + }
2875 + case sizeof(u16): {
2876 + SSB_WARN_ON(count & 1);
2877 + error = sdio_readsb(bus->host_sdio, buffer, offset, count);
2878 + break;
2879 + }
2880 + case sizeof(u32): {
2881 + SSB_WARN_ON(count & 3);
2882 + offset |= SBSDIO_SB_ACCESS_2_4B_FLAG; /* 32 bit data access */
2883 + error = sdio_readsb(bus->host_sdio, buffer, offset, count);
2884 + break;
2885 + }
2886 + default:
2887 + SSB_WARN_ON(1);
2888 + }
2889 + if (!error)
2890 + goto out;
2891 +
2892 +err_out:
2893 + dev_dbg(ssb_sdio_dev(bus), "%04X:%04X (width=%u, len=%zu), error %d\n",
2894 + bus->sdio_sbaddr >> 16, offset, reg_width, saved_count, error);
2895 +out:
2896 + sdio_release_host(bus->host_sdio);
2897 +}
2898 +#endif /* CONFIG_SSB_BLOCKIO */
2899 +
2900 +static void ssb_sdio_write8(struct ssb_device *dev, u16 offset, u8 val)
2901 +{
2902 + struct ssb_bus *bus = dev->bus;
2903 + int error = 0;
2904 +
2905 + sdio_claim_host(bus->host_sdio);
2906 + if (unlikely(ssb_sdio_switch_core(bus, dev)))
2907 + goto out;
2908 + offset |= bus->sdio_sbaddr & 0xffff;
2909 + offset &= SBSDIO_SB_OFT_ADDR_MASK;
2910 + sdio_writeb(bus->host_sdio, val, offset, &error);
2911 + if (error) {
2912 + dev_dbg(ssb_sdio_dev(bus), "%04X:%04X < %02x, error %d\n",
2913 + bus->sdio_sbaddr >> 16, offset, val, error);
2914 + }
2915 +out:
2916 + sdio_release_host(bus->host_sdio);
2917 +}
2918 +
2919 +static void ssb_sdio_write16(struct ssb_device *dev, u16 offset, u16 val)
2920 +{
2921 + struct ssb_bus *bus = dev->bus;
2922 + int error = 0;
2923 +
2924 + sdio_claim_host(bus->host_sdio);
2925 + if (unlikely(ssb_sdio_switch_core(bus, dev)))
2926 + goto out;
2927 + offset |= bus->sdio_sbaddr & 0xffff;
2928 + offset &= SBSDIO_SB_OFT_ADDR_MASK;
2929 + sdio_writew(bus->host_sdio, val, offset, &error);
2930 + if (error) {
2931 + dev_dbg(ssb_sdio_dev(bus), "%04X:%04X < %04x, error %d\n",
2932 + bus->sdio_sbaddr >> 16, offset, val, error);
2933 + }
2934 +out:
2935 + sdio_release_host(bus->host_sdio);
2936 +}
2937 +
2938 +static void ssb_sdio_write32(struct ssb_device *dev, u16 offset, u32 val)
2939 +{
2940 + struct ssb_bus *bus = dev->bus;
2941 + int error = 0;
2942 +
2943 + sdio_claim_host(bus->host_sdio);
2944 + if (unlikely(ssb_sdio_switch_core(bus, dev)))
2945 + goto out;
2946 + offset |= bus->sdio_sbaddr & 0xffff;
2947 + offset &= SBSDIO_SB_OFT_ADDR_MASK;
2948 + offset |= SBSDIO_SB_ACCESS_2_4B_FLAG; /* 32 bit data access */
2949 + sdio_writel(bus->host_sdio, val, offset, &error);
2950 + if (error) {
2951 + dev_dbg(ssb_sdio_dev(bus), "%04X:%04X < %08x, error %d\n",
2952 + bus->sdio_sbaddr >> 16, offset, val, error);
2953 + }
2954 + if (bus->quirks & SSB_QUIRK_SDIO_READ_AFTER_WRITE32)
2955 + sdio_readl(bus->host_sdio, 0, &error);
2956 +out:
2957 + sdio_release_host(bus->host_sdio);
2958 +}
2959 +
2960 +#ifdef CONFIG_SSB_BLOCKIO
2961 +static void ssb_sdio_block_write(struct ssb_device *dev, const void *buffer,
2962 + size_t count, u16 offset, u8 reg_width)
2963 +{
2964 + size_t saved_count = count;
2965 + struct ssb_bus *bus = dev->bus;
2966 + int error = 0;
2967 +
2968 + sdio_claim_host(bus->host_sdio);
2969 + if (unlikely(ssb_sdio_switch_core(bus, dev))) {
2970 + error = -EIO;
2971 + memset((void *)buffer, 0xff, count);
2972 + goto err_out;
2973 + }
2974 + offset |= bus->sdio_sbaddr & 0xffff;
2975 + offset &= SBSDIO_SB_OFT_ADDR_MASK;
2976 +
2977 + switch (reg_width) {
2978 + case sizeof(u8):
2979 + error = sdio_writesb(bus->host_sdio, offset,
2980 + (void *)buffer, count);
2981 + break;
2982 + case sizeof(u16):
2983 + SSB_WARN_ON(count & 1);
2984 + error = sdio_writesb(bus->host_sdio, offset,
2985 + (void *)buffer, count);
2986 + break;
2987 + case sizeof(u32):
2988 + SSB_WARN_ON(count & 3);
2989 + offset |= SBSDIO_SB_ACCESS_2_4B_FLAG; /* 32 bit data access */
2990 + error = sdio_writesb(bus->host_sdio, offset,
2991 + (void *)buffer, count);
2992 + break;
2993 + default:
2994 + SSB_WARN_ON(1);
2995 + }
2996 + if (!error)
2997 + goto out;
2998 +
2999 +err_out:
3000 + dev_dbg(ssb_sdio_dev(bus), "%04X:%04X (width=%u, len=%zu), error %d\n",
3001 + bus->sdio_sbaddr >> 16, offset, reg_width, saved_count, error);
3002 +out:
3003 + sdio_release_host(bus->host_sdio);
3004 +}
3005 +
3006 +#endif /* CONFIG_SSB_BLOCKIO */
3007 +
3008 +/* Not "static", as it's used in main.c */
3009 +const struct ssb_bus_ops ssb_sdio_ops = {
3010 + .read8 = ssb_sdio_read8,
3011 + .read16 = ssb_sdio_read16,
3012 + .read32 = ssb_sdio_read32,
3013 + .write8 = ssb_sdio_write8,
3014 + .write16 = ssb_sdio_write16,
3015 + .write32 = ssb_sdio_write32,
3016 +#ifdef CONFIG_SSB_BLOCKIO
3017 + .block_read = ssb_sdio_block_read,
3018 + .block_write = ssb_sdio_block_write,
3019 +#endif
3020 +};
3021 +
3022 +#define GOTO_ERROR_ON(condition, description) do { \
3023 + if (unlikely(condition)) { \
3024 + error_description = description; \
3025 + goto error; \
3026 + } \
3027 + } while (0)
3028 +
3029 +int ssb_sdio_get_invariants(struct ssb_bus *bus,
3030 + struct ssb_init_invariants *iv)
3031 +{
3032 + struct ssb_sprom *sprom = &iv->sprom;
3033 + struct ssb_boardinfo *bi = &iv->boardinfo;
3034 + const char *error_description = "none";
3035 + struct sdio_func_tuple *tuple;
3036 + void *mac;
3037 +
3038 + memset(sprom, 0xFF, sizeof(*sprom));
3039 + sprom->boardflags_lo = 0;
3040 + sprom->boardflags_hi = 0;
3041 +
3042 + tuple = bus->host_sdio->tuples;
3043 + while (tuple) {
3044 + switch (tuple->code) {
3045 + case 0x22: /* extended function */
3046 + switch (tuple->data[0]) {
3047 + case CISTPL_FUNCE_LAN_NODE_ID:
3048 + GOTO_ERROR_ON((tuple->size != 7) &&
3049 + (tuple->data[1] != 6),
3050 + "mac tpl size");
3051 + /* fetch the MAC address. */
3052 + mac = tuple->data + 2;
3053 + memcpy(sprom->il0mac, mac, ETH_ALEN);
3054 + memcpy(sprom->et1mac, mac, ETH_ALEN);
3055 + break;
3056 + default:
3057 + break;
3058 + }
3059 + break;
3060 + case 0x80: /* vendor specific tuple */
3061 + switch (tuple->data[0]) {
3062 + case SSB_SDIO_CIS_SROMREV:
3063 + GOTO_ERROR_ON(tuple->size != 2,
3064 + "sromrev tpl size");
3065 + sprom->revision = tuple->data[1];
3066 + break;
3067 + case SSB_SDIO_CIS_ID:
3068 + GOTO_ERROR_ON((tuple->size != 5) &&
3069 + (tuple->size != 7),
3070 + "id tpl size");
3071 + bi->vendor = tuple->data[1] |
3072 + (tuple->data[2]<<8);
3073 + break;
3074 + case SSB_SDIO_CIS_BOARDREV:
3075 + GOTO_ERROR_ON(tuple->size != 2,
3076 + "boardrev tpl size");
3077 + sprom->board_rev = tuple->data[1];
3078 + break;
3079 + case SSB_SDIO_CIS_PA:
3080 + GOTO_ERROR_ON((tuple->size != 9) &&
3081 + (tuple->size != 10),
3082 + "pa tpl size");
3083 + sprom->pa0b0 = tuple->data[1] |
3084 + ((u16)tuple->data[2] << 8);
3085 + sprom->pa0b1 = tuple->data[3] |
3086 + ((u16)tuple->data[4] << 8);
3087 + sprom->pa0b2 = tuple->data[5] |
3088 + ((u16)tuple->data[6] << 8);
3089 + sprom->itssi_a = tuple->data[7];
3090 + sprom->itssi_bg = tuple->data[7];
3091 + sprom->maxpwr_a = tuple->data[8];
3092 + sprom->maxpwr_bg = tuple->data[8];
3093 + break;
3094 + case SSB_SDIO_CIS_OEMNAME:
3095 + /* Not present */
3096 + break;
3097 + case SSB_SDIO_CIS_CCODE:
3098 + GOTO_ERROR_ON(tuple->size != 2,
3099 + "ccode tpl size");
3100 + sprom->country_code = tuple->data[1];
3101 + break;
3102 + case SSB_SDIO_CIS_ANTENNA:
3103 + GOTO_ERROR_ON(tuple->size != 2,
3104 + "ant tpl size");
3105 + sprom->ant_available_a = tuple->data[1];
3106 + sprom->ant_available_bg = tuple->data[1];
3107 + break;
3108 + case SSB_SDIO_CIS_ANTGAIN:
3109 + GOTO_ERROR_ON(tuple->size != 2,
3110 + "antg tpl size");
3111 + sprom->antenna_gain.ghz24.a0 = tuple->data[1];
3112 + sprom->antenna_gain.ghz24.a1 = tuple->data[1];
3113 + sprom->antenna_gain.ghz24.a2 = tuple->data[1];
3114 + sprom->antenna_gain.ghz24.a3 = tuple->data[1];
3115 + sprom->antenna_gain.ghz5.a0 = tuple->data[1];
3116 + sprom->antenna_gain.ghz5.a1 = tuple->data[1];
3117 + sprom->antenna_gain.ghz5.a2 = tuple->data[1];
3118 + sprom->antenna_gain.ghz5.a3 = tuple->data[1];
3119 + break;
3120 + case SSB_SDIO_CIS_BFLAGS:
3121 + GOTO_ERROR_ON((tuple->size != 3) &&
3122 + (tuple->size != 5),
3123 + "bfl tpl size");
3124 + sprom->boardflags_lo = tuple->data[1] |
3125 + ((u16)tuple->data[2] << 8);
3126 + break;
3127 + case SSB_SDIO_CIS_LEDS:
3128 + GOTO_ERROR_ON(tuple->size != 5,
3129 + "leds tpl size");
3130 + sprom->gpio0 = tuple->data[1];
3131 + sprom->gpio1 = tuple->data[2];
3132 + sprom->gpio2 = tuple->data[3];
3133 + sprom->gpio3 = tuple->data[4];
3134 + break;
3135 + default:
3136 + break;
3137 + }
3138 + break;
3139 + default:
3140 + break;
3141 + }
3142 + tuple = tuple->next;
3143 + }
3144 +
3145 + return 0;
3146 +error:
3147 + dev_err(ssb_sdio_dev(bus), "failed to fetch device invariants: %s\n",
3148 + error_description);
3149 + return -ENODEV;
3150 +}
3151 +
3152 +void ssb_sdio_exit(struct ssb_bus *bus)
3153 +{
3154 + if (bus->bustype != SSB_BUSTYPE_SDIO)
3155 + return;
3156 + /* Nothing to do here. */
3157 +}
3158 +
3159 +int ssb_sdio_init(struct ssb_bus *bus)
3160 +{
3161 + if (bus->bustype != SSB_BUSTYPE_SDIO)
3162 + return 0;
3163 +
3164 + bus->sdio_sbaddr = ~0;
3165 +
3166 + return 0;
3167 +}
3168 --- a/drivers/ssb/sprom.c
3169 +++ b/drivers/ssb/sprom.c
3170 @@ -2,7 +2,7 @@
3171 * Sonics Silicon Backplane
3172 * Common SPROM support routines
3173 *
3174 - * Copyright (C) 2005-2008 Michael Buesch <mb@bu3sch.de>
3175 + * Copyright (C) 2005-2008 Michael Buesch <m@bues.ch>
3176 * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
3177 * Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
3178 * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
3179 @@ -13,8 +13,11 @@
3180
3181 #include "ssb_private.h"
3182
3183 +#include <linux/ctype.h>
3184 +#include <linux/slab.h>
3185
3186 -static const struct ssb_sprom *fallback_sprom;
3187 +
3188 +static int(*get_fallback_sprom)(struct ssb_bus *dev, struct ssb_sprom *out);
3189
3190
3191 static int sprom2hex(const u16 *sprom, char *buf, size_t buf_len,
3192 @@ -33,17 +36,27 @@ static int sprom2hex(const u16 *sprom, c
3193 static int hex2sprom(u16 *sprom, const char *dump, size_t len,
3194 size_t sprom_size_words)
3195 {
3196 - char tmp[5] = { 0 };
3197 - int cnt = 0;
3198 + char c, tmp[5] = { 0 };
3199 + int err, cnt = 0;
3200 unsigned long parsed;
3201
3202 - if (len < sprom_size_words * 2)
3203 + /* Strip whitespace at the end. */
3204 + while (len) {
3205 + c = dump[len - 1];
3206 + if (!isspace(c) && c != '\0')
3207 + break;
3208 + len--;
3209 + }
3210 + /* Length must match exactly. */
3211 + if (len != sprom_size_words * 4)
3212 return -EINVAL;
3213
3214 while (cnt < sprom_size_words) {
3215 memcpy(tmp, dump, 4);
3216 dump += 4;
3217 - parsed = simple_strtoul(tmp, NULL, 16);
3218 + err = strict_strtoul(tmp, 16, &parsed);
3219 + if (err)
3220 + return err;
3221 sprom[cnt++] = swab16((u16)parsed);
3222 }
3223
3224 @@ -90,6 +103,7 @@ ssize_t ssb_attr_sprom_store(struct ssb_
3225 u16 *sprom;
3226 int res = 0, err = -ENOMEM;
3227 size_t sprom_size_words = bus->sprom_size;
3228 + struct ssb_freeze_context freeze;
3229
3230 sprom = kcalloc(bus->sprom_size, sizeof(u16), GFP_KERNEL);
3231 if (!sprom)
3232 @@ -111,18 +125,13 @@ ssize_t ssb_attr_sprom_store(struct ssb_
3233 err = -ERESTARTSYS;
3234 if (mutex_lock_interruptible(&bus->sprom_mutex))
3235 goto out_kfree;
3236 - err = ssb_devices_freeze(bus);
3237 - if (err == -EOPNOTSUPP) {
3238 - ssb_printk(KERN_ERR PFX "SPROM write: Could not freeze devices. "
3239 - "No suspend support. Is CONFIG_PM enabled?\n");
3240 - goto out_unlock;
3241 - }
3242 + err = ssb_devices_freeze(bus, &freeze);
3243 if (err) {
3244 ssb_printk(KERN_ERR PFX "SPROM write: Could not freeze all devices\n");
3245 goto out_unlock;
3246 }
3247 res = sprom_write(bus, sprom);
3248 - err = ssb_devices_thaw(bus);
3249 + err = ssb_devices_thaw(&freeze);
3250 if (err)
3251 ssb_printk(KERN_ERR PFX "SPROM write: Could not thaw all devices\n");
3252 out_unlock:
3253 @@ -136,34 +145,56 @@ out:
3254 }
3255
3256 /**
3257 - * ssb_arch_set_fallback_sprom - Set a fallback SPROM for use if no SPROM is found.
3258 - *
3259 - * @sprom: The SPROM data structure to register.
3260 - *
3261 - * With this function the architecture implementation may register a fallback
3262 - * SPROM data structure. The fallback is only used for PCI based SSB devices,
3263 - * where no valid SPROM can be found in the shadow registers.
3264 + * ssb_arch_register_fallback_sprom - Registers a method providing a
3265 + * fallback SPROM if no SPROM is found.
3266 *
3267 - * This function is useful for weird architectures that have a half-assed SSB device
3268 - * hardwired to their PCI bus.
3269 + * @sprom_callback: The callback function.
3270 *
3271 - * Note that it does only work with PCI attached SSB devices. PCMCIA devices currently
3272 - * don't use this fallback.
3273 - * Architectures must provide the SPROM for native SSB devices anyway,
3274 - * so the fallback also isn't used for native devices.
3275 + * With this function the architecture implementation may register a
3276 + * callback handler which fills the SPROM data structure. The fallback is
3277 + * only used for PCI based SSB devices, where no valid SPROM can be found
3278 + * in the shadow registers.
3279 + *
3280 + * This function is useful for weird architectures that have a half-assed
3281 + * SSB device hardwired to their PCI bus.
3282 + *
3283 + * Note that it does only work with PCI attached SSB devices. PCMCIA
3284 + * devices currently don't use this fallback.
3285 + * Architectures must provide the SPROM for native SSB devices anyway, so
3286 + * the fallback also isn't used for native devices.
3287 *
3288 - * This function is available for architecture code, only. So it is not exported.
3289 + * This function is available for architecture code, only. So it is not
3290 + * exported.
3291 */
3292 -int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom)
3293 +int ssb_arch_register_fallback_sprom(int (*sprom_callback)(struct ssb_bus *bus,
3294 + struct ssb_sprom *out))
3295 {
3296 - if (fallback_sprom)
3297 + if (get_fallback_sprom)
3298 return -EEXIST;
3299 - fallback_sprom = sprom;
3300 + get_fallback_sprom = sprom_callback;
3301
3302 return 0;
3303 }
3304
3305 -const struct ssb_sprom *ssb_get_fallback_sprom(void)
3306 +int ssb_fill_sprom_with_fallback(struct ssb_bus *bus, struct ssb_sprom *out)
3307 {
3308 - return fallback_sprom;
3309 + if (!get_fallback_sprom)
3310 + return -ENOENT;
3311 +
3312 + return get_fallback_sprom(bus, out);
3313 +}
3314 +
3315 +/* http://bcm-v4.sipsolutions.net/802.11/IsSpromAvailable */
3316 +bool ssb_is_sprom_available(struct ssb_bus *bus)
3317 +{
3318 + /* status register only exists on chipcomon rev >= 11 and we need check
3319 + for >= 31 only */
3320 + /* this routine differs from specs as we do not access SPROM directly
3321 + on PCMCIA */
3322 + if (bus->bustype == SSB_BUSTYPE_PCI &&
3323 + bus->chipco.dev && /* can be unavailable! */
3324 + bus->chipco.dev->id.revision >= 31)
3325 + return bus->chipco.capabilities & SSB_CHIPCO_CAP_SPROM;
3326 +
3327 + return true;
3328 }
3329 --- a/drivers/ssb/ssb_private.h
3330 +++ b/drivers/ssb/ssb_private.h
3331 @@ -114,6 +114,46 @@ static inline int ssb_pcmcia_init(struct
3332 }
3333 #endif /* CONFIG_SSB_PCMCIAHOST */
3334
3335 +/* sdio.c */
3336 +#ifdef CONFIG_SSB_SDIOHOST
3337 +extern int ssb_sdio_get_invariants(struct ssb_bus *bus,
3338 + struct ssb_init_invariants *iv);
3339 +
3340 +extern u32 ssb_sdio_scan_read32(struct ssb_bus *bus, u16 offset);
3341 +extern int ssb_sdio_switch_core(struct ssb_bus *bus, struct ssb_device *dev);
3342 +extern int ssb_sdio_scan_switch_coreidx(struct ssb_bus *bus, u8 coreidx);
3343 +extern int ssb_sdio_hardware_setup(struct ssb_bus *bus);
3344 +extern void ssb_sdio_exit(struct ssb_bus *bus);
3345 +extern int ssb_sdio_init(struct ssb_bus *bus);
3346 +
3347 +extern const struct ssb_bus_ops ssb_sdio_ops;
3348 +#else /* CONFIG_SSB_SDIOHOST */
3349 +static inline u32 ssb_sdio_scan_read32(struct ssb_bus *bus, u16 offset)
3350 +{
3351 + return 0;
3352 +}
3353 +static inline int ssb_sdio_switch_core(struct ssb_bus *bus,
3354 + struct ssb_device *dev)
3355 +{
3356 + return 0;
3357 +}
3358 +static inline int ssb_sdio_scan_switch_coreidx(struct ssb_bus *bus, u8 coreidx)
3359 +{
3360 + return 0;
3361 +}
3362 +static inline int ssb_sdio_hardware_setup(struct ssb_bus *bus)
3363 +{
3364 + return 0;
3365 +}
3366 +static inline void ssb_sdio_exit(struct ssb_bus *bus)
3367 +{
3368 +}
3369 +static inline int ssb_sdio_init(struct ssb_bus *bus)
3370 +{
3371 + return 0;
3372 +}
3373 +#endif /* CONFIG_SSB_SDIOHOST */
3374 +
3375
3376 /* scan.c */
3377 extern const char *ssb_core_name(u16 coreid);
3378 @@ -131,24 +171,33 @@ ssize_t ssb_attr_sprom_store(struct ssb_
3379 const char *buf, size_t count,
3380 int (*sprom_check_crc)(const u16 *sprom, size_t size),
3381 int (*sprom_write)(struct ssb_bus *bus, const u16 *sprom));
3382 -extern const struct ssb_sprom *ssb_get_fallback_sprom(void);
3383 +extern int ssb_fill_sprom_with_fallback(struct ssb_bus *bus,
3384 + struct ssb_sprom *out);
3385
3386
3387 /* core.c */
3388 extern u32 ssb_calc_clock_rate(u32 plltype, u32 n, u32 m);
3389 -extern int ssb_devices_freeze(struct ssb_bus *bus);
3390 -extern int ssb_devices_thaw(struct ssb_bus *bus);
3391 extern struct ssb_bus *ssb_pci_dev_to_bus(struct pci_dev *pdev);
3392 int ssb_for_each_bus_call(unsigned long data,
3393 int (*func)(struct ssb_bus *bus, unsigned long data));
3394 extern struct ssb_bus *ssb_pcmcia_dev_to_bus(struct pcmcia_device *pdev);
3395
3396 +struct ssb_freeze_context {
3397 + /* Pointer to the bus */
3398 + struct ssb_bus *bus;
3399 + /* Boolean list to indicate whether a device is frozen on this bus. */
3400 + bool device_frozen[SSB_MAX_NR_CORES];
3401 +};
3402 +extern int ssb_devices_freeze(struct ssb_bus *bus, struct ssb_freeze_context *ctx);
3403 +extern int ssb_devices_thaw(struct ssb_freeze_context *ctx);
3404 +
3405 +
3406
3407 /* b43_pci_bridge.c */
3408 #ifdef CONFIG_SSB_B43_PCI_BRIDGE
3409 extern int __init b43_pci_ssb_bridge_init(void);
3410 extern void __exit b43_pci_ssb_bridge_exit(void);
3411 -#else /* CONFIG_SSB_B43_PCI_BRIDGR */
3412 +#else /* CONFIG_SSB_B43_PCI_BRIDGE */
3413 static inline int b43_pci_ssb_bridge_init(void)
3414 {
3415 return 0;
3416 @@ -156,6 +205,6 @@ static inline int b43_pci_ssb_bridge_ini
3417 static inline void b43_pci_ssb_bridge_exit(void)
3418 {
3419 }
3420 -#endif /* CONFIG_SSB_PCIHOST */
3421 +#endif /* CONFIG_SSB_B43_PCI_BRIDGE */
3422
3423 #endif /* LINUX_SSB_PRIVATE_H_ */
3424 --- a/include/linux/pci_ids.h
3425 +++ b/include/linux/pci_ids.h
3426 @@ -2034,6 +2034,7 @@
3427 #define PCI_DEVICE_ID_AFAVLAB_P030 0x2182
3428 #define PCI_SUBDEVICE_ID_AFAVLAB_P061 0x2150
3429
3430 +#define PCI_VENDOR_ID_BCM_GVC 0x14a4
3431 #define PCI_VENDOR_ID_BROADCOM 0x14e4
3432 #define PCI_DEVICE_ID_TIGON3_5752 0x1600
3433 #define PCI_DEVICE_ID_TIGON3_5752M 0x1601
3434 --- a/include/linux/ssb/ssb.h
3435 +++ b/include/linux/ssb/ssb.h
3436 @@ -16,6 +16,12 @@ struct pcmcia_device;
3437 struct ssb_bus;
3438 struct ssb_driver;
3439
3440 +struct ssb_sprom_core_pwr_info {
3441 + u8 itssi_2g, itssi_5g;
3442 + u8 maxpwr_2g, maxpwr_5gl, maxpwr_5g, maxpwr_5gh;
3443 + u16 pa_2g[3], pa_5gl[3], pa_5g[3], pa_5gh[3];
3444 +};
3445 +
3446 struct ssb_sprom {
3447 u8 revision;
3448 u8 il0mac[6]; /* MAC address for 802.11b/g */
3449 @@ -25,26 +31,64 @@ struct ssb_sprom {
3450 u8 et1phyaddr; /* MII address for enet1 */
3451 u8 et0mdcport; /* MDIO for enet0 */
3452 u8 et1mdcport; /* MDIO for enet1 */
3453 - u8 board_rev; /* Board revision number from SPROM. */
3454 + u16 board_rev; /* Board revision number from SPROM. */
3455 u8 country_code; /* Country Code */
3456 - u8 ant_available_a; /* A-PHY antenna available bits (up to 4) */
3457 - u8 ant_available_bg; /* B/G-PHY antenna available bits (up to 4) */
3458 + u16 leddc_on_time; /* LED Powersave Duty Cycle On Count */
3459 + u16 leddc_off_time; /* LED Powersave Duty Cycle Off Count */
3460 + u8 ant_available_a; /* 2GHz antenna available bits (up to 4) */
3461 + u8 ant_available_bg; /* 5GHz antenna available bits (up to 4) */
3462 u16 pa0b0;
3463 u16 pa0b1;
3464 u16 pa0b2;
3465 u16 pa1b0;
3466 u16 pa1b1;
3467 u16 pa1b2;
3468 + u16 pa1lob0;
3469 + u16 pa1lob1;
3470 + u16 pa1lob2;
3471 + u16 pa1hib0;
3472 + u16 pa1hib1;
3473 + u16 pa1hib2;
3474 u8 gpio0; /* GPIO pin 0 */
3475 u8 gpio1; /* GPIO pin 1 */
3476 u8 gpio2; /* GPIO pin 2 */
3477 u8 gpio3; /* GPIO pin 3 */
3478 - u16 maxpwr_a; /* A-PHY Amplifier Max Power (in dBm Q5.2) */
3479 - u16 maxpwr_bg; /* B/G-PHY Amplifier Max Power (in dBm Q5.2) */
3480 + u16 maxpwr_bg; /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */
3481 + u16 maxpwr_al; /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */
3482 + u16 maxpwr_a; /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */
3483 + u16 maxpwr_ah; /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */
3484 u8 itssi_a; /* Idle TSSI Target for A-PHY */
3485 u8 itssi_bg; /* Idle TSSI Target for B/G-PHY */
3486 - u16 boardflags_lo; /* Boardflags (low 16 bits) */
3487 - u16 boardflags_hi; /* Boardflags (high 16 bits) */
3488 + u8 tri2g; /* 2.4GHz TX isolation */
3489 + u8 tri5gl; /* 5.2GHz TX isolation */
3490 + u8 tri5g; /* 5.3GHz TX isolation */
3491 + u8 tri5gh; /* 5.8GHz TX isolation */
3492 + u8 txpid2g[4]; /* 2GHz TX power index */
3493 + u8 txpid5gl[4]; /* 4.9 - 5.1GHz TX power index */
3494 + u8 txpid5g[4]; /* 5.1 - 5.5GHz TX power index */
3495 + u8 txpid5gh[4]; /* 5.5 - ...GHz TX power index */
3496 + u8 rxpo2g; /* 2GHz RX power offset */
3497 + u8 rxpo5g; /* 5GHz RX power offset */
3498 + u8 rssisav2g; /* 2GHz RSSI params */
3499 + u8 rssismc2g;
3500 + u8 rssismf2g;
3501 + u8 bxa2g; /* 2GHz BX arch */
3502 + u8 rssisav5g; /* 5GHz RSSI params */
3503 + u8 rssismc5g;
3504 + u8 rssismf5g;
3505 + u8 bxa5g; /* 5GHz BX arch */
3506 + u16 cck2gpo; /* CCK power offset */
3507 + u32 ofdm2gpo; /* 2.4GHz OFDM power offset */
3508 + u32 ofdm5glpo; /* 5.2GHz OFDM power offset */
3509 + u32 ofdm5gpo; /* 5.3GHz OFDM power offset */
3510 + u32 ofdm5ghpo; /* 5.8GHz OFDM power offset */
3511 + u16 boardflags_lo; /* Board flags (bits 0-15) */
3512 + u16 boardflags_hi; /* Board flags (bits 16-31) */
3513 + u16 boardflags2_lo; /* Board flags (bits 32-47) */
3514 + u16 boardflags2_hi; /* Board flags (bits 48-63) */
3515 + /* TODO store board flags in a single u64 */
3516 +
3517 + struct ssb_sprom_core_pwr_info core_pwr_info[4];
3518
3519 /* Antenna gain values for up to 4 antennas
3520 * on each band. Values in dBm/4 (Q5.2). Negative gain means the
3521 @@ -58,14 +102,23 @@ struct ssb_sprom {
3522 } ghz5; /* 5GHz band */
3523 } antenna_gain;
3524
3525 - /* TODO - add any parameters needed from rev 2, 3, or 4 SPROMs */
3526 + struct {
3527 + struct {
3528 + u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
3529 + } ghz2;
3530 + struct {
3531 + u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
3532 + } ghz5;
3533 + } fem;
3534 +
3535 + /* TODO - add any parameters needed from rev 2, 3, 4, 5 or 8 SPROMs */
3536 };
3537
3538 /* Information about the PCB the circuitry is soldered on. */
3539 struct ssb_boardinfo {
3540 u16 vendor;
3541 u16 type;
3542 - u16 rev;
3543 + u8 rev;
3544 };
3545
3546
3547 @@ -137,7 +190,7 @@ struct ssb_device {
3548 * is an optimization. */
3549 const struct ssb_bus_ops *ops;
3550
3551 - struct device *dev;
3552 + struct device *dev, *dma_dev;
3553
3554 struct ssb_bus *bus;
3555 struct ssb_device_id id;
3556 @@ -195,10 +248,9 @@ struct ssb_driver {
3557 #define drv_to_ssb_drv(_drv) container_of(_drv, struct ssb_driver, drv)
3558
3559 extern int __ssb_driver_register(struct ssb_driver *drv, struct module *owner);
3560 -static inline int ssb_driver_register(struct ssb_driver *drv)
3561 -{
3562 - return __ssb_driver_register(drv, THIS_MODULE);
3563 -}
3564 +#define ssb_driver_register(drv) \
3565 + __ssb_driver_register(drv, THIS_MODULE)
3566 +
3567 extern void ssb_driver_unregister(struct ssb_driver *drv);
3568
3569
3570 @@ -208,6 +260,7 @@ enum ssb_bustype {
3571 SSB_BUSTYPE_SSB, /* This SSB bus is the system bus */
3572 SSB_BUSTYPE_PCI, /* SSB is connected to PCI bus */
3573 SSB_BUSTYPE_PCMCIA, /* SSB is connected to PCMCIA bus */
3574 + SSB_BUSTYPE_SDIO, /* SSB is connected to SDIO bus */
3575 };
3576
3577 /* board_vendor */
3578 @@ -238,20 +291,33 @@ struct ssb_bus {
3579
3580 const struct ssb_bus_ops *ops;
3581
3582 - /* The core in the basic address register window. (PCI bus only) */
3583 + /* The core currently mapped into the MMIO window.
3584 + * Not valid on all host-buses. So don't use outside of SSB. */
3585 struct ssb_device *mapped_device;
3586 - /* Currently mapped PCMCIA segment. (bustype == SSB_BUSTYPE_PCMCIA only) */
3587 - u8 mapped_pcmcia_seg;
3588 + union {
3589 + /* Currently mapped PCMCIA segment. (bustype == SSB_BUSTYPE_PCMCIA only) */
3590 + u8 mapped_pcmcia_seg;
3591 + /* Current SSB base address window for SDIO. */
3592 + u32 sdio_sbaddr;
3593 + };
3594 /* Lock for core and segment switching.
3595 * On PCMCIA-host busses this is used to protect the whole MMIO access. */
3596 spinlock_t bar_lock;
3597
3598 - /* The bus this backplane is running on. */
3599 + /* The host-bus this backplane is running on. */
3600 enum ssb_bustype bustype;
3601 - /* Pointer to the PCI bus (only valid if bustype == SSB_BUSTYPE_PCI). */
3602 - struct pci_dev *host_pci;
3603 - /* Pointer to the PCMCIA device (only if bustype == SSB_BUSTYPE_PCMCIA). */
3604 - struct pcmcia_device *host_pcmcia;
3605 + /* Pointers to the host-bus. Check bustype before using any of these pointers. */
3606 + union {
3607 + /* Pointer to the PCI bus (only valid if bustype == SSB_BUSTYPE_PCI). */
3608 + struct pci_dev *host_pci;
3609 + /* Pointer to the PCMCIA device (only if bustype == SSB_BUSTYPE_PCMCIA). */
3610 + struct pcmcia_device *host_pcmcia;
3611 + /* Pointer to the SDIO device (only if bustype == SSB_BUSTYPE_SDIO). */
3612 + struct sdio_func *host_sdio;
3613 + };
3614 +
3615 + /* See enum ssb_quirks */
3616 + unsigned int quirks;
3617
3618 #ifdef CONFIG_SSB_SPROM
3619 /* Mutex to protect the SPROM writing. */
3620 @@ -260,7 +326,8 @@ struct ssb_bus {
3621
3622 /* ID information about the Chip. */
3623 u16 chip_id;
3624 - u16 chip_rev;
3625 + u8 chip_rev;
3626 + u16 sprom_offset;
3627 u16 sprom_size; /* number of words in sprom */
3628 u8 chip_package;
3629
3630 @@ -306,6 +373,11 @@ struct ssb_bus {
3631 #endif /* DEBUG */
3632 };
3633
3634 +enum ssb_quirks {
3635 + /* SDIO connected card requires performing a read after writing a 32-bit value */
3636 + SSB_QUIRK_SDIO_READ_AFTER_WRITE32 = (1 << 0),
3637 +};
3638 +
3639 /* The initialization-invariants. */
3640 struct ssb_init_invariants {
3641 /* Versioning information about the PCB. */
3642 @@ -336,12 +408,23 @@ extern int ssb_bus_pcmciabus_register(st
3643 struct pcmcia_device *pcmcia_dev,
3644 unsigned long baseaddr);
3645 #endif /* CONFIG_SSB_PCMCIAHOST */
3646 +#ifdef CONFIG_SSB_SDIOHOST
3647 +extern int ssb_bus_sdiobus_register(struct ssb_bus *bus,
3648 + struct sdio_func *sdio_func,
3649 + unsigned int quirks);
3650 +#endif /* CONFIG_SSB_SDIOHOST */
3651 +
3652
3653 extern void ssb_bus_unregister(struct ssb_bus *bus);
3654
3655 +/* Does the device have an SPROM? */
3656 +extern bool ssb_is_sprom_available(struct ssb_bus *bus);
3657 +
3658 /* Set a fallback SPROM.
3659 * See kdoc at the function definition for complete documentation. */
3660 -extern int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom);
3661 +extern int ssb_arch_register_fallback_sprom(
3662 + int (*sprom_callback)(struct ssb_bus *bus,
3663 + struct ssb_sprom *out));
3664
3665 /* Suspend a SSB bus.
3666 * Call this from the parent bus suspend routine. */
3667 @@ -612,6 +695,7 @@ extern int ssb_bus_may_powerdown(struct
3668 * Otherwise static always-on powercontrol will be used. */
3669 extern int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl);
3670
3671 +extern void ssb_commit_settings(struct ssb_bus *bus);
3672
3673 /* Various helper functions */
3674 extern u32 ssb_admatch_base(u32 adm);
3675 --- a/include/linux/ssb/ssb_driver_chipcommon.h
3676 +++ b/include/linux/ssb/ssb_driver_chipcommon.h
3677 @@ -8,7 +8,7 @@
3678 * gpio interface, extbus, and support for serial and parallel flashes.
3679 *
3680 * Copyright 2005, Broadcom Corporation
3681 - * Copyright 2006, Michael Buesch <mb@bu3sch.de>
3682 + * Copyright 2006, Michael Buesch <m@bues.ch>
3683 *
3684 * Licensed under the GPL version 2. See COPYING for details.
3685 */
3686 @@ -53,6 +53,7 @@
3687 #define SSB_CHIPCO_CAP_64BIT 0x08000000 /* 64-bit Backplane */
3688 #define SSB_CHIPCO_CAP_PMU 0x10000000 /* PMU available (rev >= 20) */
3689 #define SSB_CHIPCO_CAP_ECI 0x20000000 /* ECI available (rev >= 20) */
3690 +#define SSB_CHIPCO_CAP_SPROM 0x40000000 /* SPROM present */
3691 #define SSB_CHIPCO_CORECTL 0x0008
3692 #define SSB_CHIPCO_CORECTL_UARTCLK0 0x00000001 /* Drive UART with internal clock */
3693 #define SSB_CHIPCO_CORECTL_SE 0x00000002 /* sync clk out enable (corerev >= 3) */
3694 @@ -122,6 +123,8 @@
3695 #define SSB_CHIPCO_FLASHDATA 0x0048
3696 #define SSB_CHIPCO_BCAST_ADDR 0x0050
3697 #define SSB_CHIPCO_BCAST_DATA 0x0054
3698 +#define SSB_CHIPCO_GPIOPULLUP 0x0058 /* Rev >= 20 only */
3699 +#define SSB_CHIPCO_GPIOPULLDOWN 0x005C /* Rev >= 20 only */
3700 #define SSB_CHIPCO_GPIOIN 0x0060
3701 #define SSB_CHIPCO_GPIOOUT 0x0064
3702 #define SSB_CHIPCO_GPIOOUTEN 0x0068
3703 @@ -130,6 +133,9 @@
3704 #define SSB_CHIPCO_GPIOIRQ 0x0074
3705 #define SSB_CHIPCO_WATCHDOG 0x0080
3706 #define SSB_CHIPCO_GPIOTIMER 0x0088 /* LED powersave (corerev >= 16) */
3707 +#define SSB_CHIPCO_GPIOTIMER_OFFTIME 0x0000FFFF
3708 +#define SSB_CHIPCO_GPIOTIMER_OFFTIME_SHIFT 0
3709 +#define SSB_CHIPCO_GPIOTIMER_ONTIME 0xFFFF0000
3710 #define SSB_CHIPCO_GPIOTIMER_ONTIME_SHIFT 16
3711 #define SSB_CHIPCO_GPIOTOUTM 0x008C /* LED powersave (corerev >= 16) */
3712 #define SSB_CHIPCO_CLOCK_N 0x0090
3713 @@ -188,8 +194,10 @@
3714 #define SSB_CHIPCO_CLKCTLST_HAVEALPREQ 0x00000008 /* ALP available request */
3715 #define SSB_CHIPCO_CLKCTLST_HAVEHTREQ 0x00000010 /* HT available request */
3716 #define SSB_CHIPCO_CLKCTLST_HWCROFF 0x00000020 /* Force HW clock request off */
3717 -#define SSB_CHIPCO_CLKCTLST_HAVEHT 0x00010000 /* HT available */
3718 -#define SSB_CHIPCO_CLKCTLST_HAVEALP 0x00020000 /* APL available */
3719 +#define SSB_CHIPCO_CLKCTLST_HAVEALP 0x00010000 /* ALP available */
3720 +#define SSB_CHIPCO_CLKCTLST_HAVEHT 0x00020000 /* HT available */
3721 +#define SSB_CHIPCO_CLKCTLST_4328A0_HAVEHT 0x00010000 /* 4328a0 has reversed bits */
3722 +#define SSB_CHIPCO_CLKCTLST_4328A0_HAVEALP 0x00020000 /* 4328a0 has reversed bits */
3723 #define SSB_CHIPCO_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */
3724 #define SSB_CHIPCO_UART0_DATA 0x0300
3725 #define SSB_CHIPCO_UART0_IMR 0x0304
3726 @@ -385,6 +393,7 @@
3727
3728
3729 /** Chip specific Chip-Status register contents. */
3730 +#define SSB_CHIPCO_CHST_4322_SPROM_EXISTS 0x00000040 /* SPROM present */
3731 #define SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL 0x00000003
3732 #define SSB_CHIPCO_CHST_4325_DEFCIS_SEL 0 /* OTP is powered up, use def. CIS, no SPROM */
3733 #define SSB_CHIPCO_CHST_4325_SPROM_SEL 1 /* OTP is powered up, SPROM is present */
3734 @@ -398,6 +407,18 @@
3735 #define SSB_CHIPCO_CHST_4325_RCAL_VALUE_SHIFT 4
3736 #define SSB_CHIPCO_CHST_4325_PMUTOP_2B 0x00000200 /* 1 for 2b, 0 for to 2a */
3737
3738 +/** Macros to determine SPROM presence based on Chip-Status register. */
3739 +#define SSB_CHIPCO_CHST_4312_SPROM_PRESENT(status) \
3740 + ((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
3741 + SSB_CHIPCO_CHST_4325_OTP_SEL)
3742 +#define SSB_CHIPCO_CHST_4322_SPROM_PRESENT(status) \
3743 + (status & SSB_CHIPCO_CHST_4322_SPROM_EXISTS)
3744 +#define SSB_CHIPCO_CHST_4325_SPROM_PRESENT(status) \
3745 + (((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
3746 + SSB_CHIPCO_CHST_4325_DEFCIS_SEL) && \
3747 + ((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \
3748 + SSB_CHIPCO_CHST_4325_OTP_SEL))
3749 +
3750
3751
3752 /** Clockcontrol masks and values **/
3753 @@ -564,6 +585,7 @@ struct ssb_chipcommon_pmu {
3754 struct ssb_chipcommon {
3755 struct ssb_device *dev;
3756 u32 capabilities;
3757 + u32 status;
3758 /* Fast Powerup Delay constant */
3759 u16 fast_pwrup_delay;
3760 struct ssb_chipcommon_pmu pmu;
3761 @@ -629,5 +651,15 @@ extern int ssb_chipco_serial_init(struct
3762 /* PMU support */
3763 extern void ssb_pmu_init(struct ssb_chipcommon *cc);
3764
3765 +enum ssb_pmu_ldo_volt_id {
3766 + LDO_PAREF = 0,
3767 + LDO_VOLT1,
3768 + LDO_VOLT2,
3769 + LDO_VOLT3,
3770 +};
3771 +
3772 +void ssb_pmu_set_ldo_voltage(struct ssb_chipcommon *cc,
3773 + enum ssb_pmu_ldo_volt_id id, u32 voltage);
3774 +void ssb_pmu_set_ldo_paref(struct ssb_chipcommon *cc, bool on);
3775
3776 #endif /* LINUX_SSB_CHIPCO_H_ */
3777 --- a/include/linux/ssb/ssb_regs.h
3778 +++ b/include/linux/ssb/ssb_regs.h
3779 @@ -85,6 +85,8 @@
3780 #define SSB_IMSTATE_AP_RSV 0x00000030 /* Reserved */
3781 #define SSB_IMSTATE_IBE 0x00020000 /* In Band Error */
3782 #define SSB_IMSTATE_TO 0x00040000 /* Timeout */
3783 +#define SSB_IMSTATE_BUSY 0x01800000 /* Busy (Backplane rev >= 2.3 only) */
3784 +#define SSB_IMSTATE_REJECT 0x02000000 /* Reject (Backplane rev >= 2.3 only) */
3785 #define SSB_INTVEC 0x0F94 /* SB Interrupt Mask */
3786 #define SSB_INTVEC_PCI 0x00000001 /* Enable interrupts for PCI */
3787 #define SSB_INTVEC_ENET0 0x00000002 /* Enable interrupts for enet 0 */
3788 @@ -95,7 +97,7 @@
3789 #define SSB_INTVEC_ENET1 0x00000040 /* Enable interrupts for enet 1 */
3790 #define SSB_TMSLOW 0x0F98 /* SB Target State Low */
3791 #define SSB_TMSLOW_RESET 0x00000001 /* Reset */
3792 -#define SSB_TMSLOW_REJECT_22 0x00000002 /* Reject (Backplane rev 2.2) */
3793 +#define SSB_TMSLOW_REJECT 0x00000002 /* Reject (Standard Backplane) */
3794 #define SSB_TMSLOW_REJECT_23 0x00000004 /* Reject (Backplane rev 2.3) */
3795 #define SSB_TMSLOW_CLOCK 0x00010000 /* Clock Enable */
3796 #define SSB_TMSLOW_FGC 0x00020000 /* Force Gated Clocks On */
3797 @@ -162,7 +164,7 @@
3798
3799 /* SPROM shadow area. If not otherwise noted, fields are
3800 * two bytes wide. Note that the SPROM can _only_ be read
3801 - * in two-byte quantinies.
3802 + * in two-byte quantities.
3803 */
3804 #define SSB_SPROMSIZE_WORDS 64
3805 #define SSB_SPROMSIZE_BYTES (SSB_SPROMSIZE_WORDS * sizeof(u16))
3806 @@ -170,26 +172,27 @@
3807 #define SSB_SPROMSIZE_WORDS_R4 220
3808 #define SSB_SPROMSIZE_BYTES_R123 (SSB_SPROMSIZE_WORDS_R123 * sizeof(u16))
3809 #define SSB_SPROMSIZE_BYTES_R4 (SSB_SPROMSIZE_WORDS_R4 * sizeof(u16))
3810 -#define SSB_SPROM_BASE 0x1000
3811 -#define SSB_SPROM_REVISION 0x107E
3812 +#define SSB_SPROM_BASE1 0x1000
3813 +#define SSB_SPROM_BASE31 0x0800
3814 +#define SSB_SPROM_REVISION 0x007E
3815 #define SSB_SPROM_REVISION_REV 0x00FF /* SPROM Revision number */
3816 #define SSB_SPROM_REVISION_CRC 0xFF00 /* SPROM CRC8 value */
3817 #define SSB_SPROM_REVISION_CRC_SHIFT 8
3818
3819 /* SPROM Revision 1 */
3820 -#define SSB_SPROM1_SPID 0x1004 /* Subsystem Product ID for PCI */
3821 -#define SSB_SPROM1_SVID 0x1006 /* Subsystem Vendor ID for PCI */
3822 -#define SSB_SPROM1_PID 0x1008 /* Product ID for PCI */
3823 -#define SSB_SPROM1_IL0MAC 0x1048 /* 6 bytes MAC address for 802.11b/g */
3824 -#define SSB_SPROM1_ET0MAC 0x104E /* 6 bytes MAC address for Ethernet */
3825 -#define SSB_SPROM1_ET1MAC 0x1054 /* 6 bytes MAC address for 802.11a */
3826 -#define SSB_SPROM1_ETHPHY 0x105A /* Ethernet PHY settings */
3827 +#define SSB_SPROM1_SPID 0x0004 /* Subsystem Product ID for PCI */
3828 +#define SSB_SPROM1_SVID 0x0006 /* Subsystem Vendor ID for PCI */
3829 +#define SSB_SPROM1_PID 0x0008 /* Product ID for PCI */
3830 +#define SSB_SPROM1_IL0MAC 0x0048 /* 6 bytes MAC address for 802.11b/g */
3831 +#define SSB_SPROM1_ET0MAC 0x004E /* 6 bytes MAC address for Ethernet */
3832 +#define SSB_SPROM1_ET1MAC 0x0054 /* 6 bytes MAC address for 802.11a */
3833 +#define SSB_SPROM1_ETHPHY 0x005A /* Ethernet PHY settings */
3834 #define SSB_SPROM1_ETHPHY_ET0A 0x001F /* MII Address for enet0 */
3835 #define SSB_SPROM1_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */
3836 #define SSB_SPROM1_ETHPHY_ET1A_SHIFT 5
3837 #define SSB_SPROM1_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */
3838 #define SSB_SPROM1_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */
3839 -#define SSB_SPROM1_BINF 0x105C /* Board info */
3840 +#define SSB_SPROM1_BINF 0x005C /* Board info */
3841 #define SSB_SPROM1_BINF_BREV 0x00FF /* Board Revision */
3842 #define SSB_SPROM1_BINF_CCODE 0x0F00 /* Country Code */
3843 #define SSB_SPROM1_BINF_CCODE_SHIFT 8
3844 @@ -197,63 +200,63 @@
3845 #define SSB_SPROM1_BINF_ANTBG_SHIFT 12
3846 #define SSB_SPROM1_BINF_ANTA 0xC000 /* Available A-PHY antennas */
3847 #define SSB_SPROM1_BINF_ANTA_SHIFT 14
3848 -#define SSB_SPROM1_PA0B0 0x105E
3849 -#define SSB_SPROM1_PA0B1 0x1060
3850 -#define SSB_SPROM1_PA0B2 0x1062
3851 -#define SSB_SPROM1_GPIOA 0x1064 /* General Purpose IO pins 0 and 1 */
3852 +#define SSB_SPROM1_PA0B0 0x005E
3853 +#define SSB_SPROM1_PA0B1 0x0060
3854 +#define SSB_SPROM1_PA0B2 0x0062
3855 +#define SSB_SPROM1_GPIOA 0x0064 /* General Purpose IO pins 0 and 1 */
3856 #define SSB_SPROM1_GPIOA_P0 0x00FF /* Pin 0 */
3857 #define SSB_SPROM1_GPIOA_P1 0xFF00 /* Pin 1 */
3858 #define SSB_SPROM1_GPIOA_P1_SHIFT 8
3859 -#define SSB_SPROM1_GPIOB 0x1066 /* General Purpuse IO pins 2 and 3 */
3860 +#define SSB_SPROM1_GPIOB 0x0066 /* General Purpuse IO pins 2 and 3 */
3861 #define SSB_SPROM1_GPIOB_P2 0x00FF /* Pin 2 */
3862 #define SSB_SPROM1_GPIOB_P3 0xFF00 /* Pin 3 */
3863 #define SSB_SPROM1_GPIOB_P3_SHIFT 8
3864 -#define SSB_SPROM1_MAXPWR 0x1068 /* Power Amplifier Max Power */
3865 +#define SSB_SPROM1_MAXPWR 0x0068 /* Power Amplifier Max Power */
3866 #define SSB_SPROM1_MAXPWR_BG 0x00FF /* B-PHY and G-PHY (in dBm Q5.2) */
3867 #define SSB_SPROM1_MAXPWR_A 0xFF00 /* A-PHY (in dBm Q5.2) */
3868 #define SSB_SPROM1_MAXPWR_A_SHIFT 8
3869 -#define SSB_SPROM1_PA1B0 0x106A
3870 -#define SSB_SPROM1_PA1B1 0x106C
3871 -#define SSB_SPROM1_PA1B2 0x106E
3872 -#define SSB_SPROM1_ITSSI 0x1070 /* Idle TSSI Target */
3873 +#define SSB_SPROM1_PA1B0 0x006A
3874 +#define SSB_SPROM1_PA1B1 0x006C
3875 +#define SSB_SPROM1_PA1B2 0x006E
3876 +#define SSB_SPROM1_ITSSI 0x0070 /* Idle TSSI Target */
3877 #define SSB_SPROM1_ITSSI_BG 0x00FF /* B-PHY and G-PHY*/
3878 #define SSB_SPROM1_ITSSI_A 0xFF00 /* A-PHY */
3879 #define SSB_SPROM1_ITSSI_A_SHIFT 8
3880 -#define SSB_SPROM1_BFLLO 0x1072 /* Boardflags (low 16 bits) */
3881 -#define SSB_SPROM1_AGAIN 0x1074 /* Antenna Gain (in dBm Q5.2) */
3882 +#define SSB_SPROM1_BFLLO 0x0072 /* Boardflags (low 16 bits) */
3883 +#define SSB_SPROM1_AGAIN 0x0074 /* Antenna Gain (in dBm Q5.2) */
3884 #define SSB_SPROM1_AGAIN_BG 0x00FF /* B-PHY and G-PHY */
3885 #define SSB_SPROM1_AGAIN_BG_SHIFT 0
3886 #define SSB_SPROM1_AGAIN_A 0xFF00 /* A-PHY */
3887 #define SSB_SPROM1_AGAIN_A_SHIFT 8
3888
3889 /* SPROM Revision 2 (inherits from rev 1) */
3890 -#define SSB_SPROM2_BFLHI 0x1038 /* Boardflags (high 16 bits) */
3891 -#define SSB_SPROM2_MAXP_A 0x103A /* A-PHY Max Power */
3892 +#define SSB_SPROM2_BFLHI 0x0038 /* Boardflags (high 16 bits) */
3893 +#define SSB_SPROM2_MAXP_A 0x003A /* A-PHY Max Power */
3894 #define SSB_SPROM2_MAXP_A_HI 0x00FF /* Max Power High */
3895 #define SSB_SPROM2_MAXP_A_LO 0xFF00 /* Max Power Low */
3896 #define SSB_SPROM2_MAXP_A_LO_SHIFT 8
3897 -#define SSB_SPROM2_PA1LOB0 0x103C /* A-PHY PowerAmplifier Low Settings */
3898 -#define SSB_SPROM2_PA1LOB1 0x103E /* A-PHY PowerAmplifier Low Settings */
3899 -#define SSB_SPROM2_PA1LOB2 0x1040 /* A-PHY PowerAmplifier Low Settings */
3900 -#define SSB_SPROM2_PA1HIB0 0x1042 /* A-PHY PowerAmplifier High Settings */
3901 -#define SSB_SPROM2_PA1HIB1 0x1044 /* A-PHY PowerAmplifier High Settings */
3902 -#define SSB_SPROM2_PA1HIB2 0x1046 /* A-PHY PowerAmplifier High Settings */
3903 -#define SSB_SPROM2_OPO 0x1078 /* OFDM Power Offset from CCK Level */
3904 +#define SSB_SPROM2_PA1LOB0 0x003C /* A-PHY PowerAmplifier Low Settings */
3905 +#define SSB_SPROM2_PA1LOB1 0x003E /* A-PHY PowerAmplifier Low Settings */
3906 +#define SSB_SPROM2_PA1LOB2 0x0040 /* A-PHY PowerAmplifier Low Settings */
3907 +#define SSB_SPROM2_PA1HIB0 0x0042 /* A-PHY PowerAmplifier High Settings */
3908 +#define SSB_SPROM2_PA1HIB1 0x0044 /* A-PHY PowerAmplifier High Settings */
3909 +#define SSB_SPROM2_PA1HIB2 0x0046 /* A-PHY PowerAmplifier High Settings */
3910 +#define SSB_SPROM2_OPO 0x0078 /* OFDM Power Offset from CCK Level */
3911 #define SSB_SPROM2_OPO_VALUE 0x00FF
3912 #define SSB_SPROM2_OPO_UNUSED 0xFF00
3913 -#define SSB_SPROM2_CCODE 0x107C /* Two char Country Code */
3914 +#define SSB_SPROM2_CCODE 0x007C /* Two char Country Code */
3915
3916 /* SPROM Revision 3 (inherits most data from rev 2) */
3917 -#define SSB_SPROM3_IL0MAC 0x104A /* 6 bytes MAC address for 802.11b/g */
3918 -#define SSB_SPROM3_OFDMAPO 0x102C /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
3919 -#define SSB_SPROM3_OFDMALPO 0x1030 /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
3920 -#define SSB_SPROM3_OFDMAHPO 0x1034 /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
3921 -#define SSB_SPROM3_GPIOLDC 0x1042 /* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */
3922 +#define SSB_SPROM3_OFDMAPO 0x002C /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
3923 +#define SSB_SPROM3_OFDMALPO 0x0030 /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
3924 +#define SSB_SPROM3_OFDMAHPO 0x0034 /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
3925 +#define SSB_SPROM3_GPIOLDC 0x0042 /* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */
3926 #define SSB_SPROM3_GPIOLDC_OFF 0x0000FF00 /* Off Count */
3927 #define SSB_SPROM3_GPIOLDC_OFF_SHIFT 8
3928 #define SSB_SPROM3_GPIOLDC_ON 0x00FF0000 /* On Count */
3929 #define SSB_SPROM3_GPIOLDC_ON_SHIFT 16
3930 -#define SSB_SPROM3_CCKPO 0x1078 /* CCK Power Offset */
3931 +#define SSB_SPROM3_IL0MAC 0x004A /* 6 bytes MAC address for 802.11b/g */
3932 +#define SSB_SPROM3_CCKPO 0x0078 /* CCK Power Offset */
3933 #define SSB_SPROM3_CCKPO_1M 0x000F /* 1M Rate PO */
3934 #define SSB_SPROM3_CCKPO_2M 0x00F0 /* 2M Rate PO */
3935 #define SSB_SPROM3_CCKPO_2M_SHIFT 4
3936 @@ -264,104 +267,291 @@
3937 #define SSB_SPROM3_OFDMGPO 0x107A /* G-PHY OFDM Power Offset (4 bytes, BigEndian) */
3938
3939 /* SPROM Revision 4 */
3940 -#define SSB_SPROM4_IL0MAC 0x104C /* 6 byte MAC address for a/b/g/n */
3941 -#define SSB_SPROM4_ETHPHY 0x105A /* Ethernet PHY settings ?? */
3942 +#define SSB_SPROM4_BFLLO 0x0044 /* Boardflags (low 16 bits) */
3943 +#define SSB_SPROM4_BFLHI 0x0046 /* Board Flags Hi */
3944 +#define SSB_SPROM4_BFL2LO 0x0048 /* Board flags 2 (low 16 bits) */
3945 +#define SSB_SPROM4_BFL2HI 0x004A /* Board flags 2 Hi */
3946 +#define SSB_SPROM4_IL0MAC 0x004C /* 6 byte MAC address for a/b/g/n */
3947 +#define SSB_SPROM4_CCODE 0x0052 /* Country Code (2 bytes) */
3948 +#define SSB_SPROM4_GPIOA 0x0056 /* Gen. Purpose IO # 0 and 1 */
3949 +#define SSB_SPROM4_GPIOA_P0 0x00FF /* Pin 0 */
3950 +#define SSB_SPROM4_GPIOA_P1 0xFF00 /* Pin 1 */
3951 +#define SSB_SPROM4_GPIOA_P1_SHIFT 8
3952 +#define SSB_SPROM4_GPIOB 0x0058 /* Gen. Purpose IO # 2 and 3 */
3953 +#define SSB_SPROM4_GPIOB_P2 0x00FF /* Pin 2 */
3954 +#define SSB_SPROM4_GPIOB_P3 0xFF00 /* Pin 3 */
3955 +#define SSB_SPROM4_GPIOB_P3_SHIFT 8
3956 +#define SSB_SPROM4_ETHPHY 0x005A /* Ethernet PHY settings ?? */
3957 #define SSB_SPROM4_ETHPHY_ET0A 0x001F /* MII Address for enet0 */
3958 #define SSB_SPROM4_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */
3959 #define SSB_SPROM4_ETHPHY_ET1A_SHIFT 5
3960 #define SSB_SPROM4_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */
3961 #define SSB_SPROM4_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */
3962 -#define SSB_SPROM4_CCODE 0x1052 /* Country Code (2 bytes) */
3963 -#define SSB_SPROM4_ANTAVAIL 0x105D /* Antenna available bitfields */
3964 -#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */
3965 -#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0
3966 -#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */
3967 -#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8
3968 -#define SSB_SPROM4_BFLLO 0x1044 /* Boardflags (low 16 bits) */
3969 -#define SSB_SPROM4_AGAIN01 0x105E /* Antenna Gain (in dBm Q5.2) */
3970 +#define SSB_SPROM4_ANTAVAIL 0x005D /* Antenna available bitfields */
3971 +#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */
3972 +#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0
3973 +#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */
3974 +#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8
3975 +#define SSB_SPROM4_AGAIN01 0x005E /* Antenna Gain (in dBm Q5.2) */
3976 #define SSB_SPROM4_AGAIN0 0x00FF /* Antenna 0 */
3977 #define SSB_SPROM4_AGAIN0_SHIFT 0
3978 #define SSB_SPROM4_AGAIN1 0xFF00 /* Antenna 1 */
3979 #define SSB_SPROM4_AGAIN1_SHIFT 8
3980 -#define SSB_SPROM4_AGAIN23 0x1060
3981 +#define SSB_SPROM4_AGAIN23 0x0060
3982 #define SSB_SPROM4_AGAIN2 0x00FF /* Antenna 2 */
3983 #define SSB_SPROM4_AGAIN2_SHIFT 0
3984 #define SSB_SPROM4_AGAIN3 0xFF00 /* Antenna 3 */
3985 #define SSB_SPROM4_AGAIN3_SHIFT 8
3986 -#define SSB_SPROM4_BFLHI 0x1046 /* Board Flags Hi */
3987 -#define SSB_SPROM4_MAXP_BG 0x1080 /* Max Power BG in path 1 */
3988 +#define SSB_SPROM4_TXPID2G01 0x0062 /* TX Power Index 2GHz */
3989 +#define SSB_SPROM4_TXPID2G0 0x00FF
3990 +#define SSB_SPROM4_TXPID2G0_SHIFT 0
3991 +#define SSB_SPROM4_TXPID2G1 0xFF00
3992 +#define SSB_SPROM4_TXPID2G1_SHIFT 8
3993 +#define SSB_SPROM4_TXPID2G23 0x0064 /* TX Power Index 2GHz */
3994 +#define SSB_SPROM4_TXPID2G2 0x00FF
3995 +#define SSB_SPROM4_TXPID2G2_SHIFT 0
3996 +#define SSB_SPROM4_TXPID2G3 0xFF00
3997 +#define SSB_SPROM4_TXPID2G3_SHIFT 8
3998 +#define SSB_SPROM4_TXPID5G01 0x0066 /* TX Power Index 5GHz middle subband */
3999 +#define SSB_SPROM4_TXPID5G0 0x00FF
4000 +#define SSB_SPROM4_TXPID5G0_SHIFT 0
4001 +#define SSB_SPROM4_TXPID5G1 0xFF00
4002 +#define SSB_SPROM4_TXPID5G1_SHIFT 8
4003 +#define SSB_SPROM4_TXPID5G23 0x0068 /* TX Power Index 5GHz middle subband */
4004 +#define SSB_SPROM4_TXPID5G2 0x00FF
4005 +#define SSB_SPROM4_TXPID5G2_SHIFT 0
4006 +#define SSB_SPROM4_TXPID5G3 0xFF00
4007 +#define SSB_SPROM4_TXPID5G3_SHIFT 8
4008 +#define SSB_SPROM4_TXPID5GL01 0x006A /* TX Power Index 5GHz low subband */
4009 +#define SSB_SPROM4_TXPID5GL0 0x00FF
4010 +#define SSB_SPROM4_TXPID5GL0_SHIFT 0
4011 +#define SSB_SPROM4_TXPID5GL1 0xFF00
4012 +#define SSB_SPROM4_TXPID5GL1_SHIFT 8
4013 +#define SSB_SPROM4_TXPID5GL23 0x006C /* TX Power Index 5GHz low subband */
4014 +#define SSB_SPROM4_TXPID5GL2 0x00FF
4015 +#define SSB_SPROM4_TXPID5GL2_SHIFT 0
4016 +#define SSB_SPROM4_TXPID5GL3 0xFF00
4017 +#define SSB_SPROM4_TXPID5GL3_SHIFT 8
4018 +#define SSB_SPROM4_TXPID5GH01 0x006E /* TX Power Index 5GHz high subband */
4019 +#define SSB_SPROM4_TXPID5GH0 0x00FF
4020 +#define SSB_SPROM4_TXPID5GH0_SHIFT 0
4021 +#define SSB_SPROM4_TXPID5GH1 0xFF00
4022 +#define SSB_SPROM4_TXPID5GH1_SHIFT 8
4023 +#define SSB_SPROM4_TXPID5GH23 0x0070 /* TX Power Index 5GHz high subband */
4024 +#define SSB_SPROM4_TXPID5GH2 0x00FF
4025 +#define SSB_SPROM4_TXPID5GH2_SHIFT 0
4026 +#define SSB_SPROM4_TXPID5GH3 0xFF00
4027 +#define SSB_SPROM4_TXPID5GH3_SHIFT 8
4028 +#define SSB_SPROM4_MAXP_BG 0x0080 /* Max Power BG in path 1 */
4029 #define SSB_SPROM4_MAXP_BG_MASK 0x00FF /* Mask for Max Power BG */
4030 #define SSB_SPROM4_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
4031 #define SSB_SPROM4_ITSSI_BG_SHIFT 8
4032 -#define SSB_SPROM4_MAXP_A 0x108A /* Max Power A in path 1 */
4033 +#define SSB_SPROM4_MAXP_A 0x008A /* Max Power A in path 1 */
4034 #define SSB_SPROM4_MAXP_A_MASK 0x00FF /* Mask for Max Power A */
4035 #define SSB_SPROM4_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */
4036 #define SSB_SPROM4_ITSSI_A_SHIFT 8
4037 -#define SSB_SPROM4_GPIOA 0x1056 /* Gen. Purpose IO # 0 and 1 */
4038 -#define SSB_SPROM4_GPIOA_P0 0x00FF /* Pin 0 */
4039 -#define SSB_SPROM4_GPIOA_P1 0xFF00 /* Pin 1 */
4040 -#define SSB_SPROM4_GPIOA_P1_SHIFT 8
4041 -#define SSB_SPROM4_GPIOB 0x1058 /* Gen. Purpose IO # 2 and 3 */
4042 -#define SSB_SPROM4_GPIOB_P2 0x00FF /* Pin 2 */
4043 -#define SSB_SPROM4_GPIOB_P3 0xFF00 /* Pin 3 */
4044 -#define SSB_SPROM4_GPIOB_P3_SHIFT 8
4045 -#define SSB_SPROM4_PA0B0 0x1082 /* The paXbY locations are */
4046 -#define SSB_SPROM4_PA0B1 0x1084 /* only guesses */
4047 -#define SSB_SPROM4_PA0B2 0x1086
4048 -#define SSB_SPROM4_PA1B0 0x108E
4049 -#define SSB_SPROM4_PA1B1 0x1090
4050 -#define SSB_SPROM4_PA1B2 0x1092
4051 +#define SSB_SPROM4_PA0B0 0x0082 /* The paXbY locations are */
4052 +#define SSB_SPROM4_PA0B1 0x0084 /* only guesses */
4053 +#define SSB_SPROM4_PA0B2 0x0086
4054 +#define SSB_SPROM4_PA1B0 0x008E
4055 +#define SSB_SPROM4_PA1B1 0x0090
4056 +#define SSB_SPROM4_PA1B2 0x0092
4057
4058 /* SPROM Revision 5 (inherits most data from rev 4) */
4059 -#define SSB_SPROM5_BFLLO 0x104A /* Boardflags (low 16 bits) */
4060 -#define SSB_SPROM5_BFLHI 0x104C /* Board Flags Hi */
4061 -#define SSB_SPROM5_IL0MAC 0x1052 /* 6 byte MAC address for a/b/g/n */
4062 -#define SSB_SPROM5_CCODE 0x1044 /* Country Code (2 bytes) */
4063 -#define SSB_SPROM5_GPIOA 0x1076 /* Gen. Purpose IO # 0 and 1 */
4064 +#define SSB_SPROM5_CCODE 0x0044 /* Country Code (2 bytes) */
4065 +#define SSB_SPROM5_BFLLO 0x004A /* Boardflags (low 16 bits) */
4066 +#define SSB_SPROM5_BFLHI 0x004C /* Board Flags Hi */
4067 +#define SSB_SPROM5_BFL2LO 0x004E /* Board flags 2 (low 16 bits) */
4068 +#define SSB_SPROM5_BFL2HI 0x0050 /* Board flags 2 Hi */
4069 +#define SSB_SPROM5_IL0MAC 0x0052 /* 6 byte MAC address for a/b/g/n */
4070 +#define SSB_SPROM5_GPIOA 0x0076 /* Gen. Purpose IO # 0 and 1 */
4071 #define SSB_SPROM5_GPIOA_P0 0x00FF /* Pin 0 */
4072 #define SSB_SPROM5_GPIOA_P1 0xFF00 /* Pin 1 */
4073 #define SSB_SPROM5_GPIOA_P1_SHIFT 8
4074 -#define SSB_SPROM5_GPIOB 0x1078 /* Gen. Purpose IO # 2 and 3 */
4075 +#define SSB_SPROM5_GPIOB 0x0078 /* Gen. Purpose IO # 2 and 3 */
4076 #define SSB_SPROM5_GPIOB_P2 0x00FF /* Pin 2 */
4077 #define SSB_SPROM5_GPIOB_P3 0xFF00 /* Pin 3 */
4078 #define SSB_SPROM5_GPIOB_P3_SHIFT 8
4079
4080 /* SPROM Revision 8 */
4081 -#define SSB_SPROM8_BFLLO 0x1084 /* Boardflags (low 16 bits) */
4082 -#define SSB_SPROM8_BFLHI 0x1086 /* Boardflags Hi */
4083 -#define SSB_SPROM8_IL0MAC 0x108C /* 6 byte MAC address */
4084 -#define SSB_SPROM8_CCODE 0x1092 /* 2 byte country code */
4085 -#define SSB_SPROM8_ANTAVAIL 0x109C /* Antenna available bitfields*/
4086 -#define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
4087 -#define SSB_SPROM8_ANTAVAIL_A_SHIFT 8
4088 -#define SSB_SPROM8_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */
4089 -#define SSB_SPROM8_ANTAVAIL_BG_SHIFT 0
4090 -#define SSB_SPROM8_AGAIN01 0x109E /* Antenna Gain (in dBm Q5.2) */
4091 +#define SSB_SPROM8_BOARDREV 0x0082 /* Board revision */
4092 +#define SSB_SPROM8_BFLLO 0x0084 /* Board flags (bits 0-15) */
4093 +#define SSB_SPROM8_BFLHI 0x0086 /* Board flags (bits 16-31) */
4094 +#define SSB_SPROM8_BFL2LO 0x0088 /* Board flags (bits 32-47) */
4095 +#define SSB_SPROM8_BFL2HI 0x008A /* Board flags (bits 48-63) */
4096 +#define SSB_SPROM8_IL0MAC 0x008C /* 6 byte MAC address */
4097 +#define SSB_SPROM8_CCODE 0x0092 /* 2 byte country code */
4098 +#define SSB_SPROM8_GPIOA 0x0096 /*Gen. Purpose IO # 0 and 1 */
4099 +#define SSB_SPROM8_GPIOA_P0 0x00FF /* Pin 0 */
4100 +#define SSB_SPROM8_GPIOA_P1 0xFF00 /* Pin 1 */
4101 +#define SSB_SPROM8_GPIOA_P1_SHIFT 8
4102 +#define SSB_SPROM8_GPIOB 0x0098 /* Gen. Purpose IO # 2 and 3 */
4103 +#define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */
4104 +#define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */
4105 +#define SSB_SPROM8_GPIOB_P3_SHIFT 8
4106 +#define SSB_SPROM8_ANTAVAIL 0x009C /* Antenna available bitfields*/
4107 +#define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
4108 +#define SSB_SPROM8_ANTAVAIL_A_SHIFT 8
4109 +#define SSB_SPROM8_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */
4110 +#define SSB_SPROM8_ANTAVAIL_BG_SHIFT 0
4111 +#define SSB_SPROM8_AGAIN01 0x009E /* Antenna Gain (in dBm Q5.2) */
4112 #define SSB_SPROM8_AGAIN0 0x00FF /* Antenna 0 */
4113 #define SSB_SPROM8_AGAIN0_SHIFT 0
4114 #define SSB_SPROM8_AGAIN1 0xFF00 /* Antenna 1 */
4115 #define SSB_SPROM8_AGAIN1_SHIFT 8
4116 -#define SSB_SPROM8_AGAIN23 0x10A0
4117 +#define SSB_SPROM8_AGAIN23 0x00A0
4118 #define SSB_SPROM8_AGAIN2 0x00FF /* Antenna 2 */
4119 #define SSB_SPROM8_AGAIN2_SHIFT 0
4120 #define SSB_SPROM8_AGAIN3 0xFF00 /* Antenna 3 */
4121 #define SSB_SPROM8_AGAIN3_SHIFT 8
4122 -#define SSB_SPROM8_GPIOA 0x1096 /*Gen. Purpose IO # 0 and 1 */
4123 -#define SSB_SPROM8_GPIOA_P0 0x00FF /* Pin 0 */
4124 -#define SSB_SPROM8_GPIOA_P1 0xFF00 /* Pin 1 */
4125 -#define SSB_SPROM8_GPIOA_P1_SHIFT 8
4126 -#define SSB_SPROM8_GPIOB 0x1098 /* Gen. Purpose IO # 2 and 3 */
4127 -#define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */
4128 -#define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */
4129 -#define SSB_SPROM8_GPIOB_P3_SHIFT 8
4130 -#define SSB_SPROM8_MAXP_BG 0x10C0 /* Max Power BG in path 1 */
4131 -#define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power BG */
4132 +#define SSB_SPROM8_RSSIPARM2G 0x00A4 /* RSSI params for 2GHz */
4133 +#define SSB_SPROM8_RSSISMF2G 0x000F
4134 +#define SSB_SPROM8_RSSISMC2G 0x00F0
4135 +#define SSB_SPROM8_RSSISMC2G_SHIFT 4
4136 +#define SSB_SPROM8_RSSISAV2G 0x0700
4137 +#define SSB_SPROM8_RSSISAV2G_SHIFT 8
4138 +#define SSB_SPROM8_BXA2G 0x1800
4139 +#define SSB_SPROM8_BXA2G_SHIFT 11
4140 +#define SSB_SPROM8_RSSIPARM5G 0x00A6 /* RSSI params for 5GHz */
4141 +#define SSB_SPROM8_RSSISMF5G 0x000F
4142 +#define SSB_SPROM8_RSSISMC5G 0x00F0
4143 +#define SSB_SPROM8_RSSISMC5G_SHIFT 4
4144 +#define SSB_SPROM8_RSSISAV5G 0x0700
4145 +#define SSB_SPROM8_RSSISAV5G_SHIFT 8
4146 +#define SSB_SPROM8_BXA5G 0x1800
4147 +#define SSB_SPROM8_BXA5G_SHIFT 11
4148 +#define SSB_SPROM8_TRI25G 0x00A8 /* TX isolation 2.4&5.3GHz */
4149 +#define SSB_SPROM8_TRI2G 0x00FF /* TX isolation 2.4GHz */
4150 +#define SSB_SPROM8_TRI5G 0xFF00 /* TX isolation 5.3GHz */
4151 +#define SSB_SPROM8_TRI5G_SHIFT 8
4152 +#define SSB_SPROM8_TRI5GHL 0x00AA /* TX isolation 5.2/5.8GHz */
4153 +#define SSB_SPROM8_TRI5GL 0x00FF /* TX isolation 5.2GHz */
4154 +#define SSB_SPROM8_TRI5GH 0xFF00 /* TX isolation 5.8GHz */
4155 +#define SSB_SPROM8_TRI5GH_SHIFT 8
4156 +#define SSB_SPROM8_RXPO 0x00AC /* RX power offsets */
4157 +#define SSB_SPROM8_RXPO2G 0x00FF /* 2GHz RX power offset */
4158 +#define SSB_SPROM8_RXPO5G 0xFF00 /* 5GHz RX power offset */
4159 +#define SSB_SPROM8_RXPO5G_SHIFT 8
4160 +#define SSB_SPROM8_FEM2G 0x00AE
4161 +#define SSB_SPROM8_FEM5G 0x00B0
4162 +#define SSB_SROM8_FEM_TSSIPOS 0x0001
4163 +#define SSB_SROM8_FEM_TSSIPOS_SHIFT 0
4164 +#define SSB_SROM8_FEM_EXTPA_GAIN 0x0006
4165 +#define SSB_SROM8_FEM_EXTPA_GAIN_SHIFT 1
4166 +#define SSB_SROM8_FEM_PDET_RANGE 0x00F8
4167 +#define SSB_SROM8_FEM_PDET_RANGE_SHIFT 3
4168 +#define SSB_SROM8_FEM_TR_ISO 0x0700
4169 +#define SSB_SROM8_FEM_TR_ISO_SHIFT 8
4170 +#define SSB_SROM8_FEM_ANTSWLUT 0xF800
4171 +#define SSB_SROM8_FEM_ANTSWLUT_SHIFT 11
4172 +#define SSB_SPROM8_THERMAL 0x00B2
4173 +#define SSB_SPROM8_MPWR_RAWTS 0x00B4
4174 +#define SSB_SPROM8_TS_SLP_OPT_CORRX 0x00B6
4175 +#define SSB_SPROM8_FOC_HWIQ_IQSWP 0x00B8
4176 +#define SSB_SPROM8_PHYCAL_TEMPDELTA 0x00BA
4177 +
4178 +/* There are 4 blocks with power info sharing the same layout */
4179 +#define SSB_SROM8_PWR_INFO_CORE0 0x00C0
4180 +#define SSB_SROM8_PWR_INFO_CORE1 0x00E0
4181 +#define SSB_SROM8_PWR_INFO_CORE2 0x0100
4182 +#define SSB_SROM8_PWR_INFO_CORE3 0x0120
4183 +
4184 +#define SSB_SROM8_2G_MAXP_ITSSI 0x00
4185 +#define SSB_SPROM8_2G_MAXP 0x00FF
4186 +#define SSB_SPROM8_2G_ITSSI 0xFF00
4187 +#define SSB_SPROM8_2G_ITSSI_SHIFT 8
4188 +#define SSB_SROM8_2G_PA_0 0x02 /* 2GHz power amp settings */
4189 +#define SSB_SROM8_2G_PA_1 0x04
4190 +#define SSB_SROM8_2G_PA_2 0x06
4191 +#define SSB_SROM8_5G_MAXP_ITSSI 0x08 /* 5GHz ITSSI and 5.3GHz Max Power */
4192 +#define SSB_SPROM8_5G_MAXP 0x00FF
4193 +#define SSB_SPROM8_5G_ITSSI 0xFF00
4194 +#define SSB_SPROM8_5G_ITSSI_SHIFT 8
4195 +#define SSB_SPROM8_5GHL_MAXP 0x0A /* 5.2GHz and 5.8GHz Max Power */
4196 +#define SSB_SPROM8_5GH_MAXP 0x00FF
4197 +#define SSB_SPROM8_5GL_MAXP 0xFF00
4198 +#define SSB_SPROM8_5GL_MAXP_SHIFT 8
4199 +#define SSB_SROM8_5G_PA_0 0x0C /* 5.3GHz power amp settings */
4200 +#define SSB_SROM8_5G_PA_1 0x0E
4201 +#define SSB_SROM8_5G_PA_2 0x10
4202 +#define SSB_SROM8_5GL_PA_0 0x12 /* 5.2GHz power amp settings */
4203 +#define SSB_SROM8_5GL_PA_1 0x14
4204 +#define SSB_SROM8_5GL_PA_2 0x16
4205 +#define SSB_SROM8_5GH_PA_0 0x18 /* 5.8GHz power amp settings */
4206 +#define SSB_SROM8_5GH_PA_1 0x1A
4207 +#define SSB_SROM8_5GH_PA_2 0x1C
4208 +
4209 +/* TODO: Make it deprecated */
4210 +#define SSB_SPROM8_MAXP_BG 0x00C0 /* Max Power 2GHz in path 1 */
4211 +#define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */
4212 #define SSB_SPROM8_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
4213 #define SSB_SPROM8_ITSSI_BG_SHIFT 8
4214 -#define SSB_SPROM8_MAXP_A 0x10C8 /* Max Power A in path 1 */
4215 -#define SSB_SPROM8_MAXP_A_MASK 0x00FF /* Mask for Max Power A */
4216 +#define SSB_SPROM8_PA0B0 0x00C2 /* 2GHz power amp settings */
4217 +#define SSB_SPROM8_PA0B1 0x00C4
4218 +#define SSB_SPROM8_PA0B2 0x00C6
4219 +#define SSB_SPROM8_MAXP_A 0x00C8 /* Max Power 5.3GHz */
4220 +#define SSB_SPROM8_MAXP_A_MASK 0x00FF /* Mask for Max Power 5.3GHz */
4221 #define SSB_SPROM8_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */
4222 #define SSB_SPROM8_ITSSI_A_SHIFT 8
4223 +#define SSB_SPROM8_MAXP_AHL 0x00CA /* Max Power 5.2/5.8GHz */
4224 +#define SSB_SPROM8_MAXP_AH_MASK 0x00FF /* Mask for Max Power 5.8GHz */
4225 +#define SSB_SPROM8_MAXP_AL_MASK 0xFF00 /* Mask for Max Power 5.2GHz */
4226 +#define SSB_SPROM8_MAXP_AL_SHIFT 8
4227 +#define SSB_SPROM8_PA1B0 0x00CC /* 5.3GHz power amp settings */
4228 +#define SSB_SPROM8_PA1B1 0x00CE
4229 +#define SSB_SPROM8_PA1B2 0x00D0
4230 +#define SSB_SPROM8_PA1LOB0 0x00D2 /* 5.2GHz power amp settings */
4231 +#define SSB_SPROM8_PA1LOB1 0x00D4
4232 +#define SSB_SPROM8_PA1LOB2 0x00D6
4233 +#define SSB_SPROM8_PA1HIB0 0x00D8 /* 5.8GHz power amp settings */
4234 +#define SSB_SPROM8_PA1HIB1 0x00DA
4235 +#define SSB_SPROM8_PA1HIB2 0x00DC
4236 +
4237 +#define SSB_SPROM8_CCK2GPO 0x0140 /* CCK power offset */
4238 +#define SSB_SPROM8_OFDM2GPO 0x0142 /* 2.4GHz OFDM power offset */
4239 +#define SSB_SPROM8_OFDM5GPO 0x0146 /* 5.3GHz OFDM power offset */
4240 +#define SSB_SPROM8_OFDM5GLPO 0x014A /* 5.2GHz OFDM power offset */
4241 +#define SSB_SPROM8_OFDM5GHPO 0x014E /* 5.8GHz OFDM power offset */
4242 +
4243 +/* Values for boardflags_lo read from SPROM */
4244 +#define SSB_BFL_BTCOEXIST 0x0001 /* implements Bluetooth coexistance */
4245 +#define SSB_BFL_PACTRL 0x0002 /* GPIO 9 controlling the PA */
4246 +#define SSB_BFL_AIRLINEMODE 0x0004 /* implements GPIO 13 radio disable indication */
4247 +#define SSB_BFL_RSSI 0x0008 /* software calculates nrssi slope. */
4248 +#define SSB_BFL_ENETSPI 0x0010 /* has ephy roboswitch spi */
4249 +#define SSB_BFL_XTAL_NOSLOW 0x0020 /* no slow clock available */
4250 +#define SSB_BFL_CCKHIPWR 0x0040 /* can do high power CCK transmission */
4251 +#define SSB_BFL_ENETADM 0x0080 /* has ADMtek switch */
4252 +#define SSB_BFL_ENETVLAN 0x0100 /* can do vlan */
4253 +#define SSB_BFL_AFTERBURNER 0x0200 /* supports Afterburner mode */
4254 +#define SSB_BFL_NOPCI 0x0400 /* board leaves PCI floating */
4255 +#define SSB_BFL_FEM 0x0800 /* supports the Front End Module */
4256 +#define SSB_BFL_EXTLNA 0x1000 /* has an external LNA */
4257 +#define SSB_BFL_HGPA 0x2000 /* had high gain PA */
4258 +#define SSB_BFL_BTCMOD 0x4000 /* BFL_BTCOEXIST is given in alternate GPIOs */
4259 +#define SSB_BFL_ALTIQ 0x8000 /* alternate I/Q settings */
4260 +
4261 +/* Values for boardflags_hi read from SPROM */
4262 +#define SSB_BFH_NOPA 0x0001 /* has no PA */
4263 +#define SSB_BFH_RSSIINV 0x0002 /* RSSI uses positive slope (not TSSI) */
4264 +#define SSB_BFH_PAREF 0x0004 /* uses the PARef LDO */
4265 +#define SSB_BFH_3TSWITCH 0x0008 /* uses a triple throw switch shared with bluetooth */
4266 +#define SSB_BFH_PHASESHIFT 0x0010 /* can support phase shifter */
4267 +#define SSB_BFH_BUCKBOOST 0x0020 /* has buck/booster */
4268 +#define SSB_BFH_FEM_BT 0x0040 /* has FEM and switch to share antenna with bluetooth */
4269 +
4270 +/* Values for boardflags2_lo read from SPROM */
4271 +#define SSB_BFL2_RXBB_INT_REG_DIS 0x0001 /* external RX BB regulator present */
4272 +#define SSB_BFL2_APLL_WAR 0x0002 /* alternative A-band PLL settings implemented */
4273 +#define SSB_BFL2_TXPWRCTRL_EN 0x0004 /* permits enabling TX Power Control */
4274 +#define SSB_BFL2_2X4_DIV 0x0008 /* 2x4 diversity switch */
4275 +#define SSB_BFL2_5G_PWRGAIN 0x0010 /* supports 5G band power gain */
4276 +#define SSB_BFL2_PCIEWAR_OVR 0x0020 /* overrides ASPM and Clkreq settings */
4277 +#define SSB_BFL2_CAESERS_BRD 0x0040 /* is Caesers board (unused) */
4278 +#define SSB_BFL2_BTC3WIRE 0x0080 /* used 3-wire bluetooth coexist */
4279 +#define SSB_BFL2_SKWRKFEM_BRD 0x0100 /* 4321mcm93 uses Skyworks FEM */
4280 +#define SSB_BFL2_SPUR_WAR 0x0200 /* has a workaround for clock-harmonic spurs */
4281 +#define SSB_BFL2_GPLL_WAR 0x0400 /* altenative G-band PLL settings implemented */
4282
4283 /* Values for SSB_SPROM1_BINF_CCODE */
4284 enum {
4285 --- a/drivers/ssb/driver_extif.c
4286 +++ b/drivers/ssb/driver_extif.c
4287 @@ -3,7 +3,7 @@
4288 * Broadcom EXTIF core driver
4289 *
4290 * Copyright 2005, Broadcom Corporation
4291 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
4292 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
4293 * Copyright 2006, 2007, Felix Fietkau <nbd@openwrt.org>
4294 * Copyright 2007, Aurelien Jarno <aurelien@aurel32.net>
4295 *
4296 --- a/drivers/ssb/embedded.c
4297 +++ b/drivers/ssb/embedded.c
4298 @@ -3,7 +3,7 @@
4299 * Embedded systems support code
4300 *
4301 * Copyright 2005-2008, Broadcom Corporation
4302 - * Copyright 2006-2008, Michael Buesch <mb@bu3sch.de>
4303 + * Copyright 2006-2008, Michael Buesch <m@bues.ch>
4304 *
4305 * Licensed under the GNU/GPL. See COPYING for details.
4306 */
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