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linux/2.6.37: R.I.P.
[openwrt/staging/wigyori.git] / target / linux / generic / patches-2.6.38 / 020-ssb_update.patch
1 --- a/drivers/ssb/main.c
2 +++ b/drivers/ssb/main.c
3 @@ -3,7 +3,7 @@
4 * Subsystem core
5 *
6 * Copyright 2005, Broadcom Corporation
7 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
8 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
9 *
10 * Licensed under the GNU/GPL. See COPYING for details.
11 */
12 @@ -12,6 +12,7 @@
13
14 #include <linux/delay.h>
15 #include <linux/io.h>
16 +#include <linux/module.h>
17 #include <linux/ssb/ssb.h>
18 #include <linux/ssb/ssb_regs.h>
19 #include <linux/ssb/ssb_driver_gige.h>
20 @@ -139,19 +140,6 @@ static void ssb_device_put(struct ssb_de
21 put_device(dev->dev);
22 }
23
24 -static inline struct ssb_driver *ssb_driver_get(struct ssb_driver *drv)
25 -{
26 - if (drv)
27 - get_driver(&drv->drv);
28 - return drv;
29 -}
30 -
31 -static inline void ssb_driver_put(struct ssb_driver *drv)
32 -{
33 - if (drv)
34 - put_driver(&drv->drv);
35 -}
36 -
37 static int ssb_device_resume(struct device *dev)
38 {
39 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
40 @@ -249,11 +237,9 @@ int ssb_devices_freeze(struct ssb_bus *b
41 ssb_device_put(sdev);
42 continue;
43 }
44 - sdrv = ssb_driver_get(drv_to_ssb_drv(sdev->dev->driver));
45 - if (!sdrv || SSB_WARN_ON(!sdrv->remove)) {
46 - ssb_device_put(sdev);
47 + sdrv = drv_to_ssb_drv(sdev->dev->driver);
48 + if (SSB_WARN_ON(!sdrv->remove))
49 continue;
50 - }
51 sdrv->remove(sdev);
52 ctx->device_frozen[i] = 1;
53 }
54 @@ -292,7 +278,6 @@ int ssb_devices_thaw(struct ssb_freeze_c
55 dev_name(sdev->dev));
56 result = err;
57 }
58 - ssb_driver_put(sdrv);
59 ssb_device_put(sdev);
60 }
61
62 @@ -557,7 +542,7 @@ error:
63 }
64
65 /* Needs ssb_buses_lock() */
66 -static int ssb_attach_queued_buses(void)
67 +static int __devinit ssb_attach_queued_buses(void)
68 {
69 struct ssb_bus *bus, *n;
70 int err = 0;
71 @@ -768,9 +753,9 @@ out:
72 return err;
73 }
74
75 -static int ssb_bus_register(struct ssb_bus *bus,
76 - ssb_invariants_func_t get_invariants,
77 - unsigned long baseaddr)
78 +static int __devinit ssb_bus_register(struct ssb_bus *bus,
79 + ssb_invariants_func_t get_invariants,
80 + unsigned long baseaddr)
81 {
82 int err;
83
84 @@ -851,8 +836,8 @@ err_disable_xtal:
85 }
86
87 #ifdef CONFIG_SSB_PCIHOST
88 -int ssb_bus_pcibus_register(struct ssb_bus *bus,
89 - struct pci_dev *host_pci)
90 +int __devinit ssb_bus_pcibus_register(struct ssb_bus *bus,
91 + struct pci_dev *host_pci)
92 {
93 int err;
94
95 @@ -875,9 +860,9 @@ EXPORT_SYMBOL(ssb_bus_pcibus_register);
96 #endif /* CONFIG_SSB_PCIHOST */
97
98 #ifdef CONFIG_SSB_PCMCIAHOST
99 -int ssb_bus_pcmciabus_register(struct ssb_bus *bus,
100 - struct pcmcia_device *pcmcia_dev,
101 - unsigned long baseaddr)
102 +int __devinit ssb_bus_pcmciabus_register(struct ssb_bus *bus,
103 + struct pcmcia_device *pcmcia_dev,
104 + unsigned long baseaddr)
105 {
106 int err;
107
108 @@ -897,8 +882,9 @@ EXPORT_SYMBOL(ssb_bus_pcmciabus_register
109 #endif /* CONFIG_SSB_PCMCIAHOST */
110
111 #ifdef CONFIG_SSB_SDIOHOST
112 -int ssb_bus_sdiobus_register(struct ssb_bus *bus, struct sdio_func *func,
113 - unsigned int quirks)
114 +int __devinit ssb_bus_sdiobus_register(struct ssb_bus *bus,
115 + struct sdio_func *func,
116 + unsigned int quirks)
117 {
118 int err;
119
120 @@ -918,9 +904,9 @@ int ssb_bus_sdiobus_register(struct ssb_
121 EXPORT_SYMBOL(ssb_bus_sdiobus_register);
122 #endif /* CONFIG_SSB_PCMCIAHOST */
123
124 -int ssb_bus_ssbbus_register(struct ssb_bus *bus,
125 - unsigned long baseaddr,
126 - ssb_invariants_func_t get_invariants)
127 +int __devinit ssb_bus_ssbbus_register(struct ssb_bus *bus,
128 + unsigned long baseaddr,
129 + ssb_invariants_func_t get_invariants)
130 {
131 int err;
132
133 @@ -1001,8 +987,8 @@ u32 ssb_calc_clock_rate(u32 plltype, u32
134 switch (plltype) {
135 case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
136 if (m & SSB_CHIPCO_CLK_T6_MMASK)
137 - return SSB_CHIPCO_CLK_T6_M0;
138 - return SSB_CHIPCO_CLK_T6_M1;
139 + return SSB_CHIPCO_CLK_T6_M1;
140 + return SSB_CHIPCO_CLK_T6_M0;
141 case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
142 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
143 case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
144 @@ -1092,6 +1078,9 @@ u32 ssb_clockspeed(struct ssb_bus *bus)
145 u32 plltype;
146 u32 clkctl_n, clkctl_m;
147
148 + if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
149 + return ssb_pmu_get_controlclock(&bus->chipco);
150 +
151 if (ssb_extif_available(&bus->extif))
152 ssb_extif_get_clockcontrol(&bus->extif, &plltype,
153 &clkctl_n, &clkctl_m);
154 @@ -1117,23 +1106,22 @@ static u32 ssb_tmslow_reject_bitmask(str
155 {
156 u32 rev = ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_SSBREV;
157
158 - /* The REJECT bit changed position in TMSLOW between
159 - * Backplane revisions. */
160 + /* The REJECT bit seems to be different for Backplane rev 2.3 */
161 switch (rev) {
162 case SSB_IDLOW_SSBREV_22:
163 - return SSB_TMSLOW_REJECT_22;
164 + case SSB_IDLOW_SSBREV_24:
165 + case SSB_IDLOW_SSBREV_26:
166 + return SSB_TMSLOW_REJECT;
167 case SSB_IDLOW_SSBREV_23:
168 return SSB_TMSLOW_REJECT_23;
169 - case SSB_IDLOW_SSBREV_24: /* TODO - find the proper REJECT bits */
170 - case SSB_IDLOW_SSBREV_25: /* same here */
171 - case SSB_IDLOW_SSBREV_26: /* same here */
172 + case SSB_IDLOW_SSBREV_25: /* TODO - find the proper REJECT bit */
173 case SSB_IDLOW_SSBREV_27: /* same here */
174 - return SSB_TMSLOW_REJECT_23; /* this is a guess */
175 + return SSB_TMSLOW_REJECT; /* this is a guess */
176 default:
177 printk(KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
178 WARN_ON(1);
179 }
180 - return (SSB_TMSLOW_REJECT_22 | SSB_TMSLOW_REJECT_23);
181 + return (SSB_TMSLOW_REJECT | SSB_TMSLOW_REJECT_23);
182 }
183
184 int ssb_device_is_enabled(struct ssb_device *dev)
185 @@ -1192,10 +1180,10 @@ void ssb_device_enable(struct ssb_device
186 }
187 EXPORT_SYMBOL(ssb_device_enable);
188
189 -/* Wait for a bit in a register to get set or unset.
190 +/* Wait for bitmask in a register to get set or cleared.
191 * timeout is in units of ten-microseconds */
192 -static int ssb_wait_bit(struct ssb_device *dev, u16 reg, u32 bitmask,
193 - int timeout, int set)
194 +static int ssb_wait_bits(struct ssb_device *dev, u16 reg, u32 bitmask,
195 + int timeout, int set)
196 {
197 int i;
198 u32 val;
199 @@ -1203,7 +1191,7 @@ static int ssb_wait_bit(struct ssb_devic
200 for (i = 0; i < timeout; i++) {
201 val = ssb_read32(dev, reg);
202 if (set) {
203 - if (val & bitmask)
204 + if ((val & bitmask) == bitmask)
205 return 0;
206 } else {
207 if (!(val & bitmask))
208 @@ -1220,20 +1208,38 @@ static int ssb_wait_bit(struct ssb_devic
209
210 void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags)
211 {
212 - u32 reject;
213 + u32 reject, val;
214
215 if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_RESET)
216 return;
217
218 reject = ssb_tmslow_reject_bitmask(dev);
219 - ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK);
220 - ssb_wait_bit(dev, SSB_TMSLOW, reject, 1000, 1);
221 - ssb_wait_bit(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
222 - ssb_write32(dev, SSB_TMSLOW,
223 - SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
224 - reject | SSB_TMSLOW_RESET |
225 - core_specific_flags);
226 - ssb_flush_tmslow(dev);
227 +
228 + if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_CLOCK) {
229 + ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK);
230 + ssb_wait_bits(dev, SSB_TMSLOW, reject, 1000, 1);
231 + ssb_wait_bits(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
232 +
233 + if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
234 + val = ssb_read32(dev, SSB_IMSTATE);
235 + val |= SSB_IMSTATE_REJECT;
236 + ssb_write32(dev, SSB_IMSTATE, val);
237 + ssb_wait_bits(dev, SSB_IMSTATE, SSB_IMSTATE_BUSY, 1000,
238 + 0);
239 + }
240 +
241 + ssb_write32(dev, SSB_TMSLOW,
242 + SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
243 + reject | SSB_TMSLOW_RESET |
244 + core_specific_flags);
245 + ssb_flush_tmslow(dev);
246 +
247 + if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
248 + val = ssb_read32(dev, SSB_IMSTATE);
249 + val &= ~SSB_IMSTATE_REJECT;
250 + ssb_write32(dev, SSB_IMSTATE, val);
251 + }
252 + }
253
254 ssb_write32(dev, SSB_TMSLOW,
255 reject | SSB_TMSLOW_RESET |
256 @@ -1242,13 +1248,34 @@ void ssb_device_disable(struct ssb_devic
257 }
258 EXPORT_SYMBOL(ssb_device_disable);
259
260 +/* Some chipsets need routing known for PCIe and 64-bit DMA */
261 +static bool ssb_dma_translation_special_bit(struct ssb_device *dev)
262 +{
263 + u16 chip_id = dev->bus->chip_id;
264 +
265 + if (dev->id.coreid == SSB_DEV_80211) {
266 + return (chip_id == 0x4322 || chip_id == 43221 ||
267 + chip_id == 43231 || chip_id == 43222);
268 + }
269 +
270 + return 0;
271 +}
272 +
273 u32 ssb_dma_translation(struct ssb_device *dev)
274 {
275 switch (dev->bus->bustype) {
276 case SSB_BUSTYPE_SSB:
277 return 0;
278 case SSB_BUSTYPE_PCI:
279 - return SSB_PCI_DMA;
280 + if (pci_is_pcie(dev->bus->host_pci) &&
281 + ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_DMA64) {
282 + return SSB_PCIE_DMA_H32;
283 + } else {
284 + if (ssb_dma_translation_special_bit(dev))
285 + return SSB_PCIE_DMA_H32;
286 + else
287 + return SSB_PCI_DMA;
288 + }
289 default:
290 __ssb_dma_not_implemented(dev);
291 }
292 @@ -1291,20 +1318,20 @@ EXPORT_SYMBOL(ssb_bus_may_powerdown);
293
294 int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl)
295 {
296 - struct ssb_chipcommon *cc;
297 int err;
298 enum ssb_clkmode mode;
299
300 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
301 if (err)
302 goto error;
303 - cc = &bus->chipco;
304 - mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
305 - ssb_chipco_set_clockmode(cc, mode);
306
307 #ifdef CONFIG_SSB_DEBUG
308 bus->powered_up = 1;
309 #endif
310 +
311 + mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
312 + ssb_chipco_set_clockmode(&bus->chipco, mode);
313 +
314 return 0;
315 error:
316 ssb_printk(KERN_ERR PFX "Bus powerup failed\n");
317 @@ -1312,6 +1339,37 @@ error:
318 }
319 EXPORT_SYMBOL(ssb_bus_powerup);
320
321 +static void ssb_broadcast_value(struct ssb_device *dev,
322 + u32 address, u32 data)
323 +{
324 +#ifdef CONFIG_SSB_DRIVER_PCICORE
325 + /* This is used for both, PCI and ChipCommon core, so be careful. */
326 + BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
327 + BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
328 +#endif
329 +
330 + ssb_write32(dev, SSB_CHIPCO_BCAST_ADDR, address);
331 + ssb_read32(dev, SSB_CHIPCO_BCAST_ADDR); /* flush */
332 + ssb_write32(dev, SSB_CHIPCO_BCAST_DATA, data);
333 + ssb_read32(dev, SSB_CHIPCO_BCAST_DATA); /* flush */
334 +}
335 +
336 +void ssb_commit_settings(struct ssb_bus *bus)
337 +{
338 + struct ssb_device *dev;
339 +
340 +#ifdef CONFIG_SSB_DRIVER_PCICORE
341 + dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
342 +#else
343 + dev = bus->chipco.dev;
344 +#endif
345 + if (WARN_ON(!dev))
346 + return;
347 + /* This forces an update of the cached registers. */
348 + ssb_broadcast_value(dev, 0xFD8, 0);
349 +}
350 +EXPORT_SYMBOL(ssb_commit_settings);
351 +
352 u32 ssb_admatch_base(u32 adm)
353 {
354 u32 base = 0;
355 --- a/drivers/ssb/pci.c
356 +++ b/drivers/ssb/pci.c
357 @@ -1,7 +1,7 @@
358 /*
359 * Sonics Silicon Backplane PCI-Hostbus related functions.
360 *
361 - * Copyright (C) 2005-2006 Michael Buesch <mb@bu3sch.de>
362 + * Copyright (C) 2005-2006 Michael Buesch <m@bues.ch>
363 * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
364 * Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
365 * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
366 @@ -331,7 +331,6 @@ static void sprom_extract_r123(struct ss
367 {
368 int i;
369 u16 v;
370 - s8 gain;
371 u16 loc[3];
372
373 if (out->revision == 3) /* rev 3 moved MAC */
374 @@ -390,20 +389,12 @@ static void sprom_extract_r123(struct ss
375 SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0);
376
377 /* Extract the antenna gain values. */
378 - gain = r123_extract_antgain(out->revision, in,
379 - SSB_SPROM1_AGAIN_BG,
380 - SSB_SPROM1_AGAIN_BG_SHIFT);
381 - out->antenna_gain.ghz24.a0 = gain;
382 - out->antenna_gain.ghz24.a1 = gain;
383 - out->antenna_gain.ghz24.a2 = gain;
384 - out->antenna_gain.ghz24.a3 = gain;
385 - gain = r123_extract_antgain(out->revision, in,
386 - SSB_SPROM1_AGAIN_A,
387 - SSB_SPROM1_AGAIN_A_SHIFT);
388 - out->antenna_gain.ghz5.a0 = gain;
389 - out->antenna_gain.ghz5.a1 = gain;
390 - out->antenna_gain.ghz5.a2 = gain;
391 - out->antenna_gain.ghz5.a3 = gain;
392 + out->antenna_gain.a0 = r123_extract_antgain(out->revision, in,
393 + SSB_SPROM1_AGAIN_BG,
394 + SSB_SPROM1_AGAIN_BG_SHIFT);
395 + out->antenna_gain.a1 = r123_extract_antgain(out->revision, in,
396 + SSB_SPROM1_AGAIN_A,
397 + SSB_SPROM1_AGAIN_A_SHIFT);
398 }
399
400 /* Revs 4 5 and 8 have partially shared layout */
401 @@ -468,10 +459,14 @@ static void sprom_extract_r45(struct ssb
402 SPEX(country_code, SSB_SPROM4_CCODE, 0xFFFF, 0);
403 SPEX(boardflags_lo, SSB_SPROM4_BFLLO, 0xFFFF, 0);
404 SPEX(boardflags_hi, SSB_SPROM4_BFLHI, 0xFFFF, 0);
405 + SPEX(boardflags2_lo, SSB_SPROM4_BFL2LO, 0xFFFF, 0);
406 + SPEX(boardflags2_hi, SSB_SPROM4_BFL2HI, 0xFFFF, 0);
407 } else {
408 SPEX(country_code, SSB_SPROM5_CCODE, 0xFFFF, 0);
409 SPEX(boardflags_lo, SSB_SPROM5_BFLLO, 0xFFFF, 0);
410 SPEX(boardflags_hi, SSB_SPROM5_BFLHI, 0xFFFF, 0);
411 + SPEX(boardflags2_lo, SSB_SPROM5_BFL2LO, 0xFFFF, 0);
412 + SPEX(boardflags2_hi, SSB_SPROM5_BFL2HI, 0xFFFF, 0);
413 }
414 SPEX(ant_available_a, SSB_SPROM4_ANTAVAIL, SSB_SPROM4_ANTAVAIL_A,
415 SSB_SPROM4_ANTAVAIL_A_SHIFT);
416 @@ -500,16 +495,14 @@ static void sprom_extract_r45(struct ssb
417 }
418
419 /* Extract the antenna gain values. */
420 - SPEX(antenna_gain.ghz24.a0, SSB_SPROM4_AGAIN01,
421 + SPEX(antenna_gain.a0, SSB_SPROM4_AGAIN01,
422 SSB_SPROM4_AGAIN0, SSB_SPROM4_AGAIN0_SHIFT);
423 - SPEX(antenna_gain.ghz24.a1, SSB_SPROM4_AGAIN01,
424 + SPEX(antenna_gain.a1, SSB_SPROM4_AGAIN01,
425 SSB_SPROM4_AGAIN1, SSB_SPROM4_AGAIN1_SHIFT);
426 - SPEX(antenna_gain.ghz24.a2, SSB_SPROM4_AGAIN23,
427 + SPEX(antenna_gain.a2, SSB_SPROM4_AGAIN23,
428 SSB_SPROM4_AGAIN2, SSB_SPROM4_AGAIN2_SHIFT);
429 - SPEX(antenna_gain.ghz24.a3, SSB_SPROM4_AGAIN23,
430 + SPEX(antenna_gain.a3, SSB_SPROM4_AGAIN23,
431 SSB_SPROM4_AGAIN3, SSB_SPROM4_AGAIN3_SHIFT);
432 - memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
433 - sizeof(out->antenna_gain.ghz5));
434
435 sprom_extract_r458(out, in);
436
437 @@ -519,7 +512,13 @@ static void sprom_extract_r45(struct ssb
438 static void sprom_extract_r8(struct ssb_sprom *out, const u16 *in)
439 {
440 int i;
441 - u16 v;
442 + u16 v, o;
443 + u16 pwr_info_offset[] = {
444 + SSB_SROM8_PWR_INFO_CORE0, SSB_SROM8_PWR_INFO_CORE1,
445 + SSB_SROM8_PWR_INFO_CORE2, SSB_SROM8_PWR_INFO_CORE3
446 + };
447 + BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
448 + ARRAY_SIZE(out->core_pwr_info));
449
450 /* extract the MAC address */
451 for (i = 0; i < 3; i++) {
452 @@ -592,16 +591,69 @@ static void sprom_extract_r8(struct ssb_
453 SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, 0xFFFFFFFF, 0);
454
455 /* Extract the antenna gain values. */
456 - SPEX(antenna_gain.ghz24.a0, SSB_SPROM8_AGAIN01,
457 + SPEX(antenna_gain.a0, SSB_SPROM8_AGAIN01,
458 SSB_SPROM8_AGAIN0, SSB_SPROM8_AGAIN0_SHIFT);
459 - SPEX(antenna_gain.ghz24.a1, SSB_SPROM8_AGAIN01,
460 + SPEX(antenna_gain.a1, SSB_SPROM8_AGAIN01,
461 SSB_SPROM8_AGAIN1, SSB_SPROM8_AGAIN1_SHIFT);
462 - SPEX(antenna_gain.ghz24.a2, SSB_SPROM8_AGAIN23,
463 + SPEX(antenna_gain.a2, SSB_SPROM8_AGAIN23,
464 SSB_SPROM8_AGAIN2, SSB_SPROM8_AGAIN2_SHIFT);
465 - SPEX(antenna_gain.ghz24.a3, SSB_SPROM8_AGAIN23,
466 + SPEX(antenna_gain.a3, SSB_SPROM8_AGAIN23,
467 SSB_SPROM8_AGAIN3, SSB_SPROM8_AGAIN3_SHIFT);
468 - memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
469 - sizeof(out->antenna_gain.ghz5));
470 +
471 + /* Extract cores power info info */
472 + for (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) {
473 + o = pwr_info_offset[i];
474 + SPEX(core_pwr_info[i].itssi_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
475 + SSB_SPROM8_2G_ITSSI, SSB_SPROM8_2G_ITSSI_SHIFT);
476 + SPEX(core_pwr_info[i].maxpwr_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
477 + SSB_SPROM8_2G_MAXP, 0);
478 +
479 + SPEX(core_pwr_info[i].pa_2g[0], o + SSB_SROM8_2G_PA_0, ~0, 0);
480 + SPEX(core_pwr_info[i].pa_2g[1], o + SSB_SROM8_2G_PA_1, ~0, 0);
481 + SPEX(core_pwr_info[i].pa_2g[2], o + SSB_SROM8_2G_PA_2, ~0, 0);
482 +
483 + SPEX(core_pwr_info[i].itssi_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
484 + SSB_SPROM8_5G_ITSSI, SSB_SPROM8_5G_ITSSI_SHIFT);
485 + SPEX(core_pwr_info[i].maxpwr_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
486 + SSB_SPROM8_5G_MAXP, 0);
487 + SPEX(core_pwr_info[i].maxpwr_5gh, o + SSB_SPROM8_5GHL_MAXP,
488 + SSB_SPROM8_5GH_MAXP, 0);
489 + SPEX(core_pwr_info[i].maxpwr_5gl, o + SSB_SPROM8_5GHL_MAXP,
490 + SSB_SPROM8_5GL_MAXP, SSB_SPROM8_5GL_MAXP_SHIFT);
491 +
492 + SPEX(core_pwr_info[i].pa_5gl[0], o + SSB_SROM8_5GL_PA_0, ~0, 0);
493 + SPEX(core_pwr_info[i].pa_5gl[1], o + SSB_SROM8_5GL_PA_1, ~0, 0);
494 + SPEX(core_pwr_info[i].pa_5gl[2], o + SSB_SROM8_5GL_PA_2, ~0, 0);
495 + SPEX(core_pwr_info[i].pa_5g[0], o + SSB_SROM8_5G_PA_0, ~0, 0);
496 + SPEX(core_pwr_info[i].pa_5g[1], o + SSB_SROM8_5G_PA_1, ~0, 0);
497 + SPEX(core_pwr_info[i].pa_5g[2], o + SSB_SROM8_5G_PA_2, ~0, 0);
498 + SPEX(core_pwr_info[i].pa_5gh[0], o + SSB_SROM8_5GH_PA_0, ~0, 0);
499 + SPEX(core_pwr_info[i].pa_5gh[1], o + SSB_SROM8_5GH_PA_1, ~0, 0);
500 + SPEX(core_pwr_info[i].pa_5gh[2], o + SSB_SROM8_5GH_PA_2, ~0, 0);
501 + }
502 +
503 + /* Extract FEM info */
504 + SPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G,
505 + SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
506 + SPEX(fem.ghz2.extpa_gain, SSB_SPROM8_FEM2G,
507 + SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
508 + SPEX(fem.ghz2.pdet_range, SSB_SPROM8_FEM2G,
509 + SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);
510 + SPEX(fem.ghz2.tr_iso, SSB_SPROM8_FEM2G,
511 + SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);
512 + SPEX(fem.ghz2.antswlut, SSB_SPROM8_FEM2G,
513 + SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
514 +
515 + SPEX(fem.ghz5.tssipos, SSB_SPROM8_FEM5G,
516 + SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
517 + SPEX(fem.ghz5.extpa_gain, SSB_SPROM8_FEM5G,
518 + SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
519 + SPEX(fem.ghz5.pdet_range, SSB_SPROM8_FEM5G,
520 + SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);
521 + SPEX(fem.ghz5.tr_iso, SSB_SPROM8_FEM5G,
522 + SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);
523 + SPEX(fem.ghz5.antswlut, SSB_SPROM8_FEM5G,
524 + SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
525
526 sprom_extract_r458(out, in);
527
528 @@ -641,7 +693,7 @@ static int sprom_extract(struct ssb_bus
529 break;
530 default:
531 ssb_printk(KERN_WARNING PFX "Unsupported SPROM"
532 - " revision %d detected. Will extract"
533 + " revision %d detected. Will extract"
534 " v1\n", out->revision);
535 out->revision = 1;
536 sprom_extract_r123(out, in);
537 @@ -658,7 +710,6 @@ static int sprom_extract(struct ssb_bus
538 static int ssb_pci_sprom_get(struct ssb_bus *bus,
539 struct ssb_sprom *sprom)
540 {
541 - const struct ssb_sprom *fallback;
542 int err;
543 u16 *buf;
544
545 @@ -666,7 +717,7 @@ static int ssb_pci_sprom_get(struct ssb_
546 ssb_printk(KERN_ERR PFX "No SPROM available!\n");
547 return -ENODEV;
548 }
549 - if (bus->chipco.dev) { /* can be unavailible! */
550 + if (bus->chipco.dev) { /* can be unavailable! */
551 /*
552 * get SPROM offset: SSB_SPROM_BASE1 except for
553 * chipcommon rev >= 31 or chip ID is 0x4312 and
554 @@ -703,10 +754,17 @@ static int ssb_pci_sprom_get(struct ssb_
555 if (err) {
556 /* All CRC attempts failed.
557 * Maybe there is no SPROM on the device?
558 - * If we have a fallback, use that. */
559 - fallback = ssb_get_fallback_sprom();
560 - if (fallback) {
561 - memcpy(sprom, fallback, sizeof(*sprom));
562 + * Now we ask the arch code if there is some sprom
563 + * available for this device in some other storage */
564 + err = ssb_fill_sprom_with_fallback(bus, sprom);
565 + if (err) {
566 + ssb_printk(KERN_WARNING PFX "WARNING: Using"
567 + " fallback SPROM failed (err %d)\n",
568 + err);
569 + } else {
570 + ssb_dprintk(KERN_DEBUG PFX "Using SPROM"
571 + " revision %d provided by"
572 + " platform.\n", sprom->revision);
573 err = 0;
574 goto out_free;
575 }
576 @@ -724,12 +782,9 @@ out_free:
577 static void ssb_pci_get_boardinfo(struct ssb_bus *bus,
578 struct ssb_boardinfo *bi)
579 {
580 - pci_read_config_word(bus->host_pci, PCI_SUBSYSTEM_VENDOR_ID,
581 - &bi->vendor);
582 - pci_read_config_word(bus->host_pci, PCI_SUBSYSTEM_ID,
583 - &bi->type);
584 - pci_read_config_word(bus->host_pci, PCI_REVISION_ID,
585 - &bi->rev);
586 + bi->vendor = bus->host_pci->subsystem_vendor;
587 + bi->type = bus->host_pci->subsystem_device;
588 + bi->rev = bus->host_pci->revision;
589 }
590
591 int ssb_pci_get_invariants(struct ssb_bus *bus,
592 --- a/include/linux/ssb/ssb_regs.h
593 +++ b/include/linux/ssb/ssb_regs.h
594 @@ -85,6 +85,8 @@
595 #define SSB_IMSTATE_AP_RSV 0x00000030 /* Reserved */
596 #define SSB_IMSTATE_IBE 0x00020000 /* In Band Error */
597 #define SSB_IMSTATE_TO 0x00040000 /* Timeout */
598 +#define SSB_IMSTATE_BUSY 0x01800000 /* Busy (Backplane rev >= 2.3 only) */
599 +#define SSB_IMSTATE_REJECT 0x02000000 /* Reject (Backplane rev >= 2.3 only) */
600 #define SSB_INTVEC 0x0F94 /* SB Interrupt Mask */
601 #define SSB_INTVEC_PCI 0x00000001 /* Enable interrupts for PCI */
602 #define SSB_INTVEC_ENET0 0x00000002 /* Enable interrupts for enet 0 */
603 @@ -95,9 +97,8 @@
604 #define SSB_INTVEC_ENET1 0x00000040 /* Enable interrupts for enet 1 */
605 #define SSB_TMSLOW 0x0F98 /* SB Target State Low */
606 #define SSB_TMSLOW_RESET 0x00000001 /* Reset */
607 -#define SSB_TMSLOW_REJECT_22 0x00000002 /* Reject (Backplane rev 2.2) */
608 +#define SSB_TMSLOW_REJECT 0x00000002 /* Reject (Standard Backplane) */
609 #define SSB_TMSLOW_REJECT_23 0x00000004 /* Reject (Backplane rev 2.3) */
610 -#define SSB_TMSLOW_PHYCLK 0x00000010 /* MAC PHY Clock Control Enable */
611 #define SSB_TMSLOW_CLOCK 0x00010000 /* Clock Enable */
612 #define SSB_TMSLOW_FGC 0x00020000 /* Force Gated Clocks On */
613 #define SSB_TMSLOW_PE 0x40000000 /* Power Management Enable */
614 @@ -268,6 +269,8 @@
615 /* SPROM Revision 4 */
616 #define SSB_SPROM4_BFLLO 0x0044 /* Boardflags (low 16 bits) */
617 #define SSB_SPROM4_BFLHI 0x0046 /* Board Flags Hi */
618 +#define SSB_SPROM4_BFL2LO 0x0048 /* Board flags 2 (low 16 bits) */
619 +#define SSB_SPROM4_BFL2HI 0x004A /* Board flags 2 Hi */
620 #define SSB_SPROM4_IL0MAC 0x004C /* 6 byte MAC address for a/b/g/n */
621 #define SSB_SPROM4_CCODE 0x0052 /* Country Code (2 bytes) */
622 #define SSB_SPROM4_GPIOA 0x0056 /* Gen. Purpose IO # 0 and 1 */
623 @@ -358,6 +361,8 @@
624 #define SSB_SPROM5_CCODE 0x0044 /* Country Code (2 bytes) */
625 #define SSB_SPROM5_BFLLO 0x004A /* Boardflags (low 16 bits) */
626 #define SSB_SPROM5_BFLHI 0x004C /* Board Flags Hi */
627 +#define SSB_SPROM5_BFL2LO 0x004E /* Board flags 2 (low 16 bits) */
628 +#define SSB_SPROM5_BFL2HI 0x0050 /* Board flags 2 Hi */
629 #define SSB_SPROM5_IL0MAC 0x0052 /* 6 byte MAC address for a/b/g/n */
630 #define SSB_SPROM5_GPIOA 0x0076 /* Gen. Purpose IO # 0 and 1 */
631 #define SSB_SPROM5_GPIOA_P0 0x00FF /* Pin 0 */
632 @@ -427,6 +432,56 @@
633 #define SSB_SPROM8_RXPO2G 0x00FF /* 2GHz RX power offset */
634 #define SSB_SPROM8_RXPO5G 0xFF00 /* 5GHz RX power offset */
635 #define SSB_SPROM8_RXPO5G_SHIFT 8
636 +#define SSB_SPROM8_FEM2G 0x00AE
637 +#define SSB_SPROM8_FEM5G 0x00B0
638 +#define SSB_SROM8_FEM_TSSIPOS 0x0001
639 +#define SSB_SROM8_FEM_TSSIPOS_SHIFT 0
640 +#define SSB_SROM8_FEM_EXTPA_GAIN 0x0006
641 +#define SSB_SROM8_FEM_EXTPA_GAIN_SHIFT 1
642 +#define SSB_SROM8_FEM_PDET_RANGE 0x00F8
643 +#define SSB_SROM8_FEM_PDET_RANGE_SHIFT 3
644 +#define SSB_SROM8_FEM_TR_ISO 0x0700
645 +#define SSB_SROM8_FEM_TR_ISO_SHIFT 8
646 +#define SSB_SROM8_FEM_ANTSWLUT 0xF800
647 +#define SSB_SROM8_FEM_ANTSWLUT_SHIFT 11
648 +#define SSB_SPROM8_THERMAL 0x00B2
649 +#define SSB_SPROM8_MPWR_RAWTS 0x00B4
650 +#define SSB_SPROM8_TS_SLP_OPT_CORRX 0x00B6
651 +#define SSB_SPROM8_FOC_HWIQ_IQSWP 0x00B8
652 +#define SSB_SPROM8_PHYCAL_TEMPDELTA 0x00BA
653 +
654 +/* There are 4 blocks with power info sharing the same layout */
655 +#define SSB_SROM8_PWR_INFO_CORE0 0x00C0
656 +#define SSB_SROM8_PWR_INFO_CORE1 0x00E0
657 +#define SSB_SROM8_PWR_INFO_CORE2 0x0100
658 +#define SSB_SROM8_PWR_INFO_CORE3 0x0120
659 +
660 +#define SSB_SROM8_2G_MAXP_ITSSI 0x00
661 +#define SSB_SPROM8_2G_MAXP 0x00FF
662 +#define SSB_SPROM8_2G_ITSSI 0xFF00
663 +#define SSB_SPROM8_2G_ITSSI_SHIFT 8
664 +#define SSB_SROM8_2G_PA_0 0x02 /* 2GHz power amp settings */
665 +#define SSB_SROM8_2G_PA_1 0x04
666 +#define SSB_SROM8_2G_PA_2 0x06
667 +#define SSB_SROM8_5G_MAXP_ITSSI 0x08 /* 5GHz ITSSI and 5.3GHz Max Power */
668 +#define SSB_SPROM8_5G_MAXP 0x00FF
669 +#define SSB_SPROM8_5G_ITSSI 0xFF00
670 +#define SSB_SPROM8_5G_ITSSI_SHIFT 8
671 +#define SSB_SPROM8_5GHL_MAXP 0x0A /* 5.2GHz and 5.8GHz Max Power */
672 +#define SSB_SPROM8_5GH_MAXP 0x00FF
673 +#define SSB_SPROM8_5GL_MAXP 0xFF00
674 +#define SSB_SPROM8_5GL_MAXP_SHIFT 8
675 +#define SSB_SROM8_5G_PA_0 0x0C /* 5.3GHz power amp settings */
676 +#define SSB_SROM8_5G_PA_1 0x0E
677 +#define SSB_SROM8_5G_PA_2 0x10
678 +#define SSB_SROM8_5GL_PA_0 0x12 /* 5.2GHz power amp settings */
679 +#define SSB_SROM8_5GL_PA_1 0x14
680 +#define SSB_SROM8_5GL_PA_2 0x16
681 +#define SSB_SROM8_5GH_PA_0 0x18 /* 5.8GHz power amp settings */
682 +#define SSB_SROM8_5GH_PA_1 0x1A
683 +#define SSB_SROM8_5GH_PA_2 0x1C
684 +
685 +/* TODO: Make it deprecated */
686 #define SSB_SPROM8_MAXP_BG 0x00C0 /* Max Power 2GHz in path 1 */
687 #define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */
688 #define SSB_SPROM8_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
689 @@ -451,12 +506,53 @@
690 #define SSB_SPROM8_PA1HIB0 0x00D8 /* 5.8GHz power amp settings */
691 #define SSB_SPROM8_PA1HIB1 0x00DA
692 #define SSB_SPROM8_PA1HIB2 0x00DC
693 +
694 #define SSB_SPROM8_CCK2GPO 0x0140 /* CCK power offset */
695 #define SSB_SPROM8_OFDM2GPO 0x0142 /* 2.4GHz OFDM power offset */
696 #define SSB_SPROM8_OFDM5GPO 0x0146 /* 5.3GHz OFDM power offset */
697 #define SSB_SPROM8_OFDM5GLPO 0x014A /* 5.2GHz OFDM power offset */
698 #define SSB_SPROM8_OFDM5GHPO 0x014E /* 5.8GHz OFDM power offset */
699
700 +/* Values for boardflags_lo read from SPROM */
701 +#define SSB_BFL_BTCOEXIST 0x0001 /* implements Bluetooth coexistance */
702 +#define SSB_BFL_PACTRL 0x0002 /* GPIO 9 controlling the PA */
703 +#define SSB_BFL_AIRLINEMODE 0x0004 /* implements GPIO 13 radio disable indication */
704 +#define SSB_BFL_RSSI 0x0008 /* software calculates nrssi slope. */
705 +#define SSB_BFL_ENETSPI 0x0010 /* has ephy roboswitch spi */
706 +#define SSB_BFL_XTAL_NOSLOW 0x0020 /* no slow clock available */
707 +#define SSB_BFL_CCKHIPWR 0x0040 /* can do high power CCK transmission */
708 +#define SSB_BFL_ENETADM 0x0080 /* has ADMtek switch */
709 +#define SSB_BFL_ENETVLAN 0x0100 /* can do vlan */
710 +#define SSB_BFL_AFTERBURNER 0x0200 /* supports Afterburner mode */
711 +#define SSB_BFL_NOPCI 0x0400 /* board leaves PCI floating */
712 +#define SSB_BFL_FEM 0x0800 /* supports the Front End Module */
713 +#define SSB_BFL_EXTLNA 0x1000 /* has an external LNA */
714 +#define SSB_BFL_HGPA 0x2000 /* had high gain PA */
715 +#define SSB_BFL_BTCMOD 0x4000 /* BFL_BTCOEXIST is given in alternate GPIOs */
716 +#define SSB_BFL_ALTIQ 0x8000 /* alternate I/Q settings */
717 +
718 +/* Values for boardflags_hi read from SPROM */
719 +#define SSB_BFH_NOPA 0x0001 /* has no PA */
720 +#define SSB_BFH_RSSIINV 0x0002 /* RSSI uses positive slope (not TSSI) */
721 +#define SSB_BFH_PAREF 0x0004 /* uses the PARef LDO */
722 +#define SSB_BFH_3TSWITCH 0x0008 /* uses a triple throw switch shared with bluetooth */
723 +#define SSB_BFH_PHASESHIFT 0x0010 /* can support phase shifter */
724 +#define SSB_BFH_BUCKBOOST 0x0020 /* has buck/booster */
725 +#define SSB_BFH_FEM_BT 0x0040 /* has FEM and switch to share antenna with bluetooth */
726 +
727 +/* Values for boardflags2_lo read from SPROM */
728 +#define SSB_BFL2_RXBB_INT_REG_DIS 0x0001 /* external RX BB regulator present */
729 +#define SSB_BFL2_APLL_WAR 0x0002 /* alternative A-band PLL settings implemented */
730 +#define SSB_BFL2_TXPWRCTRL_EN 0x0004 /* permits enabling TX Power Control */
731 +#define SSB_BFL2_2X4_DIV 0x0008 /* 2x4 diversity switch */
732 +#define SSB_BFL2_5G_PWRGAIN 0x0010 /* supports 5G band power gain */
733 +#define SSB_BFL2_PCIEWAR_OVR 0x0020 /* overrides ASPM and Clkreq settings */
734 +#define SSB_BFL2_CAESERS_BRD 0x0040 /* is Caesers board (unused) */
735 +#define SSB_BFL2_BTC3WIRE 0x0080 /* used 3-wire bluetooth coexist */
736 +#define SSB_BFL2_SKWRKFEM_BRD 0x0100 /* 4321mcm93 uses Skyworks FEM */
737 +#define SSB_BFL2_SPUR_WAR 0x0200 /* has a workaround for clock-harmonic spurs */
738 +#define SSB_BFL2_GPLL_WAR 0x0400 /* altenative G-band PLL settings implemented */
739 +
740 /* Values for SSB_SPROM1_BINF_CCODE */
741 enum {
742 SSB_SPROM1CCODE_WORLD = 0,
743 --- a/drivers/ssb/driver_chipcommon.c
744 +++ b/drivers/ssb/driver_chipcommon.c
745 @@ -3,7 +3,7 @@
746 * Broadcom ChipCommon core driver
747 *
748 * Copyright 2005, Broadcom Corporation
749 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
750 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
751 *
752 * Licensed under the GNU/GPL. See COPYING for details.
753 */
754 @@ -46,40 +46,66 @@ void ssb_chipco_set_clockmode(struct ssb
755 if (!ccdev)
756 return;
757 bus = ccdev->bus;
758 +
759 + /* We support SLOW only on 6..9 */
760 + if (ccdev->id.revision >= 10 && mode == SSB_CLKMODE_SLOW)
761 + mode = SSB_CLKMODE_DYNAMIC;
762 +
763 + if (cc->capabilities & SSB_CHIPCO_CAP_PMU)
764 + return; /* PMU controls clockmode, separated function needed */
765 + SSB_WARN_ON(ccdev->id.revision >= 20);
766 +
767 /* chipcommon cores prior to rev6 don't support dynamic clock control */
768 if (ccdev->id.revision < 6)
769 return;
770 - /* chipcommon cores rev10 are a whole new ball game */
771 +
772 + /* ChipCommon cores rev10+ need testing */
773 if (ccdev->id.revision >= 10)
774 return;
775 +
776 if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
777 return;
778
779 switch (mode) {
780 - case SSB_CLKMODE_SLOW:
781 + case SSB_CLKMODE_SLOW: /* For revs 6..9 only */
782 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
783 tmp |= SSB_CHIPCO_SLOWCLKCTL_FSLOW;
784 chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
785 break;
786 case SSB_CLKMODE_FAST:
787 - ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */
788 - tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
789 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
790 - tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL;
791 - chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
792 + if (ccdev->id.revision < 10) {
793 + ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */
794 + tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
795 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
796 + tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL;
797 + chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
798 + } else {
799 + chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
800 + (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) |
801 + SSB_CHIPCO_SYSCLKCTL_FORCEHT));
802 + /* udelay(150); TODO: not available in early init */
803 + }
804 break;
805 case SSB_CLKMODE_DYNAMIC:
806 - tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
807 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
808 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL;
809 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
810 - if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) != SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL)
811 - tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
812 - chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
813 -
814 - /* for dynamic control, we have to release our xtal_pu "force on" */
815 - if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL)
816 - ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0);
817 + if (ccdev->id.revision < 10) {
818 + tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
819 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
820 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL;
821 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
822 + if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) !=
823 + SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL)
824 + tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
825 + chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
826 +
827 + /* For dynamic control, we have to release our xtal_pu
828 + * "force on" */
829 + if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL)
830 + ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0);
831 + } else {
832 + chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
833 + (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) &
834 + ~SSB_CHIPCO_SYSCLKCTL_FORCEHT));
835 + }
836 break;
837 default:
838 SSB_WARN_ON(1);
839 @@ -260,6 +286,12 @@ void ssb_chipcommon_init(struct ssb_chip
840 if (cc->dev->id.revision >= 11)
841 cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT);
842 ssb_dprintk(KERN_INFO PFX "chipcommon status is 0x%x\n", cc->status);
843 +
844 + if (cc->dev->id.revision >= 20) {
845 + chipco_write32(cc, SSB_CHIPCO_GPIOPULLUP, 0);
846 + chipco_write32(cc, SSB_CHIPCO_GPIOPULLDOWN, 0);
847 + }
848 +
849 ssb_pmu_init(cc);
850 chipco_powercontrol_init(cc);
851 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
852 --- a/drivers/ssb/driver_chipcommon_pmu.c
853 +++ b/drivers/ssb/driver_chipcommon_pmu.c
854 @@ -2,7 +2,7 @@
855 * Sonics Silicon Backplane
856 * Broadcom ChipCommon Power Management Unit driver
857 *
858 - * Copyright 2009, Michael Buesch <mb@bu3sch.de>
859 + * Copyright 2009, Michael Buesch <m@bues.ch>
860 * Copyright 2007, Broadcom Corporation
861 *
862 * Licensed under the GNU/GPL. See COPYING for details.
863 @@ -12,6 +12,9 @@
864 #include <linux/ssb/ssb_regs.h>
865 #include <linux/ssb/ssb_driver_chipcommon.h>
866 #include <linux/delay.h>
867 +#ifdef CONFIG_BCM47XX
868 +#include <asm/mach-bcm47xx/nvram.h>
869 +#endif
870
871 #include "ssb_private.h"
872
873 @@ -91,10 +94,6 @@ static void ssb_pmu0_pllinit_r0(struct s
874 u32 pmuctl, tmp, pllctl;
875 unsigned int i;
876
877 - if ((bus->chip_id == 0x5354) && !crystalfreq) {
878 - /* The 5354 crystal freq is 25MHz */
879 - crystalfreq = 25000;
880 - }
881 if (crystalfreq)
882 e = pmu0_plltab_find_entry(crystalfreq);
883 if (!e)
884 @@ -320,7 +319,11 @@ static void ssb_pmu_pll_init(struct ssb_
885 u32 crystalfreq = 0; /* in kHz. 0 = keep default freq. */
886
887 if (bus->bustype == SSB_BUSTYPE_SSB) {
888 - /* TODO: The user may override the crystal frequency. */
889 +#ifdef CONFIG_BCM47XX
890 + char buf[20];
891 + if (nvram_getenv("xtalfreq", buf, sizeof(buf)) >= 0)
892 + crystalfreq = simple_strtoul(buf, NULL, 0);
893 +#endif
894 }
895
896 switch (bus->chip_id) {
897 @@ -329,7 +332,11 @@ static void ssb_pmu_pll_init(struct ssb_
898 ssb_pmu1_pllinit_r0(cc, crystalfreq);
899 break;
900 case 0x4328:
901 + ssb_pmu0_pllinit_r0(cc, crystalfreq);
902 + break;
903 case 0x5354:
904 + if (crystalfreq == 0)
905 + crystalfreq = 25000;
906 ssb_pmu0_pllinit_r0(cc, crystalfreq);
907 break;
908 case 0x4322:
909 @@ -417,12 +424,14 @@ static void ssb_pmu_resources_init(struc
910 u32 min_msk = 0, max_msk = 0;
911 unsigned int i;
912 const struct pmu_res_updown_tab_entry *updown_tab = NULL;
913 - unsigned int updown_tab_size;
914 + unsigned int updown_tab_size = 0;
915 const struct pmu_res_depend_tab_entry *depend_tab = NULL;
916 - unsigned int depend_tab_size;
917 + unsigned int depend_tab_size = 0;
918
919 switch (bus->chip_id) {
920 case 0x4312:
921 + min_msk = 0xCBB;
922 + break;
923 case 0x4322:
924 /* We keep the default settings:
925 * min_msk = 0xCBB
926 @@ -604,3 +613,34 @@ void ssb_pmu_set_ldo_paref(struct ssb_ch
927
928 EXPORT_SYMBOL(ssb_pmu_set_ldo_voltage);
929 EXPORT_SYMBOL(ssb_pmu_set_ldo_paref);
930 +
931 +u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc)
932 +{
933 + struct ssb_bus *bus = cc->dev->bus;
934 +
935 + switch (bus->chip_id) {
936 + case 0x5354:
937 + /* 5354 chip uses a non programmable PLL of frequency 240MHz */
938 + return 240000000;
939 + default:
940 + ssb_printk(KERN_ERR PFX
941 + "ERROR: PMU cpu clock unknown for device %04X\n",
942 + bus->chip_id);
943 + return 0;
944 + }
945 +}
946 +
947 +u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc)
948 +{
949 + struct ssb_bus *bus = cc->dev->bus;
950 +
951 + switch (bus->chip_id) {
952 + case 0x5354:
953 + return 120000000;
954 + default:
955 + ssb_printk(KERN_ERR PFX
956 + "ERROR: PMU controlclock unknown for device %04X\n",
957 + bus->chip_id);
958 + return 0;
959 + }
960 +}
961 --- a/drivers/ssb/driver_gige.c
962 +++ b/drivers/ssb/driver_gige.c
963 @@ -3,7 +3,7 @@
964 * Broadcom Gigabit Ethernet core driver
965 *
966 * Copyright 2008, Broadcom Corporation
967 - * Copyright 2008, Michael Buesch <mb@bu3sch.de>
968 + * Copyright 2008, Michael Buesch <m@bues.ch>
969 *
970 * Licensed under the GNU/GPL. See COPYING for details.
971 */
972 @@ -106,8 +106,9 @@ void gige_pcicfg_write32(struct ssb_gige
973 gige_write32(dev, SSB_GIGE_PCICFG + offset, value);
974 }
975
976 -static int ssb_gige_pci_read_config(struct pci_bus *bus, unsigned int devfn,
977 - int reg, int size, u32 *val)
978 +static int __devinit ssb_gige_pci_read_config(struct pci_bus *bus,
979 + unsigned int devfn, int reg,
980 + int size, u32 *val)
981 {
982 struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
983 unsigned long flags;
984 @@ -136,8 +137,9 @@ static int ssb_gige_pci_read_config(stru
985 return PCIBIOS_SUCCESSFUL;
986 }
987
988 -static int ssb_gige_pci_write_config(struct pci_bus *bus, unsigned int devfn,
989 - int reg, int size, u32 val)
990 +static int __devinit ssb_gige_pci_write_config(struct pci_bus *bus,
991 + unsigned int devfn, int reg,
992 + int size, u32 val)
993 {
994 struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
995 unsigned long flags;
996 @@ -166,7 +168,8 @@ static int ssb_gige_pci_write_config(str
997 return PCIBIOS_SUCCESSFUL;
998 }
999
1000 -static int ssb_gige_probe(struct ssb_device *sdev, const struct ssb_device_id *id)
1001 +static int __devinit ssb_gige_probe(struct ssb_device *sdev,
1002 + const struct ssb_device_id *id)
1003 {
1004 struct ssb_gige *dev;
1005 u32 base, tmslow, tmshigh;
1006 --- a/drivers/ssb/driver_pcicore.c
1007 +++ b/drivers/ssb/driver_pcicore.c
1008 @@ -3,7 +3,7 @@
1009 * Broadcom PCI-core driver
1010 *
1011 * Copyright 2005, Broadcom Corporation
1012 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
1013 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
1014 *
1015 * Licensed under the GNU/GPL. See COPYING for details.
1016 */
1017 @@ -15,6 +15,11 @@
1018
1019 #include "ssb_private.h"
1020
1021 +static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address);
1022 +static void ssb_pcie_write(struct ssb_pcicore *pc, u32 address, u32 data);
1023 +static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address);
1024 +static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
1025 + u8 address, u16 data);
1026
1027 static inline
1028 u32 pcicore_read32(struct ssb_pcicore *pc, u16 offset)
1029 @@ -69,7 +74,7 @@ static u32 get_cfgspace_addr(struct ssb_
1030 u32 tmp;
1031
1032 /* We do only have one cardbus device behind the bridge. */
1033 - if (pc->cardbusmode && (dev >= 1))
1034 + if (pc->cardbusmode && (dev > 1))
1035 goto out;
1036
1037 if (bus == 0) {
1038 @@ -309,7 +314,7 @@ int ssb_pcicore_pcibios_map_irq(const st
1039 return ssb_mips_irq(extpci_core->dev) + 2;
1040 }
1041
1042 -static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
1043 +static void __devinit ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
1044 {
1045 u32 val;
1046
1047 @@ -374,7 +379,7 @@ static void ssb_pcicore_init_hostmode(st
1048 register_pci_controller(&ssb_pcicore_controller);
1049 }
1050
1051 -static int pcicore_is_in_hostmode(struct ssb_pcicore *pc)
1052 +static int __devinit pcicore_is_in_hostmode(struct ssb_pcicore *pc)
1053 {
1054 struct ssb_bus *bus = pc->dev->bus;
1055 u16 chipid_top;
1056 @@ -403,25 +408,137 @@ static int pcicore_is_in_hostmode(struct
1057 }
1058 #endif /* CONFIG_SSB_PCICORE_HOSTMODE */
1059
1060 +/**************************************************
1061 + * Workarounds.
1062 + **************************************************/
1063 +
1064 +static void __devinit ssb_pcicore_fix_sprom_core_index(struct ssb_pcicore *pc)
1065 +{
1066 + u16 tmp = pcicore_read16(pc, SSB_PCICORE_SPROM(0));
1067 + if (((tmp & 0xF000) >> 12) != pc->dev->core_index) {
1068 + tmp &= ~0xF000;
1069 + tmp |= (pc->dev->core_index << 12);
1070 + pcicore_write16(pc, SSB_PCICORE_SPROM(0), tmp);
1071 + }
1072 +}
1073 +
1074 +static u8 ssb_pcicore_polarity_workaround(struct ssb_pcicore *pc)
1075 +{
1076 + return (ssb_pcie_read(pc, 0x204) & 0x10) ? 0xC0 : 0x80;
1077 +}
1078 +
1079 +static void ssb_pcicore_serdes_workaround(struct ssb_pcicore *pc)
1080 +{
1081 + const u8 serdes_pll_device = 0x1D;
1082 + const u8 serdes_rx_device = 0x1F;
1083 + u16 tmp;
1084 +
1085 + ssb_pcie_mdio_write(pc, serdes_rx_device, 1 /* Control */,
1086 + ssb_pcicore_polarity_workaround(pc));
1087 + tmp = ssb_pcie_mdio_read(pc, serdes_pll_device, 1 /* Control */);
1088 + if (tmp & 0x4000)
1089 + ssb_pcie_mdio_write(pc, serdes_pll_device, 1, tmp & ~0x4000);
1090 +}
1091 +
1092 +static void ssb_pcicore_pci_setup_workarounds(struct ssb_pcicore *pc)
1093 +{
1094 + struct ssb_device *pdev = pc->dev;
1095 + struct ssb_bus *bus = pdev->bus;
1096 + u32 tmp;
1097 +
1098 + tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
1099 + tmp |= SSB_PCICORE_SBTOPCI_PREF;
1100 + tmp |= SSB_PCICORE_SBTOPCI_BURST;
1101 + pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
1102 +
1103 + if (pdev->id.revision < 5) {
1104 + tmp = ssb_read32(pdev, SSB_IMCFGLO);
1105 + tmp &= ~SSB_IMCFGLO_SERTO;
1106 + tmp |= 2;
1107 + tmp &= ~SSB_IMCFGLO_REQTO;
1108 + tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT;
1109 + ssb_write32(pdev, SSB_IMCFGLO, tmp);
1110 + ssb_commit_settings(bus);
1111 + } else if (pdev->id.revision >= 11) {
1112 + tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
1113 + tmp |= SSB_PCICORE_SBTOPCI_MRM;
1114 + pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
1115 + }
1116 +}
1117 +
1118 +static void ssb_pcicore_pcie_setup_workarounds(struct ssb_pcicore *pc)
1119 +{
1120 + u32 tmp;
1121 + u8 rev = pc->dev->id.revision;
1122 +
1123 + if (rev == 0 || rev == 1) {
1124 + /* TLP Workaround register. */
1125 + tmp = ssb_pcie_read(pc, 0x4);
1126 + tmp |= 0x8;
1127 + ssb_pcie_write(pc, 0x4, tmp);
1128 + }
1129 + if (rev == 1) {
1130 + /* DLLP Link Control register. */
1131 + tmp = ssb_pcie_read(pc, 0x100);
1132 + tmp |= 0x40;
1133 + ssb_pcie_write(pc, 0x100, tmp);
1134 + }
1135 +
1136 + if (rev == 0) {
1137 + const u8 serdes_rx_device = 0x1F;
1138 +
1139 + ssb_pcie_mdio_write(pc, serdes_rx_device,
1140 + 2 /* Timer */, 0x8128);
1141 + ssb_pcie_mdio_write(pc, serdes_rx_device,
1142 + 6 /* CDR */, 0x0100);
1143 + ssb_pcie_mdio_write(pc, serdes_rx_device,
1144 + 7 /* CDR BW */, 0x1466);
1145 + } else if (rev == 3 || rev == 4 || rev == 5) {
1146 + /* TODO: DLLP Power Management Threshold */
1147 + ssb_pcicore_serdes_workaround(pc);
1148 + /* TODO: ASPM */
1149 + } else if (rev == 7) {
1150 + /* TODO: No PLL down */
1151 + }
1152 +
1153 + if (rev >= 6) {
1154 + /* Miscellaneous Configuration Fixup */
1155 + tmp = pcicore_read16(pc, SSB_PCICORE_SPROM(5));
1156 + if (!(tmp & 0x8000))
1157 + pcicore_write16(pc, SSB_PCICORE_SPROM(5),
1158 + tmp | 0x8000);
1159 + }
1160 +}
1161
1162 /**************************************************
1163 * Generic and Clientmode operation code.
1164 **************************************************/
1165
1166 -static void ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)
1167 +static void __devinit ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)
1168 {
1169 + struct ssb_device *pdev = pc->dev;
1170 + struct ssb_bus *bus = pdev->bus;
1171 +
1172 + if (bus->bustype == SSB_BUSTYPE_PCI)
1173 + ssb_pcicore_fix_sprom_core_index(pc);
1174 +
1175 /* Disable PCI interrupts. */
1176 - ssb_write32(pc->dev, SSB_INTVEC, 0);
1177 + ssb_write32(pdev, SSB_INTVEC, 0);
1178 +
1179 + /* Additional PCIe always once-executed workarounds */
1180 + if (pc->dev->id.coreid == SSB_DEV_PCIE) {
1181 + ssb_pcicore_serdes_workaround(pc);
1182 + /* TODO: ASPM */
1183 + /* TODO: Clock Request Update */
1184 + }
1185 }
1186
1187 -void ssb_pcicore_init(struct ssb_pcicore *pc)
1188 +void __devinit ssb_pcicore_init(struct ssb_pcicore *pc)
1189 {
1190 struct ssb_device *dev = pc->dev;
1191 - struct ssb_bus *bus;
1192
1193 if (!dev)
1194 return;
1195 - bus = dev->bus;
1196 if (!ssb_device_is_enabled(dev))
1197 ssb_device_enable(dev, 0);
1198
1199 @@ -446,11 +563,35 @@ static void ssb_pcie_write(struct ssb_pc
1200 pcicore_write32(pc, 0x134, data);
1201 }
1202
1203 -static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
1204 - u8 address, u16 data)
1205 +static void ssb_pcie_mdio_set_phy(struct ssb_pcicore *pc, u8 phy)
1206 +{
1207 + const u16 mdio_control = 0x128;
1208 + const u16 mdio_data = 0x12C;
1209 + u32 v;
1210 + int i;
1211 +
1212 + v = (1 << 30); /* Start of Transaction */
1213 + v |= (1 << 28); /* Write Transaction */
1214 + v |= (1 << 17); /* Turnaround */
1215 + v |= (0x1F << 18);
1216 + v |= (phy << 4);
1217 + pcicore_write32(pc, mdio_data, v);
1218 +
1219 + udelay(10);
1220 + for (i = 0; i < 200; i++) {
1221 + v = pcicore_read32(pc, mdio_control);
1222 + if (v & 0x100 /* Trans complete */)
1223 + break;
1224 + msleep(1);
1225 + }
1226 +}
1227 +
1228 +static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address)
1229 {
1230 const u16 mdio_control = 0x128;
1231 const u16 mdio_data = 0x12C;
1232 + int max_retries = 10;
1233 + u16 ret = 0;
1234 u32 v;
1235 int i;
1236
1237 @@ -458,46 +599,68 @@ static void ssb_pcie_mdio_write(struct s
1238 v |= 0x2; /* MDIO Clock Divisor */
1239 pcicore_write32(pc, mdio_control, v);
1240
1241 + if (pc->dev->id.revision >= 10) {
1242 + max_retries = 200;
1243 + ssb_pcie_mdio_set_phy(pc, device);
1244 + }
1245 +
1246 v = (1 << 30); /* Start of Transaction */
1247 - v |= (1 << 28); /* Write Transaction */
1248 + v |= (1 << 29); /* Read Transaction */
1249 v |= (1 << 17); /* Turnaround */
1250 - v |= (u32)device << 22;
1251 + if (pc->dev->id.revision < 10)
1252 + v |= (u32)device << 22;
1253 v |= (u32)address << 18;
1254 - v |= data;
1255 pcicore_write32(pc, mdio_data, v);
1256 /* Wait for the device to complete the transaction */
1257 udelay(10);
1258 - for (i = 0; i < 10; i++) {
1259 + for (i = 0; i < max_retries; i++) {
1260 v = pcicore_read32(pc, mdio_control);
1261 - if (v & 0x100 /* Trans complete */)
1262 + if (v & 0x100 /* Trans complete */) {
1263 + udelay(10);
1264 + ret = pcicore_read32(pc, mdio_data);
1265 break;
1266 + }
1267 msleep(1);
1268 }
1269 pcicore_write32(pc, mdio_control, 0);
1270 + return ret;
1271 }
1272
1273 -static void ssb_broadcast_value(struct ssb_device *dev,
1274 - u32 address, u32 data)
1275 +static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
1276 + u8 address, u16 data)
1277 {
1278 - /* This is used for both, PCI and ChipCommon core, so be careful. */
1279 - BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
1280 - BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
1281 + const u16 mdio_control = 0x128;
1282 + const u16 mdio_data = 0x12C;
1283 + int max_retries = 10;
1284 + u32 v;
1285 + int i;
1286
1287 - ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address);
1288 - ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */
1289 - ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data);
1290 - ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */
1291 -}
1292 + v = 0x80; /* Enable Preamble Sequence */
1293 + v |= 0x2; /* MDIO Clock Divisor */
1294 + pcicore_write32(pc, mdio_control, v);
1295
1296 -static void ssb_commit_settings(struct ssb_bus *bus)
1297 -{
1298 - struct ssb_device *dev;
1299 + if (pc->dev->id.revision >= 10) {
1300 + max_retries = 200;
1301 + ssb_pcie_mdio_set_phy(pc, device);
1302 + }
1303
1304 - dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
1305 - if (WARN_ON(!dev))
1306 - return;
1307 - /* This forces an update of the cached registers. */
1308 - ssb_broadcast_value(dev, 0xFD8, 0);
1309 + v = (1 << 30); /* Start of Transaction */
1310 + v |= (1 << 28); /* Write Transaction */
1311 + v |= (1 << 17); /* Turnaround */
1312 + if (pc->dev->id.revision < 10)
1313 + v |= (u32)device << 22;
1314 + v |= (u32)address << 18;
1315 + v |= data;
1316 + pcicore_write32(pc, mdio_data, v);
1317 + /* Wait for the device to complete the transaction */
1318 + udelay(10);
1319 + for (i = 0; i < max_retries; i++) {
1320 + v = pcicore_read32(pc, mdio_control);
1321 + if (v & 0x100 /* Trans complete */)
1322 + break;
1323 + msleep(1);
1324 + }
1325 + pcicore_write32(pc, mdio_control, 0);
1326 }
1327
1328 int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
1329 @@ -550,48 +713,10 @@ int ssb_pcicore_dev_irqvecs_enable(struc
1330 if (pc->setup_done)
1331 goto out;
1332 if (pdev->id.coreid == SSB_DEV_PCI) {
1333 - tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
1334 - tmp |= SSB_PCICORE_SBTOPCI_PREF;
1335 - tmp |= SSB_PCICORE_SBTOPCI_BURST;
1336 - pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
1337 -
1338 - if (pdev->id.revision < 5) {
1339 - tmp = ssb_read32(pdev, SSB_IMCFGLO);
1340 - tmp &= ~SSB_IMCFGLO_SERTO;
1341 - tmp |= 2;
1342 - tmp &= ~SSB_IMCFGLO_REQTO;
1343 - tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT;
1344 - ssb_write32(pdev, SSB_IMCFGLO, tmp);
1345 - ssb_commit_settings(bus);
1346 - } else if (pdev->id.revision >= 11) {
1347 - tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
1348 - tmp |= SSB_PCICORE_SBTOPCI_MRM;
1349 - pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
1350 - }
1351 + ssb_pcicore_pci_setup_workarounds(pc);
1352 } else {
1353 WARN_ON(pdev->id.coreid != SSB_DEV_PCIE);
1354 - //TODO: Better make defines for all these magic PCIE values.
1355 - if ((pdev->id.revision == 0) || (pdev->id.revision == 1)) {
1356 - /* TLP Workaround register. */
1357 - tmp = ssb_pcie_read(pc, 0x4);
1358 - tmp |= 0x8;
1359 - ssb_pcie_write(pc, 0x4, tmp);
1360 - }
1361 - if (pdev->id.revision == 0) {
1362 - const u8 serdes_rx_device = 0x1F;
1363 -
1364 - ssb_pcie_mdio_write(pc, serdes_rx_device,
1365 - 2 /* Timer */, 0x8128);
1366 - ssb_pcie_mdio_write(pc, serdes_rx_device,
1367 - 6 /* CDR */, 0x0100);
1368 - ssb_pcie_mdio_write(pc, serdes_rx_device,
1369 - 7 /* CDR BW */, 0x1466);
1370 - } else if (pdev->id.revision == 1) {
1371 - /* DLLP Link Control register. */
1372 - tmp = ssb_pcie_read(pc, 0x100);
1373 - tmp |= 0x40;
1374 - ssb_pcie_write(pc, 0x100, tmp);
1375 - }
1376 + ssb_pcicore_pcie_setup_workarounds(pc);
1377 }
1378 pc->setup_done = 1;
1379 out:
1380 --- a/drivers/ssb/pcihost_wrapper.c
1381 +++ b/drivers/ssb/pcihost_wrapper.c
1382 @@ -6,7 +6,7 @@
1383 * Copyright (c) 2005 Stefano Brivio <st3@riseup.net>
1384 * Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
1385 * Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
1386 - * Copyright (c) 2005-2007 Michael Buesch <mbuesch@freenet.de>
1387 + * Copyright (c) 2005-2007 Michael Buesch <m@bues.ch>
1388 *
1389 * Licensed under the GNU/GPL. See COPYING for details.
1390 */
1391 @@ -53,8 +53,8 @@ static int ssb_pcihost_resume(struct pci
1392 # define ssb_pcihost_resume NULL
1393 #endif /* CONFIG_PM */
1394
1395 -static int ssb_pcihost_probe(struct pci_dev *dev,
1396 - const struct pci_device_id *id)
1397 +static int __devinit ssb_pcihost_probe(struct pci_dev *dev,
1398 + const struct pci_device_id *id)
1399 {
1400 struct ssb_bus *ssb;
1401 int err = -ENOMEM;
1402 @@ -110,7 +110,7 @@ static void ssb_pcihost_remove(struct pc
1403 pci_set_drvdata(dev, NULL);
1404 }
1405
1406 -int ssb_pcihost_register(struct pci_driver *driver)
1407 +int __devinit ssb_pcihost_register(struct pci_driver *driver)
1408 {
1409 driver->probe = ssb_pcihost_probe;
1410 driver->remove = ssb_pcihost_remove;
1411 --- a/drivers/ssb/scan.c
1412 +++ b/drivers/ssb/scan.c
1413 @@ -2,7 +2,7 @@
1414 * Sonics Silicon Backplane
1415 * Bus scanning
1416 *
1417 - * Copyright (C) 2005-2007 Michael Buesch <mb@bu3sch.de>
1418 + * Copyright (C) 2005-2007 Michael Buesch <m@bues.ch>
1419 * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
1420 * Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
1421 * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
1422 @@ -258,7 +258,10 @@ static int we_support_multiple_80211_cor
1423 #ifdef CONFIG_SSB_PCIHOST
1424 if (bus->bustype == SSB_BUSTYPE_PCI) {
1425 if (bus->host_pci->vendor == PCI_VENDOR_ID_BROADCOM &&
1426 - bus->host_pci->device == 0x4324)
1427 + ((bus->host_pci->device == 0x4313) ||
1428 + (bus->host_pci->device == 0x431A) ||
1429 + (bus->host_pci->device == 0x4321) ||
1430 + (bus->host_pci->device == 0x4324)))
1431 return 1;
1432 }
1433 #endif /* CONFIG_SSB_PCIHOST */
1434 @@ -307,8 +310,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
1435 } else {
1436 if (bus->bustype == SSB_BUSTYPE_PCI) {
1437 bus->chip_id = pcidev_to_chipid(bus->host_pci);
1438 - pci_read_config_word(bus->host_pci, PCI_REVISION_ID,
1439 - &bus->chip_rev);
1440 + bus->chip_rev = bus->host_pci->revision;
1441 bus->chip_package = 0;
1442 } else {
1443 bus->chip_id = 0x4710;
1444 @@ -316,6 +318,9 @@ int ssb_bus_scan(struct ssb_bus *bus,
1445 bus->chip_package = 0;
1446 }
1447 }
1448 + ssb_printk(KERN_INFO PFX "Found chip with id 0x%04X, rev 0x%02X and "
1449 + "package 0x%02X\n", bus->chip_id, bus->chip_rev,
1450 + bus->chip_package);
1451 if (!bus->nr_devices)
1452 bus->nr_devices = chipid_to_nrcores(bus->chip_id);
1453 if (bus->nr_devices > ARRAY_SIZE(bus->devices)) {
1454 --- a/drivers/ssb/sprom.c
1455 +++ b/drivers/ssb/sprom.c
1456 @@ -2,7 +2,7 @@
1457 * Sonics Silicon Backplane
1458 * Common SPROM support routines
1459 *
1460 - * Copyright (C) 2005-2008 Michael Buesch <mb@bu3sch.de>
1461 + * Copyright (C) 2005-2008 Michael Buesch <m@bues.ch>
1462 * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
1463 * Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
1464 * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
1465 @@ -17,7 +17,7 @@
1466 #include <linux/slab.h>
1467
1468
1469 -static const struct ssb_sprom *fallback_sprom;
1470 +static int(*get_fallback_sprom)(struct ssb_bus *dev, struct ssb_sprom *out);
1471
1472
1473 static int sprom2hex(const u16 *sprom, char *buf, size_t buf_len,
1474 @@ -145,36 +145,43 @@ out:
1475 }
1476
1477 /**
1478 - * ssb_arch_set_fallback_sprom - Set a fallback SPROM for use if no SPROM is found.
1479 + * ssb_arch_register_fallback_sprom - Registers a method providing a
1480 + * fallback SPROM if no SPROM is found.
1481 *
1482 - * @sprom: The SPROM data structure to register.
1483 + * @sprom_callback: The callback function.
1484 *
1485 - * With this function the architecture implementation may register a fallback
1486 - * SPROM data structure. The fallback is only used for PCI based SSB devices,
1487 - * where no valid SPROM can be found in the shadow registers.
1488 + * With this function the architecture implementation may register a
1489 + * callback handler which fills the SPROM data structure. The fallback is
1490 + * only used for PCI based SSB devices, where no valid SPROM can be found
1491 + * in the shadow registers.
1492 + *
1493 + * This function is useful for weird architectures that have a half-assed
1494 + * SSB device hardwired to their PCI bus.
1495 + *
1496 + * Note that it does only work with PCI attached SSB devices. PCMCIA
1497 + * devices currently don't use this fallback.
1498 + * Architectures must provide the SPROM for native SSB devices anyway, so
1499 + * the fallback also isn't used for native devices.
1500 *
1501 - * This function is useful for weird architectures that have a half-assed SSB device
1502 - * hardwired to their PCI bus.
1503 - *
1504 - * Note that it does only work with PCI attached SSB devices. PCMCIA devices currently
1505 - * don't use this fallback.
1506 - * Architectures must provide the SPROM for native SSB devices anyway,
1507 - * so the fallback also isn't used for native devices.
1508 - *
1509 - * This function is available for architecture code, only. So it is not exported.
1510 + * This function is available for architecture code, only. So it is not
1511 + * exported.
1512 */
1513 -int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom)
1514 +int ssb_arch_register_fallback_sprom(int (*sprom_callback)(struct ssb_bus *bus,
1515 + struct ssb_sprom *out))
1516 {
1517 - if (fallback_sprom)
1518 + if (get_fallback_sprom)
1519 return -EEXIST;
1520 - fallback_sprom = sprom;
1521 + get_fallback_sprom = sprom_callback;
1522
1523 return 0;
1524 }
1525
1526 -const struct ssb_sprom *ssb_get_fallback_sprom(void)
1527 +int ssb_fill_sprom_with_fallback(struct ssb_bus *bus, struct ssb_sprom *out)
1528 {
1529 - return fallback_sprom;
1530 + if (!get_fallback_sprom)
1531 + return -ENOENT;
1532 +
1533 + return get_fallback_sprom(bus, out);
1534 }
1535
1536 /* http://bcm-v4.sipsolutions.net/802.11/IsSpromAvailable */
1537 @@ -185,7 +192,7 @@ bool ssb_is_sprom_available(struct ssb_b
1538 /* this routine differs from specs as we do not access SPROM directly
1539 on PCMCIA */
1540 if (bus->bustype == SSB_BUSTYPE_PCI &&
1541 - bus->chipco.dev && /* can be unavailible! */
1542 + bus->chipco.dev && /* can be unavailable! */
1543 bus->chipco.dev->id.revision >= 31)
1544 return bus->chipco.capabilities & SSB_CHIPCO_CAP_SPROM;
1545
1546 --- a/drivers/ssb/ssb_private.h
1547 +++ b/drivers/ssb/ssb_private.h
1548 @@ -171,7 +171,8 @@ ssize_t ssb_attr_sprom_store(struct ssb_
1549 const char *buf, size_t count,
1550 int (*sprom_check_crc)(const u16 *sprom, size_t size),
1551 int (*sprom_write)(struct ssb_bus *bus, const u16 *sprom));
1552 -extern const struct ssb_sprom *ssb_get_fallback_sprom(void);
1553 +extern int ssb_fill_sprom_with_fallback(struct ssb_bus *bus,
1554 + struct ssb_sprom *out);
1555
1556
1557 /* core.c */
1558 @@ -206,4 +207,8 @@ static inline void b43_pci_ssb_bridge_ex
1559 }
1560 #endif /* CONFIG_SSB_B43_PCI_BRIDGE */
1561
1562 +/* driver_chipcommon_pmu.c */
1563 +extern u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc);
1564 +extern u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc);
1565 +
1566 #endif /* LINUX_SSB_PRIVATE_H_ */
1567 --- a/include/linux/ssb/ssb.h
1568 +++ b/include/linux/ssb/ssb.h
1569 @@ -16,6 +16,12 @@ struct pcmcia_device;
1570 struct ssb_bus;
1571 struct ssb_driver;
1572
1573 +struct ssb_sprom_core_pwr_info {
1574 + u8 itssi_2g, itssi_5g;
1575 + u8 maxpwr_2g, maxpwr_5gl, maxpwr_5g, maxpwr_5gh;
1576 + u16 pa_2g[4], pa_5gl[4], pa_5g[4], pa_5gh[4];
1577 +};
1578 +
1579 struct ssb_sprom {
1580 u8 revision;
1581 u8 il0mac[6]; /* MAC address for 802.11b/g */
1582 @@ -25,8 +31,13 @@ struct ssb_sprom {
1583 u8 et1phyaddr; /* MII address for enet1 */
1584 u8 et0mdcport; /* MDIO for enet0 */
1585 u8 et1mdcport; /* MDIO for enet1 */
1586 - u8 board_rev; /* Board revision number from SPROM. */
1587 + u16 board_rev; /* Board revision number from SPROM. */
1588 + u16 board_num; /* Board number from SPROM. */
1589 + u16 board_type; /* Board type from SPROM. */
1590 u8 country_code; /* Country Code */
1591 + char alpha2[2]; /* Country Code as two chars like EU or US */
1592 + u8 leddc_on_time; /* LED Powersave Duty Cycle On Count */
1593 + u8 leddc_off_time; /* LED Powersave Duty Cycle Off Count */
1594 u8 ant_available_a; /* 2GHz antenna available bits (up to 4) */
1595 u8 ant_available_bg; /* 5GHz antenna available bits (up to 4) */
1596 u16 pa0b0;
1597 @@ -45,10 +56,10 @@ struct ssb_sprom {
1598 u8 gpio1; /* GPIO pin 1 */
1599 u8 gpio2; /* GPIO pin 2 */
1600 u8 gpio3; /* GPIO pin 3 */
1601 - u16 maxpwr_bg; /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */
1602 - u16 maxpwr_al; /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */
1603 - u16 maxpwr_a; /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */
1604 - u16 maxpwr_ah; /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */
1605 + u8 maxpwr_bg; /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */
1606 + u8 maxpwr_al; /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */
1607 + u8 maxpwr_a; /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */
1608 + u8 maxpwr_ah; /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */
1609 u8 itssi_a; /* Idle TSSI Target for A-PHY */
1610 u8 itssi_bg; /* Idle TSSI Target for B/G-PHY */
1611 u8 tri2g; /* 2.4GHz TX isolation */
1612 @@ -59,8 +70,8 @@ struct ssb_sprom {
1613 u8 txpid5gl[4]; /* 4.9 - 5.1GHz TX power index */
1614 u8 txpid5g[4]; /* 5.1 - 5.5GHz TX power index */
1615 u8 txpid5gh[4]; /* 5.5 - ...GHz TX power index */
1616 - u8 rxpo2g; /* 2GHz RX power offset */
1617 - u8 rxpo5g; /* 5GHz RX power offset */
1618 + s8 rxpo2g; /* 2GHz RX power offset */
1619 + s8 rxpo5g; /* 5GHz RX power offset */
1620 u8 rssisav2g; /* 2GHz RSSI params */
1621 u8 rssismc2g;
1622 u8 rssismf2g;
1623 @@ -80,26 +91,104 @@ struct ssb_sprom {
1624 u16 boardflags2_hi; /* Board flags (bits 48-63) */
1625 /* TODO store board flags in a single u64 */
1626
1627 + struct ssb_sprom_core_pwr_info core_pwr_info[4];
1628 +
1629 /* Antenna gain values for up to 4 antennas
1630 * on each band. Values in dBm/4 (Q5.2). Negative gain means the
1631 * loss in the connectors is bigger than the gain. */
1632 struct {
1633 - struct {
1634 - s8 a0, a1, a2, a3;
1635 - } ghz24; /* 2.4GHz band */
1636 - struct {
1637 - s8 a0, a1, a2, a3;
1638 - } ghz5; /* 5GHz band */
1639 + s8 a0, a1, a2, a3;
1640 } antenna_gain;
1641
1642 - /* TODO - add any parameters needed from rev 2, 3, 4, 5 or 8 SPROMs */
1643 + struct {
1644 + struct {
1645 + u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
1646 + } ghz2;
1647 + struct {
1648 + u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
1649 + } ghz5;
1650 + } fem;
1651 +
1652 + u16 mcs2gpo[8];
1653 + u16 mcs5gpo[8];
1654 + u16 mcs5glpo[8];
1655 + u16 mcs5ghpo[8];
1656 + u8 opo;
1657 +
1658 + u8 rxgainerr2ga[3];
1659 + u8 rxgainerr5gla[3];
1660 + u8 rxgainerr5gma[3];
1661 + u8 rxgainerr5gha[3];
1662 + u8 rxgainerr5gua[3];
1663 +
1664 + u8 noiselvl2ga[3];
1665 + u8 noiselvl5gla[3];
1666 + u8 noiselvl5gma[3];
1667 + u8 noiselvl5gha[3];
1668 + u8 noiselvl5gua[3];
1669 +
1670 + u8 regrev;
1671 + u8 txchain;
1672 + u8 rxchain;
1673 + u8 antswitch;
1674 + u16 cddpo;
1675 + u16 stbcpo;
1676 + u16 bw40po;
1677 + u16 bwduppo;
1678 +
1679 + u8 tempthresh;
1680 + u8 tempoffset;
1681 + u16 rawtempsense;
1682 + u8 measpower;
1683 + u8 tempsense_slope;
1684 + u8 tempcorrx;
1685 + u8 tempsense_option;
1686 + u8 freqoffset_corr;
1687 + u8 iqcal_swp_dis;
1688 + u8 hw_iqcal_en;
1689 + u8 elna2g;
1690 + u8 elna5g;
1691 + u8 phycal_tempdelta;
1692 + u8 temps_period;
1693 + u8 temps_hysteresis;
1694 + u8 measpower1;
1695 + u8 measpower2;
1696 + u8 pcieingress_war;
1697 +
1698 + /* power per rate from sromrev 9 */
1699 + u16 cckbw202gpo;
1700 + u16 cckbw20ul2gpo;
1701 + u32 legofdmbw202gpo;
1702 + u32 legofdmbw20ul2gpo;
1703 + u32 legofdmbw205glpo;
1704 + u32 legofdmbw20ul5glpo;
1705 + u32 legofdmbw205gmpo;
1706 + u32 legofdmbw20ul5gmpo;
1707 + u32 legofdmbw205ghpo;
1708 + u32 legofdmbw20ul5ghpo;
1709 + u32 mcsbw202gpo;
1710 + u32 mcsbw20ul2gpo;
1711 + u32 mcsbw402gpo;
1712 + u32 mcsbw205glpo;
1713 + u32 mcsbw20ul5glpo;
1714 + u32 mcsbw405glpo;
1715 + u32 mcsbw205gmpo;
1716 + u32 mcsbw20ul5gmpo;
1717 + u32 mcsbw405gmpo;
1718 + u32 mcsbw205ghpo;
1719 + u32 mcsbw20ul5ghpo;
1720 + u32 mcsbw405ghpo;
1721 + u16 mcs32po;
1722 + u16 legofdm40duppo;
1723 + u8 sar2g;
1724 + u8 sar5g;
1725 };
1726
1727 /* Information about the PCB the circuitry is soldered on. */
1728 struct ssb_boardinfo {
1729 u16 vendor;
1730 u16 type;
1731 - u16 rev;
1732 + u8 rev;
1733 };
1734
1735
1736 @@ -229,10 +318,9 @@ struct ssb_driver {
1737 #define drv_to_ssb_drv(_drv) container_of(_drv, struct ssb_driver, drv)
1738
1739 extern int __ssb_driver_register(struct ssb_driver *drv, struct module *owner);
1740 -static inline int ssb_driver_register(struct ssb_driver *drv)
1741 -{
1742 - return __ssb_driver_register(drv, THIS_MODULE);
1743 -}
1744 +#define ssb_driver_register(drv) \
1745 + __ssb_driver_register(drv, THIS_MODULE)
1746 +
1747 extern void ssb_driver_unregister(struct ssb_driver *drv);
1748
1749
1750 @@ -308,7 +396,7 @@ struct ssb_bus {
1751
1752 /* ID information about the Chip. */
1753 u16 chip_id;
1754 - u16 chip_rev;
1755 + u8 chip_rev;
1756 u16 sprom_offset;
1757 u16 sprom_size; /* number of words in sprom */
1758 u8 chip_package;
1759 @@ -404,7 +492,9 @@ extern bool ssb_is_sprom_available(struc
1760
1761 /* Set a fallback SPROM.
1762 * See kdoc at the function definition for complete documentation. */
1763 -extern int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom);
1764 +extern int ssb_arch_register_fallback_sprom(
1765 + int (*sprom_callback)(struct ssb_bus *bus,
1766 + struct ssb_sprom *out));
1767
1768 /* Suspend a SSB bus.
1769 * Call this from the parent bus suspend routine. */
1770 @@ -518,6 +608,7 @@ extern int ssb_bus_may_powerdown(struct
1771 * Otherwise static always-on powercontrol will be used. */
1772 extern int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl);
1773
1774 +extern void ssb_commit_settings(struct ssb_bus *bus);
1775
1776 /* Various helper functions */
1777 extern u32 ssb_admatch_base(u32 adm);
1778 --- a/include/linux/ssb/ssb_driver_chipcommon.h
1779 +++ b/include/linux/ssb/ssb_driver_chipcommon.h
1780 @@ -8,7 +8,7 @@
1781 * gpio interface, extbus, and support for serial and parallel flashes.
1782 *
1783 * Copyright 2005, Broadcom Corporation
1784 - * Copyright 2006, Michael Buesch <mb@bu3sch.de>
1785 + * Copyright 2006, Michael Buesch <m@bues.ch>
1786 *
1787 * Licensed under the GPL version 2. See COPYING for details.
1788 */
1789 @@ -123,6 +123,8 @@
1790 #define SSB_CHIPCO_FLASHDATA 0x0048
1791 #define SSB_CHIPCO_BCAST_ADDR 0x0050
1792 #define SSB_CHIPCO_BCAST_DATA 0x0054
1793 +#define SSB_CHIPCO_GPIOPULLUP 0x0058 /* Rev >= 20 only */
1794 +#define SSB_CHIPCO_GPIOPULLDOWN 0x005C /* Rev >= 20 only */
1795 #define SSB_CHIPCO_GPIOIN 0x0060
1796 #define SSB_CHIPCO_GPIOOUT 0x0064
1797 #define SSB_CHIPCO_GPIOOUTEN 0x0068
1798 @@ -131,6 +133,9 @@
1799 #define SSB_CHIPCO_GPIOIRQ 0x0074
1800 #define SSB_CHIPCO_WATCHDOG 0x0080
1801 #define SSB_CHIPCO_GPIOTIMER 0x0088 /* LED powersave (corerev >= 16) */
1802 +#define SSB_CHIPCO_GPIOTIMER_OFFTIME 0x0000FFFF
1803 +#define SSB_CHIPCO_GPIOTIMER_OFFTIME_SHIFT 0
1804 +#define SSB_CHIPCO_GPIOTIMER_ONTIME 0xFFFF0000
1805 #define SSB_CHIPCO_GPIOTIMER_ONTIME_SHIFT 16
1806 #define SSB_CHIPCO_GPIOTOUTM 0x008C /* LED powersave (corerev >= 16) */
1807 #define SSB_CHIPCO_CLOCK_N 0x0090
1808 @@ -189,8 +194,10 @@
1809 #define SSB_CHIPCO_CLKCTLST_HAVEALPREQ 0x00000008 /* ALP available request */
1810 #define SSB_CHIPCO_CLKCTLST_HAVEHTREQ 0x00000010 /* HT available request */
1811 #define SSB_CHIPCO_CLKCTLST_HWCROFF 0x00000020 /* Force HW clock request off */
1812 -#define SSB_CHIPCO_CLKCTLST_HAVEHT 0x00010000 /* HT available */
1813 -#define SSB_CHIPCO_CLKCTLST_HAVEALP 0x00020000 /* APL available */
1814 +#define SSB_CHIPCO_CLKCTLST_HAVEALP 0x00010000 /* ALP available */
1815 +#define SSB_CHIPCO_CLKCTLST_HAVEHT 0x00020000 /* HT available */
1816 +#define SSB_CHIPCO_CLKCTLST_4328A0_HAVEHT 0x00010000 /* 4328a0 has reversed bits */
1817 +#define SSB_CHIPCO_CLKCTLST_4328A0_HAVEALP 0x00020000 /* 4328a0 has reversed bits */
1818 #define SSB_CHIPCO_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */
1819 #define SSB_CHIPCO_UART0_DATA 0x0300
1820 #define SSB_CHIPCO_UART0_IMR 0x0304
1821 --- a/drivers/ssb/b43_pci_bridge.c
1822 +++ b/drivers/ssb/b43_pci_bridge.c
1823 @@ -5,12 +5,13 @@
1824 * because of its small size we include it in the SSB core
1825 * instead of creating a standalone module.
1826 *
1827 - * Copyright 2007 Michael Buesch <mb@bu3sch.de>
1828 + * Copyright 2007 Michael Buesch <m@bues.ch>
1829 *
1830 * Licensed under the GNU/GPL. See COPYING for details.
1831 */
1832
1833 #include <linux/pci.h>
1834 +#include <linux/module.h>
1835 #include <linux/ssb/ssb.h>
1836
1837 #include "ssb_private.h"
1838 --- a/drivers/ssb/driver_extif.c
1839 +++ b/drivers/ssb/driver_extif.c
1840 @@ -3,7 +3,7 @@
1841 * Broadcom EXTIF core driver
1842 *
1843 * Copyright 2005, Broadcom Corporation
1844 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
1845 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
1846 * Copyright 2006, 2007, Felix Fietkau <nbd@openwrt.org>
1847 * Copyright 2007, Aurelien Jarno <aurelien@aurel32.net>
1848 *
1849 --- a/drivers/ssb/driver_mipscore.c
1850 +++ b/drivers/ssb/driver_mipscore.c
1851 @@ -3,7 +3,7 @@
1852 * Broadcom MIPS core driver
1853 *
1854 * Copyright 2005, Broadcom Corporation
1855 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
1856 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
1857 *
1858 * Licensed under the GNU/GPL. See COPYING for details.
1859 */
1860 @@ -208,6 +208,9 @@ u32 ssb_cpu_clock(struct ssb_mipscore *m
1861 struct ssb_bus *bus = mcore->dev->bus;
1862 u32 pll_type, n, m, rate = 0;
1863
1864 + if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
1865 + return ssb_pmu_get_cpu_clock(&bus->chipco);
1866 +
1867 if (bus->extif.dev) {
1868 ssb_extif_get_clockcontrol(&bus->extif, &pll_type, &n, &m);
1869 } else if (bus->chipco.dev) {
1870 --- a/drivers/ssb/embedded.c
1871 +++ b/drivers/ssb/embedded.c
1872 @@ -3,7 +3,7 @@
1873 * Embedded systems support code
1874 *
1875 * Copyright 2005-2008, Broadcom Corporation
1876 - * Copyright 2006-2008, Michael Buesch <mb@bu3sch.de>
1877 + * Copyright 2006-2008, Michael Buesch <m@bues.ch>
1878 *
1879 * Licensed under the GNU/GPL. See COPYING for details.
1880 */
1881 --- a/drivers/ssb/pcmcia.c
1882 +++ b/drivers/ssb/pcmcia.c
1883 @@ -3,7 +3,7 @@
1884 * PCMCIA-Hostbus related functions
1885 *
1886 * Copyright 2006 Johannes Berg <johannes@sipsolutions.net>
1887 - * Copyright 2007-2008 Michael Buesch <mb@bu3sch.de>
1888 + * Copyright 2007-2008 Michael Buesch <m@bues.ch>
1889 *
1890 * Licensed under the GNU/GPL. See COPYING for details.
1891 */
1892 @@ -676,14 +676,10 @@ static int ssb_pcmcia_do_get_invariants(
1893 case SSB_PCMCIA_CIS_ANTGAIN:
1894 GOTO_ERROR_ON(tuple->TupleDataLen != 2,
1895 "antg tpl size");
1896 - sprom->antenna_gain.ghz24.a0 = tuple->TupleData[1];
1897 - sprom->antenna_gain.ghz24.a1 = tuple->TupleData[1];
1898 - sprom->antenna_gain.ghz24.a2 = tuple->TupleData[1];
1899 - sprom->antenna_gain.ghz24.a3 = tuple->TupleData[1];
1900 - sprom->antenna_gain.ghz5.a0 = tuple->TupleData[1];
1901 - sprom->antenna_gain.ghz5.a1 = tuple->TupleData[1];
1902 - sprom->antenna_gain.ghz5.a2 = tuple->TupleData[1];
1903 - sprom->antenna_gain.ghz5.a3 = tuple->TupleData[1];
1904 + sprom->antenna_gain.a0 = tuple->TupleData[1];
1905 + sprom->antenna_gain.a1 = tuple->TupleData[1];
1906 + sprom->antenna_gain.a2 = tuple->TupleData[1];
1907 + sprom->antenna_gain.a3 = tuple->TupleData[1];
1908 break;
1909 case SSB_PCMCIA_CIS_BFLAGS:
1910 GOTO_ERROR_ON((tuple->TupleDataLen != 3) &&
1911 --- a/drivers/ssb/sdio.c
1912 +++ b/drivers/ssb/sdio.c
1913 @@ -6,7 +6,7 @@
1914 *
1915 * Based on drivers/ssb/pcmcia.c
1916 * Copyright 2006 Johannes Berg <johannes@sipsolutions.net>
1917 - * Copyright 2007-2008 Michael Buesch <mb@bu3sch.de>
1918 + * Copyright 2007-2008 Michael Buesch <m@bues.ch>
1919 *
1920 * Licensed under the GNU/GPL. See COPYING for details.
1921 *
1922 @@ -551,14 +551,10 @@ int ssb_sdio_get_invariants(struct ssb_b
1923 case SSB_SDIO_CIS_ANTGAIN:
1924 GOTO_ERROR_ON(tuple->size != 2,
1925 "antg tpl size");
1926 - sprom->antenna_gain.ghz24.a0 = tuple->data[1];
1927 - sprom->antenna_gain.ghz24.a1 = tuple->data[1];
1928 - sprom->antenna_gain.ghz24.a2 = tuple->data[1];
1929 - sprom->antenna_gain.ghz24.a3 = tuple->data[1];
1930 - sprom->antenna_gain.ghz5.a0 = tuple->data[1];
1931 - sprom->antenna_gain.ghz5.a1 = tuple->data[1];
1932 - sprom->antenna_gain.ghz5.a2 = tuple->data[1];
1933 - sprom->antenna_gain.ghz5.a3 = tuple->data[1];
1934 + sprom->antenna_gain.a0 = tuple->data[1];
1935 + sprom->antenna_gain.a1 = tuple->data[1];
1936 + sprom->antenna_gain.a2 = tuple->data[1];
1937 + sprom->antenna_gain.a3 = tuple->data[1];
1938 break;
1939 case SSB_SDIO_CIS_BFLAGS:
1940 GOTO_ERROR_ON((tuple->size != 3) &&
1941 --- a/include/linux/ssb/ssb_driver_gige.h
1942 +++ b/include/linux/ssb/ssb_driver_gige.h
1943 @@ -2,6 +2,7 @@
1944 #define LINUX_SSB_DRIVER_GIGE_H_
1945
1946 #include <linux/ssb/ssb.h>
1947 +#include <linux/bug.h>
1948 #include <linux/pci.h>
1949 #include <linux/spinlock.h>
1950
Staging tree of Zoltan Herpai