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kernel: update bcma and ssb to version master-2011-12-16 from wireless-testing
[openwrt/svn-archive/archive.git] / target / linux / generic / patches-2.6.38 / 020-ssb_update.patch
1 --- a/drivers/ssb/main.c
2 +++ b/drivers/ssb/main.c
3 @@ -3,7 +3,7 @@
4 * Subsystem core
5 *
6 * Copyright 2005, Broadcom Corporation
7 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
8 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
9 *
10 * Licensed under the GNU/GPL. See COPYING for details.
11 */
12 @@ -12,6 +12,7 @@
13
14 #include <linux/delay.h>
15 #include <linux/io.h>
16 +#include <linux/module.h>
17 #include <linux/ssb/ssb.h>
18 #include <linux/ssb/ssb_regs.h>
19 #include <linux/ssb/ssb_driver_gige.h>
20 @@ -557,7 +558,7 @@ error:
21 }
22
23 /* Needs ssb_buses_lock() */
24 -static int ssb_attach_queued_buses(void)
25 +static int __devinit ssb_attach_queued_buses(void)
26 {
27 struct ssb_bus *bus, *n;
28 int err = 0;
29 @@ -768,9 +769,9 @@ out:
30 return err;
31 }
32
33 -static int ssb_bus_register(struct ssb_bus *bus,
34 - ssb_invariants_func_t get_invariants,
35 - unsigned long baseaddr)
36 +static int __devinit ssb_bus_register(struct ssb_bus *bus,
37 + ssb_invariants_func_t get_invariants,
38 + unsigned long baseaddr)
39 {
40 int err;
41
42 @@ -851,8 +852,8 @@ err_disable_xtal:
43 }
44
45 #ifdef CONFIG_SSB_PCIHOST
46 -int ssb_bus_pcibus_register(struct ssb_bus *bus,
47 - struct pci_dev *host_pci)
48 +int __devinit ssb_bus_pcibus_register(struct ssb_bus *bus,
49 + struct pci_dev *host_pci)
50 {
51 int err;
52
53 @@ -875,9 +876,9 @@ EXPORT_SYMBOL(ssb_bus_pcibus_register);
54 #endif /* CONFIG_SSB_PCIHOST */
55
56 #ifdef CONFIG_SSB_PCMCIAHOST
57 -int ssb_bus_pcmciabus_register(struct ssb_bus *bus,
58 - struct pcmcia_device *pcmcia_dev,
59 - unsigned long baseaddr)
60 +int __devinit ssb_bus_pcmciabus_register(struct ssb_bus *bus,
61 + struct pcmcia_device *pcmcia_dev,
62 + unsigned long baseaddr)
63 {
64 int err;
65
66 @@ -897,8 +898,9 @@ EXPORT_SYMBOL(ssb_bus_pcmciabus_register
67 #endif /* CONFIG_SSB_PCMCIAHOST */
68
69 #ifdef CONFIG_SSB_SDIOHOST
70 -int ssb_bus_sdiobus_register(struct ssb_bus *bus, struct sdio_func *func,
71 - unsigned int quirks)
72 +int __devinit ssb_bus_sdiobus_register(struct ssb_bus *bus,
73 + struct sdio_func *func,
74 + unsigned int quirks)
75 {
76 int err;
77
78 @@ -918,9 +920,9 @@ int ssb_bus_sdiobus_register(struct ssb_
79 EXPORT_SYMBOL(ssb_bus_sdiobus_register);
80 #endif /* CONFIG_SSB_PCMCIAHOST */
81
82 -int ssb_bus_ssbbus_register(struct ssb_bus *bus,
83 - unsigned long baseaddr,
84 - ssb_invariants_func_t get_invariants)
85 +int __devinit ssb_bus_ssbbus_register(struct ssb_bus *bus,
86 + unsigned long baseaddr,
87 + ssb_invariants_func_t get_invariants)
88 {
89 int err;
90
91 @@ -1001,8 +1003,8 @@ u32 ssb_calc_clock_rate(u32 plltype, u32
92 switch (plltype) {
93 case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
94 if (m & SSB_CHIPCO_CLK_T6_MMASK)
95 - return SSB_CHIPCO_CLK_T6_M0;
96 - return SSB_CHIPCO_CLK_T6_M1;
97 + return SSB_CHIPCO_CLK_T6_M1;
98 + return SSB_CHIPCO_CLK_T6_M0;
99 case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
100 case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
101 case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
102 @@ -1117,23 +1119,22 @@ static u32 ssb_tmslow_reject_bitmask(str
103 {
104 u32 rev = ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_SSBREV;
105
106 - /* The REJECT bit changed position in TMSLOW between
107 - * Backplane revisions. */
108 + /* The REJECT bit seems to be different for Backplane rev 2.3 */
109 switch (rev) {
110 case SSB_IDLOW_SSBREV_22:
111 - return SSB_TMSLOW_REJECT_22;
112 + case SSB_IDLOW_SSBREV_24:
113 + case SSB_IDLOW_SSBREV_26:
114 + return SSB_TMSLOW_REJECT;
115 case SSB_IDLOW_SSBREV_23:
116 return SSB_TMSLOW_REJECT_23;
117 - case SSB_IDLOW_SSBREV_24: /* TODO - find the proper REJECT bits */
118 - case SSB_IDLOW_SSBREV_25: /* same here */
119 - case SSB_IDLOW_SSBREV_26: /* same here */
120 + case SSB_IDLOW_SSBREV_25: /* TODO - find the proper REJECT bit */
121 case SSB_IDLOW_SSBREV_27: /* same here */
122 - return SSB_TMSLOW_REJECT_23; /* this is a guess */
123 + return SSB_TMSLOW_REJECT; /* this is a guess */
124 default:
125 printk(KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
126 WARN_ON(1);
127 }
128 - return (SSB_TMSLOW_REJECT_22 | SSB_TMSLOW_REJECT_23);
129 + return (SSB_TMSLOW_REJECT | SSB_TMSLOW_REJECT_23);
130 }
131
132 int ssb_device_is_enabled(struct ssb_device *dev)
133 @@ -1192,10 +1193,10 @@ void ssb_device_enable(struct ssb_device
134 }
135 EXPORT_SYMBOL(ssb_device_enable);
136
137 -/* Wait for a bit in a register to get set or unset.
138 +/* Wait for bitmask in a register to get set or cleared.
139 * timeout is in units of ten-microseconds */
140 -static int ssb_wait_bit(struct ssb_device *dev, u16 reg, u32 bitmask,
141 - int timeout, int set)
142 +static int ssb_wait_bits(struct ssb_device *dev, u16 reg, u32 bitmask,
143 + int timeout, int set)
144 {
145 int i;
146 u32 val;
147 @@ -1203,7 +1204,7 @@ static int ssb_wait_bit(struct ssb_devic
148 for (i = 0; i < timeout; i++) {
149 val = ssb_read32(dev, reg);
150 if (set) {
151 - if (val & bitmask)
152 + if ((val & bitmask) == bitmask)
153 return 0;
154 } else {
155 if (!(val & bitmask))
156 @@ -1220,20 +1221,38 @@ static int ssb_wait_bit(struct ssb_devic
157
158 void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags)
159 {
160 - u32 reject;
161 + u32 reject, val;
162
163 if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_RESET)
164 return;
165
166 reject = ssb_tmslow_reject_bitmask(dev);
167 - ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK);
168 - ssb_wait_bit(dev, SSB_TMSLOW, reject, 1000, 1);
169 - ssb_wait_bit(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
170 - ssb_write32(dev, SSB_TMSLOW,
171 - SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
172 - reject | SSB_TMSLOW_RESET |
173 - core_specific_flags);
174 - ssb_flush_tmslow(dev);
175 +
176 + if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_CLOCK) {
177 + ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK);
178 + ssb_wait_bits(dev, SSB_TMSLOW, reject, 1000, 1);
179 + ssb_wait_bits(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
180 +
181 + if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
182 + val = ssb_read32(dev, SSB_IMSTATE);
183 + val |= SSB_IMSTATE_REJECT;
184 + ssb_write32(dev, SSB_IMSTATE, val);
185 + ssb_wait_bits(dev, SSB_IMSTATE, SSB_IMSTATE_BUSY, 1000,
186 + 0);
187 + }
188 +
189 + ssb_write32(dev, SSB_TMSLOW,
190 + SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
191 + reject | SSB_TMSLOW_RESET |
192 + core_specific_flags);
193 + ssb_flush_tmslow(dev);
194 +
195 + if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
196 + val = ssb_read32(dev, SSB_IMSTATE);
197 + val &= ~SSB_IMSTATE_REJECT;
198 + ssb_write32(dev, SSB_IMSTATE, val);
199 + }
200 + }
201
202 ssb_write32(dev, SSB_TMSLOW,
203 reject | SSB_TMSLOW_RESET |
204 @@ -1242,13 +1261,34 @@ void ssb_device_disable(struct ssb_devic
205 }
206 EXPORT_SYMBOL(ssb_device_disable);
207
208 +/* Some chipsets need routing known for PCIe and 64-bit DMA */
209 +static bool ssb_dma_translation_special_bit(struct ssb_device *dev)
210 +{
211 + u16 chip_id = dev->bus->chip_id;
212 +
213 + if (dev->id.coreid == SSB_DEV_80211) {
214 + return (chip_id == 0x4322 || chip_id == 43221 ||
215 + chip_id == 43231 || chip_id == 43222);
216 + }
217 +
218 + return 0;
219 +}
220 +
221 u32 ssb_dma_translation(struct ssb_device *dev)
222 {
223 switch (dev->bus->bustype) {
224 case SSB_BUSTYPE_SSB:
225 return 0;
226 case SSB_BUSTYPE_PCI:
227 - return SSB_PCI_DMA;
228 + if (pci_is_pcie(dev->bus->host_pci) &&
229 + ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_DMA64) {
230 + return SSB_PCIE_DMA_H32;
231 + } else {
232 + if (ssb_dma_translation_special_bit(dev))
233 + return SSB_PCIE_DMA_H32;
234 + else
235 + return SSB_PCI_DMA;
236 + }
237 default:
238 __ssb_dma_not_implemented(dev);
239 }
240 @@ -1291,20 +1331,20 @@ EXPORT_SYMBOL(ssb_bus_may_powerdown);
241
242 int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl)
243 {
244 - struct ssb_chipcommon *cc;
245 int err;
246 enum ssb_clkmode mode;
247
248 err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
249 if (err)
250 goto error;
251 - cc = &bus->chipco;
252 - mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
253 - ssb_chipco_set_clockmode(cc, mode);
254
255 #ifdef CONFIG_SSB_DEBUG
256 bus->powered_up = 1;
257 #endif
258 +
259 + mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
260 + ssb_chipco_set_clockmode(&bus->chipco, mode);
261 +
262 return 0;
263 error:
264 ssb_printk(KERN_ERR PFX "Bus powerup failed\n");
265 @@ -1312,6 +1352,37 @@ error:
266 }
267 EXPORT_SYMBOL(ssb_bus_powerup);
268
269 +static void ssb_broadcast_value(struct ssb_device *dev,
270 + u32 address, u32 data)
271 +{
272 +#ifdef CONFIG_SSB_DRIVER_PCICORE
273 + /* This is used for both, PCI and ChipCommon core, so be careful. */
274 + BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
275 + BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
276 +#endif
277 +
278 + ssb_write32(dev, SSB_CHIPCO_BCAST_ADDR, address);
279 + ssb_read32(dev, SSB_CHIPCO_BCAST_ADDR); /* flush */
280 + ssb_write32(dev, SSB_CHIPCO_BCAST_DATA, data);
281 + ssb_read32(dev, SSB_CHIPCO_BCAST_DATA); /* flush */
282 +}
283 +
284 +void ssb_commit_settings(struct ssb_bus *bus)
285 +{
286 + struct ssb_device *dev;
287 +
288 +#ifdef CONFIG_SSB_DRIVER_PCICORE
289 + dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
290 +#else
291 + dev = bus->chipco.dev;
292 +#endif
293 + if (WARN_ON(!dev))
294 + return;
295 + /* This forces an update of the cached registers. */
296 + ssb_broadcast_value(dev, 0xFD8, 0);
297 +}
298 +EXPORT_SYMBOL(ssb_commit_settings);
299 +
300 u32 ssb_admatch_base(u32 adm)
301 {
302 u32 base = 0;
303 --- a/drivers/ssb/pci.c
304 +++ b/drivers/ssb/pci.c
305 @@ -1,7 +1,7 @@
306 /*
307 * Sonics Silicon Backplane PCI-Hostbus related functions.
308 *
309 - * Copyright (C) 2005-2006 Michael Buesch <mb@bu3sch.de>
310 + * Copyright (C) 2005-2006 Michael Buesch <m@bues.ch>
311 * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
312 * Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
313 * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
314 @@ -468,10 +468,14 @@ static void sprom_extract_r45(struct ssb
315 SPEX(country_code, SSB_SPROM4_CCODE, 0xFFFF, 0);
316 SPEX(boardflags_lo, SSB_SPROM4_BFLLO, 0xFFFF, 0);
317 SPEX(boardflags_hi, SSB_SPROM4_BFLHI, 0xFFFF, 0);
318 + SPEX(boardflags2_lo, SSB_SPROM4_BFL2LO, 0xFFFF, 0);
319 + SPEX(boardflags2_hi, SSB_SPROM4_BFL2HI, 0xFFFF, 0);
320 } else {
321 SPEX(country_code, SSB_SPROM5_CCODE, 0xFFFF, 0);
322 SPEX(boardflags_lo, SSB_SPROM5_BFLLO, 0xFFFF, 0);
323 SPEX(boardflags_hi, SSB_SPROM5_BFLHI, 0xFFFF, 0);
324 + SPEX(boardflags2_lo, SSB_SPROM5_BFL2LO, 0xFFFF, 0);
325 + SPEX(boardflags2_hi, SSB_SPROM5_BFL2HI, 0xFFFF, 0);
326 }
327 SPEX(ant_available_a, SSB_SPROM4_ANTAVAIL, SSB_SPROM4_ANTAVAIL_A,
328 SSB_SPROM4_ANTAVAIL_A_SHIFT);
329 @@ -603,6 +607,29 @@ static void sprom_extract_r8(struct ssb_
330 memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
331 sizeof(out->antenna_gain.ghz5));
332
333 + /* Extract FEM info */
334 + SPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G,
335 + SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
336 + SPEX(fem.ghz2.extpa_gain, SSB_SPROM8_FEM2G,
337 + SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
338 + SPEX(fem.ghz2.pdet_range, SSB_SPROM8_FEM2G,
339 + SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);
340 + SPEX(fem.ghz2.tr_iso, SSB_SPROM8_FEM2G,
341 + SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);
342 + SPEX(fem.ghz2.antswlut, SSB_SPROM8_FEM2G,
343 + SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
344 +
345 + SPEX(fem.ghz5.tssipos, SSB_SPROM8_FEM5G,
346 + SSB_SROM8_FEM_TSSIPOS, SSB_SROM8_FEM_TSSIPOS_SHIFT);
347 + SPEX(fem.ghz5.extpa_gain, SSB_SPROM8_FEM5G,
348 + SSB_SROM8_FEM_EXTPA_GAIN, SSB_SROM8_FEM_EXTPA_GAIN_SHIFT);
349 + SPEX(fem.ghz5.pdet_range, SSB_SPROM8_FEM5G,
350 + SSB_SROM8_FEM_PDET_RANGE, SSB_SROM8_FEM_PDET_RANGE_SHIFT);
351 + SPEX(fem.ghz5.tr_iso, SSB_SPROM8_FEM5G,
352 + SSB_SROM8_FEM_TR_ISO, SSB_SROM8_FEM_TR_ISO_SHIFT);
353 + SPEX(fem.ghz5.antswlut, SSB_SPROM8_FEM5G,
354 + SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
355 +
356 sprom_extract_r458(out, in);
357
358 /* TODO - get remaining rev 8 stuff needed */
359 @@ -641,7 +668,7 @@ static int sprom_extract(struct ssb_bus
360 break;
361 default:
362 ssb_printk(KERN_WARNING PFX "Unsupported SPROM"
363 - " revision %d detected. Will extract"
364 + " revision %d detected. Will extract"
365 " v1\n", out->revision);
366 out->revision = 1;
367 sprom_extract_r123(out, in);
368 @@ -658,7 +685,6 @@ static int sprom_extract(struct ssb_bus
369 static int ssb_pci_sprom_get(struct ssb_bus *bus,
370 struct ssb_sprom *sprom)
371 {
372 - const struct ssb_sprom *fallback;
373 int err;
374 u16 *buf;
375
376 @@ -666,7 +692,7 @@ static int ssb_pci_sprom_get(struct ssb_
377 ssb_printk(KERN_ERR PFX "No SPROM available!\n");
378 return -ENODEV;
379 }
380 - if (bus->chipco.dev) { /* can be unavailible! */
381 + if (bus->chipco.dev) { /* can be unavailable! */
382 /*
383 * get SPROM offset: SSB_SPROM_BASE1 except for
384 * chipcommon rev >= 31 or chip ID is 0x4312 and
385 @@ -703,10 +729,17 @@ static int ssb_pci_sprom_get(struct ssb_
386 if (err) {
387 /* All CRC attempts failed.
388 * Maybe there is no SPROM on the device?
389 - * If we have a fallback, use that. */
390 - fallback = ssb_get_fallback_sprom();
391 - if (fallback) {
392 - memcpy(sprom, fallback, sizeof(*sprom));
393 + * Now we ask the arch code if there is some sprom
394 + * available for this device in some other storage */
395 + err = ssb_fill_sprom_with_fallback(bus, sprom);
396 + if (err) {
397 + ssb_printk(KERN_WARNING PFX "WARNING: Using"
398 + " fallback SPROM failed (err %d)\n",
399 + err);
400 + } else {
401 + ssb_dprintk(KERN_DEBUG PFX "Using SPROM"
402 + " revision %d provided by"
403 + " platform.\n", sprom->revision);
404 err = 0;
405 goto out_free;
406 }
407 @@ -724,12 +757,9 @@ out_free:
408 static void ssb_pci_get_boardinfo(struct ssb_bus *bus,
409 struct ssb_boardinfo *bi)
410 {
411 - pci_read_config_word(bus->host_pci, PCI_SUBSYSTEM_VENDOR_ID,
412 - &bi->vendor);
413 - pci_read_config_word(bus->host_pci, PCI_SUBSYSTEM_ID,
414 - &bi->type);
415 - pci_read_config_word(bus->host_pci, PCI_REVISION_ID,
416 - &bi->rev);
417 + bi->vendor = bus->host_pci->subsystem_vendor;
418 + bi->type = bus->host_pci->subsystem_device;
419 + bi->rev = bus->host_pci->revision;
420 }
421
422 int ssb_pci_get_invariants(struct ssb_bus *bus,
423 --- a/include/linux/ssb/ssb_regs.h
424 +++ b/include/linux/ssb/ssb_regs.h
425 @@ -85,6 +85,8 @@
426 #define SSB_IMSTATE_AP_RSV 0x00000030 /* Reserved */
427 #define SSB_IMSTATE_IBE 0x00020000 /* In Band Error */
428 #define SSB_IMSTATE_TO 0x00040000 /* Timeout */
429 +#define SSB_IMSTATE_BUSY 0x01800000 /* Busy (Backplane rev >= 2.3 only) */
430 +#define SSB_IMSTATE_REJECT 0x02000000 /* Reject (Backplane rev >= 2.3 only) */
431 #define SSB_INTVEC 0x0F94 /* SB Interrupt Mask */
432 #define SSB_INTVEC_PCI 0x00000001 /* Enable interrupts for PCI */
433 #define SSB_INTVEC_ENET0 0x00000002 /* Enable interrupts for enet 0 */
434 @@ -95,9 +97,8 @@
435 #define SSB_INTVEC_ENET1 0x00000040 /* Enable interrupts for enet 1 */
436 #define SSB_TMSLOW 0x0F98 /* SB Target State Low */
437 #define SSB_TMSLOW_RESET 0x00000001 /* Reset */
438 -#define SSB_TMSLOW_REJECT_22 0x00000002 /* Reject (Backplane rev 2.2) */
439 +#define SSB_TMSLOW_REJECT 0x00000002 /* Reject (Standard Backplane) */
440 #define SSB_TMSLOW_REJECT_23 0x00000004 /* Reject (Backplane rev 2.3) */
441 -#define SSB_TMSLOW_PHYCLK 0x00000010 /* MAC PHY Clock Control Enable */
442 #define SSB_TMSLOW_CLOCK 0x00010000 /* Clock Enable */
443 #define SSB_TMSLOW_FGC 0x00020000 /* Force Gated Clocks On */
444 #define SSB_TMSLOW_PE 0x40000000 /* Power Management Enable */
445 @@ -268,6 +269,8 @@
446 /* SPROM Revision 4 */
447 #define SSB_SPROM4_BFLLO 0x0044 /* Boardflags (low 16 bits) */
448 #define SSB_SPROM4_BFLHI 0x0046 /* Board Flags Hi */
449 +#define SSB_SPROM4_BFL2LO 0x0048 /* Board flags 2 (low 16 bits) */
450 +#define SSB_SPROM4_BFL2HI 0x004A /* Board flags 2 Hi */
451 #define SSB_SPROM4_IL0MAC 0x004C /* 6 byte MAC address for a/b/g/n */
452 #define SSB_SPROM4_CCODE 0x0052 /* Country Code (2 bytes) */
453 #define SSB_SPROM4_GPIOA 0x0056 /* Gen. Purpose IO # 0 and 1 */
454 @@ -358,6 +361,8 @@
455 #define SSB_SPROM5_CCODE 0x0044 /* Country Code (2 bytes) */
456 #define SSB_SPROM5_BFLLO 0x004A /* Boardflags (low 16 bits) */
457 #define SSB_SPROM5_BFLHI 0x004C /* Board Flags Hi */
458 +#define SSB_SPROM5_BFL2LO 0x004E /* Board flags 2 (low 16 bits) */
459 +#define SSB_SPROM5_BFL2HI 0x0050 /* Board flags 2 Hi */
460 #define SSB_SPROM5_IL0MAC 0x0052 /* 6 byte MAC address for a/b/g/n */
461 #define SSB_SPROM5_GPIOA 0x0076 /* Gen. Purpose IO # 0 and 1 */
462 #define SSB_SPROM5_GPIOA_P0 0x00FF /* Pin 0 */
463 @@ -427,6 +432,23 @@
464 #define SSB_SPROM8_RXPO2G 0x00FF /* 2GHz RX power offset */
465 #define SSB_SPROM8_RXPO5G 0xFF00 /* 5GHz RX power offset */
466 #define SSB_SPROM8_RXPO5G_SHIFT 8
467 +#define SSB_SPROM8_FEM2G 0x00AE
468 +#define SSB_SPROM8_FEM5G 0x00B0
469 +#define SSB_SROM8_FEM_TSSIPOS 0x0001
470 +#define SSB_SROM8_FEM_TSSIPOS_SHIFT 0
471 +#define SSB_SROM8_FEM_EXTPA_GAIN 0x0006
472 +#define SSB_SROM8_FEM_EXTPA_GAIN_SHIFT 1
473 +#define SSB_SROM8_FEM_PDET_RANGE 0x00F8
474 +#define SSB_SROM8_FEM_PDET_RANGE_SHIFT 3
475 +#define SSB_SROM8_FEM_TR_ISO 0x0700
476 +#define SSB_SROM8_FEM_TR_ISO_SHIFT 8
477 +#define SSB_SROM8_FEM_ANTSWLUT 0xF800
478 +#define SSB_SROM8_FEM_ANTSWLUT_SHIFT 11
479 +#define SSB_SPROM8_THERMAL 0x00B2
480 +#define SSB_SPROM8_MPWR_RAWTS 0x00B4
481 +#define SSB_SPROM8_TS_SLP_OPT_CORRX 0x00B6
482 +#define SSB_SPROM8_FOC_HWIQ_IQSWP 0x00B8
483 +#define SSB_SPROM8_PHYCAL_TEMPDELTA 0x00BA
484 #define SSB_SPROM8_MAXP_BG 0x00C0 /* Max Power 2GHz in path 1 */
485 #define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */
486 #define SSB_SPROM8_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
487 @@ -457,6 +479,46 @@
488 #define SSB_SPROM8_OFDM5GLPO 0x014A /* 5.2GHz OFDM power offset */
489 #define SSB_SPROM8_OFDM5GHPO 0x014E /* 5.8GHz OFDM power offset */
490
491 +/* Values for boardflags_lo read from SPROM */
492 +#define SSB_BFL_BTCOEXIST 0x0001 /* implements Bluetooth coexistance */
493 +#define SSB_BFL_PACTRL 0x0002 /* GPIO 9 controlling the PA */
494 +#define SSB_BFL_AIRLINEMODE 0x0004 /* implements GPIO 13 radio disable indication */
495 +#define SSB_BFL_RSSI 0x0008 /* software calculates nrssi slope. */
496 +#define SSB_BFL_ENETSPI 0x0010 /* has ephy roboswitch spi */
497 +#define SSB_BFL_XTAL_NOSLOW 0x0020 /* no slow clock available */
498 +#define SSB_BFL_CCKHIPWR 0x0040 /* can do high power CCK transmission */
499 +#define SSB_BFL_ENETADM 0x0080 /* has ADMtek switch */
500 +#define SSB_BFL_ENETVLAN 0x0100 /* can do vlan */
501 +#define SSB_BFL_AFTERBURNER 0x0200 /* supports Afterburner mode */
502 +#define SSB_BFL_NOPCI 0x0400 /* board leaves PCI floating */
503 +#define SSB_BFL_FEM 0x0800 /* supports the Front End Module */
504 +#define SSB_BFL_EXTLNA 0x1000 /* has an external LNA */
505 +#define SSB_BFL_HGPA 0x2000 /* had high gain PA */
506 +#define SSB_BFL_BTCMOD 0x4000 /* BFL_BTCOEXIST is given in alternate GPIOs */
507 +#define SSB_BFL_ALTIQ 0x8000 /* alternate I/Q settings */
508 +
509 +/* Values for boardflags_hi read from SPROM */
510 +#define SSB_BFH_NOPA 0x0001 /* has no PA */
511 +#define SSB_BFH_RSSIINV 0x0002 /* RSSI uses positive slope (not TSSI) */
512 +#define SSB_BFH_PAREF 0x0004 /* uses the PARef LDO */
513 +#define SSB_BFH_3TSWITCH 0x0008 /* uses a triple throw switch shared with bluetooth */
514 +#define SSB_BFH_PHASESHIFT 0x0010 /* can support phase shifter */
515 +#define SSB_BFH_BUCKBOOST 0x0020 /* has buck/booster */
516 +#define SSB_BFH_FEM_BT 0x0040 /* has FEM and switch to share antenna with bluetooth */
517 +
518 +/* Values for boardflags2_lo read from SPROM */
519 +#define SSB_BFL2_RXBB_INT_REG_DIS 0x0001 /* external RX BB regulator present */
520 +#define SSB_BFL2_APLL_WAR 0x0002 /* alternative A-band PLL settings implemented */
521 +#define SSB_BFL2_TXPWRCTRL_EN 0x0004 /* permits enabling TX Power Control */
522 +#define SSB_BFL2_2X4_DIV 0x0008 /* 2x4 diversity switch */
523 +#define SSB_BFL2_5G_PWRGAIN 0x0010 /* supports 5G band power gain */
524 +#define SSB_BFL2_PCIEWAR_OVR 0x0020 /* overrides ASPM and Clkreq settings */
525 +#define SSB_BFL2_CAESERS_BRD 0x0040 /* is Caesers board (unused) */
526 +#define SSB_BFL2_BTC3WIRE 0x0080 /* used 3-wire bluetooth coexist */
527 +#define SSB_BFL2_SKWRKFEM_BRD 0x0100 /* 4321mcm93 uses Skyworks FEM */
528 +#define SSB_BFL2_SPUR_WAR 0x0200 /* has a workaround for clock-harmonic spurs */
529 +#define SSB_BFL2_GPLL_WAR 0x0400 /* altenative G-band PLL settings implemented */
530 +
531 /* Values for SSB_SPROM1_BINF_CCODE */
532 enum {
533 SSB_SPROM1CCODE_WORLD = 0,
534 --- a/drivers/ssb/driver_chipcommon.c
535 +++ b/drivers/ssb/driver_chipcommon.c
536 @@ -3,7 +3,7 @@
537 * Broadcom ChipCommon core driver
538 *
539 * Copyright 2005, Broadcom Corporation
540 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
541 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
542 *
543 * Licensed under the GNU/GPL. See COPYING for details.
544 */
545 @@ -46,40 +46,66 @@ void ssb_chipco_set_clockmode(struct ssb
546 if (!ccdev)
547 return;
548 bus = ccdev->bus;
549 +
550 + /* We support SLOW only on 6..9 */
551 + if (ccdev->id.revision >= 10 && mode == SSB_CLKMODE_SLOW)
552 + mode = SSB_CLKMODE_DYNAMIC;
553 +
554 + if (cc->capabilities & SSB_CHIPCO_CAP_PMU)
555 + return; /* PMU controls clockmode, separated function needed */
556 + SSB_WARN_ON(ccdev->id.revision >= 20);
557 +
558 /* chipcommon cores prior to rev6 don't support dynamic clock control */
559 if (ccdev->id.revision < 6)
560 return;
561 - /* chipcommon cores rev10 are a whole new ball game */
562 +
563 + /* ChipCommon cores rev10+ need testing */
564 if (ccdev->id.revision >= 10)
565 return;
566 +
567 if (!(cc->capabilities & SSB_CHIPCO_CAP_PCTL))
568 return;
569
570 switch (mode) {
571 - case SSB_CLKMODE_SLOW:
572 + case SSB_CLKMODE_SLOW: /* For revs 6..9 only */
573 tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
574 tmp |= SSB_CHIPCO_SLOWCLKCTL_FSLOW;
575 chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
576 break;
577 case SSB_CLKMODE_FAST:
578 - ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */
579 - tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
580 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
581 - tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL;
582 - chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
583 + if (ccdev->id.revision < 10) {
584 + ssb_pci_xtal(bus, SSB_GPIO_XTAL, 1); /* Force crystal on */
585 + tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
586 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
587 + tmp |= SSB_CHIPCO_SLOWCLKCTL_IPLL;
588 + chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
589 + } else {
590 + chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
591 + (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) |
592 + SSB_CHIPCO_SYSCLKCTL_FORCEHT));
593 + /* udelay(150); TODO: not available in early init */
594 + }
595 break;
596 case SSB_CLKMODE_DYNAMIC:
597 - tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
598 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
599 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL;
600 - tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
601 - if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) != SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL)
602 - tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
603 - chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
604 -
605 - /* for dynamic control, we have to release our xtal_pu "force on" */
606 - if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL)
607 - ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0);
608 + if (ccdev->id.revision < 10) {
609 + tmp = chipco_read32(cc, SSB_CHIPCO_SLOWCLKCTL);
610 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_FSLOW;
611 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_IPLL;
612 + tmp &= ~SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
613 + if ((tmp & SSB_CHIPCO_SLOWCLKCTL_SRC) !=
614 + SSB_CHIPCO_SLOWCLKCTL_SRC_XTAL)
615 + tmp |= SSB_CHIPCO_SLOWCLKCTL_ENXTAL;
616 + chipco_write32(cc, SSB_CHIPCO_SLOWCLKCTL, tmp);
617 +
618 + /* For dynamic control, we have to release our xtal_pu
619 + * "force on" */
620 + if (tmp & SSB_CHIPCO_SLOWCLKCTL_ENXTAL)
621 + ssb_pci_xtal(bus, SSB_GPIO_XTAL, 0);
622 + } else {
623 + chipco_write32(cc, SSB_CHIPCO_SYSCLKCTL,
624 + (chipco_read32(cc, SSB_CHIPCO_SYSCLKCTL) &
625 + ~SSB_CHIPCO_SYSCLKCTL_FORCEHT));
626 + }
627 break;
628 default:
629 SSB_WARN_ON(1);
630 @@ -260,6 +286,12 @@ void ssb_chipcommon_init(struct ssb_chip
631 if (cc->dev->id.revision >= 11)
632 cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT);
633 ssb_dprintk(KERN_INFO PFX "chipcommon status is 0x%x\n", cc->status);
634 +
635 + if (cc->dev->id.revision >= 20) {
636 + chipco_write32(cc, SSB_CHIPCO_GPIOPULLUP, 0);
637 + chipco_write32(cc, SSB_CHIPCO_GPIOPULLDOWN, 0);
638 + }
639 +
640 ssb_pmu_init(cc);
641 chipco_powercontrol_init(cc);
642 ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST);
643 --- a/drivers/ssb/driver_chipcommon_pmu.c
644 +++ b/drivers/ssb/driver_chipcommon_pmu.c
645 @@ -2,7 +2,7 @@
646 * Sonics Silicon Backplane
647 * Broadcom ChipCommon Power Management Unit driver
648 *
649 - * Copyright 2009, Michael Buesch <mb@bu3sch.de>
650 + * Copyright 2009, Michael Buesch <m@bues.ch>
651 * Copyright 2007, Broadcom Corporation
652 *
653 * Licensed under the GNU/GPL. See COPYING for details.
654 @@ -417,12 +417,14 @@ static void ssb_pmu_resources_init(struc
655 u32 min_msk = 0, max_msk = 0;
656 unsigned int i;
657 const struct pmu_res_updown_tab_entry *updown_tab = NULL;
658 - unsigned int updown_tab_size;
659 + unsigned int updown_tab_size = 0;
660 const struct pmu_res_depend_tab_entry *depend_tab = NULL;
661 - unsigned int depend_tab_size;
662 + unsigned int depend_tab_size = 0;
663
664 switch (bus->chip_id) {
665 case 0x4312:
666 + min_msk = 0xCBB;
667 + break;
668 case 0x4322:
669 /* We keep the default settings:
670 * min_msk = 0xCBB
671 --- a/drivers/ssb/driver_gige.c
672 +++ b/drivers/ssb/driver_gige.c
673 @@ -3,7 +3,7 @@
674 * Broadcom Gigabit Ethernet core driver
675 *
676 * Copyright 2008, Broadcom Corporation
677 - * Copyright 2008, Michael Buesch <mb@bu3sch.de>
678 + * Copyright 2008, Michael Buesch <m@bues.ch>
679 *
680 * Licensed under the GNU/GPL. See COPYING for details.
681 */
682 @@ -106,8 +106,9 @@ void gige_pcicfg_write32(struct ssb_gige
683 gige_write32(dev, SSB_GIGE_PCICFG + offset, value);
684 }
685
686 -static int ssb_gige_pci_read_config(struct pci_bus *bus, unsigned int devfn,
687 - int reg, int size, u32 *val)
688 +static int __devinit ssb_gige_pci_read_config(struct pci_bus *bus,
689 + unsigned int devfn, int reg,
690 + int size, u32 *val)
691 {
692 struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
693 unsigned long flags;
694 @@ -136,8 +137,9 @@ static int ssb_gige_pci_read_config(stru
695 return PCIBIOS_SUCCESSFUL;
696 }
697
698 -static int ssb_gige_pci_write_config(struct pci_bus *bus, unsigned int devfn,
699 - int reg, int size, u32 val)
700 +static int __devinit ssb_gige_pci_write_config(struct pci_bus *bus,
701 + unsigned int devfn, int reg,
702 + int size, u32 val)
703 {
704 struct ssb_gige *dev = container_of(bus->ops, struct ssb_gige, pci_ops);
705 unsigned long flags;
706 @@ -166,7 +168,8 @@ static int ssb_gige_pci_write_config(str
707 return PCIBIOS_SUCCESSFUL;
708 }
709
710 -static int ssb_gige_probe(struct ssb_device *sdev, const struct ssb_device_id *id)
711 +static int __devinit ssb_gige_probe(struct ssb_device *sdev,
712 + const struct ssb_device_id *id)
713 {
714 struct ssb_gige *dev;
715 u32 base, tmslow, tmshigh;
716 --- a/drivers/ssb/driver_pcicore.c
717 +++ b/drivers/ssb/driver_pcicore.c
718 @@ -3,7 +3,7 @@
719 * Broadcom PCI-core driver
720 *
721 * Copyright 2005, Broadcom Corporation
722 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
723 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
724 *
725 * Licensed under the GNU/GPL. See COPYING for details.
726 */
727 @@ -15,6 +15,11 @@
728
729 #include "ssb_private.h"
730
731 +static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address);
732 +static void ssb_pcie_write(struct ssb_pcicore *pc, u32 address, u32 data);
733 +static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address);
734 +static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
735 + u8 address, u16 data);
736
737 static inline
738 u32 pcicore_read32(struct ssb_pcicore *pc, u16 offset)
739 @@ -309,7 +314,7 @@ int ssb_pcicore_pcibios_map_irq(const st
740 return ssb_mips_irq(extpci_core->dev) + 2;
741 }
742
743 -static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
744 +static void __devinit ssb_pcicore_init_hostmode(struct ssb_pcicore *pc)
745 {
746 u32 val;
747
748 @@ -374,7 +379,7 @@ static void ssb_pcicore_init_hostmode(st
749 register_pci_controller(&ssb_pcicore_controller);
750 }
751
752 -static int pcicore_is_in_hostmode(struct ssb_pcicore *pc)
753 +static int __devinit pcicore_is_in_hostmode(struct ssb_pcicore *pc)
754 {
755 struct ssb_bus *bus = pc->dev->bus;
756 u16 chipid_top;
757 @@ -403,25 +408,137 @@ static int pcicore_is_in_hostmode(struct
758 }
759 #endif /* CONFIG_SSB_PCICORE_HOSTMODE */
760
761 +/**************************************************
762 + * Workarounds.
763 + **************************************************/
764 +
765 +static void __devinit ssb_pcicore_fix_sprom_core_index(struct ssb_pcicore *pc)
766 +{
767 + u16 tmp = pcicore_read16(pc, SSB_PCICORE_SPROM(0));
768 + if (((tmp & 0xF000) >> 12) != pc->dev->core_index) {
769 + tmp &= ~0xF000;
770 + tmp |= (pc->dev->core_index << 12);
771 + pcicore_write16(pc, SSB_PCICORE_SPROM(0), tmp);
772 + }
773 +}
774 +
775 +static u8 ssb_pcicore_polarity_workaround(struct ssb_pcicore *pc)
776 +{
777 + return (ssb_pcie_read(pc, 0x204) & 0x10) ? 0xC0 : 0x80;
778 +}
779 +
780 +static void ssb_pcicore_serdes_workaround(struct ssb_pcicore *pc)
781 +{
782 + const u8 serdes_pll_device = 0x1D;
783 + const u8 serdes_rx_device = 0x1F;
784 + u16 tmp;
785 +
786 + ssb_pcie_mdio_write(pc, serdes_rx_device, 1 /* Control */,
787 + ssb_pcicore_polarity_workaround(pc));
788 + tmp = ssb_pcie_mdio_read(pc, serdes_pll_device, 1 /* Control */);
789 + if (tmp & 0x4000)
790 + ssb_pcie_mdio_write(pc, serdes_pll_device, 1, tmp & ~0x4000);
791 +}
792 +
793 +static void ssb_pcicore_pci_setup_workarounds(struct ssb_pcicore *pc)
794 +{
795 + struct ssb_device *pdev = pc->dev;
796 + struct ssb_bus *bus = pdev->bus;
797 + u32 tmp;
798 +
799 + tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
800 + tmp |= SSB_PCICORE_SBTOPCI_PREF;
801 + tmp |= SSB_PCICORE_SBTOPCI_BURST;
802 + pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
803 +
804 + if (pdev->id.revision < 5) {
805 + tmp = ssb_read32(pdev, SSB_IMCFGLO);
806 + tmp &= ~SSB_IMCFGLO_SERTO;
807 + tmp |= 2;
808 + tmp &= ~SSB_IMCFGLO_REQTO;
809 + tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT;
810 + ssb_write32(pdev, SSB_IMCFGLO, tmp);
811 + ssb_commit_settings(bus);
812 + } else if (pdev->id.revision >= 11) {
813 + tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
814 + tmp |= SSB_PCICORE_SBTOPCI_MRM;
815 + pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
816 + }
817 +}
818 +
819 +static void ssb_pcicore_pcie_setup_workarounds(struct ssb_pcicore *pc)
820 +{
821 + u32 tmp;
822 + u8 rev = pc->dev->id.revision;
823 +
824 + if (rev == 0 || rev == 1) {
825 + /* TLP Workaround register. */
826 + tmp = ssb_pcie_read(pc, 0x4);
827 + tmp |= 0x8;
828 + ssb_pcie_write(pc, 0x4, tmp);
829 + }
830 + if (rev == 1) {
831 + /* DLLP Link Control register. */
832 + tmp = ssb_pcie_read(pc, 0x100);
833 + tmp |= 0x40;
834 + ssb_pcie_write(pc, 0x100, tmp);
835 + }
836 +
837 + if (rev == 0) {
838 + const u8 serdes_rx_device = 0x1F;
839 +
840 + ssb_pcie_mdio_write(pc, serdes_rx_device,
841 + 2 /* Timer */, 0x8128);
842 + ssb_pcie_mdio_write(pc, serdes_rx_device,
843 + 6 /* CDR */, 0x0100);
844 + ssb_pcie_mdio_write(pc, serdes_rx_device,
845 + 7 /* CDR BW */, 0x1466);
846 + } else if (rev == 3 || rev == 4 || rev == 5) {
847 + /* TODO: DLLP Power Management Threshold */
848 + ssb_pcicore_serdes_workaround(pc);
849 + /* TODO: ASPM */
850 + } else if (rev == 7) {
851 + /* TODO: No PLL down */
852 + }
853 +
854 + if (rev >= 6) {
855 + /* Miscellaneous Configuration Fixup */
856 + tmp = pcicore_read16(pc, SSB_PCICORE_SPROM(5));
857 + if (!(tmp & 0x8000))
858 + pcicore_write16(pc, SSB_PCICORE_SPROM(5),
859 + tmp | 0x8000);
860 + }
861 +}
862
863 /**************************************************
864 * Generic and Clientmode operation code.
865 **************************************************/
866
867 -static void ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)
868 +static void __devinit ssb_pcicore_init_clientmode(struct ssb_pcicore *pc)
869 {
870 + struct ssb_device *pdev = pc->dev;
871 + struct ssb_bus *bus = pdev->bus;
872 +
873 + if (bus->bustype == SSB_BUSTYPE_PCI)
874 + ssb_pcicore_fix_sprom_core_index(pc);
875 +
876 /* Disable PCI interrupts. */
877 - ssb_write32(pc->dev, SSB_INTVEC, 0);
878 + ssb_write32(pdev, SSB_INTVEC, 0);
879 +
880 + /* Additional PCIe always once-executed workarounds */
881 + if (pc->dev->id.coreid == SSB_DEV_PCIE) {
882 + ssb_pcicore_serdes_workaround(pc);
883 + /* TODO: ASPM */
884 + /* TODO: Clock Request Update */
885 + }
886 }
887
888 -void ssb_pcicore_init(struct ssb_pcicore *pc)
889 +void __devinit ssb_pcicore_init(struct ssb_pcicore *pc)
890 {
891 struct ssb_device *dev = pc->dev;
892 - struct ssb_bus *bus;
893
894 if (!dev)
895 return;
896 - bus = dev->bus;
897 if (!ssb_device_is_enabled(dev))
898 ssb_device_enable(dev, 0);
899
900 @@ -446,11 +563,35 @@ static void ssb_pcie_write(struct ssb_pc
901 pcicore_write32(pc, 0x134, data);
902 }
903
904 -static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
905 - u8 address, u16 data)
906 +static void ssb_pcie_mdio_set_phy(struct ssb_pcicore *pc, u8 phy)
907 +{
908 + const u16 mdio_control = 0x128;
909 + const u16 mdio_data = 0x12C;
910 + u32 v;
911 + int i;
912 +
913 + v = (1 << 30); /* Start of Transaction */
914 + v |= (1 << 28); /* Write Transaction */
915 + v |= (1 << 17); /* Turnaround */
916 + v |= (0x1F << 18);
917 + v |= (phy << 4);
918 + pcicore_write32(pc, mdio_data, v);
919 +
920 + udelay(10);
921 + for (i = 0; i < 200; i++) {
922 + v = pcicore_read32(pc, mdio_control);
923 + if (v & 0x100 /* Trans complete */)
924 + break;
925 + msleep(1);
926 + }
927 +}
928 +
929 +static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address)
930 {
931 const u16 mdio_control = 0x128;
932 const u16 mdio_data = 0x12C;
933 + int max_retries = 10;
934 + u16 ret = 0;
935 u32 v;
936 int i;
937
938 @@ -458,46 +599,68 @@ static void ssb_pcie_mdio_write(struct s
939 v |= 0x2; /* MDIO Clock Divisor */
940 pcicore_write32(pc, mdio_control, v);
941
942 + if (pc->dev->id.revision >= 10) {
943 + max_retries = 200;
944 + ssb_pcie_mdio_set_phy(pc, device);
945 + }
946 +
947 v = (1 << 30); /* Start of Transaction */
948 - v |= (1 << 28); /* Write Transaction */
949 + v |= (1 << 29); /* Read Transaction */
950 v |= (1 << 17); /* Turnaround */
951 - v |= (u32)device << 22;
952 + if (pc->dev->id.revision < 10)
953 + v |= (u32)device << 22;
954 v |= (u32)address << 18;
955 - v |= data;
956 pcicore_write32(pc, mdio_data, v);
957 /* Wait for the device to complete the transaction */
958 udelay(10);
959 - for (i = 0; i < 10; i++) {
960 + for (i = 0; i < max_retries; i++) {
961 v = pcicore_read32(pc, mdio_control);
962 - if (v & 0x100 /* Trans complete */)
963 + if (v & 0x100 /* Trans complete */) {
964 + udelay(10);
965 + ret = pcicore_read32(pc, mdio_data);
966 break;
967 + }
968 msleep(1);
969 }
970 pcicore_write32(pc, mdio_control, 0);
971 + return ret;
972 }
973
974 -static void ssb_broadcast_value(struct ssb_device *dev,
975 - u32 address, u32 data)
976 +static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device,
977 + u8 address, u16 data)
978 {
979 - /* This is used for both, PCI and ChipCommon core, so be careful. */
980 - BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
981 - BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
982 + const u16 mdio_control = 0x128;
983 + const u16 mdio_data = 0x12C;
984 + int max_retries = 10;
985 + u32 v;
986 + int i;
987
988 - ssb_write32(dev, SSB_PCICORE_BCAST_ADDR, address);
989 - ssb_read32(dev, SSB_PCICORE_BCAST_ADDR); /* flush */
990 - ssb_write32(dev, SSB_PCICORE_BCAST_DATA, data);
991 - ssb_read32(dev, SSB_PCICORE_BCAST_DATA); /* flush */
992 -}
993 + v = 0x80; /* Enable Preamble Sequence */
994 + v |= 0x2; /* MDIO Clock Divisor */
995 + pcicore_write32(pc, mdio_control, v);
996
997 -static void ssb_commit_settings(struct ssb_bus *bus)
998 -{
999 - struct ssb_device *dev;
1000 + if (pc->dev->id.revision >= 10) {
1001 + max_retries = 200;
1002 + ssb_pcie_mdio_set_phy(pc, device);
1003 + }
1004
1005 - dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
1006 - if (WARN_ON(!dev))
1007 - return;
1008 - /* This forces an update of the cached registers. */
1009 - ssb_broadcast_value(dev, 0xFD8, 0);
1010 + v = (1 << 30); /* Start of Transaction */
1011 + v |= (1 << 28); /* Write Transaction */
1012 + v |= (1 << 17); /* Turnaround */
1013 + if (pc->dev->id.revision < 10)
1014 + v |= (u32)device << 22;
1015 + v |= (u32)address << 18;
1016 + v |= data;
1017 + pcicore_write32(pc, mdio_data, v);
1018 + /* Wait for the device to complete the transaction */
1019 + udelay(10);
1020 + for (i = 0; i < max_retries; i++) {
1021 + v = pcicore_read32(pc, mdio_control);
1022 + if (v & 0x100 /* Trans complete */)
1023 + break;
1024 + msleep(1);
1025 + }
1026 + pcicore_write32(pc, mdio_control, 0);
1027 }
1028
1029 int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc,
1030 @@ -550,48 +713,10 @@ int ssb_pcicore_dev_irqvecs_enable(struc
1031 if (pc->setup_done)
1032 goto out;
1033 if (pdev->id.coreid == SSB_DEV_PCI) {
1034 - tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
1035 - tmp |= SSB_PCICORE_SBTOPCI_PREF;
1036 - tmp |= SSB_PCICORE_SBTOPCI_BURST;
1037 - pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
1038 -
1039 - if (pdev->id.revision < 5) {
1040 - tmp = ssb_read32(pdev, SSB_IMCFGLO);
1041 - tmp &= ~SSB_IMCFGLO_SERTO;
1042 - tmp |= 2;
1043 - tmp &= ~SSB_IMCFGLO_REQTO;
1044 - tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT;
1045 - ssb_write32(pdev, SSB_IMCFGLO, tmp);
1046 - ssb_commit_settings(bus);
1047 - } else if (pdev->id.revision >= 11) {
1048 - tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2);
1049 - tmp |= SSB_PCICORE_SBTOPCI_MRM;
1050 - pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp);
1051 - }
1052 + ssb_pcicore_pci_setup_workarounds(pc);
1053 } else {
1054 WARN_ON(pdev->id.coreid != SSB_DEV_PCIE);
1055 - //TODO: Better make defines for all these magic PCIE values.
1056 - if ((pdev->id.revision == 0) || (pdev->id.revision == 1)) {
1057 - /* TLP Workaround register. */
1058 - tmp = ssb_pcie_read(pc, 0x4);
1059 - tmp |= 0x8;
1060 - ssb_pcie_write(pc, 0x4, tmp);
1061 - }
1062 - if (pdev->id.revision == 0) {
1063 - const u8 serdes_rx_device = 0x1F;
1064 -
1065 - ssb_pcie_mdio_write(pc, serdes_rx_device,
1066 - 2 /* Timer */, 0x8128);
1067 - ssb_pcie_mdio_write(pc, serdes_rx_device,
1068 - 6 /* CDR */, 0x0100);
1069 - ssb_pcie_mdio_write(pc, serdes_rx_device,
1070 - 7 /* CDR BW */, 0x1466);
1071 - } else if (pdev->id.revision == 1) {
1072 - /* DLLP Link Control register. */
1073 - tmp = ssb_pcie_read(pc, 0x100);
1074 - tmp |= 0x40;
1075 - ssb_pcie_write(pc, 0x100, tmp);
1076 - }
1077 + ssb_pcicore_pcie_setup_workarounds(pc);
1078 }
1079 pc->setup_done = 1;
1080 out:
1081 --- a/drivers/ssb/pcihost_wrapper.c
1082 +++ b/drivers/ssb/pcihost_wrapper.c
1083 @@ -6,7 +6,7 @@
1084 * Copyright (c) 2005 Stefano Brivio <st3@riseup.net>
1085 * Copyright (c) 2005 Danny van Dyk <kugelfang@gentoo.org>
1086 * Copyright (c) 2005 Andreas Jaggi <andreas.jaggi@waterwave.ch>
1087 - * Copyright (c) 2005-2007 Michael Buesch <mbuesch@freenet.de>
1088 + * Copyright (c) 2005-2007 Michael Buesch <m@bues.ch>
1089 *
1090 * Licensed under the GNU/GPL. See COPYING for details.
1091 */
1092 @@ -53,8 +53,8 @@ static int ssb_pcihost_resume(struct pci
1093 # define ssb_pcihost_resume NULL
1094 #endif /* CONFIG_PM */
1095
1096 -static int ssb_pcihost_probe(struct pci_dev *dev,
1097 - const struct pci_device_id *id)
1098 +static int __devinit ssb_pcihost_probe(struct pci_dev *dev,
1099 + const struct pci_device_id *id)
1100 {
1101 struct ssb_bus *ssb;
1102 int err = -ENOMEM;
1103 @@ -110,7 +110,7 @@ static void ssb_pcihost_remove(struct pc
1104 pci_set_drvdata(dev, NULL);
1105 }
1106
1107 -int ssb_pcihost_register(struct pci_driver *driver)
1108 +int __devinit ssb_pcihost_register(struct pci_driver *driver)
1109 {
1110 driver->probe = ssb_pcihost_probe;
1111 driver->remove = ssb_pcihost_remove;
1112 --- a/drivers/ssb/scan.c
1113 +++ b/drivers/ssb/scan.c
1114 @@ -2,7 +2,7 @@
1115 * Sonics Silicon Backplane
1116 * Bus scanning
1117 *
1118 - * Copyright (C) 2005-2007 Michael Buesch <mb@bu3sch.de>
1119 + * Copyright (C) 2005-2007 Michael Buesch <m@bues.ch>
1120 * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
1121 * Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
1122 * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
1123 @@ -258,7 +258,10 @@ static int we_support_multiple_80211_cor
1124 #ifdef CONFIG_SSB_PCIHOST
1125 if (bus->bustype == SSB_BUSTYPE_PCI) {
1126 if (bus->host_pci->vendor == PCI_VENDOR_ID_BROADCOM &&
1127 - bus->host_pci->device == 0x4324)
1128 + ((bus->host_pci->device == 0x4313) ||
1129 + (bus->host_pci->device == 0x431A) ||
1130 + (bus->host_pci->device == 0x4321) ||
1131 + (bus->host_pci->device == 0x4324)))
1132 return 1;
1133 }
1134 #endif /* CONFIG_SSB_PCIHOST */
1135 @@ -307,8 +310,7 @@ int ssb_bus_scan(struct ssb_bus *bus,
1136 } else {
1137 if (bus->bustype == SSB_BUSTYPE_PCI) {
1138 bus->chip_id = pcidev_to_chipid(bus->host_pci);
1139 - pci_read_config_word(bus->host_pci, PCI_REVISION_ID,
1140 - &bus->chip_rev);
1141 + bus->chip_rev = bus->host_pci->revision;
1142 bus->chip_package = 0;
1143 } else {
1144 bus->chip_id = 0x4710;
1145 --- a/drivers/ssb/sprom.c
1146 +++ b/drivers/ssb/sprom.c
1147 @@ -2,7 +2,7 @@
1148 * Sonics Silicon Backplane
1149 * Common SPROM support routines
1150 *
1151 - * Copyright (C) 2005-2008 Michael Buesch <mb@bu3sch.de>
1152 + * Copyright (C) 2005-2008 Michael Buesch <m@bues.ch>
1153 * Copyright (C) 2005 Martin Langer <martin-langer@gmx.de>
1154 * Copyright (C) 2005 Stefano Brivio <st3@riseup.net>
1155 * Copyright (C) 2005 Danny van Dyk <kugelfang@gentoo.org>
1156 @@ -17,7 +17,7 @@
1157 #include <linux/slab.h>
1158
1159
1160 -static const struct ssb_sprom *fallback_sprom;
1161 +static int(*get_fallback_sprom)(struct ssb_bus *dev, struct ssb_sprom *out);
1162
1163
1164 static int sprom2hex(const u16 *sprom, char *buf, size_t buf_len,
1165 @@ -145,36 +145,43 @@ out:
1166 }
1167
1168 /**
1169 - * ssb_arch_set_fallback_sprom - Set a fallback SPROM for use if no SPROM is found.
1170 + * ssb_arch_register_fallback_sprom - Registers a method providing a
1171 + * fallback SPROM if no SPROM is found.
1172 *
1173 - * @sprom: The SPROM data structure to register.
1174 + * @sprom_callback: The callback function.
1175 *
1176 - * With this function the architecture implementation may register a fallback
1177 - * SPROM data structure. The fallback is only used for PCI based SSB devices,
1178 - * where no valid SPROM can be found in the shadow registers.
1179 + * With this function the architecture implementation may register a
1180 + * callback handler which fills the SPROM data structure. The fallback is
1181 + * only used for PCI based SSB devices, where no valid SPROM can be found
1182 + * in the shadow registers.
1183 + *
1184 + * This function is useful for weird architectures that have a half-assed
1185 + * SSB device hardwired to their PCI bus.
1186 + *
1187 + * Note that it does only work with PCI attached SSB devices. PCMCIA
1188 + * devices currently don't use this fallback.
1189 + * Architectures must provide the SPROM for native SSB devices anyway, so
1190 + * the fallback also isn't used for native devices.
1191 *
1192 - * This function is useful for weird architectures that have a half-assed SSB device
1193 - * hardwired to their PCI bus.
1194 - *
1195 - * Note that it does only work with PCI attached SSB devices. PCMCIA devices currently
1196 - * don't use this fallback.
1197 - * Architectures must provide the SPROM for native SSB devices anyway,
1198 - * so the fallback also isn't used for native devices.
1199 - *
1200 - * This function is available for architecture code, only. So it is not exported.
1201 + * This function is available for architecture code, only. So it is not
1202 + * exported.
1203 */
1204 -int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom)
1205 +int ssb_arch_register_fallback_sprom(int (*sprom_callback)(struct ssb_bus *bus,
1206 + struct ssb_sprom *out))
1207 {
1208 - if (fallback_sprom)
1209 + if (get_fallback_sprom)
1210 return -EEXIST;
1211 - fallback_sprom = sprom;
1212 + get_fallback_sprom = sprom_callback;
1213
1214 return 0;
1215 }
1216
1217 -const struct ssb_sprom *ssb_get_fallback_sprom(void)
1218 +int ssb_fill_sprom_with_fallback(struct ssb_bus *bus, struct ssb_sprom *out)
1219 {
1220 - return fallback_sprom;
1221 + if (!get_fallback_sprom)
1222 + return -ENOENT;
1223 +
1224 + return get_fallback_sprom(bus, out);
1225 }
1226
1227 /* http://bcm-v4.sipsolutions.net/802.11/IsSpromAvailable */
1228 @@ -185,7 +192,7 @@ bool ssb_is_sprom_available(struct ssb_b
1229 /* this routine differs from specs as we do not access SPROM directly
1230 on PCMCIA */
1231 if (bus->bustype == SSB_BUSTYPE_PCI &&
1232 - bus->chipco.dev && /* can be unavailible! */
1233 + bus->chipco.dev && /* can be unavailable! */
1234 bus->chipco.dev->id.revision >= 31)
1235 return bus->chipco.capabilities & SSB_CHIPCO_CAP_SPROM;
1236
1237 --- a/drivers/ssb/ssb_private.h
1238 +++ b/drivers/ssb/ssb_private.h
1239 @@ -171,7 +171,8 @@ ssize_t ssb_attr_sprom_store(struct ssb_
1240 const char *buf, size_t count,
1241 int (*sprom_check_crc)(const u16 *sprom, size_t size),
1242 int (*sprom_write)(struct ssb_bus *bus, const u16 *sprom));
1243 -extern const struct ssb_sprom *ssb_get_fallback_sprom(void);
1244 +extern int ssb_fill_sprom_with_fallback(struct ssb_bus *bus,
1245 + struct ssb_sprom *out);
1246
1247
1248 /* core.c */
1249 --- a/include/linux/ssb/ssb.h
1250 +++ b/include/linux/ssb/ssb.h
1251 @@ -25,8 +25,10 @@ struct ssb_sprom {
1252 u8 et1phyaddr; /* MII address for enet1 */
1253 u8 et0mdcport; /* MDIO for enet0 */
1254 u8 et1mdcport; /* MDIO for enet1 */
1255 - u8 board_rev; /* Board revision number from SPROM. */
1256 + u16 board_rev; /* Board revision number from SPROM. */
1257 u8 country_code; /* Country Code */
1258 + u16 leddc_on_time; /* LED Powersave Duty Cycle On Count */
1259 + u16 leddc_off_time; /* LED Powersave Duty Cycle Off Count */
1260 u8 ant_available_a; /* 2GHz antenna available bits (up to 4) */
1261 u8 ant_available_bg; /* 5GHz antenna available bits (up to 4) */
1262 u16 pa0b0;
1263 @@ -92,6 +94,15 @@ struct ssb_sprom {
1264 } ghz5; /* 5GHz band */
1265 } antenna_gain;
1266
1267 + struct {
1268 + struct {
1269 + u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
1270 + } ghz2;
1271 + struct {
1272 + u8 tssipos, extpa_gain, pdet_range, tr_iso, antswlut;
1273 + } ghz5;
1274 + } fem;
1275 +
1276 /* TODO - add any parameters needed from rev 2, 3, 4, 5 or 8 SPROMs */
1277 };
1278
1279 @@ -99,7 +110,7 @@ struct ssb_sprom {
1280 struct ssb_boardinfo {
1281 u16 vendor;
1282 u16 type;
1283 - u16 rev;
1284 + u8 rev;
1285 };
1286
1287
1288 @@ -229,10 +240,9 @@ struct ssb_driver {
1289 #define drv_to_ssb_drv(_drv) container_of(_drv, struct ssb_driver, drv)
1290
1291 extern int __ssb_driver_register(struct ssb_driver *drv, struct module *owner);
1292 -static inline int ssb_driver_register(struct ssb_driver *drv)
1293 -{
1294 - return __ssb_driver_register(drv, THIS_MODULE);
1295 -}
1296 +#define ssb_driver_register(drv) \
1297 + __ssb_driver_register(drv, THIS_MODULE)
1298 +
1299 extern void ssb_driver_unregister(struct ssb_driver *drv);
1300
1301
1302 @@ -308,7 +318,7 @@ struct ssb_bus {
1303
1304 /* ID information about the Chip. */
1305 u16 chip_id;
1306 - u16 chip_rev;
1307 + u8 chip_rev;
1308 u16 sprom_offset;
1309 u16 sprom_size; /* number of words in sprom */
1310 u8 chip_package;
1311 @@ -404,7 +414,9 @@ extern bool ssb_is_sprom_available(struc
1312
1313 /* Set a fallback SPROM.
1314 * See kdoc at the function definition for complete documentation. */
1315 -extern int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom);
1316 +extern int ssb_arch_register_fallback_sprom(
1317 + int (*sprom_callback)(struct ssb_bus *bus,
1318 + struct ssb_sprom *out));
1319
1320 /* Suspend a SSB bus.
1321 * Call this from the parent bus suspend routine. */
1322 @@ -518,6 +530,7 @@ extern int ssb_bus_may_powerdown(struct
1323 * Otherwise static always-on powercontrol will be used. */
1324 extern int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl);
1325
1326 +extern void ssb_commit_settings(struct ssb_bus *bus);
1327
1328 /* Various helper functions */
1329 extern u32 ssb_admatch_base(u32 adm);
1330 --- a/include/linux/ssb/ssb_driver_chipcommon.h
1331 +++ b/include/linux/ssb/ssb_driver_chipcommon.h
1332 @@ -8,7 +8,7 @@
1333 * gpio interface, extbus, and support for serial and parallel flashes.
1334 *
1335 * Copyright 2005, Broadcom Corporation
1336 - * Copyright 2006, Michael Buesch <mb@bu3sch.de>
1337 + * Copyright 2006, Michael Buesch <m@bues.ch>
1338 *
1339 * Licensed under the GPL version 2. See COPYING for details.
1340 */
1341 @@ -123,6 +123,8 @@
1342 #define SSB_CHIPCO_FLASHDATA 0x0048
1343 #define SSB_CHIPCO_BCAST_ADDR 0x0050
1344 #define SSB_CHIPCO_BCAST_DATA 0x0054
1345 +#define SSB_CHIPCO_GPIOPULLUP 0x0058 /* Rev >= 20 only */
1346 +#define SSB_CHIPCO_GPIOPULLDOWN 0x005C /* Rev >= 20 only */
1347 #define SSB_CHIPCO_GPIOIN 0x0060
1348 #define SSB_CHIPCO_GPIOOUT 0x0064
1349 #define SSB_CHIPCO_GPIOOUTEN 0x0068
1350 @@ -131,6 +133,9 @@
1351 #define SSB_CHIPCO_GPIOIRQ 0x0074
1352 #define SSB_CHIPCO_WATCHDOG 0x0080
1353 #define SSB_CHIPCO_GPIOTIMER 0x0088 /* LED powersave (corerev >= 16) */
1354 +#define SSB_CHIPCO_GPIOTIMER_OFFTIME 0x0000FFFF
1355 +#define SSB_CHIPCO_GPIOTIMER_OFFTIME_SHIFT 0
1356 +#define SSB_CHIPCO_GPIOTIMER_ONTIME 0xFFFF0000
1357 #define SSB_CHIPCO_GPIOTIMER_ONTIME_SHIFT 16
1358 #define SSB_CHIPCO_GPIOTOUTM 0x008C /* LED powersave (corerev >= 16) */
1359 #define SSB_CHIPCO_CLOCK_N 0x0090
1360 @@ -189,8 +194,10 @@
1361 #define SSB_CHIPCO_CLKCTLST_HAVEALPREQ 0x00000008 /* ALP available request */
1362 #define SSB_CHIPCO_CLKCTLST_HAVEHTREQ 0x00000010 /* HT available request */
1363 #define SSB_CHIPCO_CLKCTLST_HWCROFF 0x00000020 /* Force HW clock request off */
1364 -#define SSB_CHIPCO_CLKCTLST_HAVEHT 0x00010000 /* HT available */
1365 -#define SSB_CHIPCO_CLKCTLST_HAVEALP 0x00020000 /* APL available */
1366 +#define SSB_CHIPCO_CLKCTLST_HAVEALP 0x00010000 /* ALP available */
1367 +#define SSB_CHIPCO_CLKCTLST_HAVEHT 0x00020000 /* HT available */
1368 +#define SSB_CHIPCO_CLKCTLST_4328A0_HAVEHT 0x00010000 /* 4328a0 has reversed bits */
1369 +#define SSB_CHIPCO_CLKCTLST_4328A0_HAVEALP 0x00020000 /* 4328a0 has reversed bits */
1370 #define SSB_CHIPCO_HW_WORKAROUND 0x01E4 /* Hardware workaround (rev >= 20) */
1371 #define SSB_CHIPCO_UART0_DATA 0x0300
1372 #define SSB_CHIPCO_UART0_IMR 0x0304
1373 --- a/drivers/ssb/b43_pci_bridge.c
1374 +++ b/drivers/ssb/b43_pci_bridge.c
1375 @@ -5,12 +5,13 @@
1376 * because of its small size we include it in the SSB core
1377 * instead of creating a standalone module.
1378 *
1379 - * Copyright 2007 Michael Buesch <mb@bu3sch.de>
1380 + * Copyright 2007 Michael Buesch <m@bues.ch>
1381 *
1382 * Licensed under the GNU/GPL. See COPYING for details.
1383 */
1384
1385 #include <linux/pci.h>
1386 +#include <linux/module.h>
1387 #include <linux/ssb/ssb.h>
1388
1389 #include "ssb_private.h"
1390 --- a/drivers/ssb/driver_extif.c
1391 +++ b/drivers/ssb/driver_extif.c
1392 @@ -3,7 +3,7 @@
1393 * Broadcom EXTIF core driver
1394 *
1395 * Copyright 2005, Broadcom Corporation
1396 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
1397 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
1398 * Copyright 2006, 2007, Felix Fietkau <nbd@openwrt.org>
1399 * Copyright 2007, Aurelien Jarno <aurelien@aurel32.net>
1400 *
1401 --- a/drivers/ssb/driver_mipscore.c
1402 +++ b/drivers/ssb/driver_mipscore.c
1403 @@ -3,7 +3,7 @@
1404 * Broadcom MIPS core driver
1405 *
1406 * Copyright 2005, Broadcom Corporation
1407 - * Copyright 2006, 2007, Michael Buesch <mb@bu3sch.de>
1408 + * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
1409 *
1410 * Licensed under the GNU/GPL. See COPYING for details.
1411 */
1412 --- a/drivers/ssb/embedded.c
1413 +++ b/drivers/ssb/embedded.c
1414 @@ -3,7 +3,7 @@
1415 * Embedded systems support code
1416 *
1417 * Copyright 2005-2008, Broadcom Corporation
1418 - * Copyright 2006-2008, Michael Buesch <mb@bu3sch.de>
1419 + * Copyright 2006-2008, Michael Buesch <m@bues.ch>
1420 *
1421 * Licensed under the GNU/GPL. See COPYING for details.
1422 */
1423 --- a/drivers/ssb/pcmcia.c
1424 +++ b/drivers/ssb/pcmcia.c
1425 @@ -3,7 +3,7 @@
1426 * PCMCIA-Hostbus related functions
1427 *
1428 * Copyright 2006 Johannes Berg <johannes@sipsolutions.net>
1429 - * Copyright 2007-2008 Michael Buesch <mb@bu3sch.de>
1430 + * Copyright 2007-2008 Michael Buesch <m@bues.ch>
1431 *
1432 * Licensed under the GNU/GPL. See COPYING for details.
1433 */
1434 --- a/drivers/ssb/sdio.c
1435 +++ b/drivers/ssb/sdio.c
1436 @@ -6,7 +6,7 @@
1437 *
1438 * Based on drivers/ssb/pcmcia.c
1439 * Copyright 2006 Johannes Berg <johannes@sipsolutions.net>
1440 - * Copyright 2007-2008 Michael Buesch <mb@bu3sch.de>
1441 + * Copyright 2007-2008 Michael Buesch <m@bues.ch>
1442 *
1443 * Licensed under the GNU/GPL. See COPYING for details.
1444 *
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