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kernel: update bcma and ssb to version master-2014-07-22
[openwrt/openwrt.git] / target / linux / generic / patches-3.10 / 025-bcma_backport.patch
1 --- a/drivers/bcma/Kconfig
2 +++ b/drivers/bcma/Kconfig
3 @@ -26,6 +26,7 @@ config BCMA_HOST_PCI_POSSIBLE
4 config BCMA_HOST_PCI
5 bool "Support for BCMA on PCI-host bus"
6 depends on BCMA_HOST_PCI_POSSIBLE
7 + default y
8
9 config BCMA_DRIVER_PCI_HOSTMODE
10 bool "Driver for PCI core working in hostmode"
11 @@ -34,8 +35,14 @@ config BCMA_DRIVER_PCI_HOSTMODE
12 PCI core hostmode operation (external PCI bus).
13
14 config BCMA_HOST_SOC
15 - bool
16 - depends on BCMA_DRIVER_MIPS
17 + bool "Support for BCMA in a SoC"
18 + depends on BCMA
19 + help
20 + Host interface for a Broadcom AIX bus directly mapped into
21 + the memory. This only works with the Broadcom SoCs from the
22 + BCM47XX line.
23 +
24 + If unsure, say N
25
26 config BCMA_DRIVER_MIPS
27 bool "BCMA Broadcom MIPS core driver"
28 @@ -68,6 +75,7 @@ config BCMA_DRIVER_GMAC_CMN
29 config BCMA_DRIVER_GPIO
30 bool "BCMA GPIO driver"
31 depends on BCMA && GPIOLIB
32 + select IRQ_DOMAIN if BCMA_HOST_SOC
33 help
34 Driver to provide access to the GPIO pins of the bcma bus.
35
36 --- a/drivers/bcma/Makefile
37 +++ b/drivers/bcma/Makefile
38 @@ -3,6 +3,7 @@ bcma-y += driver_chipcommon.o driver
39 bcma-$(CONFIG_BCMA_SFLASH) += driver_chipcommon_sflash.o
40 bcma-$(CONFIG_BCMA_NFLASH) += driver_chipcommon_nflash.o
41 bcma-y += driver_pci.o
42 +bcma-y += driver_pcie2.o
43 bcma-$(CONFIG_BCMA_DRIVER_PCI_HOSTMODE) += driver_pci_host.o
44 bcma-$(CONFIG_BCMA_DRIVER_MIPS) += driver_mips.o
45 bcma-$(CONFIG_BCMA_DRIVER_GMAC_CMN) += driver_gmac_cmn.o
46 --- a/drivers/bcma/bcma_private.h
47 +++ b/drivers/bcma/bcma_private.h
48 @@ -22,6 +22,8 @@
49 struct bcma_bus;
50
51 /* main.c */
52 +bool bcma_wait_value(struct bcma_device *core, u16 reg, u32 mask, u32 value,
53 + int timeout);
54 int bcma_bus_register(struct bcma_bus *bus);
55 void bcma_bus_unregister(struct bcma_bus *bus);
56 int __init bcma_bus_early_register(struct bcma_bus *bus,
57 @@ -31,8 +33,6 @@ int __init bcma_bus_early_register(struc
58 int bcma_bus_suspend(struct bcma_bus *bus);
59 int bcma_bus_resume(struct bcma_bus *bus);
60 #endif
61 -struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
62 - u8 unit);
63
64 /* scan.c */
65 int bcma_bus_scan(struct bcma_bus *bus);
66 --- a/drivers/bcma/core.c
67 +++ b/drivers/bcma/core.c
68 @@ -9,6 +9,25 @@
69 #include <linux/export.h>
70 #include <linux/bcma/bcma.h>
71
72 +static bool bcma_core_wait_value(struct bcma_device *core, u16 reg, u32 mask,
73 + u32 value, int timeout)
74 +{
75 + unsigned long deadline = jiffies + timeout;
76 + u32 val;
77 +
78 + do {
79 + val = bcma_aread32(core, reg);
80 + if ((val & mask) == value)
81 + return true;
82 + cpu_relax();
83 + udelay(10);
84 + } while (!time_after_eq(jiffies, deadline));
85 +
86 + bcma_warn(core->bus, "Timeout waiting for register 0x%04X!\n", reg);
87 +
88 + return false;
89 +}
90 +
91 bool bcma_core_is_enabled(struct bcma_device *core)
92 {
93 if ((bcma_aread32(core, BCMA_IOCTL) & (BCMA_IOCTL_CLK | BCMA_IOCTL_FGC))
94 @@ -25,13 +44,15 @@ void bcma_core_disable(struct bcma_devic
95 if (bcma_aread32(core, BCMA_RESET_CTL) & BCMA_RESET_CTL_RESET)
96 return;
97
98 - bcma_awrite32(core, BCMA_IOCTL, flags);
99 - bcma_aread32(core, BCMA_IOCTL);
100 - udelay(10);
101 + bcma_core_wait_value(core, BCMA_RESET_ST, ~0, 0, 300);
102
103 bcma_awrite32(core, BCMA_RESET_CTL, BCMA_RESET_CTL_RESET);
104 bcma_aread32(core, BCMA_RESET_CTL);
105 udelay(1);
106 +
107 + bcma_awrite32(core, BCMA_IOCTL, flags);
108 + bcma_aread32(core, BCMA_IOCTL);
109 + udelay(10);
110 }
111 EXPORT_SYMBOL_GPL(bcma_core_disable);
112
113 @@ -43,6 +64,7 @@ int bcma_core_enable(struct bcma_device
114 bcma_aread32(core, BCMA_IOCTL);
115
116 bcma_awrite32(core, BCMA_RESET_CTL, 0);
117 + bcma_aread32(core, BCMA_RESET_CTL);
118 udelay(1);
119
120 bcma_awrite32(core, BCMA_IOCTL, (BCMA_IOCTL_CLK | flags));
121 --- a/drivers/bcma/driver_chipcommon.c
122 +++ b/drivers/bcma/driver_chipcommon.c
123 @@ -140,8 +140,15 @@ void bcma_core_chipcommon_init(struct bc
124 bcma_core_chipcommon_early_init(cc);
125
126 if (cc->core->id.rev >= 20) {
127 - bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, 0);
128 - bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, 0);
129 + u32 pullup = 0, pulldown = 0;
130 +
131 + if (cc->core->bus->chipinfo.id == BCMA_CHIP_ID_BCM43142) {
132 + pullup = 0x402e0;
133 + pulldown = 0x20500;
134 + }
135 +
136 + bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, pullup);
137 + bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, pulldown);
138 }
139
140 if (cc->capabilities & BCMA_CC_CAP_PMU)
141 --- a/drivers/bcma/driver_chipcommon_pmu.c
142 +++ b/drivers/bcma/driver_chipcommon_pmu.c
143 @@ -56,6 +56,109 @@ void bcma_chipco_regctl_maskset(struct b
144 }
145 EXPORT_SYMBOL_GPL(bcma_chipco_regctl_maskset);
146
147 +static u32 bcma_pmu_xtalfreq(struct bcma_drv_cc *cc)
148 +{
149 + u32 ilp_ctl, alp_hz;
150 +
151 + if (!(bcma_cc_read32(cc, BCMA_CC_PMU_STAT) &
152 + BCMA_CC_PMU_STAT_EXT_LPO_AVAIL))
153 + return 0;
154 +
155 + bcma_cc_write32(cc, BCMA_CC_PMU_XTAL_FREQ,
156 + BIT(BCMA_CC_PMU_XTAL_FREQ_MEASURE_SHIFT));
157 + usleep_range(1000, 2000);
158 +
159 + ilp_ctl = bcma_cc_read32(cc, BCMA_CC_PMU_XTAL_FREQ);
160 + ilp_ctl &= BCMA_CC_PMU_XTAL_FREQ_ILPCTL_MASK;
161 +
162 + bcma_cc_write32(cc, BCMA_CC_PMU_XTAL_FREQ, 0);
163 +
164 + alp_hz = ilp_ctl * 32768 / 4;
165 + return (alp_hz + 50000) / 100000 * 100;
166 +}
167 +
168 +static void bcma_pmu2_pll_init0(struct bcma_drv_cc *cc, u32 xtalfreq)
169 +{
170 + struct bcma_bus *bus = cc->core->bus;
171 + u32 freq_tgt_target = 0, freq_tgt_current;
172 + u32 pll0, mask;
173 +
174 + switch (bus->chipinfo.id) {
175 + case BCMA_CHIP_ID_BCM43142:
176 + /* pmu2_xtaltab0_adfll_485 */
177 + switch (xtalfreq) {
178 + case 12000:
179 + freq_tgt_target = 0x50D52;
180 + break;
181 + case 20000:
182 + freq_tgt_target = 0x307FE;
183 + break;
184 + case 26000:
185 + freq_tgt_target = 0x254EA;
186 + break;
187 + case 37400:
188 + freq_tgt_target = 0x19EF8;
189 + break;
190 + case 52000:
191 + freq_tgt_target = 0x12A75;
192 + break;
193 + }
194 + break;
195 + }
196 +
197 + if (!freq_tgt_target) {
198 + bcma_err(bus, "Unknown TGT frequency for xtalfreq %d\n",
199 + xtalfreq);
200 + return;
201 + }
202 +
203 + pll0 = bcma_chipco_pll_read(cc, BCMA_CC_PMU15_PLL_PLLCTL0);
204 + freq_tgt_current = (pll0 & BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK) >>
205 + BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT;
206 +
207 + if (freq_tgt_current == freq_tgt_target) {
208 + bcma_debug(bus, "Target TGT frequency already set\n");
209 + return;
210 + }
211 +
212 + /* Turn off PLL */
213 + switch (bus->chipinfo.id) {
214 + case BCMA_CHIP_ID_BCM43142:
215 + mask = (u32)~(BCMA_RES_4314_HT_AVAIL |
216 + BCMA_RES_4314_MACPHY_CLK_AVAIL);
217 +
218 + bcma_cc_mask32(cc, BCMA_CC_PMU_MINRES_MSK, mask);
219 + bcma_cc_mask32(cc, BCMA_CC_PMU_MAXRES_MSK, mask);
220 + bcma_wait_value(cc->core, BCMA_CLKCTLST,
221 + BCMA_CLKCTLST_HAVEHT, 0, 20000);
222 + break;
223 + }
224 +
225 + pll0 &= ~BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK;
226 + pll0 |= freq_tgt_target << BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT;
227 + bcma_chipco_pll_write(cc, BCMA_CC_PMU15_PLL_PLLCTL0, pll0);
228 +
229 + /* Flush */
230 + if (cc->pmu.rev >= 2)
231 + bcma_cc_set32(cc, BCMA_CC_PMU_CTL, BCMA_CC_PMU_CTL_PLL_UPD);
232 +
233 + /* TODO: Do we need to update OTP? */
234 +}
235 +
236 +static void bcma_pmu_pll_init(struct bcma_drv_cc *cc)
237 +{
238 + struct bcma_bus *bus = cc->core->bus;
239 + u32 xtalfreq = bcma_pmu_xtalfreq(cc);
240 +
241 + switch (bus->chipinfo.id) {
242 + case BCMA_CHIP_ID_BCM43142:
243 + if (xtalfreq == 0)
244 + xtalfreq = 20000;
245 + bcma_pmu2_pll_init0(cc, xtalfreq);
246 + break;
247 + }
248 +}
249 +
250 static void bcma_pmu_resources_init(struct bcma_drv_cc *cc)
251 {
252 struct bcma_bus *bus = cc->core->bus;
253 @@ -66,6 +169,25 @@ static void bcma_pmu_resources_init(stru
254 min_msk = 0x200D;
255 max_msk = 0xFFFF;
256 break;
257 + case BCMA_CHIP_ID_BCM43142:
258 + min_msk = BCMA_RES_4314_LPLDO_PU |
259 + BCMA_RES_4314_PMU_SLEEP_DIS |
260 + BCMA_RES_4314_PMU_BG_PU |
261 + BCMA_RES_4314_CBUCK_LPOM_PU |
262 + BCMA_RES_4314_CBUCK_PFM_PU |
263 + BCMA_RES_4314_CLDO_PU |
264 + BCMA_RES_4314_LPLDO2_LVM |
265 + BCMA_RES_4314_WL_PMU_PU |
266 + BCMA_RES_4314_LDO3P3_PU |
267 + BCMA_RES_4314_OTP_PU |
268 + BCMA_RES_4314_WL_PWRSW_PU |
269 + BCMA_RES_4314_LQ_AVAIL |
270 + BCMA_RES_4314_LOGIC_RET |
271 + BCMA_RES_4314_MEM_SLEEP |
272 + BCMA_RES_4314_MACPHY_RET |
273 + BCMA_RES_4314_WL_CORE_READY;
274 + max_msk = 0x3FFFFFFF;
275 + break;
276 default:
277 bcma_debug(bus, "PMU resource config unknown or not needed for device 0x%04X\n",
278 bus->chipinfo.id);
279 @@ -165,6 +287,7 @@ void bcma_pmu_init(struct bcma_drv_cc *c
280 bcma_cc_set32(cc, BCMA_CC_PMU_CTL,
281 BCMA_CC_PMU_CTL_NOILPONW);
282
283 + bcma_pmu_pll_init(cc);
284 bcma_pmu_resources_init(cc);
285 bcma_pmu_workarounds(cc);
286 }
287 @@ -480,6 +603,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
288 tmp = BCMA_CC_PMU_CTL_PLL_UPD | BCMA_CC_PMU_CTL_NOILPONW;
289 break;
290
291 + case BCMA_CHIP_ID_BCM43217:
292 case BCMA_CHIP_ID_BCM43227:
293 case BCMA_CHIP_ID_BCM43228:
294 case BCMA_CHIP_ID_BCM43428:
295 --- a/drivers/bcma/driver_chipcommon_sflash.c
296 +++ b/drivers/bcma/driver_chipcommon_sflash.c
297 @@ -30,7 +30,7 @@ struct bcma_sflash_tbl_e {
298 u16 numblocks;
299 };
300
301 -static struct bcma_sflash_tbl_e bcma_sflash_st_tbl[] = {
302 +static const struct bcma_sflash_tbl_e bcma_sflash_st_tbl[] = {
303 { "M25P20", 0x11, 0x10000, 4, },
304 { "M25P40", 0x12, 0x10000, 8, },
305
306 @@ -38,10 +38,10 @@ static struct bcma_sflash_tbl_e bcma_sfl
307 { "M25P32", 0x15, 0x10000, 64, },
308 { "M25P64", 0x16, 0x10000, 128, },
309 { "M25FL128", 0x17, 0x10000, 256, },
310 - { 0 },
311 + { NULL },
312 };
313
314 -static struct bcma_sflash_tbl_e bcma_sflash_sst_tbl[] = {
315 +static const struct bcma_sflash_tbl_e bcma_sflash_sst_tbl[] = {
316 { "SST25WF512", 1, 0x1000, 16, },
317 { "SST25VF512", 0x48, 0x1000, 16, },
318 { "SST25WF010", 2, 0x1000, 32, },
319 @@ -56,10 +56,10 @@ static struct bcma_sflash_tbl_e bcma_sfl
320 { "SST25VF016", 0x41, 0x1000, 512, },
321 { "SST25VF032", 0x4a, 0x1000, 1024, },
322 { "SST25VF064", 0x4b, 0x1000, 2048, },
323 - { 0 },
324 + { NULL },
325 };
326
327 -static struct bcma_sflash_tbl_e bcma_sflash_at_tbl[] = {
328 +static const struct bcma_sflash_tbl_e bcma_sflash_at_tbl[] = {
329 { "AT45DB011", 0xc, 256, 512, },
330 { "AT45DB021", 0x14, 256, 1024, },
331 { "AT45DB041", 0x1c, 256, 2048, },
332 @@ -67,7 +67,7 @@ static struct bcma_sflash_tbl_e bcma_sfl
333 { "AT45DB161", 0x2c, 512, 4096, },
334 { "AT45DB321", 0x34, 512, 8192, },
335 { "AT45DB642", 0x3c, 1024, 8192, },
336 - { 0 },
337 + { NULL },
338 };
339
340 static void bcma_sflash_cmd(struct bcma_drv_cc *cc, u32 opcode)
341 @@ -89,7 +89,7 @@ int bcma_sflash_init(struct bcma_drv_cc
342 {
343 struct bcma_bus *bus = cc->core->bus;
344 struct bcma_sflash *sflash = &cc->sflash;
345 - struct bcma_sflash_tbl_e *e;
346 + const struct bcma_sflash_tbl_e *e;
347 u32 id, id2;
348
349 switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
350 --- a/drivers/bcma/driver_gpio.c
351 +++ b/drivers/bcma/driver_gpio.c
352 @@ -9,6 +9,9 @@
353 */
354
355 #include <linux/gpio.h>
356 +#include <linux/irq.h>
357 +#include <linux/interrupt.h>
358 +#include <linux/irqdomain.h>
359 #include <linux/export.h>
360 #include <linux/bcma/bcma.h>
361
362 @@ -73,19 +76,136 @@ static void bcma_gpio_free(struct gpio_c
363 bcma_chipco_gpio_pullup(cc, 1 << gpio, 0);
364 }
365
366 +#if IS_BUILTIN(CONFIG_BCMA_HOST_SOC)
367 static int bcma_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
368 {
369 struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
370
371 if (cc->core->bus->hosttype == BCMA_HOSTTYPE_SOC)
372 - return bcma_core_irq(cc->core);
373 + return irq_find_mapping(cc->irq_domain, gpio);
374 else
375 return -EINVAL;
376 }
377
378 +static void bcma_gpio_irq_unmask(struct irq_data *d)
379 +{
380 + struct bcma_drv_cc *cc = irq_data_get_irq_chip_data(d);
381 + int gpio = irqd_to_hwirq(d);
382 + u32 val = bcma_chipco_gpio_in(cc, BIT(gpio));
383 +
384 + bcma_chipco_gpio_polarity(cc, BIT(gpio), val);
385 + bcma_chipco_gpio_intmask(cc, BIT(gpio), BIT(gpio));
386 +}
387 +
388 +static void bcma_gpio_irq_mask(struct irq_data *d)
389 +{
390 + struct bcma_drv_cc *cc = irq_data_get_irq_chip_data(d);
391 + int gpio = irqd_to_hwirq(d);
392 +
393 + bcma_chipco_gpio_intmask(cc, BIT(gpio), 0);
394 +}
395 +
396 +static struct irq_chip bcma_gpio_irq_chip = {
397 + .name = "BCMA-GPIO",
398 + .irq_mask = bcma_gpio_irq_mask,
399 + .irq_unmask = bcma_gpio_irq_unmask,
400 +};
401 +
402 +static irqreturn_t bcma_gpio_irq_handler(int irq, void *dev_id)
403 +{
404 + struct bcma_drv_cc *cc = dev_id;
405 + u32 val = bcma_cc_read32(cc, BCMA_CC_GPIOIN);
406 + u32 mask = bcma_cc_read32(cc, BCMA_CC_GPIOIRQ);
407 + u32 pol = bcma_cc_read32(cc, BCMA_CC_GPIOPOL);
408 + unsigned long irqs = (val ^ pol) & mask;
409 + int gpio;
410 +
411 + if (!irqs)
412 + return IRQ_NONE;
413 +
414 + for_each_set_bit(gpio, &irqs, cc->gpio.ngpio)
415 + generic_handle_irq(bcma_gpio_to_irq(&cc->gpio, gpio));
416 + bcma_chipco_gpio_polarity(cc, irqs, val & irqs);
417 +
418 + return IRQ_HANDLED;
419 +}
420 +
421 +static int bcma_gpio_irq_domain_init(struct bcma_drv_cc *cc)
422 +{
423 + struct gpio_chip *chip = &cc->gpio;
424 + int gpio, hwirq, err;
425 +
426 + if (cc->core->bus->hosttype != BCMA_HOSTTYPE_SOC)
427 + return 0;
428 +
429 + cc->irq_domain = irq_domain_add_linear(NULL, chip->ngpio,
430 + &irq_domain_simple_ops, cc);
431 + if (!cc->irq_domain) {
432 + err = -ENODEV;
433 + goto err_irq_domain;
434 + }
435 + for (gpio = 0; gpio < chip->ngpio; gpio++) {
436 + int irq = irq_create_mapping(cc->irq_domain, gpio);
437 +
438 + irq_set_chip_data(irq, cc);
439 + irq_set_chip_and_handler(irq, &bcma_gpio_irq_chip,
440 + handle_simple_irq);
441 + }
442 +
443 + hwirq = bcma_core_irq(cc->core);
444 + err = request_irq(hwirq, bcma_gpio_irq_handler, IRQF_SHARED, "gpio",
445 + cc);
446 + if (err)
447 + goto err_req_irq;
448 +
449 + bcma_chipco_gpio_intmask(cc, ~0, 0);
450 + bcma_cc_set32(cc, BCMA_CC_IRQMASK, BCMA_CC_IRQ_GPIO);
451 +
452 + return 0;
453 +
454 +err_req_irq:
455 + for (gpio = 0; gpio < chip->ngpio; gpio++) {
456 + int irq = irq_find_mapping(cc->irq_domain, gpio);
457 +
458 + irq_dispose_mapping(irq);
459 + }
460 + irq_domain_remove(cc->irq_domain);
461 +err_irq_domain:
462 + return err;
463 +}
464 +
465 +static void bcma_gpio_irq_domain_exit(struct bcma_drv_cc *cc)
466 +{
467 + struct gpio_chip *chip = &cc->gpio;
468 + int gpio;
469 +
470 + if (cc->core->bus->hosttype != BCMA_HOSTTYPE_SOC)
471 + return;
472 +
473 + bcma_cc_mask32(cc, BCMA_CC_IRQMASK, ~BCMA_CC_IRQ_GPIO);
474 + free_irq(bcma_core_irq(cc->core), cc);
475 + for (gpio = 0; gpio < chip->ngpio; gpio++) {
476 + int irq = irq_find_mapping(cc->irq_domain, gpio);
477 +
478 + irq_dispose_mapping(irq);
479 + }
480 + irq_domain_remove(cc->irq_domain);
481 +}
482 +#else
483 +static int bcma_gpio_irq_domain_init(struct bcma_drv_cc *cc)
484 +{
485 + return 0;
486 +}
487 +
488 +static void bcma_gpio_irq_domain_exit(struct bcma_drv_cc *cc)
489 +{
490 +}
491 +#endif
492 +
493 int bcma_gpio_init(struct bcma_drv_cc *cc)
494 {
495 struct gpio_chip *chip = &cc->gpio;
496 + int err;
497
498 chip->label = "bcma_gpio";
499 chip->owner = THIS_MODULE;
500 @@ -95,8 +215,18 @@ int bcma_gpio_init(struct bcma_drv_cc *c
501 chip->set = bcma_gpio_set_value;
502 chip->direction_input = bcma_gpio_direction_input;
503 chip->direction_output = bcma_gpio_direction_output;
504 +#if IS_BUILTIN(CONFIG_BCMA_HOST_SOC)
505 chip->to_irq = bcma_gpio_to_irq;
506 - chip->ngpio = 16;
507 +#endif
508 + switch (cc->core->bus->chipinfo.id) {
509 + case BCMA_CHIP_ID_BCM5357:
510 + case BCMA_CHIP_ID_BCM53572:
511 + chip->ngpio = 32;
512 + break;
513 + default:
514 + chip->ngpio = 16;
515 + }
516 +
517 /* There is just one SoC in one device and its GPIO addresses should be
518 * deterministic to address them more easily. The other buses could get
519 * a random base number. */
520 @@ -105,10 +235,21 @@ int bcma_gpio_init(struct bcma_drv_cc *c
521 else
522 chip->base = -1;
523
524 - return gpiochip_add(chip);
525 + err = bcma_gpio_irq_domain_init(cc);
526 + if (err)
527 + return err;
528 +
529 + err = gpiochip_add(chip);
530 + if (err) {
531 + bcma_gpio_irq_domain_exit(cc);
532 + return err;
533 + }
534 +
535 + return 0;
536 }
537
538 int bcma_gpio_unregister(struct bcma_drv_cc *cc)
539 {
540 + bcma_gpio_irq_domain_exit(cc);
541 return gpiochip_remove(&cc->gpio);
542 }
543 --- a/drivers/bcma/driver_pci.c
544 +++ b/drivers/bcma/driver_pci.c
545 @@ -31,7 +31,7 @@ static void bcma_pcie_write(struct bcma_
546 pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_DATA, data);
547 }
548
549 -static void bcma_pcie_mdio_set_phy(struct bcma_drv_pci *pc, u8 phy)
550 +static void bcma_pcie_mdio_set_phy(struct bcma_drv_pci *pc, u16 phy)
551 {
552 u32 v;
553 int i;
554 @@ -55,7 +55,7 @@ static void bcma_pcie_mdio_set_phy(struc
555 }
556 }
557
558 -static u16 bcma_pcie_mdio_read(struct bcma_drv_pci *pc, u8 device, u8 address)
559 +static u16 bcma_pcie_mdio_read(struct bcma_drv_pci *pc, u16 device, u8 address)
560 {
561 int max_retries = 10;
562 u16 ret = 0;
563 @@ -98,7 +98,7 @@ static u16 bcma_pcie_mdio_read(struct bc
564 return ret;
565 }
566
567 -static void bcma_pcie_mdio_write(struct bcma_drv_pci *pc, u8 device,
568 +static void bcma_pcie_mdio_write(struct bcma_drv_pci *pc, u16 device,
569 u8 address, u16 data)
570 {
571 int max_retries = 10;
572 @@ -137,6 +137,13 @@ static void bcma_pcie_mdio_write(struct
573 pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
574 }
575
576 +static u16 bcma_pcie_mdio_writeread(struct bcma_drv_pci *pc, u16 device,
577 + u8 address, u16 data)
578 +{
579 + bcma_pcie_mdio_write(pc, device, address, data);
580 + return bcma_pcie_mdio_read(pc, device, address);
581 +}
582 +
583 /**************************************************
584 * Workarounds.
585 **************************************************/
586 @@ -229,6 +236,32 @@ void bcma_core_pci_init(struct bcma_drv_
587 bcma_core_pci_clientmode_init(pc);
588 }
589
590 +void bcma_core_pci_power_save(struct bcma_bus *bus, bool up)
591 +{
592 + struct bcma_drv_pci *pc;
593 + u16 data;
594 +
595 + if (bus->hosttype != BCMA_HOSTTYPE_PCI)
596 + return;
597 +
598 + pc = &bus->drv_pci[0];
599 +
600 + if (pc->core->id.rev >= 15 && pc->core->id.rev <= 20) {
601 + data = up ? 0x74 : 0x7C;
602 + bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
603 + BCMA_CORE_PCI_MDIO_BLK1_MGMT1, 0x7F64);
604 + bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
605 + BCMA_CORE_PCI_MDIO_BLK1_MGMT3, data);
606 + } else if (pc->core->id.rev >= 21 && pc->core->id.rev <= 22) {
607 + data = up ? 0x75 : 0x7D;
608 + bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
609 + BCMA_CORE_PCI_MDIO_BLK1_MGMT1, 0x7E65);
610 + bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
611 + BCMA_CORE_PCI_MDIO_BLK1_MGMT3, data);
612 + }
613 +}
614 +EXPORT_SYMBOL_GPL(bcma_core_pci_power_save);
615 +
616 int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc, struct bcma_device *core,
617 bool enable)
618 {
619 @@ -262,7 +295,7 @@ out:
620 }
621 EXPORT_SYMBOL_GPL(bcma_core_pci_irq_ctl);
622
623 -void bcma_core_pci_extend_L1timer(struct bcma_drv_pci *pc, bool extend)
624 +static void bcma_core_pci_extend_L1timer(struct bcma_drv_pci *pc, bool extend)
625 {
626 u32 w;
627
628 @@ -274,4 +307,29 @@ void bcma_core_pci_extend_L1timer(struct
629 bcma_pcie_write(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG, w);
630 bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG);
631 }
632 -EXPORT_SYMBOL_GPL(bcma_core_pci_extend_L1timer);
633 +
634 +void bcma_core_pci_up(struct bcma_bus *bus)
635 +{
636 + struct bcma_drv_pci *pc;
637 +
638 + if (bus->hosttype != BCMA_HOSTTYPE_PCI)
639 + return;
640 +
641 + pc = &bus->drv_pci[0];
642 +
643 + bcma_core_pci_extend_L1timer(pc, true);
644 +}
645 +EXPORT_SYMBOL_GPL(bcma_core_pci_up);
646 +
647 +void bcma_core_pci_down(struct bcma_bus *bus)
648 +{
649 + struct bcma_drv_pci *pc;
650 +
651 + if (bus->hosttype != BCMA_HOSTTYPE_PCI)
652 + return;
653 +
654 + pc = &bus->drv_pci[0];
655 +
656 + bcma_core_pci_extend_L1timer(pc, false);
657 +}
658 +EXPORT_SYMBOL_GPL(bcma_core_pci_down);
659 --- a/drivers/bcma/driver_pci_host.c
660 +++ b/drivers/bcma/driver_pci_host.c
661 @@ -581,6 +581,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI
662 int bcma_core_pci_plat_dev_init(struct pci_dev *dev)
663 {
664 struct bcma_drv_pci_host *pc_host;
665 + int readrq;
666
667 if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
668 /* This is not a device on the PCI-core bridge. */
669 @@ -595,6 +596,11 @@ int bcma_core_pci_plat_dev_init(struct p
670 dev->irq = bcma_core_irq(pc_host->pdev->core);
671 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
672
673 + readrq = pcie_get_readrq(dev);
674 + if (readrq > 128) {
675 + pr_info("change PCIe max read request size from %i to 128\n", readrq);
676 + pcie_set_readrq(dev, 128);
677 + }
678 return 0;
679 }
680 EXPORT_SYMBOL(bcma_core_pci_plat_dev_init);
681 --- /dev/null
682 +++ b/drivers/bcma/driver_pcie2.c
683 @@ -0,0 +1,175 @@
684 +/*
685 + * Broadcom specific AMBA
686 + * PCIe Gen 2 Core
687 + *
688 + * Copyright 2014, Broadcom Corporation
689 + * Copyright 2014, Rafał Miłecki <zajec5@gmail.com>
690 + *
691 + * Licensed under the GNU/GPL. See COPYING for details.
692 + */
693 +
694 +#include "bcma_private.h"
695 +#include <linux/bcma/bcma.h>
696 +
697 +/**************************************************
698 + * R/W ops.
699 + **************************************************/
700 +
701 +#if 0
702 +static u32 bcma_core_pcie2_cfg_read(struct bcma_drv_pcie2 *pcie2, u32 addr)
703 +{
704 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, addr);
705 + pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR);
706 + return pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA);
707 +}
708 +#endif
709 +
710 +static void bcma_core_pcie2_cfg_write(struct bcma_drv_pcie2 *pcie2, u32 addr,
711 + u32 val)
712 +{
713 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, addr);
714 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, val);
715 +}
716 +
717 +/**************************************************
718 + * Init.
719 + **************************************************/
720 +
721 +static u32 bcma_core_pcie2_war_delay_perst_enab(struct bcma_drv_pcie2 *pcie2,
722 + bool enable)
723 +{
724 + u32 val;
725 +
726 + /* restore back to default */
727 + val = pcie2_read32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL);
728 + val |= PCIE2_CLKC_DLYPERST;
729 + val &= ~PCIE2_CLKC_DISSPROMLD;
730 + if (enable) {
731 + val &= ~PCIE2_CLKC_DLYPERST;
732 + val |= PCIE2_CLKC_DISSPROMLD;
733 + }
734 + pcie2_write32(pcie2, (BCMA_CORE_PCIE2_CLK_CONTROL), val);
735 + /* flush */
736 + return pcie2_read32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL);
737 +}
738 +
739 +static void bcma_core_pcie2_set_ltr_vals(struct bcma_drv_pcie2 *pcie2)
740 +{
741 + /* LTR0 */
742 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x844);
743 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x883c883c);
744 + /* LTR1 */
745 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x848);
746 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x88648864);
747 + /* LTR2 */
748 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x84C);
749 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x90039003);
750 +}
751 +
752 +static void bcma_core_pcie2_hw_ltr_war(struct bcma_drv_pcie2 *pcie2)
753 +{
754 + u8 core_rev = pcie2->core->id.rev;
755 + u32 devstsctr2;
756 +
757 + if (core_rev < 2 || core_rev == 10 || core_rev > 13)
758 + return;
759 +
760 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
761 + PCIE2_CAP_DEVSTSCTRL2_OFFSET);
762 + devstsctr2 = pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA);
763 + if (devstsctr2 & PCIE2_CAP_DEVSTSCTRL2_LTRENAB) {
764 + /* force the right LTR values */
765 + bcma_core_pcie2_set_ltr_vals(pcie2);
766 +
767 + /* TODO:
768 + si_core_wrapperreg(pcie2, 3, 0x60, 0x8080, 0); */
769 +
770 + /* enable the LTR */
771 + devstsctr2 |= PCIE2_CAP_DEVSTSCTRL2_LTRENAB;
772 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
773 + PCIE2_CAP_DEVSTSCTRL2_OFFSET);
774 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, devstsctr2);
775 +
776 + /* set the LTR state to be active */
777 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_LTR_STATE,
778 + PCIE2_LTR_ACTIVE);
779 + usleep_range(1000, 2000);
780 +
781 + /* set the LTR state to be sleep */
782 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_LTR_STATE,
783 + PCIE2_LTR_SLEEP);
784 + usleep_range(1000, 2000);
785 + }
786 +}
787 +
788 +static void pciedev_crwlpciegen2(struct bcma_drv_pcie2 *pcie2)
789 +{
790 + u8 core_rev = pcie2->core->id.rev;
791 + bool pciewar160, pciewar162;
792 +
793 + pciewar160 = core_rev == 7 || core_rev == 9 || core_rev == 11;
794 + pciewar162 = core_rev == 5 || core_rev == 7 || core_rev == 8 ||
795 + core_rev == 9 || core_rev == 11;
796 +
797 + if (!pciewar160 && !pciewar162)
798 + return;
799 +
800 +/* TODO */
801 +#if 0
802 + pcie2_set32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL,
803 + PCIE_DISABLE_L1CLK_GATING);
804 +#if 0
805 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
806 + PCIEGEN2_COE_PVT_TL_CTRL_0);
807 + pcie2_mask32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA,
808 + ~(1 << COE_PVT_TL_CTRL_0_PM_DIS_L1_REENTRY_BIT));
809 +#endif
810 +#endif
811 +}
812 +
813 +static void pciedev_crwlpciegen2_180(struct bcma_drv_pcie2 *pcie2)
814 +{
815 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, PCIE2_PMCR_REFUP);
816 + pcie2_set32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x1f);
817 +}
818 +
819 +static void pciedev_crwlpciegen2_182(struct bcma_drv_pcie2 *pcie2)
820 +{
821 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, PCIE2_SBMBX);
822 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 1 << 0);
823 +}
824 +
825 +static void pciedev_reg_pm_clk_period(struct bcma_drv_pcie2 *pcie2)
826 +{
827 + struct bcma_drv_cc *drv_cc = &pcie2->core->bus->drv_cc;
828 + u8 core_rev = pcie2->core->id.rev;
829 + u32 alp_khz, pm_value;
830 +
831 + if (core_rev <= 13) {
832 + alp_khz = bcma_pmu_get_alp_clock(drv_cc) / 1000;
833 + pm_value = (1000000 * 2) / alp_khz;
834 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
835 + PCIE2_PVT_REG_PM_CLK_PERIOD);
836 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, pm_value);
837 + }
838 +}
839 +
840 +void bcma_core_pcie2_init(struct bcma_drv_pcie2 *pcie2)
841 +{
842 + struct bcma_chipinfo *ci = &pcie2->core->bus->chipinfo;
843 + u32 tmp;
844 +
845 + tmp = pcie2_read32(pcie2, BCMA_CORE_PCIE2_SPROM(54));
846 + if ((tmp & 0xe) >> 1 == 2)
847 + bcma_core_pcie2_cfg_write(pcie2, 0x4e0, 0x17);
848 +
849 + /* TODO: Do we need pcie_reqsize? */
850 +
851 + if (ci->id == BCMA_CHIP_ID_BCM4360 && ci->rev > 3)
852 + bcma_core_pcie2_war_delay_perst_enab(pcie2, true);
853 + bcma_core_pcie2_hw_ltr_war(pcie2);
854 + pciedev_crwlpciegen2(pcie2);
855 + pciedev_reg_pm_clk_period(pcie2);
856 + pciedev_crwlpciegen2_180(pcie2);
857 + pciedev_crwlpciegen2_182(pcie2);
858 +}
859 --- a/drivers/bcma/host_pci.c
860 +++ b/drivers/bcma/host_pci.c
861 @@ -188,8 +188,11 @@ static int bcma_host_pci_probe(struct pc
862 pci_write_config_dword(dev, 0x40, val & 0xffff00ff);
863
864 /* SSB needed additional powering up, do we have any AMBA PCI cards? */
865 - if (!pci_is_pcie(dev))
866 - bcma_err(bus, "PCI card detected, report problems.\n");
867 + if (!pci_is_pcie(dev)) {
868 + bcma_err(bus, "PCI card detected, they are not supported.\n");
869 + err = -ENXIO;
870 + goto err_pci_release_regions;
871 + }
872
873 /* Map MMIO */
874 err = -ENOMEM;
875 @@ -235,7 +238,6 @@ static void bcma_host_pci_remove(struct
876 pci_release_regions(dev);
877 pci_disable_device(dev);
878 kfree(bus);
879 - pci_set_drvdata(dev, NULL);
880 }
881
882 #ifdef CONFIG_PM_SLEEP
883 @@ -267,14 +269,17 @@ static SIMPLE_DEV_PM_OPS(bcma_pm_ops, bc
884
885 #endif /* CONFIG_PM_SLEEP */
886
887 -static DEFINE_PCI_DEVICE_TABLE(bcma_pci_bridge_tbl) = {
888 +static const struct pci_device_id bcma_pci_bridge_tbl[] = {
889 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x0576) },
890 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4313) },
891 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43224) },
892 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4331) },
893 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4353) },
894 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4357) },
895 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4358) },
896 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4359) },
897 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4365) },
898 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43a9) },
899 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4727) },
900 { 0, },
901 };
902 --- a/drivers/bcma/main.c
903 +++ b/drivers/bcma/main.c
904 @@ -69,28 +69,36 @@ static u16 bcma_cc_core_id(struct bcma_b
905 return BCMA_CORE_CHIPCOMMON;
906 }
907
908 -struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid)
909 +struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
910 + u8 unit)
911 {
912 struct bcma_device *core;
913
914 list_for_each_entry(core, &bus->cores, list) {
915 - if (core->id.id == coreid)
916 + if (core->id.id == coreid && core->core_unit == unit)
917 return core;
918 }
919 return NULL;
920 }
921 -EXPORT_SYMBOL_GPL(bcma_find_core);
922 +EXPORT_SYMBOL_GPL(bcma_find_core_unit);
923
924 -struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
925 - u8 unit)
926 +bool bcma_wait_value(struct bcma_device *core, u16 reg, u32 mask, u32 value,
927 + int timeout)
928 {
929 - struct bcma_device *core;
930 + unsigned long deadline = jiffies + timeout;
931 + u32 val;
932
933 - list_for_each_entry(core, &bus->cores, list) {
934 - if (core->id.id == coreid && core->core_unit == unit)
935 - return core;
936 - }
937 - return NULL;
938 + do {
939 + val = bcma_read32(core, reg);
940 + if ((val & mask) == value)
941 + return true;
942 + cpu_relax();
943 + udelay(10);
944 + } while (!time_after_eq(jiffies, deadline));
945 +
946 + bcma_warn(core->bus, "Timeout waiting for register 0x%04X!\n", reg);
947 +
948 + return false;
949 }
950
951 static void bcma_release_core_dev(struct device *dev)
952 @@ -115,6 +123,7 @@ static int bcma_register_cores(struct bc
953 case BCMA_CORE_CHIPCOMMON:
954 case BCMA_CORE_PCI:
955 case BCMA_CORE_PCIE:
956 + case BCMA_CORE_PCIE2:
957 case BCMA_CORE_MIPS_74K:
958 case BCMA_CORE_4706_MAC_GBIT_COMMON:
959 continue;
960 @@ -148,6 +157,7 @@ static int bcma_register_cores(struct bc
961 bcma_err(bus,
962 "Could not register dev for core 0x%03X\n",
963 core->id.id);
964 + put_device(&core->dev);
965 continue;
966 }
967 core->dev_registered = true;
968 @@ -218,7 +228,7 @@ int bcma_bus_register(struct bcma_bus *b
969 err = bcma_bus_scan(bus);
970 if (err) {
971 bcma_err(bus, "Failed to scan: %d\n", err);
972 - return -1;
973 + return err;
974 }
975
976 /* Early init CC core */
977 @@ -263,6 +273,13 @@ int bcma_bus_register(struct bcma_bus *b
978 bcma_core_pci_init(&bus->drv_pci[1]);
979 }
980
981 + /* Init PCIe Gen 2 core */
982 + core = bcma_find_core_unit(bus, BCMA_CORE_PCIE2, 0);
983 + if (core) {
984 + bus->drv_pcie2.core = core;
985 + bcma_core_pcie2_init(&bus->drv_pcie2);
986 + }
987 +
988 /* Init GBIT MAC COMMON core */
989 core = bcma_find_core(bus, BCMA_CORE_4706_MAC_GBIT_COMMON);
990 if (core) {
991 --- a/drivers/bcma/scan.c
992 +++ b/drivers/bcma/scan.c
993 @@ -32,6 +32,18 @@ static const struct bcma_device_id_name
994 { BCMA_CORE_4706_CHIPCOMMON, "BCM4706 ChipCommon" },
995 { BCMA_CORE_4706_SOC_RAM, "BCM4706 SOC RAM" },
996 { BCMA_CORE_4706_MAC_GBIT, "BCM4706 GBit MAC" },
997 + { BCMA_CORE_PCIEG2, "PCIe Gen 2" },
998 + { BCMA_CORE_DMA, "DMA" },
999 + { BCMA_CORE_SDIO3, "SDIO3" },
1000 + { BCMA_CORE_USB20, "USB 2.0" },
1001 + { BCMA_CORE_USB30, "USB 3.0" },
1002 + { BCMA_CORE_A9JTAG, "ARM Cortex A9 JTAG" },
1003 + { BCMA_CORE_DDR23, "Denali DDR2/DDR3 memory controller" },
1004 + { BCMA_CORE_ROM, "ROM" },
1005 + { BCMA_CORE_NAND, "NAND flash controller" },
1006 + { BCMA_CORE_QSPI, "SPI flash controller" },
1007 + { BCMA_CORE_CHIPCOMMON_B, "Chipcommon B" },
1008 + { BCMA_CORE_ARMCA9, "ARM Cortex A9 core (ihost)" },
1009 { BCMA_CORE_AMEMC, "AMEMC (DDR)" },
1010 { BCMA_CORE_ALTA, "ALTA (I2S)" },
1011 { BCMA_CORE_INVALID, "Invalid" },
1012 @@ -201,7 +213,7 @@ static s32 bcma_erom_get_mst_port(struct
1013 return ent;
1014 }
1015
1016 -static s32 bcma_erom_get_addr_desc(struct bcma_bus *bus, u32 __iomem **eromptr,
1017 +static u32 bcma_erom_get_addr_desc(struct bcma_bus *bus, u32 __iomem **eromptr,
1018 u32 type, u8 port)
1019 {
1020 u32 addrl, addrh, sizel, sizeh = 0;
1021 @@ -213,7 +225,7 @@ static s32 bcma_erom_get_addr_desc(struc
1022 ((ent & SCAN_ADDR_TYPE) != type) ||
1023 (((ent & SCAN_ADDR_PORT) >> SCAN_ADDR_PORT_SHIFT) != port)) {
1024 bcma_erom_push_ent(eromptr);
1025 - return -EINVAL;
1026 + return (u32)-EINVAL;
1027 }
1028
1029 addrl = ent & SCAN_ADDR_ADDR;
1030 @@ -257,11 +269,13 @@ static struct bcma_device *bcma_find_cor
1031 return NULL;
1032 }
1033
1034 +#define IS_ERR_VALUE_U32(x) ((x) >= (u32)-MAX_ERRNO)
1035 +
1036 static int bcma_get_next_core(struct bcma_bus *bus, u32 __iomem **eromptr,
1037 struct bcma_device_id *match, int core_num,
1038 struct bcma_device *core)
1039 {
1040 - s32 tmp;
1041 + u32 tmp;
1042 u8 i, j;
1043 s32 cia, cib;
1044 u8 ports[2], wrappers[2];
1045 @@ -339,11 +353,11 @@ static int bcma_get_next_core(struct bcm
1046 * the main register space for the core
1047 */
1048 tmp = bcma_erom_get_addr_desc(bus, eromptr, SCAN_ADDR_TYPE_SLAVE, 0);
1049 - if (tmp <= 0) {
1050 + if (tmp == 0 || IS_ERR_VALUE_U32(tmp)) {
1051 /* Try again to see if it is a bridge */
1052 tmp = bcma_erom_get_addr_desc(bus, eromptr,
1053 SCAN_ADDR_TYPE_BRIDGE, 0);
1054 - if (tmp <= 0) {
1055 + if (tmp == 0 || IS_ERR_VALUE_U32(tmp)) {
1056 return -EILSEQ;
1057 } else {
1058 bcma_info(bus, "Bridge found\n");
1059 @@ -357,7 +371,7 @@ static int bcma_get_next_core(struct bcm
1060 for (j = 0; ; j++) {
1061 tmp = bcma_erom_get_addr_desc(bus, eromptr,
1062 SCAN_ADDR_TYPE_SLAVE, i);
1063 - if (tmp < 0) {
1064 + if (IS_ERR_VALUE_U32(tmp)) {
1065 /* no more entries for port _i_ */
1066 /* pr_debug("erom: slave port %d "
1067 * "has %d descriptors\n", i, j); */
1068 @@ -374,7 +388,7 @@ static int bcma_get_next_core(struct bcm
1069 for (j = 0; ; j++) {
1070 tmp = bcma_erom_get_addr_desc(bus, eromptr,
1071 SCAN_ADDR_TYPE_MWRAP, i);
1072 - if (tmp < 0) {
1073 + if (IS_ERR_VALUE_U32(tmp)) {
1074 /* no more entries for port _i_ */
1075 /* pr_debug("erom: master wrapper %d "
1076 * "has %d descriptors\n", i, j); */
1077 @@ -392,7 +406,7 @@ static int bcma_get_next_core(struct bcm
1078 for (j = 0; ; j++) {
1079 tmp = bcma_erom_get_addr_desc(bus, eromptr,
1080 SCAN_ADDR_TYPE_SWRAP, i + hack);
1081 - if (tmp < 0) {
1082 + if (IS_ERR_VALUE_U32(tmp)) {
1083 /* no more entries for port _i_ */
1084 /* pr_debug("erom: master wrapper %d "
1085 * has %d descriptors\n", i, j); */
1086 --- a/drivers/bcma/sprom.c
1087 +++ b/drivers/bcma/sprom.c
1088 @@ -72,12 +72,12 @@ fail:
1089 * R/W ops.
1090 **************************************************/
1091
1092 -static void bcma_sprom_read(struct bcma_bus *bus, u16 offset, u16 *sprom)
1093 +static void bcma_sprom_read(struct bcma_bus *bus, u16 offset, u16 *sprom,
1094 + size_t words)
1095 {
1096 int i;
1097 - for (i = 0; i < SSB_SPROMSIZE_WORDS_R4; i++)
1098 - sprom[i] = bcma_read16(bus->drv_cc.core,
1099 - offset + (i * 2));
1100 + for (i = 0; i < words; i++)
1101 + sprom[i] = bcma_read16(bus->drv_cc.core, offset + (i * 2));
1102 }
1103
1104 /**************************************************
1105 @@ -124,29 +124,29 @@ static inline u8 bcma_crc8(u8 crc, u8 da
1106 return t[crc ^ data];
1107 }
1108
1109 -static u8 bcma_sprom_crc(const u16 *sprom)
1110 +static u8 bcma_sprom_crc(const u16 *sprom, size_t words)
1111 {
1112 int word;
1113 u8 crc = 0xFF;
1114
1115 - for (word = 0; word < SSB_SPROMSIZE_WORDS_R4 - 1; word++) {
1116 + for (word = 0; word < words - 1; word++) {
1117 crc = bcma_crc8(crc, sprom[word] & 0x00FF);
1118 crc = bcma_crc8(crc, (sprom[word] & 0xFF00) >> 8);
1119 }
1120 - crc = bcma_crc8(crc, sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & 0x00FF);
1121 + crc = bcma_crc8(crc, sprom[words - 1] & 0x00FF);
1122 crc ^= 0xFF;
1123
1124 return crc;
1125 }
1126
1127 -static int bcma_sprom_check_crc(const u16 *sprom)
1128 +static int bcma_sprom_check_crc(const u16 *sprom, size_t words)
1129 {
1130 u8 crc;
1131 u8 expected_crc;
1132 u16 tmp;
1133
1134 - crc = bcma_sprom_crc(sprom);
1135 - tmp = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & SSB_SPROM_REVISION_CRC;
1136 + crc = bcma_sprom_crc(sprom, words);
1137 + tmp = sprom[words - 1] & SSB_SPROM_REVISION_CRC;
1138 expected_crc = tmp >> SSB_SPROM_REVISION_CRC_SHIFT;
1139 if (crc != expected_crc)
1140 return -EPROTO;
1141 @@ -154,21 +154,25 @@ static int bcma_sprom_check_crc(const u1
1142 return 0;
1143 }
1144
1145 -static int bcma_sprom_valid(const u16 *sprom)
1146 +static int bcma_sprom_valid(struct bcma_bus *bus, const u16 *sprom,
1147 + size_t words)
1148 {
1149 u16 revision;
1150 int err;
1151
1152 - err = bcma_sprom_check_crc(sprom);
1153 + err = bcma_sprom_check_crc(sprom, words);
1154 if (err)
1155 return err;
1156
1157 - revision = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & SSB_SPROM_REVISION_REV;
1158 - if (revision != 8 && revision != 9) {
1159 + revision = sprom[words - 1] & SSB_SPROM_REVISION_REV;
1160 + if (revision != 8 && revision != 9 && revision != 10) {
1161 pr_err("Unsupported SPROM revision: %d\n", revision);
1162 return -ENOENT;
1163 }
1164
1165 + bus->sprom.revision = revision;
1166 + bcma_debug(bus, "Found SPROM revision %d\n", revision);
1167 +
1168 return 0;
1169 }
1170
1171 @@ -197,6 +201,23 @@ static int bcma_sprom_valid(const u16 *s
1172 SPEX(_field[7], _offset + 14, _mask, _shift); \
1173 } while (0)
1174
1175 +static s8 sprom_extract_antgain(const u16 *in, u16 offset, u16 mask, u16 shift)
1176 +{
1177 + u16 v;
1178 + u8 gain;
1179 +
1180 + v = in[SPOFF(offset)];
1181 + gain = (v & mask) >> shift;
1182 + if (gain == 0xFF) {
1183 + gain = 8; /* If unset use 2dBm */
1184 + } else {
1185 + /* Q5.2 Fractional part is stored in 0xC0 */
1186 + gain = ((gain & 0xC0) >> 6) | ((gain & 0x3F) << 2);
1187 + }
1188 +
1189 + return (s8)gain;
1190 +}
1191 +
1192 static void bcma_sprom_extract_r8(struct bcma_bus *bus, const u16 *sprom)
1193 {
1194 u16 v, o;
1195 @@ -208,9 +229,6 @@ static void bcma_sprom_extract_r8(struct
1196 BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
1197 ARRAY_SIZE(bus->sprom.core_pwr_info));
1198
1199 - bus->sprom.revision = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] &
1200 - SSB_SPROM_REVISION_REV;
1201 -
1202 for (i = 0; i < 3; i++) {
1203 v = sprom[SPOFF(SSB_SPROM8_IL0MAC) + i];
1204 *(((__be16 *)bus->sprom.il0mac) + i) = cpu_to_be16(v);
1205 @@ -380,14 +398,22 @@ static void bcma_sprom_extract_r8(struct
1206 SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, ~0, 0);
1207
1208 /* Extract the antenna gain values. */
1209 - SPEX(antenna_gain.a0, SSB_SPROM8_AGAIN01,
1210 - SSB_SPROM8_AGAIN0, SSB_SPROM8_AGAIN0_SHIFT);
1211 - SPEX(antenna_gain.a1, SSB_SPROM8_AGAIN01,
1212 - SSB_SPROM8_AGAIN1, SSB_SPROM8_AGAIN1_SHIFT);
1213 - SPEX(antenna_gain.a2, SSB_SPROM8_AGAIN23,
1214 - SSB_SPROM8_AGAIN2, SSB_SPROM8_AGAIN2_SHIFT);
1215 - SPEX(antenna_gain.a3, SSB_SPROM8_AGAIN23,
1216 - SSB_SPROM8_AGAIN3, SSB_SPROM8_AGAIN3_SHIFT);
1217 + bus->sprom.antenna_gain.a0 = sprom_extract_antgain(sprom,
1218 + SSB_SPROM8_AGAIN01,
1219 + SSB_SPROM8_AGAIN0,
1220 + SSB_SPROM8_AGAIN0_SHIFT);
1221 + bus->sprom.antenna_gain.a1 = sprom_extract_antgain(sprom,
1222 + SSB_SPROM8_AGAIN01,
1223 + SSB_SPROM8_AGAIN1,
1224 + SSB_SPROM8_AGAIN1_SHIFT);
1225 + bus->sprom.antenna_gain.a2 = sprom_extract_antgain(sprom,
1226 + SSB_SPROM8_AGAIN23,
1227 + SSB_SPROM8_AGAIN2,
1228 + SSB_SPROM8_AGAIN2_SHIFT);
1229 + bus->sprom.antenna_gain.a3 = sprom_extract_antgain(sprom,
1230 + SSB_SPROM8_AGAIN23,
1231 + SSB_SPROM8_AGAIN3,
1232 + SSB_SPROM8_AGAIN3_SHIFT);
1233
1234 SPEX(leddc_on_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_ON,
1235 SSB_SPROM8_LEDDC_ON_SHIFT);
1236 @@ -502,12 +528,13 @@ static bool bcma_sprom_onchip_available(
1237 case BCMA_CHIP_ID_BCM4331:
1238 present = chip_status & BCMA_CC_CHIPST_4331_OTP_PRESENT;
1239 break;
1240 -
1241 + case BCMA_CHIP_ID_BCM43142:
1242 case BCMA_CHIP_ID_BCM43224:
1243 case BCMA_CHIP_ID_BCM43225:
1244 /* for these chips OTP is always available */
1245 present = true;
1246 break;
1247 + case BCMA_CHIP_ID_BCM43217:
1248 case BCMA_CHIP_ID_BCM43227:
1249 case BCMA_CHIP_ID_BCM43228:
1250 case BCMA_CHIP_ID_BCM43428:
1251 @@ -550,7 +577,9 @@ int bcma_sprom_get(struct bcma_bus *bus)
1252 {
1253 u16 offset = BCMA_CC_SPROM;
1254 u16 *sprom;
1255 - int err = 0;
1256 + size_t sprom_sizes[] = { SSB_SPROMSIZE_WORDS_R4,
1257 + SSB_SPROMSIZE_WORDS_R10, };
1258 + int i, err = 0;
1259
1260 if (!bus->drv_cc.core)
1261 return -EOPNOTSUPP;
1262 @@ -579,32 +608,37 @@ int bcma_sprom_get(struct bcma_bus *bus)
1263 }
1264 }
1265
1266 - sprom = kcalloc(SSB_SPROMSIZE_WORDS_R4, sizeof(u16),
1267 - GFP_KERNEL);
1268 - if (!sprom)
1269 - return -ENOMEM;
1270 -
1271 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4331 ||
1272 bus->chipinfo.id == BCMA_CHIP_ID_BCM43431)
1273 bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, false);
1274
1275 bcma_debug(bus, "SPROM offset 0x%x\n", offset);
1276 - bcma_sprom_read(bus, offset, sprom);
1277 + for (i = 0; i < ARRAY_SIZE(sprom_sizes); i++) {
1278 + size_t words = sprom_sizes[i];
1279 +
1280 + sprom = kcalloc(words, sizeof(u16), GFP_KERNEL);
1281 + if (!sprom)
1282 + return -ENOMEM;
1283 +
1284 + bcma_sprom_read(bus, offset, sprom, words);
1285 + err = bcma_sprom_valid(bus, sprom, words);
1286 + if (!err)
1287 + break;
1288 +
1289 + kfree(sprom);
1290 + }
1291
1292 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4331 ||
1293 bus->chipinfo.id == BCMA_CHIP_ID_BCM43431)
1294 bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, true);
1295
1296 - err = bcma_sprom_valid(sprom);
1297 if (err) {
1298 - bcma_warn(bus, "invalid sprom read from the PCIe card, try to use fallback sprom\n");
1299 + bcma_warn(bus, "Invalid SPROM read from the PCIe card, trying to use fallback SPROM\n");
1300 err = bcma_fill_sprom_with_fallback(bus, &bus->sprom);
1301 - goto out;
1302 + } else {
1303 + bcma_sprom_extract_r8(bus, sprom);
1304 + kfree(sprom);
1305 }
1306
1307 - bcma_sprom_extract_r8(bus, sprom);
1308 -
1309 -out:
1310 - kfree(sprom);
1311 return err;
1312 }
1313 --- a/include/linux/bcma/bcma.h
1314 +++ b/include/linux/bcma/bcma.h
1315 @@ -6,6 +6,7 @@
1316
1317 #include <linux/bcma/bcma_driver_chipcommon.h>
1318 #include <linux/bcma/bcma_driver_pci.h>
1319 +#include <linux/bcma/bcma_driver_pcie2.h>
1320 #include <linux/bcma/bcma_driver_mips.h>
1321 #include <linux/bcma/bcma_driver_gmac_cmn.h>
1322 #include <linux/ssb/ssb.h> /* SPROM sharing */
1323 @@ -72,7 +73,19 @@ struct bcma_host_ops {
1324 /* Core-ID values. */
1325 #define BCMA_CORE_OOB_ROUTER 0x367 /* Out of band */
1326 #define BCMA_CORE_4706_CHIPCOMMON 0x500
1327 +#define BCMA_CORE_PCIEG2 0x501
1328 +#define BCMA_CORE_DMA 0x502
1329 +#define BCMA_CORE_SDIO3 0x503
1330 +#define BCMA_CORE_USB20 0x504
1331 +#define BCMA_CORE_USB30 0x505
1332 +#define BCMA_CORE_A9JTAG 0x506
1333 +#define BCMA_CORE_DDR23 0x507
1334 +#define BCMA_CORE_ROM 0x508
1335 +#define BCMA_CORE_NAND 0x509
1336 +#define BCMA_CORE_QSPI 0x50A
1337 +#define BCMA_CORE_CHIPCOMMON_B 0x50B
1338 #define BCMA_CORE_4706_SOC_RAM 0x50E
1339 +#define BCMA_CORE_ARMCA9 0x510
1340 #define BCMA_CORE_4706_MAC_GBIT 0x52D
1341 #define BCMA_CORE_AMEMC 0x52E /* DDR1/2 memory controller core */
1342 #define BCMA_CORE_ALTA 0x534 /* I2S core */
1343 @@ -144,6 +157,9 @@ struct bcma_host_ops {
1344
1345 /* Chip IDs of PCIe devices */
1346 #define BCMA_CHIP_ID_BCM4313 0x4313
1347 +#define BCMA_CHIP_ID_BCM43142 43142
1348 +#define BCMA_CHIP_ID_BCM43217 43217
1349 +#define BCMA_CHIP_ID_BCM43222 43222
1350 #define BCMA_CHIP_ID_BCM43224 43224
1351 #define BCMA_PKG_ID_BCM43224_FAB_CSM 0x8
1352 #define BCMA_PKG_ID_BCM43224_FAB_SMIC 0xa
1353 @@ -176,6 +192,11 @@ struct bcma_host_ops {
1354 #define BCMA_PKG_ID_BCM5357 11
1355 #define BCMA_CHIP_ID_BCM53572 53572
1356 #define BCMA_PKG_ID_BCM47188 9
1357 +#define BCMA_CHIP_ID_BCM4707 53010
1358 +#define BCMA_PKG_ID_BCM4707 1
1359 +#define BCMA_PKG_ID_BCM4708 2
1360 +#define BCMA_PKG_ID_BCM4709 0
1361 +#define BCMA_CHIP_ID_BCM53018 53018
1362
1363 /* Board types (on PCI usually equals to the subsystem dev id) */
1364 /* BCM4313 */
1365 @@ -315,6 +336,7 @@ struct bcma_bus {
1366
1367 struct bcma_drv_cc drv_cc;
1368 struct bcma_drv_pci drv_pci[2];
1369 + struct bcma_drv_pcie2 drv_pcie2;
1370 struct bcma_drv_mips drv_mips;
1371 struct bcma_drv_gmac_cmn drv_gmac_cmn;
1372
1373 @@ -400,7 +422,14 @@ static inline void bcma_maskset16(struct
1374 bcma_write16(cc, offset, (bcma_read16(cc, offset) & mask) | set);
1375 }
1376
1377 -extern struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid);
1378 +extern struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
1379 + u8 unit);
1380 +static inline struct bcma_device *bcma_find_core(struct bcma_bus *bus,
1381 + u16 coreid)
1382 +{
1383 + return bcma_find_core_unit(bus, coreid, 0);
1384 +}
1385 +
1386 extern bool bcma_core_is_enabled(struct bcma_device *core);
1387 extern void bcma_core_disable(struct bcma_device *core, u32 flags);
1388 extern int bcma_core_enable(struct bcma_device *core, u32 flags);
1389 --- a/include/linux/bcma/bcma_driver_chipcommon.h
1390 +++ b/include/linux/bcma/bcma_driver_chipcommon.h
1391 @@ -330,6 +330,8 @@
1392 #define BCMA_CC_PMU_CAP 0x0604 /* PMU capabilities */
1393 #define BCMA_CC_PMU_CAP_REVISION 0x000000FF /* Revision mask */
1394 #define BCMA_CC_PMU_STAT 0x0608 /* PMU status */
1395 +#define BCMA_CC_PMU_STAT_EXT_LPO_AVAIL 0x00000100
1396 +#define BCMA_CC_PMU_STAT_WDRESET 0x00000080
1397 #define BCMA_CC_PMU_STAT_INTPEND 0x00000040 /* Interrupt pending */
1398 #define BCMA_CC_PMU_STAT_SBCLKST 0x00000030 /* Backplane clock status? */
1399 #define BCMA_CC_PMU_STAT_HAVEALP 0x00000008 /* ALP available */
1400 @@ -355,6 +357,11 @@
1401 #define BCMA_CC_REGCTL_DATA 0x065C
1402 #define BCMA_CC_PLLCTL_ADDR 0x0660
1403 #define BCMA_CC_PLLCTL_DATA 0x0664
1404 +#define BCMA_CC_PMU_STRAPOPT 0x0668 /* (corerev >= 28) */
1405 +#define BCMA_CC_PMU_XTAL_FREQ 0x066C /* (pmurev >= 10) */
1406 +#define BCMA_CC_PMU_XTAL_FREQ_ILPCTL_MASK 0x00001FFF
1407 +#define BCMA_CC_PMU_XTAL_FREQ_MEASURE_MASK 0x80000000
1408 +#define BCMA_CC_PMU_XTAL_FREQ_MEASURE_SHIFT 31
1409 #define BCMA_CC_SPROM 0x0800 /* SPROM beginning */
1410 /* NAND flash MLC controller registers (corerev >= 38) */
1411 #define BCMA_CC_NAND_REVISION 0x0C00
1412 @@ -435,6 +442,23 @@
1413 #define BCMA_CC_PMU6_4706_PROC_NDIV_MODE_MASK 0x00000007
1414 #define BCMA_CC_PMU6_4706_PROC_NDIV_MODE_SHIFT 0
1415
1416 +/* PMU rev 15 */
1417 +#define BCMA_CC_PMU15_PLL_PLLCTL0 0
1418 +#define BCMA_CC_PMU15_PLL_PC0_CLKSEL_MASK 0x00000003
1419 +#define BCMA_CC_PMU15_PLL_PC0_CLKSEL_SHIFT 0
1420 +#define BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK 0x003FFFFC
1421 +#define BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT 2
1422 +#define BCMA_CC_PMU15_PLL_PC0_PRESCALE_MASK 0x00C00000
1423 +#define BCMA_CC_PMU15_PLL_PC0_PRESCALE_SHIFT 22
1424 +#define BCMA_CC_PMU15_PLL_PC0_KPCTRL_MASK 0x07000000
1425 +#define BCMA_CC_PMU15_PLL_PC0_KPCTRL_SHIFT 24
1426 +#define BCMA_CC_PMU15_PLL_PC0_FCNTCTRL_MASK 0x38000000
1427 +#define BCMA_CC_PMU15_PLL_PC0_FCNTCTRL_SHIFT 27
1428 +#define BCMA_CC_PMU15_PLL_PC0_FDCMODE_MASK 0x40000000
1429 +#define BCMA_CC_PMU15_PLL_PC0_FDCMODE_SHIFT 30
1430 +#define BCMA_CC_PMU15_PLL_PC0_CTRLBIAS_MASK 0x80000000
1431 +#define BCMA_CC_PMU15_PLL_PC0_CTRLBIAS_SHIFT 31
1432 +
1433 /* ALP clock on pre-PMU chips */
1434 #define BCMA_CC_PMU_ALP_CLOCK 20000000
1435 /* HT clock for systems with PMU-enabled chipcommon */
1436 @@ -507,6 +531,37 @@
1437 #define BCMA_CHIPCTL_5357_I2S_PINS_ENABLE BIT(18)
1438 #define BCMA_CHIPCTL_5357_I2CSPI_PINS_ENABLE BIT(19)
1439
1440 +#define BCMA_RES_4314_LPLDO_PU BIT(0)
1441 +#define BCMA_RES_4314_PMU_SLEEP_DIS BIT(1)
1442 +#define BCMA_RES_4314_PMU_BG_PU BIT(2)
1443 +#define BCMA_RES_4314_CBUCK_LPOM_PU BIT(3)
1444 +#define BCMA_RES_4314_CBUCK_PFM_PU BIT(4)
1445 +#define BCMA_RES_4314_CLDO_PU BIT(5)
1446 +#define BCMA_RES_4314_LPLDO2_LVM BIT(6)
1447 +#define BCMA_RES_4314_WL_PMU_PU BIT(7)
1448 +#define BCMA_RES_4314_LNLDO_PU BIT(8)
1449 +#define BCMA_RES_4314_LDO3P3_PU BIT(9)
1450 +#define BCMA_RES_4314_OTP_PU BIT(10)
1451 +#define BCMA_RES_4314_XTAL_PU BIT(11)
1452 +#define BCMA_RES_4314_WL_PWRSW_PU BIT(12)
1453 +#define BCMA_RES_4314_LQ_AVAIL BIT(13)
1454 +#define BCMA_RES_4314_LOGIC_RET BIT(14)
1455 +#define BCMA_RES_4314_MEM_SLEEP BIT(15)
1456 +#define BCMA_RES_4314_MACPHY_RET BIT(16)
1457 +#define BCMA_RES_4314_WL_CORE_READY BIT(17)
1458 +#define BCMA_RES_4314_ILP_REQ BIT(18)
1459 +#define BCMA_RES_4314_ALP_AVAIL BIT(19)
1460 +#define BCMA_RES_4314_MISC_PWRSW_PU BIT(20)
1461 +#define BCMA_RES_4314_SYNTH_PWRSW_PU BIT(21)
1462 +#define BCMA_RES_4314_RX_PWRSW_PU BIT(22)
1463 +#define BCMA_RES_4314_RADIO_PU BIT(23)
1464 +#define BCMA_RES_4314_VCO_LDO_PU BIT(24)
1465 +#define BCMA_RES_4314_AFE_LDO_PU BIT(25)
1466 +#define BCMA_RES_4314_RX_LDO_PU BIT(26)
1467 +#define BCMA_RES_4314_TX_LDO_PU BIT(27)
1468 +#define BCMA_RES_4314_HT_AVAIL BIT(28)
1469 +#define BCMA_RES_4314_MACPHY_CLK_AVAIL BIT(29)
1470 +
1471 /* Data for the PMU, if available.
1472 * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
1473 */
1474 @@ -585,6 +640,7 @@ struct bcma_drv_cc {
1475 spinlock_t gpio_lock;
1476 #ifdef CONFIG_BCMA_DRIVER_GPIO
1477 struct gpio_chip gpio;
1478 + struct irq_domain *irq_domain;
1479 #endif
1480 };
1481
1482 --- a/include/linux/bcma/bcma_driver_pci.h
1483 +++ b/include/linux/bcma/bcma_driver_pci.h
1484 @@ -181,10 +181,31 @@ struct pci_dev;
1485
1486 #define BCMA_CORE_PCI_CFG_DEVCTRL 0xd8
1487
1488 +#define BCMA_CORE_PCI_
1489 +
1490 +/* MDIO devices (SERDES modules) */
1491 +#define BCMA_CORE_PCI_MDIO_IEEE0 0x000
1492 +#define BCMA_CORE_PCI_MDIO_IEEE1 0x001
1493 +#define BCMA_CORE_PCI_MDIO_BLK0 0x800
1494 +#define BCMA_CORE_PCI_MDIO_BLK1 0x801
1495 +#define BCMA_CORE_PCI_MDIO_BLK1_MGMT0 0x16
1496 +#define BCMA_CORE_PCI_MDIO_BLK1_MGMT1 0x17
1497 +#define BCMA_CORE_PCI_MDIO_BLK1_MGMT2 0x18
1498 +#define BCMA_CORE_PCI_MDIO_BLK1_MGMT3 0x19
1499 +#define BCMA_CORE_PCI_MDIO_BLK1_MGMT4 0x1A
1500 +#define BCMA_CORE_PCI_MDIO_BLK2 0x802
1501 +#define BCMA_CORE_PCI_MDIO_BLK3 0x803
1502 +#define BCMA_CORE_PCI_MDIO_BLK4 0x804
1503 +#define BCMA_CORE_PCI_MDIO_TXPLL 0x808 /* TXPLL register block idx */
1504 +#define BCMA_CORE_PCI_MDIO_TXCTRL0 0x820
1505 +#define BCMA_CORE_PCI_MDIO_SERDESID 0x831
1506 +#define BCMA_CORE_PCI_MDIO_RXCTRL0 0x840
1507 +
1508 /* PCIE Root Capability Register bits (Host mode only) */
1509 #define BCMA_CORE_PCI_RC_CRS_VISIBILITY 0x0001
1510
1511 struct bcma_drv_pci;
1512 +struct bcma_bus;
1513
1514 #ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
1515 struct bcma_drv_pci_host {
1516 @@ -219,7 +240,9 @@ struct bcma_drv_pci {
1517 extern void bcma_core_pci_init(struct bcma_drv_pci *pc);
1518 extern int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc,
1519 struct bcma_device *core, bool enable);
1520 -extern void bcma_core_pci_extend_L1timer(struct bcma_drv_pci *pc, bool extend);
1521 +extern void bcma_core_pci_up(struct bcma_bus *bus);
1522 +extern void bcma_core_pci_down(struct bcma_bus *bus);
1523 +extern void bcma_core_pci_power_save(struct bcma_bus *bus, bool up);
1524
1525 extern int bcma_core_pci_pcibios_map_irq(const struct pci_dev *dev);
1526 extern int bcma_core_pci_plat_dev_init(struct pci_dev *dev);
1527 --- /dev/null
1528 +++ b/include/linux/bcma/bcma_driver_pcie2.h
1529 @@ -0,0 +1,158 @@
1530 +#ifndef LINUX_BCMA_DRIVER_PCIE2_H_
1531 +#define LINUX_BCMA_DRIVER_PCIE2_H_
1532 +
1533 +#define BCMA_CORE_PCIE2_CLK_CONTROL 0x0000
1534 +#define PCIE2_CLKC_RST_OE 0x0001 /* When set, drives PCI_RESET out to pin */
1535 +#define PCIE2_CLKC_RST 0x0002 /* Value driven out to pin */
1536 +#define PCIE2_CLKC_SPERST 0x0004 /* SurvivePeRst */
1537 +#define PCIE2_CLKC_DISABLE_L1CLK_GATING 0x0010
1538 +#define PCIE2_CLKC_DLYPERST 0x0100 /* Delay PeRst to CoE Core */
1539 +#define PCIE2_CLKC_DISSPROMLD 0x0200 /* DisableSpromLoadOnPerst */
1540 +#define PCIE2_CLKC_WAKE_MODE_L2 0x1000 /* Wake on L2 */
1541 +#define BCMA_CORE_PCIE2_RC_PM_CONTROL 0x0004
1542 +#define BCMA_CORE_PCIE2_RC_PM_STATUS 0x0008
1543 +#define BCMA_CORE_PCIE2_EP_PM_CONTROL 0x000C
1544 +#define BCMA_CORE_PCIE2_EP_PM_STATUS 0x0010
1545 +#define BCMA_CORE_PCIE2_EP_LTR_CONTROL 0x0014
1546 +#define BCMA_CORE_PCIE2_EP_LTR_STATUS 0x0018
1547 +#define BCMA_CORE_PCIE2_EP_OBFF_STATUS 0x001C
1548 +#define BCMA_CORE_PCIE2_PCIE_ERR_STATUS 0x0020
1549 +#define BCMA_CORE_PCIE2_RC_AXI_CONFIG 0x0100
1550 +#define BCMA_CORE_PCIE2_EP_AXI_CONFIG 0x0104
1551 +#define BCMA_CORE_PCIE2_RXDEBUG_STATUS0 0x0108
1552 +#define BCMA_CORE_PCIE2_RXDEBUG_CONTROL0 0x010C
1553 +#define BCMA_CORE_PCIE2_CONFIGINDADDR 0x0120
1554 +#define BCMA_CORE_PCIE2_CONFIGINDDATA 0x0124
1555 +#define BCMA_CORE_PCIE2_MDIOCONTROL 0x0128
1556 +#define BCMA_CORE_PCIE2_MDIOWRDATA 0x012C
1557 +#define BCMA_CORE_PCIE2_MDIORDDATA 0x0130
1558 +#define BCMA_CORE_PCIE2_DATAINTF 0x0180
1559 +#define BCMA_CORE_PCIE2_D2H_INTRLAZY_0 0x0188
1560 +#define BCMA_CORE_PCIE2_H2D_INTRLAZY_0 0x018c
1561 +#define BCMA_CORE_PCIE2_H2D_INTSTAT_0 0x0190
1562 +#define BCMA_CORE_PCIE2_H2D_INTMASK_0 0x0194
1563 +#define BCMA_CORE_PCIE2_D2H_INTSTAT_0 0x0198
1564 +#define BCMA_CORE_PCIE2_D2H_INTMASK_0 0x019c
1565 +#define BCMA_CORE_PCIE2_LTR_STATE 0x01A0 /* Latency Tolerance Reporting */
1566 +#define PCIE2_LTR_ACTIVE 2
1567 +#define PCIE2_LTR_ACTIVE_IDLE 1
1568 +#define PCIE2_LTR_SLEEP 0
1569 +#define PCIE2_LTR_FINAL_MASK 0x300
1570 +#define PCIE2_LTR_FINAL_SHIFT 8
1571 +#define BCMA_CORE_PCIE2_PWR_INT_STATUS 0x01A4
1572 +#define BCMA_CORE_PCIE2_PWR_INT_MASK 0x01A8
1573 +#define BCMA_CORE_PCIE2_CFG_ADDR 0x01F8
1574 +#define BCMA_CORE_PCIE2_CFG_DATA 0x01FC
1575 +#define BCMA_CORE_PCIE2_SYS_EQ_PAGE 0x0200
1576 +#define BCMA_CORE_PCIE2_SYS_MSI_PAGE 0x0204
1577 +#define BCMA_CORE_PCIE2_SYS_MSI_INTREN 0x0208
1578 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL0 0x0210
1579 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL1 0x0214
1580 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL2 0x0218
1581 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL3 0x021C
1582 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL4 0x0220
1583 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL5 0x0224
1584 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD0 0x0250
1585 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL0 0x0254
1586 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD1 0x0258
1587 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL1 0x025C
1588 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD2 0x0260
1589 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL2 0x0264
1590 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD3 0x0268
1591 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL3 0x026C
1592 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD4 0x0270
1593 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL4 0x0274
1594 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD5 0x0278
1595 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL5 0x027C
1596 +#define BCMA_CORE_PCIE2_SYS_RC_INTX_EN 0x0330
1597 +#define BCMA_CORE_PCIE2_SYS_RC_INTX_CSR 0x0334
1598 +#define BCMA_CORE_PCIE2_SYS_MSI_REQ 0x0340
1599 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR_EN 0x0344
1600 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR_CSR 0x0348
1601 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR0 0x0350
1602 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR1 0x0354
1603 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR2 0x0358
1604 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR3 0x035C
1605 +#define BCMA_CORE_PCIE2_SYS_EP_INT_EN0 0x0360
1606 +#define BCMA_CORE_PCIE2_SYS_EP_INT_EN1 0x0364
1607 +#define BCMA_CORE_PCIE2_SYS_EP_INT_CSR0 0x0370
1608 +#define BCMA_CORE_PCIE2_SYS_EP_INT_CSR1 0x0374
1609 +#define BCMA_CORE_PCIE2_SPROM(wordoffset) (0x0800 + ((wordoffset) * 2))
1610 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_0 0x0C00
1611 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_1 0x0C04
1612 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_2 0x0C08
1613 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_3 0x0C0C
1614 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_4 0x0C10
1615 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_5 0x0C14
1616 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_6 0x0C18
1617 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_7 0x0C1C
1618 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_0 0x0C20
1619 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_1 0x0C24
1620 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_2 0x0C28
1621 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_3 0x0C2C
1622 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_4 0x0C30
1623 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_5 0x0C34
1624 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_6 0x0C38
1625 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_7 0x0C3C
1626 +#define BCMA_CORE_PCIE2_FUNC0_IMAP1 0x0C80
1627 +#define BCMA_CORE_PCIE2_FUNC1_IMAP1 0x0C88
1628 +#define BCMA_CORE_PCIE2_FUNC0_IMAP2 0x0CC0
1629 +#define BCMA_CORE_PCIE2_FUNC1_IMAP2 0x0CC8
1630 +#define BCMA_CORE_PCIE2_IARR0_LOWER 0x0D00
1631 +#define BCMA_CORE_PCIE2_IARR0_UPPER 0x0D04
1632 +#define BCMA_CORE_PCIE2_IARR1_LOWER 0x0D08
1633 +#define BCMA_CORE_PCIE2_IARR1_UPPER 0x0D0C
1634 +#define BCMA_CORE_PCIE2_IARR2_LOWER 0x0D10
1635 +#define BCMA_CORE_PCIE2_IARR2_UPPER 0x0D14
1636 +#define BCMA_CORE_PCIE2_OARR0 0x0D20
1637 +#define BCMA_CORE_PCIE2_OARR1 0x0D28
1638 +#define BCMA_CORE_PCIE2_OARR2 0x0D30
1639 +#define BCMA_CORE_PCIE2_OMAP0_LOWER 0x0D40
1640 +#define BCMA_CORE_PCIE2_OMAP0_UPPER 0x0D44
1641 +#define BCMA_CORE_PCIE2_OMAP1_LOWER 0x0D48
1642 +#define BCMA_CORE_PCIE2_OMAP1_UPPER 0x0D4C
1643 +#define BCMA_CORE_PCIE2_OMAP2_LOWER 0x0D50
1644 +#define BCMA_CORE_PCIE2_OMAP2_UPPER 0x0D54
1645 +#define BCMA_CORE_PCIE2_FUNC1_IARR1_SIZE 0x0D58
1646 +#define BCMA_CORE_PCIE2_FUNC1_IARR2_SIZE 0x0D5C
1647 +#define BCMA_CORE_PCIE2_MEM_CONTROL 0x0F00
1648 +#define BCMA_CORE_PCIE2_MEM_ECC_ERRLOG0 0x0F04
1649 +#define BCMA_CORE_PCIE2_MEM_ECC_ERRLOG1 0x0F08
1650 +#define BCMA_CORE_PCIE2_LINK_STATUS 0x0F0C
1651 +#define BCMA_CORE_PCIE2_STRAP_STATUS 0x0F10
1652 +#define BCMA_CORE_PCIE2_RESET_STATUS 0x0F14
1653 +#define BCMA_CORE_PCIE2_RESETEN_IN_LINKDOWN 0x0F18
1654 +#define BCMA_CORE_PCIE2_MISC_INTR_EN 0x0F1C
1655 +#define BCMA_CORE_PCIE2_TX_DEBUG_CFG 0x0F20
1656 +#define BCMA_CORE_PCIE2_MISC_CONFIG 0x0F24
1657 +#define BCMA_CORE_PCIE2_MISC_STATUS 0x0F28
1658 +#define BCMA_CORE_PCIE2_INTR_EN 0x0F30
1659 +#define BCMA_CORE_PCIE2_INTR_CLEAR 0x0F34
1660 +#define BCMA_CORE_PCIE2_INTR_STATUS 0x0F38
1661 +
1662 +/* PCIE gen2 config regs */
1663 +#define PCIE2_INTSTATUS 0x090
1664 +#define PCIE2_INTMASK 0x094
1665 +#define PCIE2_SBMBX 0x098
1666 +
1667 +#define PCIE2_PMCR_REFUP 0x1814 /* Trefup time */
1668 +
1669 +#define PCIE2_CAP_DEVSTSCTRL2_OFFSET 0xD4
1670 +#define PCIE2_CAP_DEVSTSCTRL2_LTRENAB 0x400
1671 +#define PCIE2_PVT_REG_PM_CLK_PERIOD 0x184c
1672 +
1673 +struct bcma_drv_pcie2 {
1674 + struct bcma_device *core;
1675 +};
1676 +
1677 +#define pcie2_read16(pcie2, offset) bcma_read16((pcie2)->core, offset)
1678 +#define pcie2_read32(pcie2, offset) bcma_read32((pcie2)->core, offset)
1679 +#define pcie2_write16(pcie2, offset, val) bcma_write16((pcie2)->core, offset, val)
1680 +#define pcie2_write32(pcie2, offset, val) bcma_write32((pcie2)->core, offset, val)
1681 +
1682 +#define pcie2_set32(pcie2, offset, set) bcma_set32((pcie2)->core, offset, set)
1683 +#define pcie2_mask32(pcie2, offset, mask) bcma_mask32((pcie2)->core, offset, mask)
1684 +
1685 +void bcma_core_pcie2_init(struct bcma_drv_pcie2 *pcie2);
1686 +
1687 +#endif /* LINUX_BCMA_DRIVER_PCIE2_H_ */
1688 --- a/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
1689 +++ b/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
1690 @@ -679,27 +679,6 @@ bool ai_clkctl_cc(struct si_pub *sih, en
1691 return mode == BCMA_CLKMODE_FAST;
1692 }
1693
1694 -void ai_pci_up(struct si_pub *sih)
1695 -{
1696 - struct si_info *sii;
1697 -
1698 - sii = container_of(sih, struct si_info, pub);
1699 -
1700 - if (sii->icbus->hosttype == BCMA_HOSTTYPE_PCI)
1701 - bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci[0], true);
1702 -}
1703 -
1704 -/* Unconfigure and/or apply various WARs when going down */
1705 -void ai_pci_down(struct si_pub *sih)
1706 -{
1707 - struct si_info *sii;
1708 -
1709 - sii = container_of(sih, struct si_info, pub);
1710 -
1711 - if (sii->icbus->hosttype == BCMA_HOSTTYPE_PCI)
1712 - bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci[0], false);
1713 -}
1714 -
1715 /* Enable BT-COEX & Ex-PA for 4313 */
1716 void ai_epa_4313war(struct si_pub *sih)
1717 {
1718 --- a/drivers/net/wireless/brcm80211/brcmsmac/aiutils.h
1719 +++ b/drivers/net/wireless/brcm80211/brcmsmac/aiutils.h
1720 @@ -183,9 +183,6 @@ extern u16 ai_clkctl_fast_pwrup_delay(st
1721 extern bool ai_clkctl_cc(struct si_pub *sih, enum bcma_clkmode mode);
1722 extern bool ai_deviceremoved(struct si_pub *sih);
1723
1724 -extern void ai_pci_down(struct si_pub *sih);
1725 -extern void ai_pci_up(struct si_pub *sih);
1726 -
1727 /* Enable Ex-PA for 4313 */
1728 extern void ai_epa_4313war(struct si_pub *sih);
1729
1730 --- a/drivers/net/wireless/brcm80211/brcmsmac/main.c
1731 +++ b/drivers/net/wireless/brcm80211/brcmsmac/main.c
1732 @@ -4667,7 +4667,7 @@ static int brcms_b_attach(struct brcms_c
1733 brcms_c_coredisable(wlc_hw);
1734
1735 /* Match driver "down" state */
1736 - ai_pci_down(wlc_hw->sih);
1737 + bcma_core_pci_down(wlc_hw->d11core->bus);
1738
1739 /* turn off pll and xtal to match driver "down" state */
1740 brcms_b_xtal(wlc_hw, OFF);
1741 @@ -5010,12 +5010,12 @@ static int brcms_b_up_prep(struct brcms_
1742 */
1743 if (brcms_b_radio_read_hwdisabled(wlc_hw)) {
1744 /* put SB PCI in down state again */
1745 - ai_pci_down(wlc_hw->sih);
1746 + bcma_core_pci_down(wlc_hw->d11core->bus);
1747 brcms_b_xtal(wlc_hw, OFF);
1748 return -ENOMEDIUM;
1749 }
1750
1751 - ai_pci_up(wlc_hw->sih);
1752 + bcma_core_pci_up(wlc_hw->d11core->bus);
1753
1754 /* reset the d11 core */
1755 brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
1756 @@ -5212,7 +5212,7 @@ static int brcms_b_down_finish(struct br
1757
1758 /* turn off primary xtal and pll */
1759 if (!wlc_hw->noreset) {
1760 - ai_pci_down(wlc_hw->sih);
1761 + bcma_core_pci_down(wlc_hw->d11core->bus);
1762 brcms_b_xtal(wlc_hw, OFF);
1763 }
1764 }
OpenWrt Source Repository