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kernel: refresh generic 3.10 patches
[openwrt/openwrt.git] / target / linux / generic / patches-3.10 / 025-bcma_backport.patch
1 --- a/drivers/bcma/Kconfig
2 +++ b/drivers/bcma/Kconfig
3 @@ -26,6 +26,7 @@ config BCMA_HOST_PCI_POSSIBLE
4 config BCMA_HOST_PCI
5 bool "Support for BCMA on PCI-host bus"
6 depends on BCMA_HOST_PCI_POSSIBLE
7 + default y
8
9 config BCMA_DRIVER_PCI_HOSTMODE
10 bool "Driver for PCI core working in hostmode"
11 @@ -34,8 +35,14 @@ config BCMA_DRIVER_PCI_HOSTMODE
12 PCI core hostmode operation (external PCI bus).
13
14 config BCMA_HOST_SOC
15 - bool
16 - depends on BCMA_DRIVER_MIPS
17 + bool "Support for BCMA in a SoC"
18 + depends on BCMA
19 + help
20 + Host interface for a Broadcom AIX bus directly mapped into
21 + the memory. This only works with the Broadcom SoCs from the
22 + BCM47XX line.
23 +
24 + If unsure, say N
25
26 config BCMA_DRIVER_MIPS
27 bool "BCMA Broadcom MIPS core driver"
28 @@ -68,6 +75,7 @@ config BCMA_DRIVER_GMAC_CMN
29 config BCMA_DRIVER_GPIO
30 bool "BCMA GPIO driver"
31 depends on BCMA && GPIOLIB
32 + select IRQ_DOMAIN if BCMA_HOST_SOC
33 help
34 Driver to provide access to the GPIO pins of the bcma bus.
35
36 --- a/drivers/bcma/Makefile
37 +++ b/drivers/bcma/Makefile
38 @@ -1,8 +1,10 @@
39 bcma-y += main.o scan.o core.o sprom.o
40 bcma-y += driver_chipcommon.o driver_chipcommon_pmu.o
41 +bcma-y += driver_chipcommon_b.o
42 bcma-$(CONFIG_BCMA_SFLASH) += driver_chipcommon_sflash.o
43 bcma-$(CONFIG_BCMA_NFLASH) += driver_chipcommon_nflash.o
44 bcma-y += driver_pci.o
45 +bcma-y += driver_pcie2.o
46 bcma-$(CONFIG_BCMA_DRIVER_PCI_HOSTMODE) += driver_pci_host.o
47 bcma-$(CONFIG_BCMA_DRIVER_MIPS) += driver_mips.o
48 bcma-$(CONFIG_BCMA_DRIVER_GMAC_CMN) += driver_gmac_cmn.o
49 --- a/drivers/bcma/bcma_private.h
50 +++ b/drivers/bcma/bcma_private.h
51 @@ -22,6 +22,8 @@
52 struct bcma_bus;
53
54 /* main.c */
55 +bool bcma_wait_value(struct bcma_device *core, u16 reg, u32 mask, u32 value,
56 + int timeout);
57 int bcma_bus_register(struct bcma_bus *bus);
58 void bcma_bus_unregister(struct bcma_bus *bus);
59 int __init bcma_bus_early_register(struct bcma_bus *bus,
60 @@ -31,8 +33,6 @@ int __init bcma_bus_early_register(struc
61 int bcma_bus_suspend(struct bcma_bus *bus);
62 int bcma_bus_resume(struct bcma_bus *bus);
63 #endif
64 -struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
65 - u8 unit);
66
67 /* scan.c */
68 int bcma_bus_scan(struct bcma_bus *bus);
69 @@ -50,6 +50,10 @@ void bcma_chipco_serial_init(struct bcma
70 extern struct platform_device bcma_pflash_dev;
71 #endif /* CONFIG_BCMA_DRIVER_MIPS */
72
73 +/* driver_chipcommon_b.c */
74 +int bcma_core_chipcommon_b_init(struct bcma_drv_cc_b *ccb);
75 +void bcma_core_chipcommon_b_free(struct bcma_drv_cc_b *ccb);
76 +
77 /* driver_chipcommon_pmu.c */
78 u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc);
79 u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc);
80 @@ -84,6 +88,20 @@ extern int __init bcma_host_pci_init(voi
81 extern void __exit bcma_host_pci_exit(void);
82 #endif /* CONFIG_BCMA_HOST_PCI */
83
84 +/* host_soc.c */
85 +#if defined(CONFIG_BCMA_HOST_SOC) && defined(CONFIG_OF)
86 +extern int __init bcma_host_soc_register_driver(void);
87 +extern void __exit bcma_host_soc_unregister_driver(void);
88 +#else
89 +static inline int __init bcma_host_soc_register_driver(void)
90 +{
91 + return 0;
92 +}
93 +static inline void __exit bcma_host_soc_unregister_driver(void)
94 +{
95 +}
96 +#endif /* CONFIG_BCMA_HOST_SOC && CONFIG_OF */
97 +
98 /* driver_pci.c */
99 u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address);
100
101 --- a/drivers/bcma/core.c
102 +++ b/drivers/bcma/core.c
103 @@ -9,6 +9,25 @@
104 #include <linux/export.h>
105 #include <linux/bcma/bcma.h>
106
107 +static bool bcma_core_wait_value(struct bcma_device *core, u16 reg, u32 mask,
108 + u32 value, int timeout)
109 +{
110 + unsigned long deadline = jiffies + timeout;
111 + u32 val;
112 +
113 + do {
114 + val = bcma_aread32(core, reg);
115 + if ((val & mask) == value)
116 + return true;
117 + cpu_relax();
118 + udelay(10);
119 + } while (!time_after_eq(jiffies, deadline));
120 +
121 + bcma_warn(core->bus, "Timeout waiting for register 0x%04X!\n", reg);
122 +
123 + return false;
124 +}
125 +
126 bool bcma_core_is_enabled(struct bcma_device *core)
127 {
128 if ((bcma_aread32(core, BCMA_IOCTL) & (BCMA_IOCTL_CLK | BCMA_IOCTL_FGC))
129 @@ -25,13 +44,15 @@ void bcma_core_disable(struct bcma_devic
130 if (bcma_aread32(core, BCMA_RESET_CTL) & BCMA_RESET_CTL_RESET)
131 return;
132
133 - bcma_awrite32(core, BCMA_IOCTL, flags);
134 - bcma_aread32(core, BCMA_IOCTL);
135 - udelay(10);
136 + bcma_core_wait_value(core, BCMA_RESET_ST, ~0, 0, 300);
137
138 bcma_awrite32(core, BCMA_RESET_CTL, BCMA_RESET_CTL_RESET);
139 bcma_aread32(core, BCMA_RESET_CTL);
140 udelay(1);
141 +
142 + bcma_awrite32(core, BCMA_IOCTL, flags);
143 + bcma_aread32(core, BCMA_IOCTL);
144 + udelay(10);
145 }
146 EXPORT_SYMBOL_GPL(bcma_core_disable);
147
148 @@ -43,6 +64,7 @@ int bcma_core_enable(struct bcma_device
149 bcma_aread32(core, BCMA_IOCTL);
150
151 bcma_awrite32(core, BCMA_RESET_CTL, 0);
152 + bcma_aread32(core, BCMA_RESET_CTL);
153 udelay(1);
154
155 bcma_awrite32(core, BCMA_IOCTL, (BCMA_IOCTL_CLK | flags));
156 --- a/drivers/bcma/driver_chipcommon.c
157 +++ b/drivers/bcma/driver_chipcommon.c
158 @@ -140,8 +140,15 @@ void bcma_core_chipcommon_init(struct bc
159 bcma_core_chipcommon_early_init(cc);
160
161 if (cc->core->id.rev >= 20) {
162 - bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, 0);
163 - bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, 0);
164 + u32 pullup = 0, pulldown = 0;
165 +
166 + if (cc->core->bus->chipinfo.id == BCMA_CHIP_ID_BCM43142) {
167 + pullup = 0x402e0;
168 + pulldown = 0x20500;
169 + }
170 +
171 + bcma_cc_write32(cc, BCMA_CC_GPIOPULLUP, pullup);
172 + bcma_cc_write32(cc, BCMA_CC_GPIOPULLDOWN, pulldown);
173 }
174
175 if (cc->capabilities & BCMA_CC_CAP_PMU)
176 --- a/drivers/bcma/driver_chipcommon_pmu.c
177 +++ b/drivers/bcma/driver_chipcommon_pmu.c
178 @@ -56,6 +56,109 @@ void bcma_chipco_regctl_maskset(struct b
179 }
180 EXPORT_SYMBOL_GPL(bcma_chipco_regctl_maskset);
181
182 +static u32 bcma_pmu_xtalfreq(struct bcma_drv_cc *cc)
183 +{
184 + u32 ilp_ctl, alp_hz;
185 +
186 + if (!(bcma_cc_read32(cc, BCMA_CC_PMU_STAT) &
187 + BCMA_CC_PMU_STAT_EXT_LPO_AVAIL))
188 + return 0;
189 +
190 + bcma_cc_write32(cc, BCMA_CC_PMU_XTAL_FREQ,
191 + BIT(BCMA_CC_PMU_XTAL_FREQ_MEASURE_SHIFT));
192 + usleep_range(1000, 2000);
193 +
194 + ilp_ctl = bcma_cc_read32(cc, BCMA_CC_PMU_XTAL_FREQ);
195 + ilp_ctl &= BCMA_CC_PMU_XTAL_FREQ_ILPCTL_MASK;
196 +
197 + bcma_cc_write32(cc, BCMA_CC_PMU_XTAL_FREQ, 0);
198 +
199 + alp_hz = ilp_ctl * 32768 / 4;
200 + return (alp_hz + 50000) / 100000 * 100;
201 +}
202 +
203 +static void bcma_pmu2_pll_init0(struct bcma_drv_cc *cc, u32 xtalfreq)
204 +{
205 + struct bcma_bus *bus = cc->core->bus;
206 + u32 freq_tgt_target = 0, freq_tgt_current;
207 + u32 pll0, mask;
208 +
209 + switch (bus->chipinfo.id) {
210 + case BCMA_CHIP_ID_BCM43142:
211 + /* pmu2_xtaltab0_adfll_485 */
212 + switch (xtalfreq) {
213 + case 12000:
214 + freq_tgt_target = 0x50D52;
215 + break;
216 + case 20000:
217 + freq_tgt_target = 0x307FE;
218 + break;
219 + case 26000:
220 + freq_tgt_target = 0x254EA;
221 + break;
222 + case 37400:
223 + freq_tgt_target = 0x19EF8;
224 + break;
225 + case 52000:
226 + freq_tgt_target = 0x12A75;
227 + break;
228 + }
229 + break;
230 + }
231 +
232 + if (!freq_tgt_target) {
233 + bcma_err(bus, "Unknown TGT frequency for xtalfreq %d\n",
234 + xtalfreq);
235 + return;
236 + }
237 +
238 + pll0 = bcma_chipco_pll_read(cc, BCMA_CC_PMU15_PLL_PLLCTL0);
239 + freq_tgt_current = (pll0 & BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK) >>
240 + BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT;
241 +
242 + if (freq_tgt_current == freq_tgt_target) {
243 + bcma_debug(bus, "Target TGT frequency already set\n");
244 + return;
245 + }
246 +
247 + /* Turn off PLL */
248 + switch (bus->chipinfo.id) {
249 + case BCMA_CHIP_ID_BCM43142:
250 + mask = (u32)~(BCMA_RES_4314_HT_AVAIL |
251 + BCMA_RES_4314_MACPHY_CLK_AVAIL);
252 +
253 + bcma_cc_mask32(cc, BCMA_CC_PMU_MINRES_MSK, mask);
254 + bcma_cc_mask32(cc, BCMA_CC_PMU_MAXRES_MSK, mask);
255 + bcma_wait_value(cc->core, BCMA_CLKCTLST,
256 + BCMA_CLKCTLST_HAVEHT, 0, 20000);
257 + break;
258 + }
259 +
260 + pll0 &= ~BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK;
261 + pll0 |= freq_tgt_target << BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT;
262 + bcma_chipco_pll_write(cc, BCMA_CC_PMU15_PLL_PLLCTL0, pll0);
263 +
264 + /* Flush */
265 + if (cc->pmu.rev >= 2)
266 + bcma_cc_set32(cc, BCMA_CC_PMU_CTL, BCMA_CC_PMU_CTL_PLL_UPD);
267 +
268 + /* TODO: Do we need to update OTP? */
269 +}
270 +
271 +static void bcma_pmu_pll_init(struct bcma_drv_cc *cc)
272 +{
273 + struct bcma_bus *bus = cc->core->bus;
274 + u32 xtalfreq = bcma_pmu_xtalfreq(cc);
275 +
276 + switch (bus->chipinfo.id) {
277 + case BCMA_CHIP_ID_BCM43142:
278 + if (xtalfreq == 0)
279 + xtalfreq = 20000;
280 + bcma_pmu2_pll_init0(cc, xtalfreq);
281 + break;
282 + }
283 +}
284 +
285 static void bcma_pmu_resources_init(struct bcma_drv_cc *cc)
286 {
287 struct bcma_bus *bus = cc->core->bus;
288 @@ -66,6 +169,25 @@ static void bcma_pmu_resources_init(stru
289 min_msk = 0x200D;
290 max_msk = 0xFFFF;
291 break;
292 + case BCMA_CHIP_ID_BCM43142:
293 + min_msk = BCMA_RES_4314_LPLDO_PU |
294 + BCMA_RES_4314_PMU_SLEEP_DIS |
295 + BCMA_RES_4314_PMU_BG_PU |
296 + BCMA_RES_4314_CBUCK_LPOM_PU |
297 + BCMA_RES_4314_CBUCK_PFM_PU |
298 + BCMA_RES_4314_CLDO_PU |
299 + BCMA_RES_4314_LPLDO2_LVM |
300 + BCMA_RES_4314_WL_PMU_PU |
301 + BCMA_RES_4314_LDO3P3_PU |
302 + BCMA_RES_4314_OTP_PU |
303 + BCMA_RES_4314_WL_PWRSW_PU |
304 + BCMA_RES_4314_LQ_AVAIL |
305 + BCMA_RES_4314_LOGIC_RET |
306 + BCMA_RES_4314_MEM_SLEEP |
307 + BCMA_RES_4314_MACPHY_RET |
308 + BCMA_RES_4314_WL_CORE_READY;
309 + max_msk = 0x3FFFFFFF;
310 + break;
311 default:
312 bcma_debug(bus, "PMU resource config unknown or not needed for device 0x%04X\n",
313 bus->chipinfo.id);
314 @@ -165,6 +287,7 @@ void bcma_pmu_init(struct bcma_drv_cc *c
315 bcma_cc_set32(cc, BCMA_CC_PMU_CTL,
316 BCMA_CC_PMU_CTL_NOILPONW);
317
318 + bcma_pmu_pll_init(cc);
319 bcma_pmu_resources_init(cc);
320 bcma_pmu_workarounds(cc);
321 }
322 @@ -480,6 +603,8 @@ void bcma_pmu_spuravoid_pllupdate(struct
323 tmp = BCMA_CC_PMU_CTL_PLL_UPD | BCMA_CC_PMU_CTL_NOILPONW;
324 break;
325
326 + case BCMA_CHIP_ID_BCM43131:
327 + case BCMA_CHIP_ID_BCM43217:
328 case BCMA_CHIP_ID_BCM43227:
329 case BCMA_CHIP_ID_BCM43228:
330 case BCMA_CHIP_ID_BCM43428:
331 --- a/drivers/bcma/driver_chipcommon_sflash.c
332 +++ b/drivers/bcma/driver_chipcommon_sflash.c
333 @@ -30,7 +30,7 @@ struct bcma_sflash_tbl_e {
334 u16 numblocks;
335 };
336
337 -static struct bcma_sflash_tbl_e bcma_sflash_st_tbl[] = {
338 +static const struct bcma_sflash_tbl_e bcma_sflash_st_tbl[] = {
339 { "M25P20", 0x11, 0x10000, 4, },
340 { "M25P40", 0x12, 0x10000, 8, },
341
342 @@ -38,10 +38,10 @@ static struct bcma_sflash_tbl_e bcma_sfl
343 { "M25P32", 0x15, 0x10000, 64, },
344 { "M25P64", 0x16, 0x10000, 128, },
345 { "M25FL128", 0x17, 0x10000, 256, },
346 - { 0 },
347 + { NULL },
348 };
349
350 -static struct bcma_sflash_tbl_e bcma_sflash_sst_tbl[] = {
351 +static const struct bcma_sflash_tbl_e bcma_sflash_sst_tbl[] = {
352 { "SST25WF512", 1, 0x1000, 16, },
353 { "SST25VF512", 0x48, 0x1000, 16, },
354 { "SST25WF010", 2, 0x1000, 32, },
355 @@ -56,10 +56,10 @@ static struct bcma_sflash_tbl_e bcma_sfl
356 { "SST25VF016", 0x41, 0x1000, 512, },
357 { "SST25VF032", 0x4a, 0x1000, 1024, },
358 { "SST25VF064", 0x4b, 0x1000, 2048, },
359 - { 0 },
360 + { NULL },
361 };
362
363 -static struct bcma_sflash_tbl_e bcma_sflash_at_tbl[] = {
364 +static const struct bcma_sflash_tbl_e bcma_sflash_at_tbl[] = {
365 { "AT45DB011", 0xc, 256, 512, },
366 { "AT45DB021", 0x14, 256, 1024, },
367 { "AT45DB041", 0x1c, 256, 2048, },
368 @@ -67,7 +67,7 @@ static struct bcma_sflash_tbl_e bcma_sfl
369 { "AT45DB161", 0x2c, 512, 4096, },
370 { "AT45DB321", 0x34, 512, 8192, },
371 { "AT45DB642", 0x3c, 1024, 8192, },
372 - { 0 },
373 + { NULL },
374 };
375
376 static void bcma_sflash_cmd(struct bcma_drv_cc *cc, u32 opcode)
377 @@ -89,7 +89,7 @@ int bcma_sflash_init(struct bcma_drv_cc
378 {
379 struct bcma_bus *bus = cc->core->bus;
380 struct bcma_sflash *sflash = &cc->sflash;
381 - struct bcma_sflash_tbl_e *e;
382 + const struct bcma_sflash_tbl_e *e;
383 u32 id, id2;
384
385 switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
386 --- a/drivers/bcma/driver_gpio.c
387 +++ b/drivers/bcma/driver_gpio.c
388 @@ -9,6 +9,9 @@
389 */
390
391 #include <linux/gpio.h>
392 +#include <linux/irq.h>
393 +#include <linux/interrupt.h>
394 +#include <linux/irqdomain.h>
395 #include <linux/export.h>
396 #include <linux/bcma/bcma.h>
397
398 @@ -73,19 +76,136 @@ static void bcma_gpio_free(struct gpio_c
399 bcma_chipco_gpio_pullup(cc, 1 << gpio, 0);
400 }
401
402 +#if IS_BUILTIN(CONFIG_BCM47XX)
403 static int bcma_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
404 {
405 struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
406
407 if (cc->core->bus->hosttype == BCMA_HOSTTYPE_SOC)
408 - return bcma_core_irq(cc->core);
409 + return irq_find_mapping(cc->irq_domain, gpio);
410 else
411 return -EINVAL;
412 }
413
414 +static void bcma_gpio_irq_unmask(struct irq_data *d)
415 +{
416 + struct bcma_drv_cc *cc = irq_data_get_irq_chip_data(d);
417 + int gpio = irqd_to_hwirq(d);
418 + u32 val = bcma_chipco_gpio_in(cc, BIT(gpio));
419 +
420 + bcma_chipco_gpio_polarity(cc, BIT(gpio), val);
421 + bcma_chipco_gpio_intmask(cc, BIT(gpio), BIT(gpio));
422 +}
423 +
424 +static void bcma_gpio_irq_mask(struct irq_data *d)
425 +{
426 + struct bcma_drv_cc *cc = irq_data_get_irq_chip_data(d);
427 + int gpio = irqd_to_hwirq(d);
428 +
429 + bcma_chipco_gpio_intmask(cc, BIT(gpio), 0);
430 +}
431 +
432 +static struct irq_chip bcma_gpio_irq_chip = {
433 + .name = "BCMA-GPIO",
434 + .irq_mask = bcma_gpio_irq_mask,
435 + .irq_unmask = bcma_gpio_irq_unmask,
436 +};
437 +
438 +static irqreturn_t bcma_gpio_irq_handler(int irq, void *dev_id)
439 +{
440 + struct bcma_drv_cc *cc = dev_id;
441 + u32 val = bcma_cc_read32(cc, BCMA_CC_GPIOIN);
442 + u32 mask = bcma_cc_read32(cc, BCMA_CC_GPIOIRQ);
443 + u32 pol = bcma_cc_read32(cc, BCMA_CC_GPIOPOL);
444 + unsigned long irqs = (val ^ pol) & mask;
445 + int gpio;
446 +
447 + if (!irqs)
448 + return IRQ_NONE;
449 +
450 + for_each_set_bit(gpio, &irqs, cc->gpio.ngpio)
451 + generic_handle_irq(bcma_gpio_to_irq(&cc->gpio, gpio));
452 + bcma_chipco_gpio_polarity(cc, irqs, val & irqs);
453 +
454 + return IRQ_HANDLED;
455 +}
456 +
457 +static int bcma_gpio_irq_domain_init(struct bcma_drv_cc *cc)
458 +{
459 + struct gpio_chip *chip = &cc->gpio;
460 + int gpio, hwirq, err;
461 +
462 + if (cc->core->bus->hosttype != BCMA_HOSTTYPE_SOC)
463 + return 0;
464 +
465 + cc->irq_domain = irq_domain_add_linear(NULL, chip->ngpio,
466 + &irq_domain_simple_ops, cc);
467 + if (!cc->irq_domain) {
468 + err = -ENODEV;
469 + goto err_irq_domain;
470 + }
471 + for (gpio = 0; gpio < chip->ngpio; gpio++) {
472 + int irq = irq_create_mapping(cc->irq_domain, gpio);
473 +
474 + irq_set_chip_data(irq, cc);
475 + irq_set_chip_and_handler(irq, &bcma_gpio_irq_chip,
476 + handle_simple_irq);
477 + }
478 +
479 + hwirq = bcma_core_irq(cc->core);
480 + err = request_irq(hwirq, bcma_gpio_irq_handler, IRQF_SHARED, "gpio",
481 + cc);
482 + if (err)
483 + goto err_req_irq;
484 +
485 + bcma_chipco_gpio_intmask(cc, ~0, 0);
486 + bcma_cc_set32(cc, BCMA_CC_IRQMASK, BCMA_CC_IRQ_GPIO);
487 +
488 + return 0;
489 +
490 +err_req_irq:
491 + for (gpio = 0; gpio < chip->ngpio; gpio++) {
492 + int irq = irq_find_mapping(cc->irq_domain, gpio);
493 +
494 + irq_dispose_mapping(irq);
495 + }
496 + irq_domain_remove(cc->irq_domain);
497 +err_irq_domain:
498 + return err;
499 +}
500 +
501 +static void bcma_gpio_irq_domain_exit(struct bcma_drv_cc *cc)
502 +{
503 + struct gpio_chip *chip = &cc->gpio;
504 + int gpio;
505 +
506 + if (cc->core->bus->hosttype != BCMA_HOSTTYPE_SOC)
507 + return;
508 +
509 + bcma_cc_mask32(cc, BCMA_CC_IRQMASK, ~BCMA_CC_IRQ_GPIO);
510 + free_irq(bcma_core_irq(cc->core), cc);
511 + for (gpio = 0; gpio < chip->ngpio; gpio++) {
512 + int irq = irq_find_mapping(cc->irq_domain, gpio);
513 +
514 + irq_dispose_mapping(irq);
515 + }
516 + irq_domain_remove(cc->irq_domain);
517 +}
518 +#else
519 +static int bcma_gpio_irq_domain_init(struct bcma_drv_cc *cc)
520 +{
521 + return 0;
522 +}
523 +
524 +static void bcma_gpio_irq_domain_exit(struct bcma_drv_cc *cc)
525 +{
526 +}
527 +#endif
528 +
529 int bcma_gpio_init(struct bcma_drv_cc *cc)
530 {
531 struct gpio_chip *chip = &cc->gpio;
532 + int err;
533
534 chip->label = "bcma_gpio";
535 chip->owner = THIS_MODULE;
536 @@ -95,8 +215,22 @@ int bcma_gpio_init(struct bcma_drv_cc *c
537 chip->set = bcma_gpio_set_value;
538 chip->direction_input = bcma_gpio_direction_input;
539 chip->direction_output = bcma_gpio_direction_output;
540 +#if IS_BUILTIN(CONFIG_BCM47XX)
541 chip->to_irq = bcma_gpio_to_irq;
542 - chip->ngpio = 16;
543 +#endif
544 +#if IS_BUILTIN(CONFIG_OF)
545 + if (cc->core->bus->hosttype == BCMA_HOSTTYPE_SOC)
546 + chip->of_node = cc->core->dev.of_node;
547 +#endif
548 + switch (cc->core->bus->chipinfo.id) {
549 + case BCMA_CHIP_ID_BCM5357:
550 + case BCMA_CHIP_ID_BCM53572:
551 + chip->ngpio = 32;
552 + break;
553 + default:
554 + chip->ngpio = 16;
555 + }
556 +
557 /* There is just one SoC in one device and its GPIO addresses should be
558 * deterministic to address them more easily. The other buses could get
559 * a random base number. */
560 @@ -105,10 +239,21 @@ int bcma_gpio_init(struct bcma_drv_cc *c
561 else
562 chip->base = -1;
563
564 - return gpiochip_add(chip);
565 + err = bcma_gpio_irq_domain_init(cc);
566 + if (err)
567 + return err;
568 +
569 + err = gpiochip_add(chip);
570 + if (err) {
571 + bcma_gpio_irq_domain_exit(cc);
572 + return err;
573 + }
574 +
575 + return 0;
576 }
577
578 int bcma_gpio_unregister(struct bcma_drv_cc *cc)
579 {
580 + bcma_gpio_irq_domain_exit(cc);
581 return gpiochip_remove(&cc->gpio);
582 }
583 --- a/drivers/bcma/driver_pci.c
584 +++ b/drivers/bcma/driver_pci.c
585 @@ -31,7 +31,7 @@ static void bcma_pcie_write(struct bcma_
586 pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_DATA, data);
587 }
588
589 -static void bcma_pcie_mdio_set_phy(struct bcma_drv_pci *pc, u8 phy)
590 +static void bcma_pcie_mdio_set_phy(struct bcma_drv_pci *pc, u16 phy)
591 {
592 u32 v;
593 int i;
594 @@ -55,7 +55,7 @@ static void bcma_pcie_mdio_set_phy(struc
595 }
596 }
597
598 -static u16 bcma_pcie_mdio_read(struct bcma_drv_pci *pc, u8 device, u8 address)
599 +static u16 bcma_pcie_mdio_read(struct bcma_drv_pci *pc, u16 device, u8 address)
600 {
601 int max_retries = 10;
602 u16 ret = 0;
603 @@ -98,7 +98,7 @@ static u16 bcma_pcie_mdio_read(struct bc
604 return ret;
605 }
606
607 -static void bcma_pcie_mdio_write(struct bcma_drv_pci *pc, u8 device,
608 +static void bcma_pcie_mdio_write(struct bcma_drv_pci *pc, u16 device,
609 u8 address, u16 data)
610 {
611 int max_retries = 10;
612 @@ -137,6 +137,13 @@ static void bcma_pcie_mdio_write(struct
613 pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0);
614 }
615
616 +static u16 bcma_pcie_mdio_writeread(struct bcma_drv_pci *pc, u16 device,
617 + u8 address, u16 data)
618 +{
619 + bcma_pcie_mdio_write(pc, device, address, data);
620 + return bcma_pcie_mdio_read(pc, device, address);
621 +}
622 +
623 /**************************************************
624 * Workarounds.
625 **************************************************/
626 @@ -229,6 +236,32 @@ void bcma_core_pci_init(struct bcma_drv_
627 bcma_core_pci_clientmode_init(pc);
628 }
629
630 +void bcma_core_pci_power_save(struct bcma_bus *bus, bool up)
631 +{
632 + struct bcma_drv_pci *pc;
633 + u16 data;
634 +
635 + if (bus->hosttype != BCMA_HOSTTYPE_PCI)
636 + return;
637 +
638 + pc = &bus->drv_pci[0];
639 +
640 + if (pc->core->id.rev >= 15 && pc->core->id.rev <= 20) {
641 + data = up ? 0x74 : 0x7C;
642 + bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
643 + BCMA_CORE_PCI_MDIO_BLK1_MGMT1, 0x7F64);
644 + bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
645 + BCMA_CORE_PCI_MDIO_BLK1_MGMT3, data);
646 + } else if (pc->core->id.rev >= 21 && pc->core->id.rev <= 22) {
647 + data = up ? 0x75 : 0x7D;
648 + bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
649 + BCMA_CORE_PCI_MDIO_BLK1_MGMT1, 0x7E65);
650 + bcma_pcie_mdio_writeread(pc, BCMA_CORE_PCI_MDIO_BLK1,
651 + BCMA_CORE_PCI_MDIO_BLK1_MGMT3, data);
652 + }
653 +}
654 +EXPORT_SYMBOL_GPL(bcma_core_pci_power_save);
655 +
656 int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc, struct bcma_device *core,
657 bool enable)
658 {
659 @@ -262,7 +295,7 @@ out:
660 }
661 EXPORT_SYMBOL_GPL(bcma_core_pci_irq_ctl);
662
663 -void bcma_core_pci_extend_L1timer(struct bcma_drv_pci *pc, bool extend)
664 +static void bcma_core_pci_extend_L1timer(struct bcma_drv_pci *pc, bool extend)
665 {
666 u32 w;
667
668 @@ -274,4 +307,29 @@ void bcma_core_pci_extend_L1timer(struct
669 bcma_pcie_write(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG, w);
670 bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG);
671 }
672 -EXPORT_SYMBOL_GPL(bcma_core_pci_extend_L1timer);
673 +
674 +void bcma_core_pci_up(struct bcma_bus *bus)
675 +{
676 + struct bcma_drv_pci *pc;
677 +
678 + if (bus->hosttype != BCMA_HOSTTYPE_PCI)
679 + return;
680 +
681 + pc = &bus->drv_pci[0];
682 +
683 + bcma_core_pci_extend_L1timer(pc, true);
684 +}
685 +EXPORT_SYMBOL_GPL(bcma_core_pci_up);
686 +
687 +void bcma_core_pci_down(struct bcma_bus *bus)
688 +{
689 + struct bcma_drv_pci *pc;
690 +
691 + if (bus->hosttype != BCMA_HOSTTYPE_PCI)
692 + return;
693 +
694 + pc = &bus->drv_pci[0];
695 +
696 + bcma_core_pci_extend_L1timer(pc, false);
697 +}
698 +EXPORT_SYMBOL_GPL(bcma_core_pci_down);
699 --- a/drivers/bcma/driver_pci_host.c
700 +++ b/drivers/bcma/driver_pci_host.c
701 @@ -581,6 +581,7 @@ DECLARE_PCI_FIXUP_HEADER(PCI_ANY_ID, PCI
702 int bcma_core_pci_plat_dev_init(struct pci_dev *dev)
703 {
704 struct bcma_drv_pci_host *pc_host;
705 + int readrq;
706
707 if (dev->bus->ops->read != bcma_core_pci_hostmode_read_config) {
708 /* This is not a device on the PCI-core bridge. */
709 @@ -595,6 +596,11 @@ int bcma_core_pci_plat_dev_init(struct p
710 dev->irq = bcma_core_irq(pc_host->pdev->core);
711 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
712
713 + readrq = pcie_get_readrq(dev);
714 + if (readrq > 128) {
715 + pr_info("change PCIe max read request size from %i to 128\n", readrq);
716 + pcie_set_readrq(dev, 128);
717 + }
718 return 0;
719 }
720 EXPORT_SYMBOL(bcma_core_pci_plat_dev_init);
721 --- /dev/null
722 +++ b/drivers/bcma/driver_pcie2.c
723 @@ -0,0 +1,175 @@
724 +/*
725 + * Broadcom specific AMBA
726 + * PCIe Gen 2 Core
727 + *
728 + * Copyright 2014, Broadcom Corporation
729 + * Copyright 2014, Rafał Miłecki <zajec5@gmail.com>
730 + *
731 + * Licensed under the GNU/GPL. See COPYING for details.
732 + */
733 +
734 +#include "bcma_private.h"
735 +#include <linux/bcma/bcma.h>
736 +
737 +/**************************************************
738 + * R/W ops.
739 + **************************************************/
740 +
741 +#if 0
742 +static u32 bcma_core_pcie2_cfg_read(struct bcma_drv_pcie2 *pcie2, u32 addr)
743 +{
744 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, addr);
745 + pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR);
746 + return pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA);
747 +}
748 +#endif
749 +
750 +static void bcma_core_pcie2_cfg_write(struct bcma_drv_pcie2 *pcie2, u32 addr,
751 + u32 val)
752 +{
753 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, addr);
754 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, val);
755 +}
756 +
757 +/**************************************************
758 + * Init.
759 + **************************************************/
760 +
761 +static u32 bcma_core_pcie2_war_delay_perst_enab(struct bcma_drv_pcie2 *pcie2,
762 + bool enable)
763 +{
764 + u32 val;
765 +
766 + /* restore back to default */
767 + val = pcie2_read32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL);
768 + val |= PCIE2_CLKC_DLYPERST;
769 + val &= ~PCIE2_CLKC_DISSPROMLD;
770 + if (enable) {
771 + val &= ~PCIE2_CLKC_DLYPERST;
772 + val |= PCIE2_CLKC_DISSPROMLD;
773 + }
774 + pcie2_write32(pcie2, (BCMA_CORE_PCIE2_CLK_CONTROL), val);
775 + /* flush */
776 + return pcie2_read32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL);
777 +}
778 +
779 +static void bcma_core_pcie2_set_ltr_vals(struct bcma_drv_pcie2 *pcie2)
780 +{
781 + /* LTR0 */
782 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x844);
783 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x883c883c);
784 + /* LTR1 */
785 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x848);
786 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x88648864);
787 + /* LTR2 */
788 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, 0x84C);
789 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x90039003);
790 +}
791 +
792 +static void bcma_core_pcie2_hw_ltr_war(struct bcma_drv_pcie2 *pcie2)
793 +{
794 + u8 core_rev = pcie2->core->id.rev;
795 + u32 devstsctr2;
796 +
797 + if (core_rev < 2 || core_rev == 10 || core_rev > 13)
798 + return;
799 +
800 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
801 + PCIE2_CAP_DEVSTSCTRL2_OFFSET);
802 + devstsctr2 = pcie2_read32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA);
803 + if (devstsctr2 & PCIE2_CAP_DEVSTSCTRL2_LTRENAB) {
804 + /* force the right LTR values */
805 + bcma_core_pcie2_set_ltr_vals(pcie2);
806 +
807 + /* TODO:
808 + si_core_wrapperreg(pcie2, 3, 0x60, 0x8080, 0); */
809 +
810 + /* enable the LTR */
811 + devstsctr2 |= PCIE2_CAP_DEVSTSCTRL2_LTRENAB;
812 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
813 + PCIE2_CAP_DEVSTSCTRL2_OFFSET);
814 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, devstsctr2);
815 +
816 + /* set the LTR state to be active */
817 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_LTR_STATE,
818 + PCIE2_LTR_ACTIVE);
819 + usleep_range(1000, 2000);
820 +
821 + /* set the LTR state to be sleep */
822 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_LTR_STATE,
823 + PCIE2_LTR_SLEEP);
824 + usleep_range(1000, 2000);
825 + }
826 +}
827 +
828 +static void pciedev_crwlpciegen2(struct bcma_drv_pcie2 *pcie2)
829 +{
830 + u8 core_rev = pcie2->core->id.rev;
831 + bool pciewar160, pciewar162;
832 +
833 + pciewar160 = core_rev == 7 || core_rev == 9 || core_rev == 11;
834 + pciewar162 = core_rev == 5 || core_rev == 7 || core_rev == 8 ||
835 + core_rev == 9 || core_rev == 11;
836 +
837 + if (!pciewar160 && !pciewar162)
838 + return;
839 +
840 +/* TODO */
841 +#if 0
842 + pcie2_set32(pcie2, BCMA_CORE_PCIE2_CLK_CONTROL,
843 + PCIE_DISABLE_L1CLK_GATING);
844 +#if 0
845 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
846 + PCIEGEN2_COE_PVT_TL_CTRL_0);
847 + pcie2_mask32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA,
848 + ~(1 << COE_PVT_TL_CTRL_0_PM_DIS_L1_REENTRY_BIT));
849 +#endif
850 +#endif
851 +}
852 +
853 +static void pciedev_crwlpciegen2_180(struct bcma_drv_pcie2 *pcie2)
854 +{
855 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, PCIE2_PMCR_REFUP);
856 + pcie2_set32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 0x1f);
857 +}
858 +
859 +static void pciedev_crwlpciegen2_182(struct bcma_drv_pcie2 *pcie2)
860 +{
861 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR, PCIE2_SBMBX);
862 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, 1 << 0);
863 +}
864 +
865 +static void pciedev_reg_pm_clk_period(struct bcma_drv_pcie2 *pcie2)
866 +{
867 + struct bcma_drv_cc *drv_cc = &pcie2->core->bus->drv_cc;
868 + u8 core_rev = pcie2->core->id.rev;
869 + u32 alp_khz, pm_value;
870 +
871 + if (core_rev <= 13) {
872 + alp_khz = bcma_pmu_get_alp_clock(drv_cc) / 1000;
873 + pm_value = (1000000 * 2) / alp_khz;
874 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDADDR,
875 + PCIE2_PVT_REG_PM_CLK_PERIOD);
876 + pcie2_write32(pcie2, BCMA_CORE_PCIE2_CONFIGINDDATA, pm_value);
877 + }
878 +}
879 +
880 +void bcma_core_pcie2_init(struct bcma_drv_pcie2 *pcie2)
881 +{
882 + struct bcma_chipinfo *ci = &pcie2->core->bus->chipinfo;
883 + u32 tmp;
884 +
885 + tmp = pcie2_read32(pcie2, BCMA_CORE_PCIE2_SPROM(54));
886 + if ((tmp & 0xe) >> 1 == 2)
887 + bcma_core_pcie2_cfg_write(pcie2, 0x4e0, 0x17);
888 +
889 + /* TODO: Do we need pcie_reqsize? */
890 +
891 + if (ci->id == BCMA_CHIP_ID_BCM4360 && ci->rev > 3)
892 + bcma_core_pcie2_war_delay_perst_enab(pcie2, true);
893 + bcma_core_pcie2_hw_ltr_war(pcie2);
894 + pciedev_crwlpciegen2(pcie2);
895 + pciedev_reg_pm_clk_period(pcie2);
896 + pciedev_crwlpciegen2_180(pcie2);
897 + pciedev_crwlpciegen2_182(pcie2);
898 +}
899 --- a/drivers/bcma/host_pci.c
900 +++ b/drivers/bcma/host_pci.c
901 @@ -188,8 +188,11 @@ static int bcma_host_pci_probe(struct pc
902 pci_write_config_dword(dev, 0x40, val & 0xffff00ff);
903
904 /* SSB needed additional powering up, do we have any AMBA PCI cards? */
905 - if (!pci_is_pcie(dev))
906 - bcma_err(bus, "PCI card detected, report problems.\n");
907 + if (!pci_is_pcie(dev)) {
908 + bcma_err(bus, "PCI card detected, they are not supported.\n");
909 + err = -ENXIO;
910 + goto err_pci_release_regions;
911 + }
912
913 /* Map MMIO */
914 err = -ENOMEM;
915 @@ -205,6 +208,9 @@ static int bcma_host_pci_probe(struct pc
916 bus->boardinfo.vendor = bus->host_pci->subsystem_vendor;
917 bus->boardinfo.type = bus->host_pci->subsystem_device;
918
919 + /* Initialize struct, detect chip */
920 + bcma_init_bus(bus);
921 +
922 /* Register */
923 err = bcma_bus_register(bus);
924 if (err)
925 @@ -235,7 +241,6 @@ static void bcma_host_pci_remove(struct
926 pci_release_regions(dev);
927 pci_disable_device(dev);
928 kfree(bus);
929 - pci_set_drvdata(dev, NULL);
930 }
931
932 #ifdef CONFIG_PM_SLEEP
933 @@ -267,15 +272,20 @@ static SIMPLE_DEV_PM_OPS(bcma_pm_ops, bc
934
935 #endif /* CONFIG_PM_SLEEP */
936
937 -static DEFINE_PCI_DEVICE_TABLE(bcma_pci_bridge_tbl) = {
938 +static const struct pci_device_id bcma_pci_bridge_tbl[] = {
939 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x0576) },
940 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4313) },
941 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43224) },
942 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4331) },
943 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4353) },
944 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4357) },
945 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4358) },
946 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4359) },
947 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4365) },
948 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43a9) },
949 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x43aa) },
950 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4727) },
951 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43227) }, /* 0xA8DB */
952 { 0, },
953 };
954 MODULE_DEVICE_TABLE(pci, bcma_pci_bridge_tbl);
955 --- a/drivers/bcma/main.c
956 +++ b/drivers/bcma/main.c
957 @@ -10,6 +10,7 @@
958 #include <linux/platform_device.h>
959 #include <linux/bcma/bcma.h>
960 #include <linux/slab.h>
961 +#include <linux/of_address.h>
962
963 MODULE_DESCRIPTION("Broadcom's specific AMBA driver");
964 MODULE_LICENSE("GPL");
965 @@ -69,28 +70,36 @@ static u16 bcma_cc_core_id(struct bcma_b
966 return BCMA_CORE_CHIPCOMMON;
967 }
968
969 -struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid)
970 +struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
971 + u8 unit)
972 {
973 struct bcma_device *core;
974
975 list_for_each_entry(core, &bus->cores, list) {
976 - if (core->id.id == coreid)
977 + if (core->id.id == coreid && core->core_unit == unit)
978 return core;
979 }
980 return NULL;
981 }
982 -EXPORT_SYMBOL_GPL(bcma_find_core);
983 +EXPORT_SYMBOL_GPL(bcma_find_core_unit);
984
985 -struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
986 - u8 unit)
987 +bool bcma_wait_value(struct bcma_device *core, u16 reg, u32 mask, u32 value,
988 + int timeout)
989 {
990 - struct bcma_device *core;
991 + unsigned long deadline = jiffies + timeout;
992 + u32 val;
993
994 - list_for_each_entry(core, &bus->cores, list) {
995 - if (core->id.id == coreid && core->core_unit == unit)
996 - return core;
997 - }
998 - return NULL;
999 + do {
1000 + val = bcma_read32(core, reg);
1001 + if ((val & mask) == value)
1002 + return true;
1003 + cpu_relax();
1004 + udelay(10);
1005 + } while (!time_after_eq(jiffies, deadline));
1006 +
1007 + bcma_warn(core->bus, "Timeout waiting for register 0x%04X!\n", reg);
1008 +
1009 + return false;
1010 }
1011
1012 static void bcma_release_core_dev(struct device *dev)
1013 @@ -103,55 +112,121 @@ static void bcma_release_core_dev(struct
1014 kfree(core);
1015 }
1016
1017 -static int bcma_register_cores(struct bcma_bus *bus)
1018 +static bool bcma_is_core_needed_early(u16 core_id)
1019 +{
1020 + switch (core_id) {
1021 + case BCMA_CORE_NS_NAND:
1022 + case BCMA_CORE_NS_QSPI:
1023 + return true;
1024 + }
1025 +
1026 + return false;
1027 +}
1028 +
1029 +#ifdef CONFIG_OF
1030 +static struct device_node *bcma_of_find_child_device(struct platform_device *parent,
1031 + struct bcma_device *core)
1032 +{
1033 + struct device_node *node;
1034 + u64 size;
1035 + const __be32 *reg;
1036 +
1037 + if (!parent || !parent->dev.of_node)
1038 + return NULL;
1039 +
1040 + for_each_child_of_node(parent->dev.of_node, node) {
1041 + reg = of_get_address(node, 0, &size, NULL);
1042 + if (!reg)
1043 + continue;
1044 + if (of_translate_address(node, reg) == core->addr)
1045 + return node;
1046 + }
1047 + return NULL;
1048 +}
1049 +
1050 +static void bcma_of_fill_device(struct platform_device *parent,
1051 + struct bcma_device *core)
1052 +{
1053 + struct device_node *node;
1054 +
1055 + node = bcma_of_find_child_device(parent, core);
1056 + if (node)
1057 + core->dev.of_node = node;
1058 +}
1059 +#else
1060 +static void bcma_of_fill_device(struct platform_device *parent,
1061 + struct bcma_device *core)
1062 +{
1063 +}
1064 +#endif /* CONFIG_OF */
1065 +
1066 +static void bcma_register_core(struct bcma_bus *bus, struct bcma_device *core)
1067 +{
1068 + int err;
1069 +
1070 + core->dev.release = bcma_release_core_dev;
1071 + core->dev.bus = &bcma_bus_type;
1072 + dev_set_name(&core->dev, "bcma%d:%d", bus->num, core->core_index);
1073 +
1074 + switch (bus->hosttype) {
1075 + case BCMA_HOSTTYPE_PCI:
1076 + core->dev.parent = &bus->host_pci->dev;
1077 + core->dma_dev = &bus->host_pci->dev;
1078 + core->irq = bus->host_pci->irq;
1079 + break;
1080 + case BCMA_HOSTTYPE_SOC:
1081 + core->dev.dma_mask = &core->dev.coherent_dma_mask;
1082 + if (bus->host_pdev) {
1083 + core->dma_dev = &bus->host_pdev->dev;
1084 + core->dev.parent = &bus->host_pdev->dev;
1085 + bcma_of_fill_device(bus->host_pdev, core);
1086 + } else {
1087 + core->dma_dev = &core->dev;
1088 + }
1089 + break;
1090 + case BCMA_HOSTTYPE_SDIO:
1091 + break;
1092 + }
1093 +
1094 + err = device_register(&core->dev);
1095 + if (err) {
1096 + bcma_err(bus, "Could not register dev for core 0x%03X\n",
1097 + core->id.id);
1098 + put_device(&core->dev);
1099 + return;
1100 + }
1101 + core->dev_registered = true;
1102 +}
1103 +
1104 +static int bcma_register_devices(struct bcma_bus *bus)
1105 {
1106 struct bcma_device *core;
1107 - int err, dev_id = 0;
1108 + int err;
1109
1110 list_for_each_entry(core, &bus->cores, list) {
1111 /* We support that cores ourself */
1112 switch (core->id.id) {
1113 case BCMA_CORE_4706_CHIPCOMMON:
1114 case BCMA_CORE_CHIPCOMMON:
1115 + case BCMA_CORE_NS_CHIPCOMMON_B:
1116 case BCMA_CORE_PCI:
1117 case BCMA_CORE_PCIE:
1118 + case BCMA_CORE_PCIE2:
1119 case BCMA_CORE_MIPS_74K:
1120 case BCMA_CORE_4706_MAC_GBIT_COMMON:
1121 continue;
1122 }
1123
1124 + /* Early cores were already registered */
1125 + if (bcma_is_core_needed_early(core->id.id))
1126 + continue;
1127 +
1128 /* Only first GMAC core on BCM4706 is connected and working */
1129 if (core->id.id == BCMA_CORE_4706_MAC_GBIT &&
1130 core->core_unit > 0)
1131 continue;
1132
1133 - core->dev.release = bcma_release_core_dev;
1134 - core->dev.bus = &bcma_bus_type;
1135 - dev_set_name(&core->dev, "bcma%d:%d", bus->num, dev_id);
1136 -
1137 - switch (bus->hosttype) {
1138 - case BCMA_HOSTTYPE_PCI:
1139 - core->dev.parent = &bus->host_pci->dev;
1140 - core->dma_dev = &bus->host_pci->dev;
1141 - core->irq = bus->host_pci->irq;
1142 - break;
1143 - case BCMA_HOSTTYPE_SOC:
1144 - core->dev.dma_mask = &core->dev.coherent_dma_mask;
1145 - core->dma_dev = &core->dev;
1146 - break;
1147 - case BCMA_HOSTTYPE_SDIO:
1148 - break;
1149 - }
1150 -
1151 - err = device_register(&core->dev);
1152 - if (err) {
1153 - bcma_err(bus,
1154 - "Could not register dev for core 0x%03X\n",
1155 - core->id.id);
1156 - continue;
1157 - }
1158 - core->dev_registered = true;
1159 - dev_id++;
1160 + bcma_register_core(bus, core);
1161 }
1162
1163 #ifdef CONFIG_BCMA_DRIVER_MIPS
1164 @@ -218,7 +293,7 @@ int bcma_bus_register(struct bcma_bus *b
1165 err = bcma_bus_scan(bus);
1166 if (err) {
1167 bcma_err(bus, "Failed to scan: %d\n", err);
1168 - return -1;
1169 + return err;
1170 }
1171
1172 /* Early init CC core */
1173 @@ -228,6 +303,12 @@ int bcma_bus_register(struct bcma_bus *b
1174 bcma_core_chipcommon_early_init(&bus->drv_cc);
1175 }
1176
1177 + /* Cores providing flash access go before SPROM init */
1178 + list_for_each_entry(core, &bus->cores, list) {
1179 + if (bcma_is_core_needed_early(core->id.id))
1180 + bcma_register_core(bus, core);
1181 + }
1182 +
1183 /* Try to get SPROM */
1184 err = bcma_sprom_get(bus);
1185 if (err == -ENOENT) {
1186 @@ -242,6 +323,13 @@ int bcma_bus_register(struct bcma_bus *b
1187 bcma_core_chipcommon_init(&bus->drv_cc);
1188 }
1189
1190 + /* Init CC core */
1191 + core = bcma_find_core(bus, BCMA_CORE_NS_CHIPCOMMON_B);
1192 + if (core) {
1193 + bus->drv_cc_b.core = core;
1194 + bcma_core_chipcommon_b_init(&bus->drv_cc_b);
1195 + }
1196 +
1197 /* Init MIPS core */
1198 core = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
1199 if (core) {
1200 @@ -263,6 +351,13 @@ int bcma_bus_register(struct bcma_bus *b
1201 bcma_core_pci_init(&bus->drv_pci[1]);
1202 }
1203
1204 + /* Init PCIe Gen 2 core */
1205 + core = bcma_find_core_unit(bus, BCMA_CORE_PCIE2, 0);
1206 + if (core) {
1207 + bus->drv_pcie2.core = core;
1208 + bcma_core_pcie2_init(&bus->drv_pcie2);
1209 + }
1210 +
1211 /* Init GBIT MAC COMMON core */
1212 core = bcma_find_core(bus, BCMA_CORE_4706_MAC_GBIT_COMMON);
1213 if (core) {
1214 @@ -271,7 +366,7 @@ int bcma_bus_register(struct bcma_bus *b
1215 }
1216
1217 /* Register found cores */
1218 - bcma_register_cores(bus);
1219 + bcma_register_devices(bus);
1220
1221 bcma_info(bus, "Bus registered\n");
1222
1223 @@ -289,6 +384,8 @@ void bcma_bus_unregister(struct bcma_bus
1224 else if (err)
1225 bcma_err(bus, "Can not unregister GPIO driver: %i\n", err);
1226
1227 + bcma_core_chipcommon_b_free(&bus->drv_cc_b);
1228 +
1229 cores[0] = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
1230 cores[1] = bcma_find_core(bus, BCMA_CORE_PCIE);
1231 cores[2] = bcma_find_core(bus, BCMA_CORE_4706_MAC_GBIT_COMMON);
1232 @@ -308,8 +405,6 @@ int __init bcma_bus_early_register(struc
1233 struct bcma_device *core;
1234 struct bcma_device_id match;
1235
1236 - bcma_init_bus(bus);
1237 -
1238 match.manuf = BCMA_MANUF_BCM;
1239 match.id = bcma_cc_core_id(bus);
1240 match.class = BCMA_CL_SIM;
1241 @@ -468,6 +563,11 @@ static int __init bcma_modinit(void)
1242 if (err)
1243 return err;
1244
1245 + err = bcma_host_soc_register_driver();
1246 + if (err) {
1247 + pr_err("SoC host initialization failed\n");
1248 + err = 0;
1249 + }
1250 #ifdef CONFIG_BCMA_HOST_PCI
1251 err = bcma_host_pci_init();
1252 if (err) {
1253 @@ -485,6 +585,7 @@ static void __exit bcma_modexit(void)
1254 #ifdef CONFIG_BCMA_HOST_PCI
1255 bcma_host_pci_exit();
1256 #endif
1257 + bcma_host_soc_unregister_driver();
1258 bus_unregister(&bcma_bus_type);
1259 }
1260 module_exit(bcma_modexit)
1261 --- a/drivers/bcma/scan.c
1262 +++ b/drivers/bcma/scan.c
1263 @@ -32,6 +32,18 @@ static const struct bcma_device_id_name
1264 { BCMA_CORE_4706_CHIPCOMMON, "BCM4706 ChipCommon" },
1265 { BCMA_CORE_4706_SOC_RAM, "BCM4706 SOC RAM" },
1266 { BCMA_CORE_4706_MAC_GBIT, "BCM4706 GBit MAC" },
1267 + { BCMA_CORE_NS_PCIEG2, "PCIe Gen 2" },
1268 + { BCMA_CORE_NS_DMA, "DMA" },
1269 + { BCMA_CORE_NS_SDIO3, "SDIO3" },
1270 + { BCMA_CORE_NS_USB20, "USB 2.0" },
1271 + { BCMA_CORE_NS_USB30, "USB 3.0" },
1272 + { BCMA_CORE_NS_A9JTAG, "ARM Cortex A9 JTAG" },
1273 + { BCMA_CORE_NS_DDR23, "Denali DDR2/DDR3 memory controller" },
1274 + { BCMA_CORE_NS_ROM, "ROM" },
1275 + { BCMA_CORE_NS_NAND, "NAND flash controller" },
1276 + { BCMA_CORE_NS_QSPI, "SPI flash controller" },
1277 + { BCMA_CORE_NS_CHIPCOMMON_B, "Chipcommon B" },
1278 + { BCMA_CORE_ARMCA9, "ARM Cortex A9 core (ihost)" },
1279 { BCMA_CORE_AMEMC, "AMEMC (DDR)" },
1280 { BCMA_CORE_ALTA, "ALTA (I2S)" },
1281 { BCMA_CORE_INVALID, "Invalid" },
1282 @@ -201,7 +213,7 @@ static s32 bcma_erom_get_mst_port(struct
1283 return ent;
1284 }
1285
1286 -static s32 bcma_erom_get_addr_desc(struct bcma_bus *bus, u32 __iomem **eromptr,
1287 +static u32 bcma_erom_get_addr_desc(struct bcma_bus *bus, u32 __iomem **eromptr,
1288 u32 type, u8 port)
1289 {
1290 u32 addrl, addrh, sizel, sizeh = 0;
1291 @@ -213,7 +225,7 @@ static s32 bcma_erom_get_addr_desc(struc
1292 ((ent & SCAN_ADDR_TYPE) != type) ||
1293 (((ent & SCAN_ADDR_PORT) >> SCAN_ADDR_PORT_SHIFT) != port)) {
1294 bcma_erom_push_ent(eromptr);
1295 - return -EINVAL;
1296 + return (u32)-EINVAL;
1297 }
1298
1299 addrl = ent & SCAN_ADDR_ADDR;
1300 @@ -257,12 +269,14 @@ static struct bcma_device *bcma_find_cor
1301 return NULL;
1302 }
1303
1304 +#define IS_ERR_VALUE_U32(x) ((x) >= (u32)-MAX_ERRNO)
1305 +
1306 static int bcma_get_next_core(struct bcma_bus *bus, u32 __iomem **eromptr,
1307 struct bcma_device_id *match, int core_num,
1308 struct bcma_device *core)
1309 {
1310 - s32 tmp;
1311 - u8 i, j;
1312 + u32 tmp;
1313 + u8 i, j, k;
1314 s32 cia, cib;
1315 u8 ports[2], wrappers[2];
1316
1317 @@ -300,6 +314,7 @@ static int bcma_get_next_core(struct bcm
1318 /* Some specific cores don't need wrappers */
1319 switch (core->id.id) {
1320 case BCMA_CORE_4706_MAC_GBIT_COMMON:
1321 + case BCMA_CORE_NS_CHIPCOMMON_B:
1322 /* Not used yet: case BCMA_CORE_OOB_ROUTER: */
1323 break;
1324 default:
1325 @@ -339,11 +354,11 @@ static int bcma_get_next_core(struct bcm
1326 * the main register space for the core
1327 */
1328 tmp = bcma_erom_get_addr_desc(bus, eromptr, SCAN_ADDR_TYPE_SLAVE, 0);
1329 - if (tmp <= 0) {
1330 + if (tmp == 0 || IS_ERR_VALUE_U32(tmp)) {
1331 /* Try again to see if it is a bridge */
1332 tmp = bcma_erom_get_addr_desc(bus, eromptr,
1333 SCAN_ADDR_TYPE_BRIDGE, 0);
1334 - if (tmp <= 0) {
1335 + if (tmp == 0 || IS_ERR_VALUE_U32(tmp)) {
1336 return -EILSEQ;
1337 } else {
1338 bcma_info(bus, "Bridge found\n");
1339 @@ -353,18 +368,19 @@ static int bcma_get_next_core(struct bcm
1340 core->addr = tmp;
1341
1342 /* get & parse slave ports */
1343 + k = 0;
1344 for (i = 0; i < ports[1]; i++) {
1345 for (j = 0; ; j++) {
1346 tmp = bcma_erom_get_addr_desc(bus, eromptr,
1347 SCAN_ADDR_TYPE_SLAVE, i);
1348 - if (tmp < 0) {
1349 + if (IS_ERR_VALUE_U32(tmp)) {
1350 /* no more entries for port _i_ */
1351 /* pr_debug("erom: slave port %d "
1352 * "has %d descriptors\n", i, j); */
1353 break;
1354 - } else {
1355 - if (i == 0 && j == 0)
1356 - core->addr1 = tmp;
1357 + } else if (k < ARRAY_SIZE(core->addr_s)) {
1358 + core->addr_s[k] = tmp;
1359 + k++;
1360 }
1361 }
1362 }
1363 @@ -374,7 +390,7 @@ static int bcma_get_next_core(struct bcm
1364 for (j = 0; ; j++) {
1365 tmp = bcma_erom_get_addr_desc(bus, eromptr,
1366 SCAN_ADDR_TYPE_MWRAP, i);
1367 - if (tmp < 0) {
1368 + if (IS_ERR_VALUE_U32(tmp)) {
1369 /* no more entries for port _i_ */
1370 /* pr_debug("erom: master wrapper %d "
1371 * "has %d descriptors\n", i, j); */
1372 @@ -392,7 +408,7 @@ static int bcma_get_next_core(struct bcm
1373 for (j = 0; ; j++) {
1374 tmp = bcma_erom_get_addr_desc(bus, eromptr,
1375 SCAN_ADDR_TYPE_SWRAP, i + hack);
1376 - if (tmp < 0) {
1377 + if (IS_ERR_VALUE_U32(tmp)) {
1378 /* no more entries for port _i_ */
1379 /* pr_debug("erom: master wrapper %d "
1380 * has %d descriptors\n", i, j); */
1381 @@ -407,10 +423,13 @@ static int bcma_get_next_core(struct bcm
1382 core->io_addr = ioremap_nocache(core->addr, BCMA_CORE_SIZE);
1383 if (!core->io_addr)
1384 return -ENOMEM;
1385 - core->io_wrap = ioremap_nocache(core->wrap, BCMA_CORE_SIZE);
1386 - if (!core->io_wrap) {
1387 - iounmap(core->io_addr);
1388 - return -ENOMEM;
1389 + if (core->wrap) {
1390 + core->io_wrap = ioremap_nocache(core->wrap,
1391 + BCMA_CORE_SIZE);
1392 + if (!core->io_wrap) {
1393 + iounmap(core->io_addr);
1394 + return -ENOMEM;
1395 + }
1396 }
1397 }
1398 return 0;
1399 @@ -420,9 +439,7 @@ void bcma_init_bus(struct bcma_bus *bus)
1400 {
1401 s32 tmp;
1402 struct bcma_chipinfo *chipinfo = &(bus->chipinfo);
1403 -
1404 - if (bus->init_done)
1405 - return;
1406 + char chip_id[8];
1407
1408 INIT_LIST_HEAD(&bus->cores);
1409 bus->nr_cores = 0;
1410 @@ -433,10 +450,11 @@ void bcma_init_bus(struct bcma_bus *bus)
1411 chipinfo->id = (tmp & BCMA_CC_ID_ID) >> BCMA_CC_ID_ID_SHIFT;
1412 chipinfo->rev = (tmp & BCMA_CC_ID_REV) >> BCMA_CC_ID_REV_SHIFT;
1413 chipinfo->pkg = (tmp & BCMA_CC_ID_PKG) >> BCMA_CC_ID_PKG_SHIFT;
1414 - bcma_info(bus, "Found chip with id 0x%04X, rev 0x%02X and package 0x%02X\n",
1415 - chipinfo->id, chipinfo->rev, chipinfo->pkg);
1416
1417 - bus->init_done = true;
1418 + snprintf(chip_id, ARRAY_SIZE(chip_id),
1419 + (chipinfo->id > 0x9999) ? "%d" : "0x%04X", chipinfo->id);
1420 + bcma_info(bus, "Found chip with id %s, rev 0x%02X and package 0x%02X\n",
1421 + chip_id, chipinfo->rev, chipinfo->pkg);
1422 }
1423
1424 int bcma_bus_scan(struct bcma_bus *bus)
1425 @@ -446,8 +464,6 @@ int bcma_bus_scan(struct bcma_bus *bus)
1426
1427 int err, core_num = 0;
1428
1429 - bcma_init_bus(bus);
1430 -
1431 erombase = bcma_scan_read32(bus, 0, BCMA_CC_EROM);
1432 if (bus->hosttype == BCMA_HOSTTYPE_SOC) {
1433 eromptr = ioremap_nocache(erombase, BCMA_CORE_SIZE);
1434 --- a/drivers/bcma/sprom.c
1435 +++ b/drivers/bcma/sprom.c
1436 @@ -72,12 +72,12 @@ fail:
1437 * R/W ops.
1438 **************************************************/
1439
1440 -static void bcma_sprom_read(struct bcma_bus *bus, u16 offset, u16 *sprom)
1441 +static void bcma_sprom_read(struct bcma_bus *bus, u16 offset, u16 *sprom,
1442 + size_t words)
1443 {
1444 int i;
1445 - for (i = 0; i < SSB_SPROMSIZE_WORDS_R4; i++)
1446 - sprom[i] = bcma_read16(bus->drv_cc.core,
1447 - offset + (i * 2));
1448 + for (i = 0; i < words; i++)
1449 + sprom[i] = bcma_read16(bus->drv_cc.core, offset + (i * 2));
1450 }
1451
1452 /**************************************************
1453 @@ -124,29 +124,29 @@ static inline u8 bcma_crc8(u8 crc, u8 da
1454 return t[crc ^ data];
1455 }
1456
1457 -static u8 bcma_sprom_crc(const u16 *sprom)
1458 +static u8 bcma_sprom_crc(const u16 *sprom, size_t words)
1459 {
1460 int word;
1461 u8 crc = 0xFF;
1462
1463 - for (word = 0; word < SSB_SPROMSIZE_WORDS_R4 - 1; word++) {
1464 + for (word = 0; word < words - 1; word++) {
1465 crc = bcma_crc8(crc, sprom[word] & 0x00FF);
1466 crc = bcma_crc8(crc, (sprom[word] & 0xFF00) >> 8);
1467 }
1468 - crc = bcma_crc8(crc, sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & 0x00FF);
1469 + crc = bcma_crc8(crc, sprom[words - 1] & 0x00FF);
1470 crc ^= 0xFF;
1471
1472 return crc;
1473 }
1474
1475 -static int bcma_sprom_check_crc(const u16 *sprom)
1476 +static int bcma_sprom_check_crc(const u16 *sprom, size_t words)
1477 {
1478 u8 crc;
1479 u8 expected_crc;
1480 u16 tmp;
1481
1482 - crc = bcma_sprom_crc(sprom);
1483 - tmp = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & SSB_SPROM_REVISION_CRC;
1484 + crc = bcma_sprom_crc(sprom, words);
1485 + tmp = sprom[words - 1] & SSB_SPROM_REVISION_CRC;
1486 expected_crc = tmp >> SSB_SPROM_REVISION_CRC_SHIFT;
1487 if (crc != expected_crc)
1488 return -EPROTO;
1489 @@ -154,21 +154,25 @@ static int bcma_sprom_check_crc(const u1
1490 return 0;
1491 }
1492
1493 -static int bcma_sprom_valid(const u16 *sprom)
1494 +static int bcma_sprom_valid(struct bcma_bus *bus, const u16 *sprom,
1495 + size_t words)
1496 {
1497 u16 revision;
1498 int err;
1499
1500 - err = bcma_sprom_check_crc(sprom);
1501 + err = bcma_sprom_check_crc(sprom, words);
1502 if (err)
1503 return err;
1504
1505 - revision = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] & SSB_SPROM_REVISION_REV;
1506 - if (revision != 8 && revision != 9) {
1507 + revision = sprom[words - 1] & SSB_SPROM_REVISION_REV;
1508 + if (revision != 8 && revision != 9 && revision != 10) {
1509 pr_err("Unsupported SPROM revision: %d\n", revision);
1510 return -ENOENT;
1511 }
1512
1513 + bus->sprom.revision = revision;
1514 + bcma_debug(bus, "Found SPROM revision %d\n", revision);
1515 +
1516 return 0;
1517 }
1518
1519 @@ -197,6 +201,23 @@ static int bcma_sprom_valid(const u16 *s
1520 SPEX(_field[7], _offset + 14, _mask, _shift); \
1521 } while (0)
1522
1523 +static s8 sprom_extract_antgain(const u16 *in, u16 offset, u16 mask, u16 shift)
1524 +{
1525 + u16 v;
1526 + u8 gain;
1527 +
1528 + v = in[SPOFF(offset)];
1529 + gain = (v & mask) >> shift;
1530 + if (gain == 0xFF) {
1531 + gain = 8; /* If unset use 2dBm */
1532 + } else {
1533 + /* Q5.2 Fractional part is stored in 0xC0 */
1534 + gain = ((gain & 0xC0) >> 6) | ((gain & 0x3F) << 2);
1535 + }
1536 +
1537 + return (s8)gain;
1538 +}
1539 +
1540 static void bcma_sprom_extract_r8(struct bcma_bus *bus, const u16 *sprom)
1541 {
1542 u16 v, o;
1543 @@ -208,9 +229,6 @@ static void bcma_sprom_extract_r8(struct
1544 BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
1545 ARRAY_SIZE(bus->sprom.core_pwr_info));
1546
1547 - bus->sprom.revision = sprom[SSB_SPROMSIZE_WORDS_R4 - 1] &
1548 - SSB_SPROM_REVISION_REV;
1549 -
1550 for (i = 0; i < 3; i++) {
1551 v = sprom[SPOFF(SSB_SPROM8_IL0MAC) + i];
1552 *(((__be16 *)bus->sprom.il0mac) + i) = cpu_to_be16(v);
1553 @@ -380,14 +398,22 @@ static void bcma_sprom_extract_r8(struct
1554 SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, ~0, 0);
1555
1556 /* Extract the antenna gain values. */
1557 - SPEX(antenna_gain.a0, SSB_SPROM8_AGAIN01,
1558 - SSB_SPROM8_AGAIN0, SSB_SPROM8_AGAIN0_SHIFT);
1559 - SPEX(antenna_gain.a1, SSB_SPROM8_AGAIN01,
1560 - SSB_SPROM8_AGAIN1, SSB_SPROM8_AGAIN1_SHIFT);
1561 - SPEX(antenna_gain.a2, SSB_SPROM8_AGAIN23,
1562 - SSB_SPROM8_AGAIN2, SSB_SPROM8_AGAIN2_SHIFT);
1563 - SPEX(antenna_gain.a3, SSB_SPROM8_AGAIN23,
1564 - SSB_SPROM8_AGAIN3, SSB_SPROM8_AGAIN3_SHIFT);
1565 + bus->sprom.antenna_gain.a0 = sprom_extract_antgain(sprom,
1566 + SSB_SPROM8_AGAIN01,
1567 + SSB_SPROM8_AGAIN0,
1568 + SSB_SPROM8_AGAIN0_SHIFT);
1569 + bus->sprom.antenna_gain.a1 = sprom_extract_antgain(sprom,
1570 + SSB_SPROM8_AGAIN01,
1571 + SSB_SPROM8_AGAIN1,
1572 + SSB_SPROM8_AGAIN1_SHIFT);
1573 + bus->sprom.antenna_gain.a2 = sprom_extract_antgain(sprom,
1574 + SSB_SPROM8_AGAIN23,
1575 + SSB_SPROM8_AGAIN2,
1576 + SSB_SPROM8_AGAIN2_SHIFT);
1577 + bus->sprom.antenna_gain.a3 = sprom_extract_antgain(sprom,
1578 + SSB_SPROM8_AGAIN23,
1579 + SSB_SPROM8_AGAIN3,
1580 + SSB_SPROM8_AGAIN3_SHIFT);
1581
1582 SPEX(leddc_on_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_ON,
1583 SSB_SPROM8_LEDDC_ON_SHIFT);
1584 @@ -502,12 +528,14 @@ static bool bcma_sprom_onchip_available(
1585 case BCMA_CHIP_ID_BCM4331:
1586 present = chip_status & BCMA_CC_CHIPST_4331_OTP_PRESENT;
1587 break;
1588 -
1589 + case BCMA_CHIP_ID_BCM43142:
1590 case BCMA_CHIP_ID_BCM43224:
1591 case BCMA_CHIP_ID_BCM43225:
1592 /* for these chips OTP is always available */
1593 present = true;
1594 break;
1595 + case BCMA_CHIP_ID_BCM43131:
1596 + case BCMA_CHIP_ID_BCM43217:
1597 case BCMA_CHIP_ID_BCM43227:
1598 case BCMA_CHIP_ID_BCM43228:
1599 case BCMA_CHIP_ID_BCM43428:
1600 @@ -550,7 +578,9 @@ int bcma_sprom_get(struct bcma_bus *bus)
1601 {
1602 u16 offset = BCMA_CC_SPROM;
1603 u16 *sprom;
1604 - int err = 0;
1605 + size_t sprom_sizes[] = { SSB_SPROMSIZE_WORDS_R4,
1606 + SSB_SPROMSIZE_WORDS_R10, };
1607 + int i, err = 0;
1608
1609 if (!bus->drv_cc.core)
1610 return -EOPNOTSUPP;
1611 @@ -579,32 +609,37 @@ int bcma_sprom_get(struct bcma_bus *bus)
1612 }
1613 }
1614
1615 - sprom = kcalloc(SSB_SPROMSIZE_WORDS_R4, sizeof(u16),
1616 - GFP_KERNEL);
1617 - if (!sprom)
1618 - return -ENOMEM;
1619 -
1620 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4331 ||
1621 bus->chipinfo.id == BCMA_CHIP_ID_BCM43431)
1622 bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, false);
1623
1624 bcma_debug(bus, "SPROM offset 0x%x\n", offset);
1625 - bcma_sprom_read(bus, offset, sprom);
1626 + for (i = 0; i < ARRAY_SIZE(sprom_sizes); i++) {
1627 + size_t words = sprom_sizes[i];
1628 +
1629 + sprom = kcalloc(words, sizeof(u16), GFP_KERNEL);
1630 + if (!sprom)
1631 + return -ENOMEM;
1632 +
1633 + bcma_sprom_read(bus, offset, sprom, words);
1634 + err = bcma_sprom_valid(bus, sprom, words);
1635 + if (!err)
1636 + break;
1637 +
1638 + kfree(sprom);
1639 + }
1640
1641 if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4331 ||
1642 bus->chipinfo.id == BCMA_CHIP_ID_BCM43431)
1643 bcma_chipco_bcm4331_ext_pa_lines_ctl(&bus->drv_cc, true);
1644
1645 - err = bcma_sprom_valid(sprom);
1646 if (err) {
1647 - bcma_warn(bus, "invalid sprom read from the PCIe card, try to use fallback sprom\n");
1648 + bcma_warn(bus, "Invalid SPROM read from the PCIe card, trying to use fallback SPROM\n");
1649 err = bcma_fill_sprom_with_fallback(bus, &bus->sprom);
1650 - goto out;
1651 + } else {
1652 + bcma_sprom_extract_r8(bus, sprom);
1653 + kfree(sprom);
1654 }
1655
1656 - bcma_sprom_extract_r8(bus, sprom);
1657 -
1658 -out:
1659 - kfree(sprom);
1660 return err;
1661 }
1662 --- a/include/linux/bcma/bcma.h
1663 +++ b/include/linux/bcma/bcma.h
1664 @@ -6,6 +6,7 @@
1665
1666 #include <linux/bcma/bcma_driver_chipcommon.h>
1667 #include <linux/bcma/bcma_driver_pci.h>
1668 +#include <linux/bcma/bcma_driver_pcie2.h>
1669 #include <linux/bcma/bcma_driver_mips.h>
1670 #include <linux/bcma/bcma_driver_gmac_cmn.h>
1671 #include <linux/ssb/ssb.h> /* SPROM sharing */
1672 @@ -72,7 +73,19 @@ struct bcma_host_ops {
1673 /* Core-ID values. */
1674 #define BCMA_CORE_OOB_ROUTER 0x367 /* Out of band */
1675 #define BCMA_CORE_4706_CHIPCOMMON 0x500
1676 +#define BCMA_CORE_NS_PCIEG2 0x501
1677 +#define BCMA_CORE_NS_DMA 0x502
1678 +#define BCMA_CORE_NS_SDIO3 0x503
1679 +#define BCMA_CORE_NS_USB20 0x504
1680 +#define BCMA_CORE_NS_USB30 0x505
1681 +#define BCMA_CORE_NS_A9JTAG 0x506
1682 +#define BCMA_CORE_NS_DDR23 0x507
1683 +#define BCMA_CORE_NS_ROM 0x508
1684 +#define BCMA_CORE_NS_NAND 0x509
1685 +#define BCMA_CORE_NS_QSPI 0x50A
1686 +#define BCMA_CORE_NS_CHIPCOMMON_B 0x50B
1687 #define BCMA_CORE_4706_SOC_RAM 0x50E
1688 +#define BCMA_CORE_ARMCA9 0x510
1689 #define BCMA_CORE_4706_MAC_GBIT 0x52D
1690 #define BCMA_CORE_AMEMC 0x52E /* DDR1/2 memory controller core */
1691 #define BCMA_CORE_ALTA 0x534 /* I2S core */
1692 @@ -144,6 +157,10 @@ struct bcma_host_ops {
1693
1694 /* Chip IDs of PCIe devices */
1695 #define BCMA_CHIP_ID_BCM4313 0x4313
1696 +#define BCMA_CHIP_ID_BCM43142 43142
1697 +#define BCMA_CHIP_ID_BCM43131 43131
1698 +#define BCMA_CHIP_ID_BCM43217 43217
1699 +#define BCMA_CHIP_ID_BCM43222 43222
1700 #define BCMA_CHIP_ID_BCM43224 43224
1701 #define BCMA_PKG_ID_BCM43224_FAB_CSM 0x8
1702 #define BCMA_PKG_ID_BCM43224_FAB_SMIC 0xa
1703 @@ -176,6 +193,11 @@ struct bcma_host_ops {
1704 #define BCMA_PKG_ID_BCM5357 11
1705 #define BCMA_CHIP_ID_BCM53572 53572
1706 #define BCMA_PKG_ID_BCM47188 9
1707 +#define BCMA_CHIP_ID_BCM4707 53010
1708 +#define BCMA_PKG_ID_BCM4707 1
1709 +#define BCMA_PKG_ID_BCM4708 2
1710 +#define BCMA_PKG_ID_BCM4709 0
1711 +#define BCMA_CHIP_ID_BCM53018 53018
1712
1713 /* Board types (on PCI usually equals to the subsystem dev id) */
1714 /* BCM4313 */
1715 @@ -245,7 +267,7 @@ struct bcma_device {
1716 u8 core_unit;
1717
1718 u32 addr;
1719 - u32 addr1;
1720 + u32 addr_s[8];
1721 u32 wrap;
1722
1723 void __iomem *io_addr;
1724 @@ -301,6 +323,8 @@ struct bcma_bus {
1725 struct pci_dev *host_pci;
1726 /* Pointer to the SDIO device (only for BCMA_HOSTTYPE_SDIO) */
1727 struct sdio_func *host_sdio;
1728 + /* Pointer to platform device (only for BCMA_HOSTTYPE_SOC) */
1729 + struct platform_device *host_pdev;
1730 };
1731
1732 struct bcma_chipinfo chipinfo;
1733 @@ -310,11 +334,12 @@ struct bcma_bus {
1734 struct bcma_device *mapped_core;
1735 struct list_head cores;
1736 u8 nr_cores;
1737 - u8 init_done:1;
1738 u8 num;
1739
1740 struct bcma_drv_cc drv_cc;
1741 + struct bcma_drv_cc_b drv_cc_b;
1742 struct bcma_drv_pci drv_pci[2];
1743 + struct bcma_drv_pcie2 drv_pcie2;
1744 struct bcma_drv_mips drv_mips;
1745 struct bcma_drv_gmac_cmn drv_gmac_cmn;
1746
1747 @@ -400,7 +425,14 @@ static inline void bcma_maskset16(struct
1748 bcma_write16(cc, offset, (bcma_read16(cc, offset) & mask) | set);
1749 }
1750
1751 -extern struct bcma_device *bcma_find_core(struct bcma_bus *bus, u16 coreid);
1752 +extern struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
1753 + u8 unit);
1754 +static inline struct bcma_device *bcma_find_core(struct bcma_bus *bus,
1755 + u16 coreid)
1756 +{
1757 + return bcma_find_core_unit(bus, coreid, 0);
1758 +}
1759 +
1760 extern bool bcma_core_is_enabled(struct bcma_device *core);
1761 extern void bcma_core_disable(struct bcma_device *core, u32 flags);
1762 extern int bcma_core_enable(struct bcma_device *core, u32 flags);
1763 --- a/include/linux/bcma/bcma_driver_chipcommon.h
1764 +++ b/include/linux/bcma/bcma_driver_chipcommon.h
1765 @@ -330,6 +330,8 @@
1766 #define BCMA_CC_PMU_CAP 0x0604 /* PMU capabilities */
1767 #define BCMA_CC_PMU_CAP_REVISION 0x000000FF /* Revision mask */
1768 #define BCMA_CC_PMU_STAT 0x0608 /* PMU status */
1769 +#define BCMA_CC_PMU_STAT_EXT_LPO_AVAIL 0x00000100
1770 +#define BCMA_CC_PMU_STAT_WDRESET 0x00000080
1771 #define BCMA_CC_PMU_STAT_INTPEND 0x00000040 /* Interrupt pending */
1772 #define BCMA_CC_PMU_STAT_SBCLKST 0x00000030 /* Backplane clock status? */
1773 #define BCMA_CC_PMU_STAT_HAVEALP 0x00000008 /* ALP available */
1774 @@ -355,6 +357,11 @@
1775 #define BCMA_CC_REGCTL_DATA 0x065C
1776 #define BCMA_CC_PLLCTL_ADDR 0x0660
1777 #define BCMA_CC_PLLCTL_DATA 0x0664
1778 +#define BCMA_CC_PMU_STRAPOPT 0x0668 /* (corerev >= 28) */
1779 +#define BCMA_CC_PMU_XTAL_FREQ 0x066C /* (pmurev >= 10) */
1780 +#define BCMA_CC_PMU_XTAL_FREQ_ILPCTL_MASK 0x00001FFF
1781 +#define BCMA_CC_PMU_XTAL_FREQ_MEASURE_MASK 0x80000000
1782 +#define BCMA_CC_PMU_XTAL_FREQ_MEASURE_SHIFT 31
1783 #define BCMA_CC_SPROM 0x0800 /* SPROM beginning */
1784 /* NAND flash MLC controller registers (corerev >= 38) */
1785 #define BCMA_CC_NAND_REVISION 0x0C00
1786 @@ -435,6 +442,23 @@
1787 #define BCMA_CC_PMU6_4706_PROC_NDIV_MODE_MASK 0x00000007
1788 #define BCMA_CC_PMU6_4706_PROC_NDIV_MODE_SHIFT 0
1789
1790 +/* PMU rev 15 */
1791 +#define BCMA_CC_PMU15_PLL_PLLCTL0 0
1792 +#define BCMA_CC_PMU15_PLL_PC0_CLKSEL_MASK 0x00000003
1793 +#define BCMA_CC_PMU15_PLL_PC0_CLKSEL_SHIFT 0
1794 +#define BCMA_CC_PMU15_PLL_PC0_FREQTGT_MASK 0x003FFFFC
1795 +#define BCMA_CC_PMU15_PLL_PC0_FREQTGT_SHIFT 2
1796 +#define BCMA_CC_PMU15_PLL_PC0_PRESCALE_MASK 0x00C00000
1797 +#define BCMA_CC_PMU15_PLL_PC0_PRESCALE_SHIFT 22
1798 +#define BCMA_CC_PMU15_PLL_PC0_KPCTRL_MASK 0x07000000
1799 +#define BCMA_CC_PMU15_PLL_PC0_KPCTRL_SHIFT 24
1800 +#define BCMA_CC_PMU15_PLL_PC0_FCNTCTRL_MASK 0x38000000
1801 +#define BCMA_CC_PMU15_PLL_PC0_FCNTCTRL_SHIFT 27
1802 +#define BCMA_CC_PMU15_PLL_PC0_FDCMODE_MASK 0x40000000
1803 +#define BCMA_CC_PMU15_PLL_PC0_FDCMODE_SHIFT 30
1804 +#define BCMA_CC_PMU15_PLL_PC0_CTRLBIAS_MASK 0x80000000
1805 +#define BCMA_CC_PMU15_PLL_PC0_CTRLBIAS_SHIFT 31
1806 +
1807 /* ALP clock on pre-PMU chips */
1808 #define BCMA_CC_PMU_ALP_CLOCK 20000000
1809 /* HT clock for systems with PMU-enabled chipcommon */
1810 @@ -507,6 +531,37 @@
1811 #define BCMA_CHIPCTL_5357_I2S_PINS_ENABLE BIT(18)
1812 #define BCMA_CHIPCTL_5357_I2CSPI_PINS_ENABLE BIT(19)
1813
1814 +#define BCMA_RES_4314_LPLDO_PU BIT(0)
1815 +#define BCMA_RES_4314_PMU_SLEEP_DIS BIT(1)
1816 +#define BCMA_RES_4314_PMU_BG_PU BIT(2)
1817 +#define BCMA_RES_4314_CBUCK_LPOM_PU BIT(3)
1818 +#define BCMA_RES_4314_CBUCK_PFM_PU BIT(4)
1819 +#define BCMA_RES_4314_CLDO_PU BIT(5)
1820 +#define BCMA_RES_4314_LPLDO2_LVM BIT(6)
1821 +#define BCMA_RES_4314_WL_PMU_PU BIT(7)
1822 +#define BCMA_RES_4314_LNLDO_PU BIT(8)
1823 +#define BCMA_RES_4314_LDO3P3_PU BIT(9)
1824 +#define BCMA_RES_4314_OTP_PU BIT(10)
1825 +#define BCMA_RES_4314_XTAL_PU BIT(11)
1826 +#define BCMA_RES_4314_WL_PWRSW_PU BIT(12)
1827 +#define BCMA_RES_4314_LQ_AVAIL BIT(13)
1828 +#define BCMA_RES_4314_LOGIC_RET BIT(14)
1829 +#define BCMA_RES_4314_MEM_SLEEP BIT(15)
1830 +#define BCMA_RES_4314_MACPHY_RET BIT(16)
1831 +#define BCMA_RES_4314_WL_CORE_READY BIT(17)
1832 +#define BCMA_RES_4314_ILP_REQ BIT(18)
1833 +#define BCMA_RES_4314_ALP_AVAIL BIT(19)
1834 +#define BCMA_RES_4314_MISC_PWRSW_PU BIT(20)
1835 +#define BCMA_RES_4314_SYNTH_PWRSW_PU BIT(21)
1836 +#define BCMA_RES_4314_RX_PWRSW_PU BIT(22)
1837 +#define BCMA_RES_4314_RADIO_PU BIT(23)
1838 +#define BCMA_RES_4314_VCO_LDO_PU BIT(24)
1839 +#define BCMA_RES_4314_AFE_LDO_PU BIT(25)
1840 +#define BCMA_RES_4314_RX_LDO_PU BIT(26)
1841 +#define BCMA_RES_4314_TX_LDO_PU BIT(27)
1842 +#define BCMA_RES_4314_HT_AVAIL BIT(28)
1843 +#define BCMA_RES_4314_MACPHY_CLK_AVAIL BIT(29)
1844 +
1845 /* Data for the PMU, if available.
1846 * Check availability with ((struct bcma_chipcommon)->capabilities & BCMA_CC_CAP_PMU)
1847 */
1848 @@ -585,9 +640,16 @@ struct bcma_drv_cc {
1849 spinlock_t gpio_lock;
1850 #ifdef CONFIG_BCMA_DRIVER_GPIO
1851 struct gpio_chip gpio;
1852 + struct irq_domain *irq_domain;
1853 #endif
1854 };
1855
1856 +struct bcma_drv_cc_b {
1857 + struct bcma_device *core;
1858 + u8 setup_done:1;
1859 + void __iomem *mii;
1860 +};
1861 +
1862 /* Register access */
1863 #define bcma_cc_read32(cc, offset) \
1864 bcma_read32((cc)->core, offset)
1865 @@ -643,4 +705,6 @@ extern void bcma_pmu_spuravoid_pllupdate
1866
1867 extern u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc);
1868
1869 +void bcma_chipco_b_mii_write(struct bcma_drv_cc_b *ccb, u32 offset, u32 value);
1870 +
1871 #endif /* LINUX_BCMA_DRIVER_CC_H_ */
1872 --- a/include/linux/bcma/bcma_driver_pci.h
1873 +++ b/include/linux/bcma/bcma_driver_pci.h
1874 @@ -181,10 +181,31 @@ struct pci_dev;
1875
1876 #define BCMA_CORE_PCI_CFG_DEVCTRL 0xd8
1877
1878 +#define BCMA_CORE_PCI_
1879 +
1880 +/* MDIO devices (SERDES modules) */
1881 +#define BCMA_CORE_PCI_MDIO_IEEE0 0x000
1882 +#define BCMA_CORE_PCI_MDIO_IEEE1 0x001
1883 +#define BCMA_CORE_PCI_MDIO_BLK0 0x800
1884 +#define BCMA_CORE_PCI_MDIO_BLK1 0x801
1885 +#define BCMA_CORE_PCI_MDIO_BLK1_MGMT0 0x16
1886 +#define BCMA_CORE_PCI_MDIO_BLK1_MGMT1 0x17
1887 +#define BCMA_CORE_PCI_MDIO_BLK1_MGMT2 0x18
1888 +#define BCMA_CORE_PCI_MDIO_BLK1_MGMT3 0x19
1889 +#define BCMA_CORE_PCI_MDIO_BLK1_MGMT4 0x1A
1890 +#define BCMA_CORE_PCI_MDIO_BLK2 0x802
1891 +#define BCMA_CORE_PCI_MDIO_BLK3 0x803
1892 +#define BCMA_CORE_PCI_MDIO_BLK4 0x804
1893 +#define BCMA_CORE_PCI_MDIO_TXPLL 0x808 /* TXPLL register block idx */
1894 +#define BCMA_CORE_PCI_MDIO_TXCTRL0 0x820
1895 +#define BCMA_CORE_PCI_MDIO_SERDESID 0x831
1896 +#define BCMA_CORE_PCI_MDIO_RXCTRL0 0x840
1897 +
1898 /* PCIE Root Capability Register bits (Host mode only) */
1899 #define BCMA_CORE_PCI_RC_CRS_VISIBILITY 0x0001
1900
1901 struct bcma_drv_pci;
1902 +struct bcma_bus;
1903
1904 #ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE
1905 struct bcma_drv_pci_host {
1906 @@ -219,7 +240,9 @@ struct bcma_drv_pci {
1907 extern void bcma_core_pci_init(struct bcma_drv_pci *pc);
1908 extern int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc,
1909 struct bcma_device *core, bool enable);
1910 -extern void bcma_core_pci_extend_L1timer(struct bcma_drv_pci *pc, bool extend);
1911 +extern void bcma_core_pci_up(struct bcma_bus *bus);
1912 +extern void bcma_core_pci_down(struct bcma_bus *bus);
1913 +extern void bcma_core_pci_power_save(struct bcma_bus *bus, bool up);
1914
1915 extern int bcma_core_pci_pcibios_map_irq(const struct pci_dev *dev);
1916 extern int bcma_core_pci_plat_dev_init(struct pci_dev *dev);
1917 --- /dev/null
1918 +++ b/include/linux/bcma/bcma_driver_pcie2.h
1919 @@ -0,0 +1,158 @@
1920 +#ifndef LINUX_BCMA_DRIVER_PCIE2_H_
1921 +#define LINUX_BCMA_DRIVER_PCIE2_H_
1922 +
1923 +#define BCMA_CORE_PCIE2_CLK_CONTROL 0x0000
1924 +#define PCIE2_CLKC_RST_OE 0x0001 /* When set, drives PCI_RESET out to pin */
1925 +#define PCIE2_CLKC_RST 0x0002 /* Value driven out to pin */
1926 +#define PCIE2_CLKC_SPERST 0x0004 /* SurvivePeRst */
1927 +#define PCIE2_CLKC_DISABLE_L1CLK_GATING 0x0010
1928 +#define PCIE2_CLKC_DLYPERST 0x0100 /* Delay PeRst to CoE Core */
1929 +#define PCIE2_CLKC_DISSPROMLD 0x0200 /* DisableSpromLoadOnPerst */
1930 +#define PCIE2_CLKC_WAKE_MODE_L2 0x1000 /* Wake on L2 */
1931 +#define BCMA_CORE_PCIE2_RC_PM_CONTROL 0x0004
1932 +#define BCMA_CORE_PCIE2_RC_PM_STATUS 0x0008
1933 +#define BCMA_CORE_PCIE2_EP_PM_CONTROL 0x000C
1934 +#define BCMA_CORE_PCIE2_EP_PM_STATUS 0x0010
1935 +#define BCMA_CORE_PCIE2_EP_LTR_CONTROL 0x0014
1936 +#define BCMA_CORE_PCIE2_EP_LTR_STATUS 0x0018
1937 +#define BCMA_CORE_PCIE2_EP_OBFF_STATUS 0x001C
1938 +#define BCMA_CORE_PCIE2_PCIE_ERR_STATUS 0x0020
1939 +#define BCMA_CORE_PCIE2_RC_AXI_CONFIG 0x0100
1940 +#define BCMA_CORE_PCIE2_EP_AXI_CONFIG 0x0104
1941 +#define BCMA_CORE_PCIE2_RXDEBUG_STATUS0 0x0108
1942 +#define BCMA_CORE_PCIE2_RXDEBUG_CONTROL0 0x010C
1943 +#define BCMA_CORE_PCIE2_CONFIGINDADDR 0x0120
1944 +#define BCMA_CORE_PCIE2_CONFIGINDDATA 0x0124
1945 +#define BCMA_CORE_PCIE2_MDIOCONTROL 0x0128
1946 +#define BCMA_CORE_PCIE2_MDIOWRDATA 0x012C
1947 +#define BCMA_CORE_PCIE2_MDIORDDATA 0x0130
1948 +#define BCMA_CORE_PCIE2_DATAINTF 0x0180
1949 +#define BCMA_CORE_PCIE2_D2H_INTRLAZY_0 0x0188
1950 +#define BCMA_CORE_PCIE2_H2D_INTRLAZY_0 0x018c
1951 +#define BCMA_CORE_PCIE2_H2D_INTSTAT_0 0x0190
1952 +#define BCMA_CORE_PCIE2_H2D_INTMASK_0 0x0194
1953 +#define BCMA_CORE_PCIE2_D2H_INTSTAT_0 0x0198
1954 +#define BCMA_CORE_PCIE2_D2H_INTMASK_0 0x019c
1955 +#define BCMA_CORE_PCIE2_LTR_STATE 0x01A0 /* Latency Tolerance Reporting */
1956 +#define PCIE2_LTR_ACTIVE 2
1957 +#define PCIE2_LTR_ACTIVE_IDLE 1
1958 +#define PCIE2_LTR_SLEEP 0
1959 +#define PCIE2_LTR_FINAL_MASK 0x300
1960 +#define PCIE2_LTR_FINAL_SHIFT 8
1961 +#define BCMA_CORE_PCIE2_PWR_INT_STATUS 0x01A4
1962 +#define BCMA_CORE_PCIE2_PWR_INT_MASK 0x01A8
1963 +#define BCMA_CORE_PCIE2_CFG_ADDR 0x01F8
1964 +#define BCMA_CORE_PCIE2_CFG_DATA 0x01FC
1965 +#define BCMA_CORE_PCIE2_SYS_EQ_PAGE 0x0200
1966 +#define BCMA_CORE_PCIE2_SYS_MSI_PAGE 0x0204
1967 +#define BCMA_CORE_PCIE2_SYS_MSI_INTREN 0x0208
1968 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL0 0x0210
1969 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL1 0x0214
1970 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL2 0x0218
1971 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL3 0x021C
1972 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL4 0x0220
1973 +#define BCMA_CORE_PCIE2_SYS_MSI_CTRL5 0x0224
1974 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD0 0x0250
1975 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL0 0x0254
1976 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD1 0x0258
1977 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL1 0x025C
1978 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD2 0x0260
1979 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL2 0x0264
1980 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD3 0x0268
1981 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL3 0x026C
1982 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD4 0x0270
1983 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL4 0x0274
1984 +#define BCMA_CORE_PCIE2_SYS_EQ_HEAD5 0x0278
1985 +#define BCMA_CORE_PCIE2_SYS_EQ_TAIL5 0x027C
1986 +#define BCMA_CORE_PCIE2_SYS_RC_INTX_EN 0x0330
1987 +#define BCMA_CORE_PCIE2_SYS_RC_INTX_CSR 0x0334
1988 +#define BCMA_CORE_PCIE2_SYS_MSI_REQ 0x0340
1989 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR_EN 0x0344
1990 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR_CSR 0x0348
1991 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR0 0x0350
1992 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR1 0x0354
1993 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR2 0x0358
1994 +#define BCMA_CORE_PCIE2_SYS_HOST_INTR3 0x035C
1995 +#define BCMA_CORE_PCIE2_SYS_EP_INT_EN0 0x0360
1996 +#define BCMA_CORE_PCIE2_SYS_EP_INT_EN1 0x0364
1997 +#define BCMA_CORE_PCIE2_SYS_EP_INT_CSR0 0x0370
1998 +#define BCMA_CORE_PCIE2_SYS_EP_INT_CSR1 0x0374
1999 +#define BCMA_CORE_PCIE2_SPROM(wordoffset) (0x0800 + ((wordoffset) * 2))
2000 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_0 0x0C00
2001 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_1 0x0C04
2002 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_2 0x0C08
2003 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_3 0x0C0C
2004 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_4 0x0C10
2005 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_5 0x0C14
2006 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_6 0x0C18
2007 +#define BCMA_CORE_PCIE2_FUNC0_IMAP0_7 0x0C1C
2008 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_0 0x0C20
2009 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_1 0x0C24
2010 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_2 0x0C28
2011 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_3 0x0C2C
2012 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_4 0x0C30
2013 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_5 0x0C34
2014 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_6 0x0C38
2015 +#define BCMA_CORE_PCIE2_FUNC1_IMAP0_7 0x0C3C
2016 +#define BCMA_CORE_PCIE2_FUNC0_IMAP1 0x0C80
2017 +#define BCMA_CORE_PCIE2_FUNC1_IMAP1 0x0C88
2018 +#define BCMA_CORE_PCIE2_FUNC0_IMAP2 0x0CC0
2019 +#define BCMA_CORE_PCIE2_FUNC1_IMAP2 0x0CC8
2020 +#define BCMA_CORE_PCIE2_IARR0_LOWER 0x0D00
2021 +#define BCMA_CORE_PCIE2_IARR0_UPPER 0x0D04
2022 +#define BCMA_CORE_PCIE2_IARR1_LOWER 0x0D08
2023 +#define BCMA_CORE_PCIE2_IARR1_UPPER 0x0D0C
2024 +#define BCMA_CORE_PCIE2_IARR2_LOWER 0x0D10
2025 +#define BCMA_CORE_PCIE2_IARR2_UPPER 0x0D14
2026 +#define BCMA_CORE_PCIE2_OARR0 0x0D20
2027 +#define BCMA_CORE_PCIE2_OARR1 0x0D28
2028 +#define BCMA_CORE_PCIE2_OARR2 0x0D30
2029 +#define BCMA_CORE_PCIE2_OMAP0_LOWER 0x0D40
2030 +#define BCMA_CORE_PCIE2_OMAP0_UPPER 0x0D44
2031 +#define BCMA_CORE_PCIE2_OMAP1_LOWER 0x0D48
2032 +#define BCMA_CORE_PCIE2_OMAP1_UPPER 0x0D4C
2033 +#define BCMA_CORE_PCIE2_OMAP2_LOWER 0x0D50
2034 +#define BCMA_CORE_PCIE2_OMAP2_UPPER 0x0D54
2035 +#define BCMA_CORE_PCIE2_FUNC1_IARR1_SIZE 0x0D58
2036 +#define BCMA_CORE_PCIE2_FUNC1_IARR2_SIZE 0x0D5C
2037 +#define BCMA_CORE_PCIE2_MEM_CONTROL 0x0F00
2038 +#define BCMA_CORE_PCIE2_MEM_ECC_ERRLOG0 0x0F04
2039 +#define BCMA_CORE_PCIE2_MEM_ECC_ERRLOG1 0x0F08
2040 +#define BCMA_CORE_PCIE2_LINK_STATUS 0x0F0C
2041 +#define BCMA_CORE_PCIE2_STRAP_STATUS 0x0F10
2042 +#define BCMA_CORE_PCIE2_RESET_STATUS 0x0F14
2043 +#define BCMA_CORE_PCIE2_RESETEN_IN_LINKDOWN 0x0F18
2044 +#define BCMA_CORE_PCIE2_MISC_INTR_EN 0x0F1C
2045 +#define BCMA_CORE_PCIE2_TX_DEBUG_CFG 0x0F20
2046 +#define BCMA_CORE_PCIE2_MISC_CONFIG 0x0F24
2047 +#define BCMA_CORE_PCIE2_MISC_STATUS 0x0F28
2048 +#define BCMA_CORE_PCIE2_INTR_EN 0x0F30
2049 +#define BCMA_CORE_PCIE2_INTR_CLEAR 0x0F34
2050 +#define BCMA_CORE_PCIE2_INTR_STATUS 0x0F38
2051 +
2052 +/* PCIE gen2 config regs */
2053 +#define PCIE2_INTSTATUS 0x090
2054 +#define PCIE2_INTMASK 0x094
2055 +#define PCIE2_SBMBX 0x098
2056 +
2057 +#define PCIE2_PMCR_REFUP 0x1814 /* Trefup time */
2058 +
2059 +#define PCIE2_CAP_DEVSTSCTRL2_OFFSET 0xD4
2060 +#define PCIE2_CAP_DEVSTSCTRL2_LTRENAB 0x400
2061 +#define PCIE2_PVT_REG_PM_CLK_PERIOD 0x184c
2062 +
2063 +struct bcma_drv_pcie2 {
2064 + struct bcma_device *core;
2065 +};
2066 +
2067 +#define pcie2_read16(pcie2, offset) bcma_read16((pcie2)->core, offset)
2068 +#define pcie2_read32(pcie2, offset) bcma_read32((pcie2)->core, offset)
2069 +#define pcie2_write16(pcie2, offset, val) bcma_write16((pcie2)->core, offset, val)
2070 +#define pcie2_write32(pcie2, offset, val) bcma_write32((pcie2)->core, offset, val)
2071 +
2072 +#define pcie2_set32(pcie2, offset, set) bcma_set32((pcie2)->core, offset, set)
2073 +#define pcie2_mask32(pcie2, offset, mask) bcma_mask32((pcie2)->core, offset, mask)
2074 +
2075 +void bcma_core_pcie2_init(struct bcma_drv_pcie2 *pcie2);
2076 +
2077 +#endif /* LINUX_BCMA_DRIVER_PCIE2_H_ */
2078 --- a/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
2079 +++ b/drivers/net/wireless/brcm80211/brcmsmac/aiutils.c
2080 @@ -679,27 +679,6 @@ bool ai_clkctl_cc(struct si_pub *sih, en
2081 return mode == BCMA_CLKMODE_FAST;
2082 }
2083
2084 -void ai_pci_up(struct si_pub *sih)
2085 -{
2086 - struct si_info *sii;
2087 -
2088 - sii = container_of(sih, struct si_info, pub);
2089 -
2090 - if (sii->icbus->hosttype == BCMA_HOSTTYPE_PCI)
2091 - bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci[0], true);
2092 -}
2093 -
2094 -/* Unconfigure and/or apply various WARs when going down */
2095 -void ai_pci_down(struct si_pub *sih)
2096 -{
2097 - struct si_info *sii;
2098 -
2099 - sii = container_of(sih, struct si_info, pub);
2100 -
2101 - if (sii->icbus->hosttype == BCMA_HOSTTYPE_PCI)
2102 - bcma_core_pci_extend_L1timer(&sii->icbus->drv_pci[0], false);
2103 -}
2104 -
2105 /* Enable BT-COEX & Ex-PA for 4313 */
2106 void ai_epa_4313war(struct si_pub *sih)
2107 {
2108 --- a/drivers/net/wireless/brcm80211/brcmsmac/aiutils.h
2109 +++ b/drivers/net/wireless/brcm80211/brcmsmac/aiutils.h
2110 @@ -183,9 +183,6 @@ extern u16 ai_clkctl_fast_pwrup_delay(st
2111 extern bool ai_clkctl_cc(struct si_pub *sih, enum bcma_clkmode mode);
2112 extern bool ai_deviceremoved(struct si_pub *sih);
2113
2114 -extern void ai_pci_down(struct si_pub *sih);
2115 -extern void ai_pci_up(struct si_pub *sih);
2116 -
2117 /* Enable Ex-PA for 4313 */
2118 extern void ai_epa_4313war(struct si_pub *sih);
2119
2120 --- a/drivers/net/wireless/brcm80211/brcmsmac/main.c
2121 +++ b/drivers/net/wireless/brcm80211/brcmsmac/main.c
2122 @@ -4667,7 +4667,7 @@ static int brcms_b_attach(struct brcms_c
2123 brcms_c_coredisable(wlc_hw);
2124
2125 /* Match driver "down" state */
2126 - ai_pci_down(wlc_hw->sih);
2127 + bcma_core_pci_down(wlc_hw->d11core->bus);
2128
2129 /* turn off pll and xtal to match driver "down" state */
2130 brcms_b_xtal(wlc_hw, OFF);
2131 @@ -5010,12 +5010,12 @@ static int brcms_b_up_prep(struct brcms_
2132 */
2133 if (brcms_b_radio_read_hwdisabled(wlc_hw)) {
2134 /* put SB PCI in down state again */
2135 - ai_pci_down(wlc_hw->sih);
2136 + bcma_core_pci_down(wlc_hw->d11core->bus);
2137 brcms_b_xtal(wlc_hw, OFF);
2138 return -ENOMEDIUM;
2139 }
2140
2141 - ai_pci_up(wlc_hw->sih);
2142 + bcma_core_pci_up(wlc_hw->d11core->bus);
2143
2144 /* reset the d11 core */
2145 brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
2146 @@ -5212,7 +5212,7 @@ static int brcms_b_down_finish(struct br
2147
2148 /* turn off primary xtal and pll */
2149 if (!wlc_hw->noreset) {
2150 - ai_pci_down(wlc_hw->sih);
2151 + bcma_core_pci_down(wlc_hw->d11core->bus);
2152 brcms_b_xtal(wlc_hw, OFF);
2153 }
2154 }
2155 --- a/drivers/bcma/driver_mips.c
2156 +++ b/drivers/bcma/driver_mips.c
2157 @@ -21,6 +21,14 @@
2158 #include <linux/serial_reg.h>
2159 #include <linux/time.h>
2160
2161 +enum bcma_boot_dev {
2162 + BCMA_BOOT_DEV_UNK = 0,
2163 + BCMA_BOOT_DEV_ROM,
2164 + BCMA_BOOT_DEV_PARALLEL,
2165 + BCMA_BOOT_DEV_SERIAL,
2166 + BCMA_BOOT_DEV_NAND,
2167 +};
2168 +
2169 static const char * const part_probes[] = { "bcm47xxpart", NULL };
2170
2171 static struct physmap_flash_data bcma_pflash_data = {
2172 @@ -229,11 +237,51 @@ u32 bcma_cpu_clock(struct bcma_drv_mips
2173 }
2174 EXPORT_SYMBOL(bcma_cpu_clock);
2175
2176 +static enum bcma_boot_dev bcma_boot_dev(struct bcma_bus *bus)
2177 +{
2178 + struct bcma_drv_cc *cc = &bus->drv_cc;
2179 + u8 cc_rev = cc->core->id.rev;
2180 +
2181 + if (cc_rev == 42) {
2182 + struct bcma_device *core;
2183 +
2184 + core = bcma_find_core(bus, BCMA_CORE_NS_ROM);
2185 + if (core) {
2186 + switch (bcma_aread32(core, BCMA_IOST) &
2187 + BCMA_NS_ROM_IOST_BOOT_DEV_MASK) {
2188 + case BCMA_NS_ROM_IOST_BOOT_DEV_NOR:
2189 + return BCMA_BOOT_DEV_SERIAL;
2190 + case BCMA_NS_ROM_IOST_BOOT_DEV_NAND:
2191 + return BCMA_BOOT_DEV_NAND;
2192 + case BCMA_NS_ROM_IOST_BOOT_DEV_ROM:
2193 + default:
2194 + return BCMA_BOOT_DEV_ROM;
2195 + }
2196 + }
2197 + } else {
2198 + if (cc_rev == 38) {
2199 + if (cc->status & BCMA_CC_CHIPST_5357_NAND_BOOT)
2200 + return BCMA_BOOT_DEV_NAND;
2201 + else if (cc->status & BIT(5))
2202 + return BCMA_BOOT_DEV_ROM;
2203 + }
2204 +
2205 + if ((cc->capabilities & BCMA_CC_CAP_FLASHT) ==
2206 + BCMA_CC_FLASHT_PARA)
2207 + return BCMA_BOOT_DEV_PARALLEL;
2208 + else
2209 + return BCMA_BOOT_DEV_SERIAL;
2210 + }
2211 +
2212 + return BCMA_BOOT_DEV_SERIAL;
2213 +}
2214 +
2215 static void bcma_core_mips_flash_detect(struct bcma_drv_mips *mcore)
2216 {
2217 struct bcma_bus *bus = mcore->core->bus;
2218 struct bcma_drv_cc *cc = &bus->drv_cc;
2219 struct bcma_pflash *pflash = &cc->pflash;
2220 + enum bcma_boot_dev boot_dev;
2221
2222 switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
2223 case BCMA_CC_FLASHT_STSER:
2224 @@ -269,6 +317,20 @@ static void bcma_core_mips_flash_detect(
2225 bcma_nflash_init(cc);
2226 }
2227 }
2228 +
2229 + /* Determine flash type this SoC boots from */
2230 + boot_dev = bcma_boot_dev(bus);
2231 + switch (boot_dev) {
2232 + case BCMA_BOOT_DEV_PARALLEL:
2233 + case BCMA_BOOT_DEV_SERIAL:
2234 + /* TODO: Init NVRAM using BCMA_SOC_FLASH2 window */
2235 + break;
2236 + case BCMA_BOOT_DEV_NAND:
2237 + /* TODO: Init NVRAM using BCMA_SOC_FLASH1 window */
2238 + break;
2239 + default:
2240 + break;
2241 + }
2242 }
2243
2244 void bcma_core_mips_early_init(struct bcma_drv_mips *mcore)
2245 --- a/drivers/bcma/host_soc.c
2246 +++ b/drivers/bcma/host_soc.c
2247 @@ -7,6 +7,9 @@
2248
2249 #include "bcma_private.h"
2250 #include "scan.h"
2251 +#include <linux/slab.h>
2252 +#include <linux/module.h>
2253 +#include <linux/of_address.h>
2254 #include <linux/bcma/bcma.h>
2255 #include <linux/bcma/bcma_soc.h>
2256
2257 @@ -134,12 +137,16 @@ static void bcma_host_soc_block_write(st
2258
2259 static u32 bcma_host_soc_aread32(struct bcma_device *core, u16 offset)
2260 {
2261 + if (WARN_ONCE(!core->io_wrap, "Accessed core has no wrapper/agent\n"))
2262 + return ~0;
2263 return readl(core->io_wrap + offset);
2264 }
2265
2266 static void bcma_host_soc_awrite32(struct bcma_device *core, u16 offset,
2267 u32 value)
2268 {
2269 + if (WARN_ONCE(!core->io_wrap, "Accessed core has no wrapper/agent\n"))
2270 + return;
2271 writel(value, core->io_wrap + offset);
2272 }
2273
2274 @@ -161,7 +168,6 @@ static const struct bcma_host_ops bcma_h
2275 int __init bcma_host_soc_register(struct bcma_soc *soc)
2276 {
2277 struct bcma_bus *bus = &soc->bus;
2278 - int err;
2279
2280 /* iomap only first core. We have to read some register on this core
2281 * to scan the bus.
2282 @@ -173,11 +179,100 @@ int __init bcma_host_soc_register(struct
2283 /* Host specific */
2284 bus->hosttype = BCMA_HOSTTYPE_SOC;
2285 bus->ops = &bcma_host_soc_ops;
2286 + bus->host_pdev = NULL;
2287
2288 - /* Register */
2289 + /* Initialize struct, detect chip */
2290 + bcma_init_bus(bus);
2291 +
2292 + return 0;
2293 +}
2294 +
2295 +int __init bcma_host_soc_init(struct bcma_soc *soc)
2296 +{
2297 + struct bcma_bus *bus = &soc->bus;
2298 + int err;
2299 +
2300 + /* Scan bus and initialize it */
2301 err = bcma_bus_early_register(bus, &soc->core_cc, &soc->core_mips);
2302 if (err)
2303 iounmap(bus->mmio);
2304
2305 return err;
2306 }
2307 +
2308 +#ifdef CONFIG_OF
2309 +static int bcma_host_soc_probe(struct platform_device *pdev)
2310 +{
2311 + struct device *dev = &pdev->dev;
2312 + struct device_node *np = dev->of_node;
2313 + struct bcma_bus *bus;
2314 + int err;
2315 +
2316 + /* Alloc */
2317 + bus = devm_kzalloc(dev, sizeof(*bus), GFP_KERNEL);
2318 + if (!bus)
2319 + return -ENOMEM;
2320 +
2321 + /* Map MMIO */
2322 + bus->mmio = of_iomap(np, 0);
2323 + if (!bus->mmio)
2324 + return -ENOMEM;
2325 +
2326 + /* Host specific */
2327 + bus->hosttype = BCMA_HOSTTYPE_SOC;
2328 + bus->ops = &bcma_host_soc_ops;
2329 + bus->host_pdev = pdev;
2330 +
2331 + /* Initialize struct, detect chip */
2332 + bcma_init_bus(bus);
2333 +
2334 + /* Register */
2335 + err = bcma_bus_register(bus);
2336 + if (err)
2337 + goto err_unmap_mmio;
2338 +
2339 + platform_set_drvdata(pdev, bus);
2340 +
2341 + return err;
2342 +
2343 +err_unmap_mmio:
2344 + iounmap(bus->mmio);
2345 + return err;
2346 +}
2347 +
2348 +static int bcma_host_soc_remove(struct platform_device *pdev)
2349 +{
2350 + struct bcma_bus *bus = platform_get_drvdata(pdev);
2351 +
2352 + bcma_bus_unregister(bus);
2353 + iounmap(bus->mmio);
2354 + platform_set_drvdata(pdev, NULL);
2355 +
2356 + return 0;
2357 +}
2358 +
2359 +static const struct of_device_id bcma_host_soc_of_match[] = {
2360 + { .compatible = "brcm,bus-axi", },
2361 + {},
2362 +};
2363 +MODULE_DEVICE_TABLE(of, bcma_host_soc_of_match);
2364 +
2365 +static struct platform_driver bcma_host_soc_driver = {
2366 + .driver = {
2367 + .name = "bcma-host-soc",
2368 + .of_match_table = bcma_host_soc_of_match,
2369 + },
2370 + .probe = bcma_host_soc_probe,
2371 + .remove = bcma_host_soc_remove,
2372 +};
2373 +
2374 +int __init bcma_host_soc_register_driver(void)
2375 +{
2376 + return platform_driver_register(&bcma_host_soc_driver);
2377 +}
2378 +
2379 +void __exit bcma_host_soc_unregister_driver(void)
2380 +{
2381 + platform_driver_unregister(&bcma_host_soc_driver);
2382 +}
2383 +#endif /* CONFIG_OF */
2384 --- a/include/linux/bcma/bcma_regs.h
2385 +++ b/include/linux/bcma/bcma_regs.h
2386 @@ -39,6 +39,11 @@
2387 #define BCMA_RESET_CTL_RESET 0x0001
2388 #define BCMA_RESET_ST 0x0804
2389
2390 +#define BCMA_NS_ROM_IOST_BOOT_DEV_MASK 0x0003
2391 +#define BCMA_NS_ROM_IOST_BOOT_DEV_NOR 0x0000
2392 +#define BCMA_NS_ROM_IOST_BOOT_DEV_NAND 0x0001
2393 +#define BCMA_NS_ROM_IOST_BOOT_DEV_ROM 0x0002
2394 +
2395 /* BCMA PCI config space registers. */
2396 #define BCMA_PCI_PMCSR 0x44
2397 #define BCMA_PCI_PE 0x100
2398 --- a/drivers/usb/host/bcma-hcd.c
2399 +++ b/drivers/usb/host/bcma-hcd.c
2400 @@ -238,7 +238,7 @@ static int bcma_hcd_probe(struct bcma_de
2401 bcma_hcd_init_chip(dev);
2402
2403 /* In AI chips EHCI is addrspace 0, OHCI is 1 */
2404 - ohci_addr = dev->addr1;
2405 + ohci_addr = dev->addr_s[0];
2406 if ((chipinfo->id == 0x5357 || chipinfo->id == 0x4749)
2407 && chipinfo->rev == 0)
2408 ohci_addr = 0x18009000;
2409 --- /dev/null
2410 +++ b/drivers/bcma/driver_chipcommon_b.c
2411 @@ -0,0 +1,61 @@
2412 +/*
2413 + * Broadcom specific AMBA
2414 + * ChipCommon B Unit driver
2415 + *
2416 + * Copyright 2014, Hauke Mehrtens <hauke@hauke-m.de>
2417 + *
2418 + * Licensed under the GNU/GPL. See COPYING for details.
2419 + */
2420 +
2421 +#include "bcma_private.h"
2422 +#include <linux/export.h>
2423 +#include <linux/bcma/bcma.h>
2424 +
2425 +static bool bcma_wait_reg(struct bcma_bus *bus, void __iomem *addr, u32 mask,
2426 + u32 value, int timeout)
2427 +{
2428 + unsigned long deadline = jiffies + timeout;
2429 + u32 val;
2430 +
2431 + do {
2432 + val = readl(addr);
2433 + if ((val & mask) == value)
2434 + return true;
2435 + cpu_relax();
2436 + udelay(10);
2437 + } while (!time_after_eq(jiffies, deadline));
2438 +
2439 + bcma_err(bus, "Timeout waiting for register %p\n", addr);
2440 +
2441 + return false;
2442 +}
2443 +
2444 +void bcma_chipco_b_mii_write(struct bcma_drv_cc_b *ccb, u32 offset, u32 value)
2445 +{
2446 + struct bcma_bus *bus = ccb->core->bus;
2447 +
2448 + writel(offset, ccb->mii + 0x00);
2449 + bcma_wait_reg(bus, ccb->mii + 0x00, 0x0100, 0x0000, 100);
2450 + writel(value, ccb->mii + 0x04);
2451 + bcma_wait_reg(bus, ccb->mii + 0x00, 0x0100, 0x0000, 100);
2452 +}
2453 +EXPORT_SYMBOL_GPL(bcma_chipco_b_mii_write);
2454 +
2455 +int bcma_core_chipcommon_b_init(struct bcma_drv_cc_b *ccb)
2456 +{
2457 + if (ccb->setup_done)
2458 + return 0;
2459 +
2460 + ccb->setup_done = 1;
2461 + ccb->mii = ioremap_nocache(ccb->core->addr_s[1], BCMA_CORE_SIZE);
2462 + if (!ccb->mii)
2463 + return -ENOMEM;
2464 +
2465 + return 0;
2466 +}
2467 +
2468 +void bcma_core_chipcommon_b_free(struct bcma_drv_cc_b *ccb)
2469 +{
2470 + if (ccb->mii)
2471 + iounmap(ccb->mii);
2472 +}
2473 --- a/include/linux/bcma/bcma_soc.h
2474 +++ b/include/linux/bcma/bcma_soc.h
2475 @@ -10,6 +10,7 @@ struct bcma_soc {
2476 };
2477
2478 int __init bcma_host_soc_register(struct bcma_soc *soc);
2479 +int __init bcma_host_soc_init(struct bcma_soc *soc);
2480
2481 int bcma_bus_register(struct bcma_bus *bus);
2482
2483 --- a/arch/mips/bcm47xx/setup.c
2484 +++ b/arch/mips/bcm47xx/setup.c
2485 @@ -194,6 +194,10 @@ static void __init bcm47xx_register_bcma
2486
2487 err = bcma_host_soc_register(&bcm47xx_bus.bcma);
2488 if (err)
2489 + panic("Failed to register BCMA bus (err %d)", err);
2490 +
2491 + err = bcma_host_soc_init(&bcm47xx_bus.bcma);
2492 + if (err)
2493 panic("Failed to initialize BCMA bus (err %d)", err);
2494
2495 bcm47xx_fill_bcma_boardinfo(&bcm47xx_bus.bcma.bus.boardinfo, NULL);
2496 --- /dev/null
2497 +++ b/Documentation/devicetree/bindings/bus/bcma.txt
2498 @@ -0,0 +1,32 @@
2499 +Driver for ARM AXI Bus with Broadcom Plugins (bcma)
2500 +
2501 +Required properties:
2502 +
2503 +- compatible : brcm,bus-axi
2504 +
2505 +- reg : iomem address range of chipcommon core
2506 +
2507 +The cores on the AXI bus are automatically detected by bcma with the
2508 +memory ranges they are using and they get registered afterwards.
2509 +
2510 +The top-level axi bus may contain children representing attached cores
2511 +(devices). This is needed since some hardware details can't be auto
2512 +detected (e.g. IRQ numbers). Also some of the cores may be responsible
2513 +for extra things, e.g. ChipCommon providing access to the GPIO chip.
2514 +
2515 +Example:
2516 +
2517 + axi@18000000 {
2518 + compatible = "brcm,bus-axi";
2519 + reg = <0x18000000 0x1000>;
2520 + ranges = <0x00000000 0x18000000 0x00100000>;
2521 + #address-cells = <1>;
2522 + #size-cells = <1>;
2523 +
2524 + chipcommon {
2525 + reg = <0x00000000 0x1000>;
2526 +
2527 + gpio-controller;
2528 + #gpio-cells = <2>;
2529 + };
2530 + };
OpenWrt Source Repository