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10c70abbbb6094dbd704486426866a238880cd9b
[openwrt/svn-archive/archive.git] / target / linux / generic / patches-3.3 / 020-ssb_update.patch
1 --- a/drivers/ssb/b43_pci_bridge.c
2 +++ b/drivers/ssb/b43_pci_bridge.c
3 @@ -29,11 +29,14 @@ static const struct pci_device_id b43_pc
4 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4319) },
5 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4320) },
6 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4321) },
7 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4322) },
8 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 43222) },
9 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4324) },
10 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4325) },
11 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4328) },
12 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x4329) },
13 { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x432b) },
14 + { PCI_DEVICE(PCI_VENDOR_ID_BROADCOM, 0x432c) },
15 { 0, },
16 };
17 MODULE_DEVICE_TABLE(pci, b43_pci_bridge_tbl);
18 --- a/drivers/ssb/driver_chipcommon_pmu.c
19 +++ b/drivers/ssb/driver_chipcommon_pmu.c
20 @@ -13,6 +13,9 @@
21 #include <linux/ssb/ssb_driver_chipcommon.h>
22 #include <linux/delay.h>
23 #include <linux/export.h>
24 +#ifdef CONFIG_BCM47XX
25 +#include <asm/mach-bcm47xx/nvram.h>
26 +#endif
27
28 #include "ssb_private.h"
29
30 @@ -92,10 +95,6 @@ static void ssb_pmu0_pllinit_r0(struct s
31 u32 pmuctl, tmp, pllctl;
32 unsigned int i;
33
34 - if ((bus->chip_id == 0x5354) && !crystalfreq) {
35 - /* The 5354 crystal freq is 25MHz */
36 - crystalfreq = 25000;
37 - }
38 if (crystalfreq)
39 e = pmu0_plltab_find_entry(crystalfreq);
40 if (!e)
41 @@ -321,7 +320,11 @@ static void ssb_pmu_pll_init(struct ssb_
42 u32 crystalfreq = 0; /* in kHz. 0 = keep default freq. */
43
44 if (bus->bustype == SSB_BUSTYPE_SSB) {
45 - /* TODO: The user may override the crystal frequency. */
46 +#ifdef CONFIG_BCM47XX
47 + char buf[20];
48 + if (nvram_getenv("xtalfreq", buf, sizeof(buf)) >= 0)
49 + crystalfreq = simple_strtoul(buf, NULL, 0);
50 +#endif
51 }
52
53 switch (bus->chip_id) {
54 @@ -330,7 +333,11 @@ static void ssb_pmu_pll_init(struct ssb_
55 ssb_pmu1_pllinit_r0(cc, crystalfreq);
56 break;
57 case 0x4328:
58 + ssb_pmu0_pllinit_r0(cc, crystalfreq);
59 + break;
60 case 0x5354:
61 + if (crystalfreq == 0)
62 + crystalfreq = 25000;
63 ssb_pmu0_pllinit_r0(cc, crystalfreq);
64 break;
65 case 0x4322:
66 @@ -607,3 +614,34 @@ void ssb_pmu_set_ldo_paref(struct ssb_ch
67
68 EXPORT_SYMBOL(ssb_pmu_set_ldo_voltage);
69 EXPORT_SYMBOL(ssb_pmu_set_ldo_paref);
70 +
71 +u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc)
72 +{
73 + struct ssb_bus *bus = cc->dev->bus;
74 +
75 + switch (bus->chip_id) {
76 + case 0x5354:
77 + /* 5354 chip uses a non programmable PLL of frequency 240MHz */
78 + return 240000000;
79 + default:
80 + ssb_printk(KERN_ERR PFX
81 + "ERROR: PMU cpu clock unknown for device %04X\n",
82 + bus->chip_id);
83 + return 0;
84 + }
85 +}
86 +
87 +u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc)
88 +{
89 + struct ssb_bus *bus = cc->dev->bus;
90 +
91 + switch (bus->chip_id) {
92 + case 0x5354:
93 + return 120000000;
94 + default:
95 + ssb_printk(KERN_ERR PFX
96 + "ERROR: PMU controlclock unknown for device %04X\n",
97 + bus->chip_id);
98 + return 0;
99 + }
100 +}
101 --- a/drivers/ssb/driver_mipscore.c
102 +++ b/drivers/ssb/driver_mipscore.c
103 @@ -190,16 +190,32 @@ static void ssb_mips_flash_detect(struct
104 {
105 struct ssb_bus *bus = mcore->dev->bus;
106
107 - mcore->flash_buswidth = 2;
108 - if (bus->chipco.dev) {
109 - mcore->flash_window = 0x1c000000;
110 - mcore->flash_window_size = 0x02000000;
111 + /* When there is no chipcommon on the bus there is 4MB flash */
112 + if (!bus->chipco.dev) {
113 + mcore->pflash.present = true;
114 + mcore->pflash.buswidth = 2;
115 + mcore->pflash.window = SSB_FLASH1;
116 + mcore->pflash.window_size = SSB_FLASH1_SZ;
117 + return;
118 + }
119 +
120 + /* There is ChipCommon, so use it to read info about flash */
121 + switch (bus->chipco.capabilities & SSB_CHIPCO_CAP_FLASHT) {
122 + case SSB_CHIPCO_FLASHT_STSER:
123 + case SSB_CHIPCO_FLASHT_ATSER:
124 + pr_err("Serial flash not supported\n");
125 + break;
126 + case SSB_CHIPCO_FLASHT_PARA:
127 + pr_debug("Found parallel flash\n");
128 + mcore->pflash.present = true;
129 + mcore->pflash.window = SSB_FLASH2;
130 + mcore->pflash.window_size = SSB_FLASH2_SZ;
131 if ((ssb_read32(bus->chipco.dev, SSB_CHIPCO_FLASH_CFG)
132 & SSB_CHIPCO_CFG_DS16) == 0)
133 - mcore->flash_buswidth = 1;
134 - } else {
135 - mcore->flash_window = 0x1fc00000;
136 - mcore->flash_window_size = 0x00400000;
137 + mcore->pflash.buswidth = 1;
138 + else
139 + mcore->pflash.buswidth = 2;
140 + break;
141 }
142 }
143
144 @@ -208,6 +224,9 @@ u32 ssb_cpu_clock(struct ssb_mipscore *m
145 struct ssb_bus *bus = mcore->dev->bus;
146 u32 pll_type, n, m, rate = 0;
147
148 + if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
149 + return ssb_pmu_get_cpu_clock(&bus->chipco);
150 +
151 if (bus->extif.dev) {
152 ssb_extif_get_clockcontrol(&bus->extif, &pll_type, &n, &m);
153 } else if (bus->chipco.dev) {
154 --- a/drivers/ssb/main.c
155 +++ b/drivers/ssb/main.c
156 @@ -140,19 +140,6 @@ static void ssb_device_put(struct ssb_de
157 put_device(dev->dev);
158 }
159
160 -static inline struct ssb_driver *ssb_driver_get(struct ssb_driver *drv)
161 -{
162 - if (drv)
163 - get_driver(&drv->drv);
164 - return drv;
165 -}
166 -
167 -static inline void ssb_driver_put(struct ssb_driver *drv)
168 -{
169 - if (drv)
170 - put_driver(&drv->drv);
171 -}
172 -
173 static int ssb_device_resume(struct device *dev)
174 {
175 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
176 @@ -250,11 +237,9 @@ int ssb_devices_freeze(struct ssb_bus *b
177 ssb_device_put(sdev);
178 continue;
179 }
180 - sdrv = ssb_driver_get(drv_to_ssb_drv(sdev->dev->driver));
181 - if (!sdrv || SSB_WARN_ON(!sdrv->remove)) {
182 - ssb_device_put(sdev);
183 + sdrv = drv_to_ssb_drv(sdev->dev->driver);
184 + if (SSB_WARN_ON(!sdrv->remove))
185 continue;
186 - }
187 sdrv->remove(sdev);
188 ctx->device_frozen[i] = 1;
189 }
190 @@ -293,7 +278,6 @@ int ssb_devices_thaw(struct ssb_freeze_c
191 dev_name(sdev->dev));
192 result = err;
193 }
194 - ssb_driver_put(sdrv);
195 ssb_device_put(sdev);
196 }
197
198 @@ -1094,6 +1078,9 @@ u32 ssb_clockspeed(struct ssb_bus *bus)
199 u32 plltype;
200 u32 clkctl_n, clkctl_m;
201
202 + if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
203 + return ssb_pmu_get_controlclock(&bus->chipco);
204 +
205 if (ssb_extif_available(&bus->extif))
206 ssb_extif_get_clockcontrol(&bus->extif, &plltype,
207 &clkctl_n, &clkctl_m);
208 --- a/drivers/ssb/pci.c
209 +++ b/drivers/ssb/pci.c
210 @@ -178,6 +178,18 @@ err_pci:
211 #define SPEX(_outvar, _offset, _mask, _shift) \
212 SPEX16(_outvar, _offset, _mask, _shift)
213
214 +#define SPEX_ARRAY8(_field, _offset, _mask, _shift) \
215 + do { \
216 + SPEX(_field[0], _offset + 0, _mask, _shift); \
217 + SPEX(_field[1], _offset + 2, _mask, _shift); \
218 + SPEX(_field[2], _offset + 4, _mask, _shift); \
219 + SPEX(_field[3], _offset + 6, _mask, _shift); \
220 + SPEX(_field[4], _offset + 8, _mask, _shift); \
221 + SPEX(_field[5], _offset + 10, _mask, _shift); \
222 + SPEX(_field[6], _offset + 12, _mask, _shift); \
223 + SPEX(_field[7], _offset + 14, _mask, _shift); \
224 + } while (0)
225 +
226
227 static inline u8 ssb_crc8(u8 crc, u8 data)
228 {
229 @@ -331,7 +343,6 @@ static void sprom_extract_r123(struct ss
230 {
231 int i;
232 u16 v;
233 - s8 gain;
234 u16 loc[3];
235
236 if (out->revision == 3) /* rev 3 moved MAC */
237 @@ -361,8 +372,9 @@ static void sprom_extract_r123(struct ss
238 SPEX(et0mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET0M, 14);
239 SPEX(et1mdcport, SSB_SPROM1_ETHPHY, SSB_SPROM1_ETHPHY_ET1M, 15);
240 SPEX(board_rev, SSB_SPROM1_BINF, SSB_SPROM1_BINF_BREV, 0);
241 - SPEX(country_code, SSB_SPROM1_BINF, SSB_SPROM1_BINF_CCODE,
242 - SSB_SPROM1_BINF_CCODE_SHIFT);
243 + if (out->revision == 1)
244 + SPEX(country_code, SSB_SPROM1_BINF, SSB_SPROM1_BINF_CCODE,
245 + SSB_SPROM1_BINF_CCODE_SHIFT);
246 SPEX(ant_available_a, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTA,
247 SSB_SPROM1_BINF_ANTA_SHIFT);
248 SPEX(ant_available_bg, SSB_SPROM1_BINF, SSB_SPROM1_BINF_ANTBG,
249 @@ -388,22 +400,16 @@ static void sprom_extract_r123(struct ss
250 SPEX(boardflags_lo, SSB_SPROM1_BFLLO, 0xFFFF, 0);
251 if (out->revision >= 2)
252 SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0);
253 + SPEX(alpha2[0], SSB_SPROM1_CCODE, 0xff00, 8);
254 + SPEX(alpha2[1], SSB_SPROM1_CCODE, 0x00ff, 0);
255
256 /* Extract the antenna gain values. */
257 - gain = r123_extract_antgain(out->revision, in,
258 - SSB_SPROM1_AGAIN_BG,
259 - SSB_SPROM1_AGAIN_BG_SHIFT);
260 - out->antenna_gain.ghz24.a0 = gain;
261 - out->antenna_gain.ghz24.a1 = gain;
262 - out->antenna_gain.ghz24.a2 = gain;
263 - out->antenna_gain.ghz24.a3 = gain;
264 - gain = r123_extract_antgain(out->revision, in,
265 - SSB_SPROM1_AGAIN_A,
266 - SSB_SPROM1_AGAIN_A_SHIFT);
267 - out->antenna_gain.ghz5.a0 = gain;
268 - out->antenna_gain.ghz5.a1 = gain;
269 - out->antenna_gain.ghz5.a2 = gain;
270 - out->antenna_gain.ghz5.a3 = gain;
271 + out->antenna_gain.a0 = r123_extract_antgain(out->revision, in,
272 + SSB_SPROM1_AGAIN_BG,
273 + SSB_SPROM1_AGAIN_BG_SHIFT);
274 + out->antenna_gain.a1 = r123_extract_antgain(out->revision, in,
275 + SSB_SPROM1_AGAIN_A,
276 + SSB_SPROM1_AGAIN_A_SHIFT);
277 }
278
279 /* Revs 4 5 and 8 have partially shared layout */
280 @@ -464,14 +470,17 @@ static void sprom_extract_r45(struct ssb
281 SPEX(et0phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET0A, 0);
282 SPEX(et1phyaddr, SSB_SPROM4_ETHPHY, SSB_SPROM4_ETHPHY_ET1A,
283 SSB_SPROM4_ETHPHY_ET1A_SHIFT);
284 + SPEX(board_rev, SSB_SPROM4_BOARDREV, 0xFFFF, 0);
285 if (out->revision == 4) {
286 - SPEX(country_code, SSB_SPROM4_CCODE, 0xFFFF, 0);
287 + SPEX(alpha2[0], SSB_SPROM4_CCODE, 0xff00, 8);
288 + SPEX(alpha2[1], SSB_SPROM4_CCODE, 0x00ff, 0);
289 SPEX(boardflags_lo, SSB_SPROM4_BFLLO, 0xFFFF, 0);
290 SPEX(boardflags_hi, SSB_SPROM4_BFLHI, 0xFFFF, 0);
291 SPEX(boardflags2_lo, SSB_SPROM4_BFL2LO, 0xFFFF, 0);
292 SPEX(boardflags2_hi, SSB_SPROM4_BFL2HI, 0xFFFF, 0);
293 } else {
294 - SPEX(country_code, SSB_SPROM5_CCODE, 0xFFFF, 0);
295 + SPEX(alpha2[0], SSB_SPROM5_CCODE, 0xff00, 8);
296 + SPEX(alpha2[1], SSB_SPROM5_CCODE, 0x00ff, 0);
297 SPEX(boardflags_lo, SSB_SPROM5_BFLLO, 0xFFFF, 0);
298 SPEX(boardflags_hi, SSB_SPROM5_BFLHI, 0xFFFF, 0);
299 SPEX(boardflags2_lo, SSB_SPROM5_BFL2LO, 0xFFFF, 0);
300 @@ -504,16 +513,14 @@ static void sprom_extract_r45(struct ssb
301 }
302
303 /* Extract the antenna gain values. */
304 - SPEX(antenna_gain.ghz24.a0, SSB_SPROM4_AGAIN01,
305 + SPEX(antenna_gain.a0, SSB_SPROM4_AGAIN01,
306 SSB_SPROM4_AGAIN0, SSB_SPROM4_AGAIN0_SHIFT);
307 - SPEX(antenna_gain.ghz24.a1, SSB_SPROM4_AGAIN01,
308 + SPEX(antenna_gain.a1, SSB_SPROM4_AGAIN01,
309 SSB_SPROM4_AGAIN1, SSB_SPROM4_AGAIN1_SHIFT);
310 - SPEX(antenna_gain.ghz24.a2, SSB_SPROM4_AGAIN23,
311 + SPEX(antenna_gain.a2, SSB_SPROM4_AGAIN23,
312 SSB_SPROM4_AGAIN2, SSB_SPROM4_AGAIN2_SHIFT);
313 - SPEX(antenna_gain.ghz24.a3, SSB_SPROM4_AGAIN23,
314 + SPEX(antenna_gain.a3, SSB_SPROM4_AGAIN23,
315 SSB_SPROM4_AGAIN3, SSB_SPROM4_AGAIN3_SHIFT);
316 - memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
317 - sizeof(out->antenna_gain.ghz5));
318
319 sprom_extract_r458(out, in);
320
321 @@ -523,14 +530,22 @@ static void sprom_extract_r45(struct ssb
322 static void sprom_extract_r8(struct ssb_sprom *out, const u16 *in)
323 {
324 int i;
325 - u16 v;
326 + u16 v, o;
327 + u16 pwr_info_offset[] = {
328 + SSB_SROM8_PWR_INFO_CORE0, SSB_SROM8_PWR_INFO_CORE1,
329 + SSB_SROM8_PWR_INFO_CORE2, SSB_SROM8_PWR_INFO_CORE3
330 + };
331 + BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
332 + ARRAY_SIZE(out->core_pwr_info));
333
334 /* extract the MAC address */
335 for (i = 0; i < 3; i++) {
336 v = in[SPOFF(SSB_SPROM8_IL0MAC) + i];
337 *(((__be16 *)out->il0mac) + i) = cpu_to_be16(v);
338 }
339 - SPEX(country_code, SSB_SPROM8_CCODE, 0xFFFF, 0);
340 + SPEX(board_rev, SSB_SPROM8_BOARDREV, 0xFFFF, 0);
341 + SPEX(alpha2[0], SSB_SPROM8_CCODE, 0xff00, 8);
342 + SPEX(alpha2[1], SSB_SPROM8_CCODE, 0x00ff, 0);
343 SPEX(boardflags_lo, SSB_SPROM8_BFLLO, 0xFFFF, 0);
344 SPEX(boardflags_hi, SSB_SPROM8_BFLHI, 0xFFFF, 0);
345 SPEX(boardflags2_lo, SSB_SPROM8_BFL2LO, 0xFFFF, 0);
346 @@ -596,16 +611,46 @@ static void sprom_extract_r8(struct ssb_
347 SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, 0xFFFFFFFF, 0);
348
349 /* Extract the antenna gain values. */
350 - SPEX(antenna_gain.ghz24.a0, SSB_SPROM8_AGAIN01,
351 + SPEX(antenna_gain.a0, SSB_SPROM8_AGAIN01,
352 SSB_SPROM8_AGAIN0, SSB_SPROM8_AGAIN0_SHIFT);
353 - SPEX(antenna_gain.ghz24.a1, SSB_SPROM8_AGAIN01,
354 + SPEX(antenna_gain.a1, SSB_SPROM8_AGAIN01,
355 SSB_SPROM8_AGAIN1, SSB_SPROM8_AGAIN1_SHIFT);
356 - SPEX(antenna_gain.ghz24.a2, SSB_SPROM8_AGAIN23,
357 + SPEX(antenna_gain.a2, SSB_SPROM8_AGAIN23,
358 SSB_SPROM8_AGAIN2, SSB_SPROM8_AGAIN2_SHIFT);
359 - SPEX(antenna_gain.ghz24.a3, SSB_SPROM8_AGAIN23,
360 + SPEX(antenna_gain.a3, SSB_SPROM8_AGAIN23,
361 SSB_SPROM8_AGAIN3, SSB_SPROM8_AGAIN3_SHIFT);
362 - memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
363 - sizeof(out->antenna_gain.ghz5));
364 +
365 + /* Extract cores power info info */
366 + for (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) {
367 + o = pwr_info_offset[i];
368 + SPEX(core_pwr_info[i].itssi_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
369 + SSB_SPROM8_2G_ITSSI, SSB_SPROM8_2G_ITSSI_SHIFT);
370 + SPEX(core_pwr_info[i].maxpwr_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
371 + SSB_SPROM8_2G_MAXP, 0);
372 +
373 + SPEX(core_pwr_info[i].pa_2g[0], o + SSB_SROM8_2G_PA_0, ~0, 0);
374 + SPEX(core_pwr_info[i].pa_2g[1], o + SSB_SROM8_2G_PA_1, ~0, 0);
375 + SPEX(core_pwr_info[i].pa_2g[2], o + SSB_SROM8_2G_PA_2, ~0, 0);
376 +
377 + SPEX(core_pwr_info[i].itssi_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
378 + SSB_SPROM8_5G_ITSSI, SSB_SPROM8_5G_ITSSI_SHIFT);
379 + SPEX(core_pwr_info[i].maxpwr_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
380 + SSB_SPROM8_5G_MAXP, 0);
381 + SPEX(core_pwr_info[i].maxpwr_5gh, o + SSB_SPROM8_5GHL_MAXP,
382 + SSB_SPROM8_5GH_MAXP, 0);
383 + SPEX(core_pwr_info[i].maxpwr_5gl, o + SSB_SPROM8_5GHL_MAXP,
384 + SSB_SPROM8_5GL_MAXP, SSB_SPROM8_5GL_MAXP_SHIFT);
385 +
386 + SPEX(core_pwr_info[i].pa_5gl[0], o + SSB_SROM8_5GL_PA_0, ~0, 0);
387 + SPEX(core_pwr_info[i].pa_5gl[1], o + SSB_SROM8_5GL_PA_1, ~0, 0);
388 + SPEX(core_pwr_info[i].pa_5gl[2], o + SSB_SROM8_5GL_PA_2, ~0, 0);
389 + SPEX(core_pwr_info[i].pa_5g[0], o + SSB_SROM8_5G_PA_0, ~0, 0);
390 + SPEX(core_pwr_info[i].pa_5g[1], o + SSB_SROM8_5G_PA_1, ~0, 0);
391 + SPEX(core_pwr_info[i].pa_5g[2], o + SSB_SROM8_5G_PA_2, ~0, 0);
392 + SPEX(core_pwr_info[i].pa_5gh[0], o + SSB_SROM8_5GH_PA_0, ~0, 0);
393 + SPEX(core_pwr_info[i].pa_5gh[1], o + SSB_SROM8_5GH_PA_1, ~0, 0);
394 + SPEX(core_pwr_info[i].pa_5gh[2], o + SSB_SROM8_5GH_PA_2, ~0, 0);
395 + }
396
397 /* Extract FEM info */
398 SPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G,
399 @@ -630,6 +675,63 @@ static void sprom_extract_r8(struct ssb_
400 SPEX(fem.ghz5.antswlut, SSB_SPROM8_FEM5G,
401 SSB_SROM8_FEM_ANTSWLUT, SSB_SROM8_FEM_ANTSWLUT_SHIFT);
402
403 + SPEX(leddc_on_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_ON,
404 + SSB_SPROM8_LEDDC_ON_SHIFT);
405 + SPEX(leddc_off_time, SSB_SPROM8_LEDDC, SSB_SPROM8_LEDDC_OFF,
406 + SSB_SPROM8_LEDDC_OFF_SHIFT);
407 +
408 + SPEX(txchain, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_TXCHAIN,
409 + SSB_SPROM8_TXRXC_TXCHAIN_SHIFT);
410 + SPEX(rxchain, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_RXCHAIN,
411 + SSB_SPROM8_TXRXC_RXCHAIN_SHIFT);
412 + SPEX(antswitch, SSB_SPROM8_TXRXC, SSB_SPROM8_TXRXC_SWITCH,
413 + SSB_SPROM8_TXRXC_SWITCH_SHIFT);
414 +
415 + SPEX(opo, SSB_SPROM8_OFDM2GPO, 0x00ff, 0);
416 +
417 + SPEX_ARRAY8(mcs2gpo, SSB_SPROM8_2G_MCSPO, ~0, 0);
418 + SPEX_ARRAY8(mcs5gpo, SSB_SPROM8_5G_MCSPO, ~0, 0);
419 + SPEX_ARRAY8(mcs5glpo, SSB_SPROM8_5GL_MCSPO, ~0, 0);
420 + SPEX_ARRAY8(mcs5ghpo, SSB_SPROM8_5GH_MCSPO, ~0, 0);
421 +
422 + SPEX(rawtempsense, SSB_SPROM8_RAWTS, SSB_SPROM8_RAWTS_RAWTEMP,
423 + SSB_SPROM8_RAWTS_RAWTEMP_SHIFT);
424 + SPEX(measpower, SSB_SPROM8_RAWTS, SSB_SPROM8_RAWTS_MEASPOWER,
425 + SSB_SPROM8_RAWTS_MEASPOWER_SHIFT);
426 + SPEX(tempsense_slope, SSB_SPROM8_OPT_CORRX,
427 + SSB_SPROM8_OPT_CORRX_TEMP_SLOPE,
428 + SSB_SPROM8_OPT_CORRX_TEMP_SLOPE_SHIFT);
429 + SPEX(tempcorrx, SSB_SPROM8_OPT_CORRX, SSB_SPROM8_OPT_CORRX_TEMPCORRX,
430 + SSB_SPROM8_OPT_CORRX_TEMPCORRX_SHIFT);
431 + SPEX(tempsense_option, SSB_SPROM8_OPT_CORRX,
432 + SSB_SPROM8_OPT_CORRX_TEMP_OPTION,
433 + SSB_SPROM8_OPT_CORRX_TEMP_OPTION_SHIFT);
434 + SPEX(freqoffset_corr, SSB_SPROM8_HWIQ_IQSWP,
435 + SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR,
436 + SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR_SHIFT);
437 + SPEX(iqcal_swp_dis, SSB_SPROM8_HWIQ_IQSWP,
438 + SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP,
439 + SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP_SHIFT);
440 + SPEX(hw_iqcal_en, SSB_SPROM8_HWIQ_IQSWP, SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL,
441 + SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL_SHIFT);
442 +
443 + SPEX(bw40po, SSB_SPROM8_BW40PO, ~0, 0);
444 + SPEX(cddpo, SSB_SPROM8_CDDPO, ~0, 0);
445 + SPEX(stbcpo, SSB_SPROM8_STBCPO, ~0, 0);
446 + SPEX(bwduppo, SSB_SPROM8_BWDUPPO, ~0, 0);
447 +
448 + SPEX(tempthresh, SSB_SPROM8_THERMAL, SSB_SPROM8_THERMAL_TRESH,
449 + SSB_SPROM8_THERMAL_TRESH_SHIFT);
450 + SPEX(tempoffset, SSB_SPROM8_THERMAL, SSB_SPROM8_THERMAL_OFFSET,
451 + SSB_SPROM8_THERMAL_OFFSET_SHIFT);
452 + SPEX(phycal_tempdelta, SSB_SPROM8_TEMPDELTA,
453 + SSB_SPROM8_TEMPDELTA_PHYCAL,
454 + SSB_SPROM8_TEMPDELTA_PHYCAL_SHIFT);
455 + SPEX(temps_period, SSB_SPROM8_TEMPDELTA, SSB_SPROM8_TEMPDELTA_PERIOD,
456 + SSB_SPROM8_TEMPDELTA_PERIOD_SHIFT);
457 + SPEX(temps_hysteresis, SSB_SPROM8_TEMPDELTA,
458 + SSB_SPROM8_TEMPDELTA_HYSTERESIS,
459 + SSB_SPROM8_TEMPDELTA_HYSTERESIS_SHIFT);
460 sprom_extract_r458(out, in);
461
462 /* TODO - get remaining rev 8 stuff needed */
463 @@ -759,7 +861,6 @@ static void ssb_pci_get_boardinfo(struct
464 {
465 bi->vendor = bus->host_pci->subsystem_vendor;
466 bi->type = bus->host_pci->subsystem_device;
467 - bi->rev = bus->host_pci->revision;
468 }
469
470 int ssb_pci_get_invariants(struct ssb_bus *bus,
471 --- a/drivers/ssb/pcmcia.c
472 +++ b/drivers/ssb/pcmcia.c
473 @@ -676,14 +676,10 @@ static int ssb_pcmcia_do_get_invariants(
474 case SSB_PCMCIA_CIS_ANTGAIN:
475 GOTO_ERROR_ON(tuple->TupleDataLen != 2,
476 "antg tpl size");
477 - sprom->antenna_gain.ghz24.a0 = tuple->TupleData[1];
478 - sprom->antenna_gain.ghz24.a1 = tuple->TupleData[1];
479 - sprom->antenna_gain.ghz24.a2 = tuple->TupleData[1];
480 - sprom->antenna_gain.ghz24.a3 = tuple->TupleData[1];
481 - sprom->antenna_gain.ghz5.a0 = tuple->TupleData[1];
482 - sprom->antenna_gain.ghz5.a1 = tuple->TupleData[1];
483 - sprom->antenna_gain.ghz5.a2 = tuple->TupleData[1];
484 - sprom->antenna_gain.ghz5.a3 = tuple->TupleData[1];
485 + sprom->antenna_gain.a0 = tuple->TupleData[1];
486 + sprom->antenna_gain.a1 = tuple->TupleData[1];
487 + sprom->antenna_gain.a2 = tuple->TupleData[1];
488 + sprom->antenna_gain.a3 = tuple->TupleData[1];
489 break;
490 case SSB_PCMCIA_CIS_BFLAGS:
491 GOTO_ERROR_ON((tuple->TupleDataLen != 3) &&
492 --- a/drivers/ssb/scan.c
493 +++ b/drivers/ssb/scan.c
494 @@ -90,6 +90,8 @@ const char *ssb_core_name(u16 coreid)
495 return "ARM 1176";
496 case SSB_DEV_ARM_7TDMI:
497 return "ARM 7TDMI";
498 + case SSB_DEV_ARM_CM3:
499 + return "ARM Cortex M3";
500 }
501 return "UNKNOWN";
502 }
503 @@ -318,6 +320,9 @@ int ssb_bus_scan(struct ssb_bus *bus,
504 bus->chip_package = 0;
505 }
506 }
507 + ssb_printk(KERN_INFO PFX "Found chip with id 0x%04X, rev 0x%02X and "
508 + "package 0x%02X\n", bus->chip_id, bus->chip_rev,
509 + bus->chip_package);
510 if (!bus->nr_devices)
511 bus->nr_devices = chipid_to_nrcores(bus->chip_id);
512 if (bus->nr_devices > ARRAY_SIZE(bus->devices)) {
513 --- a/drivers/ssb/sdio.c
514 +++ b/drivers/ssb/sdio.c
515 @@ -551,14 +551,10 @@ int ssb_sdio_get_invariants(struct ssb_b
516 case SSB_SDIO_CIS_ANTGAIN:
517 GOTO_ERROR_ON(tuple->size != 2,
518 "antg tpl size");
519 - sprom->antenna_gain.ghz24.a0 = tuple->data[1];
520 - sprom->antenna_gain.ghz24.a1 = tuple->data[1];
521 - sprom->antenna_gain.ghz24.a2 = tuple->data[1];
522 - sprom->antenna_gain.ghz24.a3 = tuple->data[1];
523 - sprom->antenna_gain.ghz5.a0 = tuple->data[1];
524 - sprom->antenna_gain.ghz5.a1 = tuple->data[1];
525 - sprom->antenna_gain.ghz5.a2 = tuple->data[1];
526 - sprom->antenna_gain.ghz5.a3 = tuple->data[1];
527 + sprom->antenna_gain.a0 = tuple->data[1];
528 + sprom->antenna_gain.a1 = tuple->data[1];
529 + sprom->antenna_gain.a2 = tuple->data[1];
530 + sprom->antenna_gain.a3 = tuple->data[1];
531 break;
532 case SSB_SDIO_CIS_BFLAGS:
533 GOTO_ERROR_ON((tuple->size != 3) &&
534 --- a/drivers/ssb/ssb_private.h
535 +++ b/drivers/ssb/ssb_private.h
536 @@ -207,4 +207,8 @@ static inline void b43_pci_ssb_bridge_ex
537 }
538 #endif /* CONFIG_SSB_B43_PCI_BRIDGE */
539
540 +/* driver_chipcommon_pmu.c */
541 +extern u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc);
542 +extern u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc);
543 +
544 #endif /* LINUX_SSB_PRIVATE_H_ */
545 --- a/include/linux/ssb/ssb.h
546 +++ b/include/linux/ssb/ssb.h
547 @@ -16,6 +16,12 @@ struct pcmcia_device;
548 struct ssb_bus;
549 struct ssb_driver;
550
551 +struct ssb_sprom_core_pwr_info {
552 + u8 itssi_2g, itssi_5g;
553 + u8 maxpwr_2g, maxpwr_5gl, maxpwr_5g, maxpwr_5gh;
554 + u16 pa_2g[4], pa_5gl[4], pa_5g[4], pa_5gh[4];
555 +};
556 +
557 struct ssb_sprom {
558 u8 revision;
559 u8 il0mac[6]; /* MAC address for 802.11b/g */
560 @@ -26,9 +32,12 @@ struct ssb_sprom {
561 u8 et0mdcport; /* MDIO for enet0 */
562 u8 et1mdcport; /* MDIO for enet1 */
563 u16 board_rev; /* Board revision number from SPROM. */
564 + u16 board_num; /* Board number from SPROM. */
565 + u16 board_type; /* Board type from SPROM. */
566 u8 country_code; /* Country Code */
567 - u16 leddc_on_time; /* LED Powersave Duty Cycle On Count */
568 - u16 leddc_off_time; /* LED Powersave Duty Cycle Off Count */
569 + char alpha2[2]; /* Country Code as two chars like EU or US */
570 + u8 leddc_on_time; /* LED Powersave Duty Cycle On Count */
571 + u8 leddc_off_time; /* LED Powersave Duty Cycle Off Count */
572 u8 ant_available_a; /* 2GHz antenna available bits (up to 4) */
573 u8 ant_available_bg; /* 5GHz antenna available bits (up to 4) */
574 u16 pa0b0;
575 @@ -47,10 +56,10 @@ struct ssb_sprom {
576 u8 gpio1; /* GPIO pin 1 */
577 u8 gpio2; /* GPIO pin 2 */
578 u8 gpio3; /* GPIO pin 3 */
579 - u16 maxpwr_bg; /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */
580 - u16 maxpwr_al; /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */
581 - u16 maxpwr_a; /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */
582 - u16 maxpwr_ah; /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */
583 + u8 maxpwr_bg; /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */
584 + u8 maxpwr_al; /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */
585 + u8 maxpwr_a; /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */
586 + u8 maxpwr_ah; /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */
587 u8 itssi_a; /* Idle TSSI Target for A-PHY */
588 u8 itssi_bg; /* Idle TSSI Target for B/G-PHY */
589 u8 tri2g; /* 2.4GHz TX isolation */
590 @@ -61,8 +70,8 @@ struct ssb_sprom {
591 u8 txpid5gl[4]; /* 4.9 - 5.1GHz TX power index */
592 u8 txpid5g[4]; /* 5.1 - 5.5GHz TX power index */
593 u8 txpid5gh[4]; /* 5.5 - ...GHz TX power index */
594 - u8 rxpo2g; /* 2GHz RX power offset */
595 - u8 rxpo5g; /* 5GHz RX power offset */
596 + s8 rxpo2g; /* 2GHz RX power offset */
597 + s8 rxpo5g; /* 5GHz RX power offset */
598 u8 rssisav2g; /* 2GHz RSSI params */
599 u8 rssismc2g;
600 u8 rssismf2g;
601 @@ -82,16 +91,13 @@ struct ssb_sprom {
602 u16 boardflags2_hi; /* Board flags (bits 48-63) */
603 /* TODO store board flags in a single u64 */
604
605 + struct ssb_sprom_core_pwr_info core_pwr_info[4];
606 +
607 /* Antenna gain values for up to 4 antennas
608 * on each band. Values in dBm/4 (Q5.2). Negative gain means the
609 * loss in the connectors is bigger than the gain. */
610 struct {
611 - struct {
612 - s8 a0, a1, a2, a3;
613 - } ghz24; /* 2.4GHz band */
614 - struct {
615 - s8 a0, a1, a2, a3;
616 - } ghz5; /* 5GHz band */
617 + s8 a0, a1, a2, a3;
618 } antenna_gain;
619
620 struct {
621 @@ -103,14 +109,85 @@ struct ssb_sprom {
622 } ghz5;
623 } fem;
624
625 - /* TODO - add any parameters needed from rev 2, 3, 4, 5 or 8 SPROMs */
626 + u16 mcs2gpo[8];
627 + u16 mcs5gpo[8];
628 + u16 mcs5glpo[8];
629 + u16 mcs5ghpo[8];
630 + u8 opo;
631 +
632 + u8 rxgainerr2ga[3];
633 + u8 rxgainerr5gla[3];
634 + u8 rxgainerr5gma[3];
635 + u8 rxgainerr5gha[3];
636 + u8 rxgainerr5gua[3];
637 +
638 + u8 noiselvl2ga[3];
639 + u8 noiselvl5gla[3];
640 + u8 noiselvl5gma[3];
641 + u8 noiselvl5gha[3];
642 + u8 noiselvl5gua[3];
643 +
644 + u8 regrev;
645 + u8 txchain;
646 + u8 rxchain;
647 + u8 antswitch;
648 + u16 cddpo;
649 + u16 stbcpo;
650 + u16 bw40po;
651 + u16 bwduppo;
652 +
653 + u8 tempthresh;
654 + u8 tempoffset;
655 + u16 rawtempsense;
656 + u8 measpower;
657 + u8 tempsense_slope;
658 + u8 tempcorrx;
659 + u8 tempsense_option;
660 + u8 freqoffset_corr;
661 + u8 iqcal_swp_dis;
662 + u8 hw_iqcal_en;
663 + u8 elna2g;
664 + u8 elna5g;
665 + u8 phycal_tempdelta;
666 + u8 temps_period;
667 + u8 temps_hysteresis;
668 + u8 measpower1;
669 + u8 measpower2;
670 + u8 pcieingress_war;
671 +
672 + /* power per rate from sromrev 9 */
673 + u16 cckbw202gpo;
674 + u16 cckbw20ul2gpo;
675 + u32 legofdmbw202gpo;
676 + u32 legofdmbw20ul2gpo;
677 + u32 legofdmbw205glpo;
678 + u32 legofdmbw20ul5glpo;
679 + u32 legofdmbw205gmpo;
680 + u32 legofdmbw20ul5gmpo;
681 + u32 legofdmbw205ghpo;
682 + u32 legofdmbw20ul5ghpo;
683 + u32 mcsbw202gpo;
684 + u32 mcsbw20ul2gpo;
685 + u32 mcsbw402gpo;
686 + u32 mcsbw205glpo;
687 + u32 mcsbw20ul5glpo;
688 + u32 mcsbw405glpo;
689 + u32 mcsbw205gmpo;
690 + u32 mcsbw20ul5gmpo;
691 + u32 mcsbw405gmpo;
692 + u32 mcsbw205ghpo;
693 + u32 mcsbw20ul5ghpo;
694 + u32 mcsbw405ghpo;
695 + u16 mcs32po;
696 + u16 legofdm40duppo;
697 + u8 sar2g;
698 + u8 sar5g;
699 };
700
701 /* Information about the PCB the circuitry is soldered on. */
702 struct ssb_boardinfo {
703 u16 vendor;
704 u16 type;
705 - u8 rev;
706 };
707
708
709 @@ -166,6 +243,7 @@ struct ssb_bus_ops {
710 #define SSB_DEV_MINI_MACPHY 0x823
711 #define SSB_DEV_ARM_1176 0x824
712 #define SSB_DEV_ARM_7TDMI 0x825
713 +#define SSB_DEV_ARM_CM3 0x82A
714
715 /* Vendor-ID values */
716 #define SSB_VENDOR_BROADCOM 0x4243
717 --- a/include/linux/ssb/ssb_driver_chipcommon.h
718 +++ b/include/linux/ssb/ssb_driver_chipcommon.h
719 @@ -504,7 +504,9 @@
720 #define SSB_CHIPCO_FLASHCTL_ST_SE 0x02D8 /* Sector Erase */
721 #define SSB_CHIPCO_FLASHCTL_ST_BE 0x00C7 /* Bulk Erase */
722 #define SSB_CHIPCO_FLASHCTL_ST_DP 0x00B9 /* Deep Power-down */
723 -#define SSB_CHIPCO_FLASHCTL_ST_RSIG 0x03AB /* Read Electronic Signature */
724 +#define SSB_CHIPCO_FLASHCTL_ST_RES 0x03AB /* Read Electronic Signature */
725 +#define SSB_CHIPCO_FLASHCTL_ST_CSA 0x1000 /* Keep chip select asserted */
726 +#define SSB_CHIPCO_FLASHCTL_ST_SSE 0x0220 /* Sub-sector Erase */
727
728 /* Status register bits for ST flashes */
729 #define SSB_CHIPCO_FLASHSTA_ST_WIP 0x01 /* Write In Progress */
730 --- a/include/linux/ssb/ssb_driver_gige.h
731 +++ b/include/linux/ssb/ssb_driver_gige.h
732 @@ -2,6 +2,7 @@
733 #define LINUX_SSB_DRIVER_GIGE_H_
734
735 #include <linux/ssb/ssb.h>
736 +#include <linux/bug.h>
737 #include <linux/pci.h>
738 #include <linux/spinlock.h>
739
740 --- a/include/linux/ssb/ssb_driver_mips.h
741 +++ b/include/linux/ssb/ssb_driver_mips.h
742 @@ -13,6 +13,12 @@ struct ssb_serial_port {
743 unsigned int reg_shift;
744 };
745
746 +struct ssb_pflash {
747 + bool present;
748 + u8 buswidth;
749 + u32 window;
750 + u32 window_size;
751 +};
752
753 struct ssb_mipscore {
754 struct ssb_device *dev;
755 @@ -20,9 +26,7 @@ struct ssb_mipscore {
756 int nr_serial_ports;
757 struct ssb_serial_port serial_ports[4];
758
759 - u8 flash_buswidth;
760 - u32 flash_window;
761 - u32 flash_window_size;
762 + struct ssb_pflash pflash;
763 };
764
765 extern void ssb_mipscore_init(struct ssb_mipscore *mcore);
766 --- a/include/linux/ssb/ssb_regs.h
767 +++ b/include/linux/ssb/ssb_regs.h
768 @@ -228,6 +228,7 @@
769 #define SSB_SPROM1_AGAIN_BG_SHIFT 0
770 #define SSB_SPROM1_AGAIN_A 0xFF00 /* A-PHY */
771 #define SSB_SPROM1_AGAIN_A_SHIFT 8
772 +#define SSB_SPROM1_CCODE 0x0076
773
774 /* SPROM Revision 2 (inherits from rev 1) */
775 #define SSB_SPROM2_BFLHI 0x0038 /* Boardflags (high 16 bits) */
776 @@ -267,6 +268,7 @@
777 #define SSB_SPROM3_OFDMGPO 0x107A /* G-PHY OFDM Power Offset (4 bytes, BigEndian) */
778
779 /* SPROM Revision 4 */
780 +#define SSB_SPROM4_BOARDREV 0x0042 /* Board revision */
781 #define SSB_SPROM4_BFLLO 0x0044 /* Boardflags (low 16 bits) */
782 #define SSB_SPROM4_BFLHI 0x0046 /* Board Flags Hi */
783 #define SSB_SPROM4_BFL2LO 0x0048 /* Board flags 2 (low 16 bits) */
784 @@ -389,6 +391,11 @@
785 #define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */
786 #define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */
787 #define SSB_SPROM8_GPIOB_P3_SHIFT 8
788 +#define SSB_SPROM8_LEDDC 0x009A
789 +#define SSB_SPROM8_LEDDC_ON 0xFF00 /* oncount */
790 +#define SSB_SPROM8_LEDDC_ON_SHIFT 8
791 +#define SSB_SPROM8_LEDDC_OFF 0x00FF /* offcount */
792 +#define SSB_SPROM8_LEDDC_OFF_SHIFT 0
793 #define SSB_SPROM8_ANTAVAIL 0x009C /* Antenna available bitfields*/
794 #define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */
795 #define SSB_SPROM8_ANTAVAIL_A_SHIFT 8
796 @@ -404,6 +411,13 @@
797 #define SSB_SPROM8_AGAIN2_SHIFT 0
798 #define SSB_SPROM8_AGAIN3 0xFF00 /* Antenna 3 */
799 #define SSB_SPROM8_AGAIN3_SHIFT 8
800 +#define SSB_SPROM8_TXRXC 0x00A2
801 +#define SSB_SPROM8_TXRXC_TXCHAIN 0x000f
802 +#define SSB_SPROM8_TXRXC_TXCHAIN_SHIFT 0
803 +#define SSB_SPROM8_TXRXC_RXCHAIN 0x00f0
804 +#define SSB_SPROM8_TXRXC_RXCHAIN_SHIFT 4
805 +#define SSB_SPROM8_TXRXC_SWITCH 0xff00
806 +#define SSB_SPROM8_TXRXC_SWITCH_SHIFT 8
807 #define SSB_SPROM8_RSSIPARM2G 0x00A4 /* RSSI params for 2GHz */
808 #define SSB_SPROM8_RSSISMF2G 0x000F
809 #define SSB_SPROM8_RSSISMC2G 0x00F0
810 @@ -430,6 +444,7 @@
811 #define SSB_SPROM8_TRI5GH_SHIFT 8
812 #define SSB_SPROM8_RXPO 0x00AC /* RX power offsets */
813 #define SSB_SPROM8_RXPO2G 0x00FF /* 2GHz RX power offset */
814 +#define SSB_SPROM8_RXPO2G_SHIFT 0
815 #define SSB_SPROM8_RXPO5G 0xFF00 /* 5GHz RX power offset */
816 #define SSB_SPROM8_RXPO5G_SHIFT 8
817 #define SSB_SPROM8_FEM2G 0x00AE
818 @@ -445,10 +460,71 @@
819 #define SSB_SROM8_FEM_ANTSWLUT 0xF800
820 #define SSB_SROM8_FEM_ANTSWLUT_SHIFT 11
821 #define SSB_SPROM8_THERMAL 0x00B2
822 -#define SSB_SPROM8_MPWR_RAWTS 0x00B4
823 -#define SSB_SPROM8_TS_SLP_OPT_CORRX 0x00B6
824 -#define SSB_SPROM8_FOC_HWIQ_IQSWP 0x00B8
825 -#define SSB_SPROM8_PHYCAL_TEMPDELTA 0x00BA
826 +#define SSB_SPROM8_THERMAL_OFFSET 0x00ff
827 +#define SSB_SPROM8_THERMAL_OFFSET_SHIFT 0
828 +#define SSB_SPROM8_THERMAL_TRESH 0xff00
829 +#define SSB_SPROM8_THERMAL_TRESH_SHIFT 8
830 +/* Temp sense related entries */
831 +#define SSB_SPROM8_RAWTS 0x00B4
832 +#define SSB_SPROM8_RAWTS_RAWTEMP 0x01ff
833 +#define SSB_SPROM8_RAWTS_RAWTEMP_SHIFT 0
834 +#define SSB_SPROM8_RAWTS_MEASPOWER 0xfe00
835 +#define SSB_SPROM8_RAWTS_MEASPOWER_SHIFT 9
836 +#define SSB_SPROM8_OPT_CORRX 0x00B6
837 +#define SSB_SPROM8_OPT_CORRX_TEMP_SLOPE 0x00ff
838 +#define SSB_SPROM8_OPT_CORRX_TEMP_SLOPE_SHIFT 0
839 +#define SSB_SPROM8_OPT_CORRX_TEMPCORRX 0xfc00
840 +#define SSB_SPROM8_OPT_CORRX_TEMPCORRX_SHIFT 10
841 +#define SSB_SPROM8_OPT_CORRX_TEMP_OPTION 0x0300
842 +#define SSB_SPROM8_OPT_CORRX_TEMP_OPTION_SHIFT 8
843 +/* FOC: freiquency offset correction, HWIQ: H/W IOCAL enable, IQSWP: IQ CAL swap disable */
844 +#define SSB_SPROM8_HWIQ_IQSWP 0x00B8
845 +#define SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR 0x000f
846 +#define SSB_SPROM8_HWIQ_IQSWP_FREQ_CORR_SHIFT 0
847 +#define SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP 0x0010
848 +#define SSB_SPROM8_HWIQ_IQSWP_IQCAL_SWP_SHIFT 4
849 +#define SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL 0x0020
850 +#define SSB_SPROM8_HWIQ_IQSWP_HW_IQCAL_SHIFT 5
851 +#define SSB_SPROM8_TEMPDELTA 0x00BA
852 +#define SSB_SPROM8_TEMPDELTA_PHYCAL 0x00ff
853 +#define SSB_SPROM8_TEMPDELTA_PHYCAL_SHIFT 0
854 +#define SSB_SPROM8_TEMPDELTA_PERIOD 0x0f00
855 +#define SSB_SPROM8_TEMPDELTA_PERIOD_SHIFT 8
856 +#define SSB_SPROM8_TEMPDELTA_HYSTERESIS 0xf000
857 +#define SSB_SPROM8_TEMPDELTA_HYSTERESIS_SHIFT 12
858 +
859 +/* There are 4 blocks with power info sharing the same layout */
860 +#define SSB_SROM8_PWR_INFO_CORE0 0x00C0
861 +#define SSB_SROM8_PWR_INFO_CORE1 0x00E0
862 +#define SSB_SROM8_PWR_INFO_CORE2 0x0100
863 +#define SSB_SROM8_PWR_INFO_CORE3 0x0120
864 +
865 +#define SSB_SROM8_2G_MAXP_ITSSI 0x00
866 +#define SSB_SPROM8_2G_MAXP 0x00FF
867 +#define SSB_SPROM8_2G_ITSSI 0xFF00
868 +#define SSB_SPROM8_2G_ITSSI_SHIFT 8
869 +#define SSB_SROM8_2G_PA_0 0x02 /* 2GHz power amp settings */
870 +#define SSB_SROM8_2G_PA_1 0x04
871 +#define SSB_SROM8_2G_PA_2 0x06
872 +#define SSB_SROM8_5G_MAXP_ITSSI 0x08 /* 5GHz ITSSI and 5.3GHz Max Power */
873 +#define SSB_SPROM8_5G_MAXP 0x00FF
874 +#define SSB_SPROM8_5G_ITSSI 0xFF00
875 +#define SSB_SPROM8_5G_ITSSI_SHIFT 8
876 +#define SSB_SPROM8_5GHL_MAXP 0x0A /* 5.2GHz and 5.8GHz Max Power */
877 +#define SSB_SPROM8_5GH_MAXP 0x00FF
878 +#define SSB_SPROM8_5GL_MAXP 0xFF00
879 +#define SSB_SPROM8_5GL_MAXP_SHIFT 8
880 +#define SSB_SROM8_5G_PA_0 0x0C /* 5.3GHz power amp settings */
881 +#define SSB_SROM8_5G_PA_1 0x0E
882 +#define SSB_SROM8_5G_PA_2 0x10
883 +#define SSB_SROM8_5GL_PA_0 0x12 /* 5.2GHz power amp settings */
884 +#define SSB_SROM8_5GL_PA_1 0x14
885 +#define SSB_SROM8_5GL_PA_2 0x16
886 +#define SSB_SROM8_5GH_PA_0 0x18 /* 5.8GHz power amp settings */
887 +#define SSB_SROM8_5GH_PA_1 0x1A
888 +#define SSB_SROM8_5GH_PA_2 0x1C
889 +
890 +/* TODO: Make it deprecated */
891 #define SSB_SPROM8_MAXP_BG 0x00C0 /* Max Power 2GHz in path 1 */
892 #define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */
893 #define SSB_SPROM8_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
894 @@ -473,12 +549,23 @@
895 #define SSB_SPROM8_PA1HIB0 0x00D8 /* 5.8GHz power amp settings */
896 #define SSB_SPROM8_PA1HIB1 0x00DA
897 #define SSB_SPROM8_PA1HIB2 0x00DC
898 +
899 #define SSB_SPROM8_CCK2GPO 0x0140 /* CCK power offset */
900 #define SSB_SPROM8_OFDM2GPO 0x0142 /* 2.4GHz OFDM power offset */
901 #define SSB_SPROM8_OFDM5GPO 0x0146 /* 5.3GHz OFDM power offset */
902 #define SSB_SPROM8_OFDM5GLPO 0x014A /* 5.2GHz OFDM power offset */
903 #define SSB_SPROM8_OFDM5GHPO 0x014E /* 5.8GHz OFDM power offset */
904
905 +#define SSB_SPROM8_2G_MCSPO 0x0152
906 +#define SSB_SPROM8_5G_MCSPO 0x0162
907 +#define SSB_SPROM8_5GL_MCSPO 0x0172
908 +#define SSB_SPROM8_5GH_MCSPO 0x0182
909 +
910 +#define SSB_SPROM8_CDDPO 0x0192
911 +#define SSB_SPROM8_STBCPO 0x0194
912 +#define SSB_SPROM8_BW40PO 0x0196
913 +#define SSB_SPROM8_BWDUPPO 0x0198
914 +
915 /* Values for boardflags_lo read from SPROM */
916 #define SSB_BFL_BTCOEXIST 0x0001 /* implements Bluetooth coexistance */
917 #define SSB_BFL_PACTRL 0x0002 /* GPIO 9 controlling the PA */
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