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kernel: update bcma and ssb to version master-2012-04-12 from wireless-testing
[openwrt/svn-archive/archive.git] / target / linux / generic / patches-3.3 / 020-ssb_update.patch
1 --- a/drivers/ssb/driver_chipcommon_pmu.c
2 +++ b/drivers/ssb/driver_chipcommon_pmu.c
3 @@ -13,6 +13,9 @@
4 #include <linux/ssb/ssb_driver_chipcommon.h>
5 #include <linux/delay.h>
6 #include <linux/export.h>
7 +#ifdef CONFIG_BCM47XX
8 +#include <asm/mach-bcm47xx/nvram.h>
9 +#endif
10
11 #include "ssb_private.h"
12
13 @@ -92,10 +95,6 @@ static void ssb_pmu0_pllinit_r0(struct s
14 u32 pmuctl, tmp, pllctl;
15 unsigned int i;
16
17 - if ((bus->chip_id == 0x5354) && !crystalfreq) {
18 - /* The 5354 crystal freq is 25MHz */
19 - crystalfreq = 25000;
20 - }
21 if (crystalfreq)
22 e = pmu0_plltab_find_entry(crystalfreq);
23 if (!e)
24 @@ -321,7 +320,11 @@ static void ssb_pmu_pll_init(struct ssb_
25 u32 crystalfreq = 0; /* in kHz. 0 = keep default freq. */
26
27 if (bus->bustype == SSB_BUSTYPE_SSB) {
28 - /* TODO: The user may override the crystal frequency. */
29 +#ifdef CONFIG_BCM47XX
30 + char buf[20];
31 + if (nvram_getenv("xtalfreq", buf, sizeof(buf)) >= 0)
32 + crystalfreq = simple_strtoul(buf, NULL, 0);
33 +#endif
34 }
35
36 switch (bus->chip_id) {
37 @@ -330,7 +333,11 @@ static void ssb_pmu_pll_init(struct ssb_
38 ssb_pmu1_pllinit_r0(cc, crystalfreq);
39 break;
40 case 0x4328:
41 + ssb_pmu0_pllinit_r0(cc, crystalfreq);
42 + break;
43 case 0x5354:
44 + if (crystalfreq == 0)
45 + crystalfreq = 25000;
46 ssb_pmu0_pllinit_r0(cc, crystalfreq);
47 break;
48 case 0x4322:
49 @@ -607,3 +614,34 @@ void ssb_pmu_set_ldo_paref(struct ssb_ch
50
51 EXPORT_SYMBOL(ssb_pmu_set_ldo_voltage);
52 EXPORT_SYMBOL(ssb_pmu_set_ldo_paref);
53 +
54 +u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc)
55 +{
56 + struct ssb_bus *bus = cc->dev->bus;
57 +
58 + switch (bus->chip_id) {
59 + case 0x5354:
60 + /* 5354 chip uses a non programmable PLL of frequency 240MHz */
61 + return 240000000;
62 + default:
63 + ssb_printk(KERN_ERR PFX
64 + "ERROR: PMU cpu clock unknown for device %04X\n",
65 + bus->chip_id);
66 + return 0;
67 + }
68 +}
69 +
70 +u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc)
71 +{
72 + struct ssb_bus *bus = cc->dev->bus;
73 +
74 + switch (bus->chip_id) {
75 + case 0x5354:
76 + return 120000000;
77 + default:
78 + ssb_printk(KERN_ERR PFX
79 + "ERROR: PMU controlclock unknown for device %04X\n",
80 + bus->chip_id);
81 + return 0;
82 + }
83 +}
84 --- a/drivers/ssb/driver_mipscore.c
85 +++ b/drivers/ssb/driver_mipscore.c
86 @@ -208,6 +208,9 @@ u32 ssb_cpu_clock(struct ssb_mipscore *m
87 struct ssb_bus *bus = mcore->dev->bus;
88 u32 pll_type, n, m, rate = 0;
89
90 + if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
91 + return ssb_pmu_get_cpu_clock(&bus->chipco);
92 +
93 if (bus->extif.dev) {
94 ssb_extif_get_clockcontrol(&bus->extif, &pll_type, &n, &m);
95 } else if (bus->chipco.dev) {
96 --- a/drivers/ssb/main.c
97 +++ b/drivers/ssb/main.c
98 @@ -140,19 +140,6 @@ static void ssb_device_put(struct ssb_de
99 put_device(dev->dev);
100 }
101
102 -static inline struct ssb_driver *ssb_driver_get(struct ssb_driver *drv)
103 -{
104 - if (drv)
105 - get_driver(&drv->drv);
106 - return drv;
107 -}
108 -
109 -static inline void ssb_driver_put(struct ssb_driver *drv)
110 -{
111 - if (drv)
112 - put_driver(&drv->drv);
113 -}
114 -
115 static int ssb_device_resume(struct device *dev)
116 {
117 struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
118 @@ -250,11 +237,9 @@ int ssb_devices_freeze(struct ssb_bus *b
119 ssb_device_put(sdev);
120 continue;
121 }
122 - sdrv = ssb_driver_get(drv_to_ssb_drv(sdev->dev->driver));
123 - if (!sdrv || SSB_WARN_ON(!sdrv->remove)) {
124 - ssb_device_put(sdev);
125 + sdrv = drv_to_ssb_drv(sdev->dev->driver);
126 + if (SSB_WARN_ON(!sdrv->remove))
127 continue;
128 - }
129 sdrv->remove(sdev);
130 ctx->device_frozen[i] = 1;
131 }
132 @@ -293,7 +278,6 @@ int ssb_devices_thaw(struct ssb_freeze_c
133 dev_name(sdev->dev));
134 result = err;
135 }
136 - ssb_driver_put(sdrv);
137 ssb_device_put(sdev);
138 }
139
140 @@ -1094,6 +1078,9 @@ u32 ssb_clockspeed(struct ssb_bus *bus)
141 u32 plltype;
142 u32 clkctl_n, clkctl_m;
143
144 + if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
145 + return ssb_pmu_get_controlclock(&bus->chipco);
146 +
147 if (ssb_extif_available(&bus->extif))
148 ssb_extif_get_clockcontrol(&bus->extif, &plltype,
149 &clkctl_n, &clkctl_m);
150 --- a/drivers/ssb/pci.c
151 +++ b/drivers/ssb/pci.c
152 @@ -331,7 +331,6 @@ static void sprom_extract_r123(struct ss
153 {
154 int i;
155 u16 v;
156 - s8 gain;
157 u16 loc[3];
158
159 if (out->revision == 3) /* rev 3 moved MAC */
160 @@ -390,20 +389,12 @@ static void sprom_extract_r123(struct ss
161 SPEX(boardflags_hi, SSB_SPROM2_BFLHI, 0xFFFF, 0);
162
163 /* Extract the antenna gain values. */
164 - gain = r123_extract_antgain(out->revision, in,
165 - SSB_SPROM1_AGAIN_BG,
166 - SSB_SPROM1_AGAIN_BG_SHIFT);
167 - out->antenna_gain.ghz24.a0 = gain;
168 - out->antenna_gain.ghz24.a1 = gain;
169 - out->antenna_gain.ghz24.a2 = gain;
170 - out->antenna_gain.ghz24.a3 = gain;
171 - gain = r123_extract_antgain(out->revision, in,
172 - SSB_SPROM1_AGAIN_A,
173 - SSB_SPROM1_AGAIN_A_SHIFT);
174 - out->antenna_gain.ghz5.a0 = gain;
175 - out->antenna_gain.ghz5.a1 = gain;
176 - out->antenna_gain.ghz5.a2 = gain;
177 - out->antenna_gain.ghz5.a3 = gain;
178 + out->antenna_gain.a0 = r123_extract_antgain(out->revision, in,
179 + SSB_SPROM1_AGAIN_BG,
180 + SSB_SPROM1_AGAIN_BG_SHIFT);
181 + out->antenna_gain.a1 = r123_extract_antgain(out->revision, in,
182 + SSB_SPROM1_AGAIN_A,
183 + SSB_SPROM1_AGAIN_A_SHIFT);
184 }
185
186 /* Revs 4 5 and 8 have partially shared layout */
187 @@ -504,16 +495,14 @@ static void sprom_extract_r45(struct ssb
188 }
189
190 /* Extract the antenna gain values. */
191 - SPEX(antenna_gain.ghz24.a0, SSB_SPROM4_AGAIN01,
192 + SPEX(antenna_gain.a0, SSB_SPROM4_AGAIN01,
193 SSB_SPROM4_AGAIN0, SSB_SPROM4_AGAIN0_SHIFT);
194 - SPEX(antenna_gain.ghz24.a1, SSB_SPROM4_AGAIN01,
195 + SPEX(antenna_gain.a1, SSB_SPROM4_AGAIN01,
196 SSB_SPROM4_AGAIN1, SSB_SPROM4_AGAIN1_SHIFT);
197 - SPEX(antenna_gain.ghz24.a2, SSB_SPROM4_AGAIN23,
198 + SPEX(antenna_gain.a2, SSB_SPROM4_AGAIN23,
199 SSB_SPROM4_AGAIN2, SSB_SPROM4_AGAIN2_SHIFT);
200 - SPEX(antenna_gain.ghz24.a3, SSB_SPROM4_AGAIN23,
201 + SPEX(antenna_gain.a3, SSB_SPROM4_AGAIN23,
202 SSB_SPROM4_AGAIN3, SSB_SPROM4_AGAIN3_SHIFT);
203 - memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
204 - sizeof(out->antenna_gain.ghz5));
205
206 sprom_extract_r458(out, in);
207
208 @@ -523,7 +512,13 @@ static void sprom_extract_r45(struct ssb
209 static void sprom_extract_r8(struct ssb_sprom *out, const u16 *in)
210 {
211 int i;
212 - u16 v;
213 + u16 v, o;
214 + u16 pwr_info_offset[] = {
215 + SSB_SROM8_PWR_INFO_CORE0, SSB_SROM8_PWR_INFO_CORE1,
216 + SSB_SROM8_PWR_INFO_CORE2, SSB_SROM8_PWR_INFO_CORE3
217 + };
218 + BUILD_BUG_ON(ARRAY_SIZE(pwr_info_offset) !=
219 + ARRAY_SIZE(out->core_pwr_info));
220
221 /* extract the MAC address */
222 for (i = 0; i < 3; i++) {
223 @@ -596,16 +591,46 @@ static void sprom_extract_r8(struct ssb_
224 SPEX32(ofdm5ghpo, SSB_SPROM8_OFDM5GHPO, 0xFFFFFFFF, 0);
225
226 /* Extract the antenna gain values. */
227 - SPEX(antenna_gain.ghz24.a0, SSB_SPROM8_AGAIN01,
228 + SPEX(antenna_gain.a0, SSB_SPROM8_AGAIN01,
229 SSB_SPROM8_AGAIN0, SSB_SPROM8_AGAIN0_SHIFT);
230 - SPEX(antenna_gain.ghz24.a1, SSB_SPROM8_AGAIN01,
231 + SPEX(antenna_gain.a1, SSB_SPROM8_AGAIN01,
232 SSB_SPROM8_AGAIN1, SSB_SPROM8_AGAIN1_SHIFT);
233 - SPEX(antenna_gain.ghz24.a2, SSB_SPROM8_AGAIN23,
234 + SPEX(antenna_gain.a2, SSB_SPROM8_AGAIN23,
235 SSB_SPROM8_AGAIN2, SSB_SPROM8_AGAIN2_SHIFT);
236 - SPEX(antenna_gain.ghz24.a3, SSB_SPROM8_AGAIN23,
237 + SPEX(antenna_gain.a3, SSB_SPROM8_AGAIN23,
238 SSB_SPROM8_AGAIN3, SSB_SPROM8_AGAIN3_SHIFT);
239 - memcpy(&out->antenna_gain.ghz5, &out->antenna_gain.ghz24,
240 - sizeof(out->antenna_gain.ghz5));
241 +
242 + /* Extract cores power info info */
243 + for (i = 0; i < ARRAY_SIZE(pwr_info_offset); i++) {
244 + o = pwr_info_offset[i];
245 + SPEX(core_pwr_info[i].itssi_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
246 + SSB_SPROM8_2G_ITSSI, SSB_SPROM8_2G_ITSSI_SHIFT);
247 + SPEX(core_pwr_info[i].maxpwr_2g, o + SSB_SROM8_2G_MAXP_ITSSI,
248 + SSB_SPROM8_2G_MAXP, 0);
249 +
250 + SPEX(core_pwr_info[i].pa_2g[0], o + SSB_SROM8_2G_PA_0, ~0, 0);
251 + SPEX(core_pwr_info[i].pa_2g[1], o + SSB_SROM8_2G_PA_1, ~0, 0);
252 + SPEX(core_pwr_info[i].pa_2g[2], o + SSB_SROM8_2G_PA_2, ~0, 0);
253 +
254 + SPEX(core_pwr_info[i].itssi_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
255 + SSB_SPROM8_5G_ITSSI, SSB_SPROM8_5G_ITSSI_SHIFT);
256 + SPEX(core_pwr_info[i].maxpwr_5g, o + SSB_SROM8_5G_MAXP_ITSSI,
257 + SSB_SPROM8_5G_MAXP, 0);
258 + SPEX(core_pwr_info[i].maxpwr_5gh, o + SSB_SPROM8_5GHL_MAXP,
259 + SSB_SPROM8_5GH_MAXP, 0);
260 + SPEX(core_pwr_info[i].maxpwr_5gl, o + SSB_SPROM8_5GHL_MAXP,
261 + SSB_SPROM8_5GL_MAXP, SSB_SPROM8_5GL_MAXP_SHIFT);
262 +
263 + SPEX(core_pwr_info[i].pa_5gl[0], o + SSB_SROM8_5GL_PA_0, ~0, 0);
264 + SPEX(core_pwr_info[i].pa_5gl[1], o + SSB_SROM8_5GL_PA_1, ~0, 0);
265 + SPEX(core_pwr_info[i].pa_5gl[2], o + SSB_SROM8_5GL_PA_2, ~0, 0);
266 + SPEX(core_pwr_info[i].pa_5g[0], o + SSB_SROM8_5G_PA_0, ~0, 0);
267 + SPEX(core_pwr_info[i].pa_5g[1], o + SSB_SROM8_5G_PA_1, ~0, 0);
268 + SPEX(core_pwr_info[i].pa_5g[2], o + SSB_SROM8_5G_PA_2, ~0, 0);
269 + SPEX(core_pwr_info[i].pa_5gh[0], o + SSB_SROM8_5GH_PA_0, ~0, 0);
270 + SPEX(core_pwr_info[i].pa_5gh[1], o + SSB_SROM8_5GH_PA_1, ~0, 0);
271 + SPEX(core_pwr_info[i].pa_5gh[2], o + SSB_SROM8_5GH_PA_2, ~0, 0);
272 + }
273
274 /* Extract FEM info */
275 SPEX(fem.ghz2.tssipos, SSB_SPROM8_FEM2G,
276 --- a/drivers/ssb/pcmcia.c
277 +++ b/drivers/ssb/pcmcia.c
278 @@ -676,14 +676,10 @@ static int ssb_pcmcia_do_get_invariants(
279 case SSB_PCMCIA_CIS_ANTGAIN:
280 GOTO_ERROR_ON(tuple->TupleDataLen != 2,
281 "antg tpl size");
282 - sprom->antenna_gain.ghz24.a0 = tuple->TupleData[1];
283 - sprom->antenna_gain.ghz24.a1 = tuple->TupleData[1];
284 - sprom->antenna_gain.ghz24.a2 = tuple->TupleData[1];
285 - sprom->antenna_gain.ghz24.a3 = tuple->TupleData[1];
286 - sprom->antenna_gain.ghz5.a0 = tuple->TupleData[1];
287 - sprom->antenna_gain.ghz5.a1 = tuple->TupleData[1];
288 - sprom->antenna_gain.ghz5.a2 = tuple->TupleData[1];
289 - sprom->antenna_gain.ghz5.a3 = tuple->TupleData[1];
290 + sprom->antenna_gain.a0 = tuple->TupleData[1];
291 + sprom->antenna_gain.a1 = tuple->TupleData[1];
292 + sprom->antenna_gain.a2 = tuple->TupleData[1];
293 + sprom->antenna_gain.a3 = tuple->TupleData[1];
294 break;
295 case SSB_PCMCIA_CIS_BFLAGS:
296 GOTO_ERROR_ON((tuple->TupleDataLen != 3) &&
297 --- a/drivers/ssb/scan.c
298 +++ b/drivers/ssb/scan.c
299 @@ -318,6 +318,9 @@ int ssb_bus_scan(struct ssb_bus *bus,
300 bus->chip_package = 0;
301 }
302 }
303 + ssb_printk(KERN_INFO PFX "Found chip with id 0x%04X, rev 0x%02X and "
304 + "package 0x%02X\n", bus->chip_id, bus->chip_rev,
305 + bus->chip_package);
306 if (!bus->nr_devices)
307 bus->nr_devices = chipid_to_nrcores(bus->chip_id);
308 if (bus->nr_devices > ARRAY_SIZE(bus->devices)) {
309 --- a/drivers/ssb/sdio.c
310 +++ b/drivers/ssb/sdio.c
311 @@ -551,14 +551,10 @@ int ssb_sdio_get_invariants(struct ssb_b
312 case SSB_SDIO_CIS_ANTGAIN:
313 GOTO_ERROR_ON(tuple->size != 2,
314 "antg tpl size");
315 - sprom->antenna_gain.ghz24.a0 = tuple->data[1];
316 - sprom->antenna_gain.ghz24.a1 = tuple->data[1];
317 - sprom->antenna_gain.ghz24.a2 = tuple->data[1];
318 - sprom->antenna_gain.ghz24.a3 = tuple->data[1];
319 - sprom->antenna_gain.ghz5.a0 = tuple->data[1];
320 - sprom->antenna_gain.ghz5.a1 = tuple->data[1];
321 - sprom->antenna_gain.ghz5.a2 = tuple->data[1];
322 - sprom->antenna_gain.ghz5.a3 = tuple->data[1];
323 + sprom->antenna_gain.a0 = tuple->data[1];
324 + sprom->antenna_gain.a1 = tuple->data[1];
325 + sprom->antenna_gain.a2 = tuple->data[1];
326 + sprom->antenna_gain.a3 = tuple->data[1];
327 break;
328 case SSB_SDIO_CIS_BFLAGS:
329 GOTO_ERROR_ON((tuple->size != 3) &&
330 --- a/drivers/ssb/ssb_private.h
331 +++ b/drivers/ssb/ssb_private.h
332 @@ -207,4 +207,8 @@ static inline void b43_pci_ssb_bridge_ex
333 }
334 #endif /* CONFIG_SSB_B43_PCI_BRIDGE */
335
336 +/* driver_chipcommon_pmu.c */
337 +extern u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc);
338 +extern u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc);
339 +
340 #endif /* LINUX_SSB_PRIVATE_H_ */
341 --- a/include/linux/ssb/ssb.h
342 +++ b/include/linux/ssb/ssb.h
343 @@ -16,6 +16,12 @@ struct pcmcia_device;
344 struct ssb_bus;
345 struct ssb_driver;
346
347 +struct ssb_sprom_core_pwr_info {
348 + u8 itssi_2g, itssi_5g;
349 + u8 maxpwr_2g, maxpwr_5gl, maxpwr_5g, maxpwr_5gh;
350 + u16 pa_2g[4], pa_5gl[4], pa_5g[4], pa_5gh[4];
351 +};
352 +
353 struct ssb_sprom {
354 u8 revision;
355 u8 il0mac[6]; /* MAC address for 802.11b/g */
356 @@ -26,9 +32,12 @@ struct ssb_sprom {
357 u8 et0mdcport; /* MDIO for enet0 */
358 u8 et1mdcport; /* MDIO for enet1 */
359 u16 board_rev; /* Board revision number from SPROM. */
360 + u16 board_num; /* Board number from SPROM. */
361 + u16 board_type; /* Board type from SPROM. */
362 u8 country_code; /* Country Code */
363 - u16 leddc_on_time; /* LED Powersave Duty Cycle On Count */
364 - u16 leddc_off_time; /* LED Powersave Duty Cycle Off Count */
365 + char alpha2[2]; /* Country Code as two chars like EU or US */
366 + u8 leddc_on_time; /* LED Powersave Duty Cycle On Count */
367 + u8 leddc_off_time; /* LED Powersave Duty Cycle Off Count */
368 u8 ant_available_a; /* 2GHz antenna available bits (up to 4) */
369 u8 ant_available_bg; /* 5GHz antenna available bits (up to 4) */
370 u16 pa0b0;
371 @@ -47,10 +56,10 @@ struct ssb_sprom {
372 u8 gpio1; /* GPIO pin 1 */
373 u8 gpio2; /* GPIO pin 2 */
374 u8 gpio3; /* GPIO pin 3 */
375 - u16 maxpwr_bg; /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */
376 - u16 maxpwr_al; /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */
377 - u16 maxpwr_a; /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */
378 - u16 maxpwr_ah; /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */
379 + u8 maxpwr_bg; /* 2.4GHz Amplifier Max Power (in dBm Q5.2) */
380 + u8 maxpwr_al; /* 5.2GHz Amplifier Max Power (in dBm Q5.2) */
381 + u8 maxpwr_a; /* 5.3GHz Amplifier Max Power (in dBm Q5.2) */
382 + u8 maxpwr_ah; /* 5.8GHz Amplifier Max Power (in dBm Q5.2) */
383 u8 itssi_a; /* Idle TSSI Target for A-PHY */
384 u8 itssi_bg; /* Idle TSSI Target for B/G-PHY */
385 u8 tri2g; /* 2.4GHz TX isolation */
386 @@ -61,8 +70,8 @@ struct ssb_sprom {
387 u8 txpid5gl[4]; /* 4.9 - 5.1GHz TX power index */
388 u8 txpid5g[4]; /* 5.1 - 5.5GHz TX power index */
389 u8 txpid5gh[4]; /* 5.5 - ...GHz TX power index */
390 - u8 rxpo2g; /* 2GHz RX power offset */
391 - u8 rxpo5g; /* 5GHz RX power offset */
392 + s8 rxpo2g; /* 2GHz RX power offset */
393 + s8 rxpo5g; /* 5GHz RX power offset */
394 u8 rssisav2g; /* 2GHz RSSI params */
395 u8 rssismc2g;
396 u8 rssismf2g;
397 @@ -82,16 +91,13 @@ struct ssb_sprom {
398 u16 boardflags2_hi; /* Board flags (bits 48-63) */
399 /* TODO store board flags in a single u64 */
400
401 + struct ssb_sprom_core_pwr_info core_pwr_info[4];
402 +
403 /* Antenna gain values for up to 4 antennas
404 * on each band. Values in dBm/4 (Q5.2). Negative gain means the
405 * loss in the connectors is bigger than the gain. */
406 struct {
407 - struct {
408 - s8 a0, a1, a2, a3;
409 - } ghz24; /* 2.4GHz band */
410 - struct {
411 - s8 a0, a1, a2, a3;
412 - } ghz5; /* 5GHz band */
413 + s8 a0, a1, a2, a3;
414 } antenna_gain;
415
416 struct {
417 @@ -103,7 +109,79 @@ struct ssb_sprom {
418 } ghz5;
419 } fem;
420
421 - /* TODO - add any parameters needed from rev 2, 3, 4, 5 or 8 SPROMs */
422 + u16 mcs2gpo[8];
423 + u16 mcs5gpo[8];
424 + u16 mcs5glpo[8];
425 + u16 mcs5ghpo[8];
426 + u8 opo;
427 +
428 + u8 rxgainerr2ga[3];
429 + u8 rxgainerr5gla[3];
430 + u8 rxgainerr5gma[3];
431 + u8 rxgainerr5gha[3];
432 + u8 rxgainerr5gua[3];
433 +
434 + u8 noiselvl2ga[3];
435 + u8 noiselvl5gla[3];
436 + u8 noiselvl5gma[3];
437 + u8 noiselvl5gha[3];
438 + u8 noiselvl5gua[3];
439 +
440 + u8 regrev;
441 + u8 txchain;
442 + u8 rxchain;
443 + u8 antswitch;
444 + u16 cddpo;
445 + u16 stbcpo;
446 + u16 bw40po;
447 + u16 bwduppo;
448 +
449 + u8 tempthresh;
450 + u8 tempoffset;
451 + u16 rawtempsense;
452 + u8 measpower;
453 + u8 tempsense_slope;
454 + u8 tempcorrx;
455 + u8 tempsense_option;
456 + u8 freqoffset_corr;
457 + u8 iqcal_swp_dis;
458 + u8 hw_iqcal_en;
459 + u8 elna2g;
460 + u8 elna5g;
461 + u8 phycal_tempdelta;
462 + u8 temps_period;
463 + u8 temps_hysteresis;
464 + u8 measpower1;
465 + u8 measpower2;
466 + u8 pcieingress_war;
467 +
468 + /* power per rate from sromrev 9 */
469 + u16 cckbw202gpo;
470 + u16 cckbw20ul2gpo;
471 + u32 legofdmbw202gpo;
472 + u32 legofdmbw20ul2gpo;
473 + u32 legofdmbw205glpo;
474 + u32 legofdmbw20ul5glpo;
475 + u32 legofdmbw205gmpo;
476 + u32 legofdmbw20ul5gmpo;
477 + u32 legofdmbw205ghpo;
478 + u32 legofdmbw20ul5ghpo;
479 + u32 mcsbw202gpo;
480 + u32 mcsbw20ul2gpo;
481 + u32 mcsbw402gpo;
482 + u32 mcsbw205glpo;
483 + u32 mcsbw20ul5glpo;
484 + u32 mcsbw405glpo;
485 + u32 mcsbw205gmpo;
486 + u32 mcsbw20ul5gmpo;
487 + u32 mcsbw405gmpo;
488 + u32 mcsbw205ghpo;
489 + u32 mcsbw20ul5ghpo;
490 + u32 mcsbw405ghpo;
491 + u16 mcs32po;
492 + u16 legofdm40duppo;
493 + u8 sar2g;
494 + u8 sar5g;
495 };
496
497 /* Information about the PCB the circuitry is soldered on. */
498 --- a/include/linux/ssb/ssb_driver_gige.h
499 +++ b/include/linux/ssb/ssb_driver_gige.h
500 @@ -2,6 +2,7 @@
501 #define LINUX_SSB_DRIVER_GIGE_H_
502
503 #include <linux/ssb/ssb.h>
504 +#include <linux/bug.h>
505 #include <linux/pci.h>
506 #include <linux/spinlock.h>
507
508 --- a/include/linux/ssb/ssb_regs.h
509 +++ b/include/linux/ssb/ssb_regs.h
510 @@ -449,6 +449,39 @@
511 #define SSB_SPROM8_TS_SLP_OPT_CORRX 0x00B6
512 #define SSB_SPROM8_FOC_HWIQ_IQSWP 0x00B8
513 #define SSB_SPROM8_PHYCAL_TEMPDELTA 0x00BA
514 +
515 +/* There are 4 blocks with power info sharing the same layout */
516 +#define SSB_SROM8_PWR_INFO_CORE0 0x00C0
517 +#define SSB_SROM8_PWR_INFO_CORE1 0x00E0
518 +#define SSB_SROM8_PWR_INFO_CORE2 0x0100
519 +#define SSB_SROM8_PWR_INFO_CORE3 0x0120
520 +
521 +#define SSB_SROM8_2G_MAXP_ITSSI 0x00
522 +#define SSB_SPROM8_2G_MAXP 0x00FF
523 +#define SSB_SPROM8_2G_ITSSI 0xFF00
524 +#define SSB_SPROM8_2G_ITSSI_SHIFT 8
525 +#define SSB_SROM8_2G_PA_0 0x02 /* 2GHz power amp settings */
526 +#define SSB_SROM8_2G_PA_1 0x04
527 +#define SSB_SROM8_2G_PA_2 0x06
528 +#define SSB_SROM8_5G_MAXP_ITSSI 0x08 /* 5GHz ITSSI and 5.3GHz Max Power */
529 +#define SSB_SPROM8_5G_MAXP 0x00FF
530 +#define SSB_SPROM8_5G_ITSSI 0xFF00
531 +#define SSB_SPROM8_5G_ITSSI_SHIFT 8
532 +#define SSB_SPROM8_5GHL_MAXP 0x0A /* 5.2GHz and 5.8GHz Max Power */
533 +#define SSB_SPROM8_5GH_MAXP 0x00FF
534 +#define SSB_SPROM8_5GL_MAXP 0xFF00
535 +#define SSB_SPROM8_5GL_MAXP_SHIFT 8
536 +#define SSB_SROM8_5G_PA_0 0x0C /* 5.3GHz power amp settings */
537 +#define SSB_SROM8_5G_PA_1 0x0E
538 +#define SSB_SROM8_5G_PA_2 0x10
539 +#define SSB_SROM8_5GL_PA_0 0x12 /* 5.2GHz power amp settings */
540 +#define SSB_SROM8_5GL_PA_1 0x14
541 +#define SSB_SROM8_5GL_PA_2 0x16
542 +#define SSB_SROM8_5GH_PA_0 0x18 /* 5.8GHz power amp settings */
543 +#define SSB_SROM8_5GH_PA_1 0x1A
544 +#define SSB_SROM8_5GH_PA_2 0x1C
545 +
546 +/* TODO: Make it deprecated */
547 #define SSB_SPROM8_MAXP_BG 0x00C0 /* Max Power 2GHz in path 1 */
548 #define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */
549 #define SSB_SPROM8_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */
550 @@ -473,6 +506,7 @@
551 #define SSB_SPROM8_PA1HIB0 0x00D8 /* 5.8GHz power amp settings */
552 #define SSB_SPROM8_PA1HIB1 0x00DA
553 #define SSB_SPROM8_PA1HIB2 0x00DC
554 +
555 #define SSB_SPROM8_CCK2GPO 0x0140 /* CCK power offset */
556 #define SSB_SPROM8_OFDM2GPO 0x0142 /* 2.4GHz OFDM power offset */
557 #define SSB_SPROM8_OFDM5GPO 0x0146 /* 5.3GHz OFDM power offset */
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