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kernel: update bcma and ssb for kernel 3.8+ to version from wireless-testing master...
[openwrt/staging/yousong.git] / target / linux / generic / patches-3.8 / 025-bcma_backport.patch
1 --- a/arch/mips/bcm47xx/serial.c
2 +++ b/arch/mips/bcm47xx/serial.c
3 @@ -62,7 +62,7 @@ static int __init uart8250_init_bcma(voi
4
5 p->mapbase = (unsigned int) bcma_port->regs;
6 p->membase = (void *) bcma_port->regs;
7 - p->irq = bcma_port->irq + 2;
8 + p->irq = bcma_port->irq;
9 p->uartclk = bcma_port->baud_base;
10 p->regshift = bcma_port->reg_shift;
11 p->iotype = UPIO_MEM;
12 --- a/drivers/bcma/bcma_private.h
13 +++ b/drivers/bcma/bcma_private.h
14 @@ -31,6 +31,8 @@ int __init bcma_bus_early_register(struc
15 int bcma_bus_suspend(struct bcma_bus *bus);
16 int bcma_bus_resume(struct bcma_bus *bus);
17 #endif
18 +struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
19 + u8 unit);
20
21 /* scan.c */
22 int bcma_bus_scan(struct bcma_bus *bus);
23 @@ -45,6 +47,7 @@ int bcma_sprom_get(struct bcma_bus *bus)
24 /* driver_chipcommon.c */
25 #ifdef CONFIG_BCMA_DRIVER_MIPS
26 void bcma_chipco_serial_init(struct bcma_drv_cc *cc);
27 +extern struct platform_device bcma_pflash_dev;
28 #endif /* CONFIG_BCMA_DRIVER_MIPS */
29
30 /* driver_chipcommon_pmu.c */
31 --- a/drivers/bcma/core.c
32 +++ b/drivers/bcma/core.c
33 @@ -104,7 +104,13 @@ void bcma_core_pll_ctl(struct bcma_devic
34 if (i)
35 bcma_err(core->bus, "PLL enable timeout\n");
36 } else {
37 - bcma_warn(core->bus, "Disabling PLL not supported yet!\n");
38 + /*
39 + * Mask the PLL but don't wait for it to be disabled. PLL may be
40 + * shared between cores and will be still up if there is another
41 + * core using it.
42 + */
43 + bcma_mask32(core, BCMA_CLKCTLST, ~req);
44 + bcma_read32(core, BCMA_CLKCTLST);
45 }
46 }
47 EXPORT_SYMBOL_GPL(bcma_core_pll_ctl);
48 --- a/drivers/bcma/driver_chipcommon.c
49 +++ b/drivers/bcma/driver_chipcommon.c
50 @@ -25,13 +25,14 @@ static inline u32 bcma_cc_write32_masked
51 return value;
52 }
53
54 -static u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc)
55 +u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc)
56 {
57 if (cc->capabilities & BCMA_CC_CAP_PMU)
58 return bcma_pmu_get_alp_clock(cc);
59
60 return 20000000;
61 }
62 +EXPORT_SYMBOL_GPL(bcma_chipco_get_alp_clock);
63
64 static u32 bcma_chipco_watchdog_get_max_timer(struct bcma_drv_cc *cc)
65 {
66 @@ -213,6 +214,7 @@ u32 bcma_chipco_gpio_out(struct bcma_drv
67
68 return res;
69 }
70 +EXPORT_SYMBOL_GPL(bcma_chipco_gpio_out);
71
72 u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value)
73 {
74 @@ -225,6 +227,7 @@ u32 bcma_chipco_gpio_outen(struct bcma_d
75
76 return res;
77 }
78 +EXPORT_SYMBOL_GPL(bcma_chipco_gpio_outen);
79
80 /*
81 * If the bit is set to 0, chipcommon controlls this GPIO,
82 @@ -329,7 +332,7 @@ void bcma_chipco_serial_init(struct bcma
83 return;
84 }
85
86 - irq = bcma_core_mips_irq(cc->core);
87 + irq = bcma_core_irq(cc->core);
88
89 /* Determine the registers of the UARTs */
90 cc->nr_serial_ports = (cc->capabilities & BCMA_CC_CAP_NRUART);
91 --- a/drivers/bcma/driver_chipcommon_nflash.c
92 +++ b/drivers/bcma/driver_chipcommon_nflash.c
93 @@ -5,11 +5,11 @@
94 * Licensed under the GNU/GPL. See COPYING for details.
95 */
96
97 +#include "bcma_private.h"
98 +
99 #include <linux/platform_device.h>
100 #include <linux/bcma/bcma.h>
101
102 -#include "bcma_private.h"
103 -
104 struct platform_device bcma_nflash_dev = {
105 .name = "bcma_nflash",
106 .num_resources = 0,
107 --- a/drivers/bcma/driver_chipcommon_pmu.c
108 +++ b/drivers/bcma/driver_chipcommon_pmu.c
109 @@ -174,19 +174,35 @@ u32 bcma_pmu_get_alp_clock(struct bcma_d
110 struct bcma_bus *bus = cc->core->bus;
111
112 switch (bus->chipinfo.id) {
113 + case BCMA_CHIP_ID_BCM4313:
114 + case BCMA_CHIP_ID_BCM43224:
115 + case BCMA_CHIP_ID_BCM43225:
116 + case BCMA_CHIP_ID_BCM43227:
117 + case BCMA_CHIP_ID_BCM43228:
118 + case BCMA_CHIP_ID_BCM4331:
119 + case BCMA_CHIP_ID_BCM43421:
120 + case BCMA_CHIP_ID_BCM43428:
121 + case BCMA_CHIP_ID_BCM43431:
122 case BCMA_CHIP_ID_BCM4716:
123 - case BCMA_CHIP_ID_BCM4748:
124 case BCMA_CHIP_ID_BCM47162:
125 - case BCMA_CHIP_ID_BCM4313:
126 - case BCMA_CHIP_ID_BCM5357:
127 + case BCMA_CHIP_ID_BCM4748:
128 case BCMA_CHIP_ID_BCM4749:
129 + case BCMA_CHIP_ID_BCM5357:
130 case BCMA_CHIP_ID_BCM53572:
131 + case BCMA_CHIP_ID_BCM6362:
132 /* always 20Mhz */
133 return 20000 * 1000;
134 - case BCMA_CHIP_ID_BCM5356:
135 case BCMA_CHIP_ID_BCM4706:
136 + case BCMA_CHIP_ID_BCM5356:
137 /* always 25Mhz */
138 return 25000 * 1000;
139 + case BCMA_CHIP_ID_BCM43460:
140 + case BCMA_CHIP_ID_BCM4352:
141 + case BCMA_CHIP_ID_BCM4360:
142 + if (cc->status & BCMA_CC_CHIPST_4360_XTAL_40MZ)
143 + return 40000 * 1000;
144 + else
145 + return 20000 * 1000;
146 default:
147 bcma_warn(bus, "No ALP clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
148 bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK);
149 @@ -264,7 +280,7 @@ static u32 bcma_pmu_pll_clock_bcm4706(st
150 }
151
152 /* query bus clock frequency for PMU-enabled chipcommon */
153 -static u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc)
154 +u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc)
155 {
156 struct bcma_bus *bus = cc->core->bus;
157
158 @@ -293,6 +309,7 @@ static u32 bcma_pmu_get_bus_clock(struct
159 }
160 return BCMA_CC_PMU_HT_CLOCK;
161 }
162 +EXPORT_SYMBOL_GPL(bcma_pmu_get_bus_clock);
163
164 /* query cpu clock frequency for PMU-enabled chipcommon */
165 u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc)
166 @@ -372,7 +389,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
167 tmp |= (bcm5357_bcm43236_ndiv[spuravoid]) << BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT;
168 bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);
169
170 - tmp = 1 << 10;
171 + tmp = BCMA_CC_PMU_CTL_PLL_UPD;
172 break;
173
174 case BCMA_CHIP_ID_BCM4331:
175 @@ -393,7 +410,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
176 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
177 0x03000a08);
178 }
179 - tmp = 1 << 10;
180 + tmp = BCMA_CC_PMU_CTL_PLL_UPD;
181 break;
182
183 case BCMA_CHIP_ID_BCM43224:
184 @@ -426,7 +443,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
185 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
186 0x88888815);
187 }
188 - tmp = 1 << 10;
189 + tmp = BCMA_CC_PMU_CTL_PLL_UPD;
190 break;
191
192 case BCMA_CHIP_ID_BCM4716:
193 @@ -460,7 +477,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
194 0x88888815);
195 }
196
197 - tmp = 3 << 9;
198 + tmp = BCMA_CC_PMU_CTL_PLL_UPD | BCMA_CC_PMU_CTL_NOILPONW;
199 break;
200
201 case BCMA_CHIP_ID_BCM43227:
202 @@ -496,7 +513,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
203 bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
204 0x88888815);
205 }
206 - tmp = 1 << 10;
207 + tmp = BCMA_CC_PMU_CTL_PLL_UPD;
208 break;
209 default:
210 bcma_err(bus, "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n",
211 --- a/drivers/bcma/driver_chipcommon_sflash.c
212 +++ b/drivers/bcma/driver_chipcommon_sflash.c
213 @@ -5,11 +5,11 @@
214 * Licensed under the GNU/GPL. See COPYING for details.
215 */
216
217 +#include "bcma_private.h"
218 +
219 #include <linux/platform_device.h>
220 #include <linux/bcma/bcma.h>
221
222 -#include "bcma_private.h"
223 -
224 static struct resource bcma_sflash_resource = {
225 .name = "bcma_sflash",
226 .start = BCMA_SOC_FLASH2,
227 --- a/drivers/bcma/driver_gpio.c
228 +++ b/drivers/bcma/driver_gpio.c
229 @@ -73,6 +73,16 @@ static void bcma_gpio_free(struct gpio_c
230 bcma_chipco_gpio_pullup(cc, 1 << gpio, 0);
231 }
232
233 +static int bcma_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
234 +{
235 + struct bcma_drv_cc *cc = bcma_gpio_get_cc(chip);
236 +
237 + if (cc->core->bus->hosttype == BCMA_HOSTTYPE_SOC)
238 + return bcma_core_irq(cc->core);
239 + else
240 + return -EINVAL;
241 +}
242 +
243 int bcma_gpio_init(struct bcma_drv_cc *cc)
244 {
245 struct gpio_chip *chip = &cc->gpio;
246 @@ -85,6 +95,7 @@ int bcma_gpio_init(struct bcma_drv_cc *c
247 chip->set = bcma_gpio_set_value;
248 chip->direction_input = bcma_gpio_direction_input;
249 chip->direction_output = bcma_gpio_direction_output;
250 + chip->to_irq = bcma_gpio_to_irq;
251 chip->ngpio = 16;
252 /* There is just one SoC in one device and its GPIO addresses should be
253 * deterministic to address them more easily. The other buses could get
254 --- a/drivers/bcma/driver_mips.c
255 +++ b/drivers/bcma/driver_mips.c
256 @@ -14,11 +14,33 @@
257
258 #include <linux/bcma/bcma.h>
259
260 +#include <linux/mtd/physmap.h>
261 +#include <linux/platform_device.h>
262 #include <linux/serial.h>
263 #include <linux/serial_core.h>
264 #include <linux/serial_reg.h>
265 #include <linux/time.h>
266
267 +static const char *part_probes[] = { "bcm47xxpart", NULL };
268 +
269 +static struct physmap_flash_data bcma_pflash_data = {
270 + .part_probe_types = part_probes,
271 +};
272 +
273 +static struct resource bcma_pflash_resource = {
274 + .name = "bcma_pflash",
275 + .flags = IORESOURCE_MEM,
276 +};
277 +
278 +struct platform_device bcma_pflash_dev = {
279 + .name = "physmap-flash",
280 + .dev = {
281 + .platform_data = &bcma_pflash_data,
282 + },
283 + .resource = &bcma_pflash_resource,
284 + .num_resources = 1,
285 +};
286 +
287 /* The 47162a0 hangs when reading MIPS DMP registers registers */
288 static inline bool bcma_core_mips_bcm47162a0_quirk(struct bcma_device *dev)
289 {
290 @@ -74,28 +96,41 @@ static u32 bcma_core_mips_irqflag(struct
291 return dev->core_index;
292 flag = bcma_aread32(dev, BCMA_MIPS_OOBSELOUTA30);
293
294 - return flag & 0x1F;
295 + if (flag)
296 + return flag & 0x1F;
297 + else
298 + return 0x3f;
299 }
300
301 /* Get the MIPS IRQ assignment for a specified device.
302 * If unassigned, 0 is returned.
303 + * If disabled, 5 is returned.
304 + * If not supported, 6 is returned.
305 */
306 -unsigned int bcma_core_mips_irq(struct bcma_device *dev)
307 +static unsigned int bcma_core_mips_irq(struct bcma_device *dev)
308 {
309 struct bcma_device *mdev = dev->bus->drv_mips.core;
310 u32 irqflag;
311 unsigned int irq;
312
313 irqflag = bcma_core_mips_irqflag(dev);
314 + if (irqflag == 0x3f)
315 + return 6;
316
317 - for (irq = 1; irq <= 4; irq++)
318 + for (irq = 0; irq <= 4; irq++)
319 if (bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(irq)) &
320 (1 << irqflag))
321 return irq;
322
323 - return 0;
324 + return 5;
325 }
326 -EXPORT_SYMBOL(bcma_core_mips_irq);
327 +
328 +unsigned int bcma_core_irq(struct bcma_device *dev)
329 +{
330 + unsigned int mips_irq = bcma_core_mips_irq(dev);
331 + return mips_irq <= 4 ? mips_irq + 2 : 0;
332 +}
333 +EXPORT_SYMBOL(bcma_core_irq);
334
335 static void bcma_core_mips_set_irq(struct bcma_device *dev, unsigned int irq)
336 {
337 @@ -114,7 +149,7 @@ static void bcma_core_mips_set_irq(struc
338 bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0),
339 bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) &
340 ~(1 << irqflag));
341 - else
342 + else if (oldirq != 5)
343 bcma_write32(mdev, BCMA_MIPS_MIPS74K_INTMASK(oldirq), 0);
344
345 /* assign the new one */
346 @@ -123,9 +158,9 @@ static void bcma_core_mips_set_irq(struc
347 bcma_read32(mdev, BCMA_MIPS_MIPS74K_INTMASK(0)) |
348 (1 << irqflag));
349 } else {
350 - u32 oldirqflag = bcma_read32(mdev,
351 - BCMA_MIPS_MIPS74K_INTMASK(irq));
352 - if (oldirqflag) {
353 + u32 irqinitmask = bcma_read32(mdev,
354 + BCMA_MIPS_MIPS74K_INTMASK(irq));
355 + if (irqinitmask) {
356 struct bcma_device *core;
357
358 /* backplane irq line is in use, find out who uses
359 @@ -133,7 +168,7 @@ static void bcma_core_mips_set_irq(struc
360 */
361 list_for_each_entry(core, &bus->cores, list) {
362 if ((1 << bcma_core_mips_irqflag(core)) ==
363 - oldirqflag) {
364 + irqinitmask) {
365 bcma_core_mips_set_irq(core, 0);
366 break;
367 }
368 @@ -143,15 +178,31 @@ static void bcma_core_mips_set_irq(struc
369 1 << irqflag);
370 }
371
372 - bcma_info(bus, "set_irq: core 0x%04x, irq %d => %d\n",
373 - dev->id.id, oldirq + 2, irq + 2);
374 + bcma_debug(bus, "set_irq: core 0x%04x, irq %d => %d\n",
375 + dev->id.id, oldirq <= 4 ? oldirq + 2 : 0, irq + 2);
376 +}
377 +
378 +static void bcma_core_mips_set_irq_name(struct bcma_bus *bus, unsigned int irq,
379 + u16 coreid, u8 unit)
380 +{
381 + struct bcma_device *core;
382 +
383 + core = bcma_find_core_unit(bus, coreid, unit);
384 + if (!core) {
385 + bcma_warn(bus,
386 + "Can not find core (id: 0x%x, unit %i) for IRQ configuration.\n",
387 + coreid, unit);
388 + return;
389 + }
390 +
391 + bcma_core_mips_set_irq(core, irq);
392 }
393
394 static void bcma_core_mips_print_irq(struct bcma_device *dev, unsigned int irq)
395 {
396 int i;
397 static const char *irq_name[] = {"2(S)", "3", "4", "5", "6", "D", "I"};
398 - printk(KERN_INFO KBUILD_MODNAME ": core 0x%04x, irq :", dev->id.id);
399 + printk(KERN_DEBUG KBUILD_MODNAME ": core 0x%04x, irq :", dev->id.id);
400 for (i = 0; i <= 6; i++)
401 printk(" %s%s", irq_name[i], i == irq ? "*" : " ");
402 printk("\n");
403 @@ -182,6 +233,7 @@ static void bcma_core_mips_flash_detect(
404 {
405 struct bcma_bus *bus = mcore->core->bus;
406 struct bcma_drv_cc *cc = &bus->drv_cc;
407 + struct bcma_pflash *pflash = &cc->pflash;
408
409 switch (cc->capabilities & BCMA_CC_CAP_FLASHT) {
410 case BCMA_CC_FLASHT_STSER:
411 @@ -191,15 +243,20 @@ static void bcma_core_mips_flash_detect(
412 break;
413 case BCMA_CC_FLASHT_PARA:
414 bcma_debug(bus, "Found parallel flash\n");
415 - cc->pflash.present = true;
416 - cc->pflash.window = BCMA_SOC_FLASH2;
417 - cc->pflash.window_size = BCMA_SOC_FLASH2_SZ;
418 + pflash->present = true;
419 + pflash->window = BCMA_SOC_FLASH2;
420 + pflash->window_size = BCMA_SOC_FLASH2_SZ;
421
422 if ((bcma_read32(cc->core, BCMA_CC_FLASH_CFG) &
423 BCMA_CC_FLASH_CFG_DS) == 0)
424 - cc->pflash.buswidth = 1;
425 + pflash->buswidth = 1;
426 else
427 - cc->pflash.buswidth = 2;
428 + pflash->buswidth = 2;
429 +
430 + bcma_pflash_data.width = pflash->buswidth;
431 + bcma_pflash_resource.start = pflash->window;
432 + bcma_pflash_resource.end = pflash->window + pflash->window_size;
433 +
434 break;
435 default:
436 bcma_err(bus, "Flash type not supported\n");
437 @@ -227,6 +284,32 @@ void bcma_core_mips_early_init(struct bc
438 mcore->early_setup_done = true;
439 }
440
441 +static void bcma_fix_i2s_irqflag(struct bcma_bus *bus)
442 +{
443 + struct bcma_device *cpu, *pcie, *i2s;
444 +
445 + /* Fixup the interrupts in 4716/4748 for i2s core (2010 Broadcom SDK)
446 + * (IRQ flags > 7 are ignored when setting the interrupt masks)
447 + */
448 + if (bus->chipinfo.id != BCMA_CHIP_ID_BCM4716 &&
449 + bus->chipinfo.id != BCMA_CHIP_ID_BCM4748)
450 + return;
451 +
452 + cpu = bcma_find_core(bus, BCMA_CORE_MIPS_74K);
453 + pcie = bcma_find_core(bus, BCMA_CORE_PCIE);
454 + i2s = bcma_find_core(bus, BCMA_CORE_I2S);
455 + if (cpu && pcie && i2s &&
456 + bcma_aread32(cpu, BCMA_MIPS_OOBSELINA74) == 0x08060504 &&
457 + bcma_aread32(pcie, BCMA_MIPS_OOBSELINA74) == 0x08060504 &&
458 + bcma_aread32(i2s, BCMA_MIPS_OOBSELOUTA30) == 0x88) {
459 + bcma_awrite32(cpu, BCMA_MIPS_OOBSELINA74, 0x07060504);
460 + bcma_awrite32(pcie, BCMA_MIPS_OOBSELINA74, 0x07060504);
461 + bcma_awrite32(i2s, BCMA_MIPS_OOBSELOUTA30, 0x87);
462 + bcma_debug(bus,
463 + "Moved i2s interrupt to oob line 7 instead of 8\n");
464 + }
465 +}
466 +
467 void bcma_core_mips_init(struct bcma_drv_mips *mcore)
468 {
469 struct bcma_bus *bus;
470 @@ -236,43 +319,55 @@ void bcma_core_mips_init(struct bcma_drv
471 if (mcore->setup_done)
472 return;
473
474 - bcma_info(bus, "Initializing MIPS core...\n");
475 + bcma_debug(bus, "Initializing MIPS core...\n");
476
477 bcma_core_mips_early_init(mcore);
478
479 - mcore->assigned_irqs = 1;
480 + bcma_fix_i2s_irqflag(bus);
481
482 - /* Assign IRQs to all cores on the bus */
483 - list_for_each_entry(core, &bus->cores, list) {
484 - int mips_irq;
485 - if (core->irq)
486 - continue;
487 -
488 - mips_irq = bcma_core_mips_irq(core);
489 - if (mips_irq > 4)
490 - core->irq = 0;
491 - else
492 - core->irq = mips_irq + 2;
493 - if (core->irq > 5)
494 - continue;
495 - switch (core->id.id) {
496 - case BCMA_CORE_PCI:
497 - case BCMA_CORE_PCIE:
498 - case BCMA_CORE_ETHERNET:
499 - case BCMA_CORE_ETHERNET_GBIT:
500 - case BCMA_CORE_MAC_GBIT:
501 - case BCMA_CORE_80211:
502 - case BCMA_CORE_USB20_HOST:
503 - /* These devices get their own IRQ line if available,
504 - * the rest goes on IRQ0
505 - */
506 - if (mcore->assigned_irqs <= 4)
507 - bcma_core_mips_set_irq(core,
508 - mcore->assigned_irqs++);
509 - break;
510 + switch (bus->chipinfo.id) {
511 + case BCMA_CHIP_ID_BCM4716:
512 + case BCMA_CHIP_ID_BCM4748:
513 + bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
514 + bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
515 + bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_USB20_HOST, 0);
516 + bcma_core_mips_set_irq_name(bus, 4, BCMA_CORE_PCIE, 0);
517 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
518 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_I2S, 0);
519 + break;
520 + case BCMA_CHIP_ID_BCM5356:
521 + case BCMA_CHIP_ID_BCM47162:
522 + case BCMA_CHIP_ID_BCM53572:
523 + bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
524 + bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
525 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
526 + break;
527 + case BCMA_CHIP_ID_BCM5357:
528 + case BCMA_CHIP_ID_BCM4749:
529 + bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_80211, 0);
530 + bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_MAC_GBIT, 0);
531 + bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_USB20_HOST, 0);
532 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_CHIPCOMMON, 0);
533 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_I2S, 0);
534 + break;
535 + case BCMA_CHIP_ID_BCM4706:
536 + bcma_core_mips_set_irq_name(bus, 1, BCMA_CORE_PCIE, 0);
537 + bcma_core_mips_set_irq_name(bus, 2, BCMA_CORE_4706_MAC_GBIT,
538 + 0);
539 + bcma_core_mips_set_irq_name(bus, 3, BCMA_CORE_PCIE, 1);
540 + bcma_core_mips_set_irq_name(bus, 4, BCMA_CORE_USB20_HOST, 0);
541 + bcma_core_mips_set_irq_name(bus, 0, BCMA_CORE_4706_CHIPCOMMON,
542 + 0);
543 + break;
544 + default:
545 + list_for_each_entry(core, &bus->cores, list) {
546 + core->irq = bcma_core_irq(core);
547 }
548 + bcma_err(bus,
549 + "Unknown device (0x%x) found, can not configure IRQs\n",
550 + bus->chipinfo.id);
551 }
552 - bcma_info(bus, "IRQ reconfiguration done\n");
553 + bcma_debug(bus, "IRQ reconfiguration done\n");
554 bcma_core_mips_dump_irq(bus);
555
556 mcore->setup_done = true;
557 --- a/drivers/bcma/driver_pci_host.c
558 +++ b/drivers/bcma/driver_pci_host.c
559 @@ -94,19 +94,19 @@ static int bcma_extpci_read_config(struc
560 if (dev == 0) {
561 /* we support only two functions on device 0 */
562 if (func > 1)
563 - return -EINVAL;
564 + goto out;
565
566 /* accesses to config registers with offsets >= 256
567 * requires indirect access.
568 */
569 if (off >= PCI_CONFIG_SPACE_SIZE) {
570 addr = (func << 12);
571 - addr |= (off & 0x0FFF);
572 + addr |= (off & 0x0FFC);
573 val = bcma_pcie_read_config(pc, addr);
574 } else {
575 addr = BCMA_CORE_PCI_PCICFG0;
576 addr |= (func << 8);
577 - addr |= (off & 0xfc);
578 + addr |= (off & 0xFC);
579 val = pcicore_read32(pc, addr);
580 }
581 } else {
582 @@ -119,11 +119,9 @@ static int bcma_extpci_read_config(struc
583 goto out;
584
585 if (mips_busprobe32(val, mmio)) {
586 - val = 0xffffffff;
587 + val = 0xFFFFFFFF;
588 goto unmap;
589 }
590 -
591 - val = readl(mmio);
592 }
593 val >>= (8 * (off & 3));
594
595 @@ -151,7 +149,7 @@ static int bcma_extpci_write_config(stru
596 const void *buf, int len)
597 {
598 int err = -EINVAL;
599 - u32 addr = 0, val = 0;
600 + u32 addr, val;
601 void __iomem *mmio = 0;
602 u16 chipid = pc->core->bus->chipinfo.id;
603
604 @@ -159,16 +157,22 @@ static int bcma_extpci_write_config(stru
605 if (unlikely(len != 1 && len != 2 && len != 4))
606 goto out;
607 if (dev == 0) {
608 + /* we support only two functions on device 0 */
609 + if (func > 1)
610 + goto out;
611 +
612 /* accesses to config registers with offsets >= 256
613 * requires indirect access.
614 */
615 - if (off < PCI_CONFIG_SPACE_SIZE) {
616 - addr = pc->core->addr + BCMA_CORE_PCI_PCICFG0;
617 + if (off >= PCI_CONFIG_SPACE_SIZE) {
618 + addr = (func << 12);
619 + addr |= (off & 0x0FFC);
620 + val = bcma_pcie_read_config(pc, addr);
621 + } else {
622 + addr = BCMA_CORE_PCI_PCICFG0;
623 addr |= (func << 8);
624 - addr |= (off & 0xfc);
625 - mmio = ioremap_nocache(addr, sizeof(val));
626 - if (!mmio)
627 - goto out;
628 + addr |= (off & 0xFC);
629 + val = pcicore_read32(pc, addr);
630 }
631 } else {
632 addr = bcma_get_cfgspace_addr(pc, dev, func, off);
633 @@ -180,19 +184,17 @@ static int bcma_extpci_write_config(stru
634 goto out;
635
636 if (mips_busprobe32(val, mmio)) {
637 - val = 0xffffffff;
638 + val = 0xFFFFFFFF;
639 goto unmap;
640 }
641 }
642
643 switch (len) {
644 case 1:
645 - val = readl(mmio);
646 val &= ~(0xFF << (8 * (off & 3)));
647 val |= *((const u8 *)buf) << (8 * (off & 3));
648 break;
649 case 2:
650 - val = readl(mmio);
651 val &= ~(0xFFFF << (8 * (off & 3)));
652 val |= *((const u16 *)buf) << (8 * (off & 3));
653 break;
654 @@ -200,13 +202,14 @@ static int bcma_extpci_write_config(stru
655 val = *((const u32 *)buf);
656 break;
657 }
658 - if (dev == 0 && !addr) {
659 + if (dev == 0) {
660 /* accesses to config registers with offsets >= 256
661 * requires indirect access.
662 */
663 - addr = (func << 12);
664 - addr |= (off & 0x0FFF);
665 - bcma_pcie_write_config(pc, addr, val);
666 + if (off >= PCI_CONFIG_SPACE_SIZE)
667 + bcma_pcie_write_config(pc, addr, val);
668 + else
669 + pcicore_write32(pc, addr, val);
670 } else {
671 writel(val, mmio);
672
673 @@ -276,7 +279,7 @@ static u8 bcma_find_pci_capability(struc
674 /* check for Header type 0 */
675 bcma_extpci_read_config(pc, dev, func, PCI_HEADER_TYPE, &byte_val,
676 sizeof(u8));
677 - if ((byte_val & 0x7f) != PCI_HEADER_TYPE_NORMAL)
678 + if ((byte_val & 0x7F) != PCI_HEADER_TYPE_NORMAL)
679 return cap_ptr;
680
681 /* check if the capability pointer field exists */
682 @@ -401,6 +404,8 @@ void bcma_core_pci_hostmode_init(struct
683 return;
684 }
685
686 + spin_lock_init(&pc_host->cfgspace_lock);
687 +
688 pc->host_controller = pc_host;
689 pc_host->pci_controller.io_resource = &pc_host->io_resource;
690 pc_host->pci_controller.mem_resource = &pc_host->mem_resource;
691 @@ -426,7 +431,7 @@ void bcma_core_pci_hostmode_init(struct
692 /* Reset RC */
693 usleep_range(3000, 5000);
694 pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST_OE);
695 - usleep_range(1000, 2000);
696 + msleep(50);
697 pcicore_write32(pc, BCMA_CORE_PCI_CTL, BCMA_CORE_PCI_CTL_RST |
698 BCMA_CORE_PCI_CTL_RST_OE);
699
700 @@ -488,6 +493,17 @@ void bcma_core_pci_hostmode_init(struct
701
702 bcma_core_pci_enable_crs(pc);
703
704 + if (bus->chipinfo.id == BCMA_CHIP_ID_BCM4706 ||
705 + bus->chipinfo.id == BCMA_CHIP_ID_BCM4716) {
706 + u16 val16;
707 + bcma_extpci_read_config(pc, 0, 0, BCMA_CORE_PCI_CFG_DEVCTRL,
708 + &val16, sizeof(val16));
709 + val16 |= (2 << 5); /* Max payload size of 512 */
710 + val16 |= (2 << 12); /* MRRS 512 */
711 + bcma_extpci_write_config(pc, 0, 0, BCMA_CORE_PCI_CFG_DEVCTRL,
712 + &val16, sizeof(val16));
713 + }
714 +
715 /* Enable PCI bridge BAR0 memory & master access */
716 tmp = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
717 bcma_extpci_write_config(pc, 0, 0, PCI_COMMAND, &tmp, sizeof(tmp));
718 @@ -576,7 +592,7 @@ int bcma_core_pci_plat_dev_init(struct p
719 pr_info("PCI: Fixing up device %s\n", pci_name(dev));
720
721 /* Fix up interrupt lines */
722 - dev->irq = bcma_core_mips_irq(pc_host->pdev->core) + 2;
723 + dev->irq = bcma_core_irq(pc_host->pdev->core);
724 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
725
726 return 0;
727 @@ -595,6 +611,6 @@ int bcma_core_pci_pcibios_map_irq(const
728
729 pc_host = container_of(dev->bus->ops, struct bcma_drv_pci_host,
730 pci_ops);
731 - return bcma_core_mips_irq(pc_host->pdev->core) + 2;
732 + return bcma_core_irq(pc_host->pdev->core);
733 }
734 EXPORT_SYMBOL(bcma_core_pci_pcibios_map_irq);
735 --- a/drivers/bcma/main.c
736 +++ b/drivers/bcma/main.c
737 @@ -81,8 +81,8 @@ struct bcma_device *bcma_find_core(struc
738 }
739 EXPORT_SYMBOL_GPL(bcma_find_core);
740
741 -static struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
742 - u8 unit)
743 +struct bcma_device *bcma_find_core_unit(struct bcma_bus *bus, u16 coreid,
744 + u8 unit)
745 {
746 struct bcma_device *core;
747
748 @@ -120,6 +120,11 @@ static int bcma_register_cores(struct bc
749 continue;
750 }
751
752 + /* Only first GMAC core on BCM4706 is connected and working */
753 + if (core->id.id == BCMA_CORE_4706_MAC_GBIT &&
754 + core->core_unit > 0)
755 + continue;
756 +
757 core->dev.release = bcma_release_core_dev;
758 core->dev.bus = &bcma_bus_type;
759 dev_set_name(&core->dev, "bcma%d:%d", bus->num, dev_id);
760 @@ -149,6 +154,14 @@ static int bcma_register_cores(struct bc
761 dev_id++;
762 }
763
764 +#ifdef CONFIG_BCMA_DRIVER_MIPS
765 + if (bus->drv_cc.pflash.present) {
766 + err = platform_device_register(&bcma_pflash_dev);
767 + if (err)
768 + bcma_err(bus, "Error registering parallel flash\n");
769 + }
770 +#endif
771 +
772 #ifdef CONFIG_BCMA_SFLASH
773 if (bus->drv_cc.sflash.present) {
774 err = platform_device_register(&bcma_sflash_dev);
775 --- a/drivers/bcma/scan.c
776 +++ b/drivers/bcma/scan.c
777 @@ -137,19 +137,19 @@ static void bcma_scan_switch_core(struct
778 addr);
779 }
780
781 -static u32 bcma_erom_get_ent(struct bcma_bus *bus, u32 **eromptr)
782 +static u32 bcma_erom_get_ent(struct bcma_bus *bus, u32 __iomem **eromptr)
783 {
784 u32 ent = readl(*eromptr);
785 (*eromptr)++;
786 return ent;
787 }
788
789 -static void bcma_erom_push_ent(u32 **eromptr)
790 +static void bcma_erom_push_ent(u32 __iomem **eromptr)
791 {
792 (*eromptr)--;
793 }
794
795 -static s32 bcma_erom_get_ci(struct bcma_bus *bus, u32 **eromptr)
796 +static s32 bcma_erom_get_ci(struct bcma_bus *bus, u32 __iomem **eromptr)
797 {
798 u32 ent = bcma_erom_get_ent(bus, eromptr);
799 if (!(ent & SCAN_ER_VALID))
800 @@ -159,14 +159,14 @@ static s32 bcma_erom_get_ci(struct bcma_
801 return ent;
802 }
803
804 -static bool bcma_erom_is_end(struct bcma_bus *bus, u32 **eromptr)
805 +static bool bcma_erom_is_end(struct bcma_bus *bus, u32 __iomem **eromptr)
806 {
807 u32 ent = bcma_erom_get_ent(bus, eromptr);
808 bcma_erom_push_ent(eromptr);
809 return (ent == (SCAN_ER_TAG_END | SCAN_ER_VALID));
810 }
811
812 -static bool bcma_erom_is_bridge(struct bcma_bus *bus, u32 **eromptr)
813 +static bool bcma_erom_is_bridge(struct bcma_bus *bus, u32 __iomem **eromptr)
814 {
815 u32 ent = bcma_erom_get_ent(bus, eromptr);
816 bcma_erom_push_ent(eromptr);
817 @@ -175,7 +175,7 @@ static bool bcma_erom_is_bridge(struct b
818 ((ent & SCAN_ADDR_TYPE) == SCAN_ADDR_TYPE_BRIDGE));
819 }
820
821 -static void bcma_erom_skip_component(struct bcma_bus *bus, u32 **eromptr)
822 +static void bcma_erom_skip_component(struct bcma_bus *bus, u32 __iomem **eromptr)
823 {
824 u32 ent;
825 while (1) {
826 @@ -189,7 +189,7 @@ static void bcma_erom_skip_component(str
827 bcma_erom_push_ent(eromptr);
828 }
829
830 -static s32 bcma_erom_get_mst_port(struct bcma_bus *bus, u32 **eromptr)
831 +static s32 bcma_erom_get_mst_port(struct bcma_bus *bus, u32 __iomem **eromptr)
832 {
833 u32 ent = bcma_erom_get_ent(bus, eromptr);
834 if (!(ent & SCAN_ER_VALID))
835 @@ -199,7 +199,7 @@ static s32 bcma_erom_get_mst_port(struct
836 return ent;
837 }
838
839 -static s32 bcma_erom_get_addr_desc(struct bcma_bus *bus, u32 **eromptr,
840 +static s32 bcma_erom_get_addr_desc(struct bcma_bus *bus, u32 __iomem **eromptr,
841 u32 type, u8 port)
842 {
843 u32 addrl, addrh, sizel, sizeh = 0;
844 --- a/drivers/bcma/sprom.c
845 +++ b/drivers/bcma/sprom.c
846 @@ -217,6 +217,7 @@ static void bcma_sprom_extract_r8(struct
847 }
848
849 SPEX(board_rev, SSB_SPROM8_BOARDREV, ~0, 0);
850 + SPEX(board_type, SSB_SPROM1_SPID, ~0, 0);
851
852 SPEX(txpid2g[0], SSB_SPROM4_TXPID2G01, SSB_SPROM4_TXPID2G0,
853 SSB_SPROM4_TXPID2G0_SHIFT);
854 --- a/include/linux/bcma/bcma.h
855 +++ b/include/linux/bcma/bcma.h
856 @@ -134,6 +134,7 @@ struct bcma_host_ops {
857 #define BCMA_CORE_I2S 0x834
858 #define BCMA_CORE_SDR_DDR1_MEM_CTL 0x835 /* SDR/DDR1 memory controller core */
859 #define BCMA_CORE_SHIM 0x837 /* SHIM component in ubus/6362 */
860 +#define BCMA_CORE_ARM_CR4 0x83e
861 #define BCMA_CORE_DEFAULT 0xFFF
862
863 #define BCMA_MAX_NR_CORES 16
864 @@ -173,6 +174,60 @@ struct bcma_host_ops {
865 #define BCMA_CHIP_ID_BCM53572 53572
866 #define BCMA_PKG_ID_BCM47188 9
867
868 +/* Board types (on PCI usually equals to the subsystem dev id) */
869 +/* BCM4313 */
870 +#define BCMA_BOARD_TYPE_BCM94313BU 0X050F
871 +#define BCMA_BOARD_TYPE_BCM94313HM 0X0510
872 +#define BCMA_BOARD_TYPE_BCM94313EPA 0X0511
873 +#define BCMA_BOARD_TYPE_BCM94313HMG 0X051C
874 +/* BCM4716 */
875 +#define BCMA_BOARD_TYPE_BCM94716NR2 0X04CD
876 +/* BCM43224 */
877 +#define BCMA_BOARD_TYPE_BCM943224X21 0X056E
878 +#define BCMA_BOARD_TYPE_BCM943224X21_FCC 0X00D1
879 +#define BCMA_BOARD_TYPE_BCM943224X21B 0X00E9
880 +#define BCMA_BOARD_TYPE_BCM943224M93 0X008B
881 +#define BCMA_BOARD_TYPE_BCM943224M93A 0X0090
882 +#define BCMA_BOARD_TYPE_BCM943224X16 0X0093
883 +#define BCMA_BOARD_TYPE_BCM94322X9 0X008D
884 +#define BCMA_BOARD_TYPE_BCM94322M35E 0X008E
885 +/* BCM43228 */
886 +#define BCMA_BOARD_TYPE_BCM943228BU8 0X0540
887 +#define BCMA_BOARD_TYPE_BCM943228BU9 0X0541
888 +#define BCMA_BOARD_TYPE_BCM943228BU 0X0542
889 +#define BCMA_BOARD_TYPE_BCM943227HM4L 0X0543
890 +#define BCMA_BOARD_TYPE_BCM943227HMB 0X0544
891 +#define BCMA_BOARD_TYPE_BCM943228HM4L 0X0545
892 +#define BCMA_BOARD_TYPE_BCM943228SD 0X0573
893 +/* BCM4331 */
894 +#define BCMA_BOARD_TYPE_BCM94331X19 0X00D6
895 +#define BCMA_BOARD_TYPE_BCM94331X28 0X00E4
896 +#define BCMA_BOARD_TYPE_BCM94331X28B 0X010E
897 +#define BCMA_BOARD_TYPE_BCM94331PCIEBT3AX 0X00E4
898 +#define BCMA_BOARD_TYPE_BCM94331X12_2G 0X00EC
899 +#define BCMA_BOARD_TYPE_BCM94331X12_5G 0X00ED
900 +#define BCMA_BOARD_TYPE_BCM94331X29B 0X00EF
901 +#define BCMA_BOARD_TYPE_BCM94331CSAX 0X00EF
902 +#define BCMA_BOARD_TYPE_BCM94331X19C 0X00F5
903 +#define BCMA_BOARD_TYPE_BCM94331X33 0X00F4
904 +#define BCMA_BOARD_TYPE_BCM94331BU 0X0523
905 +#define BCMA_BOARD_TYPE_BCM94331S9BU 0X0524
906 +#define BCMA_BOARD_TYPE_BCM94331MC 0X0525
907 +#define BCMA_BOARD_TYPE_BCM94331MCI 0X0526
908 +#define BCMA_BOARD_TYPE_BCM94331PCIEBT4 0X0527
909 +#define BCMA_BOARD_TYPE_BCM94331HM 0X0574
910 +#define BCMA_BOARD_TYPE_BCM94331PCIEDUAL 0X059B
911 +#define BCMA_BOARD_TYPE_BCM94331MCH5 0X05A9
912 +#define BCMA_BOARD_TYPE_BCM94331CS 0X05C6
913 +#define BCMA_BOARD_TYPE_BCM94331CD 0X05DA
914 +/* BCM53572 */
915 +#define BCMA_BOARD_TYPE_BCM953572BU 0X058D
916 +#define BCMA_BOARD_TYPE_BCM953572NR2 0X058E
917 +#define BCMA_BOARD_TYPE_BCM947188NR2 0X058F
918 +#define BCMA_BOARD_TYPE_BCM953572SDRNR2 0X0590
919 +/* BCM43142 */
920 +#define BCMA_BOARD_TYPE_BCM943142HM 0X05E0
921 +
922 struct bcma_device {
923 struct bcma_bus *bus;
924 struct bcma_device_id id;
925 --- a/include/linux/bcma/bcma_driver_chipcommon.h
926 +++ b/include/linux/bcma/bcma_driver_chipcommon.h
927 @@ -27,7 +27,7 @@
928 #define BCMA_CC_FLASHT_NONE 0x00000000 /* No flash */
929 #define BCMA_CC_FLASHT_STSER 0x00000100 /* ST serial flash */
930 #define BCMA_CC_FLASHT_ATSER 0x00000200 /* Atmel serial flash */
931 -#define BCMA_CC_FLASHT_NFLASH 0x00000200 /* NAND flash */
932 +#define BCMA_CC_FLASHT_NAND 0x00000300 /* NAND flash */
933 #define BCMA_CC_FLASHT_PARA 0x00000700 /* Parallel flash */
934 #define BCMA_CC_CAP_PLLT 0x00038000 /* PLL Type */
935 #define BCMA_PLLTYPE_NONE 0x00000000
936 @@ -104,6 +104,7 @@
937 #define BCMA_CC_CHIPST_4706_MIPS_BENDIAN BIT(3) /* 0: little, 1: big endian */
938 #define BCMA_CC_CHIPST_4706_PCIE1_DISABLE BIT(5) /* PCIE1 enable strap pin */
939 #define BCMA_CC_CHIPST_5357_NAND_BOOT BIT(4) /* NAND boot, valid for CC rev 38 and/or BCM5357 */
940 +#define BCMA_CC_CHIPST_4360_XTAL_40MZ 0x00000001
941 #define BCMA_CC_JCMD 0x0030 /* Rev >= 10 only */
942 #define BCMA_CC_JCMD_START 0x80000000
943 #define BCMA_CC_JCMD_BUSY 0x80000000
944 @@ -315,6 +316,9 @@
945 #define BCMA_CC_PMU_CTL 0x0600 /* PMU control */
946 #define BCMA_CC_PMU_CTL_ILP_DIV 0xFFFF0000 /* ILP div mask */
947 #define BCMA_CC_PMU_CTL_ILP_DIV_SHIFT 16
948 +#define BCMA_CC_PMU_CTL_RES 0x00006000 /* reset control mask */
949 +#define BCMA_CC_PMU_CTL_RES_SHIFT 13
950 +#define BCMA_CC_PMU_CTL_RES_RELOAD 0x2 /* reload POR values */
951 #define BCMA_CC_PMU_CTL_PLL_UPD 0x00000400
952 #define BCMA_CC_PMU_CTL_NOILPONW 0x00000200 /* No ILP on wait */
953 #define BCMA_CC_PMU_CTL_HTREQEN 0x00000100 /* HT req enable */
954 @@ -528,6 +532,7 @@ struct bcma_sflash {
955 u32 size;
956
957 struct mtd_info *mtd;
958 + void *priv;
959 };
960 #endif
961
962 @@ -606,6 +611,8 @@ void bcma_chipco_bcm4331_ext_pa_lines_ct
963
964 extern u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks);
965
966 +extern u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc);
967 +
968 void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value);
969
970 u32 bcma_chipco_irq_status(struct bcma_drv_cc *cc, u32 mask);
971 @@ -634,4 +641,6 @@ extern void bcma_chipco_regctl_maskset(s
972 u32 offset, u32 mask, u32 set);
973 extern void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid);
974
975 +extern u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc);
976 +
977 #endif /* LINUX_BCMA_DRIVER_CC_H_ */
978 --- a/include/linux/bcma/bcma_driver_mips.h
979 +++ b/include/linux/bcma/bcma_driver_mips.h
980 @@ -28,6 +28,7 @@
981 #define BCMA_MIPS_MIPS74K_GPIOEN 0x0048
982 #define BCMA_MIPS_MIPS74K_CLKCTLST 0x01E0
983
984 +#define BCMA_MIPS_OOBSELINA74 0x004
985 #define BCMA_MIPS_OOBSELOUTA30 0x100
986
987 struct bcma_device;
988 @@ -36,19 +37,23 @@ struct bcma_drv_mips {
989 struct bcma_device *core;
990 u8 setup_done:1;
991 u8 early_setup_done:1;
992 - unsigned int assigned_irqs;
993 };
994
995 #ifdef CONFIG_BCMA_DRIVER_MIPS
996 extern void bcma_core_mips_init(struct bcma_drv_mips *mcore);
997 extern void bcma_core_mips_early_init(struct bcma_drv_mips *mcore);
998 +
999 +extern unsigned int bcma_core_irq(struct bcma_device *core);
1000 #else
1001 static inline void bcma_core_mips_init(struct bcma_drv_mips *mcore) { }
1002 static inline void bcma_core_mips_early_init(struct bcma_drv_mips *mcore) { }
1003 +
1004 +static inline unsigned int bcma_core_irq(struct bcma_device *core)
1005 +{
1006 + return 0;
1007 +}
1008 #endif
1009
1010 extern u32 bcma_cpu_clock(struct bcma_drv_mips *mcore);
1011
1012 -extern unsigned int bcma_core_mips_irq(struct bcma_device *dev);
1013 -
1014 #endif /* LINUX_BCMA_DRIVER_MIPS_H_ */
1015 --- a/include/linux/bcma/bcma_driver_pci.h
1016 +++ b/include/linux/bcma/bcma_driver_pci.h
1017 @@ -179,6 +179,8 @@ struct pci_dev;
1018 #define BCMA_CORE_PCI_CFG_FUN_MASK 7 /* Function mask */
1019 #define BCMA_CORE_PCI_CFG_OFF_MASK 0xfff /* Register mask */
1020
1021 +#define BCMA_CORE_PCI_CFG_DEVCTRL 0xd8
1022 +
1023 /* PCIE Root Capability Register bits (Host mode only) */
1024 #define BCMA_CORE_PCI_RC_CRS_VISIBILITY 0x0001
1025
1026 --- a/include/linux/bcma/bcma_regs.h
1027 +++ b/include/linux/bcma/bcma_regs.h
1028 @@ -37,6 +37,7 @@
1029 #define BCMA_IOST_BIST_DONE 0x8000
1030 #define BCMA_RESET_CTL 0x0800
1031 #define BCMA_RESET_CTL_RESET 0x0001
1032 +#define BCMA_RESET_ST 0x0804
1033
1034 /* BCMA PCI config space registers. */
1035 #define BCMA_PCI_PMCSR 0x44
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