target/linux/generic/patches-3.9/021-bcma_backport.patch

   1 --- a/drivers/bcma/driver_chipcommon.c
   2 +++ b/drivers/bcma/driver_chipcommon.c
   3 @@ -25,13 +25,14 @@ static inline u32 bcma_cc_write32_masked
   4         return value;
   5  }
   6
   7 -static u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc)
   8 +u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc)
   9  {
  10         if (cc->capabilities & BCMA_CC_CAP_PMU)
  11                 return bcma_pmu_get_alp_clock(cc);
  12
  13         return 20000000;
  14  }
  15 +EXPORT_SYMBOL_GPL(bcma_chipco_get_alp_clock);
  16
  17  static u32 bcma_chipco_watchdog_get_max_timer(struct bcma_drv_cc *cc)
  18  {
  19 @@ -213,6 +214,7 @@ u32 bcma_chipco_gpio_out(struct bcma_drv
  20
  21         return res;
  22  }
  23 +EXPORT_SYMBOL_GPL(bcma_chipco_gpio_out);
  24
  25  u32 bcma_chipco_gpio_outen(struct bcma_drv_cc *cc, u32 mask, u32 value)
  26  {
  27 @@ -225,6 +227,7 @@ u32 bcma_chipco_gpio_outen(struct bcma_d
  28
  29         return res;
  30  }
  31 +EXPORT_SYMBOL_GPL(bcma_chipco_gpio_outen);
  32
  33  /*
  34   * If the bit is set to 0, chipcommon controlls this GPIO,
  35 --- a/drivers/bcma/driver_chipcommon_pmu.c
  36 +++ b/drivers/bcma/driver_chipcommon_pmu.c
  37 @@ -174,19 +174,35 @@ u32 bcma_pmu_get_alp_clock(struct bcma_d
  38         struct bcma_bus *bus = cc->core->bus;
  39
  40         switch (bus->chipinfo.id) {
  41 +       case BCMA_CHIP_ID_BCM4313:
  42 +       case BCMA_CHIP_ID_BCM43224:
  43 +       case BCMA_CHIP_ID_BCM43225:
  44 +       case BCMA_CHIP_ID_BCM43227:
  45 +       case BCMA_CHIP_ID_BCM43228:
  46 +       case BCMA_CHIP_ID_BCM4331:
  47 +       case BCMA_CHIP_ID_BCM43421:
  48 +       case BCMA_CHIP_ID_BCM43428:
  49 +       case BCMA_CHIP_ID_BCM43431:
  50         case BCMA_CHIP_ID_BCM4716:
  51 -       case BCMA_CHIP_ID_BCM4748:
  52         case BCMA_CHIP_ID_BCM47162:
  53 -       case BCMA_CHIP_ID_BCM4313:
  54 -       case BCMA_CHIP_ID_BCM5357:
  55 +       case BCMA_CHIP_ID_BCM4748:
  56         case BCMA_CHIP_ID_BCM4749:
  57 +       case BCMA_CHIP_ID_BCM5357:
  58         case BCMA_CHIP_ID_BCM53572:
  59 +       case BCMA_CHIP_ID_BCM6362:
  60                 /* always 20Mhz */
  61                 return 20000 * 1000;
  62 -       case BCMA_CHIP_ID_BCM5356:
  63         case BCMA_CHIP_ID_BCM4706:
  64 +       case BCMA_CHIP_ID_BCM5356:
  65                 /* always 25Mhz */
  66                 return 25000 * 1000;
  67 +       case BCMA_CHIP_ID_BCM43460:
  68 +       case BCMA_CHIP_ID_BCM4352:
  69 +       case BCMA_CHIP_ID_BCM4360:
  70 +               if (cc->status & BCMA_CC_CHIPST_4360_XTAL_40MZ)
  71 +                       return 40000 * 1000;
  72 +               else
  73 +                       return 20000 * 1000;
  74         default:
  75                 bcma_warn(bus, "No ALP clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
  76                           bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK);
  77 @@ -373,7 +389,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
  78                 tmp |= (bcm5357_bcm43236_ndiv[spuravoid]) << BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT;
  79                 bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);
  80
  81 -               tmp = 1 << 10;
  82 +               tmp = BCMA_CC_PMU_CTL_PLL_UPD;
  83                 break;
  84
  85         case BCMA_CHIP_ID_BCM4331:
  86 @@ -394,7 +410,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
  87                         bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
  88                                                      0x03000a08);
  89                 }
  90 -               tmp = 1 << 10;
  91 +               tmp = BCMA_CC_PMU_CTL_PLL_UPD;
  92                 break;
  93
  94         case BCMA_CHIP_ID_BCM43224:
  95 @@ -427,7 +443,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
  96                         bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
  97                                                      0x88888815);
  98                 }
  99 -               tmp = 1 << 10;
 100 +               tmp = BCMA_CC_PMU_CTL_PLL_UPD;
 101                 break;
 102
 103         case BCMA_CHIP_ID_BCM4716:
 104 @@ -461,7 +477,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
 105                                                      0x88888815);
 106                 }
 107
 108 -               tmp = 3 << 9;
 109 +               tmp = BCMA_CC_PMU_CTL_PLL_UPD | BCMA_CC_PMU_CTL_NOILPONW;
 110                 break;
 111
 112         case BCMA_CHIP_ID_BCM43227:
 113 @@ -497,7 +513,7 @@ void bcma_pmu_spuravoid_pllupdate(struct
 114                         bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
 115                                                      0x88888815);
 116                 }
 117 -               tmp = 1 << 10;
 118 +               tmp = BCMA_CC_PMU_CTL_PLL_UPD;
 119                 break;
 120         default:
 121                 bcma_err(bus, "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n",
 122 --- a/include/linux/bcma/bcma_driver_chipcommon.h
 123 +++ b/include/linux/bcma/bcma_driver_chipcommon.h
 124 @@ -104,6 +104,7 @@
 125  #define  BCMA_CC_CHIPST_4706_MIPS_BENDIAN      BIT(3) /* 0: little, 1: big endian */
 126  #define  BCMA_CC_CHIPST_4706_PCIE1_DISABLE     BIT(5) /* PCIE1 enable strap pin */
 127  #define  BCMA_CC_CHIPST_5357_NAND_BOOT         BIT(4) /* NAND boot, valid for CC rev 38 and/or BCM5357 */
 128 +#define  BCMA_CC_CHIPST_4360_XTAL_40MZ         0x00000001
 129  #define BCMA_CC_JCMD                   0x0030          /* Rev >= 10 only */
 130  #define  BCMA_CC_JCMD_START            0x80000000
 131  #define  BCMA_CC_JCMD_BUSY             0x80000000
 132 @@ -607,6 +608,8 @@ void bcma_chipco_bcm4331_ext_pa_lines_ct
 133
 134  extern u32 bcma_chipco_watchdog_timer_set(struct bcma_drv_cc *cc, u32 ticks);
 135
 136 +extern u32 bcma_chipco_get_alp_clock(struct bcma_drv_cc *cc);
 137 +
 138  void bcma_chipco_irq_mask(struct bcma_drv_cc *cc, u32 mask, u32 value);
 139
 140  u32 bcma_chipco_irq_status(struct bcma_drv_cc *cc, u32 mask);