target/linux/generic/patches-3.9/025-bcma_backport.patch

   1 --- a/include/linux/bcma/bcma.h
   2 +++ b/include/linux/bcma/bcma.h
   3 @@ -134,6 +134,7 @@ struct bcma_host_ops {
   4  #define BCMA_CORE_I2S                  0x834
   5  #define BCMA_CORE_SDR_DDR1_MEM_CTL     0x835   /* SDR/DDR1 memory controller core */
   6  #define BCMA_CORE_SHIM                 0x837   /* SHIM component in ubus/6362 */
   7 +#define BCMA_CORE_ARM_CR4              0x83e
   8  #define BCMA_CORE_DEFAULT              0xFFF
   9
  10  #define BCMA_MAX_NR_CORES              16
  11 --- a/include/linux/bcma/bcma_regs.h
  12 +++ b/include/linux/bcma/bcma_regs.h
  13 @@ -37,6 +37,7 @@
  14  #define  BCMA_IOST_BIST_DONE           0x8000
  15  #define BCMA_RESET_CTL                 0x0800
  16  #define  BCMA_RESET_CTL_RESET          0x0001
  17 +#define BCMA_RESET_ST                  0x0804
  18
  19  /* BCMA PCI config space registers. */
  20  #define BCMA_PCI_PMCSR                 0x44
  21 --- a/include/linux/bcma/bcma_driver_chipcommon.h
  22 +++ b/include/linux/bcma/bcma_driver_chipcommon.h
  23 @@ -316,6 +316,9 @@
  24  #define BCMA_CC_PMU_CTL                        0x0600 /* PMU control */
  25  #define  BCMA_CC_PMU_CTL_ILP_DIV       0xFFFF0000 /* ILP div mask */
  26  #define  BCMA_CC_PMU_CTL_ILP_DIV_SHIFT 16
  27 +#define  BCMA_CC_PMU_CTL_RES           0x00006000 /* reset control mask */
  28 +#define  BCMA_CC_PMU_CTL_RES_SHIFT     13
  29 +#define  BCMA_CC_PMU_CTL_RES_RELOAD    0x2     /* reload POR values */
  30  #define  BCMA_CC_PMU_CTL_PLL_UPD       0x00000400
  31  #define  BCMA_CC_PMU_CTL_NOILPONW      0x00000200 /* No ILP on wait */
  32  #define  BCMA_CC_PMU_CTL_HTREQEN       0x00000100 /* HT req enable */