projects / openwrt / staging / dedeckeh.git / blob
? search:


67bd504da147e7d0d4bb510263cd9cb92f5cf622
[openwrt/staging/dedeckeh.git] / target / linux / generic / pending-5.15 / 731-net-ethernet-mediatek-ppe-add-support-for-flow-accou.patch
1 From patchwork Wed Nov 2 00:58:01 2022
2 Content-Type: text/plain; charset="utf-8"
3 MIME-Version: 1.0
4 Content-Transfer-Encoding: 7bit
5 X-Patchwork-Submitter: Daniel Golle <daniel@makrotopia.org>
6 X-Patchwork-Id: 13027653
7 X-Patchwork-Delegate: kuba@kernel.org
8 Return-Path: <netdev-owner@kernel.org>
9 Date: Wed, 2 Nov 2022 00:58:01 +0000
10 From: Daniel Golle <daniel@makrotopia.org>
11 To: Felix Fietkau <nbd@nbd.name>, John Crispin <john@phrozen.org>,
12 Sean Wang <sean.wang@mediatek.com>,
13 Mark Lee <Mark-MC.Lee@mediatek.com>,
14 "David S. Miller" <davem@davemloft.net>,
15 Eric Dumazet <edumazet@google.com>,
16 Jakub Kicinski <kuba@kernel.org>,
17 Paolo Abeni <pabeni@redhat.com>,
18 Matthias Brugger <matthias.bgg@gmail.com>,
19 netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
20 linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org
21 Subject: [PATCH v4] net: ethernet: mediatek: ppe: add support for flow
22 accounting
23 Message-ID: <Y2HAmYYPd77dz+K5@makrotopia.org>
24 MIME-Version: 1.0
25 Content-Disposition: inline
26 Precedence: bulk
27 List-ID: <netdev.vger.kernel.org>
28 X-Mailing-List: netdev@vger.kernel.org
29 X-Patchwork-Delegate: kuba@kernel.org
30
31 The PPE units found in MT7622 and newer support packet and byte
32 accounting of hw-offloaded flows. Add support for reading those
33 counters as found in MediaTek's SDK[1].
34
35 [1]: https://git01.mediatek.com/plugins/gitiles/openwrt/feeds/mtk-openwrt-feeds/+/bc6a6a375c800dc2b80e1a325a2c732d1737df92
36 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
37 ---
38 v4: declare function mtk_mib_entry_read as static
39 v3: don't bother to set 'false' values in any zero-initialized struct
40 use mtk_foe_entry_ib2
41 both changes were requested by Felix Fietkau
42
43 v2: fix wrong variable name in return value check spotted by Denis Kirjanov
44
45 drivers/net/ethernet/mediatek/mtk_eth_soc.c | 7 +-
46 drivers/net/ethernet/mediatek/mtk_eth_soc.h | 1 +
47 drivers/net/ethernet/mediatek/mtk_ppe.c | 110 +++++++++++++++++-
48 drivers/net/ethernet/mediatek/mtk_ppe.h | 23 +++-
49 .../net/ethernet/mediatek/mtk_ppe_debugfs.c | 9 +-
50 .../net/ethernet/mediatek/mtk_ppe_offload.c | 7 ++
51 drivers/net/ethernet/mediatek/mtk_ppe_regs.h | 14 +++
52 7 files changed, 166 insertions(+), 5 deletions(-)
53
54 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
55 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
56 @@ -4586,8 +4586,8 @@ static int mtk_probe(struct platform_dev
57 for (i = 0; i < num_ppe; i++) {
58 u32 ppe_addr = eth->soc->reg_map->ppe_base + i * 0x400;
59
60 - eth->ppe[i] = mtk_ppe_init(eth, eth->base + ppe_addr,
61 - eth->soc->offload_version, i);
62 + eth->ppe[i] = mtk_ppe_init(eth, eth->base + ppe_addr, i);
63 +
64 if (!eth->ppe[i]) {
65 err = -ENOMEM;
66 goto err_free_dev;
67 @@ -4712,6 +4712,7 @@ static const struct mtk_soc_data mt7622_
68 .required_pctl = false,
69 .offload_version = 2,
70 .hash_offset = 2,
71 + .has_accounting = true,
72 .foe_entry_size = sizeof(struct mtk_foe_entry) - 16,
73 .txrx = {
74 .txd_size = sizeof(struct mtk_tx_dma),
75 @@ -4749,6 +4750,7 @@ static const struct mtk_soc_data mt7629_
76 .hw_features = MTK_HW_FEATURES,
77 .required_clks = MT7629_CLKS_BITMAP,
78 .required_pctl = false,
79 + .has_accounting = true,
80 .txrx = {
81 .txd_size = sizeof(struct mtk_tx_dma),
82 .rxd_size = sizeof(struct mtk_rx_dma),
83 @@ -4769,6 +4771,7 @@ static const struct mtk_soc_data mt7986_
84 .offload_version = 2,
85 .hash_offset = 4,
86 .foe_entry_size = sizeof(struct mtk_foe_entry),
87 + .has_accounting = true,
88 .txrx = {
89 .txd_size = sizeof(struct mtk_tx_dma_v2),
90 .rxd_size = sizeof(struct mtk_rx_dma_v2),
91 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
92 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
93 @@ -1037,6 +1037,8 @@ struct mtk_reg_map {
94 * the extra setup for those pins used by GMAC.
95 * @hash_offset Flow table hash offset.
96 * @foe_entry_size Foe table entry size.
97 + * @has_accounting Bool indicating support for accounting of
98 + * offloaded flows.
99 * @txd_size Tx DMA descriptor size.
100 * @rxd_size Rx DMA descriptor size.
101 * @rx_irq_done_mask Rx irq done register mask.
102 @@ -1054,6 +1056,7 @@ struct mtk_soc_data {
103 u8 hash_offset;
104 u16 foe_entry_size;
105 netdev_features_t hw_features;
106 + bool has_accounting;
107 struct {
108 u32 txd_size;
109 u32 rxd_size;
110 --- a/drivers/net/ethernet/mediatek/mtk_ppe.c
111 +++ b/drivers/net/ethernet/mediatek/mtk_ppe.c
112 @@ -74,6 +74,48 @@ static int mtk_ppe_wait_busy(struct mtk_
113 return ret;
114 }
115
116 +static int mtk_ppe_mib_wait_busy(struct mtk_ppe *ppe)
117 +{
118 + int ret;
119 + u32 val;
120 +
121 + ret = readl_poll_timeout(ppe->base + MTK_PPE_MIB_SER_CR, val,
122 + !(val & MTK_PPE_MIB_SER_CR_ST),
123 + 20, MTK_PPE_WAIT_TIMEOUT_US);
124 +
125 + if (ret)
126 + dev_err(ppe->dev, "MIB table busy");
127 +
128 + return ret;
129 +}
130 +
131 +static int mtk_mib_entry_read(struct mtk_ppe *ppe, u16 index, u64 *bytes, u64 *packets)
132 +{
133 + u32 byte_cnt_low, byte_cnt_high, pkt_cnt_low, pkt_cnt_high;
134 + u32 val, cnt_r0, cnt_r1, cnt_r2;
135 + int ret;
136 +
137 + val = FIELD_PREP(MTK_PPE_MIB_SER_CR_ADDR, index) | MTK_PPE_MIB_SER_CR_ST;
138 + ppe_w32(ppe, MTK_PPE_MIB_SER_CR, val);
139 +
140 + ret = mtk_ppe_mib_wait_busy(ppe);
141 + if (ret)
142 + return ret;
143 +
144 + cnt_r0 = readl(ppe->base + MTK_PPE_MIB_SER_R0);
145 + cnt_r1 = readl(ppe->base + MTK_PPE_MIB_SER_R1);
146 + cnt_r2 = readl(ppe->base + MTK_PPE_MIB_SER_R2);
147 +
148 + byte_cnt_low = FIELD_GET(MTK_PPE_MIB_SER_R0_BYTE_CNT_LOW, cnt_r0);
149 + byte_cnt_high = FIELD_GET(MTK_PPE_MIB_SER_R1_BYTE_CNT_HIGH, cnt_r1);
150 + pkt_cnt_low = FIELD_GET(MTK_PPE_MIB_SER_R1_PKT_CNT_LOW, cnt_r1);
151 + pkt_cnt_high = FIELD_GET(MTK_PPE_MIB_SER_R2_PKT_CNT_HIGH, cnt_r2);
152 + *bytes = ((u64)byte_cnt_high << 32) | byte_cnt_low;
153 + *packets = (pkt_cnt_high << 16) | pkt_cnt_low;
154 +
155 + return 0;
156 +}
157 +
158 static void mtk_ppe_cache_clear(struct mtk_ppe *ppe)
159 {
160 ppe_set(ppe, MTK_PPE_CACHE_CTL, MTK_PPE_CACHE_CTL_CLEAR);
161 @@ -464,6 +506,13 @@ __mtk_foe_entry_clear(struct mtk_ppe *pp
162 hwe->ib1 &= ~MTK_FOE_IB1_STATE;
163 hwe->ib1 |= FIELD_PREP(MTK_FOE_IB1_STATE, MTK_FOE_STATE_INVALID);
164 dma_wmb();
165 + if (ppe->accounting) {
166 + struct mtk_foe_accounting *acct;
167 +
168 + acct = ppe->acct_table + entry->hash * sizeof(*acct);
169 + acct->packets = 0;
170 + acct->bytes = 0;
171 + }
172 }
173 entry->hash = 0xffff;
174
175 @@ -571,6 +620,9 @@ __mtk_foe_entry_commit(struct mtk_ppe *p
176 wmb();
177 hwe->ib1 = entry->ib1;
178
179 + if (ppe->accounting)
180 + *mtk_foe_entry_ib2(eth, hwe) |= MTK_FOE_IB2_MIB_CNT;
181 +
182 dma_wmb();
183
184 mtk_ppe_cache_clear(ppe);
185 @@ -762,11 +814,39 @@ int mtk_ppe_prepare_reset(struct mtk_ppe
186 return mtk_ppe_wait_busy(ppe);
187 }
188
189 -struct mtk_ppe *mtk_ppe_init(struct mtk_eth *eth, void __iomem *base,
190 - int version, int index)
191 +struct mtk_foe_accounting *mtk_foe_entry_get_mib(struct mtk_ppe *ppe, u32 index,
192 + struct mtk_foe_accounting *diff)
193 +{
194 + struct mtk_foe_accounting *acct;
195 + int size = sizeof(struct mtk_foe_accounting);
196 + u64 bytes, packets;
197 +
198 + if (!ppe->accounting)
199 + return NULL;
200 +
201 + if (mtk_mib_entry_read(ppe, index, &bytes, &packets))
202 + return NULL;
203 +
204 + acct = ppe->acct_table + index * size;
205 +
206 + acct->bytes += bytes;
207 + acct->packets += packets;
208 +
209 + if (diff) {
210 + diff->bytes = bytes;
211 + diff->packets = packets;
212 + }
213 +
214 + return acct;
215 +}
216 +
217 +struct mtk_ppe *mtk_ppe_init(struct mtk_eth *eth, void __iomem *base, int index)
218 {
219 + bool accounting = eth->soc->has_accounting;
220 const struct mtk_soc_data *soc = eth->soc;
221 + struct mtk_foe_accounting *acct;
222 struct device *dev = eth->dev;
223 + struct mtk_mib_entry *mib;
224 struct mtk_ppe *ppe;
225 u32 foe_flow_size;
226 void *foe;
227 @@ -783,7 +863,8 @@ struct mtk_ppe *mtk_ppe_init(struct mtk_
228 ppe->base = base;
229 ppe->eth = eth;
230 ppe->dev = dev;
231 - ppe->version = version;
232 + ppe->version = eth->soc->offload_version;
233 + ppe->accounting = accounting;
234
235 foe = dmam_alloc_coherent(ppe->dev,
236 MTK_PPE_ENTRIES * soc->foe_entry_size,
237 @@ -799,6 +880,23 @@ struct mtk_ppe *mtk_ppe_init(struct mtk_
238 if (!ppe->foe_flow)
239 return NULL;
240
241 + if (accounting) {
242 + mib = dmam_alloc_coherent(ppe->dev, MTK_PPE_ENTRIES * sizeof(*mib),
243 + &ppe->mib_phys, GFP_KERNEL);
244 + if (!mib)
245 + return NULL;
246 +
247 + ppe->mib_table = mib;
248 +
249 + acct = devm_kzalloc(dev, MTK_PPE_ENTRIES * sizeof(*acct),
250 + GFP_KERNEL);
251 +
252 + if (!acct)
253 + return NULL;
254 +
255 + ppe->acct_table = acct;
256 + }
257 +
258 mtk_ppe_debugfs_init(ppe, index);
259
260 return ppe;
261 @@ -913,6 +1011,16 @@ void mtk_ppe_start(struct mtk_ppe *ppe)
262 ppe_w32(ppe, MTK_PPE_DEFAULT_CPU_PORT1, 0xcb777);
263 ppe_w32(ppe, MTK_PPE_SBW_CTRL, 0x7f);
264 }
265 +
266 + if (ppe->accounting && ppe->mib_phys) {
267 + ppe_w32(ppe, MTK_PPE_MIB_TB_BASE, ppe->mib_phys);
268 + ppe_m32(ppe, MTK_PPE_MIB_CFG, MTK_PPE_MIB_CFG_EN,
269 + MTK_PPE_MIB_CFG_EN);
270 + ppe_m32(ppe, MTK_PPE_MIB_CFG, MTK_PPE_MIB_CFG_RD_CLR,
271 + MTK_PPE_MIB_CFG_RD_CLR);
272 + ppe_m32(ppe, MTK_PPE_MIB_CACHE_CTL, MTK_PPE_MIB_CACHE_CTL_EN,
273 + MTK_PPE_MIB_CFG_RD_CLR);
274 + }
275 }
276
277 int mtk_ppe_stop(struct mtk_ppe *ppe)
278 --- a/drivers/net/ethernet/mediatek/mtk_ppe.h
279 +++ b/drivers/net/ethernet/mediatek/mtk_ppe.h
280 @@ -57,6 +57,7 @@ enum {
281 #define MTK_FOE_IB2_MULTICAST BIT(8)
282
283 #define MTK_FOE_IB2_WDMA_QID2 GENMASK(13, 12)
284 +#define MTK_FOE_IB2_MIB_CNT BIT(15)
285 #define MTK_FOE_IB2_WDMA_DEVIDX BIT(16)
286 #define MTK_FOE_IB2_WDMA_WINFO BIT(17)
287
288 @@ -285,16 +286,34 @@ struct mtk_flow_entry {
289 unsigned long cookie;
290 };
291
292 +struct mtk_mib_entry {
293 + u32 byt_cnt_l;
294 + u16 byt_cnt_h;
295 + u32 pkt_cnt_l;
296 + u8 pkt_cnt_h;
297 + u8 _rsv0;
298 + u32 _rsv1;
299 +} __packed;
300 +
301 +struct mtk_foe_accounting {
302 + u64 bytes;
303 + u64 packets;
304 +};
305 +
306 struct mtk_ppe {
307 struct mtk_eth *eth;
308 struct device *dev;
309 void __iomem *base;
310 int version;
311 char dirname[5];
312 + bool accounting;
313
314 void *foe_table;
315 dma_addr_t foe_phys;
316
317 + struct mtk_mib_entry *mib_table;
318 + dma_addr_t mib_phys;
319 +
320 u16 foe_check_time[MTK_PPE_ENTRIES];
321 struct hlist_head *foe_flow;
322
323 @@ -303,8 +322,7 @@ struct mtk_ppe {
324 void *acct_table;
325 };
326
327 -struct mtk_ppe *mtk_ppe_init(struct mtk_eth *eth, void __iomem *base,
328 - int version, int index);
329 +struct mtk_ppe *mtk_ppe_init(struct mtk_eth *eth, void __iomem *base, int index);
330 void mtk_ppe_start(struct mtk_ppe *ppe);
331 int mtk_ppe_stop(struct mtk_ppe *ppe);
332 int mtk_ppe_prepare_reset(struct mtk_ppe *ppe);
333 @@ -358,5 +376,7 @@ int mtk_foe_entry_commit(struct mtk_ppe
334 void mtk_foe_entry_clear(struct mtk_ppe *ppe, struct mtk_flow_entry *entry);
335 int mtk_foe_entry_idle_time(struct mtk_ppe *ppe, struct mtk_flow_entry *entry);
336 int mtk_ppe_debugfs_init(struct mtk_ppe *ppe, int index);
337 +struct mtk_foe_accounting *mtk_foe_entry_get_mib(struct mtk_ppe *ppe, u32 index,
338 + struct mtk_foe_accounting *diff);
339
340 #endif
341 --- a/drivers/net/ethernet/mediatek/mtk_ppe_debugfs.c
342 +++ b/drivers/net/ethernet/mediatek/mtk_ppe_debugfs.c
343 @@ -82,6 +82,7 @@ mtk_ppe_debugfs_foe_show(struct seq_file
344 struct mtk_foe_entry *entry = mtk_foe_get_entry(ppe, i);
345 struct mtk_foe_mac_info *l2;
346 struct mtk_flow_addr_info ai = {};
347 + struct mtk_foe_accounting *acct;
348 unsigned char h_source[ETH_ALEN];
349 unsigned char h_dest[ETH_ALEN];
350 int type, state;
351 @@ -95,6 +96,8 @@ mtk_ppe_debugfs_foe_show(struct seq_file
352 if (bind && state != MTK_FOE_STATE_BIND)
353 continue;
354
355 + acct = mtk_foe_entry_get_mib(ppe, i, NULL);
356 +
357 type = FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, entry->ib1);
358 seq_printf(m, "%05x %s %7s", i,
359 mtk_foe_entry_state_str(state),
360 @@ -153,9 +156,11 @@ mtk_ppe_debugfs_foe_show(struct seq_file
361 *((__be16 *)&h_dest[4]) = htons(l2->dest_mac_lo);
362
363 seq_printf(m, " eth=%pM->%pM etype=%04x"
364 - " vlan=%d,%d ib1=%08x ib2=%08x\n",
365 + " vlan=%d,%d ib1=%08x ib2=%08x"
366 + " packets=%llu bytes=%llu\n",
367 h_source, h_dest, ntohs(l2->etype),
368 - l2->vlan1, l2->vlan2, entry->ib1, ib2);
369 + l2->vlan1, l2->vlan2, entry->ib1, ib2,
370 + acct ? acct->packets : 0, acct ? acct->bytes : 0);
371 }
372
373 return 0;
374 --- a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c
375 +++ b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c
376 @@ -497,6 +497,7 @@ static int
377 mtk_flow_offload_stats(struct mtk_eth *eth, struct flow_cls_offload *f)
378 {
379 struct mtk_flow_entry *entry;
380 + struct mtk_foe_accounting diff;
381 u32 idle;
382
383 entry = rhashtable_lookup(&eth->flow_table, &f->cookie,
384 @@ -507,6 +508,13 @@ mtk_flow_offload_stats(struct mtk_eth *e
385 idle = mtk_foe_entry_idle_time(eth->ppe[entry->ppe_index], entry);
386 f->stats.lastused = jiffies - idle * HZ;
387
388 + if (entry->hash != 0xFFFF &&
389 + mtk_foe_entry_get_mib(eth->ppe[entry->ppe_index], entry->hash,
390 + &diff)) {
391 + f->stats.pkts += diff.packets;
392 + f->stats.bytes += diff.bytes;
393 + }
394 +
395 return 0;
396 }
397
398 --- a/drivers/net/ethernet/mediatek/mtk_ppe_regs.h
399 +++ b/drivers/net/ethernet/mediatek/mtk_ppe_regs.h
400 @@ -149,6 +149,20 @@ enum {
401
402 #define MTK_PPE_MIB_TB_BASE 0x338
403
404 +#define MTK_PPE_MIB_SER_CR 0x33C
405 +#define MTK_PPE_MIB_SER_CR_ST BIT(16)
406 +#define MTK_PPE_MIB_SER_CR_ADDR GENMASK(13, 0)
407 +
408 +#define MTK_PPE_MIB_SER_R0 0x340
409 +#define MTK_PPE_MIB_SER_R0_BYTE_CNT_LOW GENMASK(31, 0)
410 +
411 +#define MTK_PPE_MIB_SER_R1 0x344
412 +#define MTK_PPE_MIB_SER_R1_PKT_CNT_LOW GENMASK(31, 16)
413 +#define MTK_PPE_MIB_SER_R1_BYTE_CNT_HIGH GENMASK(15, 0)
414 +
415 +#define MTK_PPE_MIB_SER_R2 0x348
416 +#define MTK_PPE_MIB_SER_R2_PKT_CNT_HIGH GENMASK(23, 0)
417 +
418 #define MTK_PPE_MIB_CACHE_CTL 0x350
419 #define MTK_PPE_MIB_CACHE_CTL_EN BIT(0)
420 #define MTK_PPE_MIB_CACHE_CTL_FLUSH BIT(2)
Staging tree of dedeckeh