target/linux/generic-2.6/files/drivers/net/phy/mvswitch.h

   1 /*
   2  * Marvell 88E6060 switch driver
   3  * Copyright (c) 2008 Felix Fietkau <nbd@openwrt.org>
   4  *
   5  * This program is free software; you can redistribute  it and/or modify it
   6  * under  the terms of the GNU General Public License v2 as published by the
   7  * Free Software Foundation
   8  */
   9 #ifndef __MVSWITCH_H
  10 #define __MVSWITCH_H
  11
  12 #define MV_PORTS        5
  13 #define MV_WANPORT      4
  14 #define MV_CPUPORT      5
  15
  16 #define MV_BASE         0x10
  17
  18 #define MV_PHYPORT_BASE         (MV_BASE + 0x0)
  19 #define MV_PHYPORT(_n)          (MV_PHYPORT_BASE + (_n))
  20 #define MV_SWITCHPORT_BASE      (MV_BASE + 0x8)
  21 #define MV_SWITCHPORT(_n)       (MV_SWITCHPORT_BASE + (_n))
  22 #define MV_SWITCHREGS           (MV_BASE + 0xf)
  23
  24 enum {
  25         MV_PHY_CONTROL      = 0x00,
  26         MV_PHY_STATUS       = 0x01,
  27         MV_PHY_IDENT0       = 0x02,
  28         MV_PHY_IDENT1       = 0x03,
  29         MV_PHY_ANEG         = 0x04,
  30         MV_PHY_LINK_ABILITY = 0x05,
  31         MV_PHY_ANEG_EXPAND  = 0x06,
  32         MV_PHY_XMIT_NEXTP   = 0x07,
  33         MV_PHY_LINK_NEXTP   = 0x08,
  34         MV_PHY_CONTROL1     = 0x10,
  35         MV_PHY_STATUS1      = 0x11,
  36         MV_PHY_INTR_EN      = 0x12,
  37         MV_PHY_INTR_STATUS  = 0x13,
  38         MV_PHY_INTR_PORT    = 0x14,
  39         MV_PHY_RECV_COUNTER = 0x15,
  40         MV_PHY_LED_PARALLEL = 0x16,
  41         MV_PHY_LED_STREAM   = 0x17,
  42         MV_PHY_LED_CTRL     = 0x18,
  43         MV_PHY_LED_OVERRIDE = 0x19,
  44         MV_PHY_VCT_CTRL     = 0x1a,
  45         MV_PHY_VCT_STATUS   = 0x1b,
  46         MV_PHY_CONTROL2     = 0x1e
  47 };
  48 #define MV_PHYREG(_type, _port) MV_PHYPORT(_port), MV_PHY_##_type
  49
  50 enum {
  51         MV_PORT_STATUS      = 0x00,
  52         MV_PORT_IDENT       = 0x03,
  53         MV_PORT_CONTROL     = 0x04,
  54         MV_PORT_VLANMAP     = 0x06,
  55         MV_PORT_ASSOC       = 0x0b,
  56         MV_PORT_RXCOUNT     = 0x10,
  57         MV_PORT_TXCOUNT     = 0x11,
  58 };
  59 #define MV_PORTREG(_type, _port) MV_SWITCHPORT(_port), MV_PORT_##_type
  60
  61 enum {
  62         MV_PORTCTRL_BLOCK   =  (1 << 0),
  63         MV_PORTCTRL_LEARN   =  (2 << 0),
  64         MV_PORTCTRL_ENABLED =  (3 << 0),
  65         MV_PORTCTRL_VLANTUN =  (1 << 7),        /* Enforce VLANs on packets */
  66         MV_PORTCTRL_RXTR    =  (1 << 8),        /* Enable Marvell packet trailer for ingress */
  67         MV_PORTCTRL_TXTR    = (1 << 14),        /* Enable Marvell packet trailer for egress */
  68         MV_PORTCTRL_FORCEFL = (1 << 15),        /* force flow control */
  69 };
  70
  71 #define MV_PORTVLAN_ID(_n) (((_n) & 0xf) << 12)
  72 #define MV_PORTVLAN_PORTS(_n) ((_n) & 0x3f)
  73
  74 #define MV_PORTASSOC_PORTS(_n) ((_n) & 0x1f)
  75 #define MV_PORTASSOC_MONITOR    (1 << 15)
  76
  77 enum {
  78         MV_SWITCH_MAC0      = 0x01,
  79         MV_SWITCH_MAC1      = 0x02,
  80         MV_SWITCH_MAC2      = 0x03,
  81         MV_SWITCH_CTRL      = 0x04,
  82         MV_SWITCH_ATU_CTRL  = 0x0a,
  83         MV_SWITCH_ATU_OP    = 0x0b,
  84         MV_SWITCH_ATU_DATA  = 0x0c,
  85         MV_SWITCH_ATU_MAC0  = 0x0d,
  86         MV_SWITCH_ATU_MAC1  = 0x0e,
  87         MV_SWITCH_ATU_MAC2  = 0x0f,
  88 };
  89 #define MV_SWITCHREG(_type) MV_SWITCHREGS, MV_SWITCH_##_type
  90
  91 enum {
  92 #define MV_ATUCTL_AGETIME(_n)   ((((_n) / 16) & 0xff) << 4)
  93         MV_ATUCTL_ATU_256   = (0 << 12),
  94         MV_ATUCTL_ATU_512   = (1 << 12),
  95         MV_ATUCTL_ATU_1K        = (2 << 12),
  96         MV_ATUCTL_ATUMASK   = (3 << 12),
  97         MV_ATUCTL_NO_LEARN  = (1 << 14),
  98         MV_ATUCTL_RESET     = (1 << 15),
  99 }
 100
 101 #define MV_IDENT_MASK           0xfff0
 102 #define MV_IDENT_VALUE          0x0600
 103
 104 #endif